Commit 7eda868

committed

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into merge-upstream

Signed-off-by: Alessandro Comodi <[email protected]> Conflicts: libs/libarchfpga/src/cad_types.h vpr/src/base/read_options.cpp

2 parents c1f0b34 + c02498a commit 7eda868Copy full SHA for 7eda868

99 files changed

+28068

-1302

lines changed

ODIN_II
doc/src
- tutorials/arch/timing_modeling
  - index.rst
- vpr
  - command_line_usage.rst
libs/libarchfpga/src
- cad_types.h
vpr/src
- base
- pack
- place
  - place.cpp
vtr_flow
- arch
  - timing
    - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml
  - titan
    - stratixiv_arch.timing.xml
- benchmarks
  - arithmetic/multipliers
  - titan_other_blif
    - ucsb_152_tap_fir_stratixiv_arch_timing.blif
- scripts
  - download_titan.py
- tasks/regression_tests
  - vtr_reg_nightly
    - titan_other/config
      - config.txt
      - golden_results.txt
    - titan_small/config
      - config.txt
      - golden_results.txt
  - vtr_reg_strong
    - strong_cin_tie_off/config
      - config.txt
      - golden_results.txt
    - strong_soft_multipliers/config
      - config.txt
      - golden_results.txt
    - strong_titan/config
      - config.txt
      - golden_results.txt
    - task_list.txt
  - vtr_reg_weekly/vtr_reg_titan/config
    - config.txt
    - golden_results.txt

99 files changed

+28068

-1302

lines changed

`‎ODIN_II/.gitignore`

-Original file line number
+Diff line change
 temp
 regression_test/latest
 *_preproc.v
 -default_out.blif
 +default_out.blif
 +*.dot

Comments

(0)