Merge pull request verilog-to-routing#627 from verilog-to-routing/odin_merge_constant_fold

fix edge sensitivity

Author: jeanlego

ODIN_II/SRC/include/odin_types.h

@@ -209,6 +209,13 @@ typedef enum
 	edge_type_e_END
 } edge_type_e;
 
+typedef enum
+{
+	COMBINATIONAL,
+	SEQUENTIAL,
+	circuit_type_e_END
+} circuit_type_e;
+
 typedef enum
 {
 	NO_OP,
@@ -532,6 +539,8 @@ struct npin_t_t
 	int pin_node_idx; // pin on the node where we're located
 	char *mapping;    // name of mapped port from hard block
 
+	edge_type_e sensitivity;
+
 	////////////////////
 	// For simulation
 	std::shared_ptr<AtomicBuffer> values;

ODIN_II/SRC/netlist_create_from_ast.cpp

@@ -57,9 +57,6 @@ OTHER DEALINGS IN THE SOFTWARE.
 #define INSTANTIATE_DRIVERS 1
 #define ALIAS_INPUTS 2
 
-#define COMBINATIONAL 1
-#define SEQUENTIAL 2
-
 STRING_CACHE *output_nets_sc;
 STRING_CACHE *input_nets_sc;
 
@@ -85,8 +82,8 @@ netlist_t *verilog_netlist;
 
 int netlist_create_line_number = -2;
 
-int type_of_circuit;
-
+circuit_type_e type_of_circuit;
+edge_type_e circuit_edge;
 
 /* PROTOTYPES */
 void create_param_table_for_module(ast_node_t* parent_parameter_list, ast_node_t *module_items, char *module_name, char *parent_module);
@@ -283,6 +280,13 @@ void create_param_table_for_module(ast_node_t* parent_parameter_list, ast_node_t
 					{
 						ast_node_t *var_declare = parent_parameter_list->children[i];
 						sc_spot = sc_lookup_string(local_param_table_sc, temp_parameter_list[parameter_count]);
+						if(sc_spot == -1)
+						{
+							error_message(NETLIST_ERROR, parent_parameter_list->line_number, parent_parameter_list->file_number,
+									"Can't find parameter name %s in module %s\n",
+									var_declare->children[0]->types.identifier,
+									module_name);
+						}
 						local_param_table_sc->data[sc_spot] = (void *)var_declare->children[5];
 					}
 
@@ -330,12 +334,23 @@ void create_param_table_for_module(ast_node_t* parent_parameter_list, ast_node_t
 	}
 
 	/* now that parameters are all updated, resolve them */
-	for (i = 0; i < parameter_num; i++) {
+	for (i = 0; i < parameter_num; i++) 
+	{
 		sc_spot = sc_lookup_string(local_param_table_sc, temp_parameter_list[i]);
+		if(sc_spot == -1)
+		{
+			error_message(NETLIST_ERROR, parent_parameter_list->line_number, parent_parameter_list->file_number,
+					"Can't find parameter name %s in module %s\n",
+					temp_parameter_list[i],
+					module_name);
+		}
 		ast_node_t *node = (ast_node_t *)local_param_table_sc->data[sc_spot];
 		oassert(node);
 		node = resolve_node(NULL, module_name, node);
-		if (node->type != NUMBERS) node = resolve_node(NULL, parent_module, node); // may contain parameters from parent
+		if (node->type != NUMBERS) 
+		{
+			node = resolve_node(NULL, parent_module, node); // may contain parameters from parent
+		}
 		oassert(node->type == NUMBERS);
 		local_param_table_sc->data[sc_spot] = (void *)node;
 	}
@@ -815,7 +830,8 @@ signal_list_t *netlist_expand_ast_of_module(ast_node_t* node, char *instance_nam
                 break;
             case VAR_DECLARE:
                 if(node->types.variable.is_parameter == 0 && node->children[5]){
-                    return_sig_list = assignment_alias(node, instance_name_prefix);
+                    /*we don't create signal list on declaration.*/
+					return_sig_list = init_signal_list();
                 }
                 skip_children = TRUE;
                 break;
@@ -885,22 +901,11 @@ signal_list_t *netlist_expand_ast_of_module(ast_node_t* node, char *instance_nam
 			case ASSIGN:
 				/* combinational path */
 				type_of_circuit = COMBINATIONAL;
+				circuit_edge = UNDEFINED_SENSITIVITY;
 				break;
 			case BLOCKING_STATEMENT:
-			{
-				/*if (type_of_circuit == SEQUENTIAL)
-					error_message(NETLIST_ERROR, node->line_number, node->file_number,
-							"ODIN doesn't handle blocking statements in Sequential blocks\n");*/
-
-				return_sig_list = assignment_alias(node, instance_name_prefix);
-				skip_children = TRUE;
-				break;
-			}
 			case NON_BLOCKING_STATEMENT:
 			{
-				/*if (type_of_circuit != SEQUENTIAL)
-					error_message(NETLIST_ERROR, node->line_number, node->file_number,
-							"ODIN doesn't handle non blocking statements in combinational blocks\n");*/
 
 				return_sig_list = assignment_alias(node, instance_name_prefix);
 				skip_children = TRUE;
@@ -1013,13 +1018,9 @@ signal_list_t *netlist_expand_ast_of_module(ast_node_t* node, char *instance_nam
 			break;
 			case ALWAYS:
 				/* attach the drivers to the driver nets */
-				switch(type_of_circuit)
+				switch(circuit_edge)
 				{
-					case FALLING_EDGE_SENSITIVITY:
-					{
-						terminate_registered_assignment(node, children_signal_list[1], local_clock_list, instance_name_prefix);
-						break;
-					}
+					case FALLING_EDGE_SENSITIVITY: //fallthrough
 					case RISING_EDGE_SENSITIVITY:
 					{
 						terminate_registered_assignment(node, children_signal_list[1], local_clock_list, instance_name_prefix);
@@ -3237,18 +3238,8 @@ signal_list_t *assignment_alias(ast_node_t* assignment, char *instance_name_pref
 {
 	ast_node_t *left;
 	ast_node_t *right;
-	if(assignment->type == VAR_DECLARE){
-		left  = assignment->children[0];
-		right = assignment->children[5];
-
-		/*we don't create signal list on declaration.*/
-		return init_signal_list();
-	}
-	else
-	{
-		left  = assignment->children[0];
-		right = assignment->children[1];
-	}
+	left  = assignment->children[0];
+	right = assignment->children[1];
 
 	implicit_memory *left_memory  = lookup_implicit_memory_reference_ast(instance_name_prefix, left);
 	implicit_memory *right_memory = lookup_implicit_memory_reference_ast(instance_name_prefix, right);
@@ -3361,7 +3352,7 @@ signal_list_t *assignment_alias(ast_node_t* assignment, char *instance_name_pref
 							"Invalid addressing mode for implicit memory %s.\n", left_memory->name);
 
 		// A memory can only be written from a clocked rising edge block.
-		if (type_of_circuit != RISING_EDGE_SENSITIVITY)
+		if (type_of_circuit != SEQUENTIAL)
 		{
 			out_list = NULL;
 			error_message(NETLIST_ERROR, assignment->line_number, assignment->file_number, "%s",
@@ -3714,6 +3705,7 @@ void terminate_registered_assignment(ast_node_t *always_node, signal_list_t* ass
 			ff_node->related_ast_node = always_node;
 
 			ff_node->type = FF_NODE;
+			ff_node->edge_type = potential_clocks->pins[local_clock_idx]->sensitivity;
 			/* create the unique name for this gate */
 			//ff_node->name = node_name(ff_node, instance_name_prefix);
 			/* Name the flipflop based on the name of its output pin */
@@ -4299,13 +4291,13 @@ signal_list_t *create_operation_node(ast_node_t *op, signal_list_t **input_lists
 signal_list_t *evaluate_sensitivity_list(ast_node_t *delay_control, char *instance_name_prefix)
 {
 	long i;
-	edge_type_e edge_type = UNDEFINED_SENSITIVITY;
+	circuit_edge = UNDEFINED_SENSITIVITY;
 	signal_list_t *return_sig_list = init_signal_list();
 
 	if (delay_control == NULL)
 	{
 		/* Assume always @* */
-		edge_type = ASYNCHRONOUS_SENSITIVITY;
+		circuit_edge = ASYNCHRONOUS_SENSITIVITY;
 	}
 	else
 	{
@@ -4328,26 +4320,26 @@ signal_list_t *evaluate_sensitivity_list(ast_node_t *delay_control, char *instan
 					break;
 			}
 
-			if(edge_type == UNDEFINED_SENSITIVITY)
-				edge_type = child_sensitivity;
+			if(circuit_edge == UNDEFINED_SENSITIVITY)
+				circuit_edge = child_sensitivity;
 
-			if(	(edge_type != child_sensitivity)
-			&& ((edge_type == ASYNCHRONOUS_SENSITIVITY) || (child_sensitivity == ASYNCHRONOUS_SENSITIVITY)) )
-				error_message(NETLIST_ERROR, delay_control->line_number, delay_control->file_number, "%s",
-					"Sensitivity list switches between edge sensitive to asynchronous.  You can't define something like always @(posedge clock or a).\n");
-			
-			switch(edge_type)
+			if(circuit_edge != child_sensitivity)
+			{
+				if(circuit_edge == ASYNCHRONOUS_SENSITIVITY || child_sensitivity == ASYNCHRONOUS_SENSITIVITY)
+				{
+					error_message(NETLIST_ERROR, delay_control->line_number, delay_control->file_number, "%s",
+						"Sensitivity list switches between edge sensitive to asynchronous.  You can't define something like always @(posedge clock or a).\n");
+				}
+			}
+
+			switch(child_sensitivity)
 			{
-				/**
-				 * TODO: finish support for falling edge, this is left here for future work
-				 */
 				case FALLING_EDGE_SENSITIVITY: //falltrhough
-					edge_type = RISING_EDGE_SENSITIVITY; //fallthrough
 				case RISING_EDGE_SENSITIVITY:
 				{
 					signal_list_t *temp_list = create_pins(delay_control->children[i]->children[0], NULL, instance_name_prefix);
 					oassert(temp_list->count == 1);
-
+					temp_list->pins[0]->sensitivity = child_sensitivity;
 					add_pin_to_signal_list(return_sig_list, temp_list->pins[0]);
 					free_signal_list(temp_list);
 					break;
@@ -4358,16 +4350,20 @@ signal_list_t *evaluate_sensitivity_list(ast_node_t *delay_control, char *instan
 	}
 
 	/* update the analysis type of this block of statements */
-	if(edge_type == UNDEFINED_SENSITIVITY)
+	if(circuit_edge == UNDEFINED_SENSITIVITY)
+	{
+		// TODO: empty always block will probably appear here
 		error_message(NETLIST_ERROR, delay_control->line_number, delay_control->file_number, "%s", "Sensitivity list error...looks empty?\n");
-
-	else if(edge_type == ASYNCHRONOUS_SENSITIVITY)
+	}
+	else if(circuit_edge == ASYNCHRONOUS_SENSITIVITY)
 	{
+		/* @(*) or @* is here */
 		free_signal_list(return_sig_list);
 		return_sig_list = NULL;
 	}
 
-	type_of_circuit = edge_type;
+	type_of_circuit = SEQUENTIAL;
+
 	return return_sig_list;
 }
 
@@ -4785,28 +4781,9 @@ signal_list_t *create_mux_statements(signal_list_t **statement_lists, nnode_t *m
 				/* Don't match, so this signal is an IMPLIED SIGNAL !!! */
 				npin_t *pin = combined_lists->pins[i];
 
-				switch(type_of_circuit)
+				switch(circuit_edge)
 				{
-					case RISING_EDGE_SENSITIVITY:
-					{
-						/* implied signal for mux */
-						if (lookup_implicit_memory_input(pin->name))
-						{
-							// If the mux feeds an implicit memory, imply zero.
-							add_input_pin_to_node(mux_node, get_zero_pin(verilog_netlist), pin_index);
-						}
-						else
-						{
-							/* lookup this driver name */
-							signal_list_t *this_pin_list = create_pins(NULL, pin->name, instance_name_prefix);
-							oassert(this_pin_list->count == 1);
-							//add_a_input_pin_to_node_spot_idx(mux_node, get_zero_pin(verilog_netlist), pin_index);
-							add_input_pin_to_node(mux_node, this_pin_list->pins[0], pin_index);
-							/* clean up */
-							free_signal_list(this_pin_list);
-						}
-						break;
-					}
+					case RISING_EDGE_SENSITIVITY: //fallthrough
 					case FALLING_EDGE_SENSITIVITY:
 					{
 						/* implied signal for mux */

ODIN_II/SRC/netlist_utils.cpp

@@ -81,7 +81,7 @@ nnode_t* allocate_nnode() {
 	new_node->num_undriven_pins = 0;
 
 	new_node->ratio = 1;
-	new_node->edge_type = RISING_EDGE_SENSITIVITY;
+	new_node->edge_type = UNDEFINED_SENSITIVITY;
 
 	new_node->has_initial_value = FALSE;
 	new_node->initial_value = 0;