diff --git a/ODIN_II/SRC/netlist_create_from_ast.cpp b/ODIN_II/SRC/netlist_create_from_ast.cpp index f32f628b073..cb55907e1f1 100644 --- a/ODIN_II/SRC/netlist_create_from_ast.cpp +++ b/ODIN_II/SRC/netlist_create_from_ast.cpp @@ -5832,6 +5832,8 @@ signal_list_t *create_hard_block(ast_node_t* block, char *instance_name_prefix, /* add the net to the list of inputs */ sc_spot = sc_add_string(input_nets_sc, pin_name); input_nets_sc->data[sc_spot] = (void*)new_net; + + vtr::free(pin_name); } current_out_idx += j; } @@ -5890,6 +5892,8 @@ signal_list_t *create_hard_block(ast_node_t* block, char *instance_name_prefix, /* add the net to the list of inputs */ sc_spot = sc_add_string(input_nets_sc, pin_name); input_nets_sc->data[sc_spot] = (void*)new_net; + + vtr::free(pin_name); } current_out_idx += j; } diff --git a/ODIN_II/SRC/parse_making_ast.cpp b/ODIN_II/SRC/parse_making_ast.cpp index 91f8ca120ff..740adc205a0 100644 --- a/ODIN_II/SRC/parse_making_ast.cpp +++ b/ODIN_II/SRC/parse_making_ast.cpp @@ -1507,10 +1507,13 @@ ast_node_t *newModule(char* module_name, ast_node_t *list_of_parameters, ast_nod long sc_spot; ast_node_t *symbol_node = newSymbolNode(module_name, line_number); - if(sc_lookup_string(hard_block_names, module_name) != -1) + if( sc_lookup_string(hard_block_names, module_name) != -1 + || !strcmp(module_name, SINGLE_PORT_RAM_string) + || !strcmp(module_name, DUAL_PORT_RAM_string) + ) { - warning_message(PARSE_ERROR, line_number, current_parse_file, - "Probable module name collision with hard block of the same name -> %s\n", module_name); + error_message(PARSE_ERROR, line_number, current_parse_file, + "Module name collides with hard block of the same name (%s)\n", module_name); } /* create a node for this array reference */ diff --git a/ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf b/ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf index f6ffe6d75ed..b04b1efd0f1 100644 --- a/ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf +++ b/ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf @@ -2,6 +2,7 @@ regression_test/benchmark/task/arch_sweep regression_test/benchmark/task/rs_decoder regression_test/benchmark/task/cmd_line_args/* regression_test/benchmark/task/func_simulator/* +regression_test/benchmark/task/hard_blocks regression_test/benchmark/task/multiclock/* regression_test/benchmark/task/operators regression_test/benchmark/task/syntax diff --git a/ODIN_II/regression_test/benchmark/task/hard_blocks/task.conf b/ODIN_II/regression_test/benchmark/task/hard_blocks/task.conf new file mode 100644 index 00000000000..676f219d7fa --- /dev/null +++ b/ODIN_II/regression_test/benchmark/task/hard_blocks/task.conf @@ -0,0 +1,17 @@ +######################## +# hard blocks benchmarks config +######################## + +script_synthesis_params=--time_limit 3600s --tool valgrind +script_simulation_params=--time_limit 3600s + +# setup the architecture +arch_dir=../vtr_flow/arch/timing + +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# setup the circuits +circuit_dir=regression_test/benchmark/verilog/micro + +circuit_list_add=adder_hard_block.v +circuit_list_add=multiply_hard_block.v diff --git a/ODIN_II/regression_test/benchmark/task/micro/task.conf b/ODIN_II/regression_test/benchmark/task/micro/task.conf index a452535d2df..cc769d35552 100644 --- a/ODIN_II/regression_test/benchmark/task/micro/task.conf +++ b/ODIN_II/regression_test/benchmark/task/micro/task.conf @@ -80,3 +80,8 @@ circuit_list_add=bm_if_common.v circuit_list_add=bm_if_collapse.v circuit_list_add=case_generate.v circuit_list_add=if_generate.v + +# these require specific architectures to run without errors + +# circuit_list_add=adder_hard_block.v +# circuit_list_add=multiply_hard_block.v \ No newline at end of file diff --git a/ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block.v b/ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block.v new file mode 100644 index 00000000000..9f7ae9ba9a7 --- /dev/null +++ b/ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block.v @@ -0,0 +1,13 @@ +module top_module +( + + input [1:0] a1, b1, a2, b2, + input cin1, cin2, + output [1:0] sumout1, sumout2, + output cout1, cout2 +); + + adder a1 (.a(a1), .b(b1), .cin(cin1), .sumout(sumout1), .cout(cout1)); + adder a2 (a2, b2, cin2, sumout2, cout2); + +endmodule \ No newline at end of file diff --git a/ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block_input b/ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block_input new file mode 100644 index 00000000000..a2e01dc80a6 --- /dev/null +++ b/ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block_input @@ -0,0 +1,101 @@ +GLOBAL_SIM_BASE_CLK a1 b1 a2 b2 cin1 cin2 +1 0X2 0X3 0X1 0X2 1 0 +0 0X2 0X1 0X0 0X0 1 0 +1 0X1 0X0 0X3 0X3 0 0 +0 0X3 0X1 0X1 0X3 1 1 +1 0X1 0X2 0X2 0X2 0 0 +0 0X0 0X2 0X3 0X2 0 1 +1 0X3 0X1 0X1 0X1 1 0 +0 0X1 0X1 0X0 0X0 1 1 +1 0X1 0X0 0X2 0X0 0 0 +0 0X1 0X0 0X3 0X1 1 0 +1 0X2 0X0 0X3 0X1 1 0 +0 0X3 0X3 0X3 0X3 1 0 +1 0X1 0X1 0X3 0X0 1 0 +0 0X3 0X0 0X2 0X2 0 1 +1 0X1 0X3 0X3 0X0 0 1 +0 0X1 0X0 0X0 0X1 1 1 +1 0X3 0X0 0X3 0X2 1 0 +0 0X2 0X3 0X3 0X0 1 1 +1 0X1 0X2 0X3 0X0 0 0 +0 0X0 0X3 0X1 0X2 0 1 +1 0X1 0X1 0X2 0X1 0 1 +0 0X0 0X3 0X1 0X2 0 0 +1 0X1 0X0 0X2 0X2 1 1 +0 0X2 0X0 0X0 0X2 0 0 +1 0X0 0X1 0X0 0X0 1 1 +0 0X2 0X3 0X1 0X1 0 1 +1 0X3 0X2 0X3 0X0 1 0 +0 0X0 0X0 0X0 0X2 1 0 +1 0X2 0X0 0X2 0X1 0 0 +0 0X2 0X1 0X3 0X3 1 0 +1 0X1 0X3 0X2 0X0 0 0 +0 0X2 0X2 0X0 0X0 0 0 +1 0X1 0X1 0X0 0X1 0 0 +0 0X3 0X1 0X2 0X0 1 1 +1 0X0 0X1 0X2 0X2 1 1 +0 0X2 0X1 0X2 0X0 0 0 +1 0X1 0X0 0X1 0X0 0 0 +0 0X1 0X3 0X1 0X0 1 0 +1 0X1 0X0 0X3 0X2 1 1 +0 0X1 0X2 0X0 0X1 1 1 +1 0X0 0X1 0X0 0X1 0 0 +0 0X2 0X3 0X1 0X2 0 1 +1 0X2 0X3 0X2 0X2 1 0 +0 0X1 0X3 0X3 0X1 0 1 +1 0X3 0X0 0X3 0X2 0 0 +0 0X3 0X0 0X1 0X2 1 1 +1 0X1 0X1 0X3 0X0 0 0 +0 0X0 0X1 0X0 0X0 0 0 +1 0X0 0X1 0X2 0X2 0 1 +0 0X3 0X0 0X2 0X0 0 1 +1 0X3 0X2 0X1 0X3 0 0 +0 0X0 0X2 0X0 0X3 1 1 +1 0X2 0X3 0X2 0X3 1 1 +0 0X1 0X3 0X2 0X0 1 0 +1 0X3 0X3 0X0 0X3 1 1 +0 0X0 0X3 0X1 0X0 0 1 +1 0X3 0X1 0X3 0X3 1 1 +0 0X0 0X2 0X1 0X0 1 1 +1 0X0 0X0 0X1 0X0 1 1 +0 0X0 0X2 0X3 0X1 1 1 +1 0X0 0X0 0X3 0X1 1 1 +0 0X3 0X1 0X1 0X1 1 0 +1 0X2 0X2 0X0 0X1 1 1 +0 0X2 0X3 0X2 0X2 0 0 +1 0X1 0X3 0X3 0X3 0 1 +0 0X0 0X1 0X3 0X0 0 0 +1 0X3 0X3 0X1 0X3 0 0 +0 0X1 0X3 0X1 0X1 1 1 +1 0X3 0X0 0X1 0X2 0 0 +0 0X3 0X0 0X2 0X0 1 0 +1 0X2 0X1 0X2 0X2 0 1 +0 0X2 0X0 0X2 0X0 0 0 +1 0X0 0X3 0X2 0X0 0 0 +0 0X3 0X3 0X1 0X1 1 1 +1 0X3 0X1 0X2 0X0 0 0 +0 0X1 0X2 0X2 0X3 0 0 +1 0X2 0X1 0X2 0X3 0 0 +0 0X2 0X3 0X3 0X0 1 1 +1 0X1 0X0 0X3 0X1 1 1 +0 0X2 0X2 0X3 0X2 0 0 +1 0X3 0X0 0X1 0X3 0 1 +0 0X2 0X1 0X2 0X3 0 0 +1 0X2 0X0 0X3 0X2 0 0 +0 0X0 0X0 0X2 0X2 1 0 +1 0X0 0X3 0X0 0X1 1 0 +0 0X1 0X3 0X0 0X1 1 1 +1 0X2 0X3 0X1 0X2 0 0 +0 0X3 0X0 0X1 0X3 1 1 +1 0X0 0X3 0X1 0X0 1 0 +0 0X0 0X0 0X2 0X2 1 0 +1 0X1 0X3 0X1 0X1 1 1 +0 0X1 0X3 0X3 0X2 0 0 +1 0X0 0X0 0X2 0X1 1 1 +0 0X1 0X2 0X1 0X3 1 0 +1 0X2 0X0 0X1 0X2 1 1 +0 0X3 0X1 0X0 0X2 0 1 +1 0X0 0X3 0X1 0X2 0 0 +0 0X0 0X1 0X1 0X0 1 1 +1 0X1 0X3 0X2 0X3 1 0 +0 0X2 0X3 0X1 0X3 1 1 diff --git a/ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block_output b/ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block_output new file mode 100644 index 00000000000..1f0c6edfd1e --- /dev/null +++ b/ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block_output @@ -0,0 +1,101 @@ +sumout1 sumout2 cout1 cout2 +0X1 0X3 1 0 +0X3 0X0 0 0 +0X1 0X2 0 1 +0X0 0X0 1 1 +0X3 0X0 0 1 +0X2 0X1 0 1 +0X0 0X2 1 0 +0X2 0X0 0 0 +0X1 0X2 0 0 +0X1 0X0 0 1 +0X2 0X0 0 1 +0X2 0X2 1 1 +0X2 0X3 0 0 +0X3 0X0 0 1 +0X0 0X3 1 0 +0X1 0X1 0 0 +0X3 0X1 0 1 +0X1 0X3 1 0 +0X3 0X3 0 0 +0X3 0X3 0 0 +0X2 0X3 0 0 +0X3 0X3 0 0 +0X1 0X0 0 1 +0X2 0X2 0 0 +0X1 0X0 0 0 +0X1 0X2 1 0 +0X1 0X3 1 0 +0X0 0X2 0 0 +0X2 0X3 0 0 +0X3 0X2 0 1 +0X0 0X2 1 0 +0X0 0X0 1 0 +0X2 0X1 0 0 +0X0 0X2 1 0 +0X1 0X0 0 1 +0X3 0X2 0 0 +0X1 0X1 0 0 +0X0 0X1 1 0 +0X1 0X1 0 1 +0X3 0X1 0 0 +0X1 0X1 0 0 +0X1 0X3 1 0 +0X1 0X0 1 1 +0X0 0X0 1 1 +0X3 0X1 0 1 +0X3 0X3 0 0 +0X2 0X3 0 0 +0X1 0X0 0 0 +0X1 0X0 0 1 +0X3 0X2 0 0 +0X1 0X0 1 1 +0X2 0X3 0 0 +0X1 0X1 1 1 +0X0 0X2 1 0 +0X2 0X3 1 0 +0X3 0X1 0 0 +0X0 0X2 1 1 +0X2 0X1 0 0 +0X0 0X1 0 0 +0X2 0X0 0 1 +0X0 0X0 0 1 +0X0 0X2 1 0 +0X0 0X1 1 0 +0X1 0X0 1 1 +0X0 0X2 1 1 +0X1 0X3 0 0 +0X2 0X0 1 1 +0X0 0X2 1 0 +0X3 0X3 0 0 +0X3 0X2 0 0 +0X3 0X0 0 1 +0X2 0X2 0 0 +0X3 0X2 0 0 +0X2 0X2 1 0 +0X0 0X2 1 0 +0X3 0X1 0 1 +0X3 0X1 0 1 +0X1 0X3 1 0 +0X1 0X0 0 1 +0X0 0X1 1 1 +0X3 0X0 0 1 +0X3 0X1 0 1 +0X2 0X1 0 1 +0X0 0X0 0 1 +0X3 0X1 0 0 +0X0 0X1 1 0 +0X1 0X3 1 0 +0X3 0X0 0 1 +0X3 0X1 0 0 +0X0 0X0 0 1 +0X0 0X2 1 0 +0X0 0X1 1 1 +0X0 0X3 0 0 +0X3 0X0 0 1 +0X2 0X3 0 0 +0X0 0X2 1 0 +0X3 0X3 0 0 +0X1 0X1 0 0 +0X0 0X1 1 1 +0X1 0X0 1 1 diff --git a/ODIN_II/regression_test/benchmark/verilog/micro/multiply_hard_block.v b/ODIN_II/regression_test/benchmark/verilog/micro/multiply_hard_block.v new file mode 100644 index 00000000000..089fec60725 --- /dev/null +++ b/ODIN_II/regression_test/benchmark/verilog/micro/multiply_hard_block.v @@ -0,0 +1,11 @@ +module top_module +( + + input [1:0] x1, x2, x3, x4, + output [3:0] y1, y2 +); + + multiply m1 (.a(x1), .b(x2), .out(y1)); + multiply m2 (x3, x4, y2); + +endmodule \ No newline at end of file diff --git a/ODIN_II/regression_test/benchmark/verilog/micro/multiply_hard_block_input b/ODIN_II/regression_test/benchmark/verilog/micro/multiply_hard_block_input new file mode 100644 index 00000000000..2cbacb04eee --- /dev/null +++ b/ODIN_II/regression_test/benchmark/verilog/micro/multiply_hard_block_input @@ -0,0 +1,101 @@ +GLOBAL_SIM_BASE_CLK x1 x2 x3 x4 +1 0X2 0X3 0X1 0X2 +0 0X2 0X2 0X1 0X0 +1 0X2 0X2 0X1 0X0 +0 0X3 0X1 0X0 0X3 +1 0X2 0X2 0X3 0X1 +0 0X0 0X1 0X1 0X1 +1 0X1 0X0 0X3 0X1 +0 0X2 0X2 0X3 0X2 +1 0X1 0X1 0X2 0X2 +0 0X0 0X0 0X3 0X2 +1 0X0 0X2 0X0 0X0 +0 0X1 0X0 0X3 0X1 +1 0X0 0X2 0X0 0X3 +0 0X2 0X2 0X3 0X3 +1 0X3 0X3 0X2 0X1 +0 0X2 0X1 0X2 0X2 +1 0X1 0X0 0X1 0X1 +0 0X2 0X2 0X3 0X1 +1 0X2 0X2 0X0 0X0 +0 0X1 0X3 0X3 0X1 +1 0X3 0X2 0X1 0X1 +0 0X3 0X3 0X0 0X3 +1 0X1 0X2 0X3 0X0 +0 0X0 0X0 0X3 0X1 +1 0X1 0X1 0X1 0X1 +0 0X3 0X0 0X1 0X0 +1 0X3 0X0 0X1 0X2 +0 0X0 0X0 0X1 0X3 +1 0X0 0X1 0X0 0X0 +0 0X0 0X0 0X2 0X0 +1 0X0 0X3 0X0 0X3 +0 0X1 0X1 0X2 0X3 +1 0X2 0X3 0X0 0X1 +0 0X0 0X0 0X0 0X2 +1 0X2 0X2 0X0 0X2 +0 0X0 0X2 0X2 0X1 +1 0X3 0X3 0X2 0X1 +0 0X1 0X1 0X0 0X0 +1 0X1 0X1 0X0 0X0 +0 0X3 0X2 0X0 0X2 +1 0X0 0X2 0X3 0X0 +0 0X0 0X3 0X1 0X2 +1 0X2 0X2 0X3 0X1 +0 0X1 0X2 0X0 0X0 +1 0X1 0X0 0X1 0X0 +0 0X0 0X1 0X3 0X1 +1 0X2 0X0 0X1 0X0 +0 0X1 0X3 0X3 0X1 +1 0X1 0X2 0X2 0X1 +0 0X2 0X0 0X2 0X0 +1 0X0 0X3 0X3 0X0 +0 0X2 0X1 0X3 0X1 +1 0X2 0X1 0X3 0X2 +0 0X3 0X1 0X2 0X3 +1 0X0 0X3 0X2 0X0 +0 0X3 0X0 0X1 0X2 +1 0X3 0X1 0X1 0X3 +0 0X0 0X2 0X0 0X1 +1 0X0 0X0 0X0 0X0 +0 0X0 0X1 0X1 0X3 +1 0X1 0X0 0X1 0X0 +0 0X2 0X1 0X3 0X2 +1 0X0 0X0 0X0 0X1 +0 0X3 0X3 0X1 0X3 +1 0X2 0X3 0X3 0X2 +0 0X3 0X2 0X0 0X1 +1 0X3 0X3 0X0 0X3 +0 0X3 0X0 0X3 0X1 +1 0X0 0X3 0X3 0X1 +0 0X3 0X3 0X1 0X0 +1 0X3 0X0 0X2 0X1 +0 0X0 0X2 0X0 0X2 +1 0X1 0X0 0X3 0X3 +0 0X3 0X1 0X0 0X2 +1 0X1 0X3 0X2 0X3 +0 0X1 0X1 0X1 0X0 +1 0X2 0X0 0X1 0X3 +0 0X2 0X3 0X2 0X2 +1 0X0 0X1 0X3 0X3 +0 0X1 0X3 0X0 0X1 +1 0X1 0X0 0X2 0X3 +0 0X3 0X2 0X1 0X2 +1 0X2 0X3 0X2 0X2 +0 0X2 0X1 0X2 0X0 +1 0X0 0X2 0X1 0X0 +0 0X0 0X1 0X0 0X3 +1 0X2 0X2 0X2 0X0 +0 0X0 0X2 0X0 0X0 +1 0X0 0X3 0X2 0X0 +0 0X2 0X3 0X3 0X1 +1 0X2 0X3 0X3 0X1 +0 0X1 0X0 0X0 0X1 +1 0X1 0X3 0X1 0X0 +0 0X3 0X0 0X3 0X1 +1 0X1 0X3 0X3 0X1 +0 0X3 0X2 0X0 0X2 +1 0X1 0X3 0X1 0X1 +0 0X3 0X2 0X0 0X2 +1 0X0 0X1 0X3 0X2 +0 0X2 0X1 0X2 0X3 diff --git a/ODIN_II/regression_test/benchmark/verilog/micro/multiply_hard_block_output b/ODIN_II/regression_test/benchmark/verilog/micro/multiply_hard_block_output new file mode 100644 index 00000000000..67944f7d6e1 --- /dev/null +++ b/ODIN_II/regression_test/benchmark/verilog/micro/multiply_hard_block_output @@ -0,0 +1,101 @@ +y1 y2 +0X6 0X2 +0X4 0X0 +0X4 0X0 +0X3 0X0 +0X4 0X3 +0X0 0X1 +0X0 0X3 +0X4 0X6 +0X1 0X4 +0X0 0X6 +0X0 0X0 +0X0 0X3 +0X0 0X0 +0X4 0X9 +0X9 0X2 +0X2 0X4 +0X0 0X1 +0X4 0X3 +0X4 0X0 +0X3 0X3 +0X6 0X1 +0X9 0X0 +0X2 0X0 +0X0 0X3 +0X1 0X1 +0X0 0X0 +0X0 0X2 +0X0 0X3 +0X0 0X0 +0X0 0X0 +0X0 0X0 +0X1 0X6 +0X6 0X0 +0X0 0X0 +0X4 0X0 +0X0 0X2 +0X9 0X2 +0X1 0X0 +0X1 0X0 +0X6 0X0 +0X0 0X0 +0X0 0X2 +0X4 0X3 +0X2 0X0 +0X0 0X0 +0X0 0X3 +0X0 0X0 +0X3 0X3 +0X2 0X2 +0X0 0X0 +0X0 0X0 +0X2 0X3 +0X2 0X6 +0X3 0X6 +0X0 0X0 +0X0 0X2 +0X3 0X3 +0X0 0X0 +0X0 0X0 +0X0 0X3 +0X0 0X0 +0X2 0X6 +0X0 0X0 +0X9 0X3 +0X6 0X6 +0X6 0X0 +0X9 0X0 +0X0 0X3 +0X0 0X3 +0X9 0X0 +0X0 0X2 +0X0 0X0 +0X0 0X9 +0X3 0X0 +0X3 0X6 +0X1 0X0 +0X0 0X3 +0X6 0X4 +0X0 0X9 +0X3 0X0 +0X0 0X6 +0X6 0X2 +0X6 0X4 +0X2 0X0 +0X0 0X0 +0X0 0X0 +0X4 0X0 +0X0 0X0 +0X0 0X0 +0X6 0X3 +0X6 0X3 +0X0 0X0 +0X3 0X0 +0X0 0X3 +0X3 0X3 +0X6 0X0 +0X3 0X1 +0X6 0X0 +0X0 0X6 +0X2 0X6 diff --git a/ODIN_II/regression_test/benchmark/verilog/operators/macromudule_test.v b/ODIN_II/regression_test/benchmark/verilog/operators/macromudule_test.v index 04926aecabe..94bad7954cf 100644 --- a/ODIN_II/regression_test/benchmark/verilog/operators/macromudule_test.v +++ b/ODIN_II/regression_test/benchmark/verilog/operators/macromudule_test.v @@ -1,4 +1,4 @@ -macromodule adder (in1,in2,out1); +macromodule my_adder (in1,in2,out1); input [3:0] in1,in2; output [4:0] out1; diff --git a/ODIN_II/regression_test/benchmark/verilog/syntax/rs_decoder_1.v b/ODIN_II/regression_test/benchmark/verilog/syntax/rs_decoder_1.v index e091bf3aeac..307f815daa2 100644 --- a/ODIN_II/regression_test/benchmark/verilog/syntax/rs_decoder_1.v +++ b/ODIN_II/regression_test/benchmark/verilog/syntax/rs_decoder_1.v @@ -329,14 +329,14 @@ module rsdec_berl (lambda_out, omega_out, syndrome0, syndrome1, syndrome2, syndr rsdec_berl_multiply x1 (tmp1, lambda11, DI, lambda1, syndrome1, phase0); rsdec_berl_multiply x2 (tmp2, A10, D, lambda2, syndrome2, phase0); rsdec_berl_multiply x3 (tmp3, omega11, DI, lambda3, syndrome3, phase0); - multiply x4 (tmp4, lambda4, syndrome4); - multiply x5 (tmp5, lambda5, syndrome5); - multiply x6 (tmp6, lambda6, syndrome6); - multiply x7 (tmp7, lambda7, syndrome7); - multiply x8 (tmp8, lambda8, syndrome8); - multiply x9 (tmp9, lambda9, syndrome9); - multiply x10 (tmp10, lambda10, syndrome10); - multiply x11 (tmp11, lambda11, syndrome11); + my_multiply x4 (tmp4, lambda4, syndrome4); + my_multiply x5 (tmp5, lambda5, syndrome5); + my_multiply x6 (tmp6, lambda6, syndrome6); + my_multiply x7 (tmp7, lambda7, syndrome7); + my_multiply x8 (tmp8, lambda8, syndrome8); + my_multiply x9 (tmp9, lambda9, syndrome9); + my_multiply x10 (tmp10, lambda10, syndrome10); + my_multiply x11 (tmp11, lambda11, syndrome11); always @ (posedge clk)// or negedge clrn) begin @@ -573,11 +573,11 @@ module rsdec_berl_multiply (y, a, b, c, d, e); if (e) q = d; else q = b; - multiply x0 (y, p, q); + my_multiply x0 (y, p, q); endmodule -module multiply (y, a, b); +module my_multiply (y, a, b); input [4:0] a, b; output [4:0] y; wire [9:0] tempy; @@ -1092,7 +1092,7 @@ module rsdec_chien (error, alpha, lambda, omega, even, D, search, load, shorten, always @ (o0 or o1 or o2 or o3 or o4 or o5 or o6 or o7 or o8 or o9 or o10 or o11) numerator = o0 ^ o1 ^ o2 ^ o3 ^ o4 ^ o5 ^ o6 ^ o7 ^ o8 ^ o9 ^ o10 ^ o11; - multiply m0 (tmp, numerator, D); + my_multiply m0 (tmp, numerator, D); always @ (even or odd or tmp) if (even == odd) error = tmp; diff --git a/ODIN_II/regression_test/benchmark/verilog/syntax/rs_decoder_2.v b/ODIN_II/regression_test/benchmark/verilog/syntax/rs_decoder_2.v index 591195c7dc9..2cd8a891a3b 100644 --- a/ODIN_II/regression_test/benchmark/verilog/syntax/rs_decoder_2.v +++ b/ODIN_II/regression_test/benchmark/verilog/syntax/rs_decoder_2.v @@ -786,10 +786,10 @@ module rsdec_berl (lambda_out, omega_out, syndrome0, syndrome1, syndrome2, syndr rsdec_berl_multiply x1 (tmp1, lambda7, DI, lambda1, syndrome1, phase0); rsdec_berl_multiply x2 (tmp2, A6, D, lambda2, syndrome2, phase0); rsdec_berl_multiply x3 (tmp3, omega7, DI, lambda3, syndrome3, phase0); - multiply x4 (tmp4, lambda4, syndrome4); - multiply x5 (tmp5, lambda5, syndrome5); - multiply x6 (tmp6, lambda6, syndrome6); - multiply x7 (tmp7, lambda7, syndrome7); + my_multiply x4 (tmp4, lambda4, syndrome4); + my_multiply x5 (tmp5, lambda5, syndrome5); + my_multiply x6 (tmp6, lambda6, syndrome6); + my_multiply x7 (tmp7, lambda7, syndrome7); always @ (posedge clk)// or negedge clrn) begin @@ -988,11 +988,11 @@ module rsdec_berl_multiply (y, a, b, c, d, e); if (e) q = d; else q = b; - multiply x0 (y, p, q); + my_multiply x0 (y, p, q); endmodule -module multiply (y, a, b); +module my_multiply (y, a, b); input [8:0] a, b; output [8:0] y; wire [8:0] y; @@ -1653,7 +1653,7 @@ module rsdec_chien (error, alpha, lambda, omega, even, D, search, load, shorten, always @ (o0 or o1 or o2 or o3 or o4 or o5 or o6 or o7) numerator = o0 ^ o1 ^ o2 ^ o3 ^ o4 ^ o5 ^ o6 ^ o7; - multiply m0 (tmp, numerator, D); + my_multiply m0 (tmp, numerator, D); always @ (even or odd or tmp) if (even == odd) error = tmp;