From f818b5736a77965e9781feb5ab8fb3edbcb6ee43 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Tue, 3 Jun 2025 17:12:43 -0400 Subject: [PATCH 1/2] [STA] Fixed Visual Bug in Post-Implementation SDC While presenting my tutorial on post-implementation timing analysis, I found that the SDC file generated did not look quite right. It was functionally correct, but some of the new-line characters were missing. Added the missing new line characters. --- vpr/src/base/netlist_writer.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/base/netlist_writer.cpp b/vpr/src/base/netlist_writer.cpp index d6f6405f16..c5e41113ee 100644 --- a/vpr/src/base/netlist_writer.cpp +++ b/vpr/src/base/netlist_writer.cpp @@ -2716,8 +2716,8 @@ void add_propagated_clocks_to_sdc_file(std::ofstream& sdc_os) { sdc_os << "#******************************************************************************#\n"; sdc_os << "# The following are clock domains in VPR which have delays on their edges.\n"; sdc_os << "#\n"; - sdc_os << "# Any non-virtual clock has its delay determined and written out as part of a"; - sdc_os << "# propagated clock command. If VPR was instructed not to route the clock, this"; + sdc_os << "# Any non-virtual clock has its delay determined and written out as part of a\n"; + sdc_os << "# propagated clock command. If VPR was instructed not to route the clock, this\n"; sdc_os << "# delay will be an underestimate.\n"; sdc_os << "#\n"; sdc_os << "# Note: Virtual clocks do not get routed and are treated as ideal.\n"; From f712d1065165019b04273da0856ffcff36c32869 Mon Sep 17 00:00:00 2001 From: AlexandreSinger Date: Tue, 3 Jun 2025 18:01:46 -0400 Subject: [PATCH 2/2] [STA] Added Tutorial Video to Timing Analysis Tutorial --- doc/src/tutorials/timing_analysis/index.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/src/tutorials/timing_analysis/index.rst b/doc/src/tutorials/timing_analysis/index.rst index 6f93faa4c0..20c6e2aef6 100644 --- a/doc/src/tutorials/timing_analysis/index.rst +++ b/doc/src/tutorials/timing_analysis/index.rst @@ -6,6 +6,8 @@ Post-Implementation Timing Analysis This tutorial describes how to perform static timing analysis (STA) on a circuit which has been implemented by :ref:`VPR` using OpenSTA, an external timing analysis tool. +A video of this tutorial can be found here: https://youtu.be/yihFJc7WOfE + External timing analysis can be useful since VPR's timing analyzer (Tatum) does not support all timing constraints and does not provide a TCL interface to allow you to directly interrogate the timing graph. VPR also has limited support for