From efd922cd0e6632f6630f9794ca36b0af05c1513d Mon Sep 17 00:00:00 2001 From: SamuelHo10 Date: Tue, 13 May 2025 17:44:13 -0400 Subject: [PATCH 1/6] removed most mallocs --- libs/libarchfpga/src/arch_util.cpp | 19 +++++++++---------- libs/libarchfpga/src/echo_arch.cpp | 4 ++-- libs/libarchfpga/src/logic_types.cpp | 2 +- libs/libarchfpga/src/read_xml_arch_file.cpp | 8 ++++---- 4 files changed, 16 insertions(+), 17 deletions(-) diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index b09bddb038..0c9c5aa2b2 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -335,7 +335,7 @@ static void free_pb_type(t_pb_type* pb_type) { for (int m = 0; m < pb_type->modes[i].interconnect[j].annotations[k].num_value_prop_pairs; ++m) { vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value[m]); } - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].prop); + delete[] pb_type->modes[i].interconnect[j].annotations[k].prop; vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value); } vtr::free(pb_type->modes[i].interconnect[j].annotations); @@ -355,7 +355,7 @@ static void free_pb_type(t_pb_type* pb_type) { vtr::free(pb_type->annotations[i].value[j]); } vtr::free(pb_type->annotations[i].value); - vtr::free(pb_type->annotations[i].prop); + delete[] pb_type->annotations[i].prop; if (pb_type->annotations[i].input_pins) { vtr::free(pb_type->annotations[i].input_pins); } @@ -367,7 +367,7 @@ static void free_pb_type(t_pb_type* pb_type) { } } if (pb_type->num_annotations > 0) { - vtr::free(pb_type->annotations); + delete[] pb_type->annotations; } if (pb_type->pb_type_power) { @@ -527,7 +527,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, } } - copy->annotations = (t_pin_to_pin_annotation*)vtr::calloc(pb_type->num_annotations, sizeof(t_pin_to_pin_annotation)); + copy->annotations = new t_pin_to_pin_annotation[pb_type->num_annotations](); copy->num_annotations = pb_type->num_annotations; for (i = 0; i < copy->num_annotations; i++) { copy->annotations[i].clock = vtr::strdup(pb_type->annotations[i].clock); @@ -549,7 +549,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, copy->annotations[i].format = pb_type->annotations[i].format; copy->annotations[i].type = pb_type->annotations[i].type; copy->annotations[i].num_value_prop_pairs = pb_type->annotations[i].num_value_prop_pairs; - copy->annotations[i].prop = (int*)vtr::malloc(sizeof(int) * pb_type->annotations[i].num_value_prop_pairs); + copy->annotations[i].prop = new int[pb_type->annotations[i].num_value_prop_pairs]; copy->annotations[i].value = (char**)vtr::malloc(sizeof(char*) * pb_type->annotations[i].num_value_prop_pairs); for (j = 0; j < pb_type->annotations[i].num_value_prop_pairs; j++) { copy->annotations[i].prop[j] = pb_type->annotations[i].prop[j]; @@ -627,8 +627,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[0].interconnect[0].annotations[i].format = lut_pb_type->annotations[i].format; lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type; lut_pb_type->modes[0].interconnect[0].annotations[i].num_value_prop_pairs = lut_pb_type->annotations[i].num_value_prop_pairs; - lut_pb_type->modes[0].interconnect[0].annotations[i].prop = (int*)vtr::malloc(sizeof(int) - * lut_pb_type->annotations[i].num_value_prop_pairs); + lut_pb_type->modes[0].interconnect[0].annotations[i].prop = new int[lut_pb_type->annotations[i].num_value_prop_pairs]; lut_pb_type->modes[0].interconnect[0].annotations[i].value = (char**)vtr::malloc(sizeof(char*) * lut_pb_type->annotations[i].num_value_prop_pairs); for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) { @@ -654,7 +653,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { free(lut_pb_type->annotations[i].value[j]); } free(lut_pb_type->annotations[i].value); - free(lut_pb_type->annotations[i].prop); + delete[] lut_pb_type->annotations[i].prop; if (lut_pb_type->annotations[i].input_pins) { free(lut_pb_type->annotations[i].input_pins); } @@ -666,7 +665,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { } } lut_pb_type->num_annotations = 0; - free(lut_pb_type->annotations); + delete[] lut_pb_type->annotations; lut_pb_type->annotations = nullptr; lut_pb_type->modes[1].pb_type_children[0].depth = lut_pb_type->depth + 1; lut_pb_type->modes[1].pb_type_children[0].parent_mode = &lut_pb_type->modes[1]; @@ -944,7 +943,7 @@ void SyncModelsPbTypes_rec(t_arch* arch, pb_type->model_id = model_match_prim_id; vtr::t_linked_vptr* old = model_match_prim.pb_types; - model_match_prim.pb_types = (vtr::t_linked_vptr*)vtr::malloc(sizeof(vtr::t_linked_vptr)); + model_match_prim.pb_types = new vtr::t_linked_vptr; model_match_prim.pb_types->next = old; model_match_prim.pb_types->data_vptr = pb_type; diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp index 2e08c19694..e50a087a77 100644 --- a/libs/libarchfpga/src/echo_arch.cpp +++ b/libs/libarchfpga/src/echo_arch.cpp @@ -383,7 +383,7 @@ static void print_model(FILE* echo, const t_model& model) { static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, const LogicalModels& models) { char* tabs; - tabs = (char*)vtr::malloc((level + 1) * sizeof(char)); + tabs = new char[level + 1]; for (int i = 0; i < level; i++) { tabs[i] = '\t'; } @@ -455,7 +455,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c if (pb_type->pb_type_power) { PrintPb_types_recPower(Echo, pb_type, tabs); } - free(tabs); + delete[] tabs; } //Added May 2013 Daniel Chen, help dump arch info after loading from XML diff --git a/libs/libarchfpga/src/logic_types.cpp b/libs/libarchfpga/src/logic_types.cpp index dc4801d334..8122c10489 100644 --- a/libs/libarchfpga/src/logic_types.cpp +++ b/libs/libarchfpga/src/logic_types.cpp @@ -144,7 +144,7 @@ void LogicalModels::free_model_data(t_model& model) { while (vptr) { vtr::t_linked_vptr* vptr_prev = vptr; vptr = vptr->next; - vtr::free(vptr_prev); + delete vptr_prev; } if (model.instances) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 3661516a53..eb431b9448 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -536,7 +536,7 @@ void XmlReadArch(const char* ArchFile, t_clock_arch* clocks_fake = (t_clock_arch*)vtr::calloc(1, sizeof(t_clock_arch)); ProcessClocks(Next, clocks_fake, loc_data); - free(clocks_fake->clock_inf); + delete[] clocks_fake->clock_inf; free(clocks_fake); } } @@ -887,7 +887,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, } annotation->num_value_prop_pairs = i; - annotation->prop = (int*)vtr::calloc(i, sizeof(int)); + annotation->prop = new int[i](); annotation->value = (char**)vtr::calloc(i, sizeof(char*)); annotation->line_num = loc_data.line(Parent); /* Todo: This is slow, I should use a case lookup */ @@ -1377,7 +1377,7 @@ static void ProcessPb_Type(pugi::xml_node Parent, num_annotations += count_children(Parent, child_name, loc_data, ReqOpt::OPTIONAL); } - pb_type->annotations = (t_pin_to_pin_annotation*)vtr::calloc(num_annotations, sizeof(t_pin_to_pin_annotation)); + pb_type->annotations = new t_pin_to_pin_annotation[num_annotations](); pb_type->num_annotations = num_annotations; int annotation_idx = 0; @@ -4725,7 +4725,7 @@ static void ProcessClocks(pugi::xml_node Parent, t_clock_arch* clocks, const pug /* Alloc the clockdetails */ clocks->clock_inf = nullptr; if (clocks->num_global_clocks > 0) { - clocks->clock_inf = (t_clock_network*)vtr::malloc(clocks->num_global_clocks * sizeof(t_clock_network)); + clocks->clock_inf = new t_clock_network[clocks->num_global_clocks]; memset(clocks->clock_inf, 0, clocks->num_global_clocks * sizeof(t_clock_network)); } From 0bdb49f4fe4aa51cbebb9b1f7df4ccf9ec44d053 Mon Sep 17 00:00:00 2001 From: SamuelHo10 Date: Wed, 14 May 2025 11:05:36 -0400 Subject: [PATCH 2/6] replaced most of the callocs with news --- libs/libarchfpga/src/arch_util.cpp | 65 ++++++++----------- .../src/read_fpga_interchange_arch.cpp | 20 +++--- libs/libarchfpga/src/read_xml_arch_file.cpp | 26 ++++---- 3 files changed, 49 insertions(+), 62 deletions(-) diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index 0c9c5aa2b2..67403e739c 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -163,7 +163,7 @@ void free_arch(t_arch* arch) { vtr::free(arch->architecture_id); if (arch->clocks) { - vtr::free(arch->clocks->clock_inf); + delete[] arch->clocks->clock_inf; } delete (arch->noc); @@ -336,16 +336,16 @@ static void free_pb_type(t_pb_type* pb_type) { vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value[m]); } delete[] pb_type->modes[i].interconnect[j].annotations[k].prop; - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value); + delete[] pb_type->modes[i].interconnect[j].annotations[k].value; } - vtr::free(pb_type->modes[i].interconnect[j].annotations); + delete[] pb_type->modes[i].interconnect[j].annotations; if (pb_type->modes[i].interconnect[j].interconnect_power) - vtr::free(pb_type->modes[i].interconnect[j].interconnect_power); + delete pb_type->modes[i].interconnect[j].interconnect_power; } if (pb_type->modes[i].interconnect) delete[] pb_type->modes[i].interconnect; if (pb_type->modes[i].mode_power) - vtr::free(pb_type->modes[i].mode_power); + delete (pb_type->modes[i].mode_power); } if (pb_type->modes) delete[] pb_type->modes; @@ -354,7 +354,7 @@ static void free_pb_type(t_pb_type* pb_type) { for (int j = 0; j < pb_type->annotations[i].num_value_prop_pairs; ++j) { vtr::free(pb_type->annotations[i].value[j]); } - vtr::free(pb_type->annotations[i].value); + delete[] pb_type->annotations[i].value; delete[] pb_type->annotations[i].prop; if (pb_type->annotations[i].input_pins) { vtr::free(pb_type->annotations[i].input_pins); @@ -371,7 +371,7 @@ static void free_pb_type(t_pb_type* pb_type) { } if (pb_type->pb_type_power) { - vtr::free(pb_type->pb_type_power); + delete pb_type->pb_type_power; } for (int i = 0; i < pb_type->num_ports; ++i) { @@ -380,10 +380,10 @@ static void free_pb_type(t_pb_type* pb_type) { vtr::free(pb_type->ports[i].port_class); } if (pb_type->ports[i].port_power) { - vtr::free(pb_type->ports[i].port_power); + delete pb_type->ports[i].port_power; } } - vtr::free(pb_type->ports); + delete[] pb_type->ports; } t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, int* low_index) { @@ -495,13 +495,12 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, copy->num_pb = 1; /* Power */ - copy->pb_type_power = (t_pb_type_power*)vtr::calloc(1, - sizeof(t_pb_type_power)); + copy->pb_type_power = new t_pb_type_power(); copy->pb_type_power->estimation_method = power_method_inherited(pb_type->pb_type_power->estimation_method); /* Ports */ copy->num_ports = pb_type->num_ports; - copy->ports = (t_port*)vtr::calloc(pb_type->num_ports, sizeof(t_port)); + copy->ports = new t_port[pb_type->num_ports](); for (i = 0; i < pb_type->num_ports; i++) { copy->ports[i].is_clock = pb_type->ports[i].is_clock; copy->ports[i].model_port = pb_type->ports[i].model_port; @@ -514,8 +513,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, copy->ports[i].index = pb_type->ports[i].index; copy->ports[i].absolute_first_pin_index = pb_type->ports[i].absolute_first_pin_index; - copy->ports[i].port_power = (t_port_power*)vtr::calloc(1, - sizeof(t_port_power)); + copy->ports[i].port_power = new t_port_power(); //Defaults if (copy->pb_type_power->estimation_method == POWER_METHOD_AUTO_SIZES) { copy->ports[i].port_power->wire_type = POWER_WIRE_TYPE_AUTO; @@ -550,7 +548,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, copy->annotations[i].type = pb_type->annotations[i].type; copy->annotations[i].num_value_prop_pairs = pb_type->annotations[i].num_value_prop_pairs; copy->annotations[i].prop = new int[pb_type->annotations[i].num_value_prop_pairs]; - copy->annotations[i].value = (char**)vtr::malloc(sizeof(char*) * pb_type->annotations[i].num_value_prop_pairs); + copy->annotations[i].value = new char*[pb_type->annotations[i].num_value_prop_pairs]; for (j = 0; j < pb_type->annotations[i].num_value_prop_pairs; j++) { copy->annotations[i].prop[j] = pb_type->annotations[i].prop[j]; copy->annotations[i].value[j] = vtr::strdup(pb_type->annotations[i].value[j]); @@ -580,8 +578,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[0].parent_pb_type = lut_pb_type; lut_pb_type->modes[0].index = 0; lut_pb_type->modes[0].num_pb_type_children = 0; - lut_pb_type->modes[0].mode_power = (t_mode_power*)vtr::calloc(1, - sizeof(t_mode_power)); + lut_pb_type->modes[0].mode_power = new t_mode_power(); /* Process interconnect */ /* TODO: add timing annotations to route-through */ @@ -613,10 +610,9 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[0].interconnect[0].parent_mode_index = 0; lut_pb_type->modes[0].interconnect[0].parent_mode = &lut_pb_type->modes[0]; - lut_pb_type->modes[0].interconnect[0].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power)); + lut_pb_type->modes[0].interconnect[0].interconnect_power = new t_interconnect_power(); - lut_pb_type->modes[0].interconnect[0].annotations = (t_pin_to_pin_annotation*)vtr::calloc(lut_pb_type->num_annotations, - sizeof(t_pin_to_pin_annotation)); + lut_pb_type->modes[0].interconnect[0].annotations = new t_pin_to_pin_annotation[lut_pb_type->num_annotations](); lut_pb_type->modes[0].interconnect[0].num_annotations = lut_pb_type->num_annotations; for (i = 0; i < lut_pb_type->modes[0].interconnect[0].num_annotations; i++) { @@ -628,8 +624,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type; lut_pb_type->modes[0].interconnect[0].annotations[i].num_value_prop_pairs = lut_pb_type->annotations[i].num_value_prop_pairs; lut_pb_type->modes[0].interconnect[0].annotations[i].prop = new int[lut_pb_type->annotations[i].num_value_prop_pairs]; - lut_pb_type->modes[0].interconnect[0].annotations[i].value = (char**)vtr::malloc(sizeof(char*) - * lut_pb_type->annotations[i].num_value_prop_pairs); + lut_pb_type->modes[0].interconnect[0].annotations[i].value = new char*[lut_pb_type->annotations[i].num_value_prop_pairs]; for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) { lut_pb_type->modes[0].interconnect[0].annotations[i].prop[j] = lut_pb_type->annotations[i].prop[j]; lut_pb_type->modes[0].interconnect[0].annotations[i].value[j] = vtr::strdup(lut_pb_type->annotations[i].value[j]); @@ -642,26 +637,25 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].parent_pb_type = lut_pb_type; lut_pb_type->modes[1].index = 1; lut_pb_type->modes[1].num_pb_type_children = 1; - lut_pb_type->modes[1].mode_power = (t_mode_power*)vtr::calloc(1, - sizeof(t_mode_power)); + lut_pb_type->modes[1].mode_power = new t_mode_power(); lut_pb_type->modes[1].pb_type_children = new t_pb_type[1]; alloc_and_load_default_child_for_pb_type(lut_pb_type, default_name, lut_pb_type->modes[1].pb_type_children); /* moved annotations to child so delete old annotations */ for (i = 0; i < lut_pb_type->num_annotations; i++) { for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) { - free(lut_pb_type->annotations[i].value[j]); + vtr::free(lut_pb_type->annotations[i].value[j]); } - free(lut_pb_type->annotations[i].value); + delete[] lut_pb_type->annotations[i].value; delete[] lut_pb_type->annotations[i].prop; if (lut_pb_type->annotations[i].input_pins) { - free(lut_pb_type->annotations[i].input_pins); + vtr::free(lut_pb_type->annotations[i].input_pins); } if (lut_pb_type->annotations[i].output_pins) { - free(lut_pb_type->annotations[i].output_pins); + vtr::free(lut_pb_type->annotations[i].output_pins); } if (lut_pb_type->annotations[i].clock) { - free(lut_pb_type->annotations[i].clock); + vtr::free(lut_pb_type->annotations[i].clock); } } lut_pb_type->num_annotations = 0; @@ -693,7 +687,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].interconnect[0].parent_mode_index = 1; lut_pb_type->modes[1].interconnect[0].parent_mode = &lut_pb_type->modes[1]; - lut_pb_type->modes[1].interconnect[0].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power)); + lut_pb_type->modes[1].interconnect[0].interconnect_power = new t_interconnect_power(); lut_pb_type->modes[1].interconnect[1].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 11, sizeof(char)); sprintf(lut_pb_type->modes[1].interconnect[1].name, "direct:%s", @@ -712,7 +706,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].interconnect[1].parent_mode_index = 1; lut_pb_type->modes[1].interconnect[1].parent_mode = &lut_pb_type->modes[1]; - lut_pb_type->modes[1].interconnect[1].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power)); + lut_pb_type->modes[1].interconnect[1].interconnect_power = new t_interconnect_power(); free(default_name); @@ -737,8 +731,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { mem_pb_type->modes[0].name = vtr::strdup(default_name); mem_pb_type->modes[0].parent_pb_type = mem_pb_type; mem_pb_type->modes[0].index = 0; - mem_pb_type->modes[0].mode_power = (t_mode_power*)vtr::calloc(1, - sizeof(t_mode_power)); + mem_pb_type->modes[0].mode_power = new t_mode_power(); num_pb = OPEN; for (i = 0; i < mem_pb_type->num_ports; i++) { if (mem_pb_type->ports[i].port_class != nullptr @@ -834,8 +827,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { } /* Allocate interconnect power structures */ - mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = (t_interconnect_power*)vtr::calloc(1, - sizeof(t_interconnect_power)); + mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power(); i_inter++; } else { for (j = 0; j < num_pb; j++) { @@ -875,8 +867,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { } /* Allocate interconnect power structures */ - mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = (t_interconnect_power*)vtr::calloc(1, - sizeof(t_interconnect_power)); + mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power(); i_inter++; } } diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index 265991c23f..161621f3f5 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -219,7 +219,7 @@ static t_port get_generic_port(t_arch* arch, port.is_non_clock_global = false; port.model_port = nullptr; port.port_class = vtr::strdup(nullptr); - port.port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power)); + port.port_power = new t_port_power(); if (!model.empty()) port.model_port = get_model_port(arch, model, name); @@ -243,8 +243,8 @@ static bool block_port_exists(t_pb_type* pb_type, std::string port_name) { static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string input, std::string output) { t_pin_to_pin_annotation pp; - pp.prop = (int*)vtr::calloc(1, sizeof(int)); - pp.value = (char**)vtr::calloc(1, sizeof(char*)); + pp.prop = new int(); + pp.value = new char*(); pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN; pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT; @@ -1293,7 +1293,7 @@ struct ArchReader { lut->model_id = get_model(arch_, LogicalModels::MODEL_NAMES); lut->num_ports = 2; - lut->ports = (t_port*)vtr::calloc(lut->num_ports, sizeof(t_port)); + lut->ports = new t_port[lut->num_ports](); lut->ports[0] = get_generic_port(arch_, lut, IN_PORT, "in", LogicalModels::MODEL_NAMES, width); lut->ports[1] = get_generic_port(arch_, lut, OUT_PORT, "out", LogicalModels::MODEL_NAMES); @@ -1377,7 +1377,7 @@ struct ArchReader { port->name = is_input ? vtr::strdup(ipin.c_str()) : vtr::strdup(opin.c_str()); port->model_port = nullptr; port->port_class = vtr::strdup(nullptr); - port->port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power)); + port->port_power = new t_port_power(); } // OPAD mode @@ -1395,7 +1395,7 @@ struct ArchReader { num_ports = 1; opad->num_ports = num_ports; - opad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + opad->ports = new t_port[num_ports](); opad->blif_model = vtr::strdup(LogicalModels::MODEL_OUTPUT); opad->model_id = get_model(arch_, LogicalModels::MODEL_OUTPUT); @@ -1417,7 +1417,7 @@ struct ArchReader { num_ports = 1; ipad->num_ports = num_ports; - ipad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + ipad->ports = new t_port[num_ports](); ipad->blif_model = vtr::strdup(LogicalModels::MODEL_INPUT); ipad->model_id = get_model(arch_, LogicalModels::MODEL_INPUT); @@ -1544,7 +1544,7 @@ struct ArchReader { int num_ports = ic_count; leaf->num_ports = num_ports; - leaf->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + leaf->ports = new t_port[num_ports](); leaf->blif_model = vtr::strdup((std::string(".subckt ") + name).c_str()); leaf->model_id = get_model(arch_, name); @@ -2082,7 +2082,7 @@ struct ArchReader { pb_type->modes = new t_mode[pb_type->num_modes]; pb_type->num_ports = 2; - pb_type->ports = (t_port*)vtr::calloc(pb_type->num_ports, sizeof(t_port)); + pb_type->ports = new t_port[pb_type->num_ports](); pb_type->num_output_pins = 2; pb_type->num_input_pins = 0; @@ -2118,7 +2118,7 @@ struct ArchReader { int num_ports = 1; leaf_pb_type->num_ports = num_ports; - leaf_pb_type->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + leaf_pb_type->ports = new t_port[num_ports](); leaf_pb_type->blif_model = vtr::strdup(const_cell.first.c_str()); leaf_pb_type->model_id = get_model(arch_, const_cell.first); diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index eb431b9448..c49118bc12 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -517,10 +517,9 @@ void XmlReadArch(const char* ArchFile, /* This information still needs to be read, even if it is just * thrown away. */ - t_power_arch* power_arch_fake = (t_power_arch*)vtr::calloc(1, - sizeof(t_power_arch)); + t_power_arch* power_arch_fake = new t_power_arch(); ProcessPower(Next, power_arch_fake, loc_data); - free(power_arch_fake); + delete power_arch_fake; } } @@ -533,11 +532,10 @@ void XmlReadArch(const char* ArchFile, /* This information still needs to be read, even if it is just * thrown away. */ - t_clock_arch* clocks_fake = (t_clock_arch*)vtr::calloc(1, - sizeof(t_clock_arch)); + t_clock_arch* clocks_fake = new t_clock_arch(); ProcessClocks(Next, clocks_fake, loc_data); delete[] clocks_fake->clock_inf; - free(clocks_fake); + delete clocks_fake; } } @@ -888,7 +886,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->num_value_prop_pairs = i; annotation->prop = new int[i](); - annotation->value = (char**)vtr::calloc(i, sizeof(char*)); + annotation->value = new char*[i](); annotation->line_num = loc_data.line(Parent); /* Todo: This is slow, I should use a case lookup */ i = 0; @@ -1285,7 +1283,7 @@ static void ProcessPb_Type(pugi::xml_node Parent, const int num_out_ports = count_children(Parent, "output", loc_data, ReqOpt::OPTIONAL); const int num_clock_ports = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL); const int num_ports = num_in_ports + num_out_ports + num_clock_ports; - pb_type->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + pb_type->ports = new t_port[num_ports](); pb_type->num_ports = num_ports; /* Enforce VPR's definition of LUT/FF by checking number of ports */ @@ -1300,7 +1298,7 @@ static void ProcessPb_Type(pugi::xml_node Parent, } /* Initialize Power Structure */ - pb_type->pb_type_power = (t_pb_type_power*)vtr::calloc(1, sizeof(t_pb_type_power)); + pb_type->pb_type_power = new t_pb_type_power(); ProcessPb_TypePowerEstMethod(Parent, pb_type, loc_data); /* process ports */ @@ -1461,7 +1459,7 @@ static void ProcessPb_TypePort_Power(pugi::xml_node Parent, t_port* port, e_powe const char* prop; bool wire_defined = false; - port->port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power)); + port->port_power = new t_port_power(); //Defaults if (power_method == POWER_METHOD_AUTO_SIZES) { @@ -1747,8 +1745,7 @@ static void ProcessInterconnect(vtr::string_internment& strings, num_annotations += count_children(Cur, annot_child_name, loc_data, ReqOpt::OPTIONAL); } - mode->interconnect[interconnect_idx].annotations = (t_pin_to_pin_annotation*)vtr::calloc(num_annotations, - sizeof(t_pin_to_pin_annotation)); + mode->interconnect[interconnect_idx].annotations = new t_pin_to_pin_annotation[num_annotations](); mode->interconnect[interconnect_idx].num_annotations = num_annotations; int annotation_idx = 0; @@ -1767,8 +1764,7 @@ static void ProcessInterconnect(vtr::string_internment& strings, VTR_ASSERT(annotation_idx == num_annotations); /* Power */ - mode->interconnect[interconnect_idx].interconnect_power = (t_interconnect_power*)vtr::calloc(1, - sizeof(t_interconnect_power)); + mode->interconnect[interconnect_idx].interconnect_power = new t_interconnect_power(); mode->interconnect[interconnect_idx].interconnect_power->port_info_initialized = false; /* get next iteration */ @@ -1848,7 +1844,7 @@ static void ProcessMode(pugi::xml_node Parent, } /* Allocate power structure */ - mode->mode_power = (t_mode_power*)vtr::calloc(1, sizeof(t_mode_power)); + mode->mode_power = new t_mode_power(); if (!implied_mode) { // Implied mode metadata is attached to the pb_type, rather than From 7cb20956e5172e997b36f87410c62eb933205639 Mon Sep 17 00:00:00 2001 From: SamuelHo10 Date: Wed, 14 May 2025 11:50:57 -0400 Subject: [PATCH 3/6] formatted c++ --- libs/libarchfpga/src/arch_util.cpp | 2 +- libs/libarchfpga/src/read_xml_arch_file.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index 67403e739c..17b1e096e1 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -624,7 +624,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type; lut_pb_type->modes[0].interconnect[0].annotations[i].num_value_prop_pairs = lut_pb_type->annotations[i].num_value_prop_pairs; lut_pb_type->modes[0].interconnect[0].annotations[i].prop = new int[lut_pb_type->annotations[i].num_value_prop_pairs]; - lut_pb_type->modes[0].interconnect[0].annotations[i].value = new char*[lut_pb_type->annotations[i].num_value_prop_pairs]; + lut_pb_type->modes[0].interconnect[0].annotations[i].value = new char*[lut_pb_type->annotations[i].num_value_prop_pairs]; for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) { lut_pb_type->modes[0].interconnect[0].annotations[i].prop[j] = lut_pb_type->annotations[i].prop[j]; lut_pb_type->modes[0].interconnect[0].annotations[i].value[j] = vtr::strdup(lut_pb_type->annotations[i].value[j]); diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index c49118bc12..cc5684d6bc 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -517,7 +517,7 @@ void XmlReadArch(const char* ArchFile, /* This information still needs to be read, even if it is just * thrown away. */ - t_power_arch* power_arch_fake = new t_power_arch(); + t_power_arch* power_arch_fake = new t_power_arch(); ProcessPower(Next, power_arch_fake, loc_data); delete power_arch_fake; } From 2c126007e5cc3e72f897340c744ab4ea4c923f31 Mon Sep 17 00:00:00 2001 From: SamuelHo10 Date: Wed, 14 May 2025 13:52:27 -0400 Subject: [PATCH 4/6] undid a couple changes to fix odin memory leak --- libs/libarchfpga/src/arch_util.cpp | 6 +++--- libs/libarchfpga/src/read_xml_arch_file.cpp | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index 17b1e096e1..c74a6c4e1e 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -367,7 +367,7 @@ static void free_pb_type(t_pb_type* pb_type) { } } if (pb_type->num_annotations > 0) { - delete[] pb_type->annotations; + vtr::free(pb_type->annotations); } if (pb_type->pb_type_power) { @@ -525,7 +525,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, } } - copy->annotations = new t_pin_to_pin_annotation[pb_type->num_annotations](); + copy->annotations = (t_pin_to_pin_annotation*)vtr::calloc(pb_type->num_annotations, sizeof(t_pin_to_pin_annotation)); copy->num_annotations = pb_type->num_annotations; for (i = 0; i < copy->num_annotations; i++) { copy->annotations[i].clock = vtr::strdup(pb_type->annotations[i].clock); @@ -659,7 +659,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { } } lut_pb_type->num_annotations = 0; - delete[] lut_pb_type->annotations; + vtr::free(lut_pb_type->annotations); lut_pb_type->annotations = nullptr; lut_pb_type->modes[1].pb_type_children[0].depth = lut_pb_type->depth + 1; lut_pb_type->modes[1].pb_type_children[0].parent_mode = &lut_pb_type->modes[1]; diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index cc5684d6bc..27014e9fa6 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -1375,7 +1375,7 @@ static void ProcessPb_Type(pugi::xml_node Parent, num_annotations += count_children(Parent, child_name, loc_data, ReqOpt::OPTIONAL); } - pb_type->annotations = new t_pin_to_pin_annotation[num_annotations](); + pb_type->annotations = (t_pin_to_pin_annotation*)vtr::calloc(num_annotations, sizeof(t_pin_to_pin_annotation)); pb_type->num_annotations = num_annotations; int annotation_idx = 0; From c0bf94c023c2d92502ae6346dcaa8c7f1b5f53eb Mon Sep 17 00:00:00 2001 From: SamuelHo10 Date: Tue, 20 May 2025 12:46:07 -0400 Subject: [PATCH 5/6] replaced t_clock_arch with std::shared_ptr> --- libs/libarchfpga/src/arch_util.cpp | 4 --- libs/libarchfpga/src/echo_arch.cpp | 20 +++++++------- libs/libarchfpga/src/physical_types.h | 12 +++------ libs/libarchfpga/src/read_xml_arch_file.cpp | 30 ++++++++------------- vpr/src/base/SetupVPR.cpp | 10 ++++--- vpr/src/base/vpr_context.h | 2 +- vpr/src/power/power.cpp | 28 +++++++++---------- 7 files changed, 46 insertions(+), 60 deletions(-) diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index c74a6c4e1e..56105d9ee1 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -162,10 +162,6 @@ void free_arch(t_arch* arch) { vtr::free(arch->architecture_id); - if (arch->clocks) { - delete[] arch->clocks->clock_inf; - } - delete (arch->noc); } diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp index e50a087a77..8d0fe1088e 100644 --- a/libs/libarchfpga/src/echo_arch.cpp +++ b/libs/libarchfpga/src/echo_arch.cpp @@ -335,19 +335,19 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { fprintf(Echo, "*************************************************\n"); fprintf(Echo, "Clock:\n"); if (arch->clocks) { - for (int i = 0; i < arch->clocks->num_global_clocks; i++) { - if (arch->clocks->clock_inf[i].autosize_buffer) { - fprintf(Echo, "\tClock[%d]: buffer_size auto C_wire %e", i + 1, - arch->clocks->clock_inf->C_wire); + for (size_t i = 0; i < arch->clocks->size(); i++) { + if ((*arch->clocks)[i].autosize_buffer) { + fprintf(Echo, "\tClock[%zu]: buffer_size auto C_wire %e", i + 1, + (*arch->clocks)[i].C_wire); } else { - fprintf(Echo, "\tClock[%d]: buffer_size %e C_wire %e", i + 1, - arch->clocks->clock_inf[i].buffer_size, - arch->clocks->clock_inf[i].C_wire); + fprintf(Echo, "\tClock[%zu]: buffer_size %e C_wire %e", i + 1, + (*arch->clocks)[i].buffer_size, + (*arch->clocks)[i].C_wire); } fprintf(Echo, "\t\t\t\tstat_prob %f switch_density %f period %e", - arch->clocks->clock_inf[i].prob, - arch->clocks->clock_inf[i].dens, - arch->clocks->clock_inf[i].period); + (*arch->clocks)[i].prob, + (*arch->clocks)[i].dens, + (*arch->clocks)[i].period); } } diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index c2459721d9..cd2982f9e9 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -47,7 +47,6 @@ #include "clock_types.h" //Forward declarations -struct t_clock_arch; struct t_clock_network; struct t_power_arch; struct t_interconnect_pins; @@ -411,12 +410,6 @@ struct t_grid_def { /************************* POWER ***********************************/ -/* Global clock architecture */ -struct t_clock_arch { - int num_global_clocks; - t_clock_network* clock_inf; /* Details about each clock */ -}; - /* Architecture information for a single clock */ struct t_clock_network { bool autosize_buffer; /* autosize clock buffers */ @@ -426,6 +419,8 @@ struct t_clock_network { float prob; /* Static probability of net assigned to this clock */ float dens; /* Switching density of net assigned to this clock */ float period; /* Period of clock */ + + t_clock_network() = default; }; /* Power-related architecture information */ @@ -2202,7 +2197,8 @@ struct t_arch { LogicalModels models; t_power_arch* power = nullptr; - t_clock_arch* clocks = nullptr; + + std::shared_ptr> clocks; //determine which layers in multi-die FPGAs require to build global routing resources std::vector layer_global_routing; diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 27014e9fa6..00ca8c2e67 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -357,7 +357,7 @@ static void ProcessPower(pugi::xml_node parent, t_power_arch* power_arch, const pugiutil::loc_data& loc_data); -static void ProcessClocks(pugi::xml_node Parent, t_clock_arch* clocks, const pugiutil::loc_data& loc_data); +static void ProcessClocks(pugi::xml_node Parent, std::vector& clocks, const pugiutil::loc_data& loc_data); static void ProcessPb_TypePowerEstMethod(pugi::xml_node Parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data); static void ProcessPb_TypePort_Power(pugi::xml_node Parent, t_port* port, e_power_estimation_method power_method, const pugiutil::loc_data& loc_data); @@ -527,15 +527,13 @@ void XmlReadArch(const char* ArchFile, Next = get_single_child(architecture, "clocks", loc_data, POWER_REQD); if (Next) { if (arch->clocks) { - ProcessClocks(Next, arch->clocks, loc_data); + ProcessClocks(Next, *arch->clocks, loc_data); } else { /* This information still needs to be read, even if it is just * thrown away. */ - t_clock_arch* clocks_fake = new t_clock_arch(); + std::vector clocks_fake; ProcessClocks(Next, clocks_fake, loc_data); - delete[] clocks_fake->clock_inf; - delete clocks_fake; } } @@ -4712,32 +4710,26 @@ static void ProcessPower(pugi::xml_node parent, } /* Get the clock architecture */ -static void ProcessClocks(pugi::xml_node Parent, t_clock_arch* clocks, const pugiutil::loc_data& loc_data) { +static void ProcessClocks(pugi::xml_node Parent, std::vector& clocks, const pugiutil::loc_data& loc_data) { pugi::xml_node Node; const char* tmp; - clocks->num_global_clocks = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL); + int num_global_clocks = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL); - /* Alloc the clockdetails */ - clocks->clock_inf = nullptr; - if (clocks->num_global_clocks > 0) { - clocks->clock_inf = new t_clock_network[clocks->num_global_clocks]; - memset(clocks->clock_inf, 0, - clocks->num_global_clocks * sizeof(t_clock_network)); - } + clocks.resize(num_global_clocks, t_clock_network()); /* Load the clock info. */ Node = get_first_child(Parent, "clock", loc_data); - for (int i = 0; i < clocks->num_global_clocks; ++i) { + for (int i = 0; i < num_global_clocks; ++i) { tmp = get_attribute(Node, "buffer_size", loc_data).value(); if (strcmp(tmp, "auto") == 0) { - clocks->clock_inf[i].autosize_buffer = true; + clocks[i].autosize_buffer = true; } else { - clocks->clock_inf[i].autosize_buffer = false; - clocks->clock_inf[i].buffer_size = (float)atof(tmp); + clocks[i].autosize_buffer = false; + clocks[i].buffer_size = (float)atof(tmp); } - clocks->clock_inf[i].C_wire = get_attribute(Node, "C_wire", loc_data).as_float(0); + clocks[i].C_wire = get_attribute(Node, "C_wire", loc_data).as_float(0); /* get the next clock item */ Node = Node.next_sibling(Node.name()); diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 2555663661..7ced0664d8 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -730,14 +730,16 @@ static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t if (!Arch->power) Arch->power = new t_power_arch(); - if (!Arch->clocks) - Arch->clocks = new t_clock_arch(); + if (!Arch->clocks) { + Arch->clocks = std::make_shared>(); + } device_ctx.clock_arch = Arch->clocks; + } else { Arch->power = nullptr; - Arch->clocks = nullptr; - device_ctx.clock_arch = nullptr; + Arch->clocks.reset(); + device_ctx.clock_arch.reset(); } } diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 3a5ca67df2..dc9b5bb146 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -267,7 +267,7 @@ struct DeviceContext : public Context { /******************************************************************* * Clock Network ********************************************************************/ - t_clock_arch* clock_arch; + std::shared_ptr> clock_arch; /// @brief Name of rrgraph file read (if any). /// Used to determine if the specified rr-graph file is already loaded, diff --git a/vpr/src/power/power.cpp b/vpr/src/power/power.cpp index 1b88e2e831..57353853b9 100644 --- a/vpr/src/power/power.cpp +++ b/vpr/src/power/power.cpp @@ -81,7 +81,7 @@ static void power_usage_local_buffers_and_wires(t_power_usage* power_usage, /* Clock */ static void power_usage_clock(t_power_usage* power_usage, - t_clock_arch* clock_arch); + std::vector clock_arch); static void power_usage_clock_single(t_power_usage* power_usage, t_clock_network* clock_inf); @@ -192,8 +192,8 @@ static void power_usage_primitive(t_power_usage* power_usage, t_pb* pb, t_pb_gra Q_dens = pin_dens(pb, Q_pin, iblk); Q_prob = pin_prob(pb, Q_pin, iblk); - clk_prob = device_ctx.clock_arch->clock_inf[0].prob; - clk_dens = device_ctx.clock_arch->clock_inf[0].dens; + clk_prob = (*device_ctx.clock_arch)[0].prob; + clk_dens = (*device_ctx.clock_arch)[0].dens; power_usage_ff(&sub_power_usage, power_ctx.arch->FF_size, D_prob, D_dens, Q_prob, Q_dens, clk_prob, clk_dens, power_ctx.solution_inf.T_crit); @@ -645,8 +645,8 @@ static void power_usage_blocks(t_power_usage* power_usage) { * Calculates the total power usage from the clock network */ static void power_usage_clock(t_power_usage* power_usage, - t_clock_arch* clock_arch) { - int clock_idx; + std::vector clock_arch) { + size_t clock_idx; auto& power_ctx = g_vpr_ctx.power(); /* Initialization */ @@ -654,27 +654,27 @@ static void power_usage_clock(t_power_usage* power_usage, power_usage->leakage = 0.; /* if no global clock, then return */ - if (clock_arch->num_global_clocks == 0) { + if (clock_arch.empty()) { return; } - for (clock_idx = 0; clock_idx < clock_arch->num_global_clocks; + for (clock_idx = 0; clock_idx < clock_arch.size(); clock_idx++) { t_power_usage clock_power; /* Assume the global clock is active even for combinational circuits */ - if (clock_arch->num_global_clocks == 1) { - if (clock_arch->clock_inf[clock_idx].dens == 0) { - clock_arch->clock_inf[clock_idx].dens = 2; - clock_arch->clock_inf[clock_idx].prob = 0.5; + if (clock_arch.size() == 1) { + if (clock_arch[clock_idx].dens == 0) { + clock_arch[clock_idx].dens = 2; + clock_arch[clock_idx].prob = 0.5; // This will need to change for multi-clock - clock_arch->clock_inf[clock_idx].period = power_ctx.solution_inf.T_crit; + clock_arch[clock_idx].period = power_ctx.solution_inf.T_crit; } } /* find the power dissipated by each clock network */ power_usage_clock_single(&clock_power, - &clock_arch->clock_inf[clock_idx]); + &clock_arch[clock_idx]); power_add_usage(power_usage, &clock_power); } @@ -1734,7 +1734,7 @@ e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, co power_component_add_usage(&sub_power_usage, POWER_COMPONENT_ROUTING); /* Clock */ - power_usage_clock(&sub_power_usage, arch->clocks); + power_usage_clock(&sub_power_usage, *arch->clocks); power_add_usage(&total_power, &sub_power_usage); power_component_add_usage(&sub_power_usage, POWER_COMPONENT_CLOCK); From e7b470a5409fa82124232703afb4f48ae3025649 Mon Sep 17 00:00:00 2001 From: SamuelHo10 Date: Fri, 23 May 2025 14:46:00 -0400 Subject: [PATCH 6/6] Repaced prop and value in t_pin_to_pin_annotation with std::pair --- libs/libarchfpga/src/arch_util.cpp | 48 +++++-------------- libs/libarchfpga/src/echo_arch.cpp | 4 +- libs/libarchfpga/src/physical_types.h | 11 +++-- .../src/read_fpga_interchange_arch.cpp | 8 +--- libs/libarchfpga/src/read_xml_arch_file.cpp | 48 +++++++++---------- vpr/src/pack/pb_type_graph_annotations.cpp | 46 +++++++++--------- vpr/src/power/power.cpp | 4 +- 7 files changed, 71 insertions(+), 98 deletions(-) diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index 56105d9ee1..16bef431bb 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -328,11 +328,7 @@ static void free_pb_type(t_pb_type* pb_type) { if (pb_type->modes[i].interconnect[j].annotations[k].output_pins) { vtr::free(pb_type->modes[i].interconnect[j].annotations[k].output_pins); } - for (int m = 0; m < pb_type->modes[i].interconnect[j].annotations[k].num_value_prop_pairs; ++m) { - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value[m]); - } - delete[] pb_type->modes[i].interconnect[j].annotations[k].prop; - delete[] pb_type->modes[i].interconnect[j].annotations[k].value; + } delete[] pb_type->modes[i].interconnect[j].annotations; if (pb_type->modes[i].interconnect[j].interconnect_power) @@ -347,11 +343,7 @@ static void free_pb_type(t_pb_type* pb_type) { delete[] pb_type->modes; for (int i = 0; i < pb_type->num_annotations; ++i) { - for (int j = 0; j < pb_type->annotations[i].num_value_prop_pairs; ++j) { - vtr::free(pb_type->annotations[i].value[j]); - } - delete[] pb_type->annotations[i].value; - delete[] pb_type->annotations[i].prop; + if (pb_type->annotations[i].input_pins) { vtr::free(pb_type->annotations[i].input_pins); } @@ -472,7 +464,7 @@ std::unordered_set get_equivalent_sites_set(t_physical void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, char* new_name, t_pb_type* copy) { - int i, j; + int i; char* dot; VTR_ASSERT(pb_type->blif_model != nullptr); @@ -542,13 +534,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, copy->annotations[i].line_num = pb_type->annotations[i].line_num; copy->annotations[i].format = pb_type->annotations[i].format; copy->annotations[i].type = pb_type->annotations[i].type; - copy->annotations[i].num_value_prop_pairs = pb_type->annotations[i].num_value_prop_pairs; - copy->annotations[i].prop = new int[pb_type->annotations[i].num_value_prop_pairs]; - copy->annotations[i].value = new char*[pb_type->annotations[i].num_value_prop_pairs]; - for (j = 0; j < pb_type->annotations[i].num_value_prop_pairs; j++) { - copy->annotations[i].prop[j] = pb_type->annotations[i].prop[j]; - copy->annotations[i].value[j] = vtr::strdup(pb_type->annotations[i].value[j]); - } + copy->annotations[i].pairs = pb_type->annotations[i].pairs; } } @@ -557,7 +543,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { char* default_name; t_port* in_port; t_port* out_port; - int i, j; + int i; if (strcmp(lut_pb_type->name, "lut") != 0) { default_name = vtr::strdup("lut"); @@ -618,13 +604,8 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[0].interconnect[0].annotations[i].line_num = lut_pb_type->annotations[i].line_num; lut_pb_type->modes[0].interconnect[0].annotations[i].format = lut_pb_type->annotations[i].format; lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type; - lut_pb_type->modes[0].interconnect[0].annotations[i].num_value_prop_pairs = lut_pb_type->annotations[i].num_value_prop_pairs; - lut_pb_type->modes[0].interconnect[0].annotations[i].prop = new int[lut_pb_type->annotations[i].num_value_prop_pairs]; - lut_pb_type->modes[0].interconnect[0].annotations[i].value = new char*[lut_pb_type->annotations[i].num_value_prop_pairs]; - for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) { - lut_pb_type->modes[0].interconnect[0].annotations[i].prop[j] = lut_pb_type->annotations[i].prop[j]; - lut_pb_type->modes[0].interconnect[0].annotations[i].value[j] = vtr::strdup(lut_pb_type->annotations[i].value[j]); - } + + lut_pb_type->modes[0].interconnect[0].annotations[i].pairs = lut_pb_type->annotations[i].pairs; } /* Second mode, LUT */ @@ -639,11 +620,6 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].pb_type_children); /* moved annotations to child so delete old annotations */ for (i = 0; i < lut_pb_type->num_annotations; i++) { - for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) { - vtr::free(lut_pb_type->annotations[i].value[j]); - } - delete[] lut_pb_type->annotations[i].value; - delete[] lut_pb_type->annotations[i].prop; if (lut_pb_type->annotations[i].input_pins) { vtr::free(lut_pb_type->annotations[i].input_pins); } @@ -1095,8 +1071,8 @@ const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_ty const t_pin_to_pin_annotation* annot = &pb_type->annotations[iannot]; InstPort annot_in(annot->input_pins); if (annot_in.port_name() == port->name) { - for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) { - if (annot->prop[iprop] == annot_type) { + for (size_t iprop = 0; iprop < annot->pairs.size(); ++iprop) { + if (annot->pairs[iprop].first == annot_type) { return annot; } } @@ -1114,9 +1090,9 @@ const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb for (const auto& annot_out_str : vtr::split(annot->output_pins)) { InstPort out_pins(annot_out_str); if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) { - for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) { - if (annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MAX - || annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MIN) { + for (size_t iprop = 0; iprop < annot->pairs.size(); ++iprop) { + if (annot->pairs[iprop].first == E_ANNOT_PIN_TO_PIN_DELAY_MAX + || annot->pairs[iprop].first == E_ANNOT_PIN_TO_PIN_DELAY_MIN) { return annot; } } diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp index 8d0fe1088e..2d5dea4562 100644 --- a/libs/libarchfpga/src/echo_arch.cpp +++ b/libs/libarchfpga/src/echo_arch.cpp @@ -419,7 +419,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c pb_type->modes[i].interconnect[j].annotations[k].input_pins, pb_type->modes[i].interconnect[j].annotations[k].output_pins, pb_type->modes[i].interconnect[j].annotations[k].format, - pb_type->modes[i].interconnect[j].annotations[k].value[0]); + pb_type->modes[i].interconnect[j].annotations[k].pairs[0].second.c_str()); } //Print power info for interconnects if (pb_type->modes[i].interconnect[j].interconnect_power) { @@ -447,7 +447,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c pb_type->annotations[k].input_pins, pb_type->annotations[k].output_pins, pb_type->annotations[k].format, - pb_type->annotations[k].value[0]); + pb_type->annotations[k].pairs[0].second.c_str()); } } } diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index cd2982f9e9..7841c4bd63 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1158,6 +1158,8 @@ struct t_interconnect { t_interconnect_power* interconnect_power = nullptr; t_metadata_dict meta; + + t_interconnect() = default; }; /** Describes I/O and clock ports @@ -1247,10 +1249,9 @@ struct t_mode_power { * output_pins: output pins as string affected by annotation * clock_pin: clock as string affected by annotation */ -struct t_pin_to_pin_annotation { - char** value; /* [0..num_value_prop_pairs - 1] */ - int* prop; /* [0..num_value_prop_pairs - 1] */ - int num_value_prop_pairs; +struct t_pin_to_pin_annotation{ + + std::vector> pairs; enum e_pin_to_pin_annotation_type type; enum e_pin_to_pin_annotation_format format; @@ -1260,6 +1261,8 @@ struct t_pin_to_pin_annotation { char* clock; int line_num; /* used to report what line number this annotation is found in architecture file */ + + t_pin_to_pin_annotation() = default; }; /************************************************************************************************* diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index 161621f3f5..91ec375288 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -243,16 +243,12 @@ static bool block_port_exists(t_pb_type* pb_type, std::string port_name) { static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string input, std::string output) { t_pin_to_pin_annotation pp; - pp.prop = new int(); - pp.value = new char*(); - pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN; pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT; - pp.prop[0] = (int)E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME; - pp.value[0] = vtr::strdup(pp_name.c_str()); + pp.pairs.push_back(std::make_pair(E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name)); pp.input_pins = vtr::strdup(input.c_str()); pp.output_pins = vtr::strdup(output.c_str()); - pp.num_value_prop_pairs = 1; + pp.clock = nullptr; return pp; diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 00ca8c2e67..d1fe59da66 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -882,9 +882,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, i = 1; } - annotation->num_value_prop_pairs = i; - annotation->prop = new int[i](); - annotation->value = new char*[i](); + annotation->pairs.resize(i); annotation->line_num = loc_data.line(Parent); /* Todo: This is slow, I should use a case lookup */ i = 0; @@ -893,14 +891,14 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "max", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (Prop) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MAX; - annotation->value[i] = vtr::strdup(Prop); + annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MAX; + annotation->pairs[i].second = Prop; i++; } Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (Prop) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MIN; - annotation->value[i] = vtr::strdup(Prop); + annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MIN; + annotation->pairs[i].second = Prop; i++; } Prop = get_attribute(Parent, "in_port", loc_data).value(); @@ -913,13 +911,13 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_MATRIX; Prop = get_attribute(Parent, "type", loc_data).value(); - annotation->value[i] = vtr::strdup(Parent.child_value()); + annotation->pairs[i].second = Parent.child_value(); if (0 == strcmp(Prop, "max")) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MAX; + annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MAX; } else { VTR_ASSERT(0 == strcmp(Prop, "min")); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MIN; + annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MIN; } i++; @@ -933,8 +931,8 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "C", loc_data).value(); - annotation->value[i] = vtr::strdup(Prop); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_CAPACITANCE_C; + annotation->pairs[i].second = Prop; + annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_CAPACITANCE_C; i++; Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); @@ -947,8 +945,8 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, } else if (0 == strcmp(Parent.name(), "C_matrix")) { annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE; annotation->format = E_ANNOT_PIN_TO_PIN_MATRIX; - annotation->value[i] = vtr::strdup(Parent.child_value()); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_CAPACITANCE_C; + annotation->pairs[i].second = Parent.child_value(); + annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_CAPACITANCE_C; i++; Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); @@ -962,8 +960,8 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "value", loc_data).value(); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_TSETUP; - annotation->value[i] = vtr::strdup(Prop); + annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_TSETUP; + annotation->pairs[i].second = Prop; i++; Prop = get_attribute(Parent, "port", loc_data).value(); @@ -981,15 +979,15 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, bool found_min_max_attrib = false; if (Prop) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX; - annotation->value[i] = vtr::strdup(Prop); + annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX; + annotation->pairs[i].second = Prop; i++; found_min_max_attrib = true; } Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (Prop) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN; - annotation->value[i] = vtr::strdup(Prop); + annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN; + annotation->pairs[i].second = Prop; i++; found_min_max_attrib = true; } @@ -1012,8 +1010,8 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "value", loc_data).value(); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_THOLD; - annotation->value[i] = vtr::strdup(Prop); + annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_DELAY_THOLD; + annotation->pairs[i].second = Prop; i++; Prop = get_attribute(Parent, "port", loc_data).value(); @@ -1028,8 +1026,8 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "name", loc_data).value(); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME; - annotation->value[i] = vtr::strdup(Prop); + annotation->pairs[i].first = E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME; + annotation->pairs[i].second = Prop; i++; Prop = get_attribute(Parent, "in_port", loc_data).value(); @@ -1043,7 +1041,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, "Unknown port type %s in %s in %s", Parent.name(), Parent.parent().name(), Parent.parent().parent().name()); } - VTR_ASSERT(i == annotation->num_value_prop_pairs); + VTR_ASSERT(i == static_cast(annotation->pairs.size())); } static void ProcessPb_TypePowerPinToggle(pugi::xml_node parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data) { diff --git a/vpr/src/pack/pb_type_graph_annotations.cpp b/vpr/src/pack/pb_type_graph_annotations.cpp index a01fec982b..4e643a7663 100644 --- a/vpr/src/pack/pb_type_graph_annotations.cpp +++ b/vpr/src/pack/pb_type_graph_annotations.cpp @@ -21,7 +21,7 @@ #include "pb_type_graph_annotations.h" #include "read_xml_arch_file.h" -static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const char* value); +static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const std::string& value); static void load_delay_annotations(const int line_num, t_pb_graph_node* pb_graph_node, @@ -51,19 +51,19 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { annotations = pb_type->annotations; for (i = 0; i < pb_type->num_annotations; i++) { if (annotations[i].type == E_ANNOT_PIN_TO_PIN_DELAY) { - for (j = 0; j < annotations[i].num_value_prop_pairs; j++) { - if (annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_MAX - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_MIN - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { + for (j = 0; j < static_cast(annotations[i].pairs.size()); j++) { + if (annotations[i].pairs[j].first == E_ANNOT_PIN_TO_PIN_DELAY_MAX + || annotations[i].pairs[j].first == E_ANNOT_PIN_TO_PIN_DELAY_MIN + || annotations[i].pairs[j].first == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX + || annotations[i].pairs[j].first == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN + || annotations[i].pairs[j].first == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP + || annotations[i].pairs[j].first == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { load_delay_annotations(annotations[i].line_num, pb_graph_node, OPEN, - annotations[i].format, (enum e_pin_to_pin_delay_annotations)annotations[i].prop[j], + annotations[i].format, (enum e_pin_to_pin_delay_annotations)annotations[i].pairs[j].first, annotations[i].input_pins, annotations[i].output_pins, annotations[i].clock, - annotations[i].value[j]); + annotations[i].pairs[j].second.c_str()); } else { VTR_ASSERT(false); } @@ -77,30 +77,30 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { annotations = pb_type->modes[i].interconnect[j].annotations; for (k = 0; k < pb_type->modes[i].interconnect[j].num_annotations; k++) { if (annotations[k].type == E_ANNOT_PIN_TO_PIN_DELAY) { - for (m = 0; m < annotations[k].num_value_prop_pairs; m++) { - if (annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_MAX - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_MIN - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { + for (m = 0; m < static_cast(annotations[k].pairs.size()); m++) { + if (annotations[k].pairs[m].first == E_ANNOT_PIN_TO_PIN_DELAY_MAX + || annotations[k].pairs[m].first == E_ANNOT_PIN_TO_PIN_DELAY_MIN + || annotations[k].pairs[m].first == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX + || annotations[k].pairs[m].first == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN + || annotations[k].pairs[m].first == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP + || annotations[k].pairs[m].first == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { load_delay_annotations(annotations[k].line_num, pb_graph_node, i, annotations[k].format, - (enum e_pin_to_pin_delay_annotations)annotations[k].prop[m], + (enum e_pin_to_pin_delay_annotations)annotations[k].pairs[m].first, annotations[k].input_pins, annotations[k].output_pins, annotations[k].clock, - annotations[k].value[m]); + annotations[k].pairs[m].second.c_str()); } else { VTR_ASSERT(false); } } } else if (annotations[k].type == E_ANNOT_PIN_TO_PIN_PACK_PATTERN) { - VTR_ASSERT(annotations[k].num_value_prop_pairs == 1); + VTR_ASSERT(annotations[k].pairs.size() == 1); load_pack_pattern_annotations(annotations[k].line_num, pb_graph_node, i, annotations[k].input_pins, annotations[k].output_pins, - annotations[k].value[0]); + annotations[k].pairs[0].second); } else { /* Todo: * load_power_annotations(pb_graph_node); @@ -126,7 +126,7 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { /* * Add the pattern name to the pack_pattern field for each pb_graph_edge that is used in a pack pattern */ -static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const char* value) { +static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const std::string& value) { int i, j, k, m, n, p, iedge; t_pb_graph_pin ***in_port, ***out_port; int *num_in_ptrs, *num_out_ptrs, num_in_sets, num_out_sets; @@ -155,7 +155,7 @@ static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* p if (iedge != in_port[i][j]->num_output_edges) { in_port[i][j]->output_edges[iedge]->num_pack_patterns++; in_port[i][j]->output_edges[iedge]->pack_pattern_names.resize(in_port[i][j]->output_edges[iedge]->num_pack_patterns); - in_port[i][j]->output_edges[iedge]->pack_pattern_names[in_port[i][j]->output_edges[iedge]->num_pack_patterns - 1] = value; + in_port[i][j]->output_edges[iedge]->pack_pattern_names[in_port[i][j]->output_edges[iedge]->num_pack_patterns - 1] = value.c_str(); // TODO: convert to std::string } p++; } diff --git a/vpr/src/power/power.cpp b/vpr/src/power/power.cpp index 57353853b9..2db0167419 100644 --- a/vpr/src/power/power.cpp +++ b/vpr/src/power/power.cpp @@ -81,7 +81,7 @@ static void power_usage_local_buffers_and_wires(t_power_usage* power_usage, /* Clock */ static void power_usage_clock(t_power_usage* power_usage, - std::vector clock_arch); + std::vector& clock_arch); static void power_usage_clock_single(t_power_usage* power_usage, t_clock_network* clock_inf); @@ -645,7 +645,7 @@ static void power_usage_blocks(t_power_usage* power_usage) { * Calculates the total power usage from the clock network */ static void power_usage_clock(t_power_usage* power_usage, - std::vector clock_arch) { + std::vector& clock_arch) { size_t clock_idx; auto& power_ctx = g_vpr_ctx.power();