diff --git a/.clang-format b/.clang-format index fa6b26413d0..774aba72016 100644 --- a/.clang-format +++ b/.clang-format @@ -15,7 +15,7 @@ AllowShortIfStatementsOnASingleLine: true AllowShortLoopsOnASingleLine: false AlwaysBreakAfterDefinitionReturnType: None AlwaysBreakAfterReturnType: None -AlwaysBreakBeforeMultilineStrings: true +AlwaysBreakBeforeMultilineStrings: false AlwaysBreakTemplateDeclarations: true BinPackArguments: true BinPackParameters: false @@ -34,7 +34,7 @@ BraceWrapping: SplitEmptyFunction: false SplitEmptyRecord: true SplitEmptyNamespace: true -BreakBeforeBinaryOperators: All +BreakBeforeBinaryOperators: NonAssignment BreakBeforeBraces: Custom BreakBeforeInheritanceComma: false BreakBeforeTernaryOperators: true @@ -68,10 +68,11 @@ IncludeIsMainRegex: '([-_](test|unittest))?$' IndentCaseLabels: true IndentWidth: 4 IndentWrappedFunctionNames: false -IndentPPDirectives: AfterHash +IndentPPDirectives: None +InsertNewlineAtEOF: true JavaScriptQuotes: Leave JavaScriptWrapImports: true -KeepEmptyLinesAtTheStartOfBlocks: false +KeepEmptyLinesAtTheStartOfBlocks: true MacroBlockBegin: '' MacroBlockEnd: '' MaxEmptyLinesToKeep: 1 diff --git a/.github/scripts/install_dependencies.sh b/.github/scripts/install_dependencies.sh index b5f5388f685..61ad671d30b 100755 --- a/.github/scripts/install_dependencies.sh +++ b/.github/scripts/install_dependencies.sh @@ -55,7 +55,7 @@ sudo apt install -y \ clang-16 \ clang-17 \ clang-18 \ - clang-format-14 \ + clang-format-18 \ libtbb-dev \ openssl diff --git a/.github/workflows/nightly_test.yml b/.github/workflows/nightly_test.yml index a57c502e0d3..a6782293b5d 100644 --- a/.github/workflows/nightly_test.yml +++ b/.github/workflows/nightly_test.yml @@ -22,8 +22,6 @@ on: # - '**.md' # - '**.rst' workflow_dispatch: - schedule: - - cron: '0 0 * * *' # daily # We want to cancel previous runs for a given PR or branch / ref if another CI # run is requested. @@ -65,9 +63,9 @@ jobs: - {test: "vtr_reg_strong", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3", extra_pkgs: "libeigen3-dev"} - {test: "vtr_reg_strong_odin", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"} - {test: "vtr_reg_strong_odin", cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"} - # - {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42) + - {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DSYNLIG_SYSTEMVERILOG=ON", extra_pkgs: ""} - {test: "odin_reg_strong", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""} - - {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=OFF", extra_pkgs: ""} + - {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DSYNLIG_SYSTEMVERILOG=ON", extra_pkgs: ""} env: DEBIAN_FRONTEND: "noninteractive" diff --git a/.github/workflows/nightly_test_manual.yml b/.github/workflows/nightly_test_manual.yml new file mode 100644 index 00000000000..f98f412eb8c --- /dev/null +++ b/.github/workflows/nightly_test_manual.yml @@ -0,0 +1,106 @@ +name: NightlyTestManual + +# This workflow can only be dispatched. +on: + workflow_dispatch: + + # Automatically runs every Sunday 5 AM UTC. + # Results should be ready ~15 hours later (Sunday 8 PM UTC), on time for Monday mornings. + schedule: + - cron: '0 5 * * 0' + +# We want to cancel previous runs for a given PR or branch / ref if another CI +# run is requested. +# See: https://docs.github.com/en/actions/using-jobs/using-concurrency +concurrency: + group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }} + cancel-in-progress: true + +env: + # default compiler for all non-compatibility tests + MATRIX_EVAL: "CC=gcc-13 && CXX=g++-13" + +jobs: + Run-tests: + # Prevents from running on forks where no custom runners are available + if: ${{ github.repository_owner == 'verilog-to-routing' }} + + name: 'Nightly Tests Manual Run' + # This workflow is expected to take around 19 hours. Giving it 24 hours + # before timing out. + timeout-minutes: 1440 + runs-on: [self-hosted, Linux, X64, SAVI] + + steps: + # Clean previous runs of this workflow. + - name: 'Cleanup build folder' + run: | + rm -rf ./* || true + rm -rf ./.??* || true + + # Checkout the VTR repo. + - uses: actions/checkout@v4 + with: + submodules: 'true' + + # Get the extra benchmarks + - name: 'Get Extra Benchmarks' + run: | + make get_titan_benchmarks + make get_ispd_benchmarks + ./dev/upgrade_vtr_archs.sh + make get_symbiflow_benchmarks + + # Build VTR using the default build options. + - name: 'Build VTR' + run: | + make -j12 + make env + source .venv/bin/activate + pip install -r requirements.txt + + # Run all of the nightly tests. + # TODO: We could expose more parallelism if we had one task list which ran + # all of these. + - name: 'Run Nightly Test 1' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test1 + + - name: 'Run Nightly Test 2' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test2 + + - name: 'Run Nightly Test 3' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test3 + + + - name: 'Run Nightly Test 4' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test4 + + - name: 'Run Nightly Test 5' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test5 + + - name: 'Run Nightly Test 6' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test6 + + - name: 'Run Nightly Test 7' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test7 diff --git a/.github/workflows/stale.yml b/.github/workflows/stale.yml new file mode 100644 index 00000000000..5f6e9fd9088 --- /dev/null +++ b/.github/workflows/stale.yml @@ -0,0 +1,31 @@ +name: 'Close Stale Issues' +on: + schedule: + # Run everyday at 1 PM UTC + - cron: '0 13 * * *' + +jobs: + stale: + runs-on: ubuntu-latest + steps: + - uses: actions/stale@v9 + with: + # The message to be shown for stale issues + stale-issue-message: 'This issue has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you believe this is still an issue, please add a comment.' + close-issue-message: 'This issue has been marked stale for 15 days and has been automatically closed.' + # If you want to exempt an issue from being marked stale/deleted, label it as 'no-stale' + exempt-issue-labels: 'no-stale' + days-before-issue-stale: 365 + days-before-issue-close: 15 + # Start from the oldest issues + ascending: true + + # The configuration below can be used to allow the same behaviour with PRs. + # Since we currently don't want to close old PRs, it is commented out but + # left here in case we change our mind. + + # stale-pr-message: 'This PR has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you are still working on this PR, please add a comment.' + # close-pr-message: 'This PR has been marked stale for 15 days and has been automatically closed.' + # exempt-pr-labels: 'no-stale' + # days-before-pr-stale: 365 + # days-before-pr-close: 15 \ No newline at end of file diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index b6c665ff3ed..5977e1221ba 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -89,6 +89,8 @@ jobs: with: python-version: 3.10.10 - uses: actions/checkout@v4 + with: + submodules: 'true' - name: Install dependencies run: ./.github/scripts/install_dependencies.sh @@ -439,7 +441,6 @@ jobs: - { name: 'GCC 11 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-11 && CXX=g++-11', } - { name: 'GCC 12 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-12 && CXX=g++-12', } - { name: 'GCC 14 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-14 && CXX=g++-14', } - - { name: 'Clang 15 (Ubuntu Noble - 24.04)', eval: 'CC=clang-15 && CXX=clang++-15', } - { name: 'Clang 16 (Ubuntu Noble - 24.04)', eval: 'CC=clang-16 && CXX=clang++-16', } - { name: 'Clang 17 (Ubuntu Noble - 24.04)', eval: 'CC=clang-17 && CXX=clang++-17', } - { name: 'Clang 18 (Ubuntu Noble - 24.04)', eval: 'CC=clang-18 && CXX=clang++-18', } diff --git a/.gitmodules b/.gitmodules index d8738f84253..8a35f2bff8c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,8 @@ [submodule "libs/EXTERNAL/libcatch2"] path = libs/EXTERNAL/libcatch2 url = https://github.com/catchorg/Catch2.git + +# fork where in branch v1.0.0_no_complication_warnings there are compilation warnings fixes for upstream tag v1.0.0 of sockpp [submodule "libs/EXTERNAL/sockpp"] path = libs/EXTERNAL/sockpp - url = https://github.com/w0lek/sockpp.git # fork where in branch v1.0.0_no_complication_warnings there are compilation warnings fixes for upstream tag v1.0.0 of sockpp + url = https://github.com/w0lek/sockpp.git diff --git a/.gitpod.Dockerfile b/.gitpod.Dockerfile index b738f995a69..bb6524f7f53 100644 --- a/.gitpod.Dockerfile +++ b/.gitpod.Dockerfile @@ -30,6 +30,7 @@ RUN apt-get update \ python-lxml \ qt5-default \ wget \ + default-jre \ && apt-get clean \ && rm -rf /var/lib/apt/lists/* diff --git a/CHANGELOG.md b/CHANGELOG.md index ba313c7720d..d86dda1c83d 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -47,6 +47,64 @@ _The following are changes which have been implemented in the VTR master branch ### Removed + +## v9.0.0 - 2024-12-23 + +### Added + * Support for Advanced Architectures: + * 3D FPGA and RAD architectures. + * Architectures with hard Networks-on-Chip (NoCs). + * Distinct horizontal and vertical channel widths and types. + * Diagonal routing wires and other complex wire shapes (L-shaped, T-shaped, ....). + + * New Benchmark Suites: + * Koios: A deep-learning-focused benchmark suite with various design sizes. + * Hermes: Benchmarks utilizing hard NoCs. + * TitanNew: Large benchmarks targeting the Stratix 10 architecture. + + * Commercial FPGAs Architecture Captures: + * Intel’s Stratix 10 FPGA architecture. + * AMD’s 7-series FPGA architecture. + + * Parmys Logic Synthesis Flow: + * Better Verilog language coverage + * More efficient hard block mapping + + * VPR Graphics Visualizations: + * New interface for improved usability and underlying graphics rewritten using EZGL/GTK to allow more UI widgets. + * Algorithm breakpoint visualizations for placement and routing algorithm debugging. + * User-guided (manual) placement optimization features. + * Enabled a live connection for client graphical application to VTR engines through sockets (server mode). + * Interactive timing path analysis (IPA) client using server mode. + + * Performance Enhancements: + * Parallel router for faster inter-cluster routing or flat routing. + + * Re-clustering API to modify packing decisions during the flow. + * Support for floorplanning and placement constraints. + * Unified intra- and inter-cluster (flat) routing. + * Comprehensive web-based VTR utilities and API documentation. + +### Changed + * The default values of many command line options (e.g. inner_num is 0.5 instead of 1.0) + * Changes to placement engine + * Smart centroid initial placement algorithm. + * Multiple smart placement directed moves. + * Reinforcement learning-based placement algorithm. + * Changes to routing engine + * Faster lookahead creation. + * More accurate lookahead for large blocks. + * More efficient heap and pruning strategies. + * max `pres_fac` capped to avoid possible numeric issues. + + +### Fixed + * Many algorithmic and coding bugs are fixed in this release + +### Removed + * Breadth-first (non-timing-driven) router. + * Non-linear congestion placement cost. + ## v8.0.0 - 2020-03-24 ### Added diff --git a/CMakeLists.txt b/CMakeLists.txt index 3ef16e0bcfc..653c3f17173 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -61,10 +61,10 @@ option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF) # Allow the user to enable building Yosys option(WITH_PARMYS "Enable Yosys as elaborator and parmys-plugin as partial mapper" ON) -option(YOSYS_F4PGA_PLUGINS "Enable building and installing Yosys SystemVerilog and UHDM plugins" OFF) +option(SYNLIG_SYSTEMVERILOG "Enable building and installing Synlig SystemVerilog and UHDM plugins" OFF) -set(VTR_VERSION_MAJOR 8) -set(VTR_VERSION_MINOR 1) +set(VTR_VERSION_MAJOR 9) +set(VTR_VERSION_MINOR 0) set(VTR_VERSION_PATCH 0) set(VTR_VERSION_PRERELEASE "dev") @@ -94,9 +94,9 @@ add_definitions("-DVTR_ASSERT_LEVEL=${VTR_ASSERT_LEVEL}") include(CheckCXXCompilerFlag) # -# We require c++17 support +# We require c++20 support # -set(CMAKE_CXX_STANDARD 17) +set(CMAKE_CXX_STANDARD 20) set(CMAKE_CXX_STANDARD_REQUIRED ON) set(CMAKE_CXX_EXTENSIONS OFF) #No compiler specific extensions @@ -161,7 +161,7 @@ else() "-Wcast-align" #Warn if a cast causes memory alignment changes "-Wshadow" #Warn if local variable shadows another variable "-Wformat=2" #Sanity checks for printf-like formatting - "-Wno-format-nonliteral" # But don't worry about non-literal formtting (i.e. run-time printf format strings) + "-Wno-format-nonliteral" # But don't worry about non-literal formatting (i.e. run-time printf format strings) "-Wlogical-op" #Checks for logical op when bit-wise expected "-Wmissing-declarations" #Warn if a global function is defined with no declaration "-Wmissing-include-dirs" #Warn if a user include directory is missing @@ -179,10 +179,10 @@ else() "-Wduplicated-cond" #Warn about identical conditions in if-else chains "-Wduplicated-branches" #Warn when different branches of an if-else chain are equivalent "-Wnull-dereference" #Warn about null pointer dereference execution paths - "-Wuninitialized" #Warn about unitialized values + "-Wuninitialized" #Warn about uninitialized values "-Winit-self" #Warn about self-initialization "-Wcatch-value=3" #Warn when catch statements don't catch by reference - "-Wextra-semi" #Warn about redudnant semicolons + "-Wextra-semi" #Warn about redundant semicolons "-Wimplicit-fallthrough=3" #Warn about case fallthroughs, but allow 'fallthrough' comments to suppress warnings #GCC-like optional #"-Wsuggest-final-types" #Suggest where 'final' would help if specified on a type methods @@ -454,7 +454,7 @@ if(${WITH_ODIN}) endif() # handle cmake params to compile Yosys SystemVerilog/UHDM plugins -if(${YOSYS_F4PGA_PLUGINS}) +if(${SYNLIG_SYSTEMVERILOG}) # avoid compiling plugins in case the Parmys frontend is not active if(NOT ${WITH_PARMYS}) message(SEND_ERROR "Utilizing SystemVerilog/UHDM plugins requires activating Parmys frontend. Please set WITH_PARMYS.") diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index f5030302bf9..2ebfababd8d 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -77,7 +77,7 @@ This information helps us to quickly reproduce (and hopefully fix) the issue: Tell us what version of VTR you are using (e.g. the output of `vpr --version`), which Operating System and compiler you are using, or any other relevant information about where or how you are building/running VTR. -Once you've gathered all the information [open an Issue](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/new?template=bug_report.md) on our issue tracker. +Once you've gathered all the information [open an Issue](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/new?template=bug_report.md) on our issue tracker. Issues that do not have any activity for a year will be automatically marked as stale and will be closed after 15 days of being marked as stale. If you know how to fix the issue, or already have it coded-up, please also consider [submitting the fix](#submitting-code-to-vtr). This is likely the fastest way to get bugs fixed! diff --git a/Dockerfile b/Dockerfile index 71f5129301a..2b36ac5c5e5 100644 --- a/Dockerfile +++ b/Dockerfile @@ -15,6 +15,7 @@ RUN apt-get update -qq \ && apt-get -y install --no-install-recommends \ wget \ ninja-build \ + default-jre \ libeigen3-dev \ libtbb-dev \ python3-pip \ diff --git a/Makefile b/Makefile index 06d2df4c158..109288f0344 100644 --- a/Makefile +++ b/Makefile @@ -48,14 +48,14 @@ ifeq ($(VERBOSE),1) override CMAKE_PARAMS := -DVTR_ENABLE_VERBOSE=on ${CMAKE_PARAMS} endif -# -s : Suppresss makefile output (e.g. entering/leaving directories) +# -s : Suppresses makefile output (e.g. entering/leaving directories) # --output-sync target : For parallel compilation ensure output for each target is synchronized (make version >= 4.0) MAKEFLAGS := -s SOURCE_DIR := $(PWD) BUILD_DIR ?= build -#Check for the cmake exectuable +#Check for the cmake executable CMAKE := $(shell command -v cmake 2> /dev/null) #Show test log on failures with 'make test' diff --git a/README.developers.md b/README.developers.md index 709a256c58c..866f8ca1dac 100644 --- a/README.developers.md +++ b/README.developers.md @@ -301,10 +301,13 @@ For the very large runs, you can submit your runs on a large cluster. A template a Slurm-managed cluster can be found under vtr_flow/tasks/slurm/ ## Continuous integration (CI) + +### Automatic (Github runner) CI tests + For the following tests, you can use remote servers instead of running them locally. Once the changes are pushed into the remote repository, or a PR is created, the [Test Workflow](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/.github/workflows/test.yml) will be triggered. Many tests are included in the workflow, including: -* [vtr_reg_nightly_test1-N](#vtr_reg_nightly_test1-N) +* [vtr_reg_nightly_test1-N](#vtr_reg_nightly_test1-n) * [vtr_reg_strong](#vtr_reg_strong) * [vtr_reg_basic](#vtr_reg_basic) * odin_reg_strong @@ -312,6 +315,15 @@ will be triggered. Many tests are included in the workflow, including: instructions on how to gather QoR results of CI runs can be found [here](#example-extracting-qor-data-from-ci-runs). +### Manual Nightly Tests + +You can use remote servers to run the [vtr_reg_nightly_test1-7](#vtr_reg_nightly_test1-n) tests. These tests are triggered manually by going to the GitHub Actions menu, selecting the NightlyTestManual workflow and selecting run workflow on the branch you want to test. Once you do that, the [Nightly Test Manual Workflow](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/.github/workflows/nightly_test_manual.yml) will be triggered. This run will take approximately 15 hours to complete and will cancel all other workflow runs for the same branch. + +Select GitHub Actions menu +
+Select the NightlyTestManual workflow +Run the Workflow + #### Re-run CI Tests In the case that you want to re-run the CI tests, due to certain issues such as infrastructure failure, go to the "Action" tab and find your workflow under Test Workflow. @@ -637,6 +649,10 @@ They can be used for FPGA architecture exploration for DL and also for tuning CA A typical approach to evaluating an algorithm change would be to run `koios_medium` (or `koios_medium_no_hb`) tasks from the nightly regression test (vtr_reg_nightly_test4), the `koios_large` (or `koios_large_no_hb`) and the `koios_proxy` (or `koios_proxy_no_hb`) tasks from the weekly regression test (vtr_reg_weekly). The nightly test contains smaller benchmarks, whereas the large designs are in the weekly regression test. To measure QoR for the entire benchmark suite, both nightly and weekly tests should be run and the results should be concatenated. +As 3 of the `koios_large` circuits require special settings due to having long DSP chains, they are split in separate tasks as follows: + * `bwave_like.float.large.v` and `bwave_like.fixed.large.v` are in `vtr_reg_weekly/koios_bwave_large` task + * `dla_like.large.v` is in `vtr_reg_weekly/koios_dla_large` task + For evaluating an algorithm change in the Odin frontend, run `koios_medium` (or `koios_medium_no_hb`) tasks from the nightly regression test (vtr_reg_nightly_test4_odin) and the `koios_large_odin` (or `koios_large_no_hb_odin`) tasks from the weekly regression test (vtr_reg_weekly). The `koios_medium`, `koios_large`, and `koios_proxy` regression tasks run these benchmarks with complex_dsp functionality enabled, whereas `koios_medium_no_hb`, `koios_large_no_hb` and `koios_proxy_no_hb` regression tasks run these benchmarks without complex_dsp functionality. Normally, only the `koios_medium`, `koios_large`, and `koios_proxy` tasks should be enough for QoR. @@ -651,6 +667,8 @@ The following table provides details on available Koios settings in VTR flow: | Nightly | Medium designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_nightly_test4_odin/koios_medium | Odin | | | Nightly | Medium designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_nightly_test4_odin/koios_medium_no_hb | Odin | | | Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_large | Parmys | | +| Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_dla_large | Parmys | | +| Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_bwave_large | Parmys | | | Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_weekly/koios_large_no_hb | Parmys | | | Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_large_odin | Odin | | | Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_weekly/koios_large_no_hb_odin | Odin | | @@ -661,7 +679,15 @@ The following table provides details on available Koios settings in VTR flow: For more information refer to the [Koios benchmark home page](vtr_flow/benchmarks/verilog/koios/README.md). -The following steps show a sequence of commands to run the `koios` tasks on the Koios benchmarks: +To make running all the koios benchmarks easier, especially with thos circuits scattered between different tasks, there is an overall task list that runs all the 40 circuits of Koios as follows (this will run all the circuits with complex DSP functionality enabled. If you want to disable the complex DSP, edit the file to point to the `koios_*_no_hb` tasks): + +```shell +$ ../scripts/run_vtr_task.py -l koios_task_list.txt + +#Several hours later... they complete +# + +If you want to run a subset of the koios benchmarks or run them without hard DSP blocks, you can run lower-level 'koios' tasks as follows: ```shell #From the VTR root @@ -681,17 +707,6 @@ $ ../scripts/run_vtr_task.py regression_tests/vtr_reg_weekly/koios_sv_no_hb & #Several hours later... they complete -#Parse the results -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_nightly_test4/koios_medium -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_large -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_proxy -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_sv - -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_large_no_hb -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_proxy_no_hb -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_sv_no_hb - #The run directory should now contain a summary parse_results.txt file $ head -5 vtr_reg_nightly_test4/koios_medium//parse_results.txt arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time diff --git a/cmake/modules/AutoClangFormat.cmake b/cmake/modules/AutoClangFormat.cmake index e4f6c3cb8a4..fb5e78d9f55 100644 --- a/cmake/modules/AutoClangFormat.cmake +++ b/cmake/modules/AutoClangFormat.cmake @@ -21,11 +21,11 @@ add_custom_target(format-cpp-files COMMAND find ${DIRS_TO_FORMAT_CPP} ${FIND_TO_FORMAT_CPP}) # -# Use clang-format-14 for code format +# Use clang-format for code format # add_custom_target(format-cpp COMMAND find ${DIRS_TO_FORMAT_CPP} ${FIND_TO_FORMAT_CPP} | - xargs -P ${CPU_COUNT} clang-format-14 -style=file -i) + xargs -P ${CPU_COUNT} clang-format-18 -style=file -i) # # Use simple python script for fixing C like boxed comments diff --git a/dev/pylint_check.py b/dev/pylint_check.py index 96e78a2393d..4d2b9bba7c6 100755 --- a/dev/pylint_check.py +++ b/dev/pylint_check.py @@ -132,7 +132,7 @@ def expand_paths(): """Build a list of all python files to process by going through 'paths_to_lint'""" paths = [] - for (path, is_recursive) in paths_to_lint: + for path, is_recursive in paths_to_lint: # Make sure all hard-coded paths point to .py files if path.is_file(): if path.suffix.lower() != ".py": diff --git a/dev/submit_slurm.py b/dev/submit_slurm.py index fe6ef4b9ab5..f372f787e45 100755 --- a/dev/submit_slurm.py +++ b/dev/submit_slurm.py @@ -188,7 +188,7 @@ def get_resource_estimates(filepath): mem_bytes = float(match.groupdict()["mem_bytes"]) time_minutes = time_sec / 60 - mem_mb = mem_bytes / (1024 ** 2) + mem_mb = mem_bytes / (1024**2) return time_minutes, mem_mb diff --git a/dev/vtr_gdb_pretty_printers.py b/dev/vtr_gdb_pretty_printers.py index 86e2e14074d..3f4b7a951b3 100644 --- a/dev/vtr_gdb_pretty_printers.py +++ b/dev/vtr_gdb_pretty_printers.py @@ -7,8 +7,10 @@ https://docs.verilogtorouting.org/en/latest/dev/developing#vtr-pretty-printers """ + import re + # VTR related class VtrStrongIdPrinter: def __init__(self, val, typename="vtr::StrongId"): diff --git a/doc/_doxygen/vpr.dox b/doc/_doxygen/vpr.dox index 5d2933b5295..79e58955469 100644 --- a/doc/_doxygen/vpr.dox +++ b/doc/_doxygen/vpr.dox @@ -6,7 +6,7 @@ EXTRACT_ALL = YES EXTRACT_PRIVATE = YES EXTRACT_STATIC = YES WARN_IF_UNDOCUMENTED = NO -INPUT = ../../vpr +INPUT = ../../vpr ../../libs/libarchfpga/ RECURSIVE = YES GENERATE_HTML = NO GENERATE_LATEX = NO diff --git a/doc/src/api/vpr/mapping.rst b/doc/src/api/vpr/mapping.rst index ef573d0e973..f46436e1897 100644 --- a/doc/src/api/vpr/mapping.rst +++ b/doc/src/api/vpr/mapping.rst @@ -1,7 +1,7 @@ =============== Netlist mapping =============== -As shown in the previous section, there are multiple levels of abstraction (multiple netlists) in VPR which are the ClusteredNetlist and the AtomNetlist. To fully use these netlists, we provide some functions to map between them. +As shown in the previous section, there are multiple levels of abstraction (multiple netlists) in VPR which are the ClusteredNetlist and the AtomNetlist. To fully use these netlists, we provide some functions to map between them. In this section, we will state how to map between the atom and clustered netlists. @@ -16,11 +16,11 @@ To get the block Id of a cluster in the ClusteredNetlist from the block Id of on .. code-block:: cpp - ClusterBlockId clb_index = g_vpr_ctx.atom().lookup.atom_clb(atom_blk_id); + ClusterBlockId clb_index = g_vpr_ctx.atom().lookup().atom_clb(atom_blk_id); * Using re_cluster_util.h helper functions - + .. code-block:: cpp ClusterBlockId clb_index = atom_to_cluster(atom_blk_id); @@ -53,7 +53,7 @@ To get the net Id in the ClusteredNetlist from its Id in the AtomNetlist, use At .. code-block:: cpp - ClusterNetId clb_net = g_vpr_ctx.atom().lookup.clb_net(atom_net); + ClusterNetId clb_net = g_vpr_ctx.atom().lookup().clb_net(atom_net); Cluster net Id to Atom net Id @@ -62,4 +62,4 @@ To get the net Id in the AtomNetlist from its Id in the ClusteredNetlist, use At .. code-block:: cpp - ClusterNetId atom_net = g_vpr_ctx.atom().lookup.atom_net(clb_net); + ClusterNetId atom_net = g_vpr_ctx.atom().lookup().atom_net(clb_net); diff --git a/doc/src/api/vtrutil/index.rst b/doc/src/api/vtrutil/index.rst index 6d44b381a2a..84dc4ede829 100644 --- a/doc/src/api/vtrutil/index.rst +++ b/doc/src/api/vtrutil/index.rst @@ -11,4 +11,5 @@ VTRUTIL API container_utils logging geometry + parallel other diff --git a/doc/src/api/vtrutil/parallel.rst b/doc/src/api/vtrutil/parallel.rst new file mode 100644 index 00000000000..a8f9b9bbfa0 --- /dev/null +++ b/doc/src/api/vtrutil/parallel.rst @@ -0,0 +1,13 @@ +===== +Parallel +===== + +vtr_thread_pool +------------- +.. doxygenfile:: vtr_thread_pool.h + :project: vtr + :sections: briefdescription detaileddescription func innernamespace enum + +.. doxygenclass:: vtr::thread_pool + :project: vtr + :members: diff --git a/doc/src/arch/reference.rst b/doc/src/arch/reference.rst index b8fccc6579a..681a6607818 100644 --- a/doc/src/arch/reference.rst +++ b/doc/src/arch/reference.rst @@ -849,7 +849,7 @@ Each tile type is specified with the ```` tag withing the ```` tag. Tile ~~~~ -.. arch:tag:: +.. arch:tag:: A tile refers to a placeable element within an FPGA architecture and describes its physical compositions on the grid. The following attributes are applicable to each tile. diff --git a/doc/src/dev/run_ci_manual/run_workflow.png b/doc/src/dev/run_ci_manual/run_workflow.png new file mode 100644 index 00000000000..ba6c9a54afd Binary files /dev/null and b/doc/src/dev/run_ci_manual/run_workflow.png differ diff --git a/doc/src/dev/run_ci_manual/select_actions.png b/doc/src/dev/run_ci_manual/select_actions.png new file mode 100644 index 00000000000..444ec464932 Binary files /dev/null and b/doc/src/dev/run_ci_manual/select_actions.png differ diff --git a/doc/src/dev/run_ci_manual/select_workflow.png b/doc/src/dev/run_ci_manual/select_workflow.png new file mode 100644 index 00000000000..42f8c5a8b36 Binary files /dev/null and b/doc/src/dev/run_ci_manual/select_workflow.png differ diff --git a/doc/src/parmys/quickstart.rst b/doc/src/parmys/quickstart.rst index eea5b3edb5b..11a8c527609 100644 --- a/doc/src/parmys/quickstart.rst +++ b/doc/src/parmys/quickstart.rst @@ -37,8 +37,8 @@ To build the VTR flow with the Parmys front-end you may use the VTR Makefile wra .. note:: - Compiling the VTR flow with the ``-DYOSYS_F4PGA_PLUGINS=ON`` flag is required to build and install Yosys SystemVerilog and UHDM plugins. - Using this compile flag, the `Yosys-F4PGA-Plugins `_ and `Surelog `_ repositories are cloned in the ``$VTR_ROOT/libs/EXTERNAL`` directory and then will be compiled and added as external plugins to the Parmys front-end. + Compiling the VTR flow with the ``-DSynlig_SystemVerilog=ON`` flag is required to build and install Synlig SystemVerilog and UHDM plugins. + Using this compile flag, the `Synlig_SystemVerilog `_ repository is cloned and installed in the ``$VTR_ROOT/build/bin`` directory and then will be compiled and added as external tool to the Parmys front-end. Basic Usage ----------- diff --git a/doc/src/quickstart/index.rst b/doc/src/quickstart/index.rst index 0621ae0cd81..242079bef99 100644 --- a/doc/src/quickstart/index.rst +++ b/doc/src/quickstart/index.rst @@ -24,12 +24,18 @@ If you cloned the repository, you will need to set up the git submodules (if you > git submodule init > git submodule update -VTR requires several system packages and Python packages to build and run the flow. You can install the required system packages using the following command (this works on Ubuntu 18.04, 20.04 and 22.04, but you may require different packages on other Linux distributions). Our CI testing is on Ubuntu 22.04, so that is the best tested platform and recommended for development. +VTR requires several system packages and Python packages to build and run the flow. Ubuntu users can install the required system packages using the following command (this works on Ubuntu 18.04, 20.04, 22.04 and 24.04, but you may require different packages on other Linux distributions). Our CI testing is on Ubuntu 24.04, so that is the best tested platform and recommended for development. .. code-block:: bash > ./install_apt_packages.sh +Fedora and RHEL users may use the following command to install the required system packages. + +.. code-block:: bash + + > ./install_dnf_packages.sh + Then, to install the required Python packages (optionally within a new Python virtual environment): .. code-block:: bash diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index c33d4352fef..f21ee85f1eb 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -89,6 +89,8 @@ VPR runs all stages of (pack, place, route, and analysis) if none of :option:`-- as such, the :option:`--pack` and :option:`--place` options should not be set when this option is set. This flow requires that the device has a fixed size and some of the primitive blocks are fixed somewhere on the device grid. + .. seealso:: See :ref:`analytical_placement_options` for the options for this flow. + .. seealso:: See :ref:`Fixed FPGA Grid Layout ` and :option:`--device` for how to fix the device size. .. seealso:: See :ref:`VPR Placement Constraints ` for how to fix primitive blocks in a design to the device grid. @@ -377,7 +379,15 @@ Use the options below to override this default naming behaviour. .. seealso:: :ref:`Routing Resource XML File `. -.. option:: --read_vpr_constraints ::...: +.. option:: --read_rr_edge_override + + Reads a file that overrides the intrinsic delay of specific edges in RR graph. + + This option should be used with both :option:`--read_rr_graph` and :option:`--write_rr_graph`. When used this way, + VPR reads the RR graph, updates the delays of selected edges using :option:`--read_rr_edge_override`, + and writes the updated RR graph. The modified RR graph can then be used in later VPR runs. + +.. option:: --read_vpr_constraints Reads the :ref:`VPR constraints ` that the flow must respect from the specified XML file. @@ -408,6 +418,50 @@ Use the options below to override this default naming behaviour. Prefix for output files +.. option:: --read_flat_place + + Reads a file containing the locations of each atom on the FPGA. + This is used by the packer to better cluster atoms together. + + The flat placement file (which often ends in ``.fplace``) is a text file + where each line describes the location of an atom. Each line in the flat + placement file should have the following syntax: + + .. code-block:: none + + + + For example: + + .. code-block:: none + + n523 6 8 0 0 3 + n522 6 8 0 0 5 + n520 6 8 0 0 2 + n518 6 8 0 0 16 + + The position of the atom on the FPGA is given by 3 floating point values + (``x``, ``y``, ``layer``). We allow for the positions of atom to be not + quite legal (ok to be off-grid) since this flat placement will be fed into + the packer and placer, which will snap the positions to grid locations. By + allowing for off-grid positions, the packer can better trade-off where to + move atom blocks if they cannot be placed at the given position. + For 2D FPGA architectures, the ``layer`` should be 0. + + The ``sub_tile`` is a clustered placement construct: which cluster-level + location at a given (x, y, layer) should these atoms go at (relevant when + multiple clusters can be stacked there). A sub-tile of -1 may be used when + the sub-tile of an atom is unkown (allowing the packing algorithm to choose + any sub-tile at the given (x, y, layer) location). + + The ``site_idx`` is an optional index into a linearized list of primitive + locations within a cluster-level block which may be used as a hint to + reconstruct clusters. + + .. warning:: + + This interface is currently experimental and under active development. + .. option:: --write_flat_place Writes the post-placement locations of each atom into a flat placement file. @@ -611,7 +665,7 @@ For people not working on CAD, you can probably leave all the options to their d .. note:: - If a pin utilization target is unspecified it defaults to 1.0 (i.e. 100% utilization). + If some pin utilizations are specified, ``auto`` mode is turned off and the utilization target for any unspecified pin types defaults to 1.0 (i.e. 100% utilization). For example: @@ -830,55 +884,9 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe **Default:** ``0.0`` -.. _dusty_sa_options: -Setting any of the following 5 options selects :ref:`Dusty's annealing schedule ` . - -.. option:: --alpha_min - - The minimum (starting) update factor (alpha) used. - Ranges between 0 and alpha_max. - - **Default:** ``0.2`` - -.. option:: --alpha_max - - The maximum (stopping) update factor (alpha) used after which simulated annealing will complete. - Ranges between alpha_min and 1. - - **Default:** ``0.9`` - -.. option:: --alpha_decay - - The rate at which alpha will approach 1: alpha(n) = 1 - (1 - alpha(n-1)) * alpha_decay - Ranges between 0 and 1. - - **Default:** ``0.7`` - -.. option:: --anneal_success_min - - The minimum success ratio after which the temperature will reset to maintain the target success ratio. - Ranges between 0 and anneal_success_target. - - **Default:** ``0.1`` - -.. option:: --anneal_success_target - - The temperature after each reset is selected to keep this target success ratio. - Ranges between anneal_success_target and 1. - - **Default:** ``0.25`` - -.. option:: --place_cost_exp - - Wiring cost is divided by the average channel width over a net's bounding box - taken to this exponent. Only impacts devices with different channel widths in - different directions or regions. - - **Default:** ``1`` - .. option:: --RL_agent_placement {on | off} - Uses a Reinforcement Learning (RL) agent in choosing the appropiate move type in placement. + Uses a Reinforcement Learning (RL) agent in choosing the appropriate move type in placement. It activates the RL agent placement instead of using a fixed probability for each move type. **Default:** ``on`` @@ -907,7 +915,7 @@ Setting any of the following 5 options selects :ref:`Dusty's annealing schedule Controls how quickly the agent's memory decays. Values between [0., 1.] specify the fraction of weight in the exponentially weighted reward average applied to moves - which occured greater than moves_per_temp moves ago. Values < 0 cause the + which occurred greater than moves_per_temp moves ago. Values < 0 cause the unweighted reward sample average to be used (all samples are weighted equally) **Default:** ``0.05`` @@ -926,6 +934,15 @@ Setting any of the following 5 options selects :ref:`Dusty's annealing schedule **Default:** ``move_block_type`` +.. option:: --place_quench_only {on | off} + + If this option is set to ``on``, the placement will skip the annealing phase and only perform the placement quench. + This option is useful when the the quality of initial placement is good enough and there is no need to perform the + annealing phase. + + **Default:** ``off`` + + .. option:: --placer_debug_block .. note:: This option is likely only of interest to developers debugging the placement algorithm @@ -1023,7 +1040,7 @@ The following options are only valid when the placement engine is in timing-driv .. option:: --place_delay_model_reducer {min, max, median, arithmean, geomean} - When calculating delta delays for the placment delay model how are multiple values combined? + When calculating delta delays for the placement delay model how are multiple values combined? **Default:** ``min`` @@ -1056,7 +1073,7 @@ The following options are only valid when the placement engine is in timing-driv .. option:: --place_tsu_abs_margin - Specifies an absolute offest added to cell setup times used by the placer. + Specifies an absolute offset added to cell setup times used by the placer. This effectively controls whether the placer should try to achieve extra margin on setup paths. For example a value of 500e-12 corresponds to requesting an extra 500ps of setup margin. @@ -1064,7 +1081,7 @@ The following options are only valid when the placement engine is in timing-driv .. option:: --post_place_timing_report - Name of the post-placement timing report file to generate (not generated if unspecfied). + Name of the post-placement timing report file to generate (not generated if unspecified). .. _noc_placement_options: @@ -1163,6 +1180,114 @@ The following options are only used when FPGA device and netlist contain a NoC r **Default:** ``vpr_noc_placement_output.txt`` + +.. _analytical_placement_options: + +Analytical Placement Options +^^^^^^^^^^^^^^^ +Instead of Packing atoms into clusters and placing the clusters into valid tile +sites on the FPGA, Analytical Placement uses analytical techniques to place atoms +on the FPGA device by relaxing the constraints on where they can be placed. This +atom-level placement is then legalized into a clustered placement and passed into +the router in VPR. + +Analytical Placement is generally split into three stages: + +* Global Placement: Uses analytical techniques to place atoms on the FPGA grid. + +* Full Legalization: Legalizes a flat (atom) placement into legal clusters placed on the FPGA grid. + +* Detailed Placement: While keeping the clusters legal, performs optimizations on the clustered placement. + +.. warning:: + + Analytical Placement is experimental and under active development. + +.. option:: --ap_analytical_solver {qp-hybrid | lp-b2b} + + Controls which Analytical Solver the Global Placer will use in the AP Flow. + The Analytical Solver solves for a placement which optimizes some objective + function, ignorant of the FPGA legality constraints. This provides a "lower- + bound" solution. The Global Placer will legalize this solution and feed it + back to the analytical solver to make its solution more legal. + + * ``qp-hybrid`` Solves for a placement that minimizes the quadratic HPWL of + the flat placement using a hybrid clique/star net model (as described in + FastPlace :cite:`Viswanathan2005_FastPlace`). + Uses the legalized solution as anchor-points to pull the solution to a + more legal solution (similar to the approach from SimPL :cite:`Kim2013_SimPL`). + + * ``lp-b2b`` Solves for a placement that minimizes the linear HPWL of the + flat placement using the Bound2Bound net model (as described in Kraftwerk2 :cite:`Spindler2008_Kraftwerk2`). + Uses the legalized solution as anchor-points to pull the solution to a + more legal solution (similar to the approach from SimPL :cite:`Kim2013_SimPL`). + + **Default:** ``lp-b2b`` + +.. option:: --ap_partial_legalizer {bipartitioning | flow-based} + + Controls which Partial Legalizer the Global Placer will use in the AP Flow. + The Partial Legalizer legalizes a placement generated by an Analytical Solver. + It is used within the Global Placer to guide the solver to a more legal + solution. + + * ``bipartitioning`` Creates minimum windows around over-dense regions of + the device bi-partitions the atoms in these windows such that the region + is no longer over-dense and the atoms are in tiles that they can be placed + into. + + * ``flow-based`` Flows atoms from regions that are overfilled to regions that + are underfilled. + + **Default:** ``bipartitioning`` + +.. option:: --ap_full_legalizer {naive | appack} + + Controls which Full Legalizer to use in the AP Flow. + + * ``naive`` Use a Naive Full Legalizer which will try to create clusters exactly where their atoms are placed. + + * ``appack`` Use APPack, which takes the Packer in VPR and uses the flat atom placement to create better clusters. + + **Default:** ``appack`` + +.. option:: --ap_detailed_placer {none | annealer} + + Controls which Detailed Placer to use in the AP Flow. + + * ``none`` Do not use any Detailed Placer. + + * ``annealer`` Use the Annealer from the Placement stage as a Detailed Placer. This will use the same Placer Options from the Place stage to configure the annealer. + + **Default:** ``annealer`` + +.. option:: --ap_timing_tradeoff + + Controls the trade-off between wirelength (HPWL) and delay minimization in the AP flow. + + A value of 0.0 makes the AP flow focus completely on wirelength minimization, + while a value of 1.0 makes the AP flow focus completely on timing optimization. + + **Default:** ``0.5`` + +.. option:: --ap_verbosity + + Controls the verbosity of the AP flow output. + Larger values produce more detailed output, which may be useful for + debugging the algorithms in the AP flow. + + * ``1 <= verbosity < 10`` Print standard, stage-level messages. This will + print messages at the GP, FL, or DP level. + + * ``10 <= verbosity < 20`` Print more detailed messages of what is happening + within stages. For example, show high-level information on the legalization + iterations within the Global Placer. + + * ``20 <= verbosity`` Print very detailed messages on intra-stage algorithms. + + **Default:** ``1`` + + .. _router_options: Router Options @@ -1179,7 +1304,7 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout This means that during the routing stage, all nets, both intra- and inter-cluster, are routed directly from one primitive pin to another primitive pin. This increases routing time but can improve routing quality by re-arranging LUT inputs and exposing additional optimization opportunities in architectures with local intra-cluster routing that is not a full crossbar. - **Default:** ``OFF` + **Default:** ``off`` .. option:: --max_router_iterations diff --git a/doc/src/vpr/file_formats.rst b/doc/src/vpr/file_formats.rst index dc76e2ff5ea..32fbb0dfc93 100644 --- a/doc/src/vpr/file_formats.rst +++ b/doc/src/vpr/file_formats.rst @@ -1100,6 +1100,28 @@ To aid in handling large graphs, rr_graph files can also be :ref:`saved in - + @@ -78,7 +78,10 @@ An ```` tag is used to add an atom that must be constrained to the par :req_param name_pattern: The name of the atom. -The ``name_pattern`` can be the exact name of the atom from the input atom netlist that was passed to VPR. It can also be a regular expression, in which case VPR will add all atoms from the netlist which have a portion of their name matching the regular expression to the partition. For example, if a module contains primitives named in the pattern of "alu[0]", "alu[1]", and "alu[2]", the regular expression "alu*" would add all of the primitives from that module. +The ``name_pattern`` can either be the exact name of an atom from the input atom netlist passed to VPR, or a regular expression pattern matching one or more atom names. VPR first searches the netlist for an exact match. If no exact match is found, it then assumes that the given name is a regex pattern and searches for atoms whose names match the pattern. + +For example, to add all atoms ``alu[0]``, ``alu[1]``, and ``alu[2]`` to the partition ``Part0``, the user can use ``alu.*`` as the ``name_pattern`` in the ```` tag. + Region ^^^^^^ @@ -124,12 +127,3 @@ It is strongly recommended that different partitions do not overlap. The packing blocks and the number of physical blocks in a region to decide pack atoms inside a partition more aggressively when there are not enough resources in a partition. Overlapping partitions causes some physical blocks to be counted in more than one partition. - - - - - - - - - diff --git a/doc/src/vtr/run_vtr_flow.rst b/doc/src/vtr/run_vtr_flow.rst index 97782ec7a77..f61bdf3226e 100644 --- a/doc/src/vtr/run_vtr_flow.rst +++ b/doc/src/vtr/run_vtr_flow.rst @@ -73,15 +73,15 @@ The parser for these runs is considered the Yosys conventional Verilog/SystemVer .. code-block:: bash - # Using the Yosys-SystemVerilog plugin if installed, otherwise the Yosys conventional Verilog parser + # Using the Synlig System_Verilog tool if installed, otherwise the Yosys conventional Verilog parser ./run_vtr_flow -parser system-verilog # Using the Surelog plugin if installed, otherwise failure on the unsupported file type ./run_vtr_flow -parser surelog Running the default VTR flow using the Parmys standalone front-end. -The Yosys HDL parser is considered as Yosys-SystemVerilog plugin (i.e., ``read_systemverilog``) and Yosys UHDM plugin (i.e., ``read_uhdm``), respectively. -Utilizing Yosys plugins requires passing the ``-DYOSYS_F4PGA_PLUGINS=ON`` compile flag to build and install the plugins for the Parmys front-end. +The Synlig HDL parser supports the (i.e., ``read_systemverilog``) and (i.e., ``read_uhdm``) commands. It utilizes Surelog for SystemVerilog 2017 processing and Yosys for synthesis. +Enable Synlig tool with the ``-DSYNLIG_SYSTEMVERILOG=ON`` compile flag for the Parmys front-end. .. code-block:: bash diff --git a/doc/src/z_references.bib b/doc/src/z_references.bib index 8822890713d..fc064f2c433 100644 --- a/doc/src/z_references.bib +++ b/doc/src/z_references.bib @@ -436,3 +436,46 @@ @inproceedings{kosar2024parallel booktitle={The 23rd International Conference on Field-Programmable Technology}, year={2024} } + +@ARTICLE{Viswanathan2005_FastPlace, + author={Viswanathan, N. and Chu, C.C.-N.}, + journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + title={{FastPlace}: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model}, + year={2005}, + volume={24}, + number={5}, + month=may, + pages={722-733}, + keywords={Clustering algorithms;Partitioning algorithms;Algorithm design and analysis;Integrated circuit interconnections;Large-scale systems;Minimization;Delay;Simulated annealing;Iterative algorithms;Acceleration;Analytical placement;computer-aided design;net models;standard cell placement}, + doi={10.1109/TCAD.2005.846365} +} + +@article{Kim2013_SimPL, + author = {Kim, Myung-Chul and Lee, Dong-Jin and Markov, Igor L.}, + journal = {Commun. ACM}, + title = {{SimPL}: an algorithm for placing {VLSI} circuits}, + year = {2013}, + issue_date = {June 2013}, + publisher = {Association for Computing Machinery}, + address = {New York, NY, USA}, + volume = {56}, + number = {6}, + issn = {0001-0782}, + doi = {10.1145/2461256.2461279}, + month = jun, + pages = {105–113}, + numpages = {9} +} + +@ARTICLE{Spindler2008_Kraftwerk2, + author={Spindler, Peter and Schlichtmann, Ulf and Johannes, Frank M.}, + journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + title={Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model}, + year={2008}, + volume={27}, + number={8}, + month=aug, + pages={1398-1411}, + keywords={Cost function;Central Processing Unit;Runtime;Quality control;Convergence;Computational efficiency;Integrated circuit synthesis;Stochastic processes;Circuit simulation;Bound2Bound;force-directed;half-perimeter wirelength (HPWL);Kraftwerk2;quadratic placement;Kraftwerk2;force-directed;quadratic placement;Bound2Bound;HPWL}, + doi={10.1109/TCAD.2008.925783} +} diff --git a/install_apt_packages.sh b/install_apt_packages.sh index 17d9aa49425..ede554a197c 100755 --- a/install_apt_packages.sh +++ b/install_apt_packages.sh @@ -36,6 +36,7 @@ sudo apt-get install -y \ libboost-system-dev \ libboost-python-dev \ libboost-filesystem-dev \ + default-jre \ zlib1g-dev # Required to build the documentation diff --git a/install_dnf_packages.sh b/install_dnf_packages.sh new file mode 100755 index 00000000000..b2a23fb7da5 --- /dev/null +++ b/install_dnf_packages.sh @@ -0,0 +1,52 @@ +sudo dnf upgrade --refresh + +# Base packages to compile and run basic regression tests +sudo dnf install -y \ + make \ + cmake \ + automake \ + gcc \ + gcc-c++ \ + kernel-devel \ + pkg-config \ + bison \ + flex \ + python3-devel \ + tbb-devel +# Required for graphics +sudo dnf install -y \ + gtk3-devel \ + libX11 + +# Required for parmys front-end from https://github.com/YosysHQ/yosys +sudo dnf install -y \ + make \ + automake \ + gcc \ + gcc-c++ \ + kernel-devel \ + clang \ + bison \ + flex \ + readline-devel \ + gawk \ + tcl-devel \ + libffi-devel \ + git \ + graphviz \ + python-xdot \ + pkg-config \ + python3-devel \ + boost-system \ + boost-python3 \ + boost-filesystem \ + zlib-ng-devel + +# Required to build the documentation +sudo dnf install -y \ + python3-sphinx \ + python-sphinx-doc + +# Required to run the analytical placement flow +sudo dnf install -y \ + eigen3-devel \ No newline at end of file diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index a60c48958eb..f70f150fbe2 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -1,4 +1,5 @@ include(ExternalProject) +include(ProcessorCount) #Manually synchronized external libraries add_subdirectory(libpugixml) @@ -9,8 +10,17 @@ add_subdirectory(libsdcparse) add_subdirectory(libblifparse) add_subdirectory(libtatum) add_subdirectory(libcatch2) +#add_subdirectory(synlig) #add_subdirectory(parmys) +#Proc numbers +ProcessorCount(PROCESSOR_COUNT) + +if(PROCESSOR_COUNT EQUAL 0) + # Fallback to 1 if the processor count cannot be determined + set(PROCESSOR_COUNT 1) +endif() + #VPR_USE_SERVER is initialized in the root CMakeLists #compile sockpp only if server mode is enabled if (VPR_USE_SERVER) @@ -27,8 +37,9 @@ endif () # The VTR root CMakeFile initializes the WITH_PARMYS if (${WITH_PARMYS}) - # building Surelog and UHDM in a custom target to avoid any target conflict with VTR targets - if (${YOSYS_F4PGA_PLUGINS}) + + if (${SYNLIG_SYSTEMVERILOG}) + set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog) set(SURELOG_BINARY_DIR ${SURELOG_SOURCE_DIR}/build) set(YOSYS_F4PGA_PLUGINS_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-f4pga-plugins) @@ -62,74 +73,90 @@ if (${WITH_PARMYS}) LOG_OUTPUT_ON_FAILURE ON # dependency - DEPENDS yosys + DEPENDS yosys ) - ExternalProject_Add(f4pga-plugins - # root directory for the Yosys-F4PGA-Plugins project - PREFIX "f4pga-plugins" - - GIT_REPOSITORY https://github.com/chipsalliance/yosys-f4pga-plugins.git - GIT_TAG v1.20230808 - GIT_PROGRESS TRUE - GIT_SHALLOW TRUE - - # setting source, build and install directories - SOURCE_DIR "${YOSYS_F4PGA_PLUGINS_SOURCE_DIR}" - BUILD_IN_SOURCE FALSE - INSTALL_DIR "" - - INSTALL_COMMAND "" - CONFIGURE_COMMAND "" - BUILD_COMMAND ${MAKE_PROGRAM} -C ${YOSYS_F4PGA_PLUGINS_SOURCE_DIR} - PATH=${CMAKE_BINARY_DIR}/bin/:$ENV{PATH} - UHDM_INSTALL_DIR=${CMAKE_BINARY_DIR} - BUILD_DIR=${CMAKE_CURRENT_BINARY_DIR}/f4pga-plugins/$(NAME) # NAME will be resolved by yosys-f4pga-plugins Make - YOSYS_PATH=${CMAKE_BINARY_DIR} - install -j${CUSTOM_BUILD_PARALLEL_LEVEL} - - # redirect logs to a logfile - LOG_BUILD ON - LOG_UPDATE ON - LOG_INSTALL ON - LOG_CONFIGURE OFF - LOG_OUTPUT_ON_FAILURE ON + # Synlig integration (manages Surelog and UHDM internally) + + # Synlig integration (manages Surelog and UHDM internally) + set(SYNLIG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/synlig) + + # Clone Synlig repository and ensure submodules are synced before building + ExternalProject_Add(synlig + PREFIX "synlig" + + # Clone the Synlig repository + GIT_REPOSITORY https://github.com/chipsalliance/synlig.git + GIT_TAG main + GIT_PROGRESS TRUE + GIT_SHALLOW TRUE + + # Set source and build directories + SOURCE_DIR "${SYNLIG_SOURCE_DIR}" + BUILD_IN_SOURCE FALSE + INSTALL_DIR " " + + # Sync submodules after cloning + + + UPDATE_COMMAND git submodule update --init --recursive third_party/surelog + WORKING_DIRECTORY ${SYNLIG_SOURCE_DIR} + + BUILD_COMMAND ${MAKE_PROGRAM} -C ${SYNLIG_SOURCE_DIR} install DESTDIR=${CMAKE_BINARY_DIR}/bin/synlig_install -j${PROCESSOR_COUNT} + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + + # Pass necessary paths and set environment variables + CMAKE_CACHE_ARGS + "-DCMAKE_BUILD_TYPE:STRING=Release" + "-DSURELOG_PATH=${CMAKE_BINARY_DIR}/surelog" + "-DYOSYS_PATH=${CMAKE_BINARY_DIR}/yosys" + "-DUHDM_INSTALL_DIR=${CMAKE_BINARY_DIR}" + "-DBUILD_DIR=${CMAKE_BINARY_DIR}/synlig-build" + "-DEXPORT_PATH=${CMAKE_BINARY_DIR}/synlig_install/usr/local/bin:$ENV{PATH}" + + LOG_BUILD ON + LOG_UPDATE ON + LOG_INSTALL ON + LOG_CONFIGURE OFF + LOG_OUTPUT_ON_FAILURE ON + + # Ensure dependencies like Yosys are built first + DEPENDS yosys # Ensure submodule sync runs before synlig build + ) - # dependency - DEPENDS surelog yosys - ) endif () - endif () -if (${VTR_ENABLE_CAPNPROTO}) - # Override default policy for capnproto (CMake policy version 3.1) - # Enable new IPO variables - set(CMAKE_POLICY_DEFAULT_CMP0069 NEW) - # Enable option overrides via variables - set(CMAKE_POLICY_DEFAULT_CMP0077 NEW) + if (${VTR_ENABLE_CAPNPROTO}) + # Override default policy for capnproto (CMake policy version 3.1) + # Enable new IPO variables + set(CMAKE_POLICY_DEFAULT_CMP0069 NEW) - # Re-enable CXX extensions for capnproto. - set(CMAKE_CXX_EXTENSIONS ON) + # Enable option overrides via variables + set(CMAKE_POLICY_DEFAULT_CMP0077 NEW) - # Disable capnproto tests - set(BUILD_TESTING OFF) + # Re-enable CXX extensions for capnproto. + set(CMAKE_CXX_EXTENSIONS ON) - #Since capnproto is an externally developed library/tool, we suppress all compiler warnings - CHECK_CXX_COMPILER_FLAG("-w" CXX_COMPILER_SUPPORTS_-w) - if (CXX_COMPILER_SUPPORTS_-w) - add_compile_options("-w") - endif () + # Disable capnproto tests + set(BUILD_TESTING OFF) - add_subdirectory(capnproto EXCLUDE_FROM_ALL) + #Since capnproto is an externally developed library/tool, we suppress all compiler warnings + CHECK_CXX_COMPILER_FLAG("-w" CXX_COMPILER_SUPPORTS_-w) + if (CXX_COMPILER_SUPPORTS_-w) + add_compile_options("-w") + endif () - #Some capnproto kj headers (e.g. filesystem.h) generate warnings, treat them as system headers to suppress warnings - #We suppress them here since we include the capnproto sub-tree as is and do not modify its CMakeLists.txts - target_include_directories(kj SYSTEM INTERFACE - $ - $ - ) + add_subdirectory(capnproto EXCLUDE_FROM_ALL) + + #Some capnproto kj headers (e.g. filesystem.h) generate warnings, treat them as system headers to suppress warnings + #We suppress them here since we include the capnproto sub-tree as is and do not modify its CMakeLists.txts + target_include_directories(kj SYSTEM INTERFACE + $ + $ + ) endif () # Some catch2 headers generate warnings, so treat them as system headers to suppress warnings diff --git a/libs/EXTERNAL/libcatch2 b/libs/EXTERNAL/libcatch2 index fa43b77429b..76f70b1403d 160000 --- a/libs/EXTERNAL/libcatch2 +++ b/libs/EXTERNAL/libcatch2 @@ -1 +1 @@ -Subproject commit fa43b77429ba76c462b1898d6cd2f2d7a9416b14 +Subproject commit 76f70b1403dbc0781216f49e20e45b71f7eccdd8 diff --git a/libs/EXTERNAL/libezgl/include/ezgl/point.hpp b/libs/EXTERNAL/libezgl/include/ezgl/point.hpp index ee8d5d17b90..a0d39279f19 100644 --- a/libs/EXTERNAL/libezgl/include/ezgl/point.hpp +++ b/libs/EXTERNAL/libezgl/include/ezgl/point.hpp @@ -36,7 +36,7 @@ class point2d { /** * Create a point at the given x and y position. */ - point2d(double x_coord, double y_coord) : x(x_coord), y(y_coord) + point2d(double x_coord, double y_coord) noexcept : x(x_coord), y(y_coord) { } diff --git a/libs/EXTERNAL/libezgl/include/ezgl/rectangle.hpp b/libs/EXTERNAL/libezgl/include/ezgl/rectangle.hpp index 70138eae392..a454e7f107c 100644 --- a/libs/EXTERNAL/libezgl/include/ezgl/rectangle.hpp +++ b/libs/EXTERNAL/libezgl/include/ezgl/rectangle.hpp @@ -33,7 +33,7 @@ class rectangle { /** * Default constructor: Create a zero-sized rectangle at {0,0}. */ - rectangle() : m_first({0, 0}), m_second({0, 0}) + rectangle() noexcept : m_first({0, 0}), m_second({0, 0}) { } diff --git a/libs/EXTERNAL/libtatum/libtatum/tatum/util/tatum_strong_id.hpp b/libs/EXTERNAL/libtatum/libtatum/tatum/util/tatum_strong_id.hpp index 71f5b7a874e..28340d53885 100644 --- a/libs/EXTERNAL/libtatum/libtatum/tatum/util/tatum_strong_id.hpp +++ b/libs/EXTERNAL/libtatum/libtatum/tatum/util/tatum_strong_id.hpp @@ -161,7 +161,7 @@ template bool operator!=(const StrongId& lhs, const StrongId& rhs); template -bool operator<(const StrongId& lhs, const StrongId& rhs); +bool operator<(const StrongId& lhs, const StrongId& rhs) noexcept; //Class template definition with default template parameters @@ -198,7 +198,7 @@ class StrongId { // after the function name (i.e. <>) friend bool operator== <>(const StrongId& lhs, const StrongId& rhs); friend bool operator!= <>(const StrongId& lhs, const StrongId& rhs); - friend bool operator< <>(const StrongId& lhs, const StrongId& rhs); + friend bool operator< <>(const StrongId& lhs, const StrongId& rhs) noexcept; private: T id_; }; @@ -215,7 +215,7 @@ bool operator!=(const StrongId& lhs, const StrongId -bool operator<(const StrongId& lhs, const StrongId& rhs) { +bool operator<(const StrongId& lhs, const StrongId& rhs) noexcept { return lhs.id_ < rhs.id_; } diff --git a/libs/EXTERNAL/sockpp b/libs/EXTERNAL/sockpp index 5388c4b5659..599f750c8b6 160000 --- a/libs/EXTERNAL/sockpp +++ b/libs/EXTERNAL/sockpp @@ -1 +1 @@ -Subproject commit 5388c4b5659e99a86bc906dd6ac2eef66f1dd51e +Subproject commit 599f750c8b6532950d4bb43b2b756700e41dbae9 diff --git a/libs/libarchfpga/CMakeLists.txt b/libs/libarchfpga/CMakeLists.txt index 65e9096cd37..283ddb55959 100644 --- a/libs/libarchfpga/CMakeLists.txt +++ b/libs/libarchfpga/CMakeLists.txt @@ -26,6 +26,8 @@ target_link_libraries(libarchfpga if(${VTR_ENABLE_CAPNPROTO}) target_link_libraries(libarchfpga libvtrcapnproto) + find_package(ZLIB REQUIRED) + target_link_libraries(libarchfpga ZLIB::ZLIB) target_compile_definitions(libarchfpga PRIVATE VTR_ENABLE_CAPNPROTO) endif() diff --git a/libs/libarchfpga/src/arch_check.cpp b/libs/libarchfpga/src/arch_check.cpp index c8fb00299c4..5360d6e4c02 100644 --- a/libs/libarchfpga/src/arch_check.cpp +++ b/libs/libarchfpga/src/arch_check.cpp @@ -32,7 +32,7 @@ bool check_model_clocks(t_model* model, const char* file, uint32_t line) { bool check_model_combinational_sinks(const t_model* model, const char* file, uint32_t line) { //Outputs should have no combinational sinks for (t_model_ports* port = model->outputs; port != nullptr; port = port->next) { - if (port->combinational_sink_ports.size() != 0) { + if (!port->combinational_sink_ports.empty()) { archfpga_throw(file, line, "Model '%s' output port '%s' can not have combinational sink ports", model->name, port->name); @@ -114,9 +114,9 @@ void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t_sub_ti } for (auto pin_map : pin_direct_map) { - auto block_port = get_port_by_pin(logical_block, pin_map.first.pin); + const t_port* block_port = logical_block->get_port_by_pin(pin_map.first.pin); - auto sub_tile_port = get_port_by_pin(sub_tile, pin_map.second.pin); + const t_physical_tile_port* sub_tile_port = sub_tile->get_port_by_pin(pin_map.second.pin); VTR_ASSERT(block_port != nullptr); VTR_ASSERT(sub_tile_port != nullptr); diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index 80b21308e9f..f991ebf30ad 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -851,6 +851,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { mem_pb_type->model = nullptr; mem_pb_type->modes[0].num_interconnect = mem_pb_type->num_ports * num_pb; + VTR_ASSERT(mem_pb_type->modes[0].num_interconnect > 0); mem_pb_type->modes[0].interconnect = new t_interconnect[mem_pb_type->modes[0].num_interconnect]; for (i = 0; i < mem_pb_type->modes[0].num_interconnect; i++) { diff --git a/libs/libarchfpga/src/arch_util.h b/libs/libarchfpga/src/arch_util.h index c39cf77b94f..fb251bffe10 100644 --- a/libs/libarchfpga/src/arch_util.h +++ b/libs/libarchfpga/src/arch_util.h @@ -23,8 +23,8 @@ class InstPort { InstPort() = default; InstPort(const std::string& str); - std::string instance_name() const { return instance_.name; } - std::string port_name() const { return port_.name; } + const std::string& instance_name() const { return instance_.name; } + const std::string& port_name() const { return port_.name; } int instance_low_index() const { return instance_.low_idx; } int instance_high_index() const { return instance_.high_idx; } @@ -40,7 +40,7 @@ class InstPort { private: struct name_index { - std::string name = ""; + std::string name; int low_idx = UNSPECIFIED; int high_idx = UNSPECIFIED; }; diff --git a/libs/libarchfpga/src/cad_types.h b/libs/libarchfpga/src/cad_types.h index 5ab46816b99..af0aac9a994 100644 --- a/libs/libarchfpga/src/cad_types.h +++ b/libs/libarchfpga/src/cad_types.h @@ -104,7 +104,7 @@ struct t_pack_patterns { std::vector> chain_root_pins; // default constructor initializing to an invalid pack pattern - t_pack_patterns() { + t_pack_patterns() noexcept { name = nullptr; index = -1; root_block = nullptr; @@ -126,7 +126,7 @@ struct t_cluster_placement_primitive { t_pb_graph_node* pb_graph_node; bool valid; float base_cost; /* cost independent of current status of packing */ - float incremental_cost; /* cost dependant on current status of packing */ + float incremental_cost; /* cost dependent on current status of packing */ }; #endif diff --git a/libs/libarchfpga/src/device_grid.h b/libs/libarchfpga/src/device_grid.h index 8e1332559ed..c04e3f8dc4e 100644 --- a/libs/libarchfpga/src/device_grid.h +++ b/libs/libarchfpga/src/device_grid.h @@ -19,8 +19,11 @@ struct t_grid_tile { const t_metadata_dict* meta = nullptr; }; -///@brief DeviceGrid represents the FPGA fabric. It is used to get information about different layers and tiles. -// TODO: All of the function that use helper functions of this class should pass the layer_num to the functions, and the default value of layer_num should be deleted eventually. +//TODO: All of the functions that use helper functions of this class should pass the layer_num to the functions, and the default value of layer_num should be deleted eventually. +/** + * @class DeviceGrid + * @brief Represents the FPGA fabric. It is used to get information about different layers and tiles. + */ class DeviceGrid { public: DeviceGrid() = default; @@ -77,6 +80,10 @@ class DeviceGrid { inline int get_height_offset(const t_physical_tile_loc& tile_loc) const { return grid_[tile_loc.layer_num][tile_loc.x][tile_loc.y].height_offset; } + ///@brief Returns true if the given location is the root location (bottom left corner) of a tile. + inline bool is_root_location(const t_physical_tile_loc& tile_loc) const { + return get_width_offset(tile_loc) == 0 && get_height_offset(tile_loc) == 0; + } ///@brief Returns a rectangle which represents the bounding box of the tile at the given location. inline vtr::Rect get_tile_bb(const t_physical_tile_loc& tile_loc) const { diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp index 4fb52c415f2..edceeb748fb 100644 --- a/libs/libarchfpga/src/echo_arch.cpp +++ b/libs/libarchfpga/src/echo_arch.cpp @@ -297,7 +297,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { int num_layers = (int)layout.layers.size(); if (num_layers > 1) { fprintf(Echo, "\t\t\t\ttype unidir mux_name for between two dice connections: %s\n", - arch->switches[seg.arch_opin_between_dice_switch].name.c_str()); + arch->switches[seg.arch_inter_die_switch].name.c_str()); } } } else { //Should be bidir diff --git a/libs/libarchfpga/src/parse_switchblocks.cpp b/libs/libarchfpga/src/parse_switchblocks.cpp index 1e8908713bf..3ef9ec8e155 100644 --- a/libs/libarchfpga/src/parse_switchblocks.cpp +++ b/libs/libarchfpga/src/parse_switchblocks.cpp @@ -4,19 +4,15 @@ * * * A large chunk of this file is dedicated to helping parse the initial switchblock - * specificaiton in the XML arch file, providing error checking, etc. + * specification in the XML arch file, providing error checking, etc. * * Another large chunk of this file is dedicated to parsing the actual formulas * specified by the switch block permutation functions into their numeric counterparts. */ -#include +#include #include -#include #include -#include -#include -#include #include "vtr_assert.h" #include "vtr_util.h" @@ -26,9 +22,7 @@ #include "arch_error.h" -#include "read_xml_util.h" #include "arch_util.h" -#include "arch_types.h" #include "physical_types.h" #include "parse_switchblocks.h" diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index 3bdabaee2a7..9b72cb95758 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -71,6 +71,42 @@ bool t_rr_switch_inf::configurable() const { return switch_type_is_configurable(type()); } +bool t_rr_switch_inf::operator==(const t_rr_switch_inf& other) const { + return R == other.R + && Cin == other.Cin + && Cout == other.Cout + && Cinternal == other.Cinternal + && Tdel == other.Tdel + && mux_trans_size == other.mux_trans_size + && buf_size == other.buf_size + && power_buffer_type == other.power_buffer_type + && power_buffer_size == other.power_buffer_size + && intra_tile == other.intra_tile + && type() == other.type(); +} + +std::size_t t_rr_switch_inf::Hasher::operator()(const t_rr_switch_inf& s) const { + std::size_t hash_val = 0; + + auto hash_combine = [&hash_val](auto&& val) { + hash_val ^= std::hash>{}(val) + 0x9e3779b9 + (hash_val << 6) + (hash_val >> 2); + }; + + hash_combine(s.R); + hash_combine(s.Cin); + hash_combine(s.Cout); + hash_combine(s.Cinternal); + hash_combine(s.Tdel); + hash_combine(s.mux_trans_size); + hash_combine(s.buf_size); + hash_combine(static_cast(s.power_buffer_type)); + hash_combine(s.power_buffer_size); + hash_combine(s.intra_tile); + hash_combine(static_cast(s.type())); + + return hash_val; +} + void t_rr_switch_inf::set_type(SwitchType type_val) { type_ = type_val; } @@ -136,6 +172,56 @@ bool t_physical_tile_type::is_empty() const { return name == std::string(EMPTY_BLOCK_NAME); } +int t_physical_tile_type::find_pin(std::string_view port_name, int pin_index_in_port) const { + int ipin = OPEN; + int port_base_ipin = 0; + int num_port_pins = OPEN; + int pin_offset = 0; + + bool port_found = false; + for (const t_sub_tile& sub_tile : sub_tiles) { + for (const t_physical_tile_port& port : sub_tile.ports) { + if (port_name == port.name) { + port_found = true; + num_port_pins = port.num_pins; + break; + } + + port_base_ipin += port.num_pins; + } + + if (port_found) { + break; + } + + port_base_ipin = 0; + pin_offset += sub_tile.num_phy_pins; + } + + if (num_port_pins != OPEN) { + VTR_ASSERT(pin_index_in_port < num_port_pins); + + ipin = port_base_ipin + pin_index_in_port + pin_offset; + } + + return ipin; +} + +int t_physical_tile_type::find_pin_class(std::string_view port_name, int pin_index_in_port, e_pin_type pin_type) const { + int iclass = OPEN; + + int ipin = find_pin(port_name, pin_index_in_port); + + if (ipin != OPEN) { + iclass = pin_class[ipin]; + + if (iclass != OPEN) { + VTR_ASSERT(class_inf[iclass].type == pin_type); + } + } + return iclass; +} + /* * t_logical_block_type */ @@ -144,6 +230,28 @@ bool t_logical_block_type::is_empty() const { return name == std::string(EMPTY_BLOCK_NAME); } +const t_port* t_logical_block_type::get_port(std::string_view port_name) const { + for (int i = 0; i < pb_type->num_ports; i++) { + auto port = pb_type->ports[i]; + if (port_name == port.name) { + return &pb_type->ports[port.index]; + } + } + + return nullptr; +} + +const t_port* t_logical_block_type::get_port_by_pin(int pin) const { + for (int i = 0; i < pb_type->num_ports; i++) { + const t_port& port = pb_type->ports[i]; + if (pin >= port.absolute_first_pin_index && pin < port.absolute_first_pin_index + port.num_pins) { + return &pb_type->ports[port.index]; + } + } + + return nullptr; +} + /** * t_pb_graph_node */ @@ -220,7 +328,7 @@ std::string t_pb_graph_pin::to_string(const bool full_description) const { return pin_string; } -/** +/* * t_pb_graph_edge */ @@ -253,3 +361,39 @@ bool t_pb_graph_edge::belongs_to_pattern(int pattern_index) const { // return false otherwise return false; } + +/* + * t_sub_tile + */ + +int t_sub_tile::total_num_internal_pins() const { + int num_pins = 0; + + for (t_logical_block_type_ptr eq_site : equivalent_sites) { + num_pins += (int)eq_site->pin_logical_num_to_pb_pin_mapping.size(); + } + + num_pins *= capacity.total(); + + return num_pins; +} + +const t_physical_tile_port* t_sub_tile::get_port(std::string_view port_name) { + for (const t_physical_tile_port& port : ports) { + if (port_name == port.name) { + return &ports[port.index]; + } + } + + return nullptr; +} + +const t_physical_tile_port* t_sub_tile::get_port_by_pin(int pin) const { + for (const t_physical_tile_port& port : ports) { + if (pin >= port.absolute_first_pin_index && pin < port.absolute_first_pin_index + port.num_pins) { + return &ports[port.index]; + } + } + + return nullptr; +} diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index a0351076127..19a625db601 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -24,8 +24,7 @@ * Authors: Jason Luu and Kenneth Kent */ -#ifndef PHYSICAL_TYPES_H -#define PHYSICAL_TYPES_H +#pragma once #include #include @@ -97,7 +96,7 @@ enum class e_sb_type; // Metadata value storage. class t_metadata_value { public: - explicit t_metadata_value(vtr::interned_string v) + explicit t_metadata_value(vtr::interned_string v) noexcept : value_(v) {} explicit t_metadata_value(const t_metadata_value& o) noexcept : value_(o.value_) {} @@ -546,10 +545,13 @@ struct t_port_power { bool reverse_scaled; /* Scale by (1-prob) */ }; -//The type of Fc specification +/** + * @enum e_fc_type + * @brief The type of Fc specification + */ enum class e_fc_type { - IN, //The fc specification for an input pin - OUT //The fc specification for an output pin + IN, /**< Fc specification for an input pin. */ + OUT /**< Fc specification for an output pin. */ }; //The value type of the Fc specification @@ -709,12 +711,6 @@ struct t_physical_tile_type { * tile_block_pin_directs_map[logical block index][logical block pin] -> physical tile pin */ std::unordered_map>> tile_block_pin_directs_map; - /* Returns the indices of pins that contain a clock for this physical logic block */ - std::vector get_clock_pins_indices() const; - - // Returns the sub tile location of the physical tile given an input pin - int get_sub_tile_loc_from_pin(int pin_num) const; - // TODO: Remove is_input_type / is_output_type as part of // https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1193 @@ -724,8 +720,21 @@ struct t_physical_tile_type { // Does this t_physical_tile_type contain an outpad? bool is_output_type = false; - // Is this t_physical_tile_type an empty type? + public: // Function members + ///@brief Returns the indices of pins that contain a clock for this physical logic block + std::vector get_clock_pins_indices() const; + + ///@brief Returns the sub tile location of the physical tile given an input pin + int get_sub_tile_loc_from_pin(int pin_num) const; + + ///@brief Is this t_physical_tile_type an empty type? bool is_empty() const; + + ///@brief Returns the relative pin index within a sub tile that corresponds to the pin within the given port and its index in the port + int find_pin(std::string_view port_name, int pin_index_in_port) const; + + ///@brief Returns the pin class associated with the specified pin_index_in_port within the port port_name on type + int find_pin_class(std::string_view port_name, int pin_index_in_port, e_pin_type pin_type) const; }; /* Holds the capacity range of a certain sub_tile block within the parent physical tile type. @@ -801,6 +810,19 @@ struct t_sub_tile { int num_phy_pins = 0; int index = -1; + + public: + int total_num_internal_pins() const; + + /** + * @brief Returns the physical tile port given the port name and the corresponding sub tile + */ + const t_physical_tile_port* get_port(std::string_view port_name); + + /** + * @brief Returns the physical tile port given the pin name and the corresponding sub tile + */ + const t_physical_tile_port* get_port_by_pin(int pin) const; }; /** A logical pin defines the pin index of a logical block type (i.e. a top level PB type) @@ -955,6 +977,17 @@ struct t_logical_block_type { // Is this t_logical_block_type empty? bool is_empty() const; + + public: + /** + * @brief Returns the logical block port given the port name and the corresponding logical block type + */ + const t_port* get_port(std::string_view port_name) const; + + /** + * @brief Returns the logical block port given the pin name and the corresponding logical block type + */ + const t_port* get_port_by_pin(int pin) const; }; /************************************************************************************************* @@ -1253,8 +1286,8 @@ struct t_pin_to_pin_annotation { * flat_site_index : Index of this primitive site within its primitive type within this cluster type. * Values are in [0...total_primitive_count-1], e.g. if there are 10 ALMs per cluster, 2 FFS * and 2 LUTs per ALM, then flat site indices for FFs would run from 0 to 19, and flat site - indices for LUTs would run from 0 to 19. This member is only used by nodes corresponding - to primitive sites. It is used when reconstructing clusters from a flat placement file. + * indices for LUTs would run from 0 to 19. This member is only used by nodes corresponding + * to primitive sites. It is used when reconstructing clusters from a flat placement file. * illegal_modes : vector containing illegal modes that result in conflicts during routing */ class t_pb_graph_node { @@ -1308,7 +1341,7 @@ class t_pb_graph_node { int total_pb_pins; /* only valid for top-level */ - void* temp_scratch_pad; /* temporary data, useful for keeping track of things when traversing data structure */ + void* temp_scratch_pad; /* temporary data, useful for keeping track of things when traversing data structure */ int* input_pin_class_size; /* Stores the number of pins that belong to a particular input pin class */ int num_input_pin_class; /* number of input pin classes that this pb_graph_node has */ @@ -1318,7 +1351,6 @@ class t_pb_graph_node { int total_primitive_count; /* total number of this primitive type in the cluster */ int flat_site_index; /* index of this primitive within sites of its type in this cluster */ - /* Interconnect instances for this pb * Only used for power */ @@ -1538,6 +1570,7 @@ enum e_directionality { UNI_DIRECTIONAL, BI_DIRECTIONAL }; + /* X_AXIS: Data that describes an x-directed wire segment (CHANX) * * Y_AXIS: Data that describes an y-directed wire segment (CHANY) * * BOTH_AXIS: Data that can be applied to both x-directed and y-directed wire segment */ @@ -1560,115 +1593,186 @@ enum class SegResType { NUM_RES_TYPES }; -constexpr std::array(SegResType::NUM_RES_TYPES)> RES_TYPE_STRING = {{"GCLK", "GENERAL"}}; //String versions of segment resource types +/// String versions of segment resource types +constexpr std::array(SegResType::NUM_RES_TYPES)> RES_TYPE_STRING{"GCLK", "GENERAL"}; +/// Defines the type of switch block used in FPGA routing. enum e_switch_block_type { + /// If the type is SUBSET, I use a Xilinx-like switch block where track i in one channel always + /// connects to track i in other channels. SUBSET, + + /// If type is WILTON, I use a switch block where track i + /// does not always connect to track i in other channels. + /// See Steve Wilton, PhD Thesis, University of Toronto, 1996. WILTON, + + /// The UNIVERSAL switch block is from Y. W. Chang et al, TODAES, Jan. 1996, pp. 80 - 101. UNIVERSAL, + + /// The FULL switch block type allows for complete connectivity between tracks. FULL, + + /// A CUSTOM switch block has also been added which allows a user to describe custom permutation functions and connection patterns. + /// See comment at top of SRC/route/build_switchblocks.c CUSTOM }; -typedef enum e_switch_block_type t_switch_block_type; + enum e_Fc_type { ABSOLUTE, FRACTIONAL }; -/* Lists all the important information about a certain segment type. Only * - * used if the route_type is DETAILED. [0 .. det_routing_arch.num_segment] * - * name: the name of this segment * - * frequency: ratio of tracks which are of this segment type. * - * length: Length (in clbs) of the segment. * - * arch_wire_switch: Index of the switch type that connects other wires * - * *to* this segment. Note that this index is in relation * - * to the switches from the architecture file, not the * - * expanded list of switches that is built at the end of * - * build_rr_graph. * - * arch_opin_switch: Index of the switch type that connects output pins * - * (OPINs) *to* this segment. Note that this index is in * - * relation to the switches from the architecture file, * - * not the expanded list of switches that is built * - * at the end of build_rr_graph * - * @param arch_wire_switch_dec: Same as arch_wire_switch but used only for * - * decremental tracks if it is specified in the * - * architecture file. If -1, this value was not set in * - * the architecture file and arch_wire_switch should be * - * used for "DEC_DIR" wire segments. * - * @param arch_opin_switch_dec: Same as arch_opin_switch but used only for * - * decremental tracks if it is specified in the * - * architecture file. If -1, this value was not set in * - * the architecture file and arch_opin_switch should be * - * used for "DEC_DIR" wire segments. * - * @param arch_opin_between_dice_switch: Index of the switch type that * - * connects output pins (OPINs) *to* this segment from * - * *another die (layer)*. Note that this index is in * - * relation to the switches from the architecture file, * - * not the expanded list of switches that is built at * - * the end of build_rr_graph * - * * - * frac_cb: The fraction of logic blocks along its length to which this * - * segment can connect. (i.e. internal population). * - * frac_sb: The fraction of the length + 1 switch blocks along the segment * - * to which the segment can connect. Segments that aren't long * - * lines must connect to at least two switch boxes. * - * parallel_axis: Defines what axis the segment is parallel to. See * - * e_parallel_axis comments for more details on the values. * - * Cmetal: Capacitance of a routing track, per unit logic block length. * - * Rmetal: Resistance of a routing track, per unit logic block length. * - * (UDSD by AY) drivers: How do signals driving a routing track connect to * - * the track? * - * seg_index: The index of the segment as stored in the appropriate Segs list* - * Upon loading the architecture, we use this field to keep track * - * the segment's index in the unified segment_inf vector. This is * - * useful when building the rr_graph for different Y & X channels * - * in terms of track distribution and segment type. * - * res_type: Determines the routing network to which the segment belongs. * - * Possible values are: * - * - GENERAL: The segment is part of the general routing * - * resources. * - * - GCLK: The segment is part of the global routing network. * - * For backward compatibility, this attribute is optional. If not * - * specified, the resource type for the segment is considered to * - * be GENERAL. * - * meta: Table storing extra arbitrary metadata attributes. * - * - * - * New added parameters for bend wires: * - * isbend: This segment is bend or not * - * bend: The bend type of the segment, "-"-0, "U"-1, "D"-2 * - * For example: bend pattern <- - U ->; corresponding bend: [0,0,1,0] * - * part_len: Divide the segment into several parts based on bend position. * - * For example: length-5 bend segment: <- - U ->; * - * Corresponding part_len: [3,2] */ +/** + * @brief Lists all the important information about a certain segment type. Only + * used if the route_type is DETAILED. [0 .. det_routing_arch.num_segment] + */ struct t_segment_inf { + /** + * @brief The name of the segment type + */ std::string name; + + /** + * @brief ratio of tracks which are of this segment type. + */ int frequency; + + /** + * @brief Length (in clbs) of the segment. + */ int length; + + /** + * @brief Index of the switch type that connects other wires to this segment. + * Note that this index is in relation to the switches from the architecture file, + * not the expanded list of switches that is built at the end of build_rr_graph. + */ short arch_wire_switch; + + /** + * @brief Index of the switch type that connects output pins to this segment. + * Note that this index is in relation to the switches from the architecture file, + * not the expanded list of switches that is built at the end of build_rr_graph. + */ short arch_opin_switch; + + /** + * @brief Same as arch_wire_switch but used only for decremental tracks if it is + * specified in the architecture file. If -1, this value was not set in the + * architecture file and arch_wire_switch should be used for "DEC_DIR" wire segments. + */ short arch_wire_switch_dec = -1; + + /** + * @brief Same as arch_opin_switch but used only for decremental tracks if + * it is specified in the architecture file. If -1, this value was not set in + * the architecture file and arch_opin_switch should be used for "DEC_DIR" wire segments. + */ short arch_opin_switch_dec = -1; - short arch_opin_between_dice_switch = -1; + + /** + * @brief Index of the switch type that connects output pins (OPINs) to this + * segment from another die (layer). Note that this index is in relation to + * the switches from the architecture file, not the expanded list of switches + * that is built at the end of build_rr_graph. + */ + short arch_inter_die_switch = -1; + + /** + * @brief The fraction of logic blocks along its length to which this segment can connect. + * (i.e. internal population). + */ float frac_cb; + + /** + * @brief The fraction of the length + 1 switch blocks along the segment to which the segment can connect. + * Segments that aren't long lines must connect to at least two switch boxes. + */ float frac_sb; + bool longline; + + /** + * @brief The resistance of a routing track, per unit logic block length. */ float Rmetal; + + /** + * @brief The capacitance of a routing track, per unit logic block length. */ float Cmetal; + enum e_directionality directionality; + + /** + * @brief Defines what axis the segment is parallel to. See e_parallel_axis + * comments for more details on the values. + */ enum e_parallel_axis parallel_axis; + + /** + * @brief A vector of booleans indicating whether the segment can connect to a logic block. + */ std::vector cb; + + /** + * @brief A vector of booleans indicating whether the segment can connect to a switch block. + */ std::vector sb; - bool isbend; + + /** + * @brief This segment is bend or not + */ + bool isbend; + + /** + * @brief The bend type of the segment, "-"-0, "U"-1, "D"-2 + * For example: bend pattern <- - U ->; corresponding bend: [0,0,1,0] + */ std::vector bend; + + /** + * @brief Divide the segment into several parts based on bend position. + * For example: length-5 bend segment: <- - U ->; + * Corresponding part_len: [3,2] + */ std::vector part_len; + + /** + * @brief The index of the segment as stored in the appropriate Segs list. + * Upon loading the architecture, we use this field to keep track of the + * segment's index in the unified segment_inf vector. This is useful when + * building the rr_graph for different Y & X channels in terms of track + * distribution and segment type. + */ int seg_index; + + /** + * @brief Determines the routing network to which the segment belongs. + * Possible values are: + * - GENERAL: The segment is part of the general routing resources. + * - GCLK: The segment is part of the global routing network. + * For backward compatibility, this attribute is optional. If not specified, + * the resource type for the segment is considered to be GENERAL. + */ enum SegResType res_type = SegResType::GENERAL; - //float Cmetal_per_m; /* Wire capacitance (per meter) */ }; inline bool operator==(const t_segment_inf& a, const t_segment_inf& b) { - return a.name == b.name && a.frequency == b.frequency && a.length == b.length && a.arch_wire_switch == b.arch_wire_switch && a.arch_opin_switch == b.arch_opin_switch && a.arch_opin_between_dice_switch == b.arch_opin_between_dice_switch && a.frac_cb == b.frac_cb && a.frac_sb == b.frac_sb && a.longline == b.longline && a.Rmetal == b.Rmetal && a.Cmetal == b.Cmetal && a.directionality == b.directionality && a.parallel_axis == b.parallel_axis && a.cb == b.cb && a.sb == b.sb; + return a.name == b.name + && a.frequency == b.frequency + && a.length == b.length + && a.arch_wire_switch == b.arch_wire_switch + && a.arch_opin_switch == b.arch_opin_switch + && a.arch_inter_die_switch == b.arch_inter_die_switch + && a.frac_cb == b.frac_cb + && a.frac_sb == b.frac_sb + && a.longline == b.longline + && a.Rmetal == b.Rmetal + && a.Cmetal == b.Cmetal + && a.directionality == b.directionality + && a.parallel_axis == b.parallel_axis + && a.cb == b.cb + && a.sb == b.sb; } /*provide hashing for t_segment_inf to enable the use of many std containers. @@ -1840,16 +1944,28 @@ struct t_rr_switch_inf { bool intra_tile = false; public: - //Returns the type of switch + /// Returns the type of switch SwitchType type() const; - //Returns true if this switch type isolates its input and output into - //separate DC-connected subcircuits + /// Returns true if this switch type isolates its input and output into + /// separate DC-connected subcircuits bool buffered() const; - //Returns true if this switch type is configurable + /// Returns true if this switch type is configurable bool configurable() const; + bool operator==(const t_rr_switch_inf& other) const; + + /** + * @brief Functor for computing a hash value for t_rr_switch_inf. + * + * This custom hasher enables the use of t_rr_switch_inf objects as keys + * in unordered containers such as std::unordered_map or std::unordered_set. + */ + struct Hasher { + std::size_t operator()(const t_rr_switch_inf& s) const; + }; + public: void set_type(SwitchType type_val); @@ -1973,7 +2089,7 @@ struct t_switchblock_inf { /* We can also define a region to apply this SB to all locations falls into this region using regular expression in the architecture file*/ t_sb_loc_spec reg_x; t_sb_loc_spec reg_y; - + t_permutation_map permutation_map; /* map holding the permutation functions attributed to this switchblock */ std::vector wireconns; /* list of wire types/groups this SB will connect */ @@ -2062,8 +2178,6 @@ struct t_noc_inf { std::string noc_router_tile_name; }; - - /* Detailed routing architecture */ struct t_arch { /** Stores unique strings used as key and values in tags, @@ -2143,11 +2257,11 @@ struct t_arch { std::vector ipin_cblock_switch_name; std::vector grid_layouts; //Set of potential device layouts - + //the layout that is chosen to be used with command line options //It is used to generate custom SB for a specific locations within the device //If the layout is not specified in the command line options, this variable will be set to "auto" - std::string device_layout; + std::string device_layout; std::vector vib_grid_layouts; @@ -2160,5 +2274,3 @@ struct t_arch { //bool is_vib_arch = false; std::vector vib_infs; }; - -#endif diff --git a/libs/libarchfpga/src/physical_types_util.cpp b/libs/libarchfpga/src/physical_types_util.cpp index 2256f81d66c..2ecc7fbd41c 100644 --- a/libs/libarchfpga/src/physical_types_util.cpp +++ b/libs/libarchfpga/src/physical_types_util.cpp @@ -154,7 +154,7 @@ static std::tuple get_pin_index_for_inst(t_physical_til pin_inst_num = (pin_physical_num - pin_offset) % pins_per_inst; } else { int pin_offset = get_sub_tile_inst_physical_pin_num_offset(type, sub_tile, sub_tile_cap); - int pins_per_inst = get_total_num_sub_tile_internal_pins(sub_tile) / sub_tile->capacity.total(); + int pins_per_inst = sub_tile->total_num_internal_pins() / sub_tile->capacity.total(); pin_inst_num = (pin_physical_num - pin_offset) % pins_per_inst; } @@ -225,7 +225,7 @@ static int get_sub_tile_physical_pin_num_offset(t_physical_tile_type_ptr physica if (&tmp_sub_tile == curr_sub_tile) break; else - offset += get_total_num_sub_tile_internal_pins(&tmp_sub_tile); + offset += tmp_sub_tile.total_num_internal_pins(); } return offset; @@ -235,7 +235,7 @@ static int get_sub_tile_inst_physical_pin_num_offset(t_physical_tile_type_ptr ph const t_sub_tile* curr_sub_tile, const int curr_relative_cap) { int offset = get_sub_tile_physical_pin_num_offset(physical_tile, curr_sub_tile); - int sub_tile_inst_num_pins = get_total_num_sub_tile_internal_pins(curr_sub_tile) / curr_sub_tile->capacity.total(); + int sub_tile_inst_num_pins = curr_sub_tile->total_num_internal_pins() / curr_sub_tile->capacity.total(); offset += (curr_relative_cap * sub_tile_inst_num_pins); @@ -563,57 +563,6 @@ int get_max_num_pins(t_logical_block_type_ptr logical_block) { return max_num_pins; } -//Returns the pin class associated with the specified pin_index_in_port within the port port_name on type -int find_pin_class(t_physical_tile_type_ptr type, std::string port_name, int pin_index_in_port, e_pin_type pin_type) { - int iclass = OPEN; - - int ipin = find_pin(type, port_name, pin_index_in_port); - - if (ipin != OPEN) { - iclass = type->pin_class[ipin]; - - if (iclass != OPEN) { - VTR_ASSERT(type->class_inf[iclass].type == pin_type); - } - } - return iclass; -} - -int find_pin(t_physical_tile_type_ptr type, std::string port_name, int pin_index_in_port) { - int ipin = OPEN; - int port_base_ipin = 0; - int num_pins = OPEN; - int pin_offset = 0; - - bool port_found = false; - for (const auto& sub_tile : type->sub_tiles) { - for (const auto& port : sub_tile.ports) { - if (0 == strcmp(port.name, port_name.c_str())) { - port_found = true; - num_pins = port.num_pins; - break; - } - - port_base_ipin += port.num_pins; - } - - if (port_found) { - break; - } - - port_base_ipin = 0; - pin_offset += sub_tile.num_phy_pins; - } - - if (num_pins != OPEN) { - VTR_ASSERT(pin_index_in_port < num_pins); - - ipin = port_base_ipin + pin_index_in_port + pin_offset; - } - - return ipin; -} - std::pair get_capacity_location_from_physical_pin(t_physical_tile_type_ptr physical_tile, int pin) { int pins_to_remove = 0; for (const auto& sub_tile : physical_tile->sub_tiles) { @@ -638,7 +587,7 @@ std::pair get_capacity_location_from_physical_pin(t_physical_tile_type int get_physical_pin_from_capacity_location(t_physical_tile_type_ptr physical_tile, int relative_pin, int capacity_location) { int pins_to_add = 0; - for (auto sub_tile : physical_tile->sub_tiles) { + for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) { auto capacity = sub_tile.capacity; int rel_capacity = capacity_location - capacity.low; int num_inst_pins = sub_tile.num_phy_pins / capacity.total(); @@ -841,52 +790,6 @@ std::vector block_type_class_index_to_pin_names(t_physical_tile_typ return pin_names; } -const t_physical_tile_port* get_port_by_name(t_sub_tile* sub_tile, const char* port_name) { - for (auto port : sub_tile->ports) { - if (0 == strcmp(port.name, port_name)) { - return &sub_tile->ports[port.index]; - } - } - - return nullptr; -} - -const t_port* get_port_by_name(t_logical_block_type_ptr type, const char* port_name) { - auto pb_type = type->pb_type; - - for (int i = 0; i < pb_type->num_ports; i++) { - auto port = pb_type->ports[i]; - if (0 == strcmp(port.name, port_name)) { - return &pb_type->ports[port.index]; - } - } - - return nullptr; -} - -const t_physical_tile_port* get_port_by_pin(const t_sub_tile* sub_tile, int pin) { - for (auto port : sub_tile->ports) { - if (pin >= port.absolute_first_pin_index && pin < port.absolute_first_pin_index + port.num_pins) { - return &sub_tile->ports[port.index]; - } - } - - return nullptr; -} - -const t_port* get_port_by_pin(t_logical_block_type_ptr type, int pin) { - auto pb_type = type->pb_type; - - for (int i = 0; i < pb_type->num_ports; i++) { - auto port = pb_type->ports[i]; - if (pin >= port.absolute_first_pin_index && pin < port.absolute_first_pin_index + port.num_pins) { - return &pb_type->ports[port.index]; - } - } - - return nullptr; -} - /* Access information related to pin classes */ /** get information given class physical num **/ @@ -1009,7 +912,7 @@ std::tuple get_sub_tile_from_pin_physical_num(t_physical int pin_offset = total_pin_counts; for (auto& sub_tile : physical_tile->sub_tiles) { - int sub_tile_num_pins = pin_on_tile ? sub_tile.num_phy_pins : get_total_num_sub_tile_internal_pins(&sub_tile); + int sub_tile_num_pins = pin_on_tile ? sub_tile.num_phy_pins : sub_tile.total_num_internal_pins(); total_pin_counts += sub_tile_num_pins; if (physical_num < total_pin_counts) { @@ -1347,15 +1250,6 @@ const t_pb_graph_node* get_pb_graph_node_from_pin_physical_num(t_physical_tile_t return pb_graph_pin->parent_node; } -int get_total_num_sub_tile_internal_pins(const t_sub_tile* sub_tile) { - int num_pins = 0; - for (auto eq_site : sub_tile->equivalent_sites) { - num_pins += (int)eq_site->pin_logical_num_to_pb_pin_mapping.size(); - } - num_pins *= sub_tile->capacity.total(); - return num_pins; -} - int get_tile_pin_max_ptc(t_physical_tile_type_ptr tile, bool is_flat) { if (is_flat) { return tile->num_pins + (int)tile->pin_num_to_pb_pin.size(); @@ -1538,4 +1432,3 @@ std::map get_sink_choking_points(t_physical_tile_type_ptr physical_til return choking_point; } -/* */ diff --git a/libs/libarchfpga/src/physical_types_util.h b/libs/libarchfpga/src/physical_types_util.h index aa7b2617834..a081683faeb 100644 --- a/libs/libarchfpga/src/physical_types_util.h +++ b/libs/libarchfpga/src/physical_types_util.h @@ -1,5 +1,5 @@ -#ifndef PHYSICAL_TYPES_UTIL_H -#define PHYSICAL_TYPES_UTIL_H + +#pragma once #include "physical_types.h" @@ -13,11 +13,11 @@ * functions in this file are the following: * * - physical_tile_type: identifies a placeable tile within * * the device grid. * - * - logical_block_tpye: identifies a clustered block type * + * - logical_block_type: identifies a clustered block type * * within the clb_netlist * * * * All the following utilities are intended to ease the * - * developement to access the above mentioned classes and perform * + * development to access the above mentioned classes and perform * * some required operations with their data. * * * * Please classify such functions in this file * @@ -107,7 +107,7 @@ * * For instance, the following information are required: * - mapping between logical and sub tile pins. - * - mapping between sub tile pins and absoulte physical pin + * - mapping between sub tile pins and absolute physical pin * - capacity instance of the sub tile * * With all the above information we can calculate correctly the connection between the CLK (logical pin) @@ -152,12 +152,12 @@ int get_physical_pin_from_capacity_location(t_physical_tile_type_ptr physical_ti * * Take the above CLOCK TILE example: * - given the CLOCK TILE and the index corresponding to the CLK_1 pin, we want the relative pin - * of one of its sub tiles at a particualr capacity location (i.e. sub tile instance). + * of one of its sub tiles at a particular capacity location (i.e. sub tile instance). * * std::tie(absolute_capacity, relative_pin) = get_capacity_location_from_physical_pin(clock_tile, 3) * * The value returned is (1, 0), where: - * - 1 corresponds to the capacity location (sub tile instance) where the absoulte physical pin index (CLK_1) is connected + * - 1 corresponds to the capacity location (sub tile instance) where the absolute physical pin index (CLK_1) is connected * - 0 corresponds to the relative pin index within the BUFGCTRL sub tile */ std::pair get_capacity_location_from_physical_pin(t_physical_tile_type_ptr physical_tile, int pin); @@ -173,11 +173,6 @@ std::vector block_type_class_index_to_pin_names(t_physical_tile_typ ///@brief Returns the physical tile type matching a given physical tile type name, or nullptr (if not found) t_physical_tile_type_ptr find_tile_type_by_name(const std::string& name, const std::vector& types); -int find_pin_class(t_physical_tile_type_ptr type, std::string port_name, int pin_index_in_port, e_pin_type pin_type); - -///@brief Returns the relative pin index within a sub tile that corresponds to the pin within the given port and its index in the port -int find_pin(t_physical_tile_type_ptr type, std::string port_name, int pin_index_in_port); - ///@brief Returns the maximum number of pins within a logical block int get_max_num_pins(t_logical_block_type_ptr logical_block); @@ -217,7 +212,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_ t_logical_block_type_ptr logical_block); /** * @brief Returns the physical pin index (within 'physical_tile') corresponding to the - * logical index ('pin' of the first instance of 'logical_block' within the physcial tile. + * logical index ('pin' of the first instance of 'logical_block' within the physical tile. * * This function is called before/during placement, when a sub tile index was not yet assigned. * @@ -228,7 +223,7 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile, int pin); /** * @brief Returns the physical pin index (within 'physical_tile') corresponding to the - * logical index ('pin' of the first instance of 'logical_block' within the physcial tile. + * logical index ('pin' of the first instance of 'logical_block' within the physical tile. * This function considers if a given offset is in the range of sub tile capacity * * (First pin index at current sub-tile) (The wanted pin index) @@ -286,26 +281,6 @@ int get_sub_tile_physical_pin(int sub_tile_index, */ t_physical_tile_port find_tile_port_by_name(t_physical_tile_type_ptr type, std::string_view port_name); -/** - * @brief Returns the physical tile port given the port name and the corresponding sub tile - */ -const t_physical_tile_port* get_port_by_name(t_sub_tile* sub_tile, const char* port_name); - -/** - * @brief Returns the logical block port given the port name and the corresponding logical block type - */ -const t_port* get_port_by_name(t_logical_block_type_ptr type, const char* port_name); - -/** - * @brief Returns the physical tile port given the pin name and the corresponding sub tile - */ -const t_physical_tile_port* get_port_by_pin(const t_sub_tile* sub_tile, int pin); - -/** - * @brief Returns the logical block port given the pin name and the corresponding logical block type - */ -const t_port* get_port_by_pin(t_logical_block_type_ptr type, int pin); - /************************************ Access to intra-block resources ************************************/ /* Access information related to pin classes */ @@ -336,12 +311,6 @@ inline bool is_class_on_tile(t_physical_tile_type_ptr physical_tile, int class_p /** * @brief Classes are indexed in a way that the number of classes on the same pb_graph_node is continuous - * @param physical_tile - * @param sub_tile - * @param logical_block - * @param sub_tile_relative_cap - * @param pb_graph_node - * @return */ t_class_range get_pb_graph_node_class_physical_range(t_physical_tile_type_ptr physical_tile, const t_sub_tile* sub_tile, @@ -358,15 +327,11 @@ std::vector get_tile_root_classes(t_physical_tile_type_ptr physical_type); /** * Get the number of all classes, on the tile and inside the cluster. - * @param physical_type - * @return */ t_class_range get_flat_tile_primitive_classes(t_physical_tile_type_ptr physical_type); /** **/ int get_tile_class_max_ptc(t_physical_tile_type_ptr tile, bool is_flat); -/* */ - /* Access information related to pins */ /** get information given pin physical number **/ @@ -434,8 +399,6 @@ int get_edge_sw_arch_idx(t_physical_tile_type_ptr physical_tile, const t_pb_graph_node* get_pb_graph_node_from_pin_physical_num(t_physical_tile_type_ptr physical_type, int pin_physical_num); -int get_total_num_sub_tile_internal_pins(const t_sub_tile* sub_tile); - int get_tile_pin_max_ptc(t_physical_tile_type_ptr tile, bool is_flat); int get_tile_num_internal_pin(t_physical_tile_type_ptr tile); @@ -459,11 +422,6 @@ float get_pin_primitive_comb_delay(t_physical_tile_type_ptr physical_type, /** * @brief This function is used during reachability analysis to check whether two classes should be put in the same group - * @param physical_tile - * @param first_class_ptc_num - * @param second_class_ptc_num - * @param is_flat - * @return */ bool classes_in_same_block(t_physical_tile_type_ptr physical_tile, int first_class_ptc_num, @@ -473,15 +431,8 @@ bool classes_in_same_block(t_physical_tile_type_ptr physical_tile, /** * @brief Given the sink group, identify the pins which can reach both sink_ptc_num and at least one of the sinks, * in the grp. - * @param physical_tile - * @param sink_ptc_num - * @param grp * @return Key is the pin number and value is the number of sinks, including sink_ptc_num, in the grp reachable by the pin */ std::map get_sink_choking_points(t_physical_tile_type_ptr physical_tile, int sink_ptc_num, const std::vector& grp); - -/* */ - -#endif diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index 8737503da3b..50840cbb948 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -5,28 +5,28 @@ #ifdef VTR_ENABLE_CAPNPROTO -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include - -# include "vtr_assert.h" -# include "vtr_digest.h" -# include "vtr_log.h" -# include "vtr_memory.h" -# include "vtr_util.h" - -# include "arch_check.h" -# include "arch_error.h" -# include "arch_util.h" -# include "arch_types.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vtr_assert.h" +#include "vtr_digest.h" +#include "vtr_log.h" +#include "vtr_memory.h" +#include "vtr_util.h" + +#include "arch_check.h" +#include "arch_error.h" +#include "arch_util.h" +#include "arch_types.h" /* * FPGA Interchange Device frontend @@ -1076,7 +1076,7 @@ struct ArchReader { continue; // Check for duplicates - auto is_duplicate = [name](const t_logical_block_type& l)-> bool { return l.name == name; }; + auto is_duplicate = [name](const t_logical_block_type& l) -> bool { return l.name == name; }; VTR_ASSERT(std::find_if(ltypes_.begin(), ltypes_.end(), is_duplicate) == ltypes_.end()); ltype.name = name; diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.h b/libs/libarchfpga/src/read_fpga_interchange_arch.h index c859f97a002..753b44d3010 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.h +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.h @@ -5,12 +5,12 @@ #ifdef VTR_ENABLE_CAPNPROTO -# include "DeviceResources.capnp.h" -# include "LogicalNetlist.capnp.h" -# include "capnp/serialize.h" -# include "capnp/serialize-packed.h" -# include -# include +#include "DeviceResources.capnp.h" +#include "LogicalNetlist.capnp.h" +#include "capnp/serialize.h" +#include "capnp/serialize-packed.h" +#include +#include #endif // VTR_ENABLE_CAPNPROTO diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 9c6d4de6608..5e6c96fbfa0 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -199,7 +199,7 @@ static void ProcessSubTiles(pugi::xml_node Node, * string interment storage. * @param loc_data Points to the location in the architecture file where the parser is reading. * @param pb_idx Used to assign unique values to index_in_logical_block field in -* t_pb_type for all pb_types under a logical block type. + * t_pb_type for all pb_types under a logical block type. */ static void ProcessPb_Type(pugi::xml_node Parent, t_pb_type* pb_type, @@ -258,7 +258,7 @@ static void ProcessMode(pugi::xml_node Parent, * @brief Processes tags. * * @param strings String internment storage used to store strings used -* as keys and values in tags. + * as keys and values in tags. * @param Parent An XML node pointing to the parent tag whose children * are to be parsed. * @param loc_data Points to the location in the architecture file where the parser is reading. @@ -316,7 +316,6 @@ static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data); - static t_grid_def ProcessGridLayout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer); static void ProcessBlockTypeLocs(t_grid_def& grid_def, int die_number, vtr::string_internment& strings, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data); @@ -380,7 +379,6 @@ static void ProcessPower(pugi::xml_node parent, static void ProcessClocks(pugi::xml_node Parent, t_clock_arch* clocks, const pugiutil::loc_data& loc_data); - static void ProcessPb_TypePowerEstMethod(pugi::xml_node Parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data); static void ProcessPb_TypePort_Power(pugi::xml_node Parent, t_port* port, e_power_estimation_method power_method, const pugiutil::loc_data& loc_data); @@ -418,7 +416,7 @@ static void ProcessVib(pugi::xml_node Vib_node, std::vector& PhysicalTileTypes, std::vector& first_stages, const pugiutil::loc_data& loc_data); static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& second_stages, const pugiutil::loc_data& loc_data); // static void ProcessFromOrToTokens(const std::vector Tokens, std::vector& PhysicalTileTypes, std::vector& froms); -void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); +// static void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); /* * @@ -936,7 +934,7 @@ static std::pair ProcessPinString(pugi::xml_node Locations, "No port name is present: %s\n", pin_loc_string); } - auto port = get_port_by_name(type, token.data); + auto port = type->get_port(token.data); if (port == nullptr) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "Port %s for %s could not be found: %s\n", @@ -1911,10 +1909,9 @@ static void ProcessInterconnect(vtr::string_internment& strings, } mode->interconnect[interconnect_idx].annotations = (t_pin_to_pin_annotation*)vtr::calloc(num_annotations, - sizeof(t_pin_to_pin_annotation)); + sizeof(t_pin_to_pin_annotation)); mode->interconnect[interconnect_idx].num_annotations = num_annotations; - int annotation_idx = 0; for (auto annot_child_name : {"delay_constant", "delay_matrix", "C_constant", "C_matrix", "pack_pattern"}) { pugi::xml_node Cur2 = get_first_child(Cur, annot_child_name, loc_data, ReqOpt::OPTIONAL); @@ -1932,7 +1929,7 @@ static void ProcessInterconnect(vtr::string_internment& strings, /* Power */ mode->interconnect[interconnect_idx].interconnect_power = (t_interconnect_power*)vtr::calloc(1, - sizeof(t_interconnect_power)); + sizeof(t_interconnect_power)); mode->interconnect[interconnect_idx].interconnect_power->port_info_initialized = false; /* get next iteration */ @@ -4006,7 +4003,7 @@ static std::vector ProcessSegments(pugi::xml_node Parent, archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), "'%s' is not a valid mux name.\n", tmp); } - Segs[i].arch_opin_between_dice_switch = switch_idx; + Segs[i].arch_inter_die_switch = switch_idx; } /* Get the wire and opin switches, or mux switch if unidir */ @@ -4016,63 +4013,61 @@ static std::vector ProcessSegments(pugi::xml_node Parent, tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); //check if tag is defined in the architecture, otherwise we should look for and - if(tmp){ + if (tmp) { /* Match names */ int switch_idx = find_switch_by_name(switches, tmp); if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), - "'%s' is not a valid mux name.\n", tmp); + "'%s' is not a valid mux name.\n", tmp); } /* Unidir muxes must have the same switch - * for wire and opin fanin since there is - * really only the mux in unidir. */ + * for wire and opin fanin since there is + * really only the mux in unidir. */ Segs[i].arch_wire_switch = switch_idx; Segs[i].arch_opin_switch = switch_idx; - } - else { //if a general mux is not defined, we should look for specific mux for each direction in the architecture file + } else { //if a general mux is not defined, we should look for specific mux for each direction in the architecture file SubElem = get_single_child(Node, "mux_inc", loc_data, ReqOpt::OPTIONAL); tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - if(!tmp){ + if (!tmp) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), - "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified"); - } else{ + "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified"); + } else { /* Match names */ int switch_idx = find_switch_by_name(switches, tmp); if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), - "'%s' is not a valid mux name.\n", tmp); + "'%s' is not a valid mux name.\n", tmp); } /* Unidir muxes must have the same switch - * for wire and opin fanin since there is - * really only the mux in unidir. */ + * for wire and opin fanin since there is + * really only the mux in unidir. */ Segs[i].arch_wire_switch = switch_idx; Segs[i].arch_opin_switch = switch_idx; } SubElem = get_single_child(Node, "mux_dec", loc_data, ReqOpt::OPTIONAL); tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - if(!tmp){ + if (!tmp) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), - "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified"); - } else{ + "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified"); + } else { /* Match names */ int switch_idx = find_switch_by_name(switches, tmp); if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), - "'%s' is not a valid mux name.\n", tmp); + "'%s' is not a valid mux name.\n", tmp); } /* Unidir muxes must have the same switch - * for wire and opin fanin since there is - * really only the mux in unidir. */ + * for wire and opin fanin since there is + * really only the mux in unidir. */ Segs[i].arch_wire_switch_dec = switch_idx; Segs[i].arch_opin_switch_dec = switch_idx; } } - } - else { + } else { VTR_ASSERT(BI_DIRECTIONAL == Segs[i].directionality); SubElem = get_single_child(Node, "wire_switch", loc_data); tmp = get_attribute(SubElem, "name", loc_data).value(); @@ -4197,11 +4192,11 @@ static void ProcessBend(pugi::xml_node Node, std::vector& list, std::vector int tmp_len = 1; int sum_len = 0; - for(size_t i_len = 0; i_len < list.size(); i_len++){ + for (size_t i_len = 0; i_len < list.size(); i_len++) { if (list[i_len] == 0) { tmp_len++; } else if (list[i_len] != 0) { - VTR_ASSERT(tmp_len < (int) list.size()+1); + VTR_ASSERT(tmp_len < (int)list.size() + 1); part_len.push_back(tmp_len); sum_len += tmp_len; tmp_len = 1; @@ -4209,16 +4204,16 @@ static void ProcessBend(pugi::xml_node Node, std::vector& list, std::vector } // add the last clip of segment - if (sum_len < (int) list.size()+1) + if (sum_len < (int)list.size() + 1) part_len.push_back(list.size() + 1 - sum_len); } -static void calculate_custom_SB_locations(const pugiutil::loc_data& loc_data, const pugi::xml_node& SubElem, const int grid_width, const int grid_height, t_switchblock_inf& sb){ +static void calculate_custom_SB_locations(const pugiutil::loc_data& loc_data, const pugi::xml_node& SubElem, const int grid_width, const int grid_height, t_switchblock_inf& sb) { auto startx_attr = get_attribute(SubElem, "startx", loc_data, ReqOpt::OPTIONAL); - auto endx_attr = get_attribute(SubElem, "endx", loc_data, ReqOpt::OPTIONAL); + auto endx_attr = get_attribute(SubElem, "endx", loc_data, ReqOpt::OPTIONAL); auto starty_attr = get_attribute(SubElem, "starty", loc_data, ReqOpt::OPTIONAL); - auto endy_attr = get_attribute(SubElem, "endy", loc_data, ReqOpt::OPTIONAL); + auto endy_attr = get_attribute(SubElem, "endy", loc_data, ReqOpt::OPTIONAL); auto repeatx_attr = get_attribute(SubElem, "repeatx", loc_data, ReqOpt::OPTIONAL); auto repeaty_attr = get_attribute(SubElem, "repeaty", loc_data, ReqOpt::OPTIONAL); @@ -4233,19 +4228,17 @@ static void calculate_custom_SB_locations(const pugiutil::loc_data& loc_data, co vars.set_var_value("W", grid_width); vars.set_var_value("H", grid_height); - sb.reg_x.start = startx_attr.empty() ? 0 : p.parse_formula(startx_attr.value(), vars); sb.reg_y.start = starty_attr.empty() ? 0 : p.parse_formula(starty_attr.value(), vars); sb.reg_x.end = endx_attr.empty() ? (grid_width - 1) : p.parse_formula(endx_attr.value(), vars); - sb.reg_y.end = endy_attr.empty() ? (grid_height -1) : p.parse_formula(endy_attr.value(), vars); + sb.reg_y.end = endy_attr.empty() ? (grid_height - 1) : p.parse_formula(endy_attr.value(), vars); sb.reg_x.repeat = repeatx_attr.empty() ? 0 : p.parse_formula(repeatx_attr.value(), vars); sb.reg_y.repeat = repeaty_attr.empty() ? 0 : p.parse_formula(repeaty_attr.value(), vars); sb.reg_x.incr = incrx_attr.empty() ? 1 : p.parse_formula(incrx_attr.value(), vars); sb.reg_y.incr = incry_attr.empty() ? 1 : p.parse_formula(incry_attr.value(), vars); - } /* Processes the switchblocklist section from the xml architecture file. @@ -4259,10 +4252,10 @@ static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiu /* get the number of switchblocks */ int num_switchblocks = count_children(Parent, "switchblock", loc_data); arch->switchblocks.reserve(num_switchblocks); - + int layout_index = -1; - for(layout_index = 0; layout_index < (int) arch->grid_layouts.size(); layout_index++){ - if(arch->grid_layouts.at(layout_index).name == arch->device_layout){ + for (layout_index = 0; layout_index < (int)arch->grid_layouts.size(); layout_index++) { + if (arch->grid_layouts.at(layout_index).name == arch->device_layout) { //found the used layout break; } @@ -4314,8 +4307,8 @@ static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiu } /* get the switchblock coordinate only if sb.location is set to E_XY_SPECIFIED*/ - if(sb.location == e_sb_location::E_XY_SPECIFIED){ - if (arch->device_layout == "auto"){ + if (sb.location == e_sb_location::E_XY_SPECIFIED) { + if (arch->device_layout == "auto") { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), "Specifying SB locations for auto layout devices are not supported yet!\n"); } expect_only_attributes(SubElem, @@ -4326,17 +4319,17 @@ static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiu int grid_width = arch->grid_layouts.at(layout_index).width; int grid_height = arch->grid_layouts.at(layout_index).height; - + /* Absolute location that this SB must be applied to, -1 if not specified*/ sb.x = get_attribute(SubElem, "x", loc_data, ReqOpt::OPTIONAL).as_int(-1); sb.y = get_attribute(SubElem, "y", loc_data, ReqOpt::OPTIONAL).as_int(-1); //check if the absolute value is within the device grid width and height - if(sb.x >= grid_width || sb.y >= grid_height) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), \ - "Location (%d,%d) is not valid within the grid! grid dimensions are: (%d,%d)\n", sb.x, sb.y, grid_width, grid_height); + if (sb.x >= grid_width || sb.y >= grid_height) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + "Location (%d,%d) is not valid within the grid! grid dimensions are: (%d,%d)\n", sb.x, sb.y, grid_width, grid_height); } - + /* if the the switchblock exact location is not specified and a region is specified within the architecture file, * we have to parse the region specification and apply the SB pattern to all the locations fall into the specified * region based on device width and height. @@ -4344,7 +4337,6 @@ static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiu if (sb.x == -1 && sb.y == -1) { calculate_custom_SB_locations(loc_data, SubElem, grid_width, grid_height, sb); } - } /* get switchblock permutation functions */ @@ -5134,7 +5126,7 @@ static T* get_type_by_name(std::string_view type_name, std::vector& types) { // // we decrease the mesh size by 1 when calculating the spacing so that the first and last routers of each row or column are positioned on the mesh boundary // /* // * For example: -// * - If we had a mesh size of 3, then using 3 would result in a spacing that would result in one router positions being placed in either the start of the reigion or end of the region. This is because the distance calculation resulted in having 3 spaces between the ends of the region +// * - If we had a mesh size of 3, then using 3 would result in a spacing that would result in one router positions being placed in either the start of the reigion or end of the region. This is because the distance calculation resulted in having 3 spaces between the ends of the region // * // * start end // *** *** *** *** @@ -5268,11 +5260,11 @@ static T* get_type_by_name(std::string_view type_name, std::vector& types) { // } // /* Each router needs a sperate tag in the architecture description -// * to declare it. The number of declarations for each router in the +// * to declare it. The number of declarations for each router in the // * architecture file is updated here. // * // * Additionally, for any given topology, a router can connect to other routers. -// * THe number of connections for each router is also updated here. +// * THe number of connections for each router is also updated here. // * // */ // static void update_router_info_in_arch(int router_id, bool router_updated_as_a_connection, std::map>& routers_in_arch_info) { @@ -5303,7 +5295,7 @@ static T* get_type_by_name(std::string_view type_name, std::vector& types) { // * Verify each router in the noc by checking whether they satisfy the following conditions: // * - The router has only one declaration in the arch file // * - The router has atleast one connection to another router -// * If any of the conditions above are not met, then an error is thrown. +// * If any of the conditions above are not met, then an error is thrown. // */ // static void verify_noc_topology(std::map>& routers_in_arch_info) { // for (auto router_info = routers_in_arch_info.begin(); router_info != routers_in_arch_info.end(); router_info++) { @@ -5336,7 +5328,7 @@ static void ProcessVibArch(pugi::xml_node Parent, std::vectorvib_infs.reserve(num_vibs); Node = get_first_child(Parent, "vib", loc_data); - + for (int i_vib = 0; i_vib < num_vibs; i_vib++) { ProcessVib(Node, PhysicalTileTypes, arch, loc_data); Node = Node.next_sibling(Node.name()); @@ -5356,8 +5348,7 @@ static void ProcessVib(pugi::xml_node Vib_node, std::vectorvib_infs.push_back(vib); } -static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& first_stages, const pugiutil::loc_data& loc_data) { +static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& /*PhysicalTileTypes*/, std::vector& first_stages, const pugiutil::loc_data& loc_data) { pugi::xml_node Node; pugi::xml_node SubElem; //pugi::xml_node Cur; @@ -5500,7 +5485,7 @@ static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& second_stages, const pugiutil::loc_data& loc_data) { +static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector& /*PhysicalTileTypes*/, std::vector& second_stages, const pugiutil::loc_data& loc_data) { pugi::xml_node Node; pugi::xml_node SubElem; //pugi::xml_node Cur; @@ -5529,7 +5514,7 @@ static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector all_sub_tile_to_tile_pin_indices; // for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { // int sub_tile_capacity = sub_tile.capacity.total(); @@ -5615,14 +5600,14 @@ static void ProcessSecondStage(pugi::xml_node Stage_node, std::vectorvib_grid_layouts.emplace_back(std::move(grid_def)); } - } static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer) { @@ -5818,13 +5801,13 @@ static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment& strings, pugi grid_def.grid_type = VibGridDefType::VIB_AUTO; grid_def.name = "auto"; - for (size_t i = 0;i < arch->grid_layouts.size(); i++) { + for (size_t i = 0; i < arch->grid_layouts.size(); i++) { if (arch->grid_layouts[i].name == grid_def.name) { grid_def.aspect_ratio = arch->grid_layouts[i].aspect_ratio; } } //grid_def.aspect_ratio = get_attribute(layout_type_tag, "aspect_ratio", loc_data, ReqOpt::OPTIONAL).as_float(1.); - + } else if (layout_type_tag.name() == std::string("fixed_layout")) { expect_only_attributes(layout_type_tag, {"name"}, loc_data); @@ -6118,4 +6101,3 @@ static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, } } } - diff --git a/libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp b/libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp index a9b6091686d..aa415590551 100644 --- a/libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp @@ -1,3 +1,4 @@ +#include #include "read_xml_arch_file_noc_tag.h" @@ -17,8 +18,8 @@ * @param noc_ref To be filled with NoC router locations and their connectivity. */ static void process_topology(pugi::xml_node topology_tag, - const pugiutil::loc_data& loc_data, - t_noc_inf* noc_ref); + const pugiutil::loc_data& loc_data, + t_noc_inf* noc_ref); /** * @brief Process a tag under a tag. @@ -49,8 +50,8 @@ static void process_router(pugi::xml_node router_tag, * @param noc_ref To be filled with NoC router locations and their connectivity. */ static void process_mesh_topology(pugi::xml_node mesh_topology_tag, - const pugiutil::loc_data& loc_data, t_noc_inf* noc_ref); - + const pugiutil::loc_data& loc_data, + t_noc_inf* noc_ref); /** * Create routers and set their properties so that a mesh grid of routers is created. @@ -59,19 +60,12 @@ static void process_mesh_topology(pugi::xml_node mesh_topology_tag, * @param mesh_topology_tag An XML tag pointing to a tag. * @param loc_data Points to the location in the xml file where the parser is reading. * @param noc_ref To be filled with NoC router locations and their connectivity. - * @param mesh_region_start_x The location the bottom left NoC router on the X-axis. - * @param mesh_region_end_x The location the top right NoC router on the X-axis. - * @param mesh_region_start_y The location the bottom left NoC router on the Y-axis. - * @param mesh_region_end_y The location the top right NoC router on the Y-axis. - * @param mesh_size The number of NoC routers in each row or column. + * @param mesh_region Specifies the number of NoC routers and their locations in a mesh. */ static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, const pugiutil::loc_data& loc_data, t_noc_inf* noc_ref, - float mesh_region_start_x, float mesh_region_end_x, - float mesh_region_start_y, float mesh_region_end_y, - int mesh_region_start_layer, int mesh_region_end_layer, - int mesh_size); + const t_mesh_region& mesh_region); /** * @brief Verify each router in the noc by checking whether they satisfy the following conditions: @@ -152,7 +146,6 @@ void process_noc_tag(pugi::xml_node noc_tag, const std::vector expected_noc_children_tags = {"mesh", "topology"}; - // identifier that lets us know when we could not properly convert a string conversion value std::string attribute_conversion_failure_string; @@ -233,48 +226,43 @@ static void process_mesh_topology(pugi::xml_node mesh_topology_tag, // verify that only the acceptable attributes were supplied pugiutil::expect_only_attributes(mesh_topology_tag, expected_router_attributes, loc_data); + t_mesh_region mesh_region; + // go through the attributes and store their values - float mesh_region_start_x = pugiutil::get_attribute(mesh_topology_tag, "startx", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); - float mesh_region_end_x = pugiutil::get_attribute(mesh_topology_tag, "endx", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); - float mesh_region_start_y = pugiutil::get_attribute(mesh_topology_tag, "starty", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); - float mesh_region_end_y = pugiutil::get_attribute(mesh_topology_tag, "endy", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.start_x = pugiutil::get_attribute(mesh_topology_tag, "startx", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.end_x = pugiutil::get_attribute(mesh_topology_tag, "endx", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.start_y = pugiutil::get_attribute(mesh_topology_tag, "starty", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.end_y = pugiutil::get_attribute(mesh_topology_tag, "endy", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); - int mesh_region_start_layer = pugiutil::get_attribute(mesh_topology_tag, "startlayer", loc_data, pugiutil::OPTIONAL).as_int(ATTRIBUTE_CONVERSION_FAILURE); - int mesh_region_end_layer = pugiutil::get_attribute(mesh_topology_tag, "endlayer", loc_data, pugiutil::OPTIONAL).as_int(ATTRIBUTE_CONVERSION_FAILURE); - int mesh_size = pugiutil::get_attribute(mesh_topology_tag, "size", loc_data, pugiutil::REQUIRED).as_int(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.start_layer = pugiutil::get_attribute(mesh_topology_tag, "startlayer", loc_data, pugiutil::OPTIONAL).as_int(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.end_layer = pugiutil::get_attribute(mesh_topology_tag, "endlayer", loc_data, pugiutil::OPTIONAL).as_int(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.mesh_size = pugiutil::get_attribute(mesh_topology_tag, "size", loc_data, pugiutil::REQUIRED).as_int(ATTRIBUTE_CONVERSION_FAILURE); // verify that the attributes provided were legal - if ((mesh_region_start_x < 0) || (mesh_region_end_x < 0) || (mesh_region_start_y < 0) || (mesh_region_end_y < 0) || (mesh_size < 0)) { + if (mesh_region.start_x < 0 || mesh_region.end_x < 0 || mesh_region.start_y < 0 || mesh_region.end_y < 0 || mesh_region.mesh_size < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), "The parameters for the mesh topology have to be positive values."); } - if (mesh_region_start_layer == ATTRIBUTE_CONVERSION_FAILURE || mesh_region_end_layer == ATTRIBUTE_CONVERSION_FAILURE) { + if (mesh_region.start_layer == ATTRIBUTE_CONVERSION_FAILURE || mesh_region.end_layer == ATTRIBUTE_CONVERSION_FAILURE) { VTR_LOGF_WARN(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), "Optional 'startlayer' and 'endlayer' attributes were not set for the tag. " "The default value of zero is used for both of them.\n"); - mesh_region_start_layer = 0; - mesh_region_end_layer = 0; + mesh_region.start_layer = 0; + mesh_region.end_layer = 0; } // now create the mesh topology for the noc // create routers, make connections and determine positions - generate_noc_mesh(mesh_topology_tag, loc_data, noc_ref, - mesh_region_start_x, mesh_region_end_x, - mesh_region_start_y, mesh_region_end_y, - mesh_region_start_layer, mesh_region_end_layer, - mesh_size); + generate_noc_mesh(mesh_topology_tag, loc_data, noc_ref, mesh_region); } static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, const pugiutil::loc_data& loc_data, t_noc_inf* noc_ref, - float mesh_region_start_x, float mesh_region_end_x, - float mesh_region_start_y, float mesh_region_end_y, - int mesh_region_start_layer, int mesh_region_end_layer, - int mesh_size) { + const t_mesh_region& mesh_region) { // check that the mesh size of the router is not 0 - if (mesh_size == 0) { + if (mesh_region.mesh_size == 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), "The NoC mesh size cannot be 0."); } @@ -301,33 +289,32 @@ static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, * * THe reasoning for this is to reduce the number of calculated router positions. */ - float vertical_router_separation = (mesh_region_end_y - mesh_region_start_y) / (mesh_size - 1); - float horizontal_router_separation = (mesh_region_end_x - mesh_region_start_x) / (mesh_size - 1); + float vertical_router_separation = (mesh_region.end_y - mesh_region.start_y) / (mesh_region.mesh_size - 1); + float horizontal_router_separation = (mesh_region.end_x - mesh_region.start_x) / (mesh_region.mesh_size - 1); // improper region check - if (vertical_router_separation <= 0 || horizontal_router_separation <= 0 || - mesh_region_end_layer < mesh_region_start_layer) { + if (vertical_router_separation <= 0 || horizontal_router_separation <= 0 || mesh_region.end_layer < mesh_region.start_layer) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), "The NoC region is invalid."); } // create routers and their connections // start with router id 0 (bottom left of the chip) to the maximum router id (top right of the chip) - for (int l = mesh_region_start_layer; l <= mesh_region_end_layer; l++) { - for (int j = 0; j < mesh_size; j++) { - for (int i = 0; i < mesh_size; i++) { + for (int l = mesh_region.start_layer; l <= mesh_region.end_layer; l++) { + for (int j = 0; j < mesh_region.mesh_size; j++) { + for (int i = 0; i < mesh_region.mesh_size; i++) { t_router temp_router; // assign router id - temp_router.id = (mesh_size * mesh_size * (l - mesh_region_start_layer)) + (mesh_size * j) + i; + temp_router.id = (mesh_region.mesh_size * mesh_region.mesh_size * (l - mesh_region.start_layer)) + (mesh_region.mesh_size * j) + i; // calculate router position /* The first and last router of each column or row will be located on the mesh region boundary, * the remaining routers will be placed within the region and seperated from other routers * using the distance calculated previously. */ - temp_router.device_x_position = (i * horizontal_router_separation) + mesh_region_start_x; - temp_router.device_y_position = (j * vertical_router_separation) + mesh_region_start_y; + temp_router.device_x_position = (i * horizontal_router_separation) + mesh_region.start_x; + temp_router.device_y_position = (j * vertical_router_separation) + mesh_region.start_y; temp_router.device_layer_position = l; // assign connections @@ -339,13 +326,13 @@ static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, } // check if there is a router to the top - if (j <= mesh_size - 2) { + if (j <= mesh_region.mesh_size - 2) { // add the top router as a connection - temp_router.connection_list.push_back(temp_router.id + mesh_size); + temp_router.connection_list.push_back(temp_router.id + mesh_region.mesh_size); } // check if there is a router to the right - if (i <= mesh_size - 2) { + if (i <= mesh_region.mesh_size - 2) { // add the router located to the right temp_router.connection_list.push_back(temp_router.id + 1); } @@ -353,17 +340,17 @@ static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, // check if there is a router below if (j >= 1) { // add the bottom router as a connection - temp_router.connection_list.push_back(temp_router.id - mesh_size); + temp_router.connection_list.push_back(temp_router.id - mesh_region.mesh_size); } // check if there is a router on the layer above - if (l < mesh_region_end_layer) { - temp_router.connection_list.push_back(temp_router.id + (mesh_size * mesh_size)); + if (l < mesh_region.end_layer) { + temp_router.connection_list.push_back(temp_router.id + (mesh_region.mesh_size * mesh_region.mesh_size)); } // check if there is a router on the layer below - if (l > mesh_region_start_layer) { - temp_router.connection_list.push_back(temp_router.id - (mesh_size * mesh_size)); + if (l > mesh_region.start_layer) { + temp_router.connection_list.push_back(temp_router.id - (mesh_region.mesh_size * mesh_region.mesh_size)); } // add the router to the list @@ -377,8 +364,8 @@ static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, * Go through each router in the NoC and store the list of routers that connect to it. */ static void process_topology(pugi::xml_node topology_tag, - const pugiutil::loc_data& loc_data, - t_noc_inf* noc_ref) { + const pugiutil::loc_data& loc_data, + t_noc_inf* noc_ref) { // The topology tag should have no attributes, check that pugiutil::expect_only_attributes(topology_tag, {}, loc_data); @@ -651,8 +638,7 @@ static void process_noc_overrides(pugi::xml_node noc_overrides_tag, } auto it = std::find_if(noc_ref.router_list.begin(), noc_ref.router_list.end(), [src, dst](const t_router& router) { - return router.id == src && - std::find(router.connection_list.begin(), router.connection_list.end(), dst) != router.connection_list.end(); + return router.id == src && std::find(router.connection_list.begin(), router.connection_list.end(), dst) != router.connection_list.end(); }); if (it == noc_ref.router_list.end()) { @@ -666,14 +652,14 @@ static void process_noc_overrides(pugi::xml_node noc_overrides_tag, double latency = std::atof(link_latency_override); if (latency <= 0.0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(override_tag), - "The override link latency value for link (%d, %d) must be positive:%g." , + "The override link latency value for link (%d, %d) must be positive:%g.", src, dst, latency); } auto [_, success] = noc_ref.link_latency_overrides.insert({{src, dst}, latency}); if (!success) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(override_tag), - "The latency for link (%d, %d) was overridden once before." , + "The latency for link (%d, %d) was overridden once before.", src, dst); } } @@ -683,14 +669,14 @@ static void process_noc_overrides(pugi::xml_node noc_overrides_tag, double bandwidth = std::atof(link_latency_override); if (bandwidth <= 0.0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(override_tag), - "The override link bandwidth value for link (%d, %d) must be positive:%g." , + "The override link bandwidth value for link (%d, %d) must be positive:%g.", src, dst, bandwidth); } auto [_, success] = noc_ref.link_bandwidth_overrides.insert({{src, dst}, bandwidth}); if (!success) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(override_tag), - "The bandwidth for link (%d, %d) was overridden once before." , + "The bandwidth for link (%d, %d) was overridden once before.", src, dst); } } @@ -698,4 +684,4 @@ static void process_noc_overrides(pugi::xml_node noc_overrides_tag, bad_tag(override_tag, loc_data, noc_overrides_tag, {"router", "link"}); } } -} \ No newline at end of file +} diff --git a/libs/libarchfpga/src/read_xml_arch_file_noc_tag.h b/libs/libarchfpga/src/read_xml_arch_file_noc_tag.h index 8309d8cdec9..ab5015ecc0e 100644 --- a/libs/libarchfpga/src/read_xml_arch_file_noc_tag.h +++ b/libs/libarchfpga/src/read_xml_arch_file_noc_tag.h @@ -17,4 +17,25 @@ void process_noc_tag(pugi::xml_node noc_tag, t_arch* arch, const pugiutil::loc_data& loc_data); +/** + * @brief Describes a mesh topology as specified in the architecture file. + * It is assumed that NoC routers are equally distanced in each axis. + */ +struct t_mesh_region { + /// The location the bottom left NoC router on the X-axis. + float start_x; + /// The location the top right NoC router on the X-axis. + float end_x; + /// The location the bottom left NoC router on the Y-axis. + float start_y; + /// The location the top right NoC router on the Y-axis. + float end_y; + /// The layer from which the mesh start. + int start_layer; + /// The layer at which the mesh ends. + int end_layer; + /// The number of NoC routers in each row or column. + int mesh_size; +}; + #endif //VTR_READ_XML_ARCH_FILE_NOC_TAG_H diff --git a/libs/libarchfpga/src/vib_inf.cpp b/libs/libarchfpga/src/vib_inf.cpp index 4fcebadfebd..105720cc01f 100644 --- a/libs/libarchfpga/src/vib_inf.cpp +++ b/libs/libarchfpga/src/vib_inf.cpp @@ -43,7 +43,7 @@ void VibInf::set_switch_name(const std::string switch_name) { void VibInf::set_seg_groups(const std::vector seg_groups) { VTR_ASSERT(!seg_groups.empty()); seg_groups_.clear(); - for(auto seg_group : seg_groups) { + for (auto seg_group : seg_groups) { seg_groups_.push_back(seg_group); } } @@ -56,7 +56,7 @@ void VibInf::push_seg_group(const t_seg_group seg_group) { void VibInf::set_first_stages(const std::vector first_stages) { VTR_ASSERT(!first_stages.empty()); first_stages_.clear(); - for(auto first_stage : first_stages) { + for (auto first_stage : first_stages) { first_stages_.push_back(first_stage); } } @@ -69,7 +69,7 @@ void VibInf::push_first_stage(const t_first_stage_mux_inf first_stage) { void VibInf::set_second_stages(const std::vector second_stages) { VTR_ASSERT(!second_stages.empty()); second_stages_.clear(); - for(auto second_stage : second_stages) { + for (auto second_stage : second_stages) { second_stages_.push_back(second_stage); } } @@ -79,58 +79,58 @@ void VibInf::push_second_stage(const t_second_stage_mux_inf second_stage) { second_stages_.push_back(second_stage); } -std::string VibInf::get_name() const{ +std::string VibInf::get_name() const { VTR_ASSERT(!name_.empty()); return name_; } -std::string VibInf::get_pbtype_name() const{ +std::string VibInf::get_pbtype_name() const { VTR_ASSERT(!pbtype_name_.empty()); return pbtype_name_; } -int VibInf::get_seg_group_num() const{ +int VibInf::get_seg_group_num() const { VTR_ASSERT(seg_group_num_ >= 0); return seg_group_num_; } -int VibInf::get_switch_idx() const{ +int VibInf::get_switch_idx() const { VTR_ASSERT(switch_idx_ != -1); return switch_idx_; } -std::string VibInf::get_switch_name() const{ +std::string VibInf::get_switch_name() const { VTR_ASSERT(!switch_name_.empty()); return switch_name_; } -std::vector VibInf::get_seg_groups() const{ +std::vector VibInf::get_seg_groups() const { VTR_ASSERT(!seg_groups_.empty()); return seg_groups_; } -std::vector VibInf::get_first_stages() const{ +std::vector VibInf::get_first_stages() const { VTR_ASSERT(!first_stages_.empty()); return first_stages_; } -std::vector VibInf::get_second_stages() const{ +std::vector VibInf::get_second_stages() const { VTR_ASSERT(!second_stages_.empty()); return second_stages_; } -size_t VibInf::medium_mux_index_by_name(const std::string& name) const{ +size_t VibInf::medium_mux_index_by_name(const std::string& name) const { for (size_t i_medium = 0; i_medium < first_stages_.size(); ++i_medium) { if (name == first_stages_[i_medium].mux_name) { return i_medium; } } VTR_LOG_ERROR("No medium mux named %s!", name.c_str()); -} + return size_t(-1); +} VibDeviceGrid::VibDeviceGrid(std::string grid_name, vtr::NdMatrix vib_grid) : name_(std::move(grid_name)) , vib_grid_(std::move(vib_grid)) { - } diff --git a/libs/libarchfpga/src/vib_inf.h b/libs/libarchfpga/src/vib_inf.h index d4766fb7f88..e0232dd4c2f 100644 --- a/libs/libarchfpga/src/vib_inf.h +++ b/libs/libarchfpga/src/vib_inf.h @@ -24,8 +24,6 @@ //#include "physical_types.h" - - /* for vib tag */ enum e_parallel_axis_vib { X, @@ -34,7 +32,7 @@ enum e_parallel_axis_vib { }; struct t_seg_group { - std::string name; + std::string name; e_parallel_axis_vib axis; int seg_index; int track_num; @@ -48,7 +46,7 @@ enum e_multistage_mux_from_or_to_type { struct t_from_or_to_inf { std::string type_name; - e_multistage_mux_from_or_to_type from_type; //from_or_to_type + e_multistage_mux_from_or_to_type from_type; //from_or_to_type int type_index = -1; int phy_pin_index = -1; char seg_dir = ' '; @@ -56,14 +54,14 @@ struct t_from_or_to_inf { }; struct t_first_stage_mux_inf { - std::string mux_name; + std::string mux_name; std::vector> from_tokens; std::vector froms; }; struct t_second_stage_mux_inf : t_first_stage_mux_inf { std::vector to_tokens; - std::vector to; // for io type, port[pin] may map to several sinks + std::vector to; // for io type, port[pin] may map to several sinks }; // struct t_vib_inf { @@ -79,24 +77,24 @@ struct t_second_stage_mux_inf : t_first_stage_mux_inf { /* VibInf is used to reserve the VIB information. * * For example, a VIB is described: * * - - - - - - - L1.E0 L1.E1 - clb.O[0] L1.E2 - - - clb.I[0] MUX0 MUX1 - L1.N0 MUX0 MUX1 - - - - - Its corresponding figure is shown: - + * + * + * + * + * + * + * L1.E0 L1.E1 + * clb.O[0] L1.E2 + * + * + * clb.I[0] MUX0 MUX1 + * L1.N0 MUX0 MUX1 + * + * + * + * + * Its corresponding figure is shown: + * * | L1.N0 * +-----------------|-------+ * L1.E0-----------------|>|\ MUX-1 _| vib0|----------\ @@ -155,13 +153,12 @@ class VibInf { std::vector get_second_stages() const; size_t medium_mux_index_by_name(const std::string& name) const; - private: - std::string name_; /* vib name */ - std::string pbtype_name_; /* pbtype name of vib */ - int seg_group_num_; /* seg group number of vib */ - int switch_idx_; /* vib switch index */ - std::string switch_name_; /* vib switch name */ + std::string name_; /* vib name */ + std::string pbtype_name_; /* pbtype name of vib */ + int seg_group_num_; /* seg group number of vib */ + int switch_idx_; /* vib switch index */ + std::string switch_name_; /* vib switch name */ std::vector seg_groups_; std::vector first_stages_; std::vector second_stages_; @@ -208,7 +205,6 @@ struct t_vib_grid_loc_def { t_vib_grid_loc_spec x; //Horizontal location specification t_vib_grid_loc_spec y; //Veritcal location specification - }; struct t_vib_layer_def { @@ -253,27 +249,26 @@ class VibDeviceGrid { } const VibInf* get_vib(size_t layer, size_t x, size_t y) const { - return vib_grid_[layer][x][y]; + return vib_grid_[layer][x][y]; } size_t num_medium_nodes(size_t layer, size_t x, size_t y) const { - return vib_grid_[layer][x][y]->get_first_stages().size(); + return vib_grid_[layer][x][y]->get_first_stages().size(); } std::string medium_node_name(size_t layer, size_t x, size_t y, size_t medium_index) const { - return vib_grid_[layer][x][y]->get_first_stages()[medium_index].mux_name; + return vib_grid_[layer][x][y]->get_first_stages()[medium_index].mux_name; } std::string vib_pbtype_name(size_t layer, size_t x, size_t y) const { - return vib_grid_[layer][x][y]->get_pbtype_name(); + return vib_grid_[layer][x][y]->get_pbtype_name(); } bool is_empty() const { - return vib_grid_.empty(); + return vib_grid_.empty(); } private: - std::string name_; /** @@ -284,7 +279,6 @@ class VibDeviceGrid { * @note traditional 2-d indexing to be used */ vtr::NdMatrix vib_grid_; //This stores the grid of complex blocks. It is a 3D matrix: [0..num_layers-1][0..grid.width()-1][0..grid_height()-1] - }; #endif diff --git a/libs/libarchfpga/src/write_models_bb.cpp b/libs/libarchfpga/src/write_models_bb.cpp index 24de3938c96..a48c0b1ab9f 100644 --- a/libs/libarchfpga/src/write_models_bb.cpp +++ b/libs/libarchfpga/src/write_models_bb.cpp @@ -116,4 +116,4 @@ void DeclareModel_bb(FILE* Echo, const t_model* model) { // endmodule fprintf(Echo, "endmodule\n\n"); -} \ No newline at end of file +} diff --git a/libs/libarchfpga/test/main.cpp b/libs/libarchfpga/test/main.cpp index 2a2e12d62b2..f5c7e84bcee 100644 --- a/libs/libarchfpga/test/main.cpp +++ b/libs/libarchfpga/test/main.cpp @@ -1,2 +1,2 @@ #define CATCH_CONFIG_MAIN -#include "catch2/catch_test_macros.hpp" \ No newline at end of file +#include "catch2/catch_test_macros.hpp" diff --git a/libs/libarchfpga/test/test_read_xml_arch_file.cpp b/libs/libarchfpga/test/test_read_xml_arch_file.cpp index edc4ad2d065..e6b4b58a3f4 100644 --- a/libs/libarchfpga/test/test_read_xml_arch_file.cpp +++ b/libs/libarchfpga/test/test_read_xml_arch_file.cpp @@ -148,31 +148,32 @@ TEST_CASE("Verifying mesh topology creation", "[NoC Arch Tests]") { t_noc_inf test_noc; // mesh parameters - float mesh_start_x = 10; - float mesh_start_y = 10; - float mesh_end_x = 5; - float mesh_end_y = 56; - float mesh_size = 0; - int mesh_start_layer = 0; - int mesh_end_layer = 0; + t_mesh_region mesh_region{ + .start_x = 10.0f, + .end_x = 5.0f, + .start_y = 10.0f, + .end_y = 56.0f, + .start_layer = 0, + .end_layer = 0, + .mesh_size = 0}; SECTION("Check the error where a mesh size was illegal.") { - REQUIRE_THROWS_WITH(generate_noc_mesh(test, test_location, &test_noc, mesh_start_x, mesh_end_x, mesh_start_y, mesh_end_y, mesh_start_layer, mesh_end_layer, mesh_size), "The NoC mesh size cannot be 0."); + REQUIRE_THROWS_WITH(generate_noc_mesh(test, test_location, &test_noc, mesh_region), "The NoC mesh size cannot be 0."); } SECTION("Check the error where a mesh region size was invalid.") { - mesh_size = 3; + mesh_region.mesh_size = 3; - REQUIRE_THROWS_WITH(generate_noc_mesh(test, test_location, &test_noc, mesh_start_x, mesh_end_x, mesh_start_y, mesh_end_y, mesh_start_layer, mesh_end_layer, mesh_size), "The NoC region is invalid."); + REQUIRE_THROWS_WITH(generate_noc_mesh(test, test_location, &test_noc, mesh_region), "The NoC region is invalid."); } SECTION("Check the mesh creation for integer precision coordinates.") { // define test parameters - mesh_size = 3; + mesh_region.mesh_size = 3; - mesh_start_x = 0; - mesh_start_y = 0; + mesh_region.start_x = 0; + mesh_region.start_y = 0; - mesh_end_x = 4; - mesh_end_y = 4; + mesh_region.end_x = 4; + mesh_region.end_y = 4; // create the golden results float golden_results_x[9]; @@ -202,10 +203,10 @@ TEST_CASE("Verifying mesh topology creation", "[NoC Arch Tests]") { golden_results_x[8] = 4; golden_results_y[8] = 4; - generate_noc_mesh(test, test_location, &test_noc, mesh_start_x, mesh_end_x, mesh_start_y, mesh_end_y, mesh_start_layer, mesh_end_layer, mesh_size); + generate_noc_mesh(test, test_location, &test_noc, mesh_region); // go through all the expected routers - for (int expected_router_id = 0; expected_router_id < (mesh_size * mesh_size); expected_router_id++) { + for (int expected_router_id = 0; expected_router_id < (mesh_region.mesh_size * mesh_region.mesh_size); expected_router_id++) { // make sure the router ids match REQUIRE(test_noc.router_list[expected_router_id].id == expected_router_id); @@ -218,13 +219,13 @@ TEST_CASE("Verifying mesh topology creation", "[NoC Arch Tests]") { } SECTION("Check the mesh creation for double precision coordinates.") { // define test parameters - mesh_size = 3; + mesh_region.mesh_size = 3; - mesh_start_x = 3.5; - mesh_start_y = 5.7; + mesh_region.start_x = 3.5; + mesh_region.start_y = 5.7; - mesh_end_x = 10.8; - mesh_end_y = 6.4; + mesh_region.end_x = 10.8; + mesh_region.end_y = 6.4; // create the golden results float golden_results_x[9]; @@ -254,10 +255,10 @@ TEST_CASE("Verifying mesh topology creation", "[NoC Arch Tests]") { golden_results_x[8] = 10.8; golden_results_y[8] = 6.4; - generate_noc_mesh(test, test_location, &test_noc, mesh_start_x, mesh_end_x, mesh_start_y, mesh_end_y, mesh_start_layer, mesh_end_layer, mesh_size); + generate_noc_mesh(test, test_location, &test_noc, mesh_region); // go through all the expected routers - for (int expected_router_id = 0; expected_router_id < (mesh_size * mesh_size); expected_router_id++) { + for (int expected_router_id = 0; expected_router_id < (mesh_region.mesh_size * mesh_region.mesh_size); expected_router_id++) { // make sure the router ids match REQUIRE(test_noc.router_list[expected_router_id].id == expected_router_id); @@ -268,4 +269,4 @@ TEST_CASE("Verifying mesh topology creation", "[NoC Arch Tests]") { REQUIRE(vtr::isclose(golden_results_y[expected_router_id], test_noc.router_list[expected_router_id].device_y_position)); } } -} \ No newline at end of file +} diff --git a/libs/libdecrypt/test/src/test.cpp b/libs/libdecrypt/test/src/test.cpp index e88b7cc1675..bc95c971409 100644 --- a/libs/libdecrypt/test/src/test.cpp +++ b/libs/libdecrypt/test/src/test.cpp @@ -15,8 +15,12 @@ void createTestXMLFile(const std::string& filePath) { // Function to read the contents of a file into a string std::string readFileToString(const std::string& filePath) { - std::ifstream inFile(filePath); - std::string content((std::istreambuf_iterator(inFile)), std::istreambuf_iterator()); - inFile.close(); - return content; + std::ifstream inFile(filePath, std::ios::binary); + if (!inFile) { + throw std::runtime_error("Unable to open file: " + filePath); + } + + std::ostringstream ss; + ss << inFile.rdbuf(); + return ss.str(); } \ No newline at end of file diff --git a/libs/libencrypt/src/encryption.cpp b/libs/libencrypt/src/encryption.cpp index 80455f0e9a5..94e8537ad35 100644 --- a/libs/libencrypt/src/encryption.cpp +++ b/libs/libencrypt/src/encryption.cpp @@ -1,3 +1,5 @@ +#include + #include "encryption.h" #ifdef SESSION_KEY_SIZE @@ -202,14 +204,19 @@ bool Encryption::encryptFile(const std::string& publicKeyFile, std::string& file // Read file contents std::ifstream file(filePath, std::ios::binary); + std::string plaintext; if (!file) { std::cerr << "Unable to open file: " << filePath << std::endl; EVP_PKEY_free(publicKey); return false; + } else { + std::ostringstream oss; + oss << file.rdbuf(); + plaintext = oss.str(); + file.close(); } - std::string plaintext((std::istreambuf_iterator(file)), std::istreambuf_iterator()); - file.close(); + // Encrypt session key std::string encryptedSessionKey = encryptSessionKey(sessionKey, publicKey); diff --git a/libs/liblog/src/main.cpp b/libs/liblog/src/main.cpp index 65388256080..646e6c94a56 100644 --- a/libs/liblog/src/main.cpp +++ b/libs/liblog/src/main.cpp @@ -15,4 +15,4 @@ int main() { log_print_info("Test complete\n"); return 0; -} \ No newline at end of file +} diff --git a/libs/libpugiutil/src/pugixml_util.cpp b/libs/libpugiutil/src/pugixml_util.cpp index 6c5e8951cd9..ccd6dd4caec 100644 --- a/libs/libpugiutil/src/pugixml_util.cpp +++ b/libs/libpugiutil/src/pugixml_util.cpp @@ -31,7 +31,7 @@ loc_data load_xml(pugi::xml_document& doc, //Document object to be loaded w + " (line: " + std::to_string(line) + " col: " + std::to_string(col) + ")", filename.c_str(), line); } - delete (final); + delete[] final; return location_data; } else { //auto location_data = loc_data(end_result_fname); diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index 2bb43da89cb..6bea36e299c 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -54,10 +54,10 @@ void check_rr_graph(const RRGraphView& rr_graph, const DeviceGrid& grid, const VibDeviceGrid& vib_grid, const t_chan_width& chan_width, - const t_graph_type graph_type, + const e_graph_type graph_type, bool is_flat) { e_route_type route_type = DETAILED; - if (graph_type == GRAPH_GLOBAL) { + if (graph_type == e_graph_type::GLOBAL) { route_type = GLOBAL; } diff --git a/libs/librrgraph/src/base/check_rr_graph.h b/libs/librrgraph/src/base/check_rr_graph.h index 65f7d7c60d1..fc0e37fe62a 100644 --- a/libs/librrgraph/src/base/check_rr_graph.h +++ b/libs/librrgraph/src/base/check_rr_graph.h @@ -11,7 +11,7 @@ void check_rr_graph(const RRGraphView& rr_graph, const DeviceGrid& grid, const VibDeviceGrid& vib_grid, const t_chan_width& chan_width, - const t_graph_type graph_type, + const e_graph_type graph_type, bool is_flat); void check_rr_node(const RRGraphView& rr_graph, diff --git a/libs/librrgraph/src/base/get_parallel_segs.cpp b/libs/librrgraph/src/base/get_parallel_segs.cpp index adc3bce4f64..871a2e500fd 100644 --- a/libs/librrgraph/src/base/get_parallel_segs.cpp +++ b/libs/librrgraph/src/base/get_parallel_segs.cpp @@ -1,7 +1,5 @@ #include "get_parallel_segs.h" -/*Gets t_segment_inf for parallel segments as defined by the user. - *Segments that have BOTH_AXIS attribute value are always included in the returned vector.*/ std::vector get_parallel_segs(const std::vector& segment_inf, t_unified_to_parallel_seg_index& seg_index_map, enum e_parallel_axis parallel_axis, diff --git a/libs/librrgraph/src/base/get_parallel_segs.h b/libs/librrgraph/src/base/get_parallel_segs.h index 70539863dda..f173b3aa15c 100644 --- a/libs/librrgraph/src/base/get_parallel_segs.h +++ b/libs/librrgraph/src/base/get_parallel_segs.h @@ -4,6 +4,18 @@ #include "rr_graph_type.h" #include "physical_types.h" +/** + * @brief Returns segments aligned with a given axis, including BOTH_AXIS segments. + * + * Filters the unified segment list (`segment_inf`) to include only segments matching + * the specified `parallel_axis` or marked as `BOTH_AXIS`. Also populates `seg_index_map` + * to map unified indices to axis-specific ones. + * + * @param segment_inf Unified list of all segments. + * @param seg_index_map Map from unified to axis-specific segment indices. + * @param parallel_axis Axis to filter segments by. + * @return Filtered list of segments for the given axis. + */ std::vector get_parallel_segs(const std::vector& segment_inf, t_unified_to_parallel_seg_index& seg_index_map, enum e_parallel_axis parallel_axis, diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index f07e135b515..07e23cfb449 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -293,7 +293,7 @@ class RRGraphBuilder { /** @brief Reserve the lists of edges to be memory efficient. * This function is mainly used to reserve memory space inside RRGraph, - * when adding a large number of edges in order to avoid memory fragements */ + * when adding a large number of edges in order to avoid memory fragments */ inline void reserve_edges(size_t num_edges) { node_storage_.reserve_edges(num_edges); } @@ -318,6 +318,12 @@ class RRGraphBuilder { node_storage_.alloc_and_load_edges(rr_edges_to_create); } + /** @brief Overrides the associated switch for a given edge by + * updating the edge to use the passed in switch. */ + inline void override_edge_switch(RREdgeId edge_id, RRSwitchId switch_id) { + node_storage_.override_edge_switch(edge_id, switch_id); + } + /** @brief set_node_cost_index gets the index of cost data in the list of cost_indexed_data data structure * It contains the routing cost for different nodes in the RRGraph * when used in evaluate different routing paths @@ -361,7 +367,7 @@ class RRGraphBuilder { /** @brief Reserve the lists of nodes, edges, switches etc. to be memory efficient. * This function is mainly used to reserve memory space inside RRGraph, * when adding a large number of nodes/edge/switches/segments, - * in order to avoid memory fragements */ + * in order to avoid memory fragments */ inline void reserve_nodes(size_t size) { node_storage_.reserve(size); } diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index e76de6e4e83..124fd81036b 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -539,10 +539,9 @@ void t_rr_graph_storage::partition_edges(const vtr::vector& rr_switches) const { VTR_ASSERT(!node_first_edge_.empty() && remapped_edges_); diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index adc2f507483..39134554718 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -407,13 +407,27 @@ class t_rr_graph_storage { * This method should generally not be used, and instead first_edge and * last_edge should be used. */ - RREdgeId edge_id(const RRNodeId& id, t_edge_size iedge) const { + RREdgeId edge_id(RRNodeId id, t_edge_size iedge) const { RREdgeId first_edge = this->first_edge(id); RREdgeId ret(size_t(first_edge) + iedge); VTR_ASSERT_SAFE(ret < last_edge(id)); return ret; } + /** + * @brief Retrieve the RREdgeId that connects the given source and sink nodes. + * If the given source/sink nodes are not connected, RREdgeId::INVALID() is returned. + */ + RREdgeId edge_id(RRNodeId src, RRNodeId sink) const { + for (RREdgeId outgoing_edge_id : edge_range(src)) { + if (edge_sink_node(outgoing_edge_id) == sink) { + return outgoing_edge_id; + } + } + + return RREdgeId::INVALID(); + } + /** @brief Get the source node for the specified edge. */ RRNodeId edge_src_node(const RREdgeId& edge) const { VTR_ASSERT_DEBUG(edge.is_valid()); @@ -472,7 +486,7 @@ class t_rr_graph_storage { * * The following methods implement an interface that appears to be * equivalent to the interface exposed by std::vector. - * This was done for backwards compability. See t_rr_node for more details. + * This was done for backwards compatibility. See t_rr_node for more details. * * Proxy methods: * @@ -507,8 +521,8 @@ class t_rr_graph_storage { ***************************/ /** @brief - * Makes room in storage for RRNodeId in amoritized O(1) fashion. - * This results in an allocation pattern similiar to what would happen + * Makes room in storage for RRNodeId in amortized O(1) fashion. + * This results in an allocation pattern similar to what would happen * if push_back(x) / emplace_back() were used if underlying storage * was not pre-allocated. */ @@ -643,8 +657,8 @@ class t_rr_graph_storage { void set_node_direction(RRNodeId, Direction new_direction); /** @brief - * Add a side to the node abbributes - * This is the function to use when you just add a new side WITHOUT reseting side attributes + * Add a side to the node attributes + * This is the function to use when you just add a new side WITHOUT resetting side attributes */ void add_node_side(RRNodeId, e_side new_side); @@ -734,9 +748,8 @@ class t_rr_graph_storage { * * init_fan_in does not need to be invoked before this method. */ - size_t count_rr_switches( - const std::vector& arch_switch_inf, - t_arch_switch_fanin& arch_switch_fanins); + size_t count_rr_switches(const std::vector& arch_switch_inf, + t_arch_switch_fanin& arch_switch_fanins); /** @brief Maps arch_switch_inf indicies to rr_switch_inf indicies. * @@ -758,6 +771,10 @@ class t_rr_graph_storage { */ void partition_edges(const vtr::vector& rr_switches); + /** @brief Overrides the associated switch for a given edge by + * updating the edge to use the passed in switch. */ + void override_edge_switch(RREdgeId edge_id, RRSwitchId switch_id); + /** @brief Validate that edge data is partitioned correctly.*/ bool validate_node(RRNodeId node_id, const vtr::vector& rr_switches) const; bool validate(const vtr::vector& rr_switches) const; diff --git a/libs/librrgraph/src/base/rr_graph_type.h b/libs/librrgraph/src/base/rr_graph_type.h index f6c5bc7efb5..05c0cad0818 100644 --- a/libs/librrgraph/src/base/rr_graph_type.h +++ b/libs/librrgraph/src/base/rr_graph_type.h @@ -19,18 +19,32 @@ enum e_route_type { DETAILED }; -enum e_graph_type { - GRAPH_GLOBAL, /* One node per channel with wire capacity > 1 and full connectivity */ - GRAPH_BIDIR, /* Detailed bidirectional graph */ - GRAPH_UNIDIR, /* Detailed unidir graph, untilable */ - /* RESEARCH TODO: Get this option debugged */ - GRAPH_UNIDIR_TILEABLE /* Detail unidir graph with wire groups multiples of 2*L */ +/** + * @enum e_graph_type + * @brief Represents the type of routing resource graph + */ +enum class e_graph_type { + GLOBAL, ///< One node per channel with wire capacity > 1 and full connectivity + BIDIR, ///< Detailed bidirectional routing graph + UNIDIR, ///< Detailed unidirectional routing graph (non-tileable) + UNIDIR_TILEABLE ///< Tileable unidirectional graph with wire groups in multiples of 2 * L (experimental) }; -typedef enum e_graph_type t_graph_type; -/* This map is used to get indices w.r.t segment_inf_x or segment_inf_y based on parallel_axis of a segment, - * from indices w.r.t the **unified** segment vector, segment_inf in devices context which stores all segments - * regardless of their axis. (see get_parallel_segs for more details)*/ +/** + * @typedef t_unified_to_parallel_seg_index + * @brief Maps indices from the unified segment list to axis-specific segment lists. + * + * This map is used to translate indices from the unified segment vector + * (`segment_inf` in the device context, which contains all segments regardless of axis) + * to axis-specific segment vectors (`segment_inf_x` or `segment_inf_y`), based on the + * segment's parallel axis. + * + * Each entry maps a unified segment index to a pair containing: + * - The index in the corresponding axis-specific segment vector + * - The axis of the segment (X or Y) + * + * @see get_parallel_segs for more details. + */ typedef std::unordered_multimap> t_unified_to_parallel_seg_index; #endif \ No newline at end of file diff --git a/libs/librrgraph/src/base/rr_graph_utils.h b/libs/librrgraph/src/base/rr_graph_utils.h index e04fe3ef177..e3f2d3cdfb9 100644 --- a/libs/librrgraph/src/base/rr_graph_utils.h +++ b/libs/librrgraph/src/base/rr_graph_utils.h @@ -21,7 +21,7 @@ struct t_pin_chain_node { int nxt_node_idx = OPEN; t_pin_chain_node() = default; - t_pin_chain_node(int pin_num, int nxt_idx) + t_pin_chain_node(int pin_num, int nxt_idx) noexcept : pin_physical_num(pin_num) , nxt_node_idx(nxt_idx) {} }; diff --git a/libs/librrgraph/src/base/rr_graph_view.cpp b/libs/librrgraph/src/base/rr_graph_view.cpp index 225af722e5b..4d2e478b220 100644 --- a/libs/librrgraph/src/base/rr_graph_view.cpp +++ b/libs/librrgraph/src/base/rr_graph_view.cpp @@ -41,7 +41,7 @@ std::vector RRGraphView::node_configurable_in_edges(RRNodeId node) con return ret_edges; } for (const RREdgeId& edge : node_in_edges_[node]) { - if (rr_switch_inf_[edge_switch(edge)].configurable()) { + if (rr_switch_inf_[RRSwitchId(edge_switch(edge))].configurable()) { ret_edges.push_back(edge); } } @@ -56,7 +56,7 @@ std::vector RRGraphView::node_non_configurable_in_edges(RRNodeId node) return ret_edges; } for (const RREdgeId& edge : node_in_edges_[node]) { - if (!rr_switch_inf_[edge_switch(edge)].configurable()) { + if (!rr_switch_inf_[RRSwitchId(edge_switch(edge))].configurable()) { ret_edges.push_back(edge); } } diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index f28a5883cbe..f7e6803c98c 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -425,12 +425,13 @@ class RRGraphView { return node_storage_.edge_switch(id, iedge); } - inline RRSwitchId edge_switch(RREdgeId edge) const { - return RRSwitchId(node_storage_.edge_switch(edge)); + /// @brief Returns the associated switch for a given edge. + inline short edge_switch(RREdgeId id) const { + return node_storage_.edge_switch(id); } - /** @brief Get the source node for the iedge'th edge from specified RRNodeId. - * This method should generally not be used, and instead first_edge and - * last_edge should be used.*/ + + /** @brief Return the source node for the specified edge. + */ inline RRNodeId edge_src_node(const RREdgeId edge_id) const { return node_storage_.edge_src_node(edge_id); } diff --git a/libs/librrgraph/src/base/rr_node_types.h b/libs/librrgraph/src/base/rr_node_types.h index b89244bc95d..8d318921593 100644 --- a/libs/librrgraph/src/base/rr_node_types.h +++ b/libs/librrgraph/src/base/rr_node_types.h @@ -10,6 +10,7 @@ #include #include "vtr_range.h" #include "vtr_ndmatrix.h" +#include "rr_graph_fwd.h" /** * @brief Type of a routing resource node. @@ -66,7 +67,7 @@ typedef uint16_t t_edge_size; /** * @brief An iterator that dereferences to an edge index * - * Used inconjunction with vtr::Range to return ranges of edge indices + * Used in conjunction with vtr::Range to return ranges of edge indices */ class edge_idx_iterator { public: @@ -101,7 +102,7 @@ typedef vtr::Range edge_idx_range; typedef std::vector> t_arch_switch_fanin; /* - * Reistance/Capacitance data for an RR Nodes + * Resistance/Capacitance data for an RR Nodes * * In practice many RR nodes have the same values, so they are fly-weighted * to keep t_rr_node small. Each RR node holds an rc_index which allows @@ -124,6 +125,6 @@ struct t_rr_rc_data { // This is the data type of fast lookups of an rr-node given an (rr_type, layer, x, y, and the side) //[0..num_rr_types-1][0..num_layer-1][0..grid_width-1][0..grid_height-1][0..NUM_2D_SIDES-1][0..max_ptc-1] -typedef std::array, 4>, NUM_RR_TYPES> t_rr_node_indices; +typedef std::array, 4>, NUM_RR_TYPES> t_rr_node_indices; #endif diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index 6234e25552e..fb1780e72ce 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -76,7 +76,7 @@ RRNodeId RRSpatialLookup::find_node(int layer, return RRNodeId::INVALID(); } - return RRNodeId(rr_node_indices_[type][layer][node_x][node_y][node_side][ptc]); + return rr_node_indices_[type][layer][node_x][node_y][node_side][ptc]; } std::vector RRSpatialLookup::find_nodes_in_range(int layer, @@ -156,14 +156,14 @@ std::vector RRSpatialLookup::find_nodes(int layer, /* Reserve space to avoid memory fragmentation */ size_t num_nodes = 0; for (const auto& node : rr_node_indices_[type][layer][node_x][node_y][side]) { - if (RRNodeId(node)) { + if (node.is_valid()) { num_nodes++; } } nodes.reserve(num_nodes); for (const auto& node : rr_node_indices_[type][layer][node_x][node_y][side]) { - if (RRNodeId(node)) { + if (node.is_valid()) { nodes.emplace_back(node); } } @@ -273,11 +273,11 @@ void RRSpatialLookup::add_node(RRNodeId node, if (size_t(ptc) >= rr_node_indices_[type][layer][x][y][side].size()) { /* Deposit invalid ids to newly allocated elements while original elements are untouched */ - rr_node_indices_[type][layer][x][y][side].resize(ptc + 1, int(RRNodeId::INVALID())); + rr_node_indices_[type][layer][x][y][side].resize(ptc + 1, RRNodeId::INVALID()); } /* Resize on demand finished; Register the node */ - rr_node_indices_[type][layer][x][y][side][ptc] = int(node); + rr_node_indices_[type][layer][x][y][side][ptc] = node; } bool RRSpatialLookup::remove_node(RRNodeId node, @@ -303,11 +303,11 @@ bool RRSpatialLookup::remove_node(RRNodeId node, if ((size_t)y >= rr_node_indices_[type].dim_size(2)) return false; if (side >= rr_node_indices_[type].dim_size(3)) return false; if ((size_t)ptc >= rr_node_indices_[type][layer][x][y][side].size()) return false; - if (rr_node_indices_[type][layer][x][y][side][ptc] != int(node)) return false; + if (rr_node_indices_[type][layer][x][y][side][ptc] != node) return false; // The node was in the spatial lookup; remove it. -1 corresponds to an invalid node id, // and so is treated as absent in the spatial lookup - rr_node_indices_[type][layer][x][y][side][ptc] = -1; + rr_node_indices_[type][layer][x][y][side][ptc] = RRNodeId::INVALID(); return true; } @@ -354,8 +354,8 @@ void RRSpatialLookup::reorder(const vtr::vector dest_order) for (size_t y = 0; y < grid.dim_size(2); y++) { for (size_t s = 0; s < grid.dim_size(3); s++) { for (auto &node: grid[l][x][y][s]) { - if (node != OPEN) { - node = size_t(dest_order[RRNodeId(node)]); + if (node.is_valid()) { + node = dest_order[node]; } } } diff --git a/libs/librrgraph/src/io/rr_graph_reader.cpp b/libs/librrgraph/src/io/rr_graph_reader.cpp index ec574080dba..0bcd843ae34 100644 --- a/libs/librrgraph/src/io/rr_graph_reader.cpp +++ b/libs/librrgraph/src/io/rr_graph_reader.cpp @@ -19,6 +19,8 @@ #include "rr_graph_uxsdcxx.h" #include +#include +#include #include "vtr_time.h" #include "pugixml.hpp" @@ -29,6 +31,20 @@ # include "mmap_file.h" #endif +/** + * @brief Parses a line from the RR edge delay override file. + * + * @details Expected formats: + * edge_id Tdel + * (source_node_id, sink_node_id) Tdel + * + * @param line The line to parse. + * @param rr_graph The RR graph for edge lookup using source-sink nodes. + * @return A pair containing an RR edge and the overridden Tdel (intrinsic delay). + */ +static std::pair process_rr_edge_override(const std::string& line, + const RRGraphView& rr_graph); + /************************ Subroutine definitions ****************************/ /* loads the given RR_graph file into the appropriate data structures * as specified by read_rr_graph_name. Set up correct routing data @@ -38,6 +54,7 @@ * parameters are a workaround to passing the data structures of DeviceContext. * Needs a solution to reduce the number of parameters passed in.*/ + void load_rr_file(RRGraphBuilder* rr_graph_builder, RRGraphView* rr_graph, const std::vector& physical_tile_types, @@ -46,14 +63,14 @@ void load_rr_file(RRGraphBuilder* rr_graph_builder, std::vector* rr_rc_data, const DeviceGrid& grid, const std::vector& arch_switch_inf, - const t_graph_type graph_type, + e_graph_type graph_type, const t_arch* arch, t_chan_width* chan_width, const enum e_base_cost_type base_cost_type, int* wire_to_rr_ipin_switch, int* wire_to_rr_ipin_switch_between_dice, const char* read_rr_graph_name, - std::string* read_rr_graph_filename, + std::string* loaded_rr_graph_filename, bool read_edge_metadata, bool do_check_rr_graph, bool echo_enabled, @@ -74,7 +91,7 @@ void load_rr_file(RRGraphBuilder* rr_graph_builder, wire_to_rr_ipin_switch_between_dice, do_check_rr_graph, read_rr_graph_name, - read_rr_graph_filename, + loaded_rr_graph_filename, read_edge_metadata, echo_enabled, echo_file_name, @@ -115,3 +132,79 @@ void load_rr_file(RRGraphBuilder* rr_graph_builder, read_rr_graph_name); } } + +static std::pair process_rr_edge_override(const std::string& line, + const RRGraphView& rr_graph) { + std::istringstream iss(line); + char ch; + RREdgeId edge_id; + + if (std::isdigit(line[0])) { + // Line starts with an integer + int first; + iss >> first; + edge_id = (RREdgeId)first; + } else if (line[0] == '(') { + // Line starts with (first, second) + int first, second; + iss >> ch >> first >> ch >> second >> ch; + + RRNodeId src_node_id = RRNodeId(first); + RRNodeId sink_node_id = RRNodeId(second); + + edge_id = rr_graph.rr_nodes().edge_id(src_node_id, sink_node_id); + + VTR_LOGV_ERROR(!edge_id.is_valid(), + "Couldn't find an edge connecting node %d to node %d\n", + src_node_id, + sink_node_id); + + } else { + VTR_LOG_ERROR("Invalid line format: %s\n", line.c_str()); + } + + float overridden_Tdel; + if (!(iss >> overridden_Tdel)) { + VTR_LOG_ERROR("Couldn't parse the overridden delay in this line: %s\n", line.c_str()); + } + + return {edge_id, overridden_Tdel}; +} + +void load_rr_edge_delay_overrides(std::string_view filename, + RRGraphBuilder& rr_graph_builder, + const RRGraphView& rr_graph) { + std::ifstream file(filename.data()); + VTR_LOGV_ERROR(!file, "Failed to open the RR edge override file: %s\n", filename.data()); + + std::unordered_map unique_switch_info; + for (const auto& [rr_sw_idx, sw] : rr_graph.rr_switch().pairs()) { + unique_switch_info.insert({sw, rr_sw_idx}); + } + + std::string line; + + while (std::getline(file, line)) { + if (line[0] == '#') { + continue; // Ignore lines starting with '#' + } + + if (!line.empty()) { + const auto [edge_id, overridden_Tdel] = process_rr_edge_override(line, rr_graph); + RRSwitchId curr_switch_id = (RRSwitchId)rr_graph.edge_switch(edge_id); + t_rr_switch_inf switch_override_info = rr_graph.rr_switch_inf(curr_switch_id); + + switch_override_info.Tdel = overridden_Tdel; + + RRSwitchId new_switch_id; + auto it = unique_switch_info.find(switch_override_info); + if (it == unique_switch_info.end()) { + new_switch_id = rr_graph_builder.add_rr_switch(switch_override_info); + unique_switch_info.insert({switch_override_info, new_switch_id}); + } else { + new_switch_id = it->second; + } + rr_graph_builder.override_edge_switch(edge_id, new_switch_id); + } + } +} \ No newline at end of file diff --git a/libs/librrgraph/src/io/rr_graph_reader.h b/libs/librrgraph/src/io/rr_graph_reader.h index 8549b712bdf..044345ee721 100644 --- a/libs/librrgraph/src/io/rr_graph_reader.h +++ b/libs/librrgraph/src/io/rr_graph_reader.h @@ -21,18 +21,38 @@ void load_rr_file(RRGraphBuilder* rr_graph_builder, std::vector* rr_rc_data, const DeviceGrid& grid, const std::vector& arch_switch_inf, - const t_graph_type graph_type, + e_graph_type graph_type, const t_arch* arch, t_chan_width* chan_width, const enum e_base_cost_type base_cost_type, int* wire_to_rr_ipin_switch, int* wire_to_rr_ipin_switch_between_dice, const char* read_rr_graph_name, - std::string* read_rr_graph_filename, + std::string* loaded_rr_graph_filename, bool read_edge_metadata, bool do_check_rr_graph, bool echo_enabled, const char* echo_file_name, bool is_flat); +/** + * @brief Reads a text file where the intrinsic delay of edges are overridden. + * + * @details This function tries to find a switch with the overridden delay. If such a + * switch exists, the edge will point to it as its corresponding switch. + * Otherwise, a new switch is created so that the edge can point to a valid switch. + * The architecture file allows the user to specify nominal switch delays, but delays + * may vary for the same switch type across the device. To represent switch delays + * more accurately, the user can specify multiple switch types in the architecture file + * and restrict each one to a region or a single location. Alternatively, the user can + * use this file to override edge delays. + * + * @param filename The text file to be ingested by this function. + * @param rr_graph_builder Used to add switches and override switch IDs for edges. + * @param rr_graph Provides read only access to RR graph. + */ +void load_rr_edge_delay_overrides(std::string_view filename, + RRGraphBuilder& rr_graph_builder, + const RRGraphView& rr_graph); + #endif /* RR_GRAPH_READER_H */ diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index cebd33c9aa0..afc5d180c3d 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -270,13 +270,13 @@ struct RrGraphContextTypes : public uxsd::DefaultRrGraphContextTypes { class RrGraphSerializer final : public uxsd::RrGraphBase { public: RrGraphSerializer( - const t_graph_type graph_type, + const e_graph_type graph_type, const enum e_base_cost_type base_cost_type, int* wire_to_rr_ipin_switch, int* wire_to_rr_ipin_switch_between_dice, bool do_check_rr_graph, const char* read_rr_graph_name, - std::string* read_rr_graph_filename, + std::string* loaded_rr_graph_filename, bool read_edge_metadata, bool echo_enabled, const char* echo_file_name, @@ -303,7 +303,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { , rr_graph_(rr_graph) , rr_switch_inf_(rr_switch_inf) , rr_indexed_data_(rr_indexed_data) - , read_rr_graph_filename_(read_rr_graph_filename) + , loaded_rr_graph_filename_(loaded_rr_graph_filename) , rr_rc_data_(rr_rc_data) , graph_type_(graph_type) , base_cost_type_(base_cost_type) @@ -829,7 +829,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { auto node = (*rr_nodes_)[inode]; RRNodeId node_id = node.id(); - if (GRAPH_GLOBAL == graph_type_) { + if (e_graph_type::GLOBAL == graph_type_) { rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(0)); } else if (rr_graph.node_type(node.id()) == CHANX) { int seg_ind_x = find_segment_index_along_axis(segment_id, X_AXIS); @@ -1832,9 +1832,9 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { (*rr_indexed_data_)[RRIndexedDataId(i)].seg_index = seg_index_[RRIndexedDataId(i)]; } - VTR_ASSERT(read_rr_graph_filename_ != nullptr); + VTR_ASSERT(loaded_rr_graph_filename_ != nullptr); VTR_ASSERT(read_rr_graph_name_ != nullptr); - read_rr_graph_filename_->assign(read_rr_graph_name_); + loaded_rr_graph_filename_->assign(read_rr_graph_name_); if (do_check_rr_graph_) { const VibDeviceGrid vib_grid_; @@ -2182,11 +2182,11 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { vtr::vector* rr_switch_inf_; vtr::vector* rr_indexed_data_; t_rr_node_indices* rr_node_indices_; - std::string* read_rr_graph_filename_; + std::string* loaded_rr_graph_filename_; std::vector* rr_rc_data_; // Constant data for loads and writes. - const t_graph_type graph_type_; + const e_graph_type graph_type_; const enum e_base_cost_type base_cost_type_; const bool do_check_rr_graph_; const char* read_rr_graph_name_; diff --git a/libs/librrgraph/src/io/rr_graph_writer.cpp b/libs/librrgraph/src/io/rr_graph_writer.cpp index d254ae9edb7..291d9ffafa4 100644 --- a/libs/librrgraph/src/io/rr_graph_writer.cpp +++ b/libs/librrgraph/src/io/rr_graph_writer.cpp @@ -21,7 +21,7 @@ /************************ Subroutine definitions ****************************/ -/* This function is used to write the rr_graph into xml format into a a file with name: file_name */ +/* This function is used to write the rr_graph into xml format into a file with name: file_name */ /**FIXME: To make rr_graph_reader independent of vpr_context, the below * parameters are a workaround to passing the data structures of DeviceContext. @@ -42,7 +42,7 @@ void write_rr_graph(RRGraphBuilder* rr_graph_builder, bool is_flat) { RrGraphSerializer reader( - /*graph_type=*/t_graph_type(), + /*graph_type=*/e_graph_type(), /*base_cost_type=*/e_base_cost_type(), /*wire_to_rr_ipin_switch=*/nullptr, /*wire_to_rr_ipin_switch_between_dice=*/nullptr, diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index d94514b1637..3fd98a700aa 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -29,7 +29,7 @@ static float get_delay_normalization_fac(const vtr::vector& rr_indexed_data); -static void calculate_average_switch(const RRGraphView& rr_graph, int inode, double& avg_switch_R, double& avg_switch_T, double& avg_switch_Cinternal, int& num_switches, short& buffered, vtr::vector>& fan_in_list); +static void calculate_average_switch(const RRGraphView& rr_graph, int inode, double& avg_switch_R, double& avg_switch_T, double& avg_switch_Cinternal, int& num_switches, int& num_shorts, short& buffered, vtr::vector>& fan_in_list); static void fixup_rr_indexed_data_T_values(vtr::vector& rr_indexed_data, size_t num_segment); @@ -542,15 +542,18 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, double avg_switch_T = 0; double avg_switch_Cinternal = 0; int num_switches = 0; + int num_shorts = 0; short buffered = UNDEFINED; - calculate_average_switch(rr_graph, (size_t)rr_id, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, buffered, fan_in_list); + calculate_average_switch(rr_graph, (size_t)rr_id, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, num_shorts, buffered, fan_in_list); if (num_switches == 0) { - VTR_LOG_WARN("Node: %d with RR_type: %s at Location:%s, had no incoming switches\n", rr_id, - rr_graph.node_type_string(rr_id), node_cords.c_str()); + if (num_shorts == 0) { + VTR_LOG_WARN("Node: %d with RR_type: %s at Location:%s, had no out-going switches\n", rr_id, + rr_graph.node_type_string(rr_id), node_cords.c_str()); + } continue; - } - VTR_ASSERT(num_switches > 0); + } + VTR_ASSERT(num_switches > 0 || num_shorts > 0); num_nodes_of_index[cost_index]++; C_total[cost_index].push_back(rr_graph.node_C(rr_id)); @@ -634,20 +637,24 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, * It is not safe to assume that each node of the same wire type has the same switches with the same * delays, therefore we take their average to take into account the possible differences */ -static void calculate_average_switch(const RRGraphView& rr_graph, int inode, double& avg_switch_R, double& avg_switch_T, double& avg_switch_Cinternal, int& num_switches, short& buffered, vtr::vector>& fan_in_list) { +static void calculate_average_switch(const RRGraphView& rr_graph, int inode, double& avg_switch_R, double& avg_switch_T, double& avg_switch_Cinternal, int& num_switches, int& num_shorts, short& buffered, vtr::vector>& fan_in_list) { auto node = RRNodeId(inode); avg_switch_R = 0; avg_switch_T = 0; avg_switch_Cinternal = 0; num_switches = 0; + num_shorts = 0; buffered = UNDEFINED; for (const auto& edge : fan_in_list[node]) { /* want to get C/R/Tdel/Cinternal of switches that connect this track segment to other track segments */ if (rr_graph.node_type(node) == CHANX || rr_graph.node_type(node) == CHANY) { int switch_index = rr_graph.rr_nodes().edge_switch(edge); - if (rr_graph.rr_switch_inf(RRSwitchId(switch_index)).type() == SwitchType::SHORT) continue; + if (rr_graph.rr_switch_inf(RRSwitchId(switch_index)).type() == SwitchType::SHORT) { + num_shorts++; + continue; + } avg_switch_R += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).R; avg_switch_T += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Tdel; @@ -739,6 +746,8 @@ static void print_rr_index_info(const vtr::vector #ifndef FILE_NAME -# define FILE_NAME (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__) +#define FILE_NAME (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__) #endif /* Enable Debug Messages for libRTLNumber: Un-Comment to Enable Debug Messages: @@ -24,22 +24,22 @@ // #define ENABLE_DEBUG_MESSAGES #ifdef ENABLE_DEBUG_MESSAGES -# define DEBUG_MSG(debugMsg) std::cerr << "DEBUG: " << FILE_NAME << ":" << __LINE__ << " " << __func__ << "()" \ - << ": " << debugMsg << std::endl +#define DEBUG_MSG(debugMsg) std::cerr << "DEBUG: " << FILE_NAME << ":" << __LINE__ << " " << __func__ << "()" \ + << ": " << debugMsg << std::endl #else -# define DEBUG_MSG(debugMsg) /* No-Op */ +#define DEBUG_MSG(debugMsg) /* No-Op */ #endif #ifndef WARN_MSG -# define WARN_MSG(warnMSG) std::cerr << "WARNING: " << FILE_NAME << ":" << __LINE__ << " " << __func__ << "()" \ - << ": " << warnMSG << "!" << std::endl +#define WARN_MSG(warnMSG) std::cerr << "WARNING: " << FILE_NAME << ":" << __LINE__ << " " << __func__ << "()" \ + << ": " << warnMSG << "!" << std::endl #endif #ifndef ERR_MSG -# define ERR_MSG(errMsg) std::cerr << std::endl \ - << "ERROR: " << FILE_NAME << ":" << __LINE__ << " " << __func__ << "()" \ - << ": " << errMsg << "!" << std::endl \ - << std::endl +#define ERR_MSG(errMsg) std::cerr << std::endl \ + << "ERROR: " << FILE_NAME << ":" << __LINE__ << " " << __func__ << "()" \ + << ": " << errMsg << "!" << std::endl \ + << std::endl #endif std::string string_of_radix_to_bitstring(std::string orig_string, size_t radix); diff --git a/libs/libvtrutil/src/specrand.cpp b/libs/libvtrutil/src/specrand.cpp index a508eb31ce3..881802b8227 100644 --- a/libs/libvtrutil/src/specrand.cpp +++ b/libs/libvtrutil/src/specrand.cpp @@ -112,7 +112,7 @@ unsigned long SpecRandomNumberGenerator::spec_genrand_int32_() { if (mti >= N) { /* generate N words at one time */ - if (mti == N + 1) /* if init_genrand() has not been called, */ + if (mti == N + 1) /* if init_genrand() has not been called, */ spec_init_genrand_(5489UL); /* a default initial seed is used */ for (size_t kk = 0; kk < N - M; kk++) { diff --git a/libs/libvtrutil/src/specrand.h b/libs/libvtrutil/src/specrand.h index 9a7634e678c..6216a3a341a 100644 --- a/libs/libvtrutil/src/specrand.h +++ b/libs/libvtrutil/src/specrand.h @@ -114,7 +114,6 @@ class SpecRandomNumberGenerator : public vtr::RandomNumberGeneratorInterface { size_t mti = N + 1; /// the array for the state vector unsigned long mt[N]; - }; #endif diff --git a/libs/libvtrutil/src/tl_optional.hpp b/libs/libvtrutil/src/tl_optional.hpp index 294755b69a1..3d5f037c559 100644 --- a/libs/libvtrutil/src/tl_optional.hpp +++ b/libs/libvtrutil/src/tl_optional.hpp @@ -32,78 +32,78 @@ #include #if (defined(_MSC_VER) && _MSC_VER == 1900) -# define TL_OPTIONAL_MSVC2015 +#define TL_OPTIONAL_MSVC2015 #endif #if (defined(__GNUC__) && __GNUC__ == 4 && __GNUC_MINOR__ <= 9 && !defined(__clang__)) -# define TL_OPTIONAL_GCC49 +#define TL_OPTIONAL_GCC49 #endif #if (defined(__GNUC__) && __GNUC__ == 5 && __GNUC_MINOR__ <= 4 && !defined(__clang__)) -# define TL_OPTIONAL_GCC54 +#define TL_OPTIONAL_GCC54 #endif #if (defined(__GNUC__) && __GNUC__ == 5 && __GNUC_MINOR__ <= 5 && !defined(__clang__)) -# define TL_OPTIONAL_GCC55 +#define TL_OPTIONAL_GCC55 #endif #if (defined(__GNUC__) && __GNUC__ == 4 && __GNUC_MINOR__ <= 9 && !defined(__clang__)) // GCC < 5 doesn't support overloading on const&& for member functions -# define TL_OPTIONAL_NO_CONSTRR +#define TL_OPTIONAL_NO_CONSTRR // GCC < 5 doesn't support some standard C++11 type traits -# define TL_OPTIONAL_IS_TRIVIALLY_COPY_CONSTRUCTIBLE(T) \ - std::has_trivial_copy_constructor::value -# define TL_OPTIONAL_IS_TRIVIALLY_COPY_ASSIGNABLE(T) std::has_trivial_copy_assign::value +#define TL_OPTIONAL_IS_TRIVIALLY_COPY_CONSTRUCTIBLE(T) \ + std::has_trivial_copy_constructor::value +#define TL_OPTIONAL_IS_TRIVIALLY_COPY_ASSIGNABLE(T) std::has_trivial_copy_assign::value // This one will be different for GCC 5.7 if it's ever supported -# define TL_OPTIONAL_IS_TRIVIALLY_DESTRUCTIBLE(T) std::is_trivially_destructible::value +#define TL_OPTIONAL_IS_TRIVIALLY_DESTRUCTIBLE(T) std::is_trivially_destructible::value // GCC 5 < v < 8 has a bug in is_trivially_copy_constructible which breaks std::vector // for non-copyable types #elif (defined(__GNUC__) && __GNUC__ < 8 && !defined(__clang__)) -# ifndef TL_GCC_LESS_8_TRIVIALLY_COPY_CONSTRUCTIBLE_MUTEX -# define TL_GCC_LESS_8_TRIVIALLY_COPY_CONSTRUCTIBLE_MUTEX +#ifndef TL_GCC_LESS_8_TRIVIALLY_COPY_CONSTRUCTIBLE_MUTEX +#define TL_GCC_LESS_8_TRIVIALLY_COPY_CONSTRUCTIBLE_MUTEX namespace tl { namespace detail { template struct is_trivially_copy_constructible : std::is_trivially_copy_constructible {}; -# ifdef _GLIBCXX_VECTOR +#ifdef _GLIBCXX_VECTOR template struct is_trivially_copy_constructible> : std::is_trivially_copy_constructible {}; -# endif +#endif } // namespace detail } // namespace tl -# endif +#endif -# define TL_OPTIONAL_IS_TRIVIALLY_COPY_CONSTRUCTIBLE(T) \ - tl::detail::is_trivially_copy_constructible::value -# define TL_OPTIONAL_IS_TRIVIALLY_COPY_ASSIGNABLE(T) \ - std::is_trivially_copy_assignable::value -# define TL_OPTIONAL_IS_TRIVIALLY_DESTRUCTIBLE(T) std::is_trivially_destructible::value +#define TL_OPTIONAL_IS_TRIVIALLY_COPY_CONSTRUCTIBLE(T) \ + tl::detail::is_trivially_copy_constructible::value +#define TL_OPTIONAL_IS_TRIVIALLY_COPY_ASSIGNABLE(T) \ + std::is_trivially_copy_assignable::value +#define TL_OPTIONAL_IS_TRIVIALLY_DESTRUCTIBLE(T) std::is_trivially_destructible::value #else -# define TL_OPTIONAL_IS_TRIVIALLY_COPY_CONSTRUCTIBLE(T) \ - std::is_trivially_copy_constructible::value -# define TL_OPTIONAL_IS_TRIVIALLY_COPY_ASSIGNABLE(T) \ - std::is_trivially_copy_assignable::value -# define TL_OPTIONAL_IS_TRIVIALLY_DESTRUCTIBLE(T) std::is_trivially_destructible::value +#define TL_OPTIONAL_IS_TRIVIALLY_COPY_CONSTRUCTIBLE(T) \ + std::is_trivially_copy_constructible::value +#define TL_OPTIONAL_IS_TRIVIALLY_COPY_ASSIGNABLE(T) \ + std::is_trivially_copy_assignable::value +#define TL_OPTIONAL_IS_TRIVIALLY_DESTRUCTIBLE(T) std::is_trivially_destructible::value #endif #if __cplusplus > 201103L -# define TL_OPTIONAL_CXX14 +#define TL_OPTIONAL_CXX14 #endif // constexpr implies const in C++11, not C++14 #if (__cplusplus == 201103L || defined(TL_OPTIONAL_MSVC2015) || defined(TL_OPTIONAL_GCC49)) -# define TL_OPTIONAL_11_CONSTEXPR +#define TL_OPTIONAL_11_CONSTEXPR #else -# define TL_OPTIONAL_11_CONSTEXPR constexpr +#define TL_OPTIONAL_11_CONSTEXPR constexpr #endif namespace tl { #ifndef TL_MONOSTATE_INPLACE_MUTEX -# define TL_MONOSTATE_INPLACE_MUTEX +#define TL_MONOSTATE_INPLACE_MUTEX /// Used to represent an optional with no data; essentially a bool class monostate {}; @@ -120,7 +120,7 @@ class optional; namespace detail { #ifndef TL_TRAITS_MUTEX -# define TL_TRAITS_MUTEX +#define TL_TRAITS_MUTEX // C++14-style aliases for brevity template using remove_const_t = typename std::remove_const::type; @@ -142,14 +142,14 @@ template struct conjunction : std::conditional, B>::type {}; -# if defined(_LIBCPP_VERSION) && __cplusplus == 201103L -# define TL_TRAITS_LIBCXX_MEM_FN_WORKAROUND -# endif +#if defined(_LIBCPP_VERSION) && __cplusplus == 201103L +#define TL_TRAITS_LIBCXX_MEM_FN_WORKAROUND +#endif // In C++11 mode, there's an issue in libc++'s std::mem_fn // which results in a hard-error when using it in a noexcept expression // in some cases. This is a check to workaround the common failing case. -# ifdef TL_TRAITS_LIBCXX_MEM_FN_WORKAROUND +#ifdef TL_TRAITS_LIBCXX_MEM_FN_WORKAROUND template struct is_pointer_to_non_const_member_func : std::false_type {}; template @@ -171,14 +171,14 @@ template struct is_const_or_const_ref : std::true_type {}; template struct is_const_or_const_ref : std::true_type {}; -# endif +#endif // std::invoke from C++17 // https://stackoverflow.com/questions/38288042/c11-14-invoke-workaround template::value && is_const_or_const_ref::value)>, -# endif +#endif typename = enable_if_t>::value>, int = 0> constexpr auto invoke(Fn&& f, Args&&... args) noexcept( @@ -212,14 +212,14 @@ using invoke_result = invoke_result_impl; template using invoke_result_t = typename invoke_result::type; -# if defined(_MSC_VER) && _MSC_VER <= 1900 +#if defined(_MSC_VER) && _MSC_VER <= 1900 // TODO make a version which works with MSVC 2015 template struct is_swappable : std::true_type {}; template struct is_nothrow_swappable : std::true_type {}; -# else +#else // https://stackoverflow.com/questions/26744589/what-is-a-proper-way-to-implement-is-swappable-to-test-for-the-swappable-concept namespace swap_adl_tests { // if swap ADL finds this then it would call std::swap otherwise (same @@ -276,12 +276,14 @@ struct is_nothrow_swappable bool, is_swappable::value && ((decltype(detail::swap_adl_tests::uses_std(0))::value && detail::swap_adl_tests::is_std_swap_noexcept::value) || (!decltype(detail::swap_adl_tests::uses_std(0))::value && detail::swap_adl_tests::is_adl_swap_noexcept::value))> { }; -# endif +#endif #endif // std::void_t from C++17 template -struct voider { using type = void; }; +struct voider { + using type = void; +}; template using void_t = typename voider::type; @@ -505,8 +507,7 @@ struct optional_copy_assign_base : optional_move_base { return *this; } optional_copy_assign_base& - operator=(optional_copy_assign_base&& rhs) - = default; + operator=(optional_copy_assign_base&& rhs) = default; }; // This class manages conditionally having a trivial move assignment operator @@ -515,7 +516,7 @@ struct optional_copy_assign_base : optional_move_base { // to make do with a non-trivial move assignment operator even if T is trivially // move assignable #ifndef TL_OPTIONAL_GCC49 -template::value&& std::is_trivially_move_constructible::value&& std::is_trivially_move_assignable::value> +template::value && std::is_trivially_move_constructible::value && std::is_trivially_move_assignable::value> struct optional_move_assign_base : optional_copy_assign_base { using optional_copy_assign_base::optional_copy_assign_base; }; @@ -534,12 +535,11 @@ struct optional_move_assign_base : optional_copy_assign_base { optional_move_assign_base(optional_move_assign_base&& rhs) = default; optional_move_assign_base& - operator=(const optional_move_assign_base& rhs) - = default; + operator=(const optional_move_assign_base& rhs) = default; optional_move_assign_base& operator=(optional_move_assign_base&& rhs) noexcept( - std::is_nothrow_move_constructible::value&& std::is_nothrow_move_assignable::value) { + std::is_nothrow_move_constructible::value && std::is_nothrow_move_assignable::value) { this->assign(std::move(rhs)); return *this; } @@ -553,8 +553,7 @@ struct optional_delete_ctor_base { optional_delete_ctor_base(const optional_delete_ctor_base&) = default; optional_delete_ctor_base(optional_delete_ctor_base&&) noexcept = default; optional_delete_ctor_base& - operator=(const optional_delete_ctor_base&) - = default; + operator=(const optional_delete_ctor_base&) = default; optional_delete_ctor_base& operator=(optional_delete_ctor_base&&) noexcept = default; }; @@ -565,8 +564,7 @@ struct optional_delete_ctor_base { optional_delete_ctor_base(const optional_delete_ctor_base&) = default; optional_delete_ctor_base(optional_delete_ctor_base&&) noexcept = delete; optional_delete_ctor_base& - operator=(const optional_delete_ctor_base&) - = default; + operator=(const optional_delete_ctor_base&) = default; optional_delete_ctor_base& operator=(optional_delete_ctor_base&&) noexcept = default; }; @@ -577,8 +575,7 @@ struct optional_delete_ctor_base { optional_delete_ctor_base(const optional_delete_ctor_base&) = delete; optional_delete_ctor_base(optional_delete_ctor_base&&) noexcept = default; optional_delete_ctor_base& - operator=(const optional_delete_ctor_base&) - = default; + operator=(const optional_delete_ctor_base&) = default; optional_delete_ctor_base& operator=(optional_delete_ctor_base&&) noexcept = default; }; @@ -589,8 +586,7 @@ struct optional_delete_ctor_base { optional_delete_ctor_base(const optional_delete_ctor_base&) = delete; optional_delete_ctor_base(optional_delete_ctor_base&&) noexcept = delete; optional_delete_ctor_base& - operator=(const optional_delete_ctor_base&) - = default; + operator=(const optional_delete_ctor_base&) = default; optional_delete_ctor_base& operator=(optional_delete_ctor_base&&) noexcept = default; }; @@ -605,8 +601,7 @@ struct optional_delete_assign_base { optional_delete_assign_base(const optional_delete_assign_base&) = default; optional_delete_assign_base(optional_delete_assign_base&&) noexcept = default; optional_delete_assign_base& - operator=(const optional_delete_assign_base&) - = default; + operator=(const optional_delete_assign_base&) = default; optional_delete_assign_base& operator=(optional_delete_assign_base&&) noexcept = default; }; @@ -617,8 +612,7 @@ struct optional_delete_assign_base { optional_delete_assign_base(const optional_delete_assign_base&) = default; optional_delete_assign_base(optional_delete_assign_base&&) noexcept = default; optional_delete_assign_base& - operator=(const optional_delete_assign_base&) - = default; + operator=(const optional_delete_assign_base&) = default; optional_delete_assign_base& operator=(optional_delete_assign_base&&) noexcept = delete; }; @@ -629,8 +623,7 @@ struct optional_delete_assign_base { optional_delete_assign_base(const optional_delete_assign_base&) = default; optional_delete_assign_base(optional_delete_assign_base&&) noexcept = default; optional_delete_assign_base& - operator=(const optional_delete_assign_base&) - = delete; + operator=(const optional_delete_assign_base&) = delete; optional_delete_assign_base& operator=(optional_delete_assign_base&&) noexcept = default; }; @@ -641,8 +634,7 @@ struct optional_delete_assign_base { optional_delete_assign_base(const optional_delete_assign_base&) = default; optional_delete_assign_base(optional_delete_assign_base&&) noexcept = default; optional_delete_assign_base& - operator=(const optional_delete_assign_base&) - = delete; + operator=(const optional_delete_assign_base&) = delete; optional_delete_assign_base& operator=(optional_delete_assign_base&&) noexcept = delete; }; @@ -719,7 +711,7 @@ class optional : private detail::optional_move_assign_base, : result(nullopt); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr auto and_then(F&& f) const&& { using result = detail::invoke_result_t; @@ -729,7 +721,7 @@ class optional : private detail::optional_move_assign_base, return has_value() ? detail::invoke(std::forward(f), std::move(**this)) : result(nullopt); } -# endif +#endif #else /// Carries out some operation which returns an optional on the stored /// object if there is one. @@ -763,7 +755,7 @@ class optional : private detail::optional_move_assign_base, : result(nullopt); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr detail::invoke_result_t and_then(F&& f) const&& { using result = detail::invoke_result_t; @@ -773,7 +765,7 @@ class optional : private detail::optional_move_assign_base, return has_value() ? detail::invoke(std::forward(f), std::move(**this)) : result(nullopt); } -# endif +#endif #endif #if defined(TL_OPTIONAL_CXX14) && !defined(TL_OPTIONAL_GCC49) && !defined(TL_OPTIONAL_GCC54) && !defined(TL_OPTIONAL_GCC55) @@ -820,14 +812,14 @@ class optional : private detail::optional_move_assign_base, return optional_map_impl(*this, std::forward(f)); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr decltype(optional_map_impl(std::declval(), std::declval())) map(F&& f) const&& { return optional_map_impl(std::move(*this), std::forward(f)); } -# endif +#endif #endif #if defined(TL_OPTIONAL_CXX14) && !defined(TL_OPTIONAL_GCC49) && !defined(TL_OPTIONAL_GCC54) && !defined(TL_OPTIONAL_GCC55) @@ -874,14 +866,14 @@ class optional : private detail::optional_move_assign_base, return optional_map_impl(*this, std::forward(f)); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr decltype(optional_map_impl(std::declval(), std::declval())) transform(F&& f) const&& { return optional_map_impl(std::move(*this), std::forward(f)); } -# endif +#endif #endif /// Calls `f` if the optional is empty @@ -1251,7 +1243,7 @@ class optional : private detail::optional_move_assign_base, /// If one has a value, it is moved to the other and the movee is left /// valueless. void - swap(optional& rhs) noexcept(std::is_nothrow_move_constructible::value&& detail::is_nothrow_swappable::value) { + swap(optional& rhs) noexcept(std::is_nothrow_move_constructible::value && detail::is_nothrow_swappable::value) { using std::swap; if (has_value()) { if (rhs.has_value()) { @@ -1593,7 +1585,7 @@ class optional { : result(nullopt); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr auto and_then(F&& f) const&& { using result = detail::invoke_result_t; @@ -1603,7 +1595,7 @@ class optional { return has_value() ? detail::invoke(std::forward(f), **this) : result(nullopt); } -# endif +#endif #else /// Carries out some operation which returns an optional on the stored /// object if there is one. @@ -1637,7 +1629,7 @@ class optional { : result(nullopt); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr detail::invoke_result_t and_then(F&& f) const&& { using result = detail::invoke_result_t; @@ -1647,7 +1639,7 @@ class optional { return has_value() ? detail::invoke(std::forward(f), **this) : result(nullopt); } -# endif +#endif #endif #if defined(TL_OPTIONAL_CXX14) && !defined(TL_OPTIONAL_GCC49) && !defined(TL_OPTIONAL_GCC54) && !defined(TL_OPTIONAL_GCC55) @@ -1694,14 +1686,14 @@ class optional { return detail::optional_map_impl(*this, std::forward(f)); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr decltype(detail::optional_map_impl(std::declval(), std::declval())) map(F&& f) const&& { return detail::optional_map_impl(std::move(*this), std::forward(f)); } -# endif +#endif #endif #if defined(TL_OPTIONAL_CXX14) && !defined(TL_OPTIONAL_GCC49) && !defined(TL_OPTIONAL_GCC54) && !defined(TL_OPTIONAL_GCC55) @@ -1750,14 +1742,14 @@ class optional { return detail::optional_map_impl(*this, std::forward(f)); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr decltype(detail::optional_map_impl(std::declval(), std::declval())) transform(F&& f) const&& { return detail::optional_map_impl(std::move(*this), std::forward(f)); } -# endif +#endif #endif /// Calls `f` if the optional is empty diff --git a/libs/libvtrutil/src/vpr_error.h b/libs/libvtrutil/src/vpr_error.h index 16ba3891b12..19813253625 100644 --- a/libs/libvtrutil/src/vpr_error.h +++ b/libs/libvtrutil/src/vpr_error.h @@ -78,12 +78,12 @@ void vpr_throw_opt(enum e_vpr_error type, const char* psz_func_pretty_name, cons // information, so we prefer to use it if possible #define VPR_THROW_FUNCTION __func__ #ifdef __GNUC__ -# ifdef __GNUC_MINOR__ -# if __GNUC__ >= 2 && __GNUC_MINOR__ > 6 -# undef VPR_THROW_FUNCTION -# define VPR_THROW_FUNCTION __PRETTY_FUNCTION__ -# endif -# endif +#ifdef __GNUC_MINOR__ +#if __GNUC__ >= 2 && __GNUC_MINOR__ > 6 +#undef VPR_THROW_FUNCTION +#define VPR_THROW_FUNCTION __PRETTY_FUNCTION__ +#endif +#endif #endif /* diff --git a/libs/libvtrutil/src/vtr_assert.h b/libs/libvtrutil/src/vtr_assert.h index ba63a4bb573..e17448a0c89 100644 --- a/libs/libvtrutil/src/vtr_assert.h +++ b/libs/libvtrutil/src/vtr_assert.h @@ -29,57 +29,57 @@ // Set a default assertion level if none is specified #ifndef VTR_ASSERT_LEVEL -# define VTR_ASSERT_LEVEL 2 +#define VTR_ASSERT_LEVEL 2 #endif // Enable the assertions based on the specified level #if VTR_ASSERT_LEVEL >= 4 -# define VTR_ASSERT_DEBUG_ENABLED +#define VTR_ASSERT_DEBUG_ENABLED #endif #if VTR_ASSERT_LEVEL >= 3 -# define VTR_ASSERT_SAFE_ENABLED +#define VTR_ASSERT_SAFE_ENABLED #endif #if VTR_ASSERT_LEVEL >= 2 -# define VTR_ASSERT_ENABLED +#define VTR_ASSERT_ENABLED #endif #if VTR_ASSERT_LEVEL >= 1 -# define VTR_ASSERT_OPT_ENABLED +#define VTR_ASSERT_OPT_ENABLED #endif // Define the user assertion macros #ifdef VTR_ASSERT_DEBUG_ENABLED -# define VTR_ASSERT_DEBUG(expr) VTR_ASSERT_IMPL(expr, nullptr) -# define VTR_ASSERT_DEBUG_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) +#define VTR_ASSERT_DEBUG(expr) VTR_ASSERT_IMPL(expr, nullptr) +#define VTR_ASSERT_DEBUG_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) #else -# define VTR_ASSERT_DEBUG(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) -# define VTR_ASSERT_DEBUG_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) +#define VTR_ASSERT_DEBUG(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) +#define VTR_ASSERT_DEBUG_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) #endif #ifdef VTR_ASSERT_SAFE_ENABLED -# define VTR_ASSERT_SAFE(expr) VTR_ASSERT_IMPL(expr, nullptr) -# define VTR_ASSERT_SAFE_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) +#define VTR_ASSERT_SAFE(expr) VTR_ASSERT_IMPL(expr, nullptr) +#define VTR_ASSERT_SAFE_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) #else -# define VTR_ASSERT_SAFE(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) -# define VTR_ASSERT_SAFE_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) +#define VTR_ASSERT_SAFE(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) +#define VTR_ASSERT_SAFE_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) #endif #ifdef VTR_ASSERT_ENABLED -# define VTR_ASSERT(expr) VTR_ASSERT_IMPL(expr, nullptr) -# define VTR_ASSERT_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) +#define VTR_ASSERT(expr) VTR_ASSERT_IMPL(expr, nullptr) +#define VTR_ASSERT_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) #else -# define VTR_ASSERT(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) -# define VTR_ASSERT_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) +#define VTR_ASSERT(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) +#define VTR_ASSERT_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) #endif #ifdef VTR_ASSERT_OPT_ENABLED -# define VTR_ASSERT_OPT(expr) VTR_ASSERT_IMPL(expr, nullptr) -# define VTR_ASSERT_OPT_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) +#define VTR_ASSERT_OPT(expr) VTR_ASSERT_IMPL(expr, nullptr) +#define VTR_ASSERT_OPT_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) #else -# define VTR_ASSERT_OPT(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) -# define VTR_ASSERT_OPT_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) +#define VTR_ASSERT_OPT(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) +#define VTR_ASSERT_OPT_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) #endif /** @@ -124,12 +124,12 @@ */ #define VTR_ASSERT_FUNCTION __func__ #ifdef __GNUC__ -# ifdef __GNUC_MINOR__ -# if __GNUC__ >= 2 && __GNUC_MINOR__ > 6 -# undef VTR_ASSERT_FUNCTION -# define VTR_ASSERT_FUNCTION __PRETTY_FUNCTION__ -# endif -# endif +#ifdef __GNUC_MINOR__ +#if __GNUC__ >= 2 && __GNUC_MINOR__ > 6 +#undef VTR_ASSERT_FUNCTION +#define VTR_ASSERT_FUNCTION __PRETTY_FUNCTION__ +#endif +#endif #endif namespace vtr { diff --git a/libs/libvtrutil/src/vtr_flat_map.h b/libs/libvtrutil/src/vtr_flat_map.h index 2c0b34f8536..bc857159bdb 100644 --- a/libs/libvtrutil/src/vtr_flat_map.h +++ b/libs/libvtrutil/src/vtr_flat_map.h @@ -21,7 +21,7 @@ class flat_map2; * @brief A function to create a flat map * * Helper function to create a flat map from a vector of pairs - * without haveing to explicity specify the key and value types + * without having to explicitly specify the key and value types */ template flat_map make_flat_map(std::vector>&& vec) { @@ -435,7 +435,7 @@ template class flat_map2 : public flat_map { public: ///@brief Constructor - flat_map2() {} + flat_map2() noexcept {} explicit flat_map2(std::vector::value_type>&& values) : flat_map(std::move(values)) {} diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index 7cc17c7d74c..d459653b0a1 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -122,7 +122,7 @@ template class Rect { public: //Constructors ///@brief default constructor - Rect(); + Rect() noexcept; ///@brief construct using 4 vertex Rect(T left_val, T bottom_val, T right_val, T top_val); @@ -183,6 +183,9 @@ class Rect { ///@brief Returns true if other is contained within the rectangle (including all edges) bool contains(const Rect& other) const; + ///@brief Returns true if other strictly overlaps this rectangle (two rectangles that only share an edge do not overlap) + bool strictly_overlaps(const Rect& other) const; + /** * @brief Checks whether the rectangle is empty * diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp index 6485f8337cf..6cc932ae4a9 100644 --- a/libs/libvtrutil/src/vtr_geometry.tpp +++ b/libs/libvtrutil/src/vtr_geometry.tpp @@ -91,7 +91,7 @@ Point& Point::operator-=(const Point& rhs) { * Rect */ template -Rect::Rect() +Rect::Rect() noexcept : Rect(Point(0, 0), Point(0, 0)) { //pass } @@ -192,6 +192,12 @@ bool Rect::contains(const Rect& other) const { && other.ymin() >= ymin() && other.ymax() <= ymax(); } +template +bool Rect::strictly_overlaps(const Rect& other) const { + return xmin() < other.xmax() && xmax() > other.xmin() + && ymax() > other.ymin() && ymin() < other.ymax(); +} + template bool Rect::empty() const { return xmax() <= xmin() || ymax() <= ymin(); diff --git a/libs/libvtrutil/src/vtr_log.h b/libs/libvtrutil/src/vtr_log.h index 3c52e249d9d..d9b340d1214 100644 --- a/libs/libvtrutil/src/vtr_log.h +++ b/libs/libvtrutil/src/vtr_log.h @@ -13,8 +13,10 @@ * * Three types of log message types are defined: * - VTR_LOG : The standard 'info' type log message - * - VTR_LOG_WARN : A warning log message. This represents unusual condition that may indicate an issue but executiom continues - * - VTR_LOG_ERROR : An error log message. This represents a clear issue that should result in stopping the program execution. Please note that using this log message will not actually terminate the program. So a VtrError should be thrown after all the neccessary VTR_LOG_ERROR messages are printed. + * - VTR_LOG_WARN : A warning log message. This represents an unusual condition that may indicate an issue but execution continues + * - VTR_LOG_ERROR : An error log message. This represents a clear issue that should result in stopping the program execution. + * Please note that using this log message will not actually terminate the program. So a VtrError should be thrown + * after all the necessary VTR_LOG_ERROR messages are printed. * * For example: * @@ -27,7 +29,7 @@ * * Each of the three message types also have a VTR_LOGV_* variant, * which will cause the message to be logged if a user-defined condition - * is satisifed. + * is satisfied. * * For example: * @@ -118,11 +120,11 @@ // Debug logging macros #ifdef VTR_ENABLE_DEBUG_LOGGING //Enable -# define VTR_LOG_DEBUG(...) VTR_LOG(__VA_ARGS__) -# define VTR_LOGV_DEBUG(expr, ...) VTR_LOGV(expr, __VA_ARGS__) +#define VTR_LOG_DEBUG(...) VTR_LOG(__VA_ARGS__) +#define VTR_LOGV_DEBUG(expr, ...) VTR_LOGV(expr, __VA_ARGS__) #else //Disable -# define VTR_LOG_DEBUG(...) VTR_LOG_NOP(__VA_ARGS__) -# define VTR_LOGV_DEBUG(expr, ...) VTR_LOGV_NOP(expr, __VA_ARGS__) +#define VTR_LOG_DEBUG(...) VTR_LOG_NOP(__VA_ARGS__) +#define VTR_LOGV_DEBUG(expr, ...) VTR_LOGV_NOP(expr, __VA_ARGS__) #endif namespace vtr { diff --git a/libs/libvtrutil/src/vtr_logic.h b/libs/libvtrutil/src/vtr_logic.h index b43ee49291e..21b08fea22b 100644 --- a/libs/libvtrutil/src/vtr_logic.h +++ b/libs/libvtrutil/src/vtr_logic.h @@ -4,12 +4,12 @@ #define VTR_LOGIC_H #ifdef FALSE -# undef FALSE +#undef FALSE #endif #define FALSE FALSE #ifdef TRUE -# undef TRUE +#undef TRUE #endif #define TRUE TRUE diff --git a/libs/libvtrutil/src/vtr_memory.cpp b/libs/libvtrutil/src/vtr_memory.cpp index 39d6b244b13..4bea9f1c652 100644 --- a/libs/libvtrutil/src/vtr_memory.cpp +++ b/libs/libvtrutil/src/vtr_memory.cpp @@ -10,9 +10,9 @@ #include "vtr_log.h" #ifndef __GLIBC__ -# include +#include #else -# include +#include #endif namespace vtr { @@ -164,7 +164,7 @@ void free_chunk_memory(t_chunk* chunk_info) { while (curr_ptr != nullptr) { /* Must cast pointers to type char*, since the're of type void*, which delete can't * be called on.*/ - delete[]((char*)curr_ptr->data_vptr); /* Free memory "chunk". */ + delete[] ((char*)curr_ptr->data_vptr); /* Free memory "chunk". */ prev_ptr = curr_ptr; curr_ptr = curr_ptr->next; delete (t_linked_vptr*)prev_ptr; /* Free memory used to track "chunk". */ diff --git a/libs/libvtrutil/src/vtr_memory.h b/libs/libvtrutil/src/vtr_memory.h index 72e92ebe8f8..4c9877ec2cc 100644 --- a/libs/libvtrutil/src/vtr_memory.h +++ b/libs/libvtrutil/src/vtr_memory.h @@ -5,8 +5,8 @@ #include #ifdef _WIN32 -# include -# include +#include +#include #endif namespace vtr { diff --git a/libs/libvtrutil/src/vtr_ndmatrix.h b/libs/libvtrutil/src/vtr_ndmatrix.h index b7d6f030d5d..a9a41ff41b4 100644 --- a/libs/libvtrutil/src/vtr_ndmatrix.h +++ b/libs/libvtrutil/src/vtr_ndmatrix.h @@ -387,10 +387,10 @@ class NdMatrix : public NdMatrixBase { // Peel off the first dimension return NdMatrixProxy( - this->dim_sizes_.data() + 1, //Pass the dimension information - this->dim_strides_.data() + 1, //Pass the stride for the next dimension - this->dim_strides_[0] * index, //Advance to index in this dimension - this->data_); //Pass the base pointer + this->dim_sizes_.data() + 1, //Pass the dimension information + this->dim_strides_.data() + 1, //Pass the stride for the next dimension + this->dim_strides_[0] * index, //Advance to index in this dimension + this->data_); //Pass the base pointer } /** @@ -438,4 +438,3 @@ using Matrix = NdMatrix; } // namespace vtr #endif - diff --git a/libs/libvtrutil/src/vtr_ndoffsetmatrix.h b/libs/libvtrutil/src/vtr_ndoffsetmatrix.h index f85ebc72008..0e1001239bc 100644 --- a/libs/libvtrutil/src/vtr_ndoffsetmatrix.h +++ b/libs/libvtrutil/src/vtr_ndoffsetmatrix.h @@ -63,7 +63,7 @@ class NdOffsetMatrixProxy { * dim_stride: The stride of this dimension (i.e. how many element in memory between indicies of this dimension) * start: Pointer to the start of the sub-matrix this proxy represents */ - NdOffsetMatrixProxy(const DimRange* dim_ranges, size_t idim, size_t dim_stride, T* start) + NdOffsetMatrixProxy(const DimRange* dim_ranges, size_t idim, size_t dim_stride, T* start) : dim_ranges_(dim_ranges) , idim_(idim) , dim_stride_(dim_stride) @@ -116,7 +116,7 @@ class NdOffsetMatrixProxy { * - dim_stride: The stride of this dimension (i.e. how many element in memory between indicies of this dimension) * - start: Pointer to the start of the sub-matrix this proxy represents */ - NdOffsetMatrixProxy(const DimRange* dim_ranges, size_t idim, size_t dim_stride, T* start) + NdOffsetMatrixProxy(const DimRange* dim_ranges, size_t idim, size_t dim_stride, T* start) : dim_ranges_(dim_ranges) , idim_(idim) , dim_stride_(dim_stride) diff --git a/libs/libvtrutil/src/vtr_prefix_sum.h b/libs/libvtrutil/src/vtr_prefix_sum.h new file mode 100644 index 00000000000..31635904f1b --- /dev/null +++ b/libs/libvtrutil/src/vtr_prefix_sum.h @@ -0,0 +1,285 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Definition of the Prefix Sum class which enables O(1) time-complexity + * sums over regions of an unchanging grid of values. + */ + +#pragma once + +#include +#include +#include "vtr_assert.h" +#include "vtr_ndmatrix.h" + +namespace vtr { + +/** + * @brief 1D Prefix Sum manager class. + * + * Given an array of values, it may be necessary to find the sum of values + * within a continuous sub-section of the array. If this operation needs to be + * performed many times, this may be expensive in runtime to calculate. + * + * If the array of values does not change, we can create a prefix sum which will + * allow us to get the sum of values in some continuous sub-section of the array + * in O(1) time, instead of O(k) time where k is the number of values in the + * sub-section. + * + * This class has a space complexity of O(l) where l is the length of the array + * of values. + * + * + * Static Array of Values Example (values stored in a vector): + * + * std::vector vals = {...}; + * + * // Build the Prefix Sum + * vtr::PrefixSum1D prefix_sum(vals); + * + * // Compute the sum of the values between index 3 and 7 of the array (inclusive) + * float sum = prefix_sum.get_sum(3, 7); + * + * + * Dynamic Vector of Values Example (values derived at runtime): + * + * // Build the Prefix Sum using a lambda + * vtr::PrefixSum1D prefix_sum(length, [&](size_t x) { + * // This lambda returns the value that would be in the array at index x. + * return static_cast(x * x); + * }); + * + * // Compute the sum of the values between index 0 and 5 of the array (inclusive) + * float sum = prefix_sum.get_sum(0, 5); + */ +template +class PrefixSum1D { + public: + PrefixSum1D() = default; + + /** + * @brief Construct the 1D prefix sum. + * + * This pre-computes the sums of values in the array, making it faster to + * get the sum of sub-regions of the array later. + * + * This constructor has a time complexity of O(length) + * + * @param length + * The length of the array to a make a prefix sum of. + * @param lookup + * A lambda function which will return the value in the array at + * the given x index. This is a lambda to allow a prefix sum to be + * created, even if the values in the array are not stored in a + * vector (may be computed on the spot). + * @param zero + * What is zero for this data type. For most basic data types (like + * int float, etc.) this parameter can be ignored; for more complex + * data classes (like multi-dimensional vectors) this is necessary + * to be passed in. + */ + PrefixSum1D(size_t length, std::function lookup, T zero = T()) + : prefix_sum_(length + 1, zero) { + // The first value in the prefix sum is already initialized to 0. + + // Initialize the prefix sum. The prefix sum at position x is the sum + // of all values in the original array from 0 to x - 1. + for (size_t x = 1; x < length + 1; x++) { + prefix_sum_[x] = prefix_sum_[x - 1] + lookup(x - 1); + } + } + + /** + * @brief Construct the 1D prefix sum from a vector. + */ + PrefixSum1D(std::vector vals, T zero = T()) + : PrefixSum1D( + vals.size(), + [&](size_t x) noexcept { + return vals[x]; + }, + zero) {} + + /** + * @brief Get the sum of all values in the original array of values between + * lower_x and upper_x (inclusive). + * + * Inclusive means that the sum will include the values at lower_x and + * upper_x. + * + * This method has O(1) time complexity. + */ + T get_sum(size_t lower_x, size_t upper_x) const { + // Some safety asserts. + VTR_ASSERT_SAFE_MSG(lower_x <= upper_x, "lower_x is larger than upper_x"); + VTR_ASSERT_SAFE_MSG(lower_x < prefix_sum_.size() - 1, "lower_x out of range"); + VTR_ASSERT_SAFE_MSG(upper_x < prefix_sum_.size() - 1, "upper_x out of range"); + + // The sum of the region lower_x to upper_x inclusive is equal to + // - The sum from 0 to upper_x + // - Minus the sum from 0 to lower_x - 1 + // Note: These are all offset by 1 since the first value is zero. This + // saves us from having to do bound checking. + return prefix_sum_[upper_x + 1] - prefix_sum_[lower_x]; + } + + private: + /** + * @brief The 1D prefix sum of the original array of values. + * + * Index x of the prefix sum contains the sum of all values in the original + * array from 0 to x - 1. The first value in this array is 0. By setting the + * first value in the array to 0, we can avoid bound checking. This data + * structure has the special property that the sum of any sub-array can be + * computed in O(1) time. + */ + std::vector prefix_sum_; +}; + +/** + * @brief 2D Prefix Sum manager class. + * + * Given a 2D grid of values, it may be necessary to find the sum of values + * within some rectangular sub-region of that grid. If this operation needs to + * be performed many times, this may be expensive in runtime to calculate. + * + * If the grid of values does not change, we can create a prefix sum which will + * allow us to get the sum of values in some rectangular sub-region of the + * grid in O(1) time, instead of O(k) time where k is the number of values + * in the region. + * + * This class has a space complexity of O(w * h) where w and h are the width + * and height of the grid of values. + * + * + * Static Matrix of Values Example (values stored in a matrix): + * + * vtr::NdMatrix vals({w, h}); + * + * // ... Initialize vals + * + * // Build the Prefix Sum + * vtr::PrefixSum2D prefix_sum(vals); + * + * // Compute the sum of the rectangular region from (1, 2) to (3, 4) inclusive. + * float sum = prefix_sum.get_sum(1, 2, 3, 4); + * + * + * Dynamic Matrix of Values Example (values derived at runtime): + * + * // Build the Prefix Sum using a lambda + * vtr::PrefixSum2D prefix_sum(w, h, [&](size_t x, size_t y) { + * // This lambda returns the value that would be in the matrix at (x, y) + * return (x + y) / 2.f; + * }); + * + * // Compute the sum of the rectangular region from (0, 4) to (3, 5) inclusive. + * float sum = prefix_sum.get_sum(0, 4, 3, 5); + */ +template +class PrefixSum2D { + public: + PrefixSum2D() = default; + + /** + * @brief Construct the 2D prefix sum. + * + * This pre-computes the sums of values in the grid, making it faster to + * get the sum of sub-regions of the grid later. + * + * This constructor has a time complexity of O(w * h). + * + * @param w + * The width of the grid of values to make a prefix sum over. + * @param h + * The height of the grid of values to make a prefix sum over. + * @param lookup + * A lambda function which will return the value in the grid at the + * given x, y position. This is a lambda to allow a prefix sum to + * be created, even if the values in the grid are not stored in + * a matrix (may be computed at runtime). + * @param zero + * What is zero for this data type. For most basic data types (like + * int, float, etc.) this parameter can be ignored; for more complex + * data classes (like multi-dimensional vectors) this is necessary + * to be passed in. + */ + PrefixSum2D(size_t w, size_t h, std::function lookup, T zero = T()) + : prefix_sum_({w + 1, h + 1}, zero) { + // The first row and first column should already be initialized to zero. + + // Initialize the prefix sum. The prefix sum at position (x, y) is the + // sum of all values in the original matrix in the rectangle from (0, 0) + // to (x - 1, y - 1) inclusive. + for (size_t x = 1; x < w + 1; x++) { + for (size_t y = 1; y < h + 1; y++) { + prefix_sum_[x][y] = prefix_sum_[x - 1][y] + + prefix_sum_[x][y - 1] + + lookup(x - 1, y - 1) + - prefix_sum_[x - 1][y - 1]; + } + } + } + + /** + * @brief Constructs a 2D prefix sum from a 2D grid of values. + */ + PrefixSum2D(const vtr::NdMatrix& vals, T zero = T()) + : PrefixSum2D( + vals.dim_size(0), + vals.dim_size(1), + [&](size_t x, size_t y) { + return vals[x][y]; + }, + zero) {} + + /** + * @brief Get the sum of all values in the original grid of values between + * x = [lower_x, upper_x] and y = [lower_y, upper_y]. + * + * This sum is inclusive, so it also sums the values at (upper_x, upper_y). + * + * This method has O(1) time complexity. + */ + T get_sum(size_t lower_x, size_t lower_y, size_t upper_x, size_t upper_y) const { + // Some safety asserts. + VTR_ASSERT_SAFE_MSG(lower_x <= upper_x, "lower_x is larger than upper_x"); + VTR_ASSERT_SAFE_MSG(lower_y <= upper_y, "lower_y is larger than upper_y"); + VTR_ASSERT_SAFE_MSG(lower_x < prefix_sum_.dim_size(0) - 1, "lower_x out of range"); + VTR_ASSERT_SAFE_MSG(upper_x < prefix_sum_.dim_size(0) - 1, "upper_x out of range"); + VTR_ASSERT_SAFE_MSG(lower_y < prefix_sum_.dim_size(1) - 1, "lower_y out of range"); + VTR_ASSERT_SAFE_MSG(upper_y < prefix_sum_.dim_size(1) - 1, "upper_y out of range"); + + // The sum of the region (lower_x, lower_y) to (upper_x, upper_y) + // inclusive is equal to: + // - The sum of the region (0, 0) to (upper_x, upper_y) + // - Minus the sum of the region (0, 0) to (lower_x - 1, upper_y) + // - Remove the part below the region + // - Minus the sum of the region (0, 0) to (upper_x, lower_y - 1) + // - Remove the part left of the region + // - Plus the sum of the region (0, 0) to (lower_x - 1, lower_y - 1) + // - Add back on the lower-left corner which was subtracted twice. + // Note: all of these are offset by 1 since the first row and column + // are all zeros. This allows us to avoid bounds checking when + // lower_x or lower_y are 0. + return prefix_sum_[upper_x + 1][upper_y + 1] + - prefix_sum_[lower_x][upper_y + 1] + - prefix_sum_[upper_x + 1][lower_y] + + prefix_sum_[lower_x][lower_y]; + } + + private: + /** + * @brief The 2D prefix sum of the original grid of values. + * + * Position (x, y) of the prefix sum contains the sum of all values in the + * rectangle (0, 0) -> (x - 1, y - 1) inclusive. The first row and column + * are all zeros. By setting these to zero, we can avoid bound checking. + * This data structure has the special property that the sum of any + * rectangular region can be computed in O(1) time. + */ + vtr::NdMatrix prefix_sum_; +}; + +} // namespace vtr diff --git a/libs/libvtrutil/src/vtr_random.cpp b/libs/libvtrutil/src/vtr_random.cpp index eb1756702da..6bef9c41198 100644 --- a/libs/libvtrutil/src/vtr_random.cpp +++ b/libs/libvtrutil/src/vtr_random.cpp @@ -23,7 +23,7 @@ int RandomNumberGenerator::irand(int imax) { // state = (state * IA + IC) % IM; random_state_ = random_state_ * IA + IC; // Use overflow to wrap - ival = random_state_ & (IM - 1); // Modulus + ival = random_state_ & (IM - 1); // Modulus ival = (int)((float)ival * (float)(imax + 0.999) / (float)IM); if constexpr (CHECK_RAND_CONSTEXPR) { @@ -42,7 +42,7 @@ int RandomNumberGenerator::irand(int imax) { float RandomNumberGenerator::frand() { random_state_ = random_state_ * IA + IC; /* Use overflow to wrap */ - int ival = random_state_ & (IM - 1); /* Modulus */ + int ival = random_state_ & (IM - 1); /* Modulus */ float fval = (float)ival / (float)IM; if constexpr (CHECK_RAND_CONSTEXPR) { diff --git a/libs/libvtrutil/src/vtr_random.h b/libs/libvtrutil/src/vtr_random.h index 76c8bb37912..15614b7141e 100644 --- a/libs/libvtrutil/src/vtr_random.h +++ b/libs/libvtrutil/src/vtr_random.h @@ -53,7 +53,6 @@ class RandomNumberGenerator : public RandomNumberGeneratorInterface { state_t random_state_ = 0; }; - class RngContainer : public RandomNumberGeneratorInterface { public: RngContainer(const RngContainer&) = delete; @@ -67,7 +66,6 @@ class RngContainer : public RandomNumberGeneratorInterface { inline virtual float frand() override { return rng_->frand(); } private: - std::unique_ptr rng_; #ifdef SPEC_CPU diff --git a/libs/libvtrutil/src/vtr_rusage.cpp b/libs/libvtrutil/src/vtr_rusage.cpp index a3b74c04c86..466e8264172 100644 --- a/libs/libvtrutil/src/vtr_rusage.cpp +++ b/libs/libvtrutil/src/vtr_rusage.cpp @@ -1,8 +1,8 @@ #include "vtr_rusage.h" #ifdef __unix__ -# include -# include +#include +#include #endif namespace vtr { diff --git a/libs/libvtrutil/src/vtr_strong_id.h b/libs/libvtrutil/src/vtr_strong_id.h index 5c738770d57..672dbae1e7e 100644 --- a/libs/libvtrutil/src/vtr_strong_id.h +++ b/libs/libvtrutil/src/vtr_strong_id.h @@ -167,7 +167,7 @@ template constexpr bool operator!=(const StrongId& lhs, const StrongId& rhs); template -constexpr bool operator<(const StrongId& lhs, const StrongId& rhs); +constexpr bool operator<(const StrongId& lhs, const StrongId& rhs) noexcept; template std::ostream& operator<<(std::ostream& out, const StrongId& rhs); @@ -182,11 +182,11 @@ class StrongId { static constexpr StrongId INVALID() noexcept { return StrongId(); } ///@brief Default to the sentinel value - constexpr StrongId() + constexpr StrongId() noexcept : id_(sentinel) {} ///@brief Only allow explicit constructions from a raw Id (no automatic conversions) - explicit constexpr StrongId(T id) + explicit constexpr StrongId(T id) noexcept : id_(id) {} // Allow some explicit conversion to useful types: @@ -216,7 +216,7 @@ class StrongId { ///@brief != operator friend constexpr bool operator!= <>(const StrongId& lhs, const StrongId& rhs); ///@brief < operator - friend constexpr bool operator< <>(const StrongId& lhs, const StrongId& rhs); + friend constexpr bool operator< <>(const StrongId& lhs, const StrongId& rhs) noexcept; /** * @brief to be able to print them out @@ -241,7 +241,7 @@ constexpr bool operator!=(const StrongId& lhs, const StrongId< ///@brief operator < Needed for std::map-like containers template -constexpr bool operator<(const StrongId& lhs, const StrongId& rhs) { +constexpr bool operator<(const StrongId& lhs, const StrongId& rhs) noexcept { return lhs.id_ < rhs.id_; } diff --git a/libs/libvtrutil/src/vtr_strong_id_range.h b/libs/libvtrutil/src/vtr_strong_id_range.h index f22df41f67e..6728f13a174 100644 --- a/libs/libvtrutil/src/vtr_strong_id_range.h +++ b/libs/libvtrutil/src/vtr_strong_id_range.h @@ -46,9 +46,9 @@ class StrongIdIterator { using difference_type = ssize_t; ///@brief Dereference operator (*) - StrongId& operator*() { + StrongId operator*() const { VTR_ASSERT_SAFE(bool(id_)); - return this->id_; + return id_; } ///@brief += operator @@ -75,6 +75,14 @@ class StrongIdIterator { return *this; } + ///@brief Post-increment operator + StrongIdIterator operator++(int) { + VTR_ASSERT_SAFE(bool(id_)); + StrongIdIterator temp = *this; // Create a copy of the current object + ++(*this); // Use the pre-increment operator to increment + return temp; // Return the copy + } + ///@brief Decremment operator StrongIdIterator& operator--() { VTR_ASSERT_SAFE(bool(id_)); diff --git a/libs/libvtrutil/src/vtr_thread_pool.h b/libs/libvtrutil/src/vtr_thread_pool.h new file mode 100644 index 00000000000..dbf2f5ed258 --- /dev/null +++ b/libs/libvtrutil/src/vtr_thread_pool.h @@ -0,0 +1,165 @@ +#pragma once + +/** + * @file vtr_thread_pool.h + * @brief A generic thread pool for parallel task execution + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vtr_log.h" +#include "vtr_time.h" + +namespace vtr { + +/** + * A thread pool for parallel task execution. It is a naive + * implementation which uses a queue for each thread and assigns + * tasks in a round robin fashion. + * + * Example usage: + * + * ``` + * vtr::thread_pool pool(4); // 4 threads + * pool.schedule_work([]{ + * // Task body + * }); + * pool.wait_for_all(); // There's no API to wait for a single task + * ``` + */ +class thread_pool { + private: + /** Thread-local data */ + struct ThreadData { + std::thread thread; + /** Per-thread task queue */ + std::queue> task_queue; + + /** Threads wait on cv for a stop signal or a new task + * queue_mutex is required for condition variable */ + std::mutex queue_mutex; + std::condition_variable cv; + bool stop = false; + }; + + /** Container for thread-local data */ + std::vector> threads; + /** Used for round-robin scheduling */ + std::atomic next_thread{0}; + /** Used for wait_for_all */ + std::atomic active_tasks{0}; + + /** Condition variable for wait_for_all */ + std::mutex completion_mutex; + std::condition_variable completion_cv; + + public: + /** Create a thread pool with \p thread_count threads. */ + thread_pool(size_t thread_count) { + threads.reserve(thread_count); + + for (size_t i = 0; i < thread_count; i++) { + auto thread_data = std::make_unique(); + + thread_data->thread = std::thread([&]() { + ThreadData* td = thread_data.get(); + + while (true) { + std::function task; + + { /* Wait until a task is available or stop signal is received */ + std::unique_lock lock(td->queue_mutex); + + td->cv.wait(lock, [td]() { + return td->stop || !td->task_queue.empty(); + }); + + if (td->stop && td->task_queue.empty()) { + return; + } + + /* Fetch a task from the queue */ + task = std::move(td->task_queue.front()); + td->task_queue.pop(); + } + + vtr::Timer task_timer; + task(); + } + }); + + threads.push_back(std::move(thread_data)); + } + } + + /** Schedule a function to be executed on one of the threads. */ + template + void schedule_work(F&& f) { + active_tasks++; + + /* Round-robin thread assignment */ + size_t thread_idx = (next_thread++) % threads.size(); + auto thread_data = threads[thread_idx].get(); + + auto task = [this, f = std::forward(f)]() { + vtr::Timer task_timer; + + try { + f(); + } catch (const std::exception& e) { + VTR_LOG_ERROR("Thread %zu failed task with error: %s\n", + std::this_thread::get_id(), e.what()); + throw; + } catch (...) { + VTR_LOG_ERROR("Thread %zu failed task with unknown error\n", + std::this_thread::get_id()); + throw; + } + + size_t remaining = --active_tasks; + if (remaining == 0) { + completion_cv.notify_all(); + } + }; + + /* Queue new task */ + { + std::lock_guard lock(thread_data->queue_mutex); + thread_data->task_queue.push(std::move(task)); + } + thread_data->cv.notify_one(); + } + + /** Wait until the work queue is empty. + * Note that functions are allowed to schedule new functions. */ + void wait_for_all() { + std::unique_lock lock(completion_mutex); + completion_cv.wait(lock, [this]() { return active_tasks == 0; }); + } + + ~thread_pool() { + /* Stop all threads */ + for (auto& thread_data : threads) { + { + std::lock_guard lock(thread_data->queue_mutex); + thread_data->stop = true; + } + thread_data->cv.notify_one(); + } + + for (auto& thread_data : threads) { + if (thread_data->thread.joinable()) { + thread_data->thread.join(); + } + } + } +}; + +} // namespace vtr diff --git a/libs/libvtrutil/src/vtr_util.cpp b/libs/libvtrutil/src/vtr_util.cpp index b3eef7379eb..eca51b05e90 100644 --- a/libs/libvtrutil/src/vtr_util.cpp +++ b/libs/libvtrutil/src/vtr_util.cpp @@ -12,7 +12,7 @@ #include "vtr_error.h" #if defined(__unix__) -# include //For getpid() +#include //For getpid() #endif namespace vtr { @@ -396,7 +396,7 @@ char* getline(char*& _lineptr, FILE* _stream) { #if defined(__unix__) nread = getdelim(&_lineptr, &_n, '\n', _stream); #elif defined(_WIN32) -# define __WIN_NLTK "\r\n" +#define __WIN_NLTK "\r\n" nread = getdelim(&_lineptr, &_n, __WIN_NLTK, _stream); #endif diff --git a/libs/libvtrutil/src/vtr_vector.h b/libs/libvtrutil/src/vtr_vector.h index be4e5874e98..921238a77d7 100644 --- a/libs/libvtrutil/src/vtr_vector.h +++ b/libs/libvtrutil/src/vtr_vector.h @@ -180,17 +180,20 @@ class vector : private std::vector { vector::const_iterator iter; bool operator!=(const enumerated_iterator& other) const { return iter != other.iter; } - void operator++() { i = key_type(size_t(i) + 1); iter++; } + void operator++() { + i = key_type(size_t(i) + 1); + iter++; + } std::tuple operator*() { return std::tie(i, *iter); } }; struct enumerated_wrapper { const vector& vec; - auto begin() { return enumerated_iterator{ key_type(0), vec.begin() }; } - auto end() { return enumerated_iterator{ key_type(vec.size()), vec.end() }; } + auto begin() { return enumerated_iterator{key_type(0), vec.begin()}; } + auto end() { return enumerated_iterator{key_type(vec.size()), vec.end()}; } }; - return enumerated_wrapper{ *this }; + return enumerated_wrapper{*this}; } public: diff --git a/libs/libvtrutil/test/test_prefix_sum.cpp b/libs/libvtrutil/test/test_prefix_sum.cpp new file mode 100644 index 00000000000..a907615fd4f --- /dev/null +++ b/libs/libvtrutil/test/test_prefix_sum.cpp @@ -0,0 +1,98 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Test cases for the Prefix Sum class in vtr_util. + */ + +#include "catch2/catch_test_macros.hpp" + +#include "vtr_ndmatrix.h" +#include "vtr_prefix_sum.h" + +using namespace Catch; + +TEST_CASE("PrefixSum1D", "[vtr_prefix_sum/PrefixSum1D]") { + // Construct a 1D array to compute the prefix sum over. + std::vector vals = {1.f, 7.f, 2.f, 2.f, 5.f, 6.f, 1.f, 9.f, 1.f, 3.f}; + + // Construct the Prefix Sum. + vtr::PrefixSum1D prefix_sum(vals); + + // Check that the sum of each length 1 region is the original value. + SECTION("construction") { + for (size_t x = 0; x < vals.size(); x++) { + float sum_val = prefix_sum.get_sum(x, x); + REQUIRE(sum_val == vals[x]); + } + } + + float sum_of_all_vals = 0.f; + for (size_t x = 0; x < vals.size(); x++) { + sum_of_all_vals += vals[x]; + } + + // Check that get_sum is working on some testcases. + SECTION("get_sum") { + REQUIRE(prefix_sum.get_sum(0, vals.size() - 1) == sum_of_all_vals); + REQUIRE(prefix_sum.get_sum(0, 2) == 10.f); + REQUIRE(prefix_sum.get_sum(7, 9) == 13.f); + REQUIRE(prefix_sum.get_sum(2, 5) == 15.f); + } +} + +TEST_CASE("PrefixSum2D", "[vtr_prefix_sum/PrefixSum2D]") { + // Construct a 2D grid to compute the prefix sum over. + vtr::NdMatrix vals({4, 4}); + /* + * [ 1 3 9 2 ] + * [ 2 4 0 8 ] + * [ 3 7 1 3 ] + * [ 5 6 9 2 ] + */ + vals[0][0] = 5.f; + vals[1][0] = 6.f; + vals[2][0] = 9.f; + vals[3][0] = 2.f; + vals[0][1] = 3.f; + vals[1][1] = 7.f; + vals[2][1] = 1.f; + vals[3][1] = 3.f; + vals[0][2] = 2.f; + vals[1][2] = 4.f; + vals[2][2] = 0.f; + vals[3][2] = 8.f; + vals[0][3] = 1.f; + vals[1][3] = 3.f; + vals[2][3] = 9.f; + vals[3][3] = 2.f; + + // Construct the Prefix Sum. + vtr::PrefixSum2D prefix_sum(vals); + + // Check that the sum of each 1x1 region is the original value. + SECTION("construction") { + for (size_t x = 0; x < 4; x++) { + for (size_t y = 0; y < 4; y++) { + float sum_val = prefix_sum.get_sum(x, y, x, y); + REQUIRE(sum_val == vals[x][y]); + } + } + } + + float sum_of_all_vals = 0; + for (size_t x = 0; x < 4; x++) { + for (size_t y = 0; y < 4; y++) { + sum_of_all_vals += vals[x][y]; + } + } + + // Check that get_sum is working on some testcases. + SECTION("get_sum") { + REQUIRE(prefix_sum.get_sum(0, 0, 3, 3) == sum_of_all_vals); + REQUIRE(prefix_sum.get_sum(1, 1, 2, 2) == 12.f); + REQUIRE(prefix_sum.get_sum(0, 0, 3, 0) == 22.f); + REQUIRE(prefix_sum.get_sum(0, 0, 0, 3) == 11.f); + REQUIRE(prefix_sum.get_sum(1, 2, 2, 3) == 16.f); + } +} diff --git a/odin_ii/regression_test/parse_result/parse_result.py b/odin_ii/regression_test/parse_result/parse_result.py index 83373489d22..0e3bb7faefc 100755 --- a/odin_ii/regression_test/parse_result/parse_result.py +++ b/odin_ii/regression_test/parse_result/parse_result.py @@ -567,7 +567,7 @@ def compare_instances(header, toml_dict, tbl_entry, golden_tbl_entry): if len(tbl_entry[header]) != len(golden_tbl_entry[header]): return False - for (value, golden_value) in zip(tbl_entry[header], golden_tbl_entry[header]): + for value, golden_value in zip(tbl_entry[header], golden_tbl_entry[header]): if not compare_values(header, toml_dict, value, golden_value): return False @@ -778,7 +778,12 @@ def main(): arguments = parse_shared_args(sys.argv[2:]) exit( - {"display": display, "parse": parse, "join": join, "compare": compare,}.get( + { + "display": display, + "parse": parse, + "join": join, + "compare": compare, + }.get( command, lambda: "Invalid Command" )(arguments) ) diff --git a/odin_ii/regression_test/tools/8_bit_arithmetic_power_output.py b/odin_ii/regression_test/tools/8_bit_arithmetic_power_output.py index 617316e5541..c0800584a71 100644 --- a/odin_ii/regression_test/tools/8_bit_arithmetic_power_output.py +++ b/odin_ii/regression_test/tools/8_bit_arithmetic_power_output.py @@ -11,12 +11,12 @@ def make_output_vector(power): print("c") next_a = 0 for i in range(0, 512): - value = next_a ** power + value = next_a**power output = f"{value:#0{4}x}" print(output[0:2] + output[-2:]) if i % 2 == 1: next_a += 1 - value = next_a ** power + value = next_a**power output = f"{value:#0{4}x}" print(output[0:2] + output[-2:]) print("0x00") diff --git a/odin_ii/regression_test/tools/asr_vector_maker.py b/odin_ii/regression_test/tools/asr_vector_maker.py index b3477e36f7d..27c5262303e 100644 --- a/odin_ii/regression_test/tools/asr_vector_maker.py +++ b/odin_ii/regression_test/tools/asr_vector_maker.py @@ -67,7 +67,7 @@ def make_input_vector(bits): # One for each value (2^bits) # a rising edge for each line ( * 2) # a line for reset ( + 1) - lines = ((2 ** bits) * 2) + 2 + lines = ((2**bits) * 2) + 2 for i in range(0, lines): if i < (lines - 1): inputs[0].append(value) diff --git a/odin_ii/src/ast/ast_elaborate.h b/odin_ii/src/ast/ast_elaborate.h index cf6beb85607..d93f0c51f6c 100644 --- a/odin_ii/src/ast/ast_elaborate.h +++ b/odin_ii/src/ast/ast_elaborate.h @@ -32,4 +32,4 @@ ast_node_t* find_top_module(ast_t* ast); int simplify_ast_module(ast_node_t** ast_module, sc_hierarchy* local_ref); void create_param_table_for_scope(ast_node_t* module_items, sc_hierarchy* local_ref); -#endif \ No newline at end of file +#endif diff --git a/odin_ii/src/ast/ast_loop_unroll.cpp b/odin_ii/src/ast/ast_loop_unroll.cpp index ff522f56e0c..1b0887c5860 100644 --- a/odin_ii/src/ast/ast_loop_unroll.cpp +++ b/odin_ii/src/ast/ast_loop_unroll.cpp @@ -342,7 +342,6 @@ post_condition_function resolve_binary_operation(ast_node_t* node) { } } - /* * (function: resolve_post_condition) * return a lambda which gives the next value diff --git a/odin_ii/src/ast/ast_util.cpp b/odin_ii/src/ast/ast_util.cpp index f60759b6ae9..cff0a438ca7 100644 --- a/odin_ii/src/ast/ast_util.cpp +++ b/odin_ii/src/ast/ast_util.cpp @@ -113,8 +113,7 @@ void add_top_module_to_ast(ast_t* ast, ast_node_t* to_add) { oassert(ast); if (to_add) { ast->top_modules_count += 1; - ast->top_modules - = (ast_node_t**)vtr::realloc(ast->top_modules, sizeof(ast_node_t*) * ast->top_modules_count); + ast->top_modules = (ast_node_t**)vtr::realloc(ast->top_modules, sizeof(ast_node_t*) * ast->top_modules_count); ast->top_modules[ast->top_modules_count - 1] = to_add; } diff --git a/odin_ii/src/config/read_xml_config_file.cpp b/odin_ii/src/config/read_xml_config_file.cpp index b329dbd461b..124c395337f 100644 --- a/odin_ii/src/config/read_xml_config_file.cpp +++ b/odin_ii/src/config/read_xml_config_file.cpp @@ -321,4 +321,4 @@ void read_optimizations(pugi::xml_node a_node, config_t* config, const pugiutil: } return; -} \ No newline at end of file +} diff --git a/odin_ii/src/core/block_memories.cpp b/odin_ii/src/core/block_memories.cpp index 0b3cad7e3ea..fe0717c953e 100644 --- a/odin_ii/src/core/block_memories.cpp +++ b/odin_ii/src/core/block_memories.cpp @@ -1470,4 +1470,4 @@ static void free_block_memory(block_memory_t* to_free) { vtr::free(to_free->memory_id); vtr::free(to_free); -} \ No newline at end of file +} diff --git a/odin_ii/src/core/odin_memory.h b/odin_ii/src/core/odin_memory.h index f681ba5e50a..2b431c9db3c 100644 --- a/odin_ii/src/core/odin_memory.h +++ b/odin_ii/src/core/odin_memory.h @@ -35,9 +35,9 @@ #include "odin_error.h" #ifndef __GLIBC__ -# include +#include #else -# include +#include #endif namespace odin { @@ -138,4 +138,4 @@ void realloc(T** ptr_ref, S _n_bytes) { } } // namespace odin -#endif //ODIN_MEMORY_H \ No newline at end of file +#endif //ODIN_MEMORY_H diff --git a/odin_ii/src/main.cpp b/odin_ii/src/main.cpp index a0bc57d9cae..458be4ae027 100644 --- a/odin_ii/src/main.cpp +++ b/odin_ii/src/main.cpp @@ -46,4 +46,4 @@ int main(int argc, char** argv) { netlist_t* odin_netlist = start_odin_ii(argc, argv); terminate_odin_ii(odin_netlist); return 0; -} \ No newline at end of file +} diff --git a/odin_ii/src/netlist/netlist_statistic.cpp b/odin_ii/src/netlist/netlist_statistic.cpp index 6a2aeef0061..6d8ce8c5711 100644 --- a/odin_ii/src/netlist/netlist_statistic.cpp +++ b/odin_ii/src/netlist/netlist_statistic.cpp @@ -547,4 +547,4 @@ void compute_statistics(netlist_t* netlist, bool display) { printf("\n"); } } -} \ No newline at end of file +} diff --git a/odin_ii/src/utils/hierarchy_util.cpp b/odin_ii/src/utils/hierarchy_util.cpp index 7e5f9556601..72c78914e3d 100644 --- a/odin_ii/src/utils/hierarchy_util.cpp +++ b/odin_ii/src/utils/hierarchy_util.cpp @@ -332,4 +332,4 @@ ast_node_t* resolve_hierarchical_name_reference_by_upward_search(sc_hierarchy* l } return NULL; -} \ No newline at end of file +} diff --git a/odin_ii/src/utils/hierarchy_util.h b/odin_ii/src/utils/hierarchy_util.h index af38204243c..88148de1bc8 100644 --- a/odin_ii/src/utils/hierarchy_util.h +++ b/odin_ii/src/utils/hierarchy_util.h @@ -62,4 +62,4 @@ sc_hierarchy* copy_sc_hierarchy(sc_hierarchy* to_copy); void free_sc_hierarchy(sc_hierarchy* to_free); ast_node_t* resolve_hierarchical_name_reference(sc_hierarchy* local_ref, char* identifier); -#endif \ No newline at end of file +#endif diff --git a/odin_ii/src/utils/odin_types.h b/odin_ii/src/utils/odin_types.h index 2fa18d01f11..8ff837d1114 100644 --- a/odin_ii/src/utils/odin_types.h +++ b/odin_ii/src/utils/odin_types.h @@ -48,9 +48,9 @@ #define ODIN_SHORT_STRING 1 #ifndef DEBUG_ODIN -# define ODIN_STRING_TYPE ODIN_SHORT_STRING +#define ODIN_STRING_TYPE ODIN_SHORT_STRING #else -# define ODIN_STRING_TYPE ODIN_LONG_STRING +#define ODIN_STRING_TYPE ODIN_LONG_STRING #endif #define ODIN_STD_BITWIDTH (sizeof(long) * 8) diff --git a/odin_ii/src/utils/odin_util.cpp b/odin_ii/src/utils/odin_util.cpp index 2597fcfdb9e..4b605607f4e 100644 --- a/odin_ii/src/utils/odin_util.cpp +++ b/odin_ii/src/utils/odin_util.cpp @@ -43,11 +43,11 @@ // for mkdir #ifdef WIN32 -# include -# define getcwd _getcwd +#include +#define getcwd _getcwd #else -# include -# include +#include +#include #endif long shift_left_value_with_overflow_check(long input_value, long shift_by, loc_t loc) { diff --git a/odin_ii/src/utils/scope_util.cpp b/odin_ii/src/utils/scope_util.cpp index 658533b9f47..2d77fd9276d 100644 --- a/odin_ii/src/utils/scope_util.cpp +++ b/odin_ii/src/utils/scope_util.cpp @@ -80,4 +80,4 @@ void push_scope() { /* update current scope */ current_scope = scope_stack.back(); -} \ No newline at end of file +} diff --git a/parmys/CMakeLists.txt b/parmys/CMakeLists.txt index 1df18065428..f2139930d36 100644 --- a/parmys/CMakeLists.txt +++ b/parmys/CMakeLists.txt @@ -35,6 +35,7 @@ target_link_libraries(parmys ) set_target_properties(parmys PROPERTIES PREFIX "") # Avoid extra 'lib' prefix +set_target_properties(parmys PROPERTIES SUFFIX ".so") # Yosys expects the suffix to be '.so' even on macOS add_custom_target(parmys-plugin ALL DEPENDS parmys diff --git a/requirements.txt b/requirements.txt index e6b107c0625..3498cec63c3 100644 --- a/requirements.txt +++ b/requirements.txt @@ -6,7 +6,7 @@ numpy scipy # Python linter and formatter click==8.0.2 # Our version of black needs an older version of click (https://stackoverflow.com/questions/71673404/importerror-cannot-import-name-unicodefun-from-click) -black==21.4b0 +black==24.3.0 pylint==2.7.4 # Surelog diff --git a/utils/fasm/src/fasm.cpp b/utils/fasm/src/fasm.cpp index 3001bb1ae8a..2785c1149e8 100644 --- a/utils/fasm/src/fasm.cpp +++ b/utils/fasm/src/fasm.cpp @@ -343,9 +343,9 @@ static AtomNetId _find_atom_input_logical_net(const t_pb* atom, const t_pb_route static LogicVec lut_outputs(const t_pb* atom_pb, size_t num_inputs, const t_pb_routes &pb_route) { auto& atom_ctx = g_vpr_ctx.atom(); - AtomBlockId block_id = atom_ctx.lookup.pb_atom(atom_pb); - const auto& truth_table = atom_ctx.nlist.block_truth_table(block_id); - auto ports = atom_ctx.nlist.block_input_ports(atom_ctx.lookup.pb_atom(atom_pb)); + AtomBlockId block_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom_pb); + const auto& truth_table = atom_ctx.netlist().block_truth_table(block_id); + auto ports = atom_ctx.netlist().block_input_ports(atom_ctx.lookup().atom_pb_bimap().pb_atom(atom_pb)); const t_pb_graph_node* gnode = atom_pb->pb_graph_node; @@ -384,7 +384,7 @@ static LogicVec lut_outputs(const t_pb* atom_pb, size_t num_inputs, const t_pb_r if(impl_input_net_id) { //If there is a valid net connected in the implementation - AtomNetId logical_net_id = atom_ctx.nlist.port_net(port_id, orig_index); + AtomNetId logical_net_id = atom_ctx.netlist().port_net(port_id, orig_index); VTR_ASSERT(impl_input_net_id == logical_net_id); //Mark the permutation. @@ -537,7 +537,7 @@ static const t_pb_routes &find_pb_route(const t_pb* pb) { void FasmWriterVisitor::check_for_param(const t_pb *atom) { auto& atom_ctx = g_vpr_ctx.atom(); - auto atom_blk_id = atom_ctx.lookup.pb_atom(atom); + auto atom_blk_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); if (atom_blk_id == AtomBlockId::INVALID()) { return; } @@ -580,7 +580,7 @@ void FasmWriterVisitor::check_for_param(const t_pb *atom) { auto ¶ms = iter->second; - for(const auto& param : atom_ctx.nlist.block_params(atom_blk_id)) { + for(const auto& param : atom_ctx.netlist().block_params(atom_blk_id)) { auto feature = params.EmitFasmFeature(param.first, param.second); if(!feature.empty()) { @@ -592,12 +592,12 @@ void FasmWriterVisitor::check_for_param(const t_pb *atom) { void FasmWriterVisitor::check_for_lut(const t_pb* atom) { auto& atom_ctx = g_vpr_ctx.atom(); - auto atom_blk_id = atom_ctx.lookup.pb_atom(atom); + auto atom_blk_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); if (atom_blk_id == AtomBlockId::INVALID()) { return; } - const t_model* model = atom_ctx.nlist.block_model(atom_blk_id); + const t_model* model = atom_ctx.netlist().block_model(atom_blk_id); if (model->name == std::string(MODEL_NAMES)) { VTR_ASSERT(atom->pb_graph_node != nullptr); const auto *lut_definition = find_lut(atom->pb_graph_node); diff --git a/utils/fasm/src/main.cpp b/utils/fasm/src/main.cpp index 2fbee0a79c2..820179c1456 100644 --- a/utils/fasm/src/main.cpp +++ b/utils/fasm/src/main.cpp @@ -41,7 +41,7 @@ static bool write_fasm(bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); auto& atom_ctx = g_vpr_ctx.atom(); - std::string fasm_filename = atom_ctx.nlist.netlist_name() + ".fasm"; + std::string fasm_filename = atom_ctx.netlist().netlist_name() + ".fasm"; vtr::printf("Writing Implementation FASM: %s\n", fasm_filename.c_str()); std::ofstream fasm_os(fasm_filename); fasm::FasmWriterVisitor visitor(&device_ctx.arch->strings, fasm_os, is_flat); diff --git a/utils/route_diag/CMakeLists.txt b/utils/route_diag/CMakeLists.txt index 809785c939a..b6b41592df9 100644 --- a/utils/route_diag/CMakeLists.txt +++ b/utils/route_diag/CMakeLists.txt @@ -8,7 +8,7 @@ target_link_libraries(route_diag libvpr ) -#Supress IPO link warnings if IPO is enabled +#Suppress IPO link warnings if IPO is enabled get_target_property(TEST_ROUTE_DIAG_USES_IPO route_diag INTERPROCEDURAL_OPTIMIZATION) if (TEST_ROUTE_DIAG_USES_IPO) set_property(TARGET route_diag APPEND PROPERTY LINK_FLAGS ${IPO_LINK_WARN_SUPRESS_FLAGS}) diff --git a/utils/route_diag/src/main.cpp b/utils/route_diag/src/main.cpp index debd89c8bd6..5074d79cc09 100644 --- a/utils/route_diag/src/main.cpp +++ b/utils/route_diag/src/main.cpp @@ -9,13 +9,10 @@ // Tool can either perform one route between a source (--source_rr_node) and // a sink (--sink_rr_node), or profile a source to all tiles (set // --source_rr_node and "--profile_source true"). -#include -#include -#include + #include #include "vtr_error.h" -#include "vtr_memory.h" #include "vtr_log.h" #include "vtr_time.h" @@ -28,16 +25,13 @@ #include "globals.h" #include "net_delay.h" -#include "RoutingDelayCalculator.h" #include "place_and_route.h" #include "router_delay_profiling.h" #include "route_tree.h" #include "route_common.h" #include "route_net.h" -#include "route_export.h" #include "rr_graph.h" -#include "rr_graph2.h" -#include "timing_place_lookup.h" +#include "compute_delta_delays_utils.h" struct t_route_util_options { /* Router diag tool Options */ @@ -238,36 +232,6 @@ static void profile_source(const Netlist<>& net_list, VTR_LOG("\n"); } -static t_chan_width setup_chan_width(t_router_opts router_opts, - t_chan_width_dist chan_width_dist) { - /*we give plenty of tracks, this increases routability for the */ - /*lookup table generation */ - - t_graph_type graph_directionality; - int width_fac; - - if (router_opts.fixed_channel_width == NO_FIXED_CHANNEL_WIDTH) { - auto& device_ctx = g_vpr_ctx.device(); - - auto type = find_most_common_tile_type(device_ctx.grid); - - width_fac = 4 * type->num_pins; - /*this is 2x the value that binary search starts */ - /*this should be enough to allow most pins to */ - /*connect to tracks in the architecture */ - } else { - width_fac = router_opts.fixed_channel_width; - } - - if (router_opts.route_type == GLOBAL) { - graph_directionality = GRAPH_BIDIR; - } else { - graph_directionality = GRAPH_UNIDIR; - } - - return init_chan(width_fac, chan_width_dist, graph_directionality); -} - t_route_util_options read_route_util_options(int argc, const char** argv) { //Explicitly initialize for zero initialization t_route_util_options args = t_route_util_options(); @@ -283,7 +247,7 @@ t_route_util_options read_route_util_options(int argc, const char** argv) { route_diag_grp.add_argument(args.profile_source, "--profile_source") .help( "Profile routes from source to IPINs at all locations." - "This is similiar to the placer delay matrix construction.") + "This is similar to the placer delay matrix construction.") .show_in(argparse::ShowIn::HELP_ONLY); parser.parse_args(argc, argv); @@ -320,20 +284,18 @@ int main(int argc, const char **argv) { bool is_flat = vpr_setup.RouterOpts.flat_routing; - const Netlist<>& net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().nlist : + const Netlist<>& net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; - t_chan_width chan_width = setup_chan_width( - vpr_setup.RouterOpts, - Arch.Chans); + t_chan_width chan_width = setup_chan_width(vpr_setup.RouterOpts, + Arch.Chans); - alloc_routing_structs( - chan_width, - vpr_setup.RouterOpts, - &vpr_setup.RoutingArch, - vpr_setup.Segments, - Arch.directs, - is_flat); + alloc_routing_structs(chan_width, + vpr_setup.RouterOpts, + &vpr_setup.RoutingArch, + vpr_setup.Segments, + Arch.directs, + is_flat); if(route_options.profile_source) { profile_source(net_list, diff --git a/utils/vqm2blif/test/scripts/test_vqm2blif.sh b/utils/vqm2blif/test/scripts/test_vqm2blif.sh index 98966a9bc45..60c217a99e5 100755 --- a/utils/vqm2blif/test/scripts/test_vqm2blif.sh +++ b/utils/vqm2blif/test/scripts/test_vqm2blif.sh @@ -259,7 +259,7 @@ do done -# we create seperate subshells to process each iteration of the loops above. +# we create separate subshells to process each iteration of the loops above. # So below we check the result of the last shell. if [ $? -eq 1 ]; then diff --git a/vpr/scripts/profile/util.py b/vpr/scripts/profile/util.py index c6a252a3c75..8ac1e2930e5 100644 --- a/vpr/scripts/profile/util.py +++ b/vpr/scripts/profile/util.py @@ -5,6 +5,7 @@ import socket import getpass + # working on the task directory def sort_runs(runs): natural_sort(runs) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 7ff47a81cf9..542269395c5 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -23,7 +23,7 @@ void generate_setup_timing_stats(const std::string& prefix, print_setup_timing_summary(*timing_ctx.constraints, *timing_info.setup_analyzer(), "Final ", analysis_opts.write_timing_summary); - VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); @@ -48,7 +48,7 @@ void generate_hold_timing_stats(const std::string& prefix, print_hold_timing_summary(*timing_ctx.constraints, *timing_info.hold_analyzer(), "Final "); - VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); diff --git a/vpr/src/analytical_place/analytical_placement_flow.cpp b/vpr/src/analytical_place/analytical_placement_flow.cpp index 9b334402114..853f4cb2f02 100644 --- a/vpr/src/analytical_place/analytical_placement_flow.cpp +++ b/vpr/src/analytical_place/analytical_placement_flow.cpp @@ -7,9 +7,12 @@ #include "analytical_placement_flow.h" #include +#include "PreClusterTimingManager.h" #include "analytical_solver.h" #include "ap_netlist.h" #include "atom_netlist.h" +#include "cluster_util.h" +#include "detailed_placer.h" #include "full_legalizer.h" #include "gen_ap_netlist_from_atoms.h" #include "global_placer.h" @@ -20,6 +23,7 @@ #include "user_place_constraints.h" #include "vpr_context.h" #include "vpr_types.h" +#include "stats.h" #include "vtr_assert.h" #include "vtr_time.h" @@ -58,18 +62,104 @@ static void print_ap_netlist_stats(const APNetlist& netlist) { VTR_LOG("\n"); } +/** + * @brief Passes the flat placement information to a provided partial placement. + * + * @param flat_placement_info The flat placement information to be read. + * @param ap_netlist The APNetlist that used to iterate over its blocks. + * @param prepacker The Prepacker to get molecule of blocks in the ap_netlist. + * @param p_placement The partial placement to be updated which is assumend + * to be generated on ap_netlist or have the same blocks. + */ +static void convert_flat_to_partial_placement(const FlatPlacementInfo& flat_placement_info, const APNetlist& ap_netlist, const Prepacker& prepacker, PartialPlacement& p_placement) { + for (APBlockId ap_blk_id : ap_netlist.blocks()) { + // Get the molecule that AP block represents + PackMoleculeId mol_id = ap_netlist.block_molecule(ap_blk_id); + const t_pack_molecule& mol = prepacker.get_molecule(mol_id); + // Get location of a valid atom in the molecule and verify that + // all atoms of the molecule share same placement information. + float atom_loc_x, atom_loc_y, atom_loc_layer; + int atom_loc_sub_tile; + bool found_valid_atom = false; + for (AtomBlockId atom_blk_id : mol.atom_block_ids) { + if (!atom_blk_id.is_valid()) + continue; + float current_loc_x = flat_placement_info.blk_x_pos[atom_blk_id]; + float current_loc_y = flat_placement_info.blk_y_pos[atom_blk_id]; + float current_loc_layer = flat_placement_info.blk_layer[atom_blk_id]; + int current_loc_sub_tile = flat_placement_info.blk_sub_tile[atom_blk_id]; + if (found_valid_atom) { + if (current_loc_x != atom_loc_x || current_loc_y != atom_loc_y || current_loc_layer != atom_loc_layer || current_loc_sub_tile != atom_loc_sub_tile) + VPR_FATAL_ERROR(VPR_ERROR_AP, + "Molecule of ID %zu contains atom %s (ID: %zu) with a location (%g, %g, layer: %g, subtile: %d) " + "that conflicts the location of other atoms in this molecule of (%g, %g, layer: %g, subtile: %d).", + mol_id, g_vpr_ctx.atom().netlist().block_name(atom_blk_id).c_str(), atom_blk_id, + current_loc_x, current_loc_y, current_loc_layer, current_loc_sub_tile, + atom_loc_x, atom_loc_y, atom_loc_layer, atom_loc_sub_tile); + } else { + atom_loc_x = current_loc_x; + atom_loc_y = current_loc_y; + atom_loc_layer = current_loc_layer; + atom_loc_sub_tile = current_loc_sub_tile; + found_valid_atom = true; + } + } + // Ensure that there is a valid atom in the molecule to pass its location. + VTR_ASSERT_MSG(found_valid_atom, "Each molecule must contain at least one valid atom"); + // Pass the placement information + p_placement.block_x_locs[ap_blk_id] = atom_loc_x; + p_placement.block_y_locs[ap_blk_id] = atom_loc_y; + p_placement.block_layer_nums[ap_blk_id] = atom_loc_layer; + p_placement.block_sub_tiles[ap_blk_id] = atom_loc_sub_tile; + } +} + +/** + * @brief If a flat placement is provided, skips the Global Placer and + * converts it to a partial placement. Otherwise, runs the Global Placer. + */ +static PartialPlacement run_global_placer(const t_ap_opts& ap_opts, + const AtomNetlist& atom_nlist, + const APNetlist& ap_netlist, + const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, + const DeviceContext& device_ctx) { + if (g_vpr_ctx.atom().flat_placement_info().valid) { + VTR_LOG("Flat Placement is provided in the AP flow, skipping the Global Placement.\n"); + PartialPlacement p_placement(ap_netlist); + convert_flat_to_partial_placement(g_vpr_ctx.atom().flat_placement_info(), + ap_netlist, + prepacker, + p_placement); + return p_placement; + } else { + // Run the Global Placer + std::unique_ptr global_placer = make_global_placer(ap_opts.analytical_solver_type, + ap_opts.partial_legalizer_type, + ap_netlist, + prepacker, + atom_nlist, + device_ctx.grid, + device_ctx.logical_block_types, + device_ctx.physical_tile_types, + pre_cluster_timing_manager, + ap_opts.ap_timing_tradeoff, + ap_opts.log_verbosity); + return global_placer->place(); + } +} + void run_analytical_placement_flow(t_vpr_setup& vpr_setup) { // Start an overall timer for the Analytical Placement flow. vtr::ScopedStartFinishTimer timer("Analytical Placement"); // The global state used/modified by this flow. - const AtomNetlist& atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); const DeviceContext& device_ctx = g_vpr_ctx.device(); const UserPlaceConstraints& constraints = g_vpr_ctx.floorplanning().constraints; // Run the prepacker - Prepacker prepacker; - prepacker.init(atom_nlist, device_ctx.logical_block_types); + const Prepacker prepacker(atom_nlist, device_ctx.logical_block_types); // Create the ap netlist from the atom netlist using the result from the // prepacker. @@ -78,10 +168,26 @@ void run_analytical_placement_flow(t_vpr_setup& vpr_setup) { constraints); print_ap_netlist_stats(ap_netlist); - // Run the Global Placer - std::unique_ptr global_placer = make_global_placer(e_global_placer::SimPL, - ap_netlist); - PartialPlacement p_placement = global_placer->place(); + // Pre-compute the pre-clustering timing delays. This object will be passed + // into the global placer and the full legalizer to make them timing driven. + PreClusterTimingManager pre_cluster_timing_manager(vpr_setup.PackerOpts.timing_driven, + atom_nlist, + g_vpr_ctx.atom().lookup(), + prepacker, + vpr_setup.PackerOpts.timing_update_type, + *device_ctx.arch, + vpr_setup.RoutingArch, + vpr_setup.PackerOpts.device_layout, + vpr_setup.AnalysisOpts); + + // Run the Global Placer. + const t_ap_opts& ap_opts = vpr_setup.APOpts; + PartialPlacement p_placement = run_global_placer(ap_opts, + atom_nlist, + ap_netlist, + prepacker, + pre_cluster_timing_manager, + device_ctx); // Verify that the partial placement is valid before running the full // legalizer. @@ -93,17 +199,33 @@ void run_analytical_placement_flow(t_vpr_setup& vpr_setup) { device_ctx.grid.get_num_layers())); // Run the Full Legalizer. - FullLegalizer full_legalizer(ap_netlist, - vpr_setup, - device_ctx.grid, - device_ctx.arch, - atom_nlist, - prepacker, - device_ctx.logical_block_types, - vpr_setup.PackerRRGraph, - device_ctx.arch->models, - device_ctx.arch->model_library, - vpr_setup.PackerOpts); - full_legalizer.legalize(p_placement); -} + std::unique_ptr full_legalizer = make_full_legalizer(ap_opts.full_legalizer_type, + ap_netlist, + atom_nlist, + prepacker, + pre_cluster_timing_manager, + vpr_setup, + *device_ctx.arch, + device_ctx.grid); + full_legalizer->legalize(p_placement); + + // Print the number of resources in netlist and number of resources available in architecture + float target_device_utilization = vpr_setup.PackerOpts.target_device_utilization; + print_resource_usage(); + // Print the device utilization + print_device_utilization(target_device_utilization); + // Run the Detailed Placer. + std::unique_ptr detailed_placer = make_detailed_placer(ap_opts.detailed_placer_type, + g_vpr_ctx.placement().blk_loc_registry(), + atom_nlist, + g_vpr_ctx.clustering().clb_nlist, + vpr_setup, + *device_ctx.arch); + detailed_placer->optimize_placement(); + + // Clean up some of the global variables that will no longer be used outside + // of this flow. + g_vpr_ctx.mutable_placement().clean_placement_context_post_place(); + g_vpr_ctx.mutable_floorplanning().clean_floorplanning_context_post_place(); +} diff --git a/vpr/src/analytical_place/analytical_placement_flow.h b/vpr/src/analytical_place/analytical_placement_flow.h index 638456177f1..527fe241706 100644 --- a/vpr/src/analytical_place/analytical_placement_flow.h +++ b/vpr/src/analytical_place/analytical_placement_flow.h @@ -16,4 +16,3 @@ struct t_vpr_setup; * @param vpr_setup The setup options provided by the user. */ void run_analytical_placement_flow(t_vpr_setup& vpr_setup); - diff --git a/vpr/src/analytical_place/analytical_solver.cpp b/vpr/src/analytical_place/analytical_solver.cpp index 4c5e0037c7b..22a846d43ea 100644 --- a/vpr/src/analytical_place/analytical_solver.cpp +++ b/vpr/src/analytical_place/analytical_solver.cpp @@ -9,13 +9,20 @@ #include "analytical_solver.h" #include #include +#include #include #include #include +#include "PreClusterTimingManager.h" +#include "atom_netlist.h" +#include "atom_netlist_fwd.h" +#include "device_grid.h" +#include "flat_placement_types.h" #include "partial_placement.h" #include "ap_netlist.h" #include "vpr_error.h" #include "vtr_assert.h" +#include "vtr_time.h" #include "vtr_vector.h" #ifdef EIGEN_INSTALLED @@ -35,18 +42,46 @@ #pragma GCC diagnostic pop #endif // EIGEN_INSTALLED -std::unique_ptr make_analytical_solver(e_analytical_solver solver_type, - const APNetlist& netlist) { +std::unique_ptr make_analytical_solver(e_ap_analytical_solver solver_type, + const APNetlist& netlist, + const DeviceGrid& device_grid, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity) { // Based on the solver type passed in, build the solver. switch (solver_type) { - case e_analytical_solver::QP_HYBRID: + case e_ap_analytical_solver::QP_Hybrid: #ifdef EIGEN_INSTALLED - return std::make_unique(netlist); + return std::make_unique(netlist, + device_grid, + atom_netlist, + pre_cluster_timing_manager, + ap_timing_tradeoff, + log_verbosity); #else (void)netlist; + (void)device_grid; + (void)atom_netlist; + (void)pre_cluster_timing_manager; + (void)ap_timing_tradeoff; + (void)log_verbosity; VPR_FATAL_ERROR(VPR_ERROR_AP, "QP Hybrid Solver requires the Eigen library"); break; +#endif // EIGEN_INSTALLED + case e_ap_analytical_solver::LP_B2B: +#ifdef EIGEN_INSTALLED + return std::make_unique(netlist, + device_grid, + atom_netlist, + pre_cluster_timing_manager, + ap_timing_tradeoff, + log_verbosity); +#else + VPR_FATAL_ERROR(VPR_ERROR_AP, + "LP B2B Solver requires the Eigen library"); + break; #endif // EIGEN_INSTALLED default: VPR_FATAL_ERROR(VPR_ERROR_AP, @@ -56,16 +91,25 @@ std::unique_ptr make_analytical_solver(e_analytical_solver sol return nullptr; } -AnalyticalSolver::AnalyticalSolver(const APNetlist& netlist) - : netlist_(netlist), - blk_id_to_row_id_(netlist.blocks().size(), APRowId::INVALID()), - row_id_to_blk_id_(netlist.blocks().size(), APBlockId::INVALID()) { +AnalyticalSolver::AnalyticalSolver(const APNetlist& netlist, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity) + : netlist_(netlist) + , blk_id_to_row_id_(netlist.blocks().size(), APRowId::INVALID()) + , row_id_to_blk_id_(netlist.blocks().size(), APBlockId::INVALID()) + , net_weights_(netlist.nets().size(), 1.0f) + , log_verbosity_(log_verbosity) { // Get the number of moveable blocks in the netlist and create a unique // row ID from [0, num_moveable_blocks) for each moveable block in the // netlist. num_moveable_blocks_ = 0; + num_fixed_blocks_ = 0; size_t current_row_id = 0; for (APBlockId blk_id : netlist.blocks()) { + if (netlist.block_mobility(blk_id) == APBlockMobility::FIXED) + num_fixed_blocks_++; if (netlist.block_mobility(blk_id) != APBlockMobility::MOVEABLE) continue; APRowId new_row_id = APRowId(current_row_id); @@ -74,6 +118,21 @@ AnalyticalSolver::AnalyticalSolver(const APNetlist& netlist) current_row_id++; num_moveable_blocks_++; } + + if (pre_cluster_timing_manager.is_valid()) { + for (APNetId net_id : netlist.nets()) { + // Get the atom net associated with the given AP net. When + // constructing the AP netlist, we happen to set the name of each + // AP net to the same name as the atom net that generated them! + // TODO: Create a proper lookup structure to go from the AP Netlist + // back to the Atom Netlist. + AtomNetId atom_net_id = atom_netlist.find_net(netlist.net_name(net_id)); + VTR_ASSERT(atom_net_id.is_valid()); + float crit = pre_cluster_timing_manager.calc_net_setup_criticality(atom_net_id, atom_netlist); + + net_weights_[net_id] = ap_timing_tradeoff * crit + (1.0f - ap_timing_tradeoff); + } + } } #ifdef EIGEN_INSTALLED @@ -155,10 +214,10 @@ void QPHybridSolver::init_linear_system() { } // Initialize the linear system with zeros. - size_t num_variables = num_moveable_blocks_ + num_star_nodes; - A_sparse = Eigen::SparseMatrix(num_variables, num_variables); - b_x = Eigen::VectorXd::Zero(num_variables); - b_y = Eigen::VectorXd::Zero(num_variables); + num_variables_ = num_moveable_blocks_ + num_star_nodes; + A_sparse = Eigen::SparseMatrix(num_variables_, num_variables_); + b_x = Eigen::VectorXd::Zero(num_variables_); + b_y = Eigen::VectorXd::Zero(num_variables_); // Create a list of triplets that will be used to create the sparse // coefficient matrix. This is the method recommended by Eigen to initialize @@ -169,13 +228,11 @@ void QPHybridSolver::init_linear_system() { std::vector> tripletList; // Reserve enough space for the triplets. This is just to help with // performance. - // This is an over-estimate that assumes that each net connnects to all - // moveable blocks using a star node. // TODO: This can be made more space-efficient by getting the average fanout // of all nets in the APNetlist. Ideally this should be not enough // space, but be within a constant factor. size_t num_nets = netlist_.nets().size(); - tripletList.reserve(num_moveable_blocks_ * num_nets); + tripletList.reserve(num_nets); // Create the connections using a hybrid connection model of the star and // clique connnection models. @@ -183,12 +240,15 @@ void QPHybridSolver::init_linear_system() { for (APNetId net_id : netlist_.nets()) { size_t num_pins = netlist_.net_pins(net_id).size(); VTR_ASSERT_DEBUG(num_pins > 1); + + double net_weight = net_weights_[net_id]; + if (num_pins > star_num_pins_threshold) { // Create a star node and connect each block in the net to the star // node. // Using the weight from FastPlace // TODO: Investigate other weight terms. - double w = static_cast(num_pins) / static_cast(num_pins - 1); + double w = net_weight * static_cast(num_pins) / static_cast(num_pins - 1); size_t star_node_id = num_moveable_blocks_ + star_node_offset; for (APPinId pin_id : netlist_.net_pins(net_id)) { APBlockId blk_id = netlist_.pin_block(pin_id); @@ -202,7 +262,7 @@ void QPHybridSolver::init_linear_system() { // exactly once to every other block in the net. // Using the weight from FastPlace // TODO: Investigate other weight terms. - double w = 1.0 / static_cast(num_pins - 1); + double w = net_weight * 1.0 / static_cast(num_pins - 1); for (size_t ipin_idx = 0; ipin_idx < num_pins; ipin_idx++) { APPinId first_pin_id = netlist_.net_pin(net_id, ipin_idx); APBlockId first_blk_id = netlist_.pin_block(first_pin_id); @@ -238,42 +298,17 @@ void QPHybridSolver::init_linear_system() { A_sparse.setFromTriplets(tripletList.begin(), tripletList.end()); } -/** - * @brief Helper method to update the linear system with anchors to the current - * partial placement. - * - * For each moveable block (with row = i) in the netlist: - * A[i][i] = A[i][i] + coeff_pseudo_anchor; - * b[i] = b[i] + pos[block(i)] * coeff_pseudo_anchor; - * Where coeff_pseudo_anchor grows with each iteration. - * - * This is basically a fast way of adding a connection between all moveable - * blocks in the netlist and their target fixed placement location. - * - * See add_connection_to_system. - * - * @param A_sparse_diff The ceofficient matrix to update. - * @param b_x_diff The x-dimension constant vector to update. - * @param b_y_diff The y-dimension constant vector to update. - * @param p_placement The location the moveable blocks should be anchored - * to. - * @param num_moveable_blocks The number of moveable blocks in the netlist. - * @param row_id_to_blk_id Lookup for the row id from the APBlock Id. - * @param iteration The current iteration of the Global Placer. - */ -static inline void update_linear_system_with_anchors( - Eigen::SparseMatrix &A_sparse_diff, - Eigen::VectorXd &b_x_diff, - Eigen::VectorXd &b_y_diff, - PartialPlacement& p_placement, - size_t num_moveable_blocks, - vtr::vector row_id_to_blk_id, - unsigned iteration) { +void QPHybridSolver::update_linear_system_with_anchors( + Eigen::SparseMatrix& A_sparse_diff, + Eigen::VectorXd& b_x_diff, + Eigen::VectorXd& b_y_diff, + PartialPlacement& p_placement, + unsigned iteration) { // Anchor weights grow exponentially with iteration. - double coeff_pseudo_anchor = 0.01 * std::exp((double)iteration/5); - for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks; row_id_idx++) { + double coeff_pseudo_anchor = anchor_weight_mult_ * std::exp((double)iteration / anchor_weight_exp_fac_); + for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { APRowId row_id = APRowId(row_id_idx); - APBlockId blk_id = row_id_to_blk_id[row_id]; + APBlockId blk_id = row_id_to_blk_id_[row_id]; double pseudo_w = coeff_pseudo_anchor; A_sparse_diff.coeffRef(row_id_idx, row_id_idx) += pseudo_w; b_x_diff(row_id_idx) += pseudo_w * p_placement.block_x_locs[blk_id]; @@ -281,7 +316,54 @@ static inline void update_linear_system_with_anchors( } } -void QPHybridSolver::solve(unsigned iteration, PartialPlacement &p_placement) { +void QPHybridSolver::init_guesses(const DeviceGrid& device_grid) { + // If the number of fixed blocks is zero, initialized the guesses to the + // center of the device. + if (num_fixed_blocks_ == 0) { + guess_x = Eigen::VectorXd::Constant(num_variables_, device_grid.width() / 2.0); + guess_y = Eigen::VectorXd::Constant(num_variables_, device_grid.height() / 2.0); + return; + } + + // Compute the centroid of all fixed blocks in the netlist. + t_flat_pl_loc centroid({0.0f, 0.0f, 0.0f}); + unsigned num_blks_summed = 0; + for (APBlockId blk_id : netlist_.blocks()) { + // We only get the centroid of fixed blocks since these are the only + // blocks with positions that we know. + if (netlist_.block_mobility(blk_id) != APBlockMobility::FIXED) + continue; + // Get the flat location of the fixed block. + APFixedBlockLoc fixed_blk_loc = netlist_.block_loc(blk_id); + VTR_ASSERT_SAFE(fixed_blk_loc.x != APFixedBlockLoc::UNFIXED_DIM); + VTR_ASSERT_SAFE(fixed_blk_loc.y != APFixedBlockLoc::UNFIXED_DIM); + VTR_ASSERT_SAFE(fixed_blk_loc.layer_num != APFixedBlockLoc::UNFIXED_DIM); + t_flat_pl_loc flat_blk_loc; + flat_blk_loc.x = fixed_blk_loc.x; + flat_blk_loc.y = fixed_blk_loc.y; + flat_blk_loc.layer = fixed_blk_loc.layer_num; + // Accumulate into the centroid. + centroid += flat_blk_loc; + num_blks_summed++; + } + // Divide the sum by the number of fixed blocks. + VTR_ASSERT_SAFE(num_blks_summed == num_fixed_blocks_); + centroid /= static_cast(num_blks_summed); + + // Set the guesses to the centroid location. + guess_x = Eigen::VectorXd::Constant(num_variables_, centroid.x); + guess_y = Eigen::VectorXd::Constant(num_variables_, centroid.y); +} + +void QPHybridSolver::solve(unsigned iteration, PartialPlacement& p_placement) { + // In the first iteration, if the number of fixed blocks is 0, set the + // placement to be equal to the guess. The solver below will just set the + // solution to the zero vector if we do not set it to the guess directly. + if (iteration == 0 && num_fixed_blocks_ == 0) { + store_solution_into_placement(guess_x, guess_y, p_placement); + return; + } + // Create a temporary linear system which will contain the original linear // system which may be updated to include the anchor points. Eigen::SparseMatrix A_sparse_diff = Eigen::SparseMatrix(A_sparse); @@ -292,30 +374,41 @@ void QPHybridSolver::solve(unsigned iteration, PartialPlacement &p_placement) { // anchor-points (fixed block positions). if (iteration != 0) { update_linear_system_with_anchors(A_sparse_diff, b_x_diff, b_y_diff, - p_placement, num_moveable_blocks_, - row_id_to_blk_id_, iteration); + p_placement, iteration); } // Verify that the constant vectors are valid. - VTR_ASSERT_DEBUG(!b_x_diff.hasNaN() && "b_x has NaN!"); - VTR_ASSERT_DEBUG(!b_y_diff.hasNaN() && "b_y has NaN!"); + VTR_ASSERT_SAFE_MSG(!b_x_diff.hasNaN(), "b_x has NaN!"); + VTR_ASSERT_SAFE_MSG(!b_y_diff.hasNaN(), "b_y has NaN!"); // Set up the ConjugateGradient Solver using the coefficient matrix. // TODO: can change cg.tolerance to increase performance when needed // - This tolerance may need to be a function of the number of nets. // - Instead of normalizing the fixed blocks, the tolerance can be scaled // by the size of the device. - Eigen::ConjugateGradient, Eigen::Lower|Eigen::Upper> cg; + Eigen::ConjugateGradient, Eigen::Lower | Eigen::Upper> cg; cg.compute(A_sparse_diff); VTR_ASSERT(cg.info() == Eigen::Success && "Conjugate Gradient failed at compute!"); // Use the solver to solve for x and y using the constant vectors - // TODO: Use solve with guess to make this faster. Use the previous placement - // as a guess. - Eigen::VectorXd x = cg.solve(b_x_diff); + Eigen::VectorXd x = cg.solveWithGuess(b_x_diff, guess_x); + total_num_cg_iters_ += cg.iterations(); VTR_ASSERT(cg.info() == Eigen::Success && "Conjugate Gradient failed at solving b_x!"); - Eigen::VectorXd y = cg.solve(b_y_diff); + Eigen::VectorXd y = cg.solveWithGuess(b_y_diff, guess_y); + total_num_cg_iters_ += cg.iterations(); VTR_ASSERT(cg.info() == Eigen::Success && "Conjugate Gradient failed at solving b_y!"); // Write the results back into the partial placement object. + store_solution_into_placement(x, y, p_placement); + + // Update the guess. The guess for the next iteration is the solution in + // this iteration. + guess_x = x; + guess_y = y; +} + +void QPHybridSolver::store_solution_into_placement(const Eigen::VectorXd& x_soln, + const Eigen::VectorXd& y_soln, + PartialPlacement& p_placement) { + // NOTE: The first [0, num_moveable_blocks_) rows always represent the // moveable APBlocks. The star nodes always come after and are ignored // in the solution. @@ -324,10 +417,430 @@ void QPHybridSolver::solve(unsigned iteration, PartialPlacement &p_placement) { APBlockId blk_id = row_id_to_blk_id_[row_id]; VTR_ASSERT_DEBUG(blk_id.is_valid()); VTR_ASSERT_DEBUG(netlist_.block_mobility(blk_id) == APBlockMobility::MOVEABLE); - p_placement.block_x_locs[blk_id] = x[row_id_idx]; - p_placement.block_y_locs[blk_id] = y[row_id_idx]; + // Due to the iterative nature of CG, it is possible for the solver to + // overstep 0 and return a negative number by an incredibly small margin. + // Clamp the number to 0 in this case. + // TODO: Should investigate good bounds on this, the bounds below were + // chosen since any difference higher than 1e-9 would concern me. + double x_pos = x_soln[row_id_idx]; + if (x_pos < 0.0) { + VTR_ASSERT_SAFE(std::abs(x_pos) < negative_soln_tolerance_); + x_pos = 0.0; + } + double y_pos = y_soln[row_id_idx]; + if (y_pos < 0.0) { + VTR_ASSERT_SAFE(std::abs(y_pos) < negative_soln_tolerance_); + y_pos = 0.0; + } + p_placement.block_x_locs[blk_id] = x_pos; + p_placement.block_y_locs[blk_id] = y_pos; } } -#endif // EIGEN_INSTALLED +void QPHybridSolver::print_statistics() { + VTR_LOG("QP-Hybrid Solver Statistics:\n"); + VTR_LOG("\tTotal number of CG iterations: %u\n", total_num_cg_iters_); +} + +void B2BSolver::solve(unsigned iteration, PartialPlacement& p_placement) { + // Store an initial placement into the p_placement object as a starting point + // for the B2B solver. + if (iteration == 0) { + // If there are no fixed blocks, running bound2bound will always yield + // the trivial solution (all blocks on top of each other anywhere on the + // device). Skip having to solve for this by just putting all the blocks + // at the center of the device. + // TODO: This can be further improved by using the average compatible + // tile location for each AP block. The center is just an + // approximation. + if (num_fixed_blocks_ == 0) { + for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { + APRowId row_id = APRowId(row_id_idx); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + p_placement.block_x_locs[blk_id] = device_grid_width_ / 2.0; + p_placement.block_y_locs[blk_id] = device_grid_height_ / 2.0; + } + block_x_locs_solved = p_placement.block_x_locs; + block_y_locs_solved = p_placement.block_y_locs; + return; + } + + // In the first iteration, we have no prior information. + // Run the intial placer to get a first guess. + switch (initial_placement_ty_) { + case e_initial_placement_type::LeastDense: + initialize_placement_least_dense(p_placement); + break; + default: + VPR_FATAL_ERROR(VPR_ERROR_AP, "Unknown initial placement type"); + } + } else { + // After the first iteration, the prior solved solution will serve as + // the best starting points for the bounds. + + // Save the legalized solution; we need it for the anchors. + block_x_locs_legalized = p_placement.block_x_locs; + block_y_locs_legalized = p_placement.block_y_locs; + + // Store last solved position into p_placement for b2b model + p_placement.block_x_locs = block_x_locs_solved; + p_placement.block_y_locs = block_y_locs_solved; + } + + // Run the B2B solver using p_placement as a starting point. + b2b_solve_loop(iteration, p_placement); + + // Store the solved solutions for the next iteration. + block_x_locs_solved = p_placement.block_x_locs; + block_y_locs_solved = p_placement.block_y_locs; +} + +void B2BSolver::initialize_placement_least_dense(PartialPlacement& p_placement) { + // Find a gap for the blocks such that each block can fit onto the device + // if they were evenly spaced by this gap. + double gap = std::sqrt(device_grid_height_ * device_grid_width_ / static_cast(num_moveable_blocks_)); + + // Assuming this gap, get how many columns/rows of blocks there will be. + size_t cols = std::ceil(device_grid_width_ / gap); + size_t rows = std::ceil(device_grid_height_ / gap); + + // Spread the blocks at these grid coordinates. + for (size_t r = 0; r <= rows; r++) { + for (size_t c = 0; c <= cols; c++) { + size_t i = r * cols + c; + if (i >= num_moveable_blocks_) + break; + APRowId row_id = APRowId(i); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + p_placement.block_x_locs[blk_id] = c * gap; + p_placement.block_y_locs[blk_id] = r * gap; + } + } +} + +void B2BSolver::b2b_solve_loop(unsigned iteration, PartialPlacement& p_placement) { + // Set up the guesses for x and y to help CG converge faster + // A good guess for B2B is the last solved solution. + Eigen::VectorXd x_guess(num_moveable_blocks_); + Eigen::VectorXd y_guess(num_moveable_blocks_); + for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { + APRowId row_id = APRowId(row_id_idx); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + x_guess(row_id_idx) = p_placement.block_x_locs[blk_id]; + y_guess(row_id_idx) = p_placement.block_y_locs[blk_id]; + } + + // Create a timer to keep track of how long each part of the solver take. + vtr::Timer runtime_timer; + + // To solve B2B, we need to do the following: + // 1) Set up the connectivity matrix and constant vectors based on the + // bounds of the current solution (stored in p_placement). + // 2) Solve the system of equations using CG and store the result into + // p_placement. + // 3) Repeat. Note: We need to repeat step 1 and 2 iteratively since + // the bounds are likely to have changed after step 2. + // We stop when it looks like the placement is converging (the change in + // HPWL is sufficiently small for a few iterations). + double prev_hpwl = std::numeric_limits::max(); + double curr_hpwl = prev_hpwl; + unsigned num_convergence = 0; + for (unsigned counter = 0; counter < max_num_bound_updates_; counter++) { + VTR_LOGV(log_verbosity_ >= 10, + "\tPlacement HPWL in b2b loop: %f\n", + p_placement.get_hpwl(netlist_)); + + // Set up the linear system, including anchor points. + float build_linear_system_start_time = runtime_timer.elapsed_sec(); + init_linear_system(p_placement); + if (iteration != 0) + update_linear_system_with_anchors(iteration); + total_time_spent_building_linear_system_ += runtime_timer.elapsed_sec() - build_linear_system_start_time; + VTR_ASSERT_SAFE_MSG(!b_x.hasNaN(), "b_x has NaN!"); + VTR_ASSERT_SAFE_MSG(!b_y.hasNaN(), "b_y has NaN!"); + VTR_ASSERT_SAFE_MSG((b_x.array() >= 0).all(), "b_x has NaN!"); + VTR_ASSERT_SAFE_MSG((b_y.array() >= 0).all(), "b_y has NaN!"); + + // Build the solvers for each dimension. + // Note: Since we have two different connectivity matrices, we need to + // different CG solver objects. + float solve_linear_system_start_time = runtime_timer.elapsed_sec(); + Eigen::VectorXd x, y; + Eigen::ConjugateGradient, Eigen::Lower | Eigen::Upper> cg_x; + Eigen::ConjugateGradient, Eigen::Lower | Eigen::Upper> cg_y; + cg_x.compute(A_sparse_x); + cg_y.compute(A_sparse_y); + VTR_ASSERT_SAFE_MSG(cg_x.info() == Eigen::Success, "Conjugate Gradient failed at compute for A_x!"); + VTR_ASSERT_SAFE_MSG(cg_y.info() == Eigen::Success, "Conjugate Gradient failed at compute for A_y!"); + cg_x.setMaxIterations(max_cg_iterations_); + cg_y.setMaxIterations(max_cg_iterations_); + + // Solve the x dimension. + x = cg_x.solveWithGuess(b_x, x_guess); + total_num_cg_iters_ += cg_x.iterations(); + VTR_LOGV(log_verbosity_ >= 20, "\t\tNum CG-x iter: %zu\n", cg_x.iterations()); + + // Solve the y dimension. + y = cg_y.solveWithGuess(b_y, y_guess); + total_num_cg_iters_ += cg_y.iterations(); + VTR_LOGV(log_verbosity_ >= 20, "\t\tNum CG-y iter: %zu\n", cg_y.iterations()); + + total_time_spent_solving_linear_system_ += runtime_timer.elapsed_sec() - solve_linear_system_start_time; + + // Save the result into the partial placement object. + store_solution_into_placement(x, y, p_placement); + + // If the current HPWL is larger than the previous HPWL (i.e. the HPWL + // got worst since last B2B iter) or the gap between the two solutions + // is small. Increment a counter. + // TODO: Since, in theory, the HPWL could get worst due to numerical + // reasons, should we save the best result? May not be worth it... + curr_hpwl = p_placement.get_hpwl(netlist_); + double target_gap = b2b_convergence_gap_fac_ * curr_hpwl; + if (curr_hpwl > prev_hpwl || std::abs(curr_hpwl - prev_hpwl) < target_gap) + num_convergence++; + // If the HPWL got close enough times, stop. This is to allow the HPWL + // to "bounce", which can happen as it converges. + // This trades-off quality for run time. + if (num_convergence >= target_num_b2b_convergences_) + break; + prev_hpwl = curr_hpwl; + + // Update the guesses with the most recent answer + x_guess = x; + y_guess = y; + } +} + +namespace { +/** + * @brief Struct used to hold the bounding blocks of an AP net. + */ +struct APNetBounds { + /// @brief The leftmost block in the net. + APBlockId min_x_blk; + /// @brief The rightmost block in the net. + APBlockId max_x_blk; + /// @brief The bottom-most block in the net. + APBlockId min_y_blk; + /// @brief The top-most block in the net. + APBlockId max_y_blk; +}; + +} // namespace + +/** + * @brief Helper method to get the unique bounding blocks of a given net. + * + * In the B2B model, we do not want the same block to be the bounds in a given + * dimension. Therefore, if all blocks share the same x location for example, + * different bounds will be chosen for the x dimension. + */ +static inline APNetBounds get_unique_net_bounds(APNetId net_id, + const PartialPlacement& p_placement, + const APNetlist& netlist) { + VTR_ASSERT_SAFE_MSG(netlist.net_pins(net_id).size() != 0, + "Cannot get the bounds of an empty net"); + VTR_ASSERT_SAFE_MSG(netlist.net_pins(net_id).size() >= 2, + "Expect nets to have at least 2 pins"); + + APNetBounds bounds; + double max_x_pos = std::numeric_limits::lowest(); + double min_x_pos = std::numeric_limits::max(); + double max_y_pos = std::numeric_limits::lowest(); + double min_y_pos = std::numeric_limits::max(); + + for (APPinId pin_id : netlist.net_pins(net_id)) { + // Update the bounds based on the position of the block that has this pin. + APBlockId blk_id = netlist.pin_block(pin_id); + double x_pos = p_placement.block_x_locs[blk_id]; + double y_pos = p_placement.block_y_locs[blk_id]; + if (x_pos < min_x_pos) { + min_x_pos = x_pos; + bounds.min_x_blk = blk_id; + } + if (y_pos < min_y_pos) { + min_y_pos = y_pos; + bounds.min_y_blk = blk_id; + } + if (x_pos > max_x_pos) { + max_x_pos = x_pos; + bounds.max_x_blk = blk_id; + } + if (y_pos > max_y_pos) { + max_y_pos = y_pos; + bounds.max_y_blk = blk_id; + } + + // In the case of a tie, we do not want to have the same blocks as bounds. + // If there is a tie for the max position, and the current min bound is + // not this block, take the incoming block. + if (x_pos == max_x_pos && bounds.min_x_blk != blk_id) { + max_x_pos = x_pos; + bounds.max_x_blk = blk_id; + } + if (y_pos == max_y_pos && bounds.min_y_blk != blk_id) { + max_y_pos = y_pos; + bounds.max_y_blk = blk_id; + } + } + + // Ensure the same block is set as the bounds. + // If there is not a bug in the above code, then this could imply that a + // net only connects to a single APBlock, which does not make sense in this + // context. + VTR_ASSERT_SAFE(bounds.min_x_blk != bounds.max_x_blk); + VTR_ASSERT_SAFE(bounds.min_y_blk != bounds.max_y_blk); + + return bounds; +} + +void B2BSolver::add_connection_to_system(APBlockId first_blk_id, + APBlockId second_blk_id, + size_t num_pins, + double net_w, + const vtr::vector& blk_locs, + std::vector>& triplet_list, + Eigen::VectorXd& b) { + // To make the code below simpler, we assume that the first block is always + // moveable. + if (netlist_.block_mobility(first_blk_id) != APBlockMobility::MOVEABLE) { + if (netlist_.block_mobility(second_blk_id) != APBlockMobility::MOVEABLE) { + // If both blocks are fixed, do not connect them. + return; + } + // If the first block is fixed and the second block is moveable, swap them. + std::swap(first_blk_id, second_blk_id); + } + + // Compute the weight of the connection. + // From the Kraftwerk2 paper: + // w = (2 / (P - 1)) * (1 / distance) + // + // epsilon is needed to prevent numerical instability. If two nodes are on top of each other. + // The denominator of weight is zero, which causes infinity term in the matrix. Another way of + // interpreting epsilon is the minimum distance two nodes are considered to be in placement. + double dist = std::max(std::abs(blk_locs[first_blk_id] - blk_locs[second_blk_id]), distance_epsilon_); + double w = net_w * (2.0 / static_cast(num_pins - 1)) * (1.0 / dist); + + // Update the connectivity matrix and the constant vector. + // This is similar to how connections are added for the quadratic formulation. + size_t first_row_id = (size_t)blk_id_to_row_id_[first_blk_id]; + if (netlist_.block_mobility(second_blk_id) == APBlockMobility::MOVEABLE) { + size_t second_row_id = (size_t)blk_id_to_row_id_[second_blk_id]; + triplet_list.emplace_back(first_row_id, first_row_id, w); + triplet_list.emplace_back(second_row_id, second_row_id, w); + triplet_list.emplace_back(first_row_id, second_row_id, -w); + triplet_list.emplace_back(second_row_id, first_row_id, -w); + } else { + triplet_list.emplace_back(first_row_id, first_row_id, w); + b(first_row_id) += w * blk_locs[second_blk_id]; + } +} + +void B2BSolver::init_linear_system(PartialPlacement& p_placement) { + // Reset the linear system + A_sparse_x = Eigen::SparseMatrix(num_moveable_blocks_, num_moveable_blocks_); + A_sparse_y = Eigen::SparseMatrix(num_moveable_blocks_, num_moveable_blocks_); + b_x = Eigen::VectorXd::Zero(num_moveable_blocks_); + b_y = Eigen::VectorXd::Zero(num_moveable_blocks_); + + // Create triplet lists to store the sparse positions to update and reserve + // space for them. + size_t num_nets = netlist_.nets().size(); + std::vector> triplet_list_x; + triplet_list_x.reserve(num_nets); + std::vector> triplet_list_y; + triplet_list_y.reserve(num_nets); + + for (APNetId net_id : netlist_.nets()) { + size_t num_pins = netlist_.net_pins(net_id).size(); + VTR_ASSERT_SAFE_MSG(num_pins > 1, "net must have at least 2 pins"); + + double net_w = net_weights_[net_id]; + + // Find the bounding blocks + APNetBounds net_bounds = get_unique_net_bounds(net_id, p_placement, netlist_); + + // Add an edge from every block to their bounds (ignoring the bounds + // themselves for now). + // FIXME: If one block has multiple pins, it may connect to the bounds + // multiple times. Should investigate the effect of this. + for (APPinId pin_id : netlist_.net_pins(net_id)) { + APBlockId blk_id = netlist_.pin_block(pin_id); + if (blk_id != net_bounds.max_x_blk && blk_id != net_bounds.min_x_blk) { + add_connection_to_system(blk_id, net_bounds.max_x_blk, num_pins, net_w, p_placement.block_x_locs, triplet_list_x, b_x); + add_connection_to_system(blk_id, net_bounds.min_x_blk, num_pins, net_w, p_placement.block_x_locs, triplet_list_x, b_x); + } + if (blk_id != net_bounds.max_y_blk && blk_id != net_bounds.min_y_blk) { + add_connection_to_system(blk_id, net_bounds.max_y_blk, num_pins, net_w, p_placement.block_y_locs, triplet_list_y, b_y); + add_connection_to_system(blk_id, net_bounds.min_y_blk, num_pins, net_w, p_placement.block_y_locs, triplet_list_y, b_y); + } + } + + // Connect the bounds to each other. Its just easier to put these here + // instead of in the for loop above. + add_connection_to_system(net_bounds.max_x_blk, net_bounds.min_x_blk, num_pins, net_w, p_placement.block_x_locs, triplet_list_x, b_x); + add_connection_to_system(net_bounds.max_y_blk, net_bounds.min_y_blk, num_pins, net_w, p_placement.block_y_locs, triplet_list_y, b_y); + } + + // Build the sparse connectivity matrices from the triplets. + A_sparse_x.setFromTriplets(triplet_list_x.begin(), triplet_list_x.end()); + A_sparse_y.setFromTriplets(triplet_list_y.begin(), triplet_list_y.end()); +} + +// This function adds anchors for legalized solution. Anchors are treated as fixed node, +// each connecting to a movable node. Number of nodes in a anchor net is always 2. +void B2BSolver::update_linear_system_with_anchors(unsigned iteration) { + VTR_ASSERT_SAFE_MSG(iteration != 0, + "no fixed solution to anchor to in the first iteration"); + // Get the anchor weight based on the iteration number. We want the anchor + // weights to get stronger as we get later in global placement. Found that + // an exponential weight term worked well for this. + double coeff_pseudo_anchor = anchor_weight_mult_ * std::exp((double)iteration / anchor_weight_exp_fac_); + + // Add an anchor for each moveable block to its solved position. + for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { + APRowId row_id = APRowId(row_id_idx); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + double pseudo_w_x = coeff_pseudo_anchor * 2.0; + double pseudo_w_y = coeff_pseudo_anchor * 2.0; + A_sparse_x.coeffRef(row_id_idx, row_id_idx) += pseudo_w_x; + A_sparse_y.coeffRef(row_id_idx, row_id_idx) += pseudo_w_y; + b_x(row_id_idx) += pseudo_w_x * block_x_locs_legalized[blk_id]; + b_y(row_id_idx) += pseudo_w_y * block_y_locs_legalized[blk_id]; + } +} + +void B2BSolver::store_solution_into_placement(Eigen::VectorXd& x_soln, + Eigen::VectorXd& y_soln, + PartialPlacement& p_placement) { + for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { + // Since we are capping the number of iterations, the solver may not + // have enough time to converge on a solution that is on the device. + // We just clamp the solution to zero for now. + // TODO: Should handle this better. If the solution is very negative + // it may indicate a bug. + if (x_soln[row_id_idx] < 0.0) + x_soln[row_id_idx] = 0.0; + if (y_soln[row_id_idx] < 0.0) + y_soln[row_id_idx] = 0.0; + + APRowId row_id = APRowId(row_id_idx); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + p_placement.block_x_locs[blk_id] = x_soln[row_id_idx]; + p_placement.block_y_locs[blk_id] = y_soln[row_id_idx]; + } +} + +void B2BSolver::print_statistics() { + VTR_LOG("B2B Solver Statistics:\n"); + VTR_LOG("\tTotal number of CG iterations: %u\n", total_num_cg_iters_); + VTR_LOG("\tTotal time spent building linear system: %g seconds\n", + total_time_spent_building_linear_system_); + VTR_LOG("\tTotal time spent solving linear system: %g seconds\n", + total_time_spent_solving_linear_system_); +} + +#endif // EIGEN_INSTALLED diff --git a/vpr/src/analytical_place/analytical_solver.h b/vpr/src/analytical_place/analytical_solver.h index 33397a554d1..2d748e2a493 100644 --- a/vpr/src/analytical_place/analytical_solver.h +++ b/vpr/src/analytical_place/analytical_solver.h @@ -9,7 +9,9 @@ #pragma once #include -#include "ap_netlist_fwd.h" +#include "ap_flow_enums.h" +#include "ap_netlist.h" +#include "device_grid.h" #include "vtr_strong_id.h" #include "vtr_vector.h" @@ -24,20 +26,13 @@ // Pop the GCC diagnostics state back to what it was before. #pragma GCC diagnostic pop -#endif // EIGEN_INSTALLED +#endif // EIGEN_INSTALLED // Forward declarations class PartialPlacement; class APNetlist; - -/** - * @brief Enumeration of all of the solvers currently implemented in VPR. - * - * NOTE: More are coming. - */ -enum class e_analytical_solver { - QP_HYBRID // A solver which optimizes the quadratic HPWL of the design. -}; +class AtomNetlist; +class PreClusterTimingManager; /** * @brief A strong ID for the rows in a matrix used during solving. @@ -58,7 +53,7 @@ typedef vtr::StrongId APRowId; * compare different solvers. */ class AnalyticalSolver { -public: + public: virtual ~AnalyticalSolver() {} /** @@ -67,7 +62,11 @@ class AnalyticalSolver { * Initializes the internal data members of the base class which are useful * for all solvers. */ - AnalyticalSolver(const APNetlist &netlist); + AnalyticalSolver(const APNetlist& netlist, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity); /** * @brief Run an iteration of the solver using the given partial placement @@ -87,10 +86,17 @@ class AnalyticalSolver { * @param p_placement A "hint" to a legal solution that the solver should * try and be like. */ - virtual void solve(unsigned iteration, PartialPlacement &p_placement) = 0; + virtual void solve(unsigned iteration, PartialPlacement& p_placement) = 0; -protected: + /** + * @brief Print statistics on the analytical solver. + * + * This is expected to be called after global placement to collect cummulative + * information on how the solver performed. + */ + virtual void print_statistics() = 0; + protected: /// @brief The APNetlist the solver is optimizing over. It is implied that /// the netlist is not being modified during global placement. const APNetlist& netlist_; @@ -99,6 +105,9 @@ class AnalyticalSolver { /// when allocating matrices. size_t num_moveable_blocks_ = 0; + /// @brief The number of fixed blocks in the netlist. + size_t num_fixed_blocks_ = 0; + /// @brief A lookup between a moveable APBlock and its linear ID from /// [0, num_moveable_blocks). Fixed blocks will return an invalid row /// ID. This is useful when knowing which row in the matrix @@ -109,13 +118,27 @@ class AnalyticalSolver { /// APBlock it represents. useful when getting the results from the /// solver. vtr::vector row_id_to_blk_id_; + + /// @brief The base weight of each net in the AP netlist. This weight can + /// be used to make the solver more interested in some nets over + /// others. These weights can be any positive value, but are often + /// between 0 and 1. + vtr::vector net_weights_; + + /// @brief The verbosity of log messages in the Analytical Solver. + int log_verbosity_; }; /** * @brief A factory method which creates an Analytical Solver of the given type. */ -std::unique_ptr make_analytical_solver(e_analytical_solver solver_type, - const APNetlist &netlist); +std::unique_ptr make_analytical_solver(e_ap_analytical_solver solver_type, + const APNetlist& netlist, + const DeviceGrid& device_grid, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity); // The Eigen library is used to solve matrix equations in the following solvers. // The solver cannot be built if Eigen is not installed. @@ -145,7 +168,7 @@ std::unique_ptr make_analytical_solver(e_analytical_solver sol * https://doi.org/10.1109/TCAD.2005.846365 */ class QPHybridSolver : public AnalyticalSolver { -private: + private: /// @brief The threshold for the number of pins a net will have to use the /// Star or Clique net models. If the number of pins is larger /// than this number, a star node will be created. @@ -156,6 +179,29 @@ class QPHybridSolver : public AnalyticalSolver { /// sparse. static constexpr size_t star_num_pins_threshold = 3; + // The following constants are used to configure the anchor weighting. + // The weights of anchors grow exponentially each iteration by the following + // function: + // anchor_w = anchor_weight_mult_ * e^(iter / anchor_weight_exp_fac_) + // The numbers below were empircally found to work well. + + /// @brief Multiplier for the anchorweight. The smaller this number is, the + /// weaker the anchors will be at the start. + static constexpr double anchor_weight_mult_ = 0.001; + + /// @brief Factor for controlling the growth of the exponential term in the + /// weight factor function. Larger numbers will cause the anchor + /// weights to grow slower. + static constexpr double anchor_weight_exp_fac_ = 5.0; + + /// @brief Due to the iterative nature of Conjugate Gradient method, the + /// solver may overstep 0 to give a slightly negative solution. This + /// is ok, and we can just clamp the position to 0. However, negative + /// values that are too large may be indicative of an issue in the + /// formulation. This value is how negative we tolerate the positions + /// to be. + static constexpr double negative_soln_tolerance_ = 1e-9; + /** * @brief Initializes the linear system of Ax = b_x and Ay = b_y based on * the APNetlist and the fixed APBlock locations. @@ -166,6 +212,51 @@ class QPHybridSolver : public AnalyticalSolver { */ void init_linear_system(); + /** + * @brief Intializes the guesses which will be used in the solver. + * + * The guesses will be used as starting points for the CG solver. The better + * these guesses are, the faster the solver will converge. + */ + void init_guesses(const DeviceGrid& device_grid); + + /** + * @brief Helper method to update the linear system with anchors to the + * current partial placement. + * + * For each moveable block (with row = i) in the netlist: + * A[i][i] = A[i][i] + coeff_pseudo_anchor; + * b[i] = b[i] + pos[block(i)] * coeff_pseudo_anchor; + * Where coeff_pseudo_anchor grows with each iteration. + * + * This is basically a fast way of adding a connection between all moveable + * blocks in the netlist and their target fixed placement location. + * + * See add_connection_to_system. + * + * @param A_sparse_diff The ceofficient matrix to update. + * @param b_x_diff The x-dimension constant vector to update. + * @param b_y_diff The y-dimension constant vector to update. + * @param p_placement The location the moveable blocks should be + * anchored to. + * @param num_moveable_blocks The number of moveable blocks in the netlist. + * @param row_id_to_blk_id Lookup for the row id from the APBlock Id. + * @param iteration The current iteration of the Global Placer. + */ + void update_linear_system_with_anchors(Eigen::SparseMatrix& A_sparse_diff, + Eigen::VectorXd& b_x_diff, + Eigen::VectorXd& b_y_diff, + PartialPlacement& p_placement, + unsigned iteration); + + /** + * @brief Store the x and y solutions in Eigen's vectors into the partial + * placement object. + */ + void store_solution_into_placement(const Eigen::VectorXd& x_soln, + const Eigen::VectorXd& y_soln, + PartialPlacement& p_placement); + // The following variables represent the linear system without any anchor // points. These are filled in the constructor and never modified. // When the anchor-points are taken into consideration, the diagonal of the @@ -181,19 +272,39 @@ class QPHybridSolver : public AnalyticalSolver { Eigen::VectorXd b_x; /// @brief The constant vector in the y dimension for the linear system. Eigen::VectorXd b_y; + /// @brief The number of variables in the solver. This is the sum of the + /// number of moveable blocks in the netlist and the number of star + /// nodes that exist. + size_t num_variables_ = 0; -public: + /// @brief The current guess for the x positions of the blocks. + Eigen::VectorXd guess_x; + /// @brief The current guess for the y positions of the blocks. + Eigen::VectorXd guess_y; + /// @brief The total number of CG iterations this solver has performed so far. + unsigned total_num_cg_iters_ = 0; + + public: /** * @brief Constructor of the QPHybridSolver * * Initializes internal data and constructs the initial linear system. */ - QPHybridSolver(const APNetlist& netlist) : AnalyticalSolver(netlist) { + QPHybridSolver(const APNetlist& netlist, + const DeviceGrid& device_grid, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity) + : AnalyticalSolver(netlist, atom_netlist, pre_cluster_timing_manager, ap_timing_tradeoff, log_verbosity) { // Initializing the linear system only depends on the netlist and fixed // block locations. Both are provided by the netlist, allowing this to // be initialized in the constructor. init_linear_system(); + + // Initialize the guesses for the first iteration. + init_guesses(device_grid); } /** @@ -216,8 +327,288 @@ class QPHybridSolver : public AnalyticalSolver { * @param p_placement A "guess" solution. The result will be written into * this object. */ - void solve(unsigned iteration, PartialPlacement &p_placement) final; + void solve(unsigned iteration, PartialPlacement& p_placement) final; + + /** + * @brief Print statistics of the solver. + */ + void print_statistics() final; }; -#endif // EIGEN_INSTALLED +/** + * @brief An Analytical Solver which tries to minimize the linear HPWL objective: + * SUM((xmax - xmin) + (ymax - ymin)) over all nets. + * + * This is implemented using the Bound2Bound method, which iteratively sets up a + * linear system of equations (similar to the QP Hybrid approach above) which + * solves a quadratic objective function. For a net model, each block connects + * to the current bounding blocks in the given dimension and the weight of this + * connection is inversly proportional to the distance of the block to the bound. + * After minimizing this system, the bounds are likely to change; so the system + * needs to be reconstructed and solved iteratively. + * + * This technique was proposed in Kraftwerk2, where they proved that the B2B Net + * Model will, in theory, converge on the linear HPWL solution. + * https://doi.org/10.1109/TCAD.2008.925783 + */ +class B2BSolver : public AnalyticalSolver { + private: + /** + * @brief Enumeration for different initial placements that this class can + * perform in the first iteration. + * + * TODO: Investigate other initial placement techniques, the first iteration + * can be very expensive. + */ + enum class e_initial_placement_type { + LeastDense //< Randomly place blocks as a uniform grid over the device. + }; + + /// @brief Which initial placement algorithm to use in the first iteration. + /// In the first iteration, we need some solution to initialize the + /// bounds. Some papers have found that setting it to a random + /// initial placement is the best approach. + static constexpr e_initial_placement_type initial_placement_ty_ = e_initial_placement_type::LeastDense; + + /// @brief Since the weights in the B2B model divide by the distance between + /// blocks and their bounds, that distance may get very very close to + /// 0. This causes the weight matrix to become numerically unstable. + /// We can gaurd against this by clamping the distance to not be smaller + /// than some epsilon. + /// Decreasing this number may lead to more instability, but can yield + /// a higher quality solution. + static constexpr double distance_epsilon_ = 0.01; + + /// @brief The gap between the HPWL of the current solved solution in the + /// B2B loop and the previous solved solution that is considered to + /// be close-enough to be converged (as a fraction of the current + /// solved solution HPWL). + /// Decreasing this number toward zero would cause the B2B solver to run + /// more iterations to try and reduce the HPWL further. + static constexpr double b2b_convergence_gap_fac_ = 0.001; + + /// @brief The number of times the B2B loop should "converge" before stopping + /// the loop. Due to numerical inaccuracies, it is possible for the + /// HPWL to bounce up and down as it converges. Increasing this number + /// will allow more bounces which may get better quality; however + /// more iterations will need to be run. + static constexpr unsigned target_num_b2b_convergences_ = 2; + + /// @brief Max number of bound update / solve iterations. Increasing this + /// number will yield better quality at the expense of runtime. + static constexpr unsigned max_num_bound_updates_ = 24; + + /// @brief Max number of iterations the Conjugate Gradient solver can perform. + /// Due to the weights getting very large in the early iterations of + /// Global Placement, the CG solver may take a very long time to + /// converge; but the solution quality will not change much. By + /// default the max iteration is set to 2 * num_moveable_blocks; + /// which causes the first iteration of B2B to become quadratic in the + /// number of moveable blocks if it cannot converge. Found through + /// experimentation that this can be clamped to a much smaller number + /// to prevent this behaviour and get good runtime. + // TODO: Need to investigate this more to find a good number for this. + // TODO: Should this be a proportion of the design size? + static constexpr unsigned max_cg_iterations_ = 150; + + // The following constants are used to configure the anchor weighting. + // The weights of anchors grow exponentially each iteration by the following + // function: + // anchor_w = anchor_weight_mult_ * e^(iter / anchor_weight_exp_fac_) + // The numbers below were empircally found to work well. + + /// @brief Multiplier for the anchorweight. The smaller this number is, the + /// weaker the anchors will be at the start. + static constexpr double anchor_weight_mult_ = 0.01; + + /// @brief Factor for controlling the growth of the exponential term in the + /// weight factor function. Larger numbers will cause the anchor + /// weights to grow slower. + static constexpr double anchor_weight_exp_fac_ = 5.0; + + public: + B2BSolver(const APNetlist& ap_netlist, + const DeviceGrid& device_grid, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity) + : AnalyticalSolver(ap_netlist, atom_netlist, pre_cluster_timing_manager, ap_timing_tradeoff, log_verbosity) + , device_grid_width_(device_grid.width()) + , device_grid_height_(device_grid.height()) {} + + /** + * @brief Perform an iteration of the B2B solver, storing the result into + * the partial placement object passed in. + * + * In the first iteration (iteration = 0), the partial placement object will + * be ignored, and a random initial placement will be used to initially + * construct the system of equations. In all other iterations, the previous + * solved solution will be used. + * + * The B2B solver will then iteratively solve the system of equations and + * update the system to achieve a good HPWL solution which is close to the + * linear HPWL solution. Due to numerical issues with this algorithm, we will + * likely not converge on the true minimum HPWL solution, but it should be + * close. + * + * See the base class for more information. + * + * @param iteration + * The current iteration of the Global Placer + * @param p_placement + * A "guess" solution. The result will be written into this object. + * In all iterations other than the first, this solution will be used + * as anchor-points in the system. + */ + void solve(unsigned iteration, PartialPlacement& p_placement) final; + + /** + * @brief Print overall statistics on this solver. + * + * This is expected to be called after all iterations of Global Placement + * has been complete. + */ + void print_statistics() final; + + private: + /** + * @brief Run the B2B outer solving loop. + * + * The placement in p_placement should be initialized with the initial + * positions of the blocks that the B2B algorithm should use to build the + * first system of equations. This placement will be iteratively updated + * with better and better solutions as B2B iterates. + * + * If iteration is 0, no anchor-blocks will be added to the system, otherwise + * the solution in block_locs_legalized will be used as anchor-blocks. + */ + void b2b_solve_loop(unsigned iteration, PartialPlacement& p_placement); + + /** + * @brief Randomly distributes AP blocks using a normal distribution. + */ + void initialize_placement_random_normal(PartialPlacement& p_placement); + + /** + * @brief Randomly distributes AP blocks using a uniform distribution. + */ + void initialize_placement_random_uniform(PartialPlacement& p_placement); + /** + * @brief Randomly distributes AP blocks using as a uniform grid. + */ + void initialize_placement_least_dense(PartialPlacement& p_placement); + + /** + * @brief Add a weighted connection to the linear system between the first + * and second blocks for a single dimension. + * + * This method is used to construct different linear systems for different + * dimensions (x and y). Since the act of adding weighted connections is the + * same regardless of dimension, this method passes in dimension-specific + * information to be updated. + * + * @param first_blk_id + * @param second_blk_id + * @param num_pins + * The number of pins in the hypernet connecting the two blocks. + * @param blk_locs + * The location of all blocks in a given dimension. + * @param triplet_list + * The triplet list which will be used to construct the connectivity + * matrix for this dimension. + * @param b + * The constant vector for this dimension. + */ + void add_connection_to_system(APBlockId first_blk_id, + APBlockId second_blk_id, + size_t num_pins, + double net_w, + const vtr::vector& blk_locs, + std::vector>& triplet_list, + Eigen::VectorXd& b); + + /** + * @brief Initializes the linear system with the given partial placement. + * + * Blocks will be connected to the bounding blocks of their nets using + * weighted connections, with weight inversly proportional to the distance + * between blocks and the bounds. When solved in a quadratic equation this + * approximates a linear equation. + * + * This will set the connectivity matrices (A) and constant vectors (b) to + * be solved by B2B. + */ + void init_linear_system(PartialPlacement& p_placement); + + /** + * @brief Updates the linear system with anchor-blocks from the legalized + * solution. + */ + void update_linear_system_with_anchors(unsigned iteration); + + /** + * @brief Store the x and y solutions in Eigen's vectors into the partial + * placement object. + * + * Note: The x_soln and y_soln may be modified if it is found that the + * solution is imposible (i.e. has negative positions). + */ + void store_solution_into_placement(Eigen::VectorXd& x_soln, + Eigen::VectorXd& y_soln, + PartialPlacement& p_placement); + + // The following are variables used to store the system of equations to be + // solved in the x and y dimensions. The equations are of the form: + // Ax = b + // There are two sets of matrices and vectors since the x and y dimensions + // of the objective are independent and can be solved separately. + // These are updated each iteration of the B2B loop. + + /// @brief The coefficient / connectivity matrix for the x dimension. + Eigen::SparseMatrix A_sparse_x; + /// @brief The coefficient / connectivity matrix for the y dimension. + Eigen::SparseMatrix A_sparse_y; + /// @brief The constant vector in the x dimension. + Eigen::VectorXd b_x; + /// @brief The constant vector in the y dimension. + Eigen::VectorXd b_y; + + // The following is the solution of the previous iteration of this solver. + // They are updated at the end of solve() and are used as the starting point + // for the next call to solve. + vtr::vector block_x_locs_solved; + vtr::vector block_y_locs_solved; + + // The following are the legalized solution coming into the analytical solver + // (other than the first iteration). These are stored to be used as anchor + // blocks during the solver. + vtr::vector block_x_locs_legalized; + vtr::vector block_y_locs_legalized; + + /// @brief The width of the device grid. Used for randomly generating points + /// on the grid. + size_t device_grid_width_; + /// @brief The height of the device grid. Used for randomly generating points + /// on the grid. + size_t device_grid_height_; + + /// @brief The total number of CG iterations that this solver has performed + /// so far. This can be a useful metric for the amount of work the + /// solver performs. + unsigned total_num_cg_iters_ = 0; + + /// @brief The total time spent building the linear systems in the B2B solve + /// loop so far. This includes creating connections between blocks + /// in the connectivity matrix and constant vector as well as adding + /// anchor connections. + float total_time_spent_building_linear_system_ = 0.0f; + + /// @brief The total time spent solving the linear systems in the B2B solve + /// loop so far. This includes creating the CG solver object and + /// actually solving for a solution. + float total_time_spent_solving_linear_system_ = 0.0f; +}; + +#endif // EIGEN_INSTALLED diff --git a/vpr/src/analytical_place/ap_flow_enums.h b/vpr/src/analytical_place/ap_flow_enums.h new file mode 100644 index 00000000000..91c1407059d --- /dev/null +++ b/vpr/src/analytical_place/ap_flow_enums.h @@ -0,0 +1,55 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Enumerations used by the Analytical Placement Flow. + */ + +#pragma once + +/** + * @brief The type of an Analytical Solver. + * + * The Analytical Placement flow may implement different Analytical Solvers as + * part of the Global Placer. This enum can select between these different + * Analytical Solvers. + */ +enum class e_ap_analytical_solver { + QP_Hybrid, ///< Analytical Solver which uses the hybrid net model to optimize the quadratic HPWL objective. + LP_B2B ///< Analytical Solver which uses the B2B net model to optimize the linear HPWL objective. +}; + +/** + * @brief The type of a Partial Legalizer. + * + * The Analytical Placement flow may implement different Partial Legalizer as + * part of the Global Placer. This enum can select between these different + * Partial Legalizers. + */ +enum class e_ap_partial_legalizer { + BiPartitioning, ///< Partial Legalizer which forms minimum windows around dense regions and uses bipartitioning to spread blocks over windows. + FlowBased ///> Partial Legalizer which flows blocks from overfilled bins to underfilled bins. +}; + +/** + * @brief The type of a Full Legalizer. + * + * The Analytical Placement flow may implement different Full Legalizers. This + * enum can select between these different Full Legalizers. + */ +enum class e_ap_full_legalizer { + Naive, ///< The Naive Full Legalizer, which clusters atoms placed in the same tile and tries to place them in that tile according to the flat placement. + APPack, ///< The APPack Full Legalizer, which uses the flat placement to improve the Packer and Placer. + Basic_Min_Disturbance ///< The Basic Min. Disturbance Full Legalizer, which tries to reconstruct a clustered placement that is as close to the incoming flat placement as it can. +}; + +/** + * @brief The type of a Detailed Placer. + * + * The Analytical Placement flow may implement different Detailed Placers. This + * enum can select between these different Detailed Placers. + */ +enum class e_ap_detailed_placer { + Identity, ///< The Identity Detailed Placer, which does not perform any optimizations on the legalized placement. Needed as a placeholder. + Annealer ///< The Annealer Detailed Placer, which runs the annealer found in the Place part of the VPR flow (using the same options as the Placement stage). +}; diff --git a/vpr/src/analytical_place/ap_netlist.cpp b/vpr/src/analytical_place/ap_netlist.cpp index 6ae59e596b4..26c80119b9a 100644 --- a/vpr/src/analytical_place/ap_netlist.cpp +++ b/vpr/src/analytical_place/ap_netlist.cpp @@ -9,13 +9,13 @@ #include #include "netlist_fwd.h" #include "netlist_utils.h" -#include "vpr_types.h" +#include "prepack.h" #include "vtr_assert.h" /* * Blocks */ -const t_pack_molecule* APNetlist::block_molecule(const APBlockId id) const { +PackMoleculeId APNetlist::block_molecule(const APBlockId id) const { VTR_ASSERT_SAFE(valid_block_id(id)); return block_molecules_[id]; @@ -37,11 +37,11 @@ const APFixedBlockLoc& APNetlist::block_loc(const APBlockId id) const { /* * Mutators */ -APBlockId APNetlist::create_block(const std::string& name, const t_pack_molecule* mol) { +APBlockId APNetlist::create_block(const std::string& name, PackMoleculeId molecule_id) { APBlockId blk_id = Netlist::create_block(name); // Initialize the data - block_molecules_.insert(blk_id, mol); + block_molecules_.insert(blk_id, molecule_id); block_mobilities_.insert(blk_id, APBlockMobility::MOVEABLE); block_locs_.insert(blk_id, APFixedBlockLoc()); @@ -49,7 +49,7 @@ APBlockId APNetlist::create_block(const std::string& name, const t_pack_molecule VTR_ASSERT(validate_block_sizes()); // Check post-conditions: values - VTR_ASSERT(block_molecule(blk_id) == mol); + VTR_ASSERT(block_molecule(blk_id) == molecule_id); VTR_ASSERT(block_mobility(blk_id) == APBlockMobility::MOVEABLE); return blk_id; @@ -59,18 +59,18 @@ void APNetlist::set_block_loc(const APBlockId id, const APFixedBlockLoc& loc) { VTR_ASSERT_SAFE(valid_block_id(id)); // Check that the location is fixed; if all dims are unfixed then it is not fixed. - if (loc.x == APFixedBlockLoc::UNFIXED_DIM && - loc.y == APFixedBlockLoc::UNFIXED_DIM && - loc.sub_tile == APFixedBlockLoc::UNFIXED_DIM && - loc.layer_num == APFixedBlockLoc::UNFIXED_DIM) + if (loc.x == APFixedBlockLoc::UNFIXED_DIM + && loc.y == APFixedBlockLoc::UNFIXED_DIM + && loc.sub_tile == APFixedBlockLoc::UNFIXED_DIM + && loc.layer_num == APFixedBlockLoc::UNFIXED_DIM) return; // Ensure that the block is fixed to a single position on the grid (x, y, layer). // sub-tile is allowed to be unfixed. - VTR_ASSERT(loc.x != APFixedBlockLoc::UNFIXED_DIM && - loc.y != APFixedBlockLoc::UNFIXED_DIM && - loc.layer_num != APFixedBlockLoc::UNFIXED_DIM && - "AP: Currently, AP assumes block is locked down to a single position on the device grid."); + VTR_ASSERT(loc.x != APFixedBlockLoc::UNFIXED_DIM + && loc.y != APFixedBlockLoc::UNFIXED_DIM + && loc.layer_num != APFixedBlockLoc::UNFIXED_DIM + && "AP: Currently, AP assumes block is locked down to a single position on the device grid."); block_locs_[id] = loc; block_mobilities_[id] = APBlockMobility::FIXED; @@ -207,4 +207,3 @@ bool APNetlist::validate_net_sizes_impl(size_t /*num_nets*/) const { // No AP-specific net data to check return true; } - diff --git a/vpr/src/analytical_place/ap_netlist.h b/vpr/src/analytical_place/ap_netlist.h index ec64ae38a9b..1bfe8c5e49b 100644 --- a/vpr/src/analytical_place/ap_netlist.h +++ b/vpr/src/analytical_place/ap_netlist.h @@ -23,9 +23,7 @@ #include #include "netlist.h" #include "ap_netlist_fwd.h" - -// Forward declarations -class t_pack_molecule; +#include "prepack.h" /** * @brief Struct to store fixed block location information @@ -37,10 +35,10 @@ class t_pack_molecule; */ struct APFixedBlockLoc { // Value that represents an unfixed dimension. - static constexpr int UNFIXED_DIM = -1; + static constexpr float UNFIXED_DIM = -1; // The dimensions to fix. - int x = UNFIXED_DIM; - int y = UNFIXED_DIM; + float x = UNFIXED_DIM; + float y = UNFIXED_DIM; int layer_num = UNFIXED_DIM; int sub_tile = UNFIXED_DIM; }; @@ -51,8 +49,8 @@ struct APFixedBlockLoc { * block ids. */ enum class APBlockMobility : bool { - MOVEABLE, // The block is not constrained in any dimension. - FIXED // The block is fixed. + MOVEABLE, // The block is not constrained in any dimension. + FIXED // The block is fixed. }; /** @@ -64,7 +62,7 @@ enum class APBlockMobility : bool { * APBlocks. These need not have physical meaning. */ class APNetlist : public Netlist { -public: + public: /** * @brief Constructs a netlist * @@ -72,18 +70,19 @@ class APNetlist : public Netlist { * @param id A unique identifier for the netlist (e.g. a secure digest of * the input file) */ - APNetlist(std::string name = "", std::string id = "") : Netlist(name, id) {} + APNetlist(std::string name = "", std::string id = "") + : Netlist(name, id) {} APNetlist(const APNetlist& rhs) = default; APNetlist& operator=(const APNetlist& rhs) = default; -public: // Public Accessors + public: // Public Accessors /* * Blocks */ /// @brief Returns the molecule that this block represents. - const t_pack_molecule* block_molecule(const APBlockId id) const; + PackMoleculeId block_molecule(const APBlockId id) const; /// @brief Returns the mobility of this block. APBlockMobility block_mobility(const APBlockId id) const; @@ -92,7 +91,7 @@ class APNetlist : public Netlist { /// This method should not be used if the block is moveable. const APFixedBlockLoc& block_loc(const APBlockId id) const; -public: // Public Mutators + public: // Public Mutators /* * Note: all create_*() functions will silently return the appropriate ID * if it has already been created. @@ -104,7 +103,7 @@ class APNetlist : public Netlist { * @param name The unique name of the block * @param mol The molecule the block represents */ - APBlockId create_block(const std::string& name, const t_pack_molecule* mol); + APBlockId create_block(const std::string& name, PackMoleculeId molecule_id); /** * @brief Fixes a block at the given location @@ -143,7 +142,7 @@ class APNetlist : public Netlist { */ APNetId create_net(const std::string& name); -private: // Private Members + private: // Private Members /* * Netlist compression / optimization */ @@ -180,13 +179,12 @@ class APNetlist : public Netlist { bool validate_pin_sizes_impl(size_t num_pins) const override; bool validate_net_sizes_impl(size_t num_nets) const override; -private: // Private Data + private: // Private Data /// @brief Molecule of each block - vtr::vector_map block_molecules_; + vtr::vector_map block_molecules_; /// @brief Type of each block vtr::vector_map block_mobilities_; /// @brief Location of each block (if fixed). /// NOTE: This vector will likely be quite sparse. vtr::vector_map block_locs_; }; - diff --git a/vpr/src/analytical_place/ap_netlist_fwd.h b/vpr/src/analytical_place/ap_netlist_fwd.h index 3fc9e87dea7..ede36cf6a07 100644 --- a/vpr/src/analytical_place/ap_netlist_fwd.h +++ b/vpr/src/analytical_place/ap_netlist_fwd.h @@ -26,7 +26,7 @@ class APNetlist; * @brief A unique identifier for a block in the AP netlist */ class APBlockId : public ParentBlockId { -public: + public: static constexpr APBlockId INVALID() { return APBlockId(); } using ParentBlockId::ParentBlockId; @@ -37,7 +37,7 @@ class APBlockId : public ParentBlockId { * @brief A unique identifier for a net in the AP netlist */ class APNetId : public ParentNetId { -public: + public: static constexpr APNetId INVALID() { return APNetId(); } using ParentNetId::ParentNetId; @@ -48,7 +48,7 @@ class APNetId : public ParentNetId { * @brief A unique identifier for a port in the AP netlist */ class APPortId : public ParentPortId { -public: + public: static constexpr APPortId INVALID() { return APPortId(); } using ParentPortId::ParentPortId; @@ -59,7 +59,7 @@ class APPortId : public ParentPortId { * @brief A unique identifier for a pin in the AP netlist */ class APPinId : public ParentPinId { -public: + public: static constexpr APPinId INVALID() { return APPinId(); } using ParentPinId::ParentPinId; @@ -101,4 +101,3 @@ struct hash { } }; } // namespace std - diff --git a/vpr/src/analytical_place/detailed_placer.cpp b/vpr/src/analytical_place/detailed_placer.cpp new file mode 100644 index 00000000000..75001fe4c42 --- /dev/null +++ b/vpr/src/analytical_place/detailed_placer.cpp @@ -0,0 +1,109 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Implementation of the Detailed Placers. + */ + +#include "detailed_placer.h" +#include +#include "PlacementDelayModelCreator.h" +#include "ap_flow_enums.h" +#include "atom_netlist.h" +#include "clustered_netlist.h" +#include "clustered_netlist_utils.h" +#include "echo_files.h" +#include "flat_placement_types.h" +#include "globals.h" +#include "physical_types.h" +#include "place_and_route.h" +#include "place_delay_model.h" +#include "placer.h" +#include "vpr_error.h" +#include "vpr_types.h" +#include "vpr_utils.h" +#include "vtr_time.h" + +std::unique_ptr make_detailed_placer(e_ap_detailed_placer detailed_placer_type, + const BlkLocRegistry& curr_clustered_placement, + const AtomNetlist& atom_netlist, + const ClusteredNetlist& clustered_netlist, + t_vpr_setup& vpr_setup, + const t_arch& arch) { + switch (detailed_placer_type) { + case e_ap_detailed_placer::Identity: + return std::make_unique(); + case e_ap_detailed_placer::Annealer: + return std::make_unique(curr_clustered_placement, + atom_netlist, + clustered_netlist, + vpr_setup, + arch); + default: + VPR_FATAL_ERROR(VPR_ERROR_AP, + "Unrecognized detailed placer type"); + } +} + +AnnealerDetailedPlacer::AnnealerDetailedPlacer(const BlkLocRegistry& curr_clustered_placement, + const AtomNetlist& atom_netlist, + const ClusteredNetlist& clustered_netlist, + t_vpr_setup& vpr_setup, + const t_arch& arch) + : DetailedPlacer() + // TODO: These two variables needed to be stored in the class since + // the Placer stores a reference to these objects. These + // should really be initialized and stored into the Placer + // class directly. + , pb_gpin_lookup_(g_vpr_ctx.device().logical_block_types) + , netlist_pin_lookup_(clustered_netlist, atom_netlist, pb_gpin_lookup_) { + // Initialize the place delay model. + // TODO: This initialization is complicated. Should be moved within create_delay_model + // or something. + std::shared_ptr place_delay_model; + if (vpr_setup.PlacerOpts.place_algorithm.is_timing_driven()) { + place_delay_model = PlacementDelayModelCreator::create_delay_model(vpr_setup.PlacerOpts, + vpr_setup.RouterOpts, + (const Netlist<>&)clustered_netlist, + &vpr_setup.RoutingArch, + vpr_setup.Segments, + arch.Chans, + arch.directs, + false /*is_flat*/); + if (isEchoFileEnabled(E_ECHO_PLACEMENT_DELTA_DELAY_MODEL)) { + place_delay_model->dump_echo(getEchoFileName(E_ECHO_PLACEMENT_DELTA_DELAY_MODEL)); + } + } + + placer_ = std::make_unique((const Netlist<>&)clustered_netlist, + curr_clustered_placement, + vpr_setup.PlacerOpts, + vpr_setup.AnalysisOpts, + vpr_setup.NocOpts, + pb_gpin_lookup_, + netlist_pin_lookup_, + FlatPlacementInfo(), + place_delay_model, + g_vpr_ctx.placement().cube_bb, + false /*is_flat*/, + false /*quiet*/); +} + +void AnnealerDetailedPlacer::optimize_placement() { + // Create a scoped timer for the detailed placer. + vtr::ScopedStartFinishTimer full_legalizer_timer("AP Detailed Placer"); + + // Prevent the annealer from directly modifying the global legal placement. + // It should only modify its own, local placement. + g_vpr_ctx.mutable_placement().lock_loc_vars(); + + // Run the simulated annealer. + placer_->place(); + + // Copy the placement solution into the global placement solution. + placer_->copy_locs_to_global_state(g_vpr_ctx.mutable_placement()); + + // Since the placement was modified, need to resynchronize the pins in the + // clusters. + post_place_sync(); +} diff --git a/vpr/src/analytical_place/detailed_placer.h b/vpr/src/analytical_place/detailed_placer.h new file mode 100644 index 00000000000..46f769a4d22 --- /dev/null +++ b/vpr/src/analytical_place/detailed_placer.h @@ -0,0 +1,108 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Defines the DetailedPlacer class which takes a fully legal clustering + * and placement and optimizes them while remaining legal. + */ + +#pragma once + +#include +#include "ap_flow_enums.h" +#include "clustered_netlist_utils.h" +#include "placer.h" +#include "vpr_utils.h" + +/** + * @brief The detailed placer in an AP flow. + * + * Given a fully legal clustering and clustered placement, will optimize the + * solution while remaining fully legal (able to be used in the rest of the VPR + * flow). + */ +class DetailedPlacer { + public: + virtual ~DetailedPlacer() {} + + DetailedPlacer() = default; + + /** + * @brief Optimize the current legal placement. + */ + virtual void optimize_placement() = 0; +}; + +/** + * @brief A factory method which creates a Detailed Placer of the given type. + */ +std::unique_ptr make_detailed_placer(e_ap_detailed_placer detailed_placer_type, + const BlkLocRegistry& curr_clustered_placement, + const AtomNetlist& atom_netlist, + const ClusteredNetlist& clustered_netlist, + t_vpr_setup& vpr_setup, + const t_arch& arch); + +/** + * @brief The Identity Detailed Placer. + * + * This detailed placer does literally nothing to the legal placement. This + * class is used as a placeholder to make the higher-level code easier to work + * with. + */ +class IdentityDetailedPlacer : public DetailedPlacer { + public: + using DetailedPlacer::DetailedPlacer; + + void optimize_placement() final {} +}; + +/** + * @brief The Annealer Detailed Placer. + * + * This Detailed Placer passes the legal solution into the Annealer in the + * VPR flow (uses the legal solution as the initial placement). This performs + * the Simulated Annealing algorithm on the solution at the cluster level to + * try and find a better clustered placement. + * + * This Detailed Placer reuses the options from the Placer stage of VPR for this + * stage. So options passed to the Placer will be used in here. + */ +class AnnealerDetailedPlacer : public DetailedPlacer { + public: + /** + * @brief Construct the Annealer Detailed Placer class. + * + * @param curr_clustered_placement + * The legalized placement solution to pass as the initial placement + * into the annealer. + * @param atom_netlist + * The netlist of atoms in the circuit. + * @param clustered_netlist + * The netlist of clusters created by the Full Legalizer. + * @param vpr_setup + * The setup variables, used to get the params from the user. + * @param arch + * The FPGA architecture to optimize onto. + */ + AnnealerDetailedPlacer(const BlkLocRegistry& curr_clustered_placement, + const AtomNetlist& atom_netlist, + const ClusteredNetlist& clustered_netlist, + t_vpr_setup& vpr_setup, + const t_arch& arch); + + /** + * @brief Run the annealer. + */ + void optimize_placement() final; + + private: + /// @brief The placer class, which contains the annealer. + std::unique_ptr placer_; + + /// @brief A lookup between the block pin indices and pb graph pins. + IntraLbPbPinLookup pb_gpin_lookup_; + + /// @brief A lookup between CLB pins and atom pins. + ClusteredPinAtomPinsLookup netlist_pin_lookup_; +}; diff --git a/vpr/src/analytical_place/flat_placement_bins.h b/vpr/src/analytical_place/flat_placement_bins.h new file mode 100644 index 00000000000..e94ed958312 --- /dev/null +++ b/vpr/src/analytical_place/flat_placement_bins.h @@ -0,0 +1,196 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Flat Placement Bin Abstraction + * + * This file declares a class which can bin AP Blocks spatially throughout the + * FPGA. + */ + +#pragma once + +#include +#include "ap_netlist.h" +#include "vtr_assert.h" +#include "vtr_geometry.h" +#include "vtr_log.h" +#include "vtr_range.h" +#include "vtr_strong_id.h" +#include "vtr_vector.h" +#include "vtr_vector_map.h" + +// The tag for the flat placement bin. +struct flat_placement_bin_tag {}; + +/** + * @brief A unique ID to a flat placement bin. + */ +typedef vtr::StrongId FlatPlacementBinId; + +/** + * @brief A container of bins which hold AP blocks and take up space on the FPGA. + * + * For flat placement, blocks may be placed anywhere on the FPGA grid. This + * placement is continuous; however, in order to compute quantities like density + * and legality, there needs to be a way to bin blocks together spatially. + * + * This class maintains bins which hold AP blocks and take up a rectangular + * amount of space on the FPGA grid. + * + * This class is only a container; it leaves how the FPGA is split into bins to + * higher level classes. + */ +class FlatPlacementBins { + public: + // Iterator for the flat placement bin IDs + typedef typename vtr::vector_map::const_iterator bin_iterator; + + // Range for the flat placement bin IDs + typedef typename vtr::Range bin_range; + + FlatPlacementBins(const APNetlist& ap_netlist) + : block_bin_(ap_netlist.blocks().size(), FlatPlacementBinId::INVALID()) {} + + /** + * @brief Returns a range of all bins that have been created. + */ + bin_range bins() const { + return vtr::make_range(bin_ids_.begin(), bin_ids_.end()); + } + + /** + * @brief Creates a bin which exists in the given bin_region. + * + * @param bin_region + * The rectangular region of the FPGA device that this bin will + * represent. + */ + inline FlatPlacementBinId create_bin(const vtr::Rect& bin_region) { + FlatPlacementBinId new_bin_id = FlatPlacementBinId(bin_ids_.size()); + bin_ids_.push_back(new_bin_id); + bin_region_.push_back(bin_region); + bin_contained_blocks_.resize(bin_contained_blocks_.size() + 1); + return new_bin_id; + } + + /** + * @brief Add the given block to the given bin. + */ + inline void add_block_to_bin(APBlockId blk_id, FlatPlacementBinId bin_id) { + VTR_ASSERT(blk_id.is_valid()); + VTR_ASSERT(bin_id.is_valid()); + VTR_ASSERT(!block_bin_[blk_id].is_valid()); + bin_contained_blocks_[bin_id].insert(blk_id); + block_bin_[blk_id] = bin_id; + } + + /** + * @brief Remove the given block from the given bin. The bin must contain + * this block. + */ + inline void remove_block_from_bin(APBlockId blk_id, FlatPlacementBinId bin_id) { + VTR_ASSERT(blk_id.is_valid()); + VTR_ASSERT(bin_id.is_valid()); + VTR_ASSERT(block_bin_[blk_id] == bin_id); + bin_contained_blocks_[bin_id].erase(blk_id); + block_bin_[blk_id] = FlatPlacementBinId::INVALID(); + } + + /** + * @brief Get the blocks contained within the given bin. + */ + inline const std::unordered_set& bin_contained_blocks(FlatPlacementBinId bin_id) const { + VTR_ASSERT(bin_id.is_valid()); + return bin_contained_blocks_[bin_id]; + } + + /** + * @brief Get the region of the FPGA that the given bin covers. + */ + inline const vtr::Rect& bin_region(FlatPlacementBinId bin_id) const { + VTR_ASSERT(bin_id.is_valid()); + return bin_region_[bin_id]; + } + + /** + * @brief Get the bin that contains the given AP block. + */ + inline FlatPlacementBinId block_bin(APBlockId blk_id) const { + VTR_ASSERT(blk_id.is_valid()); + return block_bin_[blk_id]; + } + + /** + * @brief Remove all of the AP blocks from the given bin. + */ + inline void remove_all_blocks_from_bin(FlatPlacementBinId bin_id) { + VTR_ASSERT(bin_id.is_valid()); + // Invalidate the block bin lookup for the blocks in the bin. + for (APBlockId blk_id : bin_contained_blocks_[bin_id]) { + block_bin_[blk_id] = FlatPlacementBinId::INVALID(); + } + // Remove all of the blocks from the bin. + bin_contained_blocks_[bin_id].clear(); + } + + /** + * @brief Verify the internal members of this class are consistent. + */ + inline bool verify() const { + // Ensure all bin IDs are valid and consistent. + for (FlatPlacementBinId bin_id : bin_ids_) { + if (!bin_id.is_valid()) { + VTR_LOG("Bin Verify: Invalid bin ID in bins.\n"); + return false; + } + if (bin_ids_.count(bin_id) != 1) { + VTR_LOG("Bin Verify: Found a bin ID not in the bin IDs array.\n"); + return false; + } + if (bin_ids_[bin_id] != bin_id) { + VTR_LOG("Bin Verify: Bin ID found which is not consistent.\n"); + return false; + } + } + + // Ensure the data members of this class are all the correct size. + size_t num_bins = bin_ids_.size(); + if (bin_contained_blocks_.size() != num_bins) { + VTR_LOG("Bin Verify: bin_constained_blocks_ not the correct size.\n"); + return false; + } + if (bin_region_.size() != num_bins) { + VTR_LOG("Bin Verify: bin_region_ not the correct size.\n"); + return false; + } + + // Make sure that the bin_contained_blocks_ and the block_bin_ are + // consistent. + for (FlatPlacementBinId bin_id : bin_ids_) { + for (APBlockId blk_id : bin_contained_blocks_[bin_id]) { + if (block_bin_[blk_id] != bin_id) { + VTR_LOG("Bin Verify: Block is contained within a bin but does not agree.\n"); + return false; + } + } + } + + return true; + } + + private: + /// @brief A vector of the Flat Placement Bin IDs. If any of them are invalid, + /// then that means that the bin has been destroyed. + vtr::vector_map bin_ids_; + + /// @brief The contained AP blocks of each bin. + vtr::vector_map> bin_contained_blocks_; + + /// @brief The bin that contains each AP block. + vtr::vector block_bin_; + + /// @brief The region that each bin represents on the FPGA grid. + // TODO: For 3D FPGAs, this should be a 3D rectangle. + vtr::vector_map> bin_region_; +}; diff --git a/vpr/src/analytical_place/flat_placement_density_manager.cpp b/vpr/src/analytical_place/flat_placement_density_manager.cpp new file mode 100644 index 00000000000..f4c37b191c8 --- /dev/null +++ b/vpr/src/analytical_place/flat_placement_density_manager.cpp @@ -0,0 +1,309 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Implementation of the density manager class. + */ + +#include "flat_placement_density_manager.h" +#include +#include "ap_netlist.h" +#include "ap_netlist_fwd.h" +#include "atom_netlist.h" +#include "flat_placement_bins.h" +#include "flat_placement_mass_calculator.h" +#include "partial_placement.h" +#include "physical_types.h" +#include "prepack.h" +#include "vtr_assert.h" +#include "vtr_geometry.h" +#include "vtr_vector.h" +#include "vtr_vector_map.h" + +/** + * @brief Calculates how over-capacity the given utilization vector is. + */ +static PrimitiveVector calc_bin_overfill(const PrimitiveVector& bin_utilization, + const PrimitiveVector& bin_capacity) { + PrimitiveVector overfill = bin_utilization - bin_capacity; + overfill.relu(); + VTR_ASSERT_DEBUG(overfill.is_non_negative()); + return overfill; +} + +/** + * @brief Calculates how under-capacity the given utilization vector is. + */ +static PrimitiveVector calc_bin_underfill(const PrimitiveVector& bin_utilization, + const PrimitiveVector& bin_capacity) { + PrimitiveVector underfill = bin_capacity - bin_utilization; + underfill.relu(); + VTR_ASSERT_DEBUG(underfill.is_non_negative()); + return underfill; +} + +FlatPlacementDensityManager::FlatPlacementDensityManager(const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const DeviceGrid& device_grid, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + int log_verbosity) + : ap_netlist_(ap_netlist) + , bins_(ap_netlist) + , mass_calculator_(ap_netlist, prepacker, atom_netlist, logical_block_types, physical_tile_types, log_verbosity) + , log_verbosity_(log_verbosity) { + // Initialize the bin spatial lookup object. + size_t num_layers, width, height; + std::tie(num_layers, width, height) = device_grid.dim_sizes(); + bin_spatial_lookup_.resize({num_layers, width, height}); + + // Create a bin for each tile. This will create one bin for each root tile + // location. + vtr::vector_map bin_phy_tile_type_idx; + for (size_t layer = 0; layer < num_layers; layer++) { + for (size_t x = 0; x < width; x++) { + for (size_t y = 0; y < height; y++) { + // Only create bins for root tile locations. + auto tile_loc = t_physical_tile_loc(x, y, layer); + int w_offset = device_grid.get_width_offset(tile_loc); + int h_offset = device_grid.get_height_offset(tile_loc); + if (w_offset != 0 || h_offset != 0) { + // If this is not a root tile location, set the spatial bin + // lookup to point to the root tile location's bin. + FlatPlacementBinId root_bin_id = bin_spatial_lookup_[layer][x - w_offset][y - h_offset]; + bin_spatial_lookup_[layer][x][y] = root_bin_id; + continue; + } + + // Create a bin for this tile. + auto tile_type = device_grid.get_physical_type(tile_loc); + int tw = tile_type->width; + int th = tile_type->height; + VTR_ASSERT_SAFE(tw != 0 && th != 0); + vtr::Rect new_bin_region(vtr::Point(x, y), + vtr::Point(x + tw, + y + th)); + FlatPlacementBinId new_bin_id = bins_.create_bin(new_bin_region); + + // Add the bin to the spatial lookup + bin_spatial_lookup_[layer][x][y] = new_bin_id; + + // Store the index of the physical tile type into a map to be + // used to compute the capacity. + bin_phy_tile_type_idx.insert(new_bin_id, tile_type->index); + } + } + } + + // Initialize the bin capacities to the mass capacity of the physical tile + // this bin represents. + bin_capacity_.resize(bins_.bins().size()); + for (FlatPlacementBinId bin_id : bins_.bins()) { + size_t physical_tile_type_index = bin_phy_tile_type_idx[bin_id]; + bin_capacity_[bin_id] = mass_calculator_.get_physical_tile_type_capacity(physical_tile_type_index); + } + + // Initialize the bin utilizations to be zero (there is nothing in the bin + // currently). + bin_utilization_.resize(bins_.bins().size(), PrimitiveVector()); + + // Initialize the bin underfill and overfill. + bin_underfill_.resize(bins_.bins().size()); + bin_overfill_.resize(bins_.bins().size()); + for (FlatPlacementBinId bin_id : bins_.bins()) { + bin_underfill_[bin_id] = calc_bin_underfill(bin_utilization_[bin_id], bin_capacity_[bin_id]); + bin_overfill_[bin_id] = calc_bin_overfill(bin_utilization_[bin_id], bin_capacity_[bin_id]); + } + + // Note: The overfilled_bins_ are left empty. All bins are empty, therefore + // no bin is overfilled. +} + +FlatPlacementBinId FlatPlacementDensityManager::get_bin(double x, double y, double layer) const { + size_t layer_pos = std::floor(layer); + size_t x_pos = std::floor(x); + size_t y_pos = std::floor(y); + VTR_ASSERT(layer_pos < bin_spatial_lookup_.dim_size(0)); + VTR_ASSERT(x_pos < bin_spatial_lookup_.dim_size(1)); + VTR_ASSERT(y_pos < bin_spatial_lookup_.dim_size(2)); + return bin_spatial_lookup_[layer_pos][x][y]; +} + +void FlatPlacementDensityManager::insert_block_into_bin(APBlockId blk_id, + FlatPlacementBinId bin_id) { + VTR_ASSERT(blk_id.is_valid()); + VTR_ASSERT(bin_id.is_valid()); + // Add the block to the bin. + bins_.add_block_to_bin(blk_id, bin_id); + // Update the bin utilization. + bin_utilization_[bin_id] += mass_calculator_.get_block_mass(blk_id); + // Update the bin overfill and underfill + bin_overfill_[bin_id] = calc_bin_overfill(bin_utilization_[bin_id], bin_capacity_[bin_id]); + bin_underfill_[bin_id] = calc_bin_underfill(bin_utilization_[bin_id], bin_capacity_[bin_id]); + // Insert the bin into the overfilled bin set if it is overfilled. + if (bin_is_overfilled(bin_id)) + overfilled_bins_.insert(bin_id); +} + +void FlatPlacementDensityManager::remove_block_from_bin(APBlockId blk_id, + FlatPlacementBinId bin_id) { + VTR_ASSERT(blk_id.is_valid()); + VTR_ASSERT(bin_id.is_valid()); + // Remove the block from the bin. + bins_.remove_block_from_bin(blk_id, bin_id); + // Update the bin utilization. + bin_utilization_[bin_id] -= mass_calculator_.get_block_mass(blk_id); + // Update the bin overfill and underfill. + bin_overfill_[bin_id] = calc_bin_overfill(bin_utilization_[bin_id], bin_capacity_[bin_id]); + bin_underfill_[bin_id] = calc_bin_underfill(bin_utilization_[bin_id], bin_capacity_[bin_id]); + // Remove from overfilled bins set if it is not overfilled. + if (!bin_is_overfilled(bin_id)) + overfilled_bins_.erase(bin_id); +} + +void FlatPlacementDensityManager::import_placement_into_bins(const PartialPlacement& p_placement) { + // Empty the bins such that all blocks are no longer within the bins. + empty_bins(); + + // Insert each block in the netlist into their bin based on their placement. + // TODO: Maybe import the fixed block locations in the constructor and then + // only import the moveable block locations. + for (APBlockId blk_id : ap_netlist_.blocks()) { + FlatPlacementBinId bin_id = get_bin(p_placement.block_x_locs[blk_id], + p_placement.block_y_locs[blk_id], + p_placement.block_layer_nums[blk_id]); + insert_block_into_bin(blk_id, bin_id); + } +} + +vtr::Point FlatPlacementDensityManager::get_block_location_in_bin(APBlockId blk_id, + const vtr::Rect& bin_region, + const PartialPlacement& p_placement) const { + // A block should not be placed on the edges of the region + // of a bin; however they can be infinitely close to these sides. It is + // arbitrary how close to the edge we place the blocks; opted to place them + // as close as possible. + double epsilon = 0.0001; + double x = std::clamp(p_placement.block_x_locs[blk_id], + bin_region.bottom_left().x() + epsilon, + bin_region.top_right().x() - epsilon); + double y = std::clamp(p_placement.block_y_locs[blk_id], + bin_region.bottom_left().y() + epsilon, + bin_region.top_right().y() - epsilon); + return vtr::Point(x, y); +} + +void FlatPlacementDensityManager::export_placement_from_bins(PartialPlacement& p_placement) const { + // Updates the partial placement with the location of the blocks in the bin + // by moving the blocks to the point with the bin closest to where they + // were originally. + for (APBlockId blk_id : ap_netlist_.blocks()) { + // Only the moveable block locations should be exported. + if (ap_netlist_.block_mobility(blk_id) == APBlockMobility::FIXED) + continue; + // Project the coordinate of the block in the partial placement to the + // closest point in the bin. + FlatPlacementBinId blk_bin_id = bins_.block_bin(blk_id); + VTR_ASSERT_DEBUG(blk_bin_id.is_valid()); + vtr::Point new_blk_pos = get_block_location_in_bin(blk_id, + bins_.bin_region(blk_bin_id), + p_placement); + p_placement.block_x_locs[blk_id] = new_blk_pos.x(); + p_placement.block_y_locs[blk_id] = new_blk_pos.y(); + // NOTE: This code currently does not support 3D FPGAs. + VTR_ASSERT(std::floor(p_placement.block_layer_nums[blk_id]) == 0.0); + } +} + +void FlatPlacementDensityManager::empty_bins() { + // Reset all of the bins and their utilizations. + for (FlatPlacementBinId bin_id : bins_.bins()) { + bins_.remove_all_blocks_from_bin(bin_id); + bin_utilization_[bin_id].clear(); + bin_overfill_[bin_id].clear(); + bin_underfill_[bin_id] = bin_capacity_[bin_id]; + } + // Once all the bins are reset, all bins should be empty; therefore no bins + // are overfilled. + overfilled_bins_.clear(); +} + +bool FlatPlacementDensityManager::verify() const { + // Verify the bins for consistency. + if (!bins_.verify()) { + VTR_LOG("Bins failed to verify.\n"); + return false; + } + // Make sure that every block has a bin. + for (APBlockId blk_id : ap_netlist_.blocks()) { + if (!bins_.block_bin(blk_id).is_valid()) { + VTR_LOG("Bin Verify: Found a block that is not in a bin.\n"); + return false; + } + } + // Make sure that every bin has the correct utilization, supply, and demand. + for (FlatPlacementBinId bin_id : bins_.bins()) { + PrimitiveVector calc_utilization; + for (APBlockId blk_id : bins_.bin_contained_blocks(bin_id)) { + calc_utilization += mass_calculator_.get_block_mass(blk_id); + } + if (bin_utilization_[bin_id] != calc_utilization) { + VTR_LOG("Bin Verify: Found a bin with incorrect utilization.\n"); + return false; + } + PrimitiveVector calc_overfill = bin_utilization_[bin_id] - bin_capacity_[bin_id]; + calc_overfill.relu(); + if (bin_overfill_[bin_id] != calc_overfill) { + VTR_LOG("Bin Verify: Found a bin with incorrect overfill.\n"); + return false; + } + PrimitiveVector calc_underfill = bin_capacity_[bin_id] - bin_utilization_[bin_id]; + calc_underfill.relu(); + if (bin_underfill_[bin_id] != calc_underfill) { + VTR_LOG("Bin Verify: Found a bin with incorrect underfill.\n"); + return false; + } + if (!bin_overfill_[bin_id].is_non_negative()) { + VTR_LOG("Bin Verify: Found a bin with a negative overfill.\n"); + return false; + } + if (!bin_underfill_[bin_id].is_non_negative()) { + VTR_LOG("Bin Verify: Found a bin with a negative underfill.\n"); + return false; + } + if (!bin_capacity_[bin_id].is_non_negative()) { + VTR_LOG("Bin Verify: Found a bin with a negative capacity.\n"); + return false; + } + if (!bin_utilization_[bin_id].is_non_negative()) { + VTR_LOG("Bin Verify: Found a bin with a negative utilization.\n"); + return false; + } + } + // Make sure all overfilled bins are actually overfilled. + // TODO: Need to make sure that all non-overfilled bins are actually not + // overfilled. + for (FlatPlacementBinId bin_id : overfilled_bins_) { + if (bin_overfill_[bin_id].is_zero()) { + VTR_LOG("Bin Verify: Found an overfilled bin that was not overfilled.\n"); + return false; + } + } + // If all above passed, then the bins are valid. + return true; +} + +void FlatPlacementDensityManager::print_bin_grid() const { + size_t width = bin_spatial_lookup_.dim_size(1); + size_t height = bin_spatial_lookup_.dim_size(2); + for (size_t y = 0; y < height; y++) { + for (size_t x = 0; x < width; x++) { + FlatPlacementBinId bin_id = get_bin(x, y, 0.0); + VTR_LOG("%3zu ", + bins_.bin_contained_blocks(bin_id).size()); + } + VTR_LOG("\n"); + } + VTR_LOG("\n"); +} diff --git a/vpr/src/analytical_place/flat_placement_density_manager.h b/vpr/src/analytical_place/flat_placement_density_manager.h new file mode 100644 index 00000000000..ad3977589c1 --- /dev/null +++ b/vpr/src/analytical_place/flat_placement_density_manager.h @@ -0,0 +1,273 @@ +/** + * @file + * @author Alex Singer + * @date February 2024 + * @brief Manager class for how density is calculated in the AP flow. + * + * This class decides how the FPGA grid is partitioned into bins and what + * defines a bin that is "overfilled". + */ + +#pragma once + +#include +#include +#include +#include "flat_placement_bins.h" +#include "flat_placement_mass_calculator.h" +#include "vtr_assert.h" +#include "vtr_ndmatrix.h" +#include "vtr_vector.h" + +class APNetlist; +class AtomNetlist; +class DeviceGrid; +class Prepacker; +struct PartialPlacement; +struct t_logical_block_type; +struct t_physical_tile_type; + +/** + * @brief Manager class for computing the density of a flat placement. + * + * Density is a function of mass and volume. Since a flat placement is a + * continuous placement of discrete objects, the space the objects are placed + * over needs to be partitioned into discrete bins. Regions that are too dense + * are called overfilled bins and regions that may hold more (not too dense) + * are called underfilled bins. This class manages the construction of these + * bins and how overfilled / underfilled they are. + * + * Currently, a bin is created for each tile in the FPGA grid (with a unique + * root tile location). For example, a CLB taking up a single tile would be a + * 1x1 bin, while a DSP block taking up multiple tiles may be a 4x1 bin. The + * capacity of each bin is the capacity of the tile it represents (as computed + * by the flat placement mass calculator). When AP blocks are added / removed + * from bins, this class will maintain the current utilization of the bin. Since + * these masses / capacities are repesented by M-dimensional quantities (where + * M is the number of models in the architecture), the overfill and underfill of + * each bin is given as an M-dimensional vector. For example, in an architecture + * of only LUTs and FFs, an overfill of <3, 1> means that a bin has 3 too many + * LUTs and 1 too many FFs. + * + * This class is able to answer questions about the current density of the flat + * placement such as which bins are currently overfilled, what bin is at the + * given location, etc. + * + * TODO: Add an option to this class to change the granularity of the bins. This + * may allow us to trade off quality and runtime. + */ +class FlatPlacementDensityManager { + public: + /** + * @brief Construct the density manager. + * + * @param ap_netlist + * @param prepacker + * @param atom_netlist + * @param device_grid + * @param logical_block_types + * @param physical_tile_types + * @param log_verbosity + */ + FlatPlacementDensityManager(const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const DeviceGrid& device_grid, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + int log_verbosity); + + /** + * @brief Returns a reference to the bins the manager has created. + */ + inline const FlatPlacementBins& flat_placement_bins() const { + return bins_; + } + + /** + * @brief Returns a reference to the mass calculator that the manager class + * is using to detect overfilled / undefilled bins. + */ + inline const FlatPlacementMassCalculator& mass_calculator() const { + return mass_calculator_; + } + + /** + * @brief Returns the bin located at the given (x, y, layer) position. + */ + FlatPlacementBinId get_bin(double x, double y, double layer) const; + + /** + * @brief Returns the size of the placeable region, i.e. the region that + * contains all bins. + */ + inline std::tuple get_overall_placeable_region_size() const { + return std::make_tuple(bin_spatial_lookup_.dim_size(1), // width + bin_spatial_lookup_.dim_size(2), // height + bin_spatial_lookup_.dim_size(0)); // depth + } + + /** + * @brief Insert the given block into the given bin. + * + * As well as updating the bin's contents, also maintains the utilization + * of the bins. + */ + void insert_block_into_bin(APBlockId blk_id, FlatPlacementBinId bin_id); + + /** + * @brief Remove the given block from the given bin. + * + * Like insertion, this maintains the utilization of bins. + */ + void remove_block_from_bin(APBlockId blk_id, FlatPlacementBinId bin_id); + + /** + * @brief Returns the current utilization of the given bin. + * + * This is the sum of the mass of each atoms in the given bin. + */ + inline const PrimitiveVector& get_bin_utilization(FlatPlacementBinId bin_id) const { + VTR_ASSERT(bin_id.is_valid()); + return bin_utilization_[bin_id]; + } + + /** + * @brief Returns the capacity of the given bin. + * + * This is an approximation of the amount of mass that the tile that this + * bin represents can hold. + */ + inline const PrimitiveVector& get_bin_capacity(FlatPlacementBinId bin_id) const { + VTR_ASSERT(bin_id.is_valid()); + return bin_capacity_[bin_id]; + } + + /** + * @brief Returns how overfilled the given bin is. + * + * This cannot be negative. This is how much over the capacity the current + * utilization is. An overfill of 0 implies that the bin is not overfilled. + */ + inline const PrimitiveVector& get_bin_overfill(FlatPlacementBinId bin_id) const { + VTR_ASSERT(bin_id.is_valid()); + return bin_overfill_[bin_id]; + } + + /** + * @brief Returns how underfilled the given bin is. + * + * This cannot be negative. This is how much more mass the given bin can + * hold without going over capactiy. + */ + inline const PrimitiveVector& get_bin_underfill(FlatPlacementBinId bin_id) const { + VTR_ASSERT(bin_id.is_valid()); + return bin_underfill_[bin_id]; + } + + /** + * @brief Returns true of the given bin is overfilled (it contains too much + * mass and is over capacity). + */ + inline bool bin_is_overfilled(FlatPlacementBinId bin_id) const { + // A bin is overfilled if the overfill is non-zero. + return get_bin_overfill(bin_id).is_non_zero(); + } + + /** + * @brief Returns a list of all overfilled bins. + */ + inline const std::unordered_set& get_overfilled_bins() const { + return overfilled_bins_; + } + + /** + * @brief Import the given flat placement into the bins. + * + * This will place AP blocks into the bins that they are placed over. + * + * This will reset the bins before importing the placement. Anything inside + * the bins will be removed. + */ + void import_placement_into_bins(const PartialPlacement& p_placement); + + /** + * @brief Exports the placement of blocks in bins to a flat placement. + * + * This will move each block to the position closest to the original flat + * placement that is still within the bin the block was placed into. + */ + void export_placement_from_bins(PartialPlacement& p_placement) const; + + /** + * @brief Gets the position of the AP block within the bin it contains. + * + * This will return the position of the block that is closest to the position + * in the given flat placement, while still being within the the bin region. + * + * For example, if the block is located within the bin, its position will + * be returned (unmodified). If the block is located to the left of the bin + * (y coordinate is within the bounds of the bin), then this will return + * the point on the left edge of the bin with the same y coordinate as the + * block. + * + * TODO: It may be a good idea to investigate placing blocks at the input + * or output pin locations of the bin. + */ + vtr::Point get_block_location_in_bin(APBlockId blk_id, + const vtr::Rect& bin_region, + const PartialPlacement& p_placement) const; + + /** + * @brief Resets all bins by emptying them. + */ + void empty_bins(); + + /** + * @brief Verifies that the bins were constructed correctly and that the + * utilization, overfill, underfill, and capacity are all correct. + * Returns false if there are any issues. + */ + bool verify() const; + + /** + * @brief Debug printer which prints a simple representation of the bins + * and their capacity to the log file. + */ + void print_bin_grid() const; + + private: + /// @brief The AP netlist of blocks which are filling the bins. + const APNetlist& ap_netlist_; + + /// @brief The bins created by this class. + FlatPlacementBins bins_; + + /// @brief The mass calculator used to compute the mass of the blocks and + /// physical tiles. + FlatPlacementMassCalculator mass_calculator_; + + /// @brief Spatial lookup for an (layer, x, y) position to the bin at that + /// location. + /// + /// Access: [0..grid.num_layers-1][0..grid.width-1][0..grid.height-1] + vtr::NdMatrix bin_spatial_lookup_; + + /// @brief The capacity of each bin. + vtr::vector bin_capacity_; + + /// @brief The utilization of each bin. + vtr::vector bin_utilization_; + + /// @brief The overfill of each bin. + vtr::vector bin_overfill_; + + /// @brief The underfill of each bin. + vtr::vector bin_underfill_; + + /// @brief The set of overfilled bins. + std::unordered_set overfilled_bins_; + + /// @brief The verbosity of log messages in this class. + const int log_verbosity_; +}; diff --git a/vpr/src/analytical_place/flat_placement_mass_calculator.cpp b/vpr/src/analytical_place/flat_placement_mass_calculator.cpp new file mode 100644 index 00000000000..c99aaf29339 --- /dev/null +++ b/vpr/src/analytical_place/flat_placement_mass_calculator.cpp @@ -0,0 +1,278 @@ +/** + * @file + * @author Alex Singer + * @date February 2024 + * @brief Implementation of the mass calculator used in the AP flow. + */ + +#include "flat_placement_mass_calculator.h" +#include +#include "ap_netlist.h" +#include "atom_netlist.h" +#include "globals.h" +#include "logic_types.h" +#include "physical_types.h" +#include "prepack.h" +#include "primitive_vector.h" +#include "vtr_log.h" + +/** + * @brief Get the scalar mass of the given model (primitive type). + * + * A model with a higher mass will take up more space in its bin which may force + * more spreading of that type of primitive. + * + * TODO: This will be made more complicated later. Models may be weighted based + * on some factors. + */ +static float get_model_mass(const t_model* model) { + // Currently, all models have a mass of one. + (void)model; + return 1.f; +} + +// This method is being forward-declared due to the double recursion below. +// Eventually this should be made into a non-recursive algorithm for performance, +// however this is not in a performance critical part of the code. +static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type); + +/** + * @brief Get the amount of primitives this mode can contain. + * + * This is part of a double recursion, since a mode contains primitives which + * themselves have modes. + */ +static PrimitiveVector calc_mode_capacity(const t_mode& mode) { + // Accumulate the capacities of all the pbs in this mode. + PrimitiveVector capacity; + for (int pb_child_idx = 0; pb_child_idx < mode.num_pb_type_children; pb_child_idx++) { + const t_pb_type& pb_type = mode.pb_type_children[pb_child_idx]; + PrimitiveVector pb_capacity = calc_pb_type_capacity(&pb_type); + // A mode may contain multiple pbs of the same type, multiply the + // capacity. + pb_capacity *= pb_type.num_pb; + capacity += pb_capacity; + } + return capacity; +} + +/** + * @brief Get the amount of primitives this pb can contain. + * + * This is the other part of the double recursion. A pb may have multiple modes. + * Modes are made of pbs. + */ +static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type) { + // Since a pb cannot be multiple modes at the same time, we do not + // accumulate the capacities of the mode. Instead we need to "mix" the two + // capacities as if the pb could choose either one. + PrimitiveVector capacity; + // If this is a leaf / primitive, create the base PrimitiveVector capacity. + if (pb_type->num_modes == 0) { + const t_model* model = pb_type->model; + VTR_ASSERT(model != nullptr); + VTR_ASSERT_DEBUG(model->index >= 0); + capacity.add_val_to_dim(get_model_mass(model), model->index); + return capacity; + } + // For now, we simply mix the capacities of modes by taking the max of each + // dimension of the capcities. This provides an upper-bound on the amount of + // primitives this pb can contain. + for (int mode = 0; mode < pb_type->num_modes; mode++) { + PrimitiveVector mode_capacity = calc_mode_capacity(pb_type->modes[mode]); + capacity = PrimitiveVector::max(capacity, mode_capacity); + } + return capacity; +} + +/** + * @brief Calculate the cpacity of the given logical block type. + */ +static PrimitiveVector calc_logical_block_type_capacity(const t_logical_block_type& logical_block_type) { + // If this logical block is empty, it cannot contain any primitives. + if (logical_block_type.is_empty()) + return PrimitiveVector(); + // The primitive capacity of a logical block is the primitive capacity of + // its root pb. + return calc_pb_type_capacity(logical_block_type.pb_type); +} + +/** + * @brief Get the primitive capacity of the given sub_tile. + * + * Sub_tiles may reuse logical blocks between one another, therefore this method + * requires that the capacities of all of the logical blocks have been + * pre-calculated and stored in the given vector. + * + * @param sub_tile The sub_tile to get the capacity of. + * @param logical_block_type_capacities The capacities of all logical block + * types. + */ +static PrimitiveVector calc_sub_tile_capacity(const t_sub_tile& sub_tile, + const std::vector& logical_block_type_capacities) { + // Similar to getting the primitive capacity of the pb, sub_tiles have many + // equivalent sites, but it can only be one of them at a time. Need to "mix" + // the capacities of the different sites this sub_tile may be. + PrimitiveVector capacity; + for (t_logical_block_type_ptr block_type : sub_tile.equivalent_sites) { + const PrimitiveVector& block_capacity = logical_block_type_capacities[block_type->index]; + // Currently, we take the max of each primitive dimension as an upper + // bound on the capacity of the sub_tile. + capacity = PrimitiveVector::max(capacity, block_capacity); + } + return capacity; +} + +/** + * @brief Get the primitive capacity of a tile of the given type. + * + * Tiles may reuse logical blocks between one another, therefore this method + * requires that the capacities of all of the logical blocks have been + * pre-calculated and stored in the given vector. + * + * @param tile_type The tile type to get the capacity of. + * @param logical_block_type_capacities The capacities of all logical block + * types. + */ +static PrimitiveVector calc_physical_tile_type_capacity(const t_physical_tile_type& tile_type, + const std::vector& logical_block_type_capacities) { + // Accumulate the capacities of all the sub_tiles in the given tile type. + PrimitiveVector capacity; + for (const t_sub_tile& sub_tile : tile_type.sub_tiles) { + PrimitiveVector sub_tile_capacity = calc_sub_tile_capacity(sub_tile, logical_block_type_capacities); + // A tile may contain many sub_tiles of the same type. Multiply by the + // number of sub_tiles of this type. + sub_tile_capacity *= sub_tile.capacity.total(); + capacity += sub_tile_capacity; + } + return capacity; +} + +/** + * @brief Get the primitive mass of the given block. + * + * This returns an M-dimensional vector with each entry indicating the mass of + * that primitive type in this block. M is the number of unique models + * (primitive types) in the architecture. + */ +static PrimitiveVector calc_block_mass(APBlockId blk_id, + const APNetlist& netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist) { + PrimitiveVector mass; + PackMoleculeId mol_id = netlist.block_molecule(blk_id); + const t_pack_molecule& mol = prepacker.get_molecule(mol_id); + for (AtomBlockId atom_blk_id : mol.atom_block_ids) { + // See issue #2791, some of the atom_block_ids may be invalid. They can + // safely be ignored. + if (!atom_blk_id.is_valid()) + continue; + const t_model* model = atom_netlist.block_model(atom_blk_id); + VTR_ASSERT_DEBUG(model->index >= 0); + mass.add_val_to_dim(get_model_mass(model), model->index); + } + return mass; +} + +/** + * @brief Debug printing method to print the capacities of all logical blocks + * and physical tile types. + */ +static void print_capacities(const std::vector& logical_block_type_capacities, + const std::vector& physical_tile_type_capacities, + const std::vector& logical_block_types, + const std::vector& physical_tile_types) { + // Get a linear list of all models. + // TODO: I do not like using the global context here, but these models + // should be stable in VTR. If they were stored better, we may be + // able to pass them in. + std::vector all_models; + t_model* curr_model = g_vpr_ctx.device().arch->models; + while (curr_model != nullptr) { + if (curr_model->index >= (int)all_models.size()) + all_models.resize(curr_model->index + 1); + all_models[curr_model->index] = curr_model; + curr_model = curr_model->next; + } + curr_model = g_vpr_ctx.device().arch->model_library; + while (curr_model != nullptr) { + if (curr_model->index >= (int)all_models.size()) + all_models.resize(curr_model->index + 1); + all_models[curr_model->index] = curr_model; + curr_model = curr_model->next; + } + // Print the capacities. + VTR_LOG("Logical Block Type Capacities:\n"); + VTR_LOG("------------------------------\n"); + VTR_LOG("name\t"); + for (t_model* model : all_models) { + VTR_LOG("%s\t", model->name); + } + VTR_LOG("\n"); + for (const t_logical_block_type& block_type : logical_block_types) { + const PrimitiveVector& capacity = logical_block_type_capacities[block_type.index]; + VTR_LOG("%s\t", block_type.name.c_str()); + for (t_model* model : all_models) { + VTR_LOG("%.2f\t", capacity.get_dim_val(model->index)); + } + VTR_LOG("\n"); + } + VTR_LOG("\n"); + VTR_LOG("Physical Tile Type Capacities:\n"); + VTR_LOG("------------------------------\n"); + VTR_LOG("name\t"); + for (t_model* model : all_models) { + VTR_LOG("%s\t", model->name); + } + VTR_LOG("\n"); + for (const t_physical_tile_type& tile_type : physical_tile_types) { + const PrimitiveVector& capacity = physical_tile_type_capacities[tile_type.index]; + VTR_LOG("%s\t", tile_type.name.c_str()); + for (t_model* model : all_models) { + VTR_LOG("%.2f\t", capacity.get_dim_val(model->index)); + } + VTR_LOG("\n"); + } + VTR_LOG("\n"); + // TODO: Print the masses of each model. +} + +FlatPlacementMassCalculator::FlatPlacementMassCalculator(const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + int log_verbosity) + : physical_tile_type_capacity_(physical_tile_types.size()) + , logical_block_type_capacity_(logical_block_types.size()) + , block_mass_(ap_netlist.blocks().size()) + , log_verbosity_(log_verbosity) { + + // Precompute the capacity of each logical block type. + for (const t_logical_block_type& logical_block_type : logical_block_types) { + logical_block_type_capacity_[logical_block_type.index] = calc_logical_block_type_capacity(logical_block_type); + } + + // Precompute the capacity of each physical tile type. + for (const t_physical_tile_type& physical_tile_type : physical_tile_types) { + physical_tile_type_capacity_[physical_tile_type.index] = calc_physical_tile_type_capacity(physical_tile_type, logical_block_type_capacity_); + } + + // Precompute the mass of each block in the APNetlist + VTR_LOGV(log_verbosity_ >= 10, "Pre-computing the block masses...\n"); + for (APBlockId ap_block_id : ap_netlist.blocks()) { + block_mass_[ap_block_id] = calc_block_mass(ap_block_id, + ap_netlist, + prepacker, + atom_netlist); + } + VTR_LOGV(log_verbosity_ >= 10, "Finished pre-computing the block masses.\n"); + + // Print the precomputed block capacities. This can be helpful for debugging. + if (log_verbosity_ > 1) { + print_capacities(logical_block_type_capacity_, + physical_tile_type_capacity_, + logical_block_types, + physical_tile_types); + } +} diff --git a/vpr/src/analytical_place/flat_placement_mass_calculator.h b/vpr/src/analytical_place/flat_placement_mass_calculator.h new file mode 100644 index 00000000000..286b91dd743 --- /dev/null +++ b/vpr/src/analytical_place/flat_placement_mass_calculator.h @@ -0,0 +1,114 @@ +/** + * @file + * @author Alex Singer + * @date February 2024 + * @brief Mass calculation for AP blocks and logical/physical block/tile types + */ + +#pragma once + +#include +#include "ap_netlist_fwd.h" +#include "primitive_vector.h" +#include "vtr_assert.h" +#include "vtr_vector.h" + +class AtomNetlist; +class Prepacker; +struct t_logical_block_type; +struct t_physical_tile_type; + +/** + * @brief A calculator class which computes the M-dimensional mass of AP blocks + * and the capacity of tiles. + * + * Each atom in the Atom Netlist represents some model which may be implemented + * on the FPGA. The FPGA architecture has M models. Since an AP block may + * represent multiple atoms, its "mass" (the amount of "space" this block takes + * up) must be M-dimensional. For example, a LUT+FF molecule would have a mass + * of <1, 1> if LUTs and FFs were the only models in the architecture; while a + * single LUT would have a mass of <1, 0>. + * + * This class handles how the mass of the AP blocks are calculated. + * + * This class also handles how much capacity each tile in the FGPA has. This + * capacity is an approximation of how much M-dimensional mass that the tile + * can hold. Since tiles may have multiple modes, the actual capacity of the + * tiles change depending on what is in the tile. This class simplifies this + * to assume that the capacity does not change and approximates the theoretical + * mass that the tile should aim to hold. + */ +class FlatPlacementMassCalculator { + public: + /** + * @brief Construct the mass calculator. + * + * @param ap_netlist + * The netlist of AP blocks to compute the mass of. The mass of each + * block is precomputed in the constructor and loaded cheaply later. + * @param prepacker + * The prepacker used to pack atoms into the molecules. The AP netlist + * contains molecules; this class is needed to get information on these + * molecules. + * @param atom_netlist + * The netlist of atoms for the circuit. + * @param logical_block_types + * A list of all logical block types that can be implemented in the + * device. The capacity of each logical block type is precomputed to + * help compute the capacity of physical_tile_types. + * @param physical_tile_types + * A list of all physical_tile_types that exist on the FGPA. The + * capacity of each physical tile is precomputed in the constructor to + * be loaded cheaply later. + * @param log_verbosity + * The verbosity of log messages in the mass calculator. + */ + FlatPlacementMassCalculator(const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + int log_verbosity); + + /** + * @brief Get the M-dimensional capacity of the given physical tile type. + * + * This is an approximation based on the description of the tile in the + * architecture. + */ + inline const PrimitiveVector& get_physical_tile_type_capacity(size_t physical_tile_type_index) const { + VTR_ASSERT(physical_tile_type_index < physical_tile_type_capacity_.size()); + return physical_tile_type_capacity_[physical_tile_type_index]; + } + + /** + * @brief Get the M-dimensional capacity of the given logical block type. + */ + inline const PrimitiveVector& get_logical_block_type_capacity(size_t logical_block_type_index) const { + VTR_ASSERT(logical_block_type_index < logical_block_type_capacity_.size()); + return logical_block_type_capacity_[logical_block_type_index]; + } + + /** + * @brief Get the M-dimensional mass of the given AP block. + */ + inline const PrimitiveVector& get_block_mass(APBlockId blk_id) const { + VTR_ASSERT(blk_id.is_valid()); + return block_mass_[blk_id]; + } + + private: + /// @brief The capacity of each physical tile type, indexed by the index + /// of the physical_tile_type. + std::vector physical_tile_type_capacity_; + + /// @brief The capacity of each logical block type, indexed by the index + /// of the logical block type. + std::vector logical_block_type_capacity_; + + /// @brief The mass of each block in the AP netlist. + vtr::vector block_mass_; + + /// @brief The verbosity of log messages in the mass calculator. + const int log_verbosity_; +}; diff --git a/vpr/src/analytical_place/full_legalizer.cpp b/vpr/src/analytical_place/full_legalizer.cpp index e0850479118..767ac67e3d9 100644 --- a/vpr/src/analytical_place/full_legalizer.cpp +++ b/vpr/src/analytical_place/full_legalizer.cpp @@ -9,25 +9,38 @@ #include "full_legalizer.h" +#include #include +#include +#include #include #include -#include "partial_placement.h" +#include "PreClusterTimingManager.h" #include "ShowSetup.h" +#include "ap_flow_enums.h" #include "ap_netlist_fwd.h" +#include "blk_loc_registry.h" #include "check_netlist.h" #include "cluster_legalizer.h" #include "cluster_util.h" #include "clustered_netlist.h" +#include "device_grid.h" +#include "flat_placement_types.h" #include "globals.h" #include "initial_placement.h" +#include "load_flat_place.h" #include "logic_types.h" +#include "noc_place_utils.h" #include "pack.h" +#include "partial_placement.h" #include "physical_types.h" +#include "place.h" #include "place_and_route.h" #include "place_constraints.h" #include "place_macro.h" +#include "prepack.h" +#include "read_place.h" #include "verify_clustering.h" #include "verify_placement.h" #include "vpr_api.h" @@ -37,10 +50,47 @@ #include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_ndmatrix.h" +#include "vtr_random.h" #include "vtr_strong_id.h" #include "vtr_time.h" #include "vtr_vector.h" +std::unique_ptr make_full_legalizer(e_ap_full_legalizer full_legalizer_type, + const APNetlist& ap_netlist, + const AtomNetlist& atom_netlist, + const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, + const t_vpr_setup& vpr_setup, + const t_arch& arch, + const DeviceGrid& device_grid) { + switch (full_legalizer_type) { + case e_ap_full_legalizer::Naive: + return std::make_unique(ap_netlist, + atom_netlist, + prepacker, + pre_cluster_timing_manager, + vpr_setup, + arch, + device_grid); + case e_ap_full_legalizer::APPack: + return std::make_unique(ap_netlist, + atom_netlist, + prepacker, + pre_cluster_timing_manager, + vpr_setup, + arch, + device_grid); + case e_ap_full_legalizer::Basic_Min_Disturbance: + VTR_LOG("Basic Minimum Disturbance Full Legalizer selected!\n"); + VPR_FATAL_ERROR(VPR_ERROR_AP, + "Basic Min. Disturbance Full Legalizer has not been implemented yet."); + + default: + VPR_FATAL_ERROR(VPR_ERROR_AP, + "Unrecognized full legalizer type"); + } +} + namespace { /// @brief A unique ID for each root tile on the device. @@ -60,17 +110,16 @@ typedef vtr::StrongId DeviceTileId; * unify the two flows and make it more stable! */ class APClusterPlacer { -private: + private: // Get the macro for the given cluster block. t_pl_macro get_macro(ClusterBlockId clb_blk_id) { - const auto& place_macros = g_vpr_ctx.placement().blk_loc_registry().place_macros(); // Basically stolen from initial_placement.cpp:place_one_block // TODO: Make this a cleaner interface and share the code. - int imacro = place_macros.get_imacro_from_iblk(clb_blk_id); + int imacro = place_macros_.get_imacro_from_iblk(clb_blk_id); // If this block is part of a macro, return it. if (imacro != -1) { - return place_macros[imacro]; + return place_macros_[imacro]; } // If not, create a "fake" macro with a single element. t_pl_macro_member macro_member; @@ -83,39 +132,34 @@ class APClusterPlacer { return pl_macro; } -public: + const PlaceMacros& place_macros_; + + public: /** * @brief Constructor for the APClusterPlacer * * Initializes internal and global state necessary to place clusters on the * FPGA device. */ - APClusterPlacer() { - // FIXME: This was stolen from place/place.cpp - // it used a static method, just taking what I think I will need. + APClusterPlacer(const PlaceMacros& place_macros, + const char* constraints_file) + : place_macros_(place_macros) { + // Initialize the block loc registry. auto& blk_loc_registry = g_vpr_ctx.mutable_placement().mutable_blk_loc_registry(); - const auto& directs = g_vpr_ctx.device().arch->directs; - - init_placement_context(blk_loc_registry, directs); - - // stolen from place/place.cpp:alloc_and_load_try_swap_structs - // FIXME: set cube_bb to false by hand, should be passed in. - g_vpr_ctx.mutable_placement().cube_bb = false; - g_vpr_ctx.mutable_placement().compressed_block_grids = create_compressed_block_grids(); - - // TODO: The next few steps will be basically a direct copy of the initial - // placement code since it does everything we need! It would be nice - // to share the code. - - // Clear the grid locations (stolen from initial_placement) - blk_loc_registry.clear_all_grid_locs(); - - // Deal with the placement constraints. - propagate_place_constraints(blk_loc_registry.place_macros()); + blk_loc_registry.init(); + // Place the fixed blocks and mark them as fixed. mark_fixed_blocks(blk_loc_registry); - alloc_and_load_compressed_cluster_constraints(); + // Read the constraint file and place fixed blocks. + if (strlen(constraints_file) != 0) { + read_constraints(constraints_file, blk_loc_registry); + } + + // Update the block loc registry with the fixed / moveable blocks. + // We can do this here since the fixed blocks will not change beyond + // this point. + blk_loc_registry.alloc_and_load_movable_blocks(); } /** @@ -202,7 +246,8 @@ class APClusterPlacer { * @param primitive_candidate_block_types A list of candidate block types for * the given molecule. */ -static LegalizationClusterId create_new_cluster(t_pack_molecule* seed_molecule, +static LegalizationClusterId create_new_cluster(PackMoleculeId seed_molecule_id, + const Prepacker& prepacker, ClusterLegalizer& cluster_legalizer, const std::map>& primitive_candidate_block_types) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); @@ -212,8 +257,10 @@ static LegalizationClusterId create_new_cluster(t_pack_molecule* seed_molecule, // placed into. // TODO: The original implementation sorted based on balance. Perhaps this // should do the same. - AtomBlockId root_atom = seed_molecule->atom_block_ids[seed_molecule->root]; - const t_model* root_model = atom_ctx.nlist.block_model(root_atom); + VTR_ASSERT(seed_molecule_id.is_valid()); + const t_pack_molecule& seed_molecule = prepacker.get_molecule(seed_molecule_id); + AtomBlockId root_atom = seed_molecule.atom_block_ids[seed_molecule.root]; + const t_model* root_model = atom_ctx.netlist().block_model(root_atom); auto itr = primitive_candidate_block_types.find(root_model); VTR_ASSERT(itr != primitive_candidate_block_types.end()); @@ -224,7 +271,7 @@ static LegalizationClusterId create_new_cluster(t_pack_molecule* seed_molecule, for (int mode = 0; mode < num_modes; mode++) { e_block_pack_status pack_status = e_block_pack_status::BLK_STATUS_UNDEFINED; LegalizationClusterId new_cluster_id; - std::tie(pack_status, new_cluster_id) = cluster_legalizer.start_new_cluster(seed_molecule, type, mode); + std::tie(pack_status, new_cluster_id) = cluster_legalizer.start_new_cluster(seed_molecule_id, type, mode); if (pack_status == e_block_pack_status::BLK_PASSED) return new_cluster_id; } @@ -235,24 +282,20 @@ static LegalizationClusterId create_new_cluster(t_pack_molecule* seed_molecule, return LegalizationClusterId(); } -void FullLegalizer::create_clusters(const PartialPlacement& p_placement) { +void NaiveFullLegalizer::create_clusters(const PartialPlacement& p_placement) { // PACKING: // Initialize the cluster legalizer (Packing) // FIXME: The legalization strategy is currently set to full. Should handle // this better to make it faster. - t_pack_high_fanout_thresholds high_fanout_thresholds(packer_opts_.high_fanout_threshold); + t_pack_high_fanout_thresholds high_fanout_thresholds(vpr_setup_.PackerOpts.high_fanout_threshold); ClusterLegalizer cluster_legalizer(atom_netlist_, prepacker_, - logical_block_types_, - lb_type_rr_graphs_, - user_models_, - library_models_, - packer_opts_.target_external_pin_util, + vpr_setup_.PackerRRGraph, + vpr_setup_.PackerOpts.target_external_pin_util, high_fanout_thresholds, ClusterLegalizationStrategy::FULL, - packer_opts_.enable_pin_feasibility_filter, - packer_opts_.feasible_block_array_size, - packer_opts_.pack_verbosity); + vpr_setup_.PackerOpts.enable_pin_feasibility_filter, + vpr_setup_.PackerOpts.pack_verbosity); // Create clusters for each tile. // Start by giving each root tile a unique ID. size_t grid_width = device_grid_.width(); @@ -290,33 +333,29 @@ void FullLegalizer::create_clusters(const PartialPlacement& p_placement) { for (size_t tile_id_idx = 0; tile_id_idx < num_device_tiles; tile_id_idx++) { DeviceTileId tile_id = DeviceTileId(tile_id_idx); // Create the molecule list - std::list mol_list; + std::list mol_list; for (APBlockId ap_blk_id : blocks_in_tiles[tile_id]) { - // FIXME: The netlist stores a const pointer to mol; but the cluster - // legalizer does not accept this. Need to fix one or the other. - // For now, using const_cast. - t_pack_molecule* mol = const_cast(ap_netlist_.block_molecule(ap_blk_id)); - mol_list.push_back(mol); + mol_list.push_back(ap_netlist_.block_molecule(ap_blk_id)); } // Clustering algorithm: Create clusters one at a time. while (!mol_list.empty()) { // Arbitrarily choose the first molecule as a seed molecule. - t_pack_molecule* seed_mol = mol_list.front(); + PackMoleculeId seed_mol_id = mol_list.front(); mol_list.pop_front(); // Use the seed molecule to create a cluster for this tile. - LegalizationClusterId new_cluster_id = create_new_cluster(seed_mol, cluster_legalizer, primitive_candidate_block_types); + LegalizationClusterId new_cluster_id = create_new_cluster(seed_mol_id, prepacker_, cluster_legalizer, primitive_candidate_block_types); // Insert all molecules that you can into the cluster. // NOTE: If the mol_list was somehow sorted, we can just stop at // first failure! auto it = mol_list.begin(); while (it != mol_list.end()) { - t_pack_molecule* mol = *it; - if (!cluster_legalizer.is_molecule_compatible(mol, new_cluster_id)) { + PackMoleculeId mol_id = *it; + if (!cluster_legalizer.is_molecule_compatible(mol_id, new_cluster_id)) { ++it; continue; } // Try to insert it. If successful, remove from list. - e_block_pack_status pack_status = cluster_legalizer.add_mol_to_cluster(mol, new_cluster_id); + e_block_pack_status pack_status = cluster_legalizer.add_mol_to_cluster(mol_id, new_cluster_id); if (pack_status == e_block_pack_status::BLK_PASSED) { it = mol_list.erase(it); } else { @@ -330,30 +369,31 @@ void FullLegalizer::create_clusters(const PartialPlacement& p_placement) { // Check and output the clustering. std::unordered_set is_clock = alloc_and_load_is_clock(); - check_and_output_clustering(cluster_legalizer, packer_opts_, is_clock, arch_); + check_and_output_clustering(cluster_legalizer, vpr_setup_.PackerOpts, is_clock, &arch_); // Reset the cluster legalizer. This is required to load the packing. cluster_legalizer.reset(); // Regenerate the clustered netlist from the file generated previously. // FIXME: This writing and loading from a file is wasteful. Should generate // the clusters directly from the cluster legalizer. - vpr_load_packing(vpr_setup_, *arch_); - load_cluster_constraints(); + vpr_load_packing(vpr_setup_, arch_); const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; // Verify the packing and print some info - check_netlist(packer_opts_.pack_verbosity); + check_netlist(vpr_setup_.PackerOpts.pack_verbosity); writeClusteredNetlistStats(vpr_setup_.FileNameOpts.write_block_usage); print_pb_type_count(clb_nlist); } -void FullLegalizer::place_clusters(const ClusteredNetlist& clb_nlist, - const PartialPlacement& p_placement) { +void NaiveFullLegalizer::place_clusters(const ClusteredNetlist& clb_nlist, + const PlaceMacros& place_macros, + const PartialPlacement& p_placement) { // PLACING: // Create a lookup from the AtomBlockId to the APBlockId vtr::vector atom_to_ap_block(atom_netlist_.blocks().size()); for (APBlockId ap_blk_id : ap_netlist_.blocks()) { - const t_pack_molecule* blk_mol = ap_netlist_.block_molecule(ap_blk_id); - for (AtomBlockId atom_blk_id : blk_mol->atom_block_ids) { + PackMoleculeId blk_mol_id = ap_netlist_.block_molecule(ap_blk_id); + const t_pack_molecule& blk_mol = prepacker_.get_molecule(blk_mol_id); + for (AtomBlockId atom_blk_id : blk_mol.atom_block_ids) { // See issue #2791, some of the atom_block_ids may be invalid. They // can safely be ignored. if (!atom_blk_id.is_valid()) @@ -367,7 +407,7 @@ void FullLegalizer::place_clusters(const ClusteredNetlist& clb_nlist, // Move the clusters to where they want to be first. // TODO: The fixed clusters should probably be moved first for legality // reasons. - APClusterPlacer ap_cluster_placer; + APClusterPlacer ap_cluster_placer(place_macros, vpr_setup_.PlacerOpts.constraints_file.c_str()); std::vector unplaced_clusters; for (ClusterBlockId cluster_blk_id : clb_nlist.blocks()) { // Assume that the cluster will always want to be placed wherever the @@ -408,7 +448,7 @@ void FullLegalizer::place_clusters(const ClusteredNetlist& clb_nlist, // - This may be needed to perform SA. Not needed right now. } -void FullLegalizer::legalize(const PartialPlacement& p_placement) { +void NaiveFullLegalizer::legalize(const PartialPlacement& p_placement) { // Create a scoped timer for the full legalizer vtr::ScopedStartFinishTimer full_legalizer_timer("AP Full Legalizer"); @@ -428,8 +468,17 @@ void FullLegalizer::legalize(const PartialPlacement& p_placement) { // TODO: Eventually should be returned from the create_clusters method. const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; + // Initialize the placement context. + g_vpr_ctx.mutable_placement().init_placement_context(vpr_setup_.PlacerOpts, + arch_.directs); + + const PlaceMacros& place_macros = *g_vpr_ctx.placement().place_macros; + + // Update the floorplanning context with the macro information. + g_vpr_ctx.mutable_floorplanning().update_floorplanning_context_pre_place(place_macros); + // Place the clusters based on where the atoms want to be placed. - place_clusters(clb_nlist, p_placement); + place_clusters(clb_nlist, place_macros, p_placement); // Verify that the placement created by the full legalizer is valid. unsigned num_placement_errors = verify_placement(g_vpr_ctx); @@ -448,3 +497,86 @@ void FullLegalizer::legalize(const PartialPlacement& p_placement) { post_place_sync(); } +void APPack::legalize(const PartialPlacement& p_placement) { + // Create a scoped timer for the full legalizer + vtr::ScopedStartFinishTimer full_legalizer_timer("AP Full Legalizer"); + + // Convert the Partial Placement (APNetlist) to a flat placement (AtomNetlist). + FlatPlacementInfo flat_placement_info(atom_netlist_); + for (APBlockId ap_blk_id : ap_netlist_.blocks()) { + PackMoleculeId mol_id = ap_netlist_.block_molecule(ap_blk_id); + const t_pack_molecule& mol = prepacker_.get_molecule(mol_id); + for (AtomBlockId atom_blk_id : mol.atom_block_ids) { + if (!atom_blk_id.is_valid()) + continue; + flat_placement_info.blk_x_pos[atom_blk_id] = p_placement.block_x_locs[ap_blk_id]; + flat_placement_info.blk_y_pos[atom_blk_id] = p_placement.block_y_locs[ap_blk_id]; + flat_placement_info.blk_layer[atom_blk_id] = p_placement.block_layer_nums[ap_blk_id]; + flat_placement_info.blk_sub_tile[atom_blk_id] = p_placement.block_sub_tiles[ap_blk_id]; + } + } + + // Run the Packer stage with the flat placement as a hint. + try_pack(vpr_setup_.PackerOpts, + vpr_setup_.AnalysisOpts, + arch_, + vpr_setup_.PackerRRGraph, + prepacker_, + pre_cluster_timing_manager_, + flat_placement_info); + + // The Packer stores the clusters into a .net file. Load the packing file. + // FIXME: This should be removed. Reading from a file is strange. + vpr_load_packing(vpr_setup_, arch_); + + // Setup the global variables for placement. + g_vpr_ctx.mutable_placement().init_placement_context(vpr_setup_.PlacerOpts, arch_.directs); + g_vpr_ctx.mutable_floorplanning().update_floorplanning_context_pre_place(*g_vpr_ctx.placement().place_macros); + + // The placement will be stored in the global block loc registry. + BlkLocRegistry& blk_loc_registry = g_vpr_ctx.mutable_placement().mutable_blk_loc_registry(); + + // Create the noc cost handler used in the initial placer. + std::optional noc_cost_handler; + if (vpr_setup_.NocOpts.noc) + noc_cost_handler.emplace(blk_loc_registry.block_locs()); + + // Create the RNG container for the initial placer. + vtr::RngContainer rng(vpr_setup_.PlacerOpts.seed); + + // Run the initial placer on the clusters created by the packer, using the + // flat placement information from the global placer to guide where to place + // the clusters. + initial_placement(vpr_setup_.PlacerOpts, + vpr_setup_.PlacerOpts.constraints_file.c_str(), + vpr_setup_.NocOpts, + blk_loc_registry, + *g_vpr_ctx.placement().place_macros, + noc_cost_handler, + flat_placement_info, + rng); + + // Log some information on how good the reconstruction was. + log_flat_placement_reconstruction_info(flat_placement_info, + blk_loc_registry.block_locs(), + g_vpr_ctx.clustering().atoms_lookup, + g_vpr_ctx.atom().lookup(), + atom_netlist_, + g_vpr_ctx.clustering().clb_nlist); + + // Verify that the placement is valid for the VTR flow. + unsigned num_errors = verify_placement(blk_loc_registry, + *g_vpr_ctx.placement().place_macros, + g_vpr_ctx.clustering().clb_nlist, + g_vpr_ctx.device().grid, + g_vpr_ctx.floorplanning().cluster_constraints); + if (num_errors != 0) { + VPR_ERROR(VPR_ERROR_AP, + "\nCompleted placement consistency check, %d errors found.\n" + "Aborting program.\n", + num_errors); + } + + // Synchronize the pins in the clusters after placement. + post_place_sync(); +} diff --git a/vpr/src/analytical_place/full_legalizer.h b/vpr/src/analytical_place/full_legalizer.h index e5f72586b28..57baef27fc9 100644 --- a/vpr/src/analytical_place/full_legalizer.h +++ b/vpr/src/analytical_place/full_legalizer.h @@ -9,7 +9,8 @@ #pragma once -#include +#include +#include "ap_flow_enums.h" // Forward declarations class APNetlist; @@ -17,50 +18,37 @@ class AtomNetlist; class ClusteredNetlist; class DeviceGrid; class PartialPlacement; +class PlaceMacros; +class PreClusterTimingManager; class Prepacker; struct t_arch; -struct t_lb_type_rr_node; -struct t_logical_block_type; -struct t_model; -struct t_packer_opts; struct t_vpr_setup; /** * @brief The full legalizer in an AP flow * * Given a valid partial placement (of any level of legality), will produce a - * fully legal clustering and placement for use in the rest of the VTR flow. + * fully legal clustering and clustered placement for use in the rest of the + * VTR flow. */ class FullLegalizer { -public: - /** - * @brief Constructor of the Full Legalizer class. - * - * Brings in all the necessary state here. This is the state needed from the - * AP Context. the Packer Context, and the Placer Context. - */ + public: + virtual ~FullLegalizer() {} + FullLegalizer(const APNetlist& ap_netlist, - t_vpr_setup& vpr_setup, - const DeviceGrid& device_grid, - const t_arch* arch, const AtomNetlist& atom_netlist, const Prepacker& prepacker, - const std::vector& logical_block_types, - std::vector* lb_type_rr_graphs, - const t_model* user_models, - const t_model* library_models, - const t_packer_opts& packer_opts) - : ap_netlist_(ap_netlist), - vpr_setup_(vpr_setup), - device_grid_(device_grid), - arch_(arch), - atom_netlist_(atom_netlist), - prepacker_(prepacker), - logical_block_types_(logical_block_types), - lb_type_rr_graphs_(lb_type_rr_graphs), - user_models_(user_models), - library_models_(library_models), - packer_opts_(packer_opts) {} + const PreClusterTimingManager& pre_cluster_timing_manager, + const t_vpr_setup& vpr_setup, + const t_arch& arch, + const DeviceGrid& device_grid) + : ap_netlist_(ap_netlist) + , atom_netlist_(atom_netlist) + , prepacker_(prepacker) + , pre_cluster_timing_manager_(pre_cluster_timing_manager) + , vpr_setup_(vpr_setup) + , arch_(arch) + , device_grid_(device_grid) {} /** * @brief Perform legalization on the given partial placement solution @@ -69,9 +57,65 @@ class FullLegalizer { * This implies that all blocks are placed on the * device grid and fixed blocks are observed. */ - void legalize(const PartialPlacement& p_placement); + virtual void legalize(const PartialPlacement& p_placement) = 0; + + protected: + /// @brief The AP Netlist to fully legalize the flat placement of. + const APNetlist& ap_netlist_; + + /// @brief The Atom Netlist used to generate the AP Netlist. + const AtomNetlist& atom_netlist_; + + /// @brief The Prepacker used to create molecules from the Atom Netlist. + const Prepacker& prepacker_; + + /// @brief Pre-Clustering timing manager, hold pre-computed delay information + /// at the primitive level prior to packing. + const PreClusterTimingManager& pre_cluster_timing_manager_; -private: + /// @brief The VPR setup options passed into the VPR flow. This must be + /// mutable since some parts of packing modify the options. + const t_vpr_setup& vpr_setup_; + + /// @brief Information on the architecture of the FPGA. + const t_arch& arch_; + + /// @brief The device grid which records where clusters can be placed. + const DeviceGrid& device_grid_; +}; + +/** + * @brief A factory method which creates a Full Legalizer of the given type. + */ +std::unique_ptr make_full_legalizer(e_ap_full_legalizer full_legalizer_type, + const APNetlist& ap_netlist, + const AtomNetlist& atom_netlist, + const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, + const t_vpr_setup& vpr_setup, + const t_arch& arch, + const DeviceGrid& device_grid); + +/** + * @brief The Naive Full Legalizer. + * + * This Full Legalizer will try to create clusters exactly where they want to + * according to the Partial Placement. It will grow clusters from atoms that + * are placed in the same tile, then it will try to place the cluster at that + * location. If a location cannot be found, once all other clusters have tried + * to be placed, it will try to find anywhere the cluster will fit and place it + * there. + */ +class NaiveFullLegalizer : public FullLegalizer { + public: + using FullLegalizer::FullLegalizer; + + /** + * @brief Perform naive full legalization. + */ + void legalize(const PartialPlacement& p_placement) final; + + private: /** * @brief Helper method to create the clusters from the given partial * placement. @@ -85,26 +129,35 @@ class FullLegalizer { * placement. */ void place_clusters(const ClusteredNetlist& clb_nlist, + const PlaceMacros& place_macros, const PartialPlacement& p_placement); - - // AP Context Info - const APNetlist& ap_netlist_; - // Overall Setup Info - // FIXME: I do not like bringing all of this in. Perhaps clean up the methods - // that use it. - t_vpr_setup& vpr_setup_; - // Device Context Info - const DeviceGrid& device_grid_; - const t_arch* arch_; - // Packing Context Info - const AtomNetlist& atom_netlist_; - const Prepacker& prepacker_; - const std::vector& logical_block_types_; - std::vector* lb_type_rr_graphs_; - const t_model* user_models_; - const t_model* library_models_; - const t_packer_opts& packer_opts_; - // Placement Context Info - // TODO: Populate this once the placer is cleaned up some. }; +/** + * @brief APPack: A flat-placement-informed Packer Placer. + * + * The idea of APPack is to use the flat-placement information generated by the + * AP Flow to guide the Packer and Placer to a better solution. + * + * In the Packer, the flat-placement can provide more context for the clusters + * to pull in atoms that want to be near the other atoms in the cluster, and + * repell atoms that are far apart. This can potentially make better clusters + * than a Packer that does not know that information. + * + * In the Placer, the flat-placement can help decide where clusters of atoms + * want to be placed. If this placement is then fed into a Simulated Annealing + * based Detailed Placement step, this would enable it to converge on a better + * answer faster. + */ +class APPack : public FullLegalizer { + public: + using FullLegalizer::FullLegalizer; + + /** + * @brief Run APPack. + * + * This will call the Packer and Placer using the options provided by the + * user for these stages in VPR. + */ + void legalize(const PartialPlacement& p_placement) final; +}; diff --git a/vpr/src/analytical_place/gen_ap_netlist_from_atoms.cpp b/vpr/src/analytical_place/gen_ap_netlist_from_atoms.cpp index 34207e88145..75c3361ec3d 100644 --- a/vpr/src/analytical_place/gen_ap_netlist_from_atoms.cpp +++ b/vpr/src/analytical_place/gen_ap_netlist_from_atoms.cpp @@ -16,7 +16,6 @@ #include "prepack.h" #include "region.h" #include "user_place_constraints.h" -#include "vpr_types.h" #include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_time.h" @@ -40,10 +39,11 @@ APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, // Each net has the exact same name as in the atom netlist for (AtomBlockId atom_blk_id : atom_netlist.blocks()) { // Get the molecule of this block - t_pack_molecule* mol = prepacker.get_atom_molecule(atom_blk_id); + PackMoleculeId molecule_id = prepacker.get_atom_molecule(atom_blk_id); + const t_pack_molecule& mol = prepacker.get_molecule(molecule_id); // Create the AP block (if not already done) - const std::string& first_blk_name = atom_netlist.block_name(mol->atom_block_ids[0]); - APBlockId ap_blk_id = ap_netlist.create_block(first_blk_name, mol); + const std::string& first_blk_name = atom_netlist.block_name(mol.atom_block_ids[0]); + APBlockId ap_blk_id = ap_netlist.create_block(first_blk_name, molecule_id); // Add the ports and pins of this block to the supernode for (AtomPortId atom_port_id : atom_netlist.block_ports(atom_blk_id)) { BitIndex port_width = atom_netlist.port_width(atom_port_id); @@ -68,8 +68,9 @@ APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, // Fix the block locations given by the VPR constraints for (APBlockId ap_blk_id : ap_netlist.blocks()) { - const t_pack_molecule* mol = ap_netlist.block_molecule(ap_blk_id); - for (AtomBlockId mol_atom_blk_id : mol->atom_block_ids) { + PackMoleculeId molecule_id = ap_netlist.block_molecule(ap_blk_id); + const t_pack_molecule& mol = prepacker.get_molecule(molecule_id); + for (AtomBlockId mol_atom_blk_id : mol.atom_block_ids) { PartitionId part_id = constraints.get_atom_partition(mol_atom_blk_id); if (!part_id.is_valid()) continue; @@ -88,8 +89,13 @@ APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, const vtr::Rect& region_rect = region.get_rect(); VTR_ASSERT(region_rect.xmin() == region_rect.xmax() && "AP: Expect each region to be a single point in x!"); VTR_ASSERT(region_rect.ymin() == region_rect.ymax() && "AP: Expect each region to be a single point in y!"); - int blk_x_loc = region_rect.xmin(); - int blk_y_loc = region_rect.ymin(); + // Here we offset by 0.5 to put the fixed point in the center of the + // tile (assuming the tile is 1x1). + // TODO: Think about what to do when the user fixes blocks to large + // tiles. However, this solution will at least keep the atoms + // away from the edge of tiles. + float blk_x_loc = region_rect.xmin() + 0.5f; + float blk_y_loc = region_rect.ymin() + 0.5f; // Get the layer. VTR_ASSERT(region.get_layer_range().first == region.get_layer_range().second && "AP: Expect each region to be a single point in layer!"); int blk_layer_num = region.get_layer_range().first; @@ -172,4 +178,3 @@ APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, return ap_netlist; } - diff --git a/vpr/src/analytical_place/gen_ap_netlist_from_atoms.h b/vpr/src/analytical_place/gen_ap_netlist_from_atoms.h index f03055a826d..ed5ae7bb0d1 100644 --- a/vpr/src/analytical_place/gen_ap_netlist_from_atoms.h +++ b/vpr/src/analytical_place/gen_ap_netlist_from_atoms.h @@ -27,4 +27,3 @@ class UserPlaceConstraints; APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, const Prepacker& prepacker, const UserPlaceConstraints& constraints); - diff --git a/vpr/src/analytical_place/global_placer.cpp b/vpr/src/analytical_place/global_placer.cpp index d2fbfe42d11..d9131e85308 100644 --- a/vpr/src/analytical_place/global_placer.cpp +++ b/vpr/src/analytical_place/global_placer.cpp @@ -8,38 +8,156 @@ #include "global_placer.h" #include +#include #include +#include #include "analytical_solver.h" +#include "ap_flow_enums.h" #include "ap_netlist.h" +#include "ap_netlist_fwd.h" +#include "atom_netlist.h" +#include "device_grid.h" +#include "flat_placement_bins.h" +#include "flat_placement_density_manager.h" +#include "globals.h" #include "partial_legalizer.h" #include "partial_placement.h" -#include "vpr_error.h" +#include "physical_types.h" +#include "primitive_vector.h" #include "vtr_log.h" #include "vtr_time.h" -std::unique_ptr make_global_placer(e_global_placer placer_type, - const APNetlist& netlist) { - // Based on the placer type passed in, build the global placer. - switch (placer_type) { - case e_global_placer::SimPL: - return std::make_unique(netlist); - default: - VPR_FATAL_ERROR(VPR_ERROR_AP, - "Unrecognized global placer type"); - - } +std::unique_ptr make_global_placer(e_ap_analytical_solver analytical_solver_type, + e_ap_partial_legalizer partial_legalizer_type, + const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const DeviceGrid& device_grid, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity) { + return std::make_unique(analytical_solver_type, + partial_legalizer_type, + ap_netlist, + prepacker, + atom_netlist, + device_grid, + logical_block_types, + physical_tile_types, + pre_cluster_timing_manager, + ap_timing_tradeoff, + log_verbosity); } -SimPLGlobalPlacer::SimPLGlobalPlacer(const APNetlist& netlist) : GlobalPlacer(netlist) { +SimPLGlobalPlacer::SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_type, + e_ap_partial_legalizer partial_legalizer_type, + const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const DeviceGrid& device_grid, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity) + : GlobalPlacer(ap_netlist, log_verbosity) { // This can be a long method. Good to time this to see how long it takes to // construct the global placer. vtr::ScopedStartFinishTimer global_placer_building_timer("Constructing Global Placer"); + // Build the solver. - solver_ = make_analytical_solver(e_analytical_solver::QP_HYBRID, - netlist); + VTR_LOGV(log_verbosity_ >= 10, "\tBuilding the solver...\n"); + solver_ = make_analytical_solver(analytical_solver_type, + ap_netlist_, + device_grid, + atom_netlist, + pre_cluster_timing_manager, + ap_timing_tradeoff, + log_verbosity_); + + // Build the density manager used by the partial legalizer. + VTR_LOGV(log_verbosity_ >= 10, "\tBuilding the density manager...\n"); + density_manager_ = std::make_shared(ap_netlist_, + prepacker, + atom_netlist, + device_grid, + logical_block_types, + physical_tile_types, + log_verbosity_); + // Build the partial legalizer - partial_legalizer_ = make_partial_legalizer(e_partial_legalizer::FLOW_BASED, - netlist); + VTR_LOGV(log_verbosity_ >= 10, "\tBuilding the partial legalizer...\n"); + partial_legalizer_ = make_partial_legalizer(partial_legalizer_type, + ap_netlist_, + density_manager_, + prepacker, + log_verbosity_); +} + +/** + * @brief Helper method to print the statistics on the given partial placement. + */ +static void print_placement_stats(const PartialPlacement& p_placement, + const APNetlist& ap_netlist, + FlatPlacementDensityManager& density_manager) { + // Print the placement HPWL + VTR_LOG("\tPlacement HPWL: %f\n", p_placement.get_hpwl(ap_netlist)); + + // Print density information. Need to reset the density manager to ensure + // the data is valid. + density_manager.import_placement_into_bins(p_placement); + + // Print the number of overfilled bins. + size_t num_overfilled_bins = density_manager.get_overfilled_bins().size(); + VTR_LOG("\tNumber of overfilled bins: %zu\n", num_overfilled_bins); + + // Print the average overfill + float total_overfill = 0.0f; + for (FlatPlacementBinId bin_id : density_manager.get_overfilled_bins()) { + total_overfill += density_manager.get_bin_overfill(bin_id).manhattan_norm(); + } + float avg_overfill = 0.0f; + if (num_overfilled_bins != 0) + avg_overfill = total_overfill / static_cast(num_overfilled_bins); + VTR_LOG("\tAverage overfill magnitude: %f\n", avg_overfill); + + // Print the number of overfilled tiles per type. + const auto& physical_tile_types = g_vpr_ctx.device().physical_tile_types; + const auto& device_grid = g_vpr_ctx.device().grid; + std::vector overfilled_tiles_by_type(physical_tile_types.size(), 0); + for (FlatPlacementBinId bin_id : density_manager.get_overfilled_bins()) { + const auto& bin_region = density_manager.flat_placement_bins().bin_region(bin_id); + auto tile_loc = t_physical_tile_loc((int)bin_region.xmin(), + (int)bin_region.ymin(), + 0); + auto tile_type = device_grid.get_physical_type(tile_loc); + overfilled_tiles_by_type[tile_type->index]++; + } + VTR_LOG("\tOverfilled bins by tile type:\n"); + for (size_t type_idx = 0; type_idx < physical_tile_types.size(); type_idx++) { + VTR_LOG("\t\t%10s: %zu\n", + physical_tile_types[type_idx].name.c_str(), + overfilled_tiles_by_type[type_idx]); + } + + // Count the number of blocks that were placed in a bin which they cannot + // physically be placed into (according to their mass). + unsigned num_misplaced_blocks = 0; + for (FlatPlacementBinId bin_id : density_manager.get_overfilled_bins()) { + for (APBlockId ap_blk_id : density_manager.flat_placement_bins().bin_contained_blocks(bin_id)) { + // Get the blk mass and project it onto the capacity of its bin. + PrimitiveVector blk_mass = density_manager.mass_calculator().get_block_mass(ap_blk_id); + PrimitiveVector projected_mass = blk_mass; + projected_mass.project(density_manager.get_bin_capacity(bin_id)); + // If the projected mass does not match its match, this implies that + // there this block does not belong in this bin. + if (projected_mass != blk_mass) + num_misplaced_blocks++; + } + } + VTR_LOG("\tNumber of blocks in an incompatible bin: %zu\n", num_misplaced_blocks); } /** @@ -94,7 +212,17 @@ PartialPlacement SimPLGlobalPlacer::place() { if (log_verbosity_ >= 1) print_SimPL_status_header(); // Initialialize the partial placement object. - PartialPlacement p_placement(netlist_); + PartialPlacement p_placement(ap_netlist_); + + float total_time_spent_in_solver = 0.0f; + float total_time_spent_in_legalizer = 0.0f; + + // Create a partial placement object to store the best placement found during + // global placement. It is possible for the global placement to hit a minimum + // in the middle of its iterations, this lets us keep that solution. + PartialPlacement best_p_placement(ap_netlist_); + double best_ub_hpwl = std::numeric_limits::max(); + // Run the global placer. for (size_t i = 0; i < max_num_iterations_; i++) { float iter_start_time = runtime_timer.elapsed_sec(); @@ -103,13 +231,16 @@ PartialPlacement SimPLGlobalPlacer::place() { float solver_start_time = runtime_timer.elapsed_sec(); solver_->solve(i, p_placement); float solver_end_time = runtime_timer.elapsed_sec(); - double lb_hpwl = p_placement.get_hpwl(netlist_); + double lb_hpwl = p_placement.get_hpwl(ap_netlist_); // Run the legalizer. float legalizer_start_time = runtime_timer.elapsed_sec(); partial_legalizer_->legalize(p_placement); float legalizer_end_time = runtime_timer.elapsed_sec(); - double ub_hpwl = p_placement.get_hpwl(netlist_); + double ub_hpwl = p_placement.get_hpwl(ap_netlist_); + + total_time_spent_in_solver += solver_end_time - solver_start_time; + total_time_spent_in_legalizer += legalizer_end_time - legalizer_start_time; // Print some stats if (log_verbosity_ >= 1) { @@ -120,15 +251,37 @@ PartialPlacement SimPLGlobalPlacer::place() { iter_end_time - iter_start_time); } + // If this placement is better than the best we have seen, save it. + if (ub_hpwl < best_ub_hpwl) { + best_ub_hpwl = ub_hpwl; + best_p_placement = p_placement; + } + // Exit condition: If the upper-bound and lower-bound HPWLs are // sufficiently close together then stop. double hpwl_relative_gap = (ub_hpwl - lb_hpwl) / ub_hpwl; if (hpwl_relative_gap < target_hpwl_relative_gap_) break; } + + // Print statistics on the solver used. + solver_->print_statistics(); + + // Print statistics on the partial legalizer used. + partial_legalizer_->print_statistics(); + + VTR_LOG("Global Placer Statistics:\n"); + VTR_LOG("\tTime spent in solver: %g seconds\n", total_time_spent_in_solver); + VTR_LOG("\tTime spent in legalizer: %g seconds\n", total_time_spent_in_legalizer); + + // Print some statistics on the final placement. + VTR_LOG("Placement after Global Placement:\n"); + print_placement_stats(best_p_placement, + ap_netlist_, + *density_manager_); + // Return the placement from the final iteration. // TODO: investigate saving the best solution found so far. It should be // cheap to save a copy of the PartialPlacement object. - return p_placement; + return best_p_placement; } - diff --git a/vpr/src/analytical_place/global_placer.h b/vpr/src/analytical_place/global_placer.h index 0628b9b0d50..7772aa302bb 100644 --- a/vpr/src/analytical_place/global_placer.h +++ b/vpr/src/analytical_place/global_placer.h @@ -15,19 +15,17 @@ #pragma once #include +#include "ap_flow_enums.h" +#include "flat_placement_density_manager.h" +#include "partial_legalizer.h" // Forward declarations class APNetlist; class AnalyticalSolver; -class PartialPlacement; class PartialLegalizer; - -/** - * @brief Enumeration of all of the global placers currently implemented in VPR. - */ -enum class e_global_placer { - SimPL // Global placer based on the SimPL paper. -}; +class Prepacker; +class PreClusterTimingManager; +struct PartialPlacement; /** * @brief The Global Placer base class @@ -38,7 +36,7 @@ enum class e_global_placer { * placers. */ class GlobalPlacer { -public: + public: virtual ~GlobalPlacer() {} /** @@ -50,9 +48,9 @@ class GlobalPlacer { * @param log_verbosity The verbosity of log messages in the Global * Placer. */ - GlobalPlacer(const APNetlist& netlist, int log_verbosity = 1) - : netlist_(netlist), - log_verbosity_(log_verbosity) {} + GlobalPlacer(const APNetlist& ap_netlist, int log_verbosity) + : ap_netlist_(ap_netlist) + , log_verbosity_(log_verbosity) {} /** * @brief Perform global placement on the given netlist. @@ -62,10 +60,9 @@ class GlobalPlacer { */ virtual PartialPlacement place() = 0; -protected: - + protected: /// @brief The APNetlist the global placer is placing. - const APNetlist& netlist_; + const APNetlist& ap_netlist_; /// @brief The setting of how verbose the log messages should be in the /// global placer. Anything larger than zero will display per @@ -76,8 +73,17 @@ class GlobalPlacer { /** * @brief A factory method which creates a Global Placer of the given type. */ -std::unique_ptr make_global_placer(e_global_placer placer_type, - const APNetlist& netlist); +std::unique_ptr make_global_placer(e_ap_analytical_solver analytical_solver_type, + e_ap_partial_legalizer partial_legalizer_type, + const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const DeviceGrid& device_grid, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity); /** * @brief A Global Placer based on the SimPL work for analytical ASIC placement. @@ -106,8 +112,7 @@ std::unique_ptr make_global_placer(e_global_placer placer_type, * approach each other until a good quality, mostly-legal solution is found. */ class SimPLGlobalPlacer : public GlobalPlacer { -private: - + private: /// @brief The maximum number of iterations the global placer can perform. static constexpr size_t max_num_iterations_ = 100; @@ -115,22 +120,35 @@ class SimPLGlobalPlacer : public GlobalPlacer { /// lower-bound placements. The placer will stop if the difference /// between the two bounds, normalized to the upper-bound, is smaller /// than this number. - static constexpr double target_hpwl_relative_gap_ = 0.10; + /// This number was empircally found to work well. + static constexpr double target_hpwl_relative_gap_ = 0.05; /// @brief The solver which generates the lower-bound placement. std::unique_ptr solver_; + /// @brief The denisty manager the partial legalizer will optimize over. + std::shared_ptr density_manager_; + /// @brief The legalizer which generates the upper-bound placement. std::unique_ptr partial_legalizer_; -public: - + public: /** * @brief Constructor for the SimPL Global Placer * * Constructs the solver and partial legalizer. */ - SimPLGlobalPlacer(const APNetlist& netlist); + SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_type, + e_ap_partial_legalizer partial_legalizer_type, + const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const DeviceGrid& device_grid, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity); /** * @brief Run a SimPL-like global placement algorithm @@ -140,4 +158,3 @@ class SimPLGlobalPlacer : public GlobalPlacer { */ PartialPlacement place() final; }; - diff --git a/vpr/src/analytical_place/model_grouper.cpp b/vpr/src/analytical_place/model_grouper.cpp new file mode 100644 index 00000000000..0aca963c96a --- /dev/null +++ b/vpr/src/analytical_place/model_grouper.cpp @@ -0,0 +1,184 @@ +/** + * @file + * @author Alex Singer + * @date March 2025 + * @brief Implementation of a model grouper class which groups models together + * which must be legalized together in a flat placement. + */ + +#include "model_grouper.h" +#include +#include +#include +#include +#include "cad_types.h" +#include "logic_types.h" +#include "prepack.h" +#include "vtr_assert.h" +#include "vtr_log.h" + +/** + * @brief Recursive helper function which gets the models in the given pattern + * block. + * + * @param pattern_block + * The pattern block to get the models of. + * @param models + * A set of the models found so far. + * @param block_visited + * A vector of flags for each pattern block to signify which blocks have + * been visited. + */ +static void get_pattern_models_recurr(t_pack_pattern_block* pattern_block, + std::unordered_set& models, + std::vector& block_visited) { + // If the pattern block is invalid or this block has been visited, return. + if (pattern_block == nullptr || block_visited[pattern_block->block_id]) { + return; + } + + // Mark this block as visited and insert its model into the models vector. + block_visited[pattern_block->block_id] = true; + models.insert(pattern_block->pb_type->model->index); + + // Go through this block's connections and get their pattern models. + t_pack_pattern_connections* connection = pattern_block->connections; + while (connection != nullptr) { + get_pattern_models_recurr(connection->from_block, models, block_visited); + get_pattern_models_recurr(connection->to_block, models, block_visited); + connection = connection->next; + } +} + +/** + * @brief Entry point into the recursive function above. Gets the models in + * the given pack pattern. + */ +static std::unordered_set get_pattern_models(const t_pack_patterns& pack_pattern) { + std::unordered_set models_in_pattern; + + // Initialize the visited flags for each block to false. + std::vector block_visited(pack_pattern.num_blocks, false); + // Begin the recursion with the root block. + get_pattern_models_recurr(pack_pattern.root_block, models_in_pattern, block_visited); + + return models_in_pattern; +} + +ModelGrouper::ModelGrouper(const Prepacker& prepacker, + t_model* user_models, + t_model* library_models, + int log_verbosity) { + /** + * Group the models together based on their pack patterns. If model A and + * model B form a pattern, and model B and model C form a pattern, then + * models A, B, and C are in a group together. + * + * An efficient way to find this is to represent this problem as a graph, + * where each node is a model and each edge is a relationship where a model + * is in a pack pattern with another model. We can then perform BFS to find + * the connected sub-graphs which will be the groups. + */ + + // Get the number of models + // TODO: Clean up the models vectors in VTR. + std::unordered_map model_name; + unsigned num_models = 0; + t_model* model = library_models; + while (model != nullptr) { + model_name[model->index] = model->name; + num_models++; + model = model->next; + } + model = user_models; + while (model != nullptr) { + model_name[model->index] = model->name; + num_models++; + model = model->next; + } + + // Create an adjacency list for the edges. An edge is formed where two + // models share a pack pattern together. + std::vector> adj_list(num_models); + for (const t_pack_patterns& pack_pattern : prepacker.get_all_pack_patterns()) { + // Get the models within this pattern. + auto models_in_pattern = get_pattern_models(pack_pattern); + VTR_ASSERT_SAFE(!models_in_pattern.empty()); + + // Debug print the models within the pattern. + if (log_verbosity >= 20) { + VTR_LOG("Pattern: %s\n\t", pack_pattern.name); + for (int model_idx : models_in_pattern) { + VTR_LOG("%s ", model_name[model_idx]); + } + VTR_LOG("\n"); + } + + // Connect each of the models to the first model in the pattern. Since + // we only care if there exist a path from each model to another, we do + // not need to connect the models in a clique. + int first_model_idx = *models_in_pattern.begin(); + for (int model_idx : models_in_pattern) { + adj_list[model_idx].insert(first_model_idx); + adj_list[first_model_idx].insert(model_idx); + } + } + + // Perform BFS to group the models. + VTR_LOGV(log_verbosity >= 20, + "Finding model groups...\n"); + std::queue node_queue; + model_group_id_.resize(num_models, ModelGroupId::INVALID()); + for (int model_idx = 0; model_idx < (int)num_models; model_idx++) { + // If this model is already in a group, skip it. + if (model_group_id_[model_idx].is_valid()) { + VTR_LOGV(log_verbosity >= 20, + "\t(%d -> %d)\n", model_idx, model_group_id_[model_idx]); + continue; + } + + ModelGroupId group_id = ModelGroupId(group_ids_.size()); + // Put the model in this group and push to the queue. + model_group_id_[model_idx] = group_id; + node_queue.push(model_idx); + + while (!node_queue.empty()) { + // Pop a node from the queue, and explore its neighbors. + int node_model_idx = node_queue.front(); + node_queue.pop(); + for (int neighbor_model_idx : adj_list[node_model_idx]) { + // If this neighbor is already in this group, skip it. + if (model_group_id_[neighbor_model_idx].is_valid()) { + VTR_ASSERT_SAFE(model_group_id_[neighbor_model_idx] == group_id); + continue; + } + // Put the neighbor in this group and push it to the queue. + model_group_id_[neighbor_model_idx] = group_id; + node_queue.push(neighbor_model_idx); + } + } + + VTR_LOGV(log_verbosity >= 20, + "\t(%d -> %d)\n", model_idx, model_group_id_[model_idx]); + group_ids_.push_back(group_id); + } + + // Create a lookup between each group and the models it contains. + groups_.resize(groups().size()); + for (int model_idx = 0; model_idx < (int)num_models; model_idx++) { + groups_[model_group_id_[model_idx]].push_back(model_idx); + } + + // Debug printing for each group. + if (log_verbosity >= 20) { + for (ModelGroupId group_id : groups()) { + const std::vector& group = groups_[group_id]; + VTR_LOG("Group %zu:\n", group_id); + VTR_LOG("\tSize = %zu\n", group.size()); + VTR_LOG("\tContained models:\n"); + for (int model_idx : group) { + VTR_LOG("\t\t%s\n", model_name[model_idx]); + } + } + } +} diff --git a/vpr/src/analytical_place/model_grouper.h b/vpr/src/analytical_place/model_grouper.h new file mode 100644 index 00000000000..d5a9113d6c1 --- /dev/null +++ b/vpr/src/analytical_place/model_grouper.h @@ -0,0 +1,115 @@ +/** + * @file + * @author Alex Singer + * @date March 2025 + * @brief Declaration of a model grouper class which groups together models + * that must be legalized together in a flat placement. + */ + +#pragma once + +#include +#include "vtr_assert.h" +#include "vtr_range.h" +#include "vtr_strong_id.h" +#include "vtr_vector.h" +#include "vtr_vector_map.h" + +// Forward declarations. +class Prepacker; +struct t_model; + +/// @brief Tag for the ModelGroupId +struct model_group_id_tag; + +/// @brief A unique ID of a group of models created by the ModelGrouper class. +typedef vtr::StrongId ModelGroupId; + +/** + * @brief A manager class for grouping together models that must be legalized + * together in a flat placement due to how they form molecules with each + * other. + * + * When performing legalization of a flat placement, it is desirable to split + * the problem into independent legalization problems. We cannot place all of + * the blocks of different model types independently since some blocks are made + * of multiple different types of models. We wish to find the minimum number of + * models that we need to legalize at the same time. + * + * This class groups models together based on the pack patterns that they can + * form in the prepacker. If model A and model B can form a pack pattern, and + * model B and model C can form a pack pattern, then models A, B, and C form a + * group and must be legalized together. + * + * This class also manages what models each group contains and the group of each + * model, where the user can use IDs to get relavent information. + */ +class ModelGrouper { + public: + // Iterator for the model group IDs + typedef typename vtr::vector_map::const_iterator group_iterator; + + // Range for the model group IDs + typedef typename vtr::Range group_range; + + public: + ModelGrouper() = delete; + + /** + * @brief Constructor for the model grouper class. Groups are formed here. + * + * @param prepacker + * The prepacker used to create molecules in the flat placement. This + * provides the pack patterns for forming the groups. + * @param user_models + * Linked list of user-provided models. + * @param library_models + * Linked list of library models. + * @param log_verbosity + * The verbosity of log messages in the grouper class. + */ + ModelGrouper(const Prepacker& prepacker, + t_model* user_models, + t_model* library_models, + int log_verbosity); + + /** + * @brief Returns a list of all valid group IDs. + */ + inline group_range groups() const { + return vtr::make_range(group_ids_.begin(), group_ids_.end()); + } + + /** + * @brief Gets the group ID of the given model. + */ + inline ModelGroupId get_model_group_id(int model_index) const { + VTR_ASSERT_SAFE_MSG(model_index < (int)model_group_id_.size(), + "Model index outside of range for model_group_id_"); + ModelGroupId group_id = model_group_id_[model_index]; + VTR_ASSERT_SAFE_MSG(group_id.is_valid(), + "Model is not in a group"); + return group_id; + } + + /** + * @brief Gets the models in the given group. + */ + inline const std::vector& get_models_in_group(ModelGroupId group_id) const { + VTR_ASSERT_SAFE_MSG(group_id.is_valid(), + "Invalid group id"); + VTR_ASSERT_SAFE_MSG(groups_[group_id].size() != 0, + "Group is empty"); + return groups_[group_id]; + } + + private: + /// @brief List of all group IDs. + vtr::vector_map group_ids_; + + /// @brief A lookup between models and the group ID that contains them. + std::vector model_group_id_; + + /// @brief A lookup between each group ID and the models in that group. + vtr::vector> groups_; +}; diff --git a/vpr/src/analytical_place/partial_legalizer.cpp b/vpr/src/analytical_place/partial_legalizer.cpp index e782c85b073..7021734f8d5 100644 --- a/vpr/src/analytical_place/partial_legalizer.cpp +++ b/vpr/src/analytical_place/partial_legalizer.cpp @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include #include @@ -19,28 +21,43 @@ #include #include #include "ap_netlist.h" -#include "device_grid.h" +#include "flat_placement_bins.h" +#include "flat_placement_density_manager.h" +#include "flat_placement_mass_calculator.h" #include "globals.h" +#include "model_grouper.h" #include "partial_placement.h" #include "physical_types.h" +#include "prepack.h" #include "primitive_vector.h" #include "vpr_context.h" #include "vpr_error.h" -#include "vpr_types.h" #include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_log.h" -#include "vtr_ndmatrix.h" +#include "vtr_math.h" +#include "vtr_prefix_sum.h" #include "vtr_strong_id.h" +#include "vtr_time.h" #include "vtr_vector.h" #include "vtr_vector_map.h" -std::unique_ptr make_partial_legalizer(e_partial_legalizer legalizer_type, - const APNetlist& netlist) { +std::unique_ptr make_partial_legalizer(e_ap_partial_legalizer legalizer_type, + const APNetlist& netlist, + std::shared_ptr density_manager, + const Prepacker& prepacker, + int log_verbosity) { // Based on the partial legalizer type passed in, build the partial legalizer. switch (legalizer_type) { - case e_partial_legalizer::FLOW_BASED: - return std::make_unique(netlist); + case e_ap_partial_legalizer::FlowBased: + return std::make_unique(netlist, + density_manager, + log_verbosity); + case e_ap_partial_legalizer::BiPartitioning: + return std::make_unique(netlist, + density_manager, + prepacker, + log_verbosity); default: VPR_FATAL_ERROR(VPR_ERROR_AP, "Unrecognized partial legalizer type"); @@ -49,164 +66,6 @@ std::unique_ptr make_partial_legalizer(e_partial_legalizer leg return nullptr; } -/** - * @brief Get the scalar mass of the given model (primitive type). - * - * A model with a higher mass will take up more space in its bin which may force - * more spreading of that type of primitive. - * - * TODO: This will be made more complicated later. Models may be weighted based - * on some factors. - */ -static inline float get_model_mass(const t_model* model) { - // Currently, all models have a mass of one. - (void)model; - return 1.f; -} - -/** - * @brief Get the primitive mass of the given block. - * - * This returns an M-dimensional vector with each entry indicating the mass of - * that primitive type in this block. M is the number of unique models - * (primitive types) in the architecture. - */ -static inline PrimitiveVector get_primitive_mass(APBlockId blk_id, - const APNetlist& netlist) { - PrimitiveVector mass; - const t_pack_molecule* mol = netlist.block_molecule(blk_id); - for (AtomBlockId atom_blk_id : mol->atom_block_ids) { - // See issue #2791, some of the atom_block_ids may be invalid. They can - // safely be ignored. - if (!atom_blk_id.is_valid()) - continue; - const t_model* model = g_vpr_ctx.atom().nlist.block_model(atom_blk_id); - VTR_ASSERT_DEBUG(model->index >= 0); - mass.add_val_to_dim(get_model_mass(model), model->index); - } - return mass; -} - -// This method is being forward-declared due to the double recursion below. -// Eventually this should be made into a non-recursive algorithm for performance, -// however this is not in a performance critical part of the code. -static PrimitiveVector get_primitive_capacity(const t_pb_type* pb_type); - -/** - * @brief Get the amount of primitives this mode can contain. - * - * This is part of a double recursion, since a mode contains primitives which - * themselves have modes. - */ -static PrimitiveVector get_primitive_capacity(const t_mode& mode) { - // Accumulate the capacities of all the pbs in this mode. - PrimitiveVector capacity; - for (int pb_child_idx = 0; pb_child_idx < mode.num_pb_type_children; pb_child_idx++) { - const t_pb_type& pb_type = mode.pb_type_children[pb_child_idx]; - PrimitiveVector pb_capacity = get_primitive_capacity(&pb_type); - // A mode may contain multiple pbs of the same type, multiply the - // capacity. - pb_capacity *= pb_type.num_pb; - capacity += pb_capacity; - } - return capacity; -} - -/** - * @brief Get the amount of primitives this pb can contain. - * - * This is the other part of the double recursion. A pb may have multiple modes. - * Modes are made of pbs. - */ -static PrimitiveVector get_primitive_capacity(const t_pb_type* pb_type) { - // Since a pb cannot be multiple modes at the same time, we do not - // accumulate the capacities of the mode. Instead we need to "mix" the two - // capacities as if the pb could choose either one. - PrimitiveVector capacity; - // If this is a leaf / primitive, create the base PrimitiveVector capacity. - if (pb_type->num_modes == 0) { - const t_model* model = pb_type->model; - VTR_ASSERT(model != nullptr); - VTR_ASSERT_DEBUG(model->index >= 0); - capacity.add_val_to_dim(get_model_mass(model), model->index); - return capacity; - } - // For now, we simply mix the capacities of modes by taking the max of each - // dimension of the capcities. This provides an upper-bound on the amount of - // primitives this pb can contain. - for (int mode = 0; mode < pb_type->num_modes; mode++) { - PrimitiveVector mode_capacity = get_primitive_capacity(pb_type->modes[mode]); - capacity = PrimitiveVector::max(capacity, mode_capacity); - } - return capacity; -} - -/** - * @brief Helper method to get the primitive capacity of the given logical block - * type. - * - * This is the entry point to the double recursion. - */ -static inline PrimitiveVector get_primitive_capacity(const t_logical_block_type& block_type) { - // If this logical block is empty, it cannot contain any primitives. - if (block_type.is_empty()) - return PrimitiveVector(); - // The primitive capacity of a logical block is the primitive capacity of - // its root pb. - return get_primitive_capacity(block_type.pb_type); -} - -/** - * @brief Get the primitive capacity of the given sub_tile. - * - * Sub_tiles may reuse logical blocks between one another, therefore this method - * requires that the capacities of all of the logical blocks have been - * pre-calculated and stored in the given vector. - * - * @param sub_tile The sub_tile to get the capacity of. - * @param logical_block_type_capacities The capacities of all logical block - * types. - */ -static inline PrimitiveVector get_primitive_capacity(const t_sub_tile& sub_tile, - const std::vector& logical_block_type_capacities) { - // Similar to getting the primitive capacity of the pb, sub_tiles have many - // equivalent sites, but it can only be one of them at a time. Need to "mix" - // the capacities of the different sites this sub_tile may be. - PrimitiveVector capacity; - for (t_logical_block_type_ptr block_type : sub_tile.equivalent_sites) { - const PrimitiveVector& block_capacity = logical_block_type_capacities[block_type->index]; - // Currently, we take the max of each primitive dimension as an upper - // bound on the capacity of the sub_tile. - capacity = PrimitiveVector::max(capacity, block_capacity); - } - return capacity; -} - -/** - * @brief Get the primitive capacity of a tile of the given type. - * - * Tiles may reuse logical blocks between one another, therefore this method - * requires that the capacities of all of the logical blocks have been - * pre-calculated and stored in the given vector. - * - * @param tile_type The tile type to get the capacity of. - * @param logical_block_type_capacities The capacities of all logical block - * types. - */ -static inline PrimitiveVector get_primitive_capacity(const t_physical_tile_type& tile_type, - const std::vector& logical_block_type_capacities) { - // Accumulate the capacities of all the sub_tiles in the given tile type. - PrimitiveVector capacity; - for (const t_sub_tile& sub_tile : tile_type.sub_tiles) { - PrimitiveVector sub_tile_capacity = get_primitive_capacity(sub_tile, logical_block_type_capacities); - // A tile may contain many sub_tiles of the same type. Multiply by the - // number of sub_tiles of this type. - sub_tile_capacity *= sub_tile.capacity.total(); - capacity += sub_tile_capacity; - } - return capacity; -} - /** * @brief Get the number of models in the device architecture. * @@ -228,106 +87,46 @@ static inline size_t get_num_models() { return num_models; } -/** - * @brief Debug printing method to print the capacities of all logical blocks - * and physical tile types. - */ -static inline void print_capacities(const std::vector& logical_block_type_capacities, - const std::vector& physical_tile_type_capacities, - const std::vector& logical_block_types, - const std::vector& physical_tile_types) { - // Get a linear list of all models. - // TODO: Again, the way these models are stored is so annoying. It would be - // nice if they were already vectors! - std::vector all_models; - t_model* curr_model = g_vpr_ctx.device().arch->models; - while (curr_model != nullptr) { - if (curr_model->index >= (int)all_models.size()) - all_models.resize(curr_model->index + 1); - all_models[curr_model->index] = curr_model; - curr_model = curr_model->next; - } - curr_model = g_vpr_ctx.device().arch->model_library; - while (curr_model != nullptr) { - if (curr_model->index >= (int)all_models.size()) - all_models.resize(curr_model->index + 1); - all_models[curr_model->index] = curr_model; - curr_model = curr_model->next; - } - // Print the capacities. - VTR_LOG("Logical Block Type Capacities:\n"); - VTR_LOG("------------------------------\n"); - VTR_LOG("name\t"); - for (t_model* model : all_models) { - VTR_LOG("%s\t", model->name); - } - VTR_LOG("\n"); - for (const t_logical_block_type& block_type : logical_block_types) { - const PrimitiveVector& capacity = logical_block_type_capacities[block_type.index]; - VTR_LOG("%s\t", block_type.name.c_str()); - for (t_model* model : all_models) { - VTR_LOG("%.2f\t", capacity.get_dim_val(model->index)); - } - VTR_LOG("\n"); - } - VTR_LOG("\n"); - VTR_LOG("Physical Tile Type Capacities:\n"); - VTR_LOG("------------------------------\n"); - VTR_LOG("name\t"); - for (t_model* model : all_models) { - VTR_LOG("%s\t", model->name); - } - VTR_LOG("\n"); - for (const t_physical_tile_type& tile_type : physical_tile_types) { - const PrimitiveVector& capacity = physical_tile_type_capacities[tile_type.index]; - VTR_LOG("%s\t", tile_type.name.c_str()); - for (t_model* model : all_models) { - VTR_LOG("%.2f\t", capacity.get_dim_val(model->index)); - } - VTR_LOG("\n"); - } - VTR_LOG("\n"); -} - /** * @brief Helper method to get the direct neighbors of the given bin. * * A direct neighbor of a bin is a bin which shares a side with the given bin on * the tile graph. Corners do not count. */ -static std::unordered_set get_direct_neighbors_of_bin( - LegalizerBinId bin_id, - const vtr::vector_map& bins, - const vtr::NdMatrix tile_bin) { - const LegalizerBin& bin = bins[bin_id]; - int bl_x = bin.bounding_box.bottom_left().x(); - int bl_y = bin.bounding_box.bottom_left().y(); - size_t bin_width = bin.bounding_box.width(); - size_t bin_height = bin.bounding_box.height(); +static std::unordered_set get_direct_neighbors_of_bin( + FlatPlacementBinId bin_id, + const FlatPlacementDensityManager& density_manager) { + const vtr::Rect& bin_region = density_manager.flat_placement_bins().bin_region(bin_id); + int bl_x = bin_region.bottom_left().x(); + int bl_y = bin_region.bottom_left().y(); + size_t bin_width = bin_region.width(); + size_t bin_height = bin_region.height(); // This is an unfortunate consequence of using double precision to store // the bounding box. We need to ensure that the bin represents a tile (not // part of a tile). If it did represent part of a tile, this algorithm // would need to change. - VTR_ASSERT_DEBUG(static_cast(bl_x) == bin.bounding_box.bottom_left().x() && - static_cast(bl_y) == bin.bounding_box.bottom_left().y() && - static_cast(bin_width) == bin.bounding_box.width() && - static_cast(bin_height) == bin.bounding_box.height()); + VTR_ASSERT_DEBUG(static_cast(bl_x) == bin_region.bottom_left().x() && static_cast(bl_y) == bin_region.bottom_left().y() && static_cast(bin_width) == bin_region.width() && static_cast(bin_height) == bin_region.height()); + + double placeable_region_width, placeable_region_height, placeable_region_depth; + std::tie(placeable_region_width, placeable_region_height, placeable_region_depth) = density_manager.get_overall_placeable_region_size(); + // Current does not handle 3D FPGAs + VTR_ASSERT(placeable_region_depth == 1.0); // Add the neighbors. - std::unordered_set neighbor_bin_ids; + std::unordered_set neighbor_bin_ids; // Add unique tiles on left and right sides for (size_t ty = bl_y; ty < bl_y + bin_height; ty++) { if (bl_x >= 1) - neighbor_bin_ids.insert(tile_bin[bl_x - 1][ty]); - if (bl_x <= (int)(tile_bin.dim_size(0) - bin_width - 1)) - neighbor_bin_ids.insert(tile_bin[bl_x + bin_width][ty]); + neighbor_bin_ids.insert(density_manager.get_bin(bl_x - 1, ty, 0.0)); + if (bl_x <= (int)(placeable_region_width - bin_width - 1)) + neighbor_bin_ids.insert(density_manager.get_bin(bl_x + bin_width, ty, 0.0)); } // Add unique tiles on the top and bottom for (size_t tx = bl_x; tx < bl_x + bin_width; tx++) { if (bl_y >= 1) - neighbor_bin_ids.insert(tile_bin[tx][bl_y - 1]); - if (bl_y <= (int)(tile_bin.dim_size(1) - bin_height - 1)) - neighbor_bin_ids.insert(tile_bin[tx][bl_y + bin_height]); + neighbor_bin_ids.insert(density_manager.get_bin(tx, bl_y - 1, 0.0)); + if (bl_y <= (int)(placeable_region_height - bin_height - 1)) + neighbor_bin_ids.insert(density_manager.get_bin(tx, bl_y + bin_height, 0.0)); } // A bin cannot be a neighbor with itself. @@ -343,23 +142,26 @@ static inline vtr::Point get_center_of_rect(vtr::Rect rect) { return rect.bottom_left() + vtr::Point(rect.width() / 2.0, rect.height() / 2.0); } -void FlowBasedLegalizer::compute_neighbors_of_bin(LegalizerBinId src_bin_id, size_t num_models) { +void FlowBasedLegalizer::compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, size_t num_models) { // Make sure that this bin does not already have neighbors. - VTR_ASSERT_DEBUG(bins_[src_bin_id].neighbors.size() == 0); + VTR_ASSERT_DEBUG(bin_neighbors_.size() == 0); // Bins need to be neighbors to every possible molecule type so things can // flow properly. // Perform BFS to find the closest bins of each type. Where closest is in // manhattan distance. + const FlatPlacementBins& flat_placement_bins = density_manager_->flat_placement_bins(); + size_t num_bins = flat_placement_bins.bins().size(); + // Create the queue and insert the source bin into it. - std::queue q; + std::queue q; q.push(src_bin_id); // Create visited flags for each bin. Set the source to visited. - vtr::vector_map bin_visited(bins_.size(), false); + vtr::vector_map bin_visited(num_bins, false); bin_visited[src_bin_id] = true; // Create a distance count for each bin from the src. - vtr::vector_map bin_distance(bins_.size(), 0); + vtr::vector_map bin_distance(num_bins, 0); // Flags to check if a specific model has been found in the given direction. // In this case, direction is the direction of the largest component of the // manhattan distance between the source bin and the target bin. @@ -374,15 +176,16 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(LegalizerBinId src_bin_id, siz bool all_right_found = false; bool all_models_found_in_all_directions = false; // The center of the source bin. - vtr::Point src_bin_center = get_center_of_rect(bins_[src_bin_id].bounding_box); + const vtr::Rect& src_bin_region = flat_placement_bins.bin_region(src_bin_id); + vtr::Point src_bin_center = get_center_of_rect(src_bin_region); // The result will be stored in this set. - std::unordered_set neighbors; + std::unordered_set neighbors; // Helper method to add a neighbor to the set of neighbors and update the // found flags for a given direction if this bin is new for a given model // type. This method returns true if every model has been found in the given // direction (i.e. dir_found is now all true). - auto add_neighbor_if_new_dir = [&](LegalizerBinId target_bin_id, + auto add_neighbor_if_new_dir = [&](FlatPlacementBinId target_bin_id, std::vector& dir_found) { bool all_found = true; // Go through all possible models @@ -391,7 +194,8 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(LegalizerBinId src_bin_id, siz if (dir_found[i]) continue; // If this bin has this model in its capacity, we found a neighbor! - if (bins_[target_bin_id].capacity.get_dim_val(i) > 0) { + const PrimitiveVector& target_bin_capacity = density_manager_->get_bin_capacity(target_bin_id); + if (target_bin_capacity.get_dim_val(i) > 0) { dir_found[i] = true; neighbors.insert(target_bin_id); } else { @@ -403,9 +207,9 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(LegalizerBinId src_bin_id, siz // Perform the BFS from the source node until all nodes have been explored // or all of the models have been found in all directions. - while(!q.empty() && !all_models_found_in_all_directions) { + while (!q.empty() && !all_models_found_in_all_directions) { // Pop the bin from the queue. - LegalizerBinId bin_id = q.front(); + FlatPlacementBinId bin_id = q.front(); q.pop(); // If the distance of this block from the source is too large, do not // explore. @@ -414,14 +218,15 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(LegalizerBinId src_bin_id, siz continue; // Get the direct neighbors of the bin (neighbors that are directly // touching). - auto direct_neighbors = get_direct_neighbors_of_bin(bin_id, bins_, tile_bin_); - for (LegalizerBinId dir_neighbor_bin_id : direct_neighbors) { + auto direct_neighbors = get_direct_neighbors_of_bin(bin_id, *density_manager_); + for (FlatPlacementBinId dir_neighbor_bin_id : direct_neighbors) { // If this neighbor has been visited, do not do anything. if (bin_visited[dir_neighbor_bin_id]) continue; // Get the signed distance from the src bin to the target bin in the // x and y dimensions. - vtr::Point target_bin_center = get_center_of_rect(bins_[dir_neighbor_bin_id].bounding_box); + const vtr::Rect& dir_neighbor_bin_region = flat_placement_bins.bin_region(dir_neighbor_bin_id); + vtr::Point target_bin_center = get_center_of_rect(dir_neighbor_bin_region); double dx = target_bin_center.x() - src_bin_center.x(); double dy = target_bin_center.y() - src_bin_center.y(); // Is the target bin above the source bin? @@ -451,260 +256,45 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(LegalizerBinId src_bin_id, siz q.push(dir_neighbor_bin_id); } // Check if all of the models have been found in all directions. - all_models_found_in_all_directions = all_up_found && all_down_found && - all_left_found && all_right_found; + all_models_found_in_all_directions = all_up_found && all_down_found && all_left_found && all_right_found; } // Assign the results into the neighbors of the bin. - bins_[src_bin_id].neighbors.assign(neighbors.begin(), neighbors.end()); + bin_neighbors_[src_bin_id].assign(neighbors.begin(), neighbors.end()); } -FlowBasedLegalizer::FlowBasedLegalizer(const APNetlist& netlist) - : PartialLegalizer(netlist), - // TODO: Pass the device grid in. - tile_bin_({g_vpr_ctx.device().grid.width(), g_vpr_ctx.device().grid.height()}) { - const DeviceGrid& grid = g_vpr_ctx.device().grid; - size_t grid_width = grid.width(); - size_t grid_height = grid.height(); - - // Pre-compute the capacities of all logical blocks in the device. - // logical_block_type::index -> PrimitiveVector - std::vector logical_block_type_capacities(g_vpr_ctx.device().logical_block_types.size()); - for (const t_logical_block_type& logical_block_type : g_vpr_ctx.device().logical_block_types) { - logical_block_type_capacities[logical_block_type.index] = get_primitive_capacity(logical_block_type); - } - // Pre-compute the capacities of all physical tile types in the device. - // physical_tile_type::index -> PrimitiveVector - std::vector physical_tile_type_capacities(g_vpr_ctx.device().physical_tile_types.size()); - for (const t_physical_tile_type& physical_tile_type : g_vpr_ctx.device().physical_tile_types) { - physical_tile_type_capacities[physical_tile_type.index] = get_primitive_capacity(physical_tile_type, logical_block_type_capacities); - } - // Print these capacities. Helpful for debugging. - if (log_verbosity_ > 1) { - print_capacities(logical_block_type_capacities, - physical_tile_type_capacities, - g_vpr_ctx.device().logical_block_types, - g_vpr_ctx.device().physical_tile_types); - } - // Create the bins - // This currently creates 1 bin per tile. - for (size_t x = 0; x < grid_width; x++) { - for (size_t y = 0; y < grid_height; y++) { - // Ignoring 3D placement for now. - t_physical_tile_loc tile_loc = {(int)x, (int)y, 0}; - // Is this the root location? Only create bins for roots. - size_t width_offset = grid.get_width_offset(tile_loc); - size_t height_offset = grid.get_height_offset(tile_loc); - if (width_offset != 0 || height_offset != 0) { - // If this is not a root, point the tile_bin_ lookup to the root - // tile location. - tile_bin_[x][y] = tile_bin_[x - width_offset][y - height_offset]; - continue; - } - // Create the bin - LegalizerBinId new_bin_id = LegalizerBinId(bins_.size()); - LegalizerBin new_bin; - // NOTE: The bounding box from the tile does not make sense in this - // context, making my own here based on the tile size and - // position. - t_physical_tile_type_ptr tile_type = grid.get_physical_type(tile_loc); - int width = tile_type->width; - int height = tile_type->height; - new_bin.bounding_box = vtr::Rect(vtr::Point(x, y), - vtr::Point(x + width, - y + height)); - // The capacity of the bin is the capacity of the tile it represents. - new_bin.capacity = physical_tile_type_capacities[tile_type->index]; - bins_.push_back(std::move(new_bin)); - tile_bin_[x][y] = new_bin_id; - } - } +FlowBasedLegalizer::FlowBasedLegalizer(const APNetlist& netlist, + std::shared_ptr density_manager, + int log_verbosity) + : PartialLegalizer(netlist, log_verbosity) + , density_manager_(density_manager) + , bin_neighbors_(density_manager_->flat_placement_bins().bins().size()) { - // Get the number of models in the device. - size_t num_models = get_num_models(); // Connect the bins. - // TODO: Should create a list of bin IDs to make this more efficient. - for (size_t x = 0; x < grid_width; x++) { - for (size_t y = 0; y < grid_height; y++) { - // Ignoring 3D placement for now. Will likely require modification to - // the solver and legalizer. - t_physical_tile_loc tile_loc = {(int)x, (int)y, 0}; - // Is this the root location? - if (grid.get_width_offset(tile_loc) != 0 || - grid.get_height_offset(tile_loc) != 0) { - continue; - } - // Compute the neighbors of this bin. - compute_neighbors_of_bin(tile_bin_[x][y], num_models); - } - } - - // Pre-compute the masses of the APBlocks - VTR_LOGV(log_verbosity_ >= 10, "Pre-computing the block masses...\n"); - for (APBlockId blk_id : netlist.blocks()) { - block_masses_.insert(blk_id, get_primitive_mass(blk_id, netlist)); + size_t num_models = get_num_models(); + for (FlatPlacementBinId bin_id : density_manager_->flat_placement_bins().bins()) { + compute_neighbors_of_bin(bin_id, num_models); } - VTR_LOGV(log_verbosity_ >= 10, "Finished pre-computing the block masses.\n"); - - // Initialize the block_bins. - block_bins_.resize(netlist.blocks().size(), LegalizerBinId::INVALID()); } -bool FlowBasedLegalizer::verify_bins() const { - // Make sure that every block has a bin. - for (APBlockId blk_id : netlist_.blocks()) { - if (!block_bins_[blk_id].is_valid()) { - VTR_LOG("Bin Verify: Found a block that is not in a bin.\n"); - return false; - } - } - // Make sure that every tile has a bin. - const DeviceGrid& device_grid = g_vpr_ctx.device().grid; - if (tile_bin_.dim_size(0) != device_grid.width() || - tile_bin_.dim_size(1) != device_grid.height()) { - VTR_LOG("Bin Verify: Tile-bin lookup does not contain every tile.\n"); - return false; - } - for (size_t x = 0; x < device_grid.width(); x++) { - for (size_t y = 0; y < device_grid.height(); y++) { - if (!tile_bin_[x][y].is_valid()) { - VTR_LOG("Bin Verify: Found a tile with no bin.\n"); - return false; - } - } +bool FlowBasedLegalizer::verify() const { + if (density_manager_->verify() == false) { + VTR_LOG("Flow-Based Legalizer Verify: Density Manager failed verification.\n"); } - // Make sure that every bin has the correct utilization, supply, and demand. - for (const LegalizerBin& bin : bins_) { - PrimitiveVector calc_utilization; - for (APBlockId blk_id : bin.contained_blocks) { - calc_utilization += block_masses_[blk_id]; - } - if (bin.utilization != calc_utilization) { - VTR_LOG("Bin Verify: Found a bin with incorrect utilization.\n"); - return false; - } - PrimitiveVector calc_supply = bin.utilization - bin.capacity; - calc_supply.relu(); - if (bin.supply != calc_supply) { - VTR_LOG("Bin Verify: Found a bin with incorrect supply.\n"); - return false; - } - PrimitiveVector calc_demand = bin.capacity - bin.utilization; - calc_demand.relu(); - if (bin.demand != calc_demand) { - VTR_LOG("Bin Verify: Found a bin with incorrect demand.\n"); - return false; - } - if (!bin.supply.is_non_negative()) { - VTR_LOG("Bin Verify: Found a bin with a negative supply.\n"); - return false; - } - if (!bin.demand.is_non_negative()) { - VTR_LOG("Bin Verify: Found a bin with a negative demand.\n"); - return false; - } - if (!bin.capacity.is_non_negative()) { - VTR_LOG("Bin Verify: Found a bin with a negative capacity.\n"); - return false; - } - if (!bin.utilization.is_non_negative()) { - VTR_LOG("Bin Verify: Found a bin with a negative utilization.\n"); - return false; - } - if (bin.neighbors.size() == 0) { - VTR_LOG("Bin Verify: Found a bin with no neighbors.\n"); - return false; - } - } - // Make sure all overfilled bins are actually overfilled. - // TODO: Need to make sure that all non-overfilled bins are actually not - // overfilled. - for (LegalizerBinId bin_id : overfilled_bins_) { - const LegalizerBin& bin = bins_[bin_id]; - if (bin.supply.is_zero()) { - VTR_LOG("Bin Verify: Found an overfilled bin that was not overfilled.\n"); + // Make sure that the bins are connected correctly. + for (FlatPlacementBinId bin_id : density_manager_->flat_placement_bins().bins()) { + if (bin_neighbors_[bin_id].empty()) { + VTR_LOG("Flow-Based Legalizer Verify: Found a bin with no neighbors.\n"); return false; } + // TODO: Should verify more about the connectivity. Such as every bin + // has a neighbor of each model type and a path exists from every + // bin to every other bin. } // If all above passed, then the bins are valid. return true; } -void FlowBasedLegalizer::reset_bins() { - // Reset all of the bins by removing all of the contained blocks. - for (LegalizerBin& bin : bins_) { - bin.contained_blocks.clear(); - bin.utilization = PrimitiveVector(); - bin.compute_supply(); - bin.compute_demand(); - } - // Reset the reverse lookup of block_bins_ - std::fill(block_bins_.begin(), block_bins_.end(), LegalizerBinId::INVALID()); - // No bin can be overfilled right now. - overfilled_bins_.clear(); -} - -void FlowBasedLegalizer::import_placement_into_bins(const PartialPlacement& p_placement) { - // TODO: Maybe import the fixed block locations in the constructor and - // then only import the moveable block locations. - for (APBlockId blk_id : netlist_.blocks()) { - size_t x_loc = p_placement.block_x_locs[blk_id]; - size_t y_loc = p_placement.block_y_locs[blk_id]; - LegalizerBinId bin_id = get_bin(x_loc, y_loc); - insert_blk_into_bin(blk_id, bin_id); - } -} - -/** - * @brief Get the location of a block assuming that it is placed within the - * given bin. - * - * This function will return the position of the block in the point within the - * bin's bounding box which is closest to the original position of the block - * (the position in p_placement). - */ -static inline vtr::Point get_block_location_in_bin(APBlockId blk_id, - const LegalizerBin& bin, - const PartialPlacement& p_placement) { - // A block cannot be placed on the right or top sides of the bounding box - // of a bin; however they can be infinitely close to these sides. It is - // arbitrary how close to the edge we place the blocks; opted to place them - // as close as possible. - double epsilon = 0.0001; - double x = std::clamp(p_placement.block_x_locs[blk_id], - bin.bounding_box.bottom_left().x(), - bin.bounding_box.top_right().x() - epsilon); - double y = std::clamp(p_placement.block_y_locs[blk_id], - bin.bounding_box.bottom_left().y(), - bin.bounding_box.top_right().y() - epsilon); - return vtr::Point(x, y); -} - -void FlowBasedLegalizer::export_placement_from_bins(PartialPlacement& p_placement) const { - // Updates the partial placement with the location of the blocks in the bin - // by moving the blocks to the point within the bin closest to where they - // were originally. - // TODO: This should be investigated more. This may put blocks onto the edges - // of bins which may not be ideal. - for (APBlockId blk_id : netlist_.blocks()) { - // Only the moveable block locations should be exported. - if (netlist_.block_mobility(blk_id) == APBlockMobility::FIXED) - continue; - // Project the coordinate of the block in the partial placement to the - // closest point in the bin. - LegalizerBinId bin_id = block_bins_[blk_id]; - VTR_ASSERT_DEBUG(bin_id.is_valid()); - const LegalizerBin& bin = bins_[bin_id]; - // Set the position of the block to the closest position in the bin to - // where the block was. - vtr::Point new_blk_pos = get_block_location_in_bin(blk_id, - bin, - p_placement); - p_placement.block_x_locs[blk_id] = new_blk_pos.x(); - p_placement.block_y_locs[blk_id] = new_blk_pos.y(); - } -} - // Helper method to compute the phi term in the durav algorithm. static inline float computeMaxMovement(size_t iter) { return 100 * (iter + 1) * (iter + 1); @@ -719,40 +309,44 @@ static inline float computeMaxMovement(size_t iter) { * * @param src_bin The bin that contains the blocks to move. * @param target_bin The bin to move blocks to. - * @param block_masses A lookup for the masses of all blocks. * @param p_placement The placement of the blocks prior to legalization. * @param netlist The APNetlist for the placement. + * @param density_manager The density manager for this partial legalizer. * * @return A pair of the minimum cost moveable block and its cost. */ static inline std::pair get_min_cost_block_in_bin( - const LegalizerBin& src_bin, - const LegalizerBin& target_bin, - const vtr::vector_map& block_masses, - const PartialPlacement& p_placement, - const APNetlist& netlist) { + FlatPlacementBinId src_bin, + FlatPlacementBinId target_bin, + const PartialPlacement& p_placement, + const APNetlist& netlist, + const FlatPlacementDensityManager& density_manager) { // Get the min cost block and its cost. APBlockId min_cost_block; float min_cost = std::numeric_limits::infinity(); + const FlatPlacementBins& bins = density_manager.flat_placement_bins(); + const FlatPlacementMassCalculator& mass_calculator = density_manager.mass_calculator(); + const std::unordered_set& src_contained_blocks = bins.bin_contained_blocks(src_bin); // FIXME: If these were somehow pre-sorted, this can be made much cheaper. - for (APBlockId blk_id : src_bin.contained_blocks) { + for (APBlockId blk_id : src_contained_blocks) { // If this block is fixed, it has infinite cost to move. if (netlist.block_mobility(blk_id) == APBlockMobility::FIXED) continue; - const PrimitiveVector& block_mass = block_masses[blk_id]; + const PrimitiveVector& block_mass = mass_calculator.get_block_mass(blk_id); // Is this block compatible with the target bin? // If the capacity of the target, projected onto the mass, is less than // the mass, then the block is not compatible. // TODO: We may want to add a cost term based on how much space is // available in the bin? - PrimitiveVector target_capacity = target_bin.capacity; + PrimitiveVector target_capacity = density_manager.get_bin_capacity(target_bin); target_capacity.project(block_mass); if (target_capacity < block_mass) continue; // Compute the quadratic movement (aka cost). - vtr::Point new_block_pos = get_block_location_in_bin(blk_id, - target_bin, - p_placement); + const vtr::Rect& target_bin_region = bins.bin_region(target_bin); + const vtr::Point& new_block_pos = density_manager.get_block_location_in_bin(blk_id, + target_bin_region, + p_placement); double dx = new_block_pos.x() - p_placement.block_x_locs[blk_id]; double dy = new_block_pos.y() - p_placement.block_y_locs[blk_id]; float cost = (dx * dx) + (dy * dy); @@ -777,18 +371,18 @@ static inline std::pair get_min_cost_block_in_bin( * @param psi Algorithm parameter which represents the maximum * cost this function can return. This function will * return inf if the cost is larger than psi. - * @param block_masses A lookup for the masses of all blocks. * @param p_placement The placement of the blocks prior to legalization. * @param netlist The APNetlist for the placement. + * @param density_manager The density manager for this partial legalizer. */ -static inline float compute_cost(const LegalizerBin& src_bin, - const LegalizerBin& target_bin, +static inline float compute_cost(FlatPlacementBinId src_bin, + FlatPlacementBinId target_bin, float psi, - const vtr::vector_map& block_masses, const PartialPlacement& p_placement, - const APNetlist& netlist) { + const APNetlist& netlist, + const FlatPlacementDensityManager& density_manager) { // If the src bin is empty, then there is nothing to move. - if (src_bin.contained_blocks.size() == 0) + if (density_manager.flat_placement_bins().bin_contained_blocks(src_bin).size() == 0) return std::numeric_limits::infinity(); // Get the min cost block in the src bin which is compatible with the target // bin. @@ -796,9 +390,9 @@ static inline float compute_cost(const LegalizerBin& src_bin, float min_cost; std::tie(min_cost_block, min_cost) = get_min_cost_block_in_bin(src_bin, target_bin, - block_masses, p_placement, - netlist); + netlist, + density_manager); // If no block can be moved to the target bin, return. if (std::isinf(min_cost)) return std::numeric_limits::infinity(); @@ -810,59 +404,64 @@ static inline float compute_cost(const LegalizerBin& src_bin, // This weight tries to keep blocks of the same type together. // This term can be found by taking the L1 norm of the projection of the // src bin's utilization on the direction of the mass. - PrimitiveVector weight_vec = src_bin.utilization; - weight_vec.project(block_masses[min_cost_block]); + const FlatPlacementMassCalculator& mass_calculator = density_manager.mass_calculator(); + const PrimitiveVector& min_cost_block_mass = mass_calculator.get_block_mass(min_cost_block); + PrimitiveVector weight_vec = density_manager.get_bin_utilization(src_bin); + weight_vec.project(min_cost_block_mass); float weight = weight_vec.manhattan_norm(); // Return the overall cost which is the quadratic movement times the weight. return weight * min_cost; } -std::vector> FlowBasedLegalizer::get_paths(LegalizerBinId src_bin_id, - const PartialPlacement& p_placement, - float psi) { +std::vector> FlowBasedLegalizer::get_paths( + FlatPlacementBinId src_bin_id, + const PartialPlacement& p_placement, + float psi) { VTR_LOGV(log_verbosity_ >= 20, "\tGetting paths...\n"); + const FlatPlacementBins& flat_placement_bins = density_manager_->flat_placement_bins(); + size_t num_bins = flat_placement_bins.bins().size(); // Create a visited vector. - vtr::vector_map bin_visited(bins_.size(), false); + vtr::vector_map bin_visited(num_bins, false); bin_visited[src_bin_id] = true; // Create a cost array. The cost of a path is equal to the cost of its tail // bin. - vtr::vector_map bin_cost(bins_.size(), 0.f); + vtr::vector_map bin_cost(num_bins, 0.f); // Create a starting path. - std::vector starting_path; + std::vector starting_path; starting_path.push_back(src_bin_id); // Create a FIFO queue. - std::queue> queue; + std::queue> queue; queue.push(std::move(starting_path)); // Create the resulting vector of paths. // TODO: Can we store this more efficiently as a tree? - std::vector> paths; + std::vector> paths; // Perform the BFS to search for direct paths to flow the starting bin's // supply of primitives until it has found sufficient demand. PrimitiveVector demand; - const PrimitiveVector& starting_bin_supply = bins_[src_bin_id].supply; + const PrimitiveVector& starting_bin_supply = get_bin_supply(src_bin_id); while (!queue.empty() && demand < starting_bin_supply) { // Pop the current bin off the queue. - std::vector &p = queue.front(); - LegalizerBinId tail_bin_id = p.back(); + std::vector& p = queue.front(); + FlatPlacementBinId tail_bin_id = p.back(); // Look over its neighbors - for (LegalizerBinId neighbor_bin_id : bins_[tail_bin_id].neighbors) { + for (FlatPlacementBinId neighbor_bin_id : bin_neighbors_[tail_bin_id]) { // If this bin has already been visited, skip it. if (bin_visited[neighbor_bin_id]) continue; // Compute the cost of moving a block from the tail bin to its // neighbor. - float cost = compute_cost(bins_[tail_bin_id], - bins_[neighbor_bin_id], + float cost = compute_cost(tail_bin_id, + neighbor_bin_id, psi, - block_masses_, p_placement, - netlist_); + netlist_, + *density_manager_); // If the cost is infinite, then the path cannot be made to this // neighbor bin. if (std::isinf(cost)) continue; // Else, a path can be made. - std::vector p_copy(p); + std::vector p_copy(p); bin_cost[neighbor_bin_id] = bin_cost[tail_bin_id] + cost; p_copy.push_back(neighbor_bin_id); bin_visited[neighbor_bin_id] = true; @@ -879,7 +478,7 @@ std::vector> FlowBasedLegalizer::get_paths(Legalizer // investigated further... // FIXME: Perhaps we do not check if it is empty, but check if the // demand is sufficiently large... - PrimitiveVector neighbor_demand = bins_[neighbor_bin_id].demand; + PrimitiveVector neighbor_demand = get_bin_demand(neighbor_bin_id); neighbor_demand.project(starting_bin_supply); VTR_ASSERT_DEBUG(neighbor_demand.is_non_negative()); // if (bins_[neighbor_bin_id].contained_blocks.size() == 0) { @@ -900,39 +499,38 @@ std::vector> FlowBasedLegalizer::get_paths(Legalizer // Helpful debug messages. VTR_LOGV(log_verbosity_ >= 20, "\t\tSupply of source bin: %.2f\n", - starting_bin_supply.manhattan_norm()); + starting_bin_supply.manhattan_norm()); VTR_LOGV(log_verbosity_ >= 20, "\t\tDemand of all paths from source: %.2f\n", - starting_bin_supply.manhattan_norm()); + starting_bin_supply.manhattan_norm()); // Sort the paths in increasing order of cost. - std::sort(paths.begin(), paths.end(), [&](const std::vector& a, - const std::vector& b) { + std::sort(paths.begin(), paths.end(), [&](const std::vector& a, const std::vector& b) { return bin_cost[a.back()] < bin_cost[b.back()]; }); return paths; } -void FlowBasedLegalizer::flow_blocks_along_path(const std::vector& path, +void FlowBasedLegalizer::flow_blocks_along_path(const std::vector& path, const PartialPlacement& p_placement, float psi) { // Get the root bin of the path. VTR_ASSERT(!path.empty()); - LegalizerBinId src_bin_id = path[0]; + FlatPlacementBinId src_bin_id = path[0]; // Create a stack and put the src bin on top. - std::stack s; + std::stack s; s.push(src_bin_id); // Insert the bins in the path into the stack in reverse order (so the last // bin in the path is on top of the stack). size_t path_size = path.size(); for (size_t path_idx = 1; path_idx < path_size; path_idx++) { - LegalizerBinId sink_bin_id = path[path_idx]; + FlatPlacementBinId sink_bin_id = path[path_idx]; // Check that the cost of moving a block from the source bin to the sink // bin is non-infinite. According to the paper, this check is needed // since a previous flow on another path may have made this path not // necessary anymore. - float cost = compute_cost(bins_[src_bin_id], bins_[sink_bin_id], psi, - block_masses_, p_placement, netlist_); + float cost = compute_cost(src_bin_id, sink_bin_id, psi, + p_placement, netlist_, *density_manager_); if (std::isinf(cost)) return; src_bin_id = sink_bin_id; @@ -940,7 +538,7 @@ void FlowBasedLegalizer::flow_blocks_along_path(const std::vector p = get_min_cost_block_in_bin(bins_[src_bin_id], - bins_[sink_bin_id], - block_masses_, + std::pair p = get_min_cost_block_in_bin(src_bin_id, + sink_bin_id, p_placement, - netlist_); + netlist_, + *density_manager_); // Move the block from the src bin to the sink bin. - remove_blk_from_bin(p.first, src_bin_id); - insert_blk_into_bin(p.first, sink_bin_id); + density_manager_->remove_block_from_bin(p.first, src_bin_id); + density_manager_->insert_block_into_bin(p.first, sink_bin_id); sink_bin_id = src_bin_id; } @@ -999,38 +597,18 @@ static void print_flow_based_legalizer_status(size_t iteration, fflush(stdout); } -/** - * @brief Debug method to print the current number of blocks contained in each - * bin visually. - * - * This method helps to see how the spreading is working. - */ -static void print_flow_based_bin_grid(const vtr::NdMatrix& tile_bin, - const vtr::vector_map& bins) { - for (size_t y = 0; y < tile_bin.dim_size(1); y++) { - for (size_t x = 0; x < tile_bin.dim_size(0); x++) { - const LegalizerBin& bin = bins[tile_bin[x][y]]; - VTR_LOG("%3zu ", bin.contained_blocks.size()); - } - VTR_LOG("\n"); - } - VTR_LOG("\n"); -} - -void FlowBasedLegalizer::legalize(PartialPlacement &p_placement) { +void FlowBasedLegalizer::legalize(PartialPlacement& p_placement) { VTR_LOGV(log_verbosity_ >= 10, "Running Flow-Based Legalizer\n"); - // Reset the bins from the previous iteration and prepare for this iteration. - reset_bins(); // Import the partial placement into bins. - import_placement_into_bins(p_placement); + density_manager_->import_placement_into_bins(p_placement); // Verify that the placement was imported correctly. - VTR_ASSERT_SAFE(verify_bins()); + VTR_ASSERT_SAFE(density_manager_->verify()); // Print the number of blocks in each bin visually before spreading. if (log_verbosity_ >= 15) { VTR_LOG("Bin utilization prior to spreading:\n"); - print_flow_based_bin_grid(tile_bin_, bins_); + density_manager_->print_bin_grid(); } // Print the status header to make printing the status clearer. @@ -1048,7 +626,8 @@ void FlowBasedLegalizer::legalize(PartialPlacement &p_placement) { break; } // If there are no overfilled bins, no more work to do. - if (overfilled_bins_.empty()) { + const std::unordered_set& overfilled_bins = density_manager_->get_overfilled_bins(); + if (overfilled_bins.empty()) { VTR_LOGV(log_verbosity_ >= 10, "Flow-Based legalizer has no overfilled tiles. No further spreading needed.\n"); break; @@ -1063,28 +642,28 @@ void FlowBasedLegalizer::legalize(PartialPlacement &p_placement) { // NOTE: Although the supply should always be non-negative, we still // take the absolute value in the norm for completeness. // TODO: This is a guess. Should investigate other norms. - std::vector overfilled_bins_vec(overfilled_bins_.begin(), overfilled_bins_.end()); - std::sort(overfilled_bins_vec.begin(), overfilled_bins_vec.end(), [&](LegalizerBinId a, LegalizerBinId b) { - return bins_[a].supply.manhattan_norm() < bins_[b].supply.manhattan_norm(); + std::vector overfilled_bins_vec(overfilled_bins.begin(), overfilled_bins.end()); + std::sort(overfilled_bins_vec.begin(), overfilled_bins_vec.end(), [&](FlatPlacementBinId a, FlatPlacementBinId b) { + return get_bin_supply(a).manhattan_norm() < get_bin_supply(b).manhattan_norm(); }); // Get the paths to flow blocks from the overfilled bins to the under // filled bins and flow the blocks. - for (LegalizerBinId src_bin_id : overfilled_bins_vec) { + for (FlatPlacementBinId src_bin_id : overfilled_bins_vec) { // Get the list of candidate paths based on psi. A path is a list // of LegalizerBins traversed. // NOTE: The paths are sorted by increasing cost within the // getPaths method. - std::vector> paths = get_paths(src_bin_id, - p_placement, - psi); + std::vector> paths = get_paths(src_bin_id, + p_placement, + psi); VTR_LOGV(log_verbosity_ >= 20, "\tNum paths: %zu\n", paths.size()); // For each path, flow the blocks along the path. - for (const std::vector& path : paths) { + for (const std::vector& path : paths) { VTR_LOGV(log_verbosity_ >= 30, "\t\tPath length: %zu\n", path.size()); // If the bin is no longer overfilled, no need to move any more // blocks along the paths. - if (!bin_is_overfilled(src_bin_id)) + if (!density_manager_->bin_is_overfilled(src_bin_id)) break; // Move blocks over the paths. // NOTE: This will only modify the bins. (actual block @@ -1097,10 +676,10 @@ void FlowBasedLegalizer::legalize(PartialPlacement &p_placement) { if (log_verbosity_ >= 10) { // TODO: Get the total cell displacement for debugging. print_flow_based_legalizer_status( - flowBasedIter, - overfilled_bins_vec.size(), - bins_[overfilled_bins_vec.back()].supply.manhattan_norm(), - psi); + flowBasedIter, + overfilled_bins_vec.size(), + get_bin_supply(overfilled_bins_vec.back()).manhattan_norm(), + psi); } // Increment the iteration. @@ -1111,15 +690,853 @@ void FlowBasedLegalizer::legalize(PartialPlacement &p_placement) { flowBasedIter + 1); // Verify that the bins are valid before export. - VTR_ASSERT(verify_bins()); + VTR_ASSERT(verify()); // Print the number of blocks in each bin after spreading. if (log_verbosity_ >= 15) { VTR_LOG("Bin utilization after spreading:\n"); - print_flow_based_bin_grid(tile_bin_, bins_); + density_manager_->print_bin_grid(); + } + + // Export the legalized placement to the partial placement. + density_manager_->export_placement_from_bins(p_placement); +} + +PerModelPrefixSum2D::PerModelPrefixSum2D(const FlatPlacementDensityManager& density_manager, + t_model* user_models, + t_model* library_models, + std::function lookup) { + // Get the number of models in the architecture. + // TODO: We really need to clean up how models are stored in VPR... + t_model* cur = user_models; + int num_models = 0; + while (cur != nullptr) { + num_models++; + cur = cur->next; + } + cur = library_models; + while (cur != nullptr) { + num_models++; + cur = cur->next; + } + + // Get the size that the prefix sums should be. + size_t width, height, layers; + std::tie(width, height, layers) = density_manager.get_overall_placeable_region_size(); + + // Create each of the prefix sums. + model_prefix_sum_.resize(num_models); + for (int model_index = 0; model_index < num_models; model_index++) { + model_prefix_sum_[model_index] = vtr::PrefixSum2D( + width, + height, + [&](size_t x, size_t y) { + return lookup(model_index, x, y); + }); + } +} + +float PerModelPrefixSum2D::get_model_sum(int model_index, + const vtr::Rect& region) const { + VTR_ASSERT_SAFE(model_index < (int)model_prefix_sum_.size() && model_index >= 0); + // Get the sum over the given region. + return model_prefix_sum_[model_index].get_sum(region.xmin(), + region.ymin(), + region.xmax() - 1, + region.ymax() - 1); +} + +PrimitiveVector PerModelPrefixSum2D::get_sum(const std::vector& model_indices, + const vtr::Rect& region) const { + PrimitiveVector res; + for (int model_index : model_indices) { + VTR_ASSERT_SAFE(res.get_dim_val(model_index) == 0.0f); + res.set_dim_val(model_index, get_model_sum(model_index, region)); + } + return res; +} + +BiPartitioningPartialLegalizer::BiPartitioningPartialLegalizer( + const APNetlist& netlist, + std::shared_ptr density_manager, + const Prepacker& prepacker, + int log_verbosity) + : PartialLegalizer(netlist, log_verbosity) + , density_manager_(density_manager) + , model_grouper_(prepacker, + g_vpr_ctx.device().arch->models, + g_vpr_ctx.device().arch->model_library, + log_verbosity) { + // Compute the capacity prefix sum. Capacity is assumed to not change + // between iterations of the partial legalizer. + capacity_prefix_sum_ = PerModelPrefixSum2D( + *density_manager, + g_vpr_ctx.device().arch->models, + g_vpr_ctx.device().arch->model_library, + [&](int model_index, size_t x, size_t y) { + // Get the bin at this grid location. + FlatPlacementBinId bin_id = density_manager_->get_bin(x, y, 0); + // Get the capacity of the bin for this model. + float cap = density_manager_->get_bin_capacity(bin_id).get_dim_val(model_index); + VTR_ASSERT_SAFE(cap >= 0.0f); + // Bins may be large, but the prefix sum assumes a 1x1 grid of + // values. Normalize by the area of the bin to turn this into + // a 1x1 bin equivalent. + const vtr::Rect& bin_region = density_manager_->flat_placement_bins().bin_region(bin_id); + float bin_area = bin_region.width() * bin_region.height(); + VTR_ASSERT_SAFE(!vtr::isclose(bin_area, 0.f)); + return cap / bin_area; + }); + + num_windows_partitioned_ = 0; + num_blocks_partitioned_ = 0; +} + +void BiPartitioningPartialLegalizer::print_statistics() { + VTR_LOG("Bi-Partitioning Partial Legalizer Statistics:\n"); + VTR_LOG("\tTotal number of windows partitioned: %u\n", num_windows_partitioned_); + VTR_LOG("\tTotal number of blocks partitioned: %u\n", num_blocks_partitioned_); +} + +void BiPartitioningPartialLegalizer::legalize(PartialPlacement& p_placement) { + VTR_LOGV(log_verbosity_ >= 10, "Running Bi-Partitioning Legalizer\n"); + + // Prepare the density manager. + density_manager_->import_placement_into_bins(p_placement); + + // Quick return. If there are no overfilled bins, there is nothing to spread. + if (density_manager_->get_overfilled_bins().size() == 0) { + VTR_LOGV(log_verbosity_ >= 10, "No overfilled bins. Nothing to legalize.\n"); + return; + } + + if (log_verbosity_ >= 10) { + size_t num_overfilled_bins = density_manager_->get_overfilled_bins().size(); + VTR_LOG("\tNumber of overfilled blocks before legalization: %zu\n", + num_overfilled_bins); + // FIXME: Make this a method in the density manager class. + float avg_overfill = 0.f; + for (FlatPlacementBinId overfilled_bin_id : density_manager_->get_overfilled_bins()) { + avg_overfill += density_manager_->get_bin_overfill(overfilled_bin_id).manhattan_norm(); + } + VTR_LOG("\t\tAverage overfill per overfilled bin: %f\n", + avg_overfill / static_cast(num_overfilled_bins)); + } + + // 1) Identify the groups that need to be spread + std::unordered_set groups_to_spread; + for (FlatPlacementBinId overfilled_bin_id : density_manager_->get_overfilled_bins()) { + // Get the overfilled models in this bin. + const PrimitiveVector& overfill = density_manager_->get_bin_overfill(overfilled_bin_id); + std::vector overfilled_models = overfill.get_non_zero_dims(); + // For each model, insert its group into the set. Set will handle dupes. + for (int model_index : overfilled_models) { + groups_to_spread.insert(model_grouper_.get_model_group_id(model_index)); + } + } + + // 2) For each group, identify non-overlapping windows and spread + vtr::Timer runtime_timer; + float window_identification_time = 0.0f; + float window_spreading_time = 0.0f; + for (ModelGroupId group_id : groups_to_spread) { + VTR_LOGV(log_verbosity_ >= 10, "\tSpreading group %zu\n", group_id); + // Identify non-overlapping spreading windows. + float window_identification_start_time = runtime_timer.elapsed_sec(); + auto non_overlapping_windows = identify_non_overlapping_windows(group_id); + window_identification_time += runtime_timer.elapsed_sec() - window_identification_start_time; + VTR_ASSERT(non_overlapping_windows.size() != 0); + + // Spread the blocks over the non-overlapping windows. + float window_spreading_start_time = runtime_timer.elapsed_sec(); + spread_over_windows(non_overlapping_windows, p_placement, group_id); + window_spreading_time += runtime_timer.elapsed_sec() - window_spreading_start_time; + } + + // FIXME: Remove this duplicate code... + if (log_verbosity_ >= 10) { + size_t num_overfilled_bins = density_manager_->get_overfilled_bins().size(); + VTR_LOG("\tNumber of overfilled blocks after legalization: %zu\n", + num_overfilled_bins); + // FIXME: Make this a method in the density manager class. + float avg_overfill = 0.f; + for (FlatPlacementBinId overfilled_bin_id : density_manager_->get_overfilled_bins()) { + avg_overfill += density_manager_->get_bin_overfill(overfilled_bin_id).manhattan_norm(); + } + VTR_LOG("\t\tAverage overfill per overfilled bin: %f\n", + avg_overfill / static_cast(num_overfilled_bins)); + VTR_LOG("\tTime spent identifying windows: %g\n", window_identification_time); + VTR_LOG("\tTime spent spreading windows: %g\n", window_spreading_time); } // Export the legalized placement to the partial placement. - export_placement_from_bins(p_placement); + density_manager_->export_placement_from_bins(p_placement); +} + +std::vector BiPartitioningPartialLegalizer::identify_non_overlapping_windows(ModelGroupId group_id) { + + // 1) Cluster the overfilled bins. This will make creating minimum spanning + // windows more efficient. + auto overfilled_bin_clusters = get_overfilled_bin_clusters(group_id); + + // 2) For each of the overfilled bin clusters, create a minimum window such + // that there is enough space in the window for the atoms inside. + auto windows = get_min_windows_around_clusters(overfilled_bin_clusters, group_id); + + // 3) Merge overlapping windows. + merge_overlapping_windows(windows); + + // TODO: Investigate shrinking the windows. + + // 4) Move the blocks out of their bins and into the windows. + move_blocks_into_windows(windows, group_id); + + return windows; +} + +/** + * @brief Helper method to check if the given PrimitiveVector has any values + * in the model dimensions in the given group. + * + * This method assumes the vector is non-negative. If the vector had any negative + * dimensions, it does not make sense to ask if it is in the group or not. + */ +static bool is_vector_in_group(const PrimitiveVector& vec, + ModelGroupId group_id, + const ModelGrouper& model_grouper) { + VTR_ASSERT_SAFE(vec.is_non_negative()); + const std::vector& models_in_group = model_grouper.get_models_in_group(group_id); + for (int model_index : models_in_group) { + float dim_val = vec.get_dim_val(model_index); + if (dim_val != 0.0f) + return true; + } + return false; +} + +/** + * @brief Checks if the overfilled models in the given overfilled bin is in the + * given model group. + * + * This method does not check if the bin could be in the given group (for + * example the capacity), this checks if the overfilled blocks are in the group. + */ +static bool is_overfilled_bin_in_group(FlatPlacementBinId overfilled_bin_id, + ModelGroupId group_id, + const FlatPlacementDensityManager& density_manager, + const ModelGrouper& model_grouper) { + const PrimitiveVector& bin_overfill = density_manager.get_bin_overfill(overfilled_bin_id); + VTR_ASSERT_SAFE(bin_overfill.is_non_zero()); + return is_vector_in_group(bin_overfill, group_id, model_grouper); +} + +/** + * @brief Checks if the given AP block is in the given model group. + * + * An AP block is in a model group if it contains any models in the model group. + */ +static bool is_block_in_group(APBlockId blk_id, + ModelGroupId group_id, + const FlatPlacementDensityManager& density_manager, + const ModelGrouper& model_grouper) { + const PrimitiveVector& blk_mass = density_manager.mass_calculator().get_block_mass(blk_id); + return is_vector_in_group(blk_mass, group_id, model_grouper); } +std::vector BiPartitioningPartialLegalizer::get_overfilled_bin_clusters( + ModelGroupId group_id) { + // Use BFS over the overfilled bins to cluster them. + std::vector overfilled_bin_clusters; + // Maintain the distance from the last overfilled bin + vtr::vector dist(density_manager_->flat_placement_bins().bins().size(), -1); + for (FlatPlacementBinId overfilled_bin_id : density_manager_->get_overfilled_bins()) { + // If this bin is not overfilled with the models in the group, skip. + if (!is_overfilled_bin_in_group(overfilled_bin_id, + group_id, + *density_manager_, + model_grouper_)) { + continue; + } + // If this bin is already in a cluster, skip. + if (dist[overfilled_bin_id] != -1) + continue; + dist[overfilled_bin_id] = 0; + // Collect nearby bins into a vector. + FlatPlacementBinCluster nearby_bins; + nearby_bins.push_back(overfilled_bin_id); + // Create a queue and insert the overfilled bin into it. + std::queue bin_queue; + bin_queue.push(overfilled_bin_id); + while (!bin_queue.empty()) { + // Pop a bin from queue. + FlatPlacementBinId bin_node = bin_queue.front(); + bin_queue.pop(); + // If the node's distance from an overfilled bin is the max gap, + // do not explore its neighbors. + if (dist[bin_node] > max_bin_cluster_gap_) + continue; + // Explore the neighbors of this bin. + for (FlatPlacementBinId neighbor : get_direct_neighbors_of_bin(bin_node, *density_manager_)) { + int neighbor_dist = dist[bin_node] + 1; + // If this neighbor has been explore with a better distance, + // do not explore it. + if (dist[neighbor] != -1 && dist[neighbor] <= neighbor_dist) + continue; + // If the neighbor is an overfilled bin that we care about, add + // it to the list of nearby bins and set its distance to 0. + if (density_manager_->bin_is_overfilled(neighbor) + && is_overfilled_bin_in_group(neighbor, group_id, *density_manager_, model_grouper_)) { + nearby_bins.push_back(neighbor); + dist[neighbor] = 0; + } else { + dist[neighbor] = neighbor_dist; + } + // Enqueue the neighbor. + bin_queue.push(neighbor); + } + } + + // Move the cluster into the vector of overfilled bin clusters. + overfilled_bin_clusters.push_back(std::move(nearby_bins)); + } + + return overfilled_bin_clusters; +} + +/** + * @brief Helper method to decide if the given region's utilization is higher + * than its capacity. + */ +static bool is_region_overfilled(const vtr::Rect& region, + const PerModelPrefixSum2D& capacity_prefix_sum, + const PerModelPrefixSum2D& utilization_prefix_sum, + const std::vector& model_indices) { + // Go through each model in the model group we are interested in. + for (int model_index : model_indices) { + // Get the capacity of this region for this model. + float region_model_capacity = capacity_prefix_sum.get_model_sum(model_index, + region); + // Get the utilization of this region for this model. + float region_model_utilization = utilization_prefix_sum.get_model_sum(model_index, + region); + // If the utilization is higher than the capacity, then this region is + // overfilled. + // TODO: Look into adding some head room to account for rounding. + if (region_model_utilization > region_model_capacity) + return true; + } + + // If the utilization is less than or equal to the capacity for each model + // then this region is not overfilled. + return false; +} + +std::vector BiPartitioningPartialLegalizer::get_min_windows_around_clusters( + const std::vector& overfilled_bin_clusters, + ModelGroupId group_id) { + // TODO: Currently, we greedily grow the region by 1 in all directions until + // the capacity is larger than the utilization. This may not produce + // the minimum window. Should investigate "touching-up" the windows. + // FIXME: It may be a good idea to sort the bins by their overfill here. Then + // we can check for overlap as we go. + + // Get the width, height, and number of layers for the spreading region. + // This is used by the growing part of this routine to prevent the windows + // from outgrowing the device. + size_t width, height, layers; + std::tie(width, height, layers) = density_manager_->get_overall_placeable_region_size(); + + // Precompute a prefix sum for the current utilization of each 1x1 region + // of the device. This needs to be recomputed every time the bins are + // modified, so it is recomputed here. + PerModelPrefixSum2D utilization_prefix_sum( + *density_manager_, + g_vpr_ctx.device().arch->models, + g_vpr_ctx.device().arch->model_library, + [&](int model_index, size_t x, size_t y) { + FlatPlacementBinId bin_id = density_manager_->get_bin(x, y, 0); + // This is computed the same way as the capacity prefix sum above. + const vtr::Rect& bin_region = density_manager_->flat_placement_bins().bin_region(bin_id); + float bin_area = bin_region.width() * bin_region.height(); + float util = density_manager_->get_bin_utilization(bin_id).get_dim_val(model_index); + VTR_ASSERT_SAFE(util >= 0.0f); + return util / bin_area; + }); + + // Create windows for each overfilled bin cluster. + std::vector windows; + for (const std::vector& overfilled_bin_cluster : overfilled_bin_clusters) { + // Create a new window for this cluster of bins. + SpreadingWindow new_window; + + // Set the region of the window to the bounding box of the cluster of bins. + size_t num_bins_in_cluster = overfilled_bin_cluster.size(); + VTR_ASSERT_SAFE(num_bins_in_cluster != 0); + vtr::Rect& region = new_window.region; + region = density_manager_->flat_placement_bins().bin_region(overfilled_bin_cluster[0]); + for (size_t i = 1; i < num_bins_in_cluster; i++) { + region = vtr::bounding_box(region, + density_manager_->flat_placement_bins().bin_region(overfilled_bin_cluster[i])); + } + + // Grow the region until it is just large enough to not overfill + while (true) { + // Grow the region by 1 on all sides. + double new_xmin = std::clamp(region.xmin() - 1.0, 0.0, width); + double new_xmax = std::clamp(region.xmax() + 1.0, 0.0, width); + double new_ymin = std::clamp(region.ymin() - 1.0, 0.0, height); + double new_ymax = std::clamp(region.ymax() + 1.0, 0.0, height); + + // If the region did not grow, exit. This is a maximal bin. + // TODO: Maybe print warning. + if (new_xmin == region.xmin() && new_xmax == region.xmax() && new_ymin == region.ymin() && new_ymax == region.ymax()) { + break; + } + + region.set_xmin(new_xmin); + region.set_xmax(new_xmax); + region.set_ymin(new_ymin); + region.set_ymax(new_ymax); + + // If the region is no longer overfilled, stop growing. + if (!is_region_overfilled(region, capacity_prefix_sum_, utilization_prefix_sum, model_grouper_.get_models_in_group(group_id))) + break; + } + // Insert this window into the list of windows. + windows.emplace_back(std::move(new_window)); + } + + return windows; +} + +void BiPartitioningPartialLegalizer::merge_overlapping_windows( + std::vector& windows) { + // Merge overlapping windows. + // TODO: This is a very basic merging process which will identify the + // minimum region containing both windows; however, after merging it + // is very likely that this window will now be too large. Need to + // investigate shrinking the windows after merging. + // TODO: I am not sure if it is possible, but after merging 2 windows, the + // new window may overlap with another window that has been already + // created. This should not cause issues with the algorithm since one + // of the new windows will just be empty, but it is not ideal. + // FIXME: This loop is O(N^2) with the number of overfilled bins which may + // get expensive as the circuit sizes increase. Should investigate + // spatial sorting structures (like kd-trees) to help keep this fast. + // Another idea is to merge windows early on (before growing them). + std::vector non_overlapping_windows; + size_t num_windows = windows.size(); + // Need to keep track of which windows have been merged or not to prevent + // merging windows multiple times. + std::vector finished_window(num_windows, false); + for (size_t i = 0; i < num_windows; i++) { + // If the window has already been finished (merged), nothing to do. + if (finished_window[i]) + continue; + + // Check for overlaps between this window and the future windows and + // update the region accordingly. + vtr::Rect& region = windows[i].region; + for (size_t j = i + 1; j < num_windows; j++) { + // No need to check windows which have already finished. + if (finished_window[j]) + continue; + // Check for overlap + if (region.strictly_overlaps(windows[j].region)) { + // If overlap, merge with this region and mark the window as + // finished. + // Here, the merged region is the bounding box around the two + // regions. + region = vtr::bounding_box(region, windows[j].region); + finished_window[j] = true; + } + } + + // This is not strictly necessary, but marking this window as finished + // is just a nice, clean thing to do. + finished_window[i] = true; + + // Move this window into the new list of non-overlapping windows. + non_overlapping_windows.emplace_back(std::move(windows[i])); + } + + // Store the results into the input window. + windows = std::move(non_overlapping_windows); +} + +void BiPartitioningPartialLegalizer::move_blocks_into_windows( + std::vector& non_overlapping_windows, + ModelGroupId group_id) { + // Move the blocks from their bins into the windows that should contain them. + // TODO: It may be good for debugging to check if the windows have nothing + // to move. This may indicate a problem (overfilled bins of fixed + // blocks, overlapping windows, etc.). + for (SpreadingWindow& window : non_overlapping_windows) { + // Iterate over all bins that this window covers. + // TODO: This is a bit crude and should somehow be made more robust. + size_t lower_x = window.region.xmin(); + size_t upper_x = window.region.xmax() - 1; + size_t lower_y = window.region.ymin(); + size_t upper_y = window.region.ymax() - 1; + for (size_t x = lower_x; x <= upper_x; x++) { + for (size_t y = lower_y; y <= upper_y; y++) { + // Get all of the movable blocks from the bin. + std::vector moveable_blks; + FlatPlacementBinId bin_id = density_manager_->get_bin(x, y, 0); + const auto& bin_contained_blocks = density_manager_->flat_placement_bins().bin_contained_blocks(bin_id); + moveable_blks.reserve(bin_contained_blocks.size()); + for (APBlockId blk_id : bin_contained_blocks) { + // If this block is not moveable, do not move it. + if (netlist_.block_mobility(blk_id) != APBlockMobility::MOVEABLE) + continue; + // If this block is not in the group, do not move it. + if (!is_block_in_group(blk_id, group_id, *density_manager_, model_grouper_)) + continue; + + moveable_blks.push_back(blk_id); + } + // Remove the moveable blocks from their bins and store into + // the windows. + for (APBlockId blk_id : moveable_blks) { + density_manager_->remove_block_from_bin(blk_id, bin_id); + window.contained_blocks.push_back(blk_id); + } + } + } + } +} + +void BiPartitioningPartialLegalizer::spread_over_windows(std::vector& non_overlapping_windows, + const PartialPlacement& p_placement, + ModelGroupId group_id) { + if (log_verbosity_ >= 10) { + VTR_LOG("\tIdentified %zu non-overlapping spreading windows.\n", + non_overlapping_windows.size()); + + if (log_verbosity_ >= 20) { + for (const SpreadingWindow& window : non_overlapping_windows) { + VTR_LOG("\t\t[(%.1f, %.1f), (%.1f, %.1f)]\n", + window.region.xmin(), window.region.ymin(), + window.region.xmax(), window.region.ymax()); + PrimitiveVector window_capacity = capacity_prefix_sum_.get_sum(model_grouper_.get_models_in_group(group_id), + window.region); + VTR_LOG("\t\t\tCapacity: %f\n", + window_capacity.manhattan_norm()); + VTR_LOG("\t\t\tNumber of contained blocks: %zu\n", + window.contained_blocks.size()); + } + } + } + + // Insert the windows into a queue for spreading. + std::queue window_queue; + for (SpreadingWindow& window : non_overlapping_windows) { + window_queue.push(std::move(window)); + } + + // For each window in the queue: + // 1) If the window is small enough, do not partition further. + // 2) Partition the window + // 3) Partition the blocks into the window partitions + // 4) Insert the new windows into the queue + std::vector finished_windows; + while (!window_queue.empty()) { + // Get a reference to the front of the queue but do not pop it yet. We + // can save time from having to copy the element out since these windows + // contain vectors. + SpreadingWindow& window = window_queue.front(); + + // Check if the window is empty. This can happen when there is odd + // numbers of blocks or when things do not perfectly fit. + if (window.contained_blocks.empty()) { + // If the window does not contain any blocks, pop it from the queue + // and do not put it in finished windows. There is no point + // operating on it further. + window_queue.pop(); + continue; + } + + // 1) Check if the window is small enough (one bin in size). + // TODO: Perhaps we can make this stopping criteria more intelligent. + // Like stopping when we know there is only one bin within the + // window. + double window_area = window.region.width() * window.region.height(); + if (window_area <= 1.0) { + finished_windows.emplace_back(std::move(window)); + window_queue.pop(); + continue; + } + + num_windows_partitioned_++; + num_blocks_partitioned_ += window.contained_blocks.size(); + + // 2) Partition the window. + auto partitioned_window = partition_window(window); + + // 3) Partition the blocks. + partition_blocks_in_window(window, partitioned_window, group_id, p_placement); + + // 4) Enqueue the new windows. + window_queue.push(std::move(partitioned_window.lower_window)); + window_queue.push(std::move(partitioned_window.upper_window)); + + // Pop the top element off the queue. This will invalidate the window + // object. + window_queue.pop(); + } + + if (log_verbosity_ >= 10) { + VTR_LOG("\t%zu finalized windows.\n", + finished_windows.size()); + + if (log_verbosity_ >= 30) { + for (const SpreadingWindow& window : finished_windows) { + VTR_LOG("\t\t[(%.1f, %.1f), (%.1f, %.1f)]\n", + window.region.xmin(), window.region.ymin(), + window.region.xmax(), window.region.ymax()); + PrimitiveVector window_capacity = capacity_prefix_sum_.get_sum(model_grouper_.get_models_in_group(group_id), + window.region); + VTR_LOG("\t\t\tCapacity: %f\n", + window_capacity.manhattan_norm()); + VTR_LOG("\t\t\tNumber of contained blocks: %zu\n", + window.contained_blocks.size()); + } + } + } + + // Move the blocks into the bins. + move_blocks_out_of_windows(finished_windows); + + // Verify that the bins are valid after moving blocks back from windows. + VTR_ASSERT_SAFE(density_manager_->verify()); +} + +PartitionedWindow BiPartitioningPartialLegalizer::partition_window(SpreadingWindow& window) { + PartitionedWindow partitioned_window; + + // Select the partition direction. + // To keep it simple, we partition the direction which would cut the + // region the most. + // TODO: Should explore making the partition line based on the capacity + // of the two partitioned regions. We may want to cut the + // region in half such that the mass of the atoms contained within + // the two future regions is equal. + partitioned_window.partition_dir = e_partition_dir::VERTICAL; + if (window.region.height() > window.region.width()) + partitioned_window.partition_dir = e_partition_dir::HORIZONTAL; + + // To keep it simple, just cut the space in half. + // TODO: Should investigate other cutting techniques. Cutting perfectly + // in half may not be the most efficient technique. + SpreadingWindow& lower_window = partitioned_window.lower_window; + SpreadingWindow& upper_window = partitioned_window.upper_window; + partitioned_window.pivot_pos = 0.f; + if (partitioned_window.partition_dir == e_partition_dir::VERTICAL) { + // Find the x-coordinate of a cut line directly in the middle of the + // region. We floor this to prevent fractional cut lines. + double pivot_x = std::floor((window.region.xmin() + window.region.xmax()) / 2.0); + + // Cut the region at this cut line. + lower_window.region = vtr::Rect(vtr::Point(window.region.xmin(), + window.region.ymin()), + vtr::Point(pivot_x, + window.region.ymax())); + + upper_window.region = vtr::Rect(vtr::Point(pivot_x, + window.region.ymin()), + vtr::Point(window.region.xmax(), + window.region.ymax())); + partitioned_window.pivot_pos = pivot_x; + } else { + VTR_ASSERT(partitioned_window.partition_dir == e_partition_dir::HORIZONTAL); + // Similarly in the y direction, find the non-fractional y coordinate + // to make a horizontal cut. + double pivot_y = std::floor((window.region.ymin() + window.region.ymax()) / 2.0); + + // Then cut the window. + lower_window.region = vtr::Rect(vtr::Point(window.region.xmin(), + window.region.ymin()), + vtr::Point(window.region.xmax(), + pivot_y)); + + upper_window.region = vtr::Rect(vtr::Point(window.region.xmin(), + pivot_y), + vtr::Point(window.region.xmax(), + window.region.ymax())); + partitioned_window.pivot_pos = pivot_y; + } + + return partitioned_window; +} + +void BiPartitioningPartialLegalizer::partition_blocks_in_window( + SpreadingWindow& window, + PartitionedWindow& partitioned_window, + ModelGroupId group_id, + const PartialPlacement& p_placement) { + + SpreadingWindow& lower_window = partitioned_window.lower_window; + SpreadingWindow& upper_window = partitioned_window.upper_window; + + // Get the capacity of each window partition. + const std::vector& model_indices = model_grouper_.get_models_in_group(group_id); + PrimitiveVector lower_window_capacity = capacity_prefix_sum_.get_sum(model_indices, + lower_window.region); + PrimitiveVector upper_window_capacity = capacity_prefix_sum_.get_sum(model_indices, + upper_window.region); + + // Due to the division by the area, we may get numerical underflows / + // overflows which accumulate. If they accumulate in the positive + // direction, it is not a big deal; but in the negative direction it + // will cause problems with the algorithm below. Clamp any negative + // numbers to 0. + lower_window_capacity.relu(); + upper_window_capacity.relu(); + PrimitiveVector lower_window_underfill = lower_window_capacity; + PrimitiveVector upper_window_underfill = upper_window_capacity; + VTR_ASSERT_SAFE(lower_window_underfill.is_non_negative()); + VTR_ASSERT_SAFE(upper_window_underfill.is_non_negative()); + + // FIXME: We need to take into account the current utilization of the + // fixed blocks... We need to take into account that they are there. + // Currently we assume the underfill is the capacity + // Without this, we may overfill blocks which have fixed blocks in + // them. + + // If the lower window has no space, put all of the blocks in the upper window. + // NOTE: We give some room due to numerical overflows from the prefix sum. + if (lower_window_underfill.manhattan_norm() < 0.01f) { + upper_window.contained_blocks = std::move(window.contained_blocks); + return; + } + // If the upper window has no space, put all of the blocks in the lower window. + if (upper_window_underfill.manhattan_norm() < 0.01f) { + lower_window.contained_blocks = std::move(window.contained_blocks); + return; + } + + // Reserve space in each of the windows to make insertion faster. + upper_window.contained_blocks.reserve(window.contained_blocks.size()); + lower_window.contained_blocks.reserve(window.contained_blocks.size()); + + // Sort the blocks and get the pivot index. The pivot index is the index in + // the windows contained block which decides which sub-window the block + // wants to be in. The blocks at indices [0, pivot) want to be in the lower + // window, blocks at indices [pivot, num_blks) want to be in the upper window. + // This want is based on the solved positions of the blocks. + size_t pivot; + if (partitioned_window.partition_dir == e_partition_dir::VERTICAL) { + // Sort the blocks in the window by the x coordinate. + std::sort(window.contained_blocks.begin(), window.contained_blocks.end(), [&](APBlockId a, APBlockId b) { + return p_placement.block_x_locs[a] < p_placement.block_x_locs[b]; + }); + auto upper = std::upper_bound(window.contained_blocks.begin(), + window.contained_blocks.end(), + partitioned_window.pivot_pos, + [&](double value, APBlockId blk_id) { + return value < p_placement.block_x_locs[blk_id]; + }); + pivot = std::distance(window.contained_blocks.begin(), upper); + } else { + VTR_ASSERT(partitioned_window.partition_dir == e_partition_dir::HORIZONTAL); + // Sort the blocks in the window by the y coordinate. + std::sort(window.contained_blocks.begin(), window.contained_blocks.end(), [&](APBlockId a, APBlockId b) { + return p_placement.block_y_locs[a] < p_placement.block_y_locs[b]; + }); + auto upper = std::upper_bound(window.contained_blocks.begin(), + window.contained_blocks.end(), + partitioned_window.pivot_pos, + [&](double value, APBlockId blk_id) { + return value < p_placement.block_y_locs[blk_id]; + }); + pivot = std::distance(window.contained_blocks.begin(), upper); + } + + // Try to place the blocks that want to be in the lower window from lower + // to upper. + std::vector unplaced_blocks; + for (size_t i = 0; i < pivot; i++) { + const PrimitiveVector& blk_mass = density_manager_->mass_calculator().get_block_mass(window.contained_blocks[i]); + VTR_ASSERT_SAFE(lower_window_underfill.is_non_negative()); + // Try to put the blk in the window. + lower_window_underfill -= blk_mass; + if (lower_window_underfill.is_non_negative()) + // If the underfill is not negative, then we can add it to the window. + lower_window.contained_blocks.push_back(window.contained_blocks[i]); + else { + // If the underfill went negative, undo the addition and mark this + // block as unplaced. + lower_window_underfill += blk_mass; + unplaced_blocks.push_back(window.contained_blocks[i]); + } + } + // Try to place the blocks that want to be in the upper window from upper + // to lower. + // NOTE: This needs to be an int in case the pivot is 0. + for (int i = window.contained_blocks.size() - 1; i >= (int)pivot; i--) { + const PrimitiveVector& blk_mass = density_manager_->mass_calculator().get_block_mass(window.contained_blocks[i]); + VTR_ASSERT_SAFE(lower_window_underfill.is_non_negative()); + upper_window_underfill -= blk_mass; + if (upper_window_underfill.is_non_negative()) + upper_window.contained_blocks.push_back(window.contained_blocks[i]); + else { + upper_window_underfill += blk_mass; + unplaced_blocks.push_back(window.contained_blocks[i]); + } + } + + // Handle the unplaced blocks. + // To handle these blocks, we will try to balance the overfill in both + // windows. To do this we sort the unplaced blocks by largest mass to + // smallest mass. Then we place each block in the bin with the highest + // underfill. + // FIXME: Above was the intuition; however, after experimentation, found that + // sorting by smallest mass to largest mass worked better... + // FIXME: I think large blocks (like carry chains) need to be handled special + // early on. If they are put into a partition too late, they may have + // to create overfill! Perhaps the partitions can hold two lists. + std::sort(unplaced_blocks.begin(), + unplaced_blocks.end(), + [&](APBlockId a, APBlockId b) { + const auto& blk_a_mass = density_manager_->mass_calculator().get_block_mass(a); + const auto& blk_b_mass = density_manager_->mass_calculator().get_block_mass(b); + return blk_a_mass.manhattan_norm() < blk_b_mass.manhattan_norm(); + }); + for (APBlockId blk_id : unplaced_blocks) { + // Project the underfill from each window onto the mass. This gives us + // the overfill in the dimensions the mass cares about. + const PrimitiveVector& blk_mass = density_manager_->mass_calculator().get_block_mass(blk_id); + PrimitiveVector projected_lower_window_underfill = lower_window_underfill; + lower_window_underfill.project(blk_mass); + PrimitiveVector projected_upper_window_underfill = upper_window_underfill; + upper_window_underfill.project(blk_mass); + // Put the block in the window with a higher underfill. This tries to + // balance the overfill as much as possible. This works even if the + // overfill becomes negative. + if (projected_lower_window_underfill.manhattan_norm() >= projected_upper_window_underfill.manhattan_norm()) { + lower_window.contained_blocks.push_back(blk_id); + lower_window_underfill -= blk_mass; + } else { + upper_window.contained_blocks.push_back(blk_id); + upper_window_underfill -= blk_mass; + } + } +} + +void BiPartitioningPartialLegalizer::move_blocks_out_of_windows( + std::vector& finished_windows) { + + for (const SpreadingWindow& window : finished_windows) { + // Get the bin at the center of the window. + vtr::Point center = get_center_of_rect(window.region); + FlatPlacementBinId bin_id = density_manager_->get_bin(center.x(), center.y(), 0); + + // Move all blocks in the window into this bin. + for (APBlockId blk_id : window.contained_blocks) { + // Note: The blocks should have been removed from their original + // bins when they were put into the windows. There are asserts + // within the denisty manager class which will verify this. + density_manager_->insert_block_into_bin(blk_id, bin_id); + } + } +} diff --git a/vpr/src/analytical_place/partial_legalizer.h b/vpr/src/analytical_place/partial_legalizer.h index 96171e5fdb5..2eb4e5771da 100644 --- a/vpr/src/analytical_place/partial_legalizer.h +++ b/vpr/src/analytical_place/partial_legalizer.h @@ -13,29 +13,24 @@ #pragma once +#include #include -#include #include #include "ap_netlist_fwd.h" +#include "ap_flow_enums.h" +#include "flat_placement_bins.h" +#include "flat_placement_density_manager.h" +#include "model_grouper.h" #include "primitive_vector.h" -#include "vtr_assert.h" #include "vtr_geometry.h" -#include "vtr_ndmatrix.h" -#include "vtr_strong_id.h" -#include "vtr_vector_map.h" +#include "vtr_prefix_sum.h" +#include "vtr_vector.h" // Forward declarations class APNetlist; +class Prepacker; struct PartialPlacement; -/** - * @brief Enumeration of all of the partial legalizers currently implemented in - * VPR. - */ -enum class e_partial_legalizer { - FLOW_BASED // Multi-commodity flow-based partial legalizer. -}; - /** * @brief The Partial Legalizer base class * @@ -46,7 +41,7 @@ enum class e_partial_legalizer { * compare different solvers. */ class PartialLegalizer { -public: + public: virtual ~PartialLegalizer() {} /** @@ -54,9 +49,9 @@ class PartialLegalizer { * * Currently just copies the parameters into the class as member varaibles. */ - PartialLegalizer(const APNetlist& netlist, int log_verbosity = 1) - : netlist_(netlist), - log_verbosity_(log_verbosity) {} + PartialLegalizer(const APNetlist& netlist, int log_verbosity) + : netlist_(netlist) + , log_verbosity_(log_verbosity) {} /** * @brief Partially legalize the given partial placement. @@ -71,10 +66,17 @@ class PartialLegalizer { * @param p_placement The placement to legalize. Will be filled with the * legalized placement. */ - virtual void legalize(PartialPlacement &p_placement) = 0; + virtual void legalize(PartialPlacement& p_placement) = 0; -protected: + /** + * @brief Print statistics on the Partial Legalizer. + * + * This is expected to be called at the end of Global Placement to provide + * cummulative information on how much work the partial legalizer performed. + */ + virtual void print_statistics() = 0; + protected: /// @brief The APNetlist the legalizer will be legalizing the placement of. /// It is implied that the netlist is not being modified during /// global placement. @@ -89,85 +91,11 @@ class PartialLegalizer { /** * @brief A factory method which creates a Partial Legalizer of the given type. */ -std::unique_ptr make_partial_legalizer(e_partial_legalizer legalizer_type, - const APNetlist& netlist); - -/** - * @brief A strong ID for the bins used in the partial legalizer. - * - * This allows a separation between the legalizers and tiles such that a bin may - * represent multiple tiles. - */ -struct legalizer_bin_tag {}; -typedef vtr::StrongId LegalizerBinId; - -/** - * @brief A bin used to contain blocks in the partial legalizer. - * - * Bins can be thought of as generalized tiles which have a capacity of blocks - * (and their types) and a current utilization of the bin. A bin may represent - * multiple tiles. - * - * The capacity, utilization, supply, and demand of the bin are stored as - * M-dimensional vectors; where M is the number of models (primitives) in the - * device. This allows the bin to quickly know how much of each types of - * primitives it can contain and how much of each type it currently contains. - */ -struct LegalizerBin { - /// @brief The blocks currently contained in this bin. - std::unordered_set contained_blocks; - - /// @brief The maximum mass of each primitive type this bin can contain. - PrimitiveVector capacity; - - /// @brief The current mass of each primitive type this bin contains. - PrimitiveVector utilization; - - /// @brief The current over-utilization of the bin. This is defined as: - /// elementwise_max(utilization - capacity, 0) - PrimitiveVector supply; - - /// @brief The current under-utilization of the bin. This is defined as: - /// elementwise_max(capacity - utilization, 0) - PrimitiveVector demand; - - /// @brief The bounding box of the bin on the device grid. This is the - /// positions on the grid the blocks will exist. - /// - /// For example, if the tile at location (2,3) was turned directly into a - /// bin, the bounding box of that bin would be [(2.0, 3.0), (3.0, 4.0)) - /// Notice the notation here. The left and bottom edges are included in the - /// set. - /// It is implied that blocks cannot be placed on the right or top edges of - /// the bounding box (since then they may be in another bin!). - /// - /// NOTE: This uses a double to match the precision of the positions of - /// APBlocks (which are doubles). The use of a double here also allows - /// bins to represent partial tiles which may be useful. - vtr::Rect bounding_box; - - /// @brief The neighbors of this bin. These are neighboring bins that this - /// bin can flow blocks to. - std::vector neighbors; - - /** - * @brief Helper method to compute the supply of the bin. - */ - void compute_supply() { - supply = utilization - capacity; - supply.relu(); - VTR_ASSERT_DEBUG(supply.is_non_negative()); - } - - /** - * @brief Helper method to compute the demand of the bin. - */ - void compute_demand() { - demand = capacity - utilization; - demand.relu(); - VTR_ASSERT_DEBUG(demand.is_non_negative()); - } -}; +std::unique_ptr make_partial_legalizer(e_ap_partial_legalizer legalizer_type, + const APNetlist& netlist, + std::shared_ptr density_manager, + const Prepacker& prepacker, + int log_verbosity); /** * @brief A multi-commodity flow-based spreading partial legalizer. @@ -183,14 +111,9 @@ struct LegalizerBin { * on their work by generalizing it to any theoretical architecture which can be * expressed in VPR. * https://doi.org/10.1145/3289602.3293896 - * - * - * TODO: Make the bin size a parameter for the legalizer somehow. That way we - * can make 1x1 bins for very accurate legalizers and larger (clamped) for - * less accurate legalizers. */ class FlowBasedLegalizer : public PartialLegalizer { -private: + private: /// @brief The maximum number of iterations the legalizer can take. This /// prevents the legalizer from never converging if there is not /// enough space to flow blocks. @@ -208,99 +131,32 @@ class FlowBasedLegalizer : public PartialLegalizer { /// sufficient neighbors. static constexpr unsigned max_bin_neighbor_dist_ = 4; - /// @brief A vector of all the bins in the legalizer. - vtr::vector_map bins_; - - /// @brief A reverse lookup between every block and the bin they are - /// currently in. - vtr::vector_map block_bins_; - - /// @brief The mass of each APBlock, represented as a primitive vector. - vtr::vector_map block_masses_; - - /// @brief A lookup that gets the bin that represents every tile (and - /// sub-tile). - vtr::NdMatrix tile_bin_; - - /// @brief A set of overfilled bins. Instead of computing this when needed, - /// this list is maintained whenever a block is moved from one bin to - /// another. - std::unordered_set overfilled_bins_; + /// @brief The density manager which manages how the bins are constructed + /// and maintains how overfilled bins are. + std::shared_ptr density_manager_; - /** - * @brief Returns true if the given bin is overfilled. - */ - inline bool bin_is_overfilled(LegalizerBinId bin_id) const { - VTR_ASSERT_DEBUG(bin_id.is_valid()); - VTR_ASSERT_DEBUG(bins_[bin_id].supply.is_non_negative()); - // By definition, a bin is overfilled if its supply is non-zero. - return bins_[bin_id].supply.is_non_zero(); - } + /// @brief The neighbors of each bin. + /// + /// These are the closest bins in each direction for each model type to flow + /// from this bin into. + vtr::vector> bin_neighbors_; /** - * @brief Helper method to insert a block into a bin. - * - * This method maintains all the necessary state of the class and updates - * the bin the block is being inserted into. - * - * This method assumes that the given block is not currently in a bin. + * @brief Get the supply of the given bin. Supply is how much over-capacity + * the bin is. */ - inline void insert_blk_into_bin(APBlockId blk_id, LegalizerBinId bin_id) { - VTR_ASSERT_DEBUG(blk_id.is_valid()); - VTR_ASSERT_DEBUG(bin_id.is_valid()); - // Make sure that this block is not anywhere else. - VTR_ASSERT(block_bins_[blk_id] == LegalizerBinId::INVALID()); - // Insert the block into the bin. - block_bins_[blk_id] = bin_id; - LegalizerBin& bin = bins_[bin_id]; - bin.contained_blocks.insert(blk_id); - // Update the utilization, supply, and demand. - const PrimitiveVector& blk_mass = block_masses_[blk_id]; - bin.utilization += blk_mass; - bin.compute_supply(); - bin.compute_demand(); - // Update the overfilled bins since this bin may have become overfilled. - if (bin_is_overfilled(bin_id)) - overfilled_bins_.insert(bin_id); + inline const PrimitiveVector& get_bin_supply(FlatPlacementBinId bin_id) const { + // Supply is defined as the overfill of the bin. + return density_manager_->get_bin_overfill(bin_id); } /** - * @brief Helper method to remove a block from a bin. - * - * This method maintains all the necessary state of the class and updates - * the bin the block is being removed from. - * - * This method assumes that the given block is currently in the given bin. + * @brief Get the demand of the given bin. Demand is how much under-capacity + * the bin is. */ - inline void remove_blk_from_bin(APBlockId blk_id, LegalizerBinId bin_id) { - VTR_ASSERT_DEBUG(blk_id.is_valid()); - VTR_ASSERT_DEBUG(bin_id.is_valid()); - // Make sure that this block is in this bin. - VTR_ASSERT(block_bins_[blk_id] == bin_id); - LegalizerBin& bin = bins_[bin_id]; - VTR_ASSERT_DEBUG(bin.contained_blocks.count(blk_id) == 1); - // Remove the block from the bin. - block_bins_[blk_id] = LegalizerBinId::INVALID(); - bin.contained_blocks.erase(blk_id); - // Update the utilization, supply, and demand. - const PrimitiveVector& blk_mass = block_masses_[blk_id]; - bin.utilization -= blk_mass; - bin.compute_supply(); - bin.compute_demand(); - // Update the overfilled bins since this bin may no longer be - // overfilled. - if (!bin_is_overfilled(bin_id)) - overfilled_bins_.erase(bin_id); - } - - /** - * @brief Helper method to get the bin at the current device x and y tile - * coordinate. - */ - inline LegalizerBinId get_bin(size_t x, size_t y) const { - VTR_ASSERT_DEBUG(x < tile_bin_.dim_size(0)); - VTR_ASSERT_DEBUG(y < tile_bin_.dim_size(1)); - return tile_bin_[x][y]; + inline const PrimitiveVector& get_bin_demand(FlatPlacementBinId bin_id) const { + // Demand is defined as the underfill of the bin. + return density_manager_->get_bin_underfill(bin_id); } /** @@ -325,7 +181,7 @@ class FlowBasedLegalizer : public PartialLegalizer { * @param src_bin_id The bin to compute the neighbors for. * @param num_models The number of models in the architecture. */ - void compute_neighbors_of_bin(LegalizerBinId src_bin_id, size_t num_models); + void compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, size_t num_models); /** * @brief Debugging method which verifies that all the bins are valid. @@ -336,30 +192,7 @@ class FlowBasedLegalizer : public PartialLegalizer { * - Every bin has the correct utilization, supply, and demand * - The overfilled bins are correct */ - bool verify_bins() const; - - /** - * @brief Resets all of the bins from a previous call to partial legalize. - * - * This removes all of the blocks from the bins. - */ - void reset_bins(); - - /** - * @brief Import the given partial placement into bins. - * - * This is called at the beginning of legalize to prepare the bins with the - * current placement. - */ - void import_placement_into_bins(const PartialPlacement& p_placement); - - /** - * @brief Export the placement found from spreading the bins. - * - * This is called at the end of legalize to write back the result of the - * legalizer. - */ - void export_placement_from_bins(PartialPlacement& p_placement) const; + bool verify() const; /** * @brief Gets paths to flow blocks from the src_bin_id at a maximum cost @@ -371,9 +204,9 @@ class FlowBasedLegalizer : public PartialLegalizer { * @param psi An algorithm parameter that increases over many * iterations. The "max-cost" a path can be. */ - std::vector> get_paths(LegalizerBinId src_bin_id, - const PartialPlacement& p_placement, - float psi); + std::vector> get_paths(FlatPlacementBinId src_bin_id, + const PartialPlacement& p_placement, + float psi); /** * @brief Flows the blocks along the given path. @@ -387,20 +220,21 @@ class FlowBasedLegalizer : public PartialLegalizer { * @param psi An algorithm parameter that increases over many * iterations. The "max-cost" a path can be. */ - void flow_blocks_along_path(const std::vector& path, + void flow_blocks_along_path(const std::vector& path, const PartialPlacement& p_placement, float psi); -public: - + public: /** - * @brief Construcotr for the flow-based legalizer. + * @brief Constructor for the flow-based legalizer. * * Builds all of the bins, computing their capacities based on the device * description. Builds the connectivity of bins. Computes the mass of all * blocks in the netlist. */ - FlowBasedLegalizer(const APNetlist& netlist); + FlowBasedLegalizer(const APNetlist& netlist, + std::shared_ptr density_manager, + int log_verbosity); /** * @brief Performs flow-based spreading on the given partial placement. @@ -408,6 +242,290 @@ class FlowBasedLegalizer : public PartialLegalizer { * @param p_placement The placmeent to legalize. The result of the partial * legalizer will be stored in this object. */ - void legalize(PartialPlacement &p_placement) final; + void legalize(PartialPlacement& p_placement) final; + + void print_statistics() final {} +}; + +/** + * @brief A cluster of flat placement bins. + */ +typedef typename std::vector FlatPlacementBinCluster; + +/** + * @brief Enum for the direction of a partition. + */ +enum class e_partition_dir { + VERTICAL, + HORIZONTAL +}; + +/** + * @brief Spatial window used to spread the blocks contained within. + * + * This window's region is identified and grown until it has enough space to + * accomodate the blocks stored within. This window is then successivly + * partitioned until it is small enough (blocks are not too dense). + */ +struct SpreadingWindow { + /// @brief The blocks contained within this window. + std::vector contained_blocks; + + /// @brief The 2D region of space that this window covers. + vtr::Rect region; +}; + +/** + * @brief Struct to hold the information from partitioning a window. Contains + * the two window partitions and some information about how they were + * generated. + */ +struct PartitionedWindow { + /// @brief The direction of the partition. + e_partition_dir partition_dir; + + /// @brief The position that the parent window was split at. + double pivot_pos; + + /// @brief The lower window. This is the left partition when the direction + /// is vertical, and the bottom partition when the direction is + /// horizontal. + SpreadingWindow lower_window; + + /// @brief The upper window. This is the right partition when the direction + /// is vertical, and the top partition when the direction is + /// horizontal. + SpreadingWindow upper_window; +}; + +/** + * @brief Wrapper class around the prefix sum class which creates a prefix sum + * for each model type and has helper methods for getting the sums over + * regions. + */ +class PerModelPrefixSum2D { + public: + PerModelPrefixSum2D() = default; + + /** + * @brief Construct prefix sums for each of the models in the architecture. + * + * Uses the density manager to get the size of the placeable region. + * + * The lookup is a lambda used to populate the prefix sum. It provides + * the model index, x, and y to be populated. + */ + PerModelPrefixSum2D(const FlatPlacementDensityManager& density_manager, + t_model* user_models, + t_model* library_models, + std::function lookup); + + /** + * @brief Get the sum for a given model over the given region. + */ + float get_model_sum(int model_index, + const vtr::Rect& region) const; + + /** + * @brief Get the multi-dimensional sum over the given model indices over + * the given region. + */ + PrimitiveVector get_sum(const std::vector& model_indices, + const vtr::Rect& region) const; + + private: + /// @brief Per-Model Prefix Sums + std::vector> model_prefix_sum_; }; +/** + * @brief A bi-paritioning spreading full legalizer. + * + * This creates minimum spanning windows around overfilled bins in the device + * such that the capacity of the bins within the window is just higher than the + * current utilization of the bins within the window. These windows are then + * split in both region and contained atoms. This spatially spreads out the + * atoms within each window. This splitting continues until the windows are + * small enough and the atoms are placed. The benefit of this approach is that + * it cuts the problem size for each partition, which can yield improved + * performance when there is a lot of overfill. + * + * This technique is based on the lookahead legalizer in SimPL and the window- + * based legalization found in GPlace3.0. + * SimPL: https://doi.org/10.1145/2461256.2461279 + * GPlace3.0: https://doi.org/10.1145/3233244 + */ +class BiPartitioningPartialLegalizer : public PartialLegalizer { + private: + /// @brief The maximum gap between overfilled bins we can have in a flat + /// placement bin cluster. For example, if this is set to 1, we will + /// allow two overfilled bins to be clustered together if they only + /// have 1 non-overfilled bin of gap between them. + /// The rational behind this is that it allows us to predict that the windows + /// created for each cluster will overlap if they are within some gap distance. + /// Increasing this number too much may cluster bins together too much and + /// create large windows; decreasing this number will put more pressure on + /// the window generation code, which can increase window size and runtime. + /// TODO: Should this be distance instead of number of bins? + static constexpr int max_bin_cluster_gap_ = 2; + + public: + /** + * @brief Constructor for the bi-partitioning partial legalizer. + * + * Uses the provided denisity manager to identify the capacity and + * utilization of regions of the device. + */ + BiPartitioningPartialLegalizer(const APNetlist& netlist, + std::shared_ptr density_manager, + const Prepacker& prepacker, + int log_verbosity); + + /** + * @brief Perform bi-partitioning spreading on the given partial placement. + * + * @param p_placement + * The placement to legalize. The result of the partial legalizer + * will be stored in this object. + */ + void legalize(PartialPlacement& p_placement) final; + + /** + * @brief Print statistics on the BiPartitioning Partial Legalizer. + */ + void print_statistics() final; + + private: + // ======================================================================== + // Identifying spreading windows + // ======================================================================== + + /** + * @brief Identify spreading windows which contain overfilled bins in the + * given model group on the device and do not overlap. + * + * This process is split into 4 stages: + * 1) Overfilled bins are identified and clustered. + * 2) Grow windows around the overfilled bin clusters. These windows + * will grow until there is just enough space to accomodate the blocks + * within the window (capacity of the window is larger than the utilization). + * 3) Merge overlapping windows. + * 4) Move the blocks within these window regions from their bins into + * their windows. This updates the current utilization of bins, making + * spreading easier. + * + * We identify non-overlapping windows for different model groups independtly + * for a few reasons: + * - Each model group, by design, can be spread independent of each other. + * This reduces the problem size by the number of groups. + * - Without model groups, one block placed on the wrong side of the chip + * may create a window the size of the entire chip! This would rip up and + * spread all the blocks in the chip, which is very expensive. + * - This allows us to ignore block models which are already in legal + * positions. + */ + std::vector identify_non_overlapping_windows(ModelGroupId group_id); + + /** + * @brief Identifies clusters of overfilled bins for the given model group. + * + * This locates clusters of overfilled bins which are within a given + * distance from each other. + */ + std::vector get_overfilled_bin_clusters(ModelGroupId group_id); + + /** + * @brief Creates and grows minimum spanning windows around the given + * overfilled bin clusters. + * + * Here, minimum means that the windows are just large enough such that the + * capacity of the bins within the window is larger than the utilization for + * the given model group. + */ + std::vector get_min_windows_around_clusters( + const std::vector& overfilled_bin_clusters, + ModelGroupId group_id); + + /** + * @brief Merges overlapping windows in the given vector of windows. + * + * The resulting merged windows is stored in the given windows object. + */ + void merge_overlapping_windows(std::vector& windows); + + /** + * @brief Moves the blocks out of their bins and into their window. + * + * Only blocks in the given model group will be moved. + */ + void move_blocks_into_windows(std::vector& non_overlapping_windows, + ModelGroupId group_id); + + // ======================================================================== + // Spreading blocks over windows + // ======================================================================== + + /** + * @brief Spread the blocks over each of the given non-overlapping windows. + * + * The partial placement solution from the solver is used to decide which + * window partition to put a block into. The model group this window is + * spreading over can make it more efficient to make decisions. + */ + void spread_over_windows(std::vector& non_overlapping_windows, + const PartialPlacement& p_placement, + ModelGroupId group_id); + + /** + * @brief Partition the given window into two sub-windows. + * + * We return extra information about how the window was created; for example, + * the direction of the partition (vertical / horizontal) and the position + * of the cut. + */ + PartitionedWindow partition_window(SpreadingWindow& window); + + /** + * @brief Partition the blocks in the given window into the partitioned + * windows. + * + * This is kept separate from splitting the physical window region for + * cleanliness. After this point, the window will not have any atoms in + * it. + */ + void partition_blocks_in_window(SpreadingWindow& window, + PartitionedWindow& partitioned_window, + ModelGroupId group_id, + const PartialPlacement& p_placement); + + /** + * @brief Move the blocks out of the given windows and put them back into + * the correct bin according to the window that contains them. + */ + void move_blocks_out_of_windows(std::vector& finished_windows); + + private: + /// @brief The density manager which manages the capacity and utilization + /// of regions of the device. + std::shared_ptr density_manager_; + + /// @brief Grouper object which handles grouping together models which must + /// be spread together. Models are grouped based on the pack patterns + /// that they can form with each other. + ModelGrouper model_grouper_; + + /// @brief The prefix sum for the capacity of the device, as given by the + /// density manager. We will need to get the capacity of 2D regions + /// of the device very often for this partial legalizer. This data + /// structure greatly improves the time complexity of this operation. + /// + /// This is populated in the constructor and not modified. + PerModelPrefixSum2D capacity_prefix_sum_; + + /// @brief The number of times a window was partitioned in the legalizer. + unsigned num_windows_partitioned_ = 0; + + /// @brief The number of times a block was partitioned from one window into + /// another. This includes blocks which get partitioned multiple times. + unsigned num_blocks_partitioned_ = 0; +}; diff --git a/vpr/src/analytical_place/partial_placement.cpp b/vpr/src/analytical_place/partial_placement.cpp index fc80f43b4a7..4e52faecef0 100644 --- a/vpr/src/analytical_place/partial_placement.cpp +++ b/vpr/src/analytical_place/partial_placement.cpp @@ -43,13 +43,9 @@ bool PartialPlacement::verify_locs(const APNetlist& netlist, for (APBlockId blk_id : netlist.blocks()) { double x_pos = block_x_locs[blk_id]; double y_pos = block_y_locs[blk_id]; - if (std::isnan(x_pos) || - x_pos < 0.0 || - x_pos >= grid_width) + if (std::isnan(x_pos) || x_pos < 0.0 || x_pos >= grid_width) return false; - if (std::isnan(y_pos) || - y_pos < 0.0 || - y_pos >= grid_height) + if (std::isnan(y_pos) || y_pos < 0.0 || y_pos >= grid_height) return false; if (netlist.block_mobility(blk_id) == APBlockMobility::FIXED) { const APFixedBlockLoc& fixed_loc = netlist.block_loc(blk_id); @@ -120,4 +116,3 @@ bool PartialPlacement::verify(const APNetlist& netlist, // If all other verify methods passed, then the placement is valid. return true; } - diff --git a/vpr/src/analytical_place/partial_placement.h b/vpr/src/analytical_place/partial_placement.h index e111dd7bd79..bb7406fcd34 100644 --- a/vpr/src/analytical_place/partial_placement.h +++ b/vpr/src/analytical_place/partial_placement.h @@ -71,10 +71,10 @@ struct PartialPlacement { * @param netlist The APNetlist which contains the blocks to be placed. */ PartialPlacement(const APNetlist& netlist) - : block_x_locs(netlist.blocks().size(), -1.0), - block_y_locs(netlist.blocks().size(), -1.0), - block_layer_nums(netlist.blocks().size(), 0.0), - block_sub_tiles(netlist.blocks().size(), 0) { + : block_x_locs(netlist.blocks().size(), -1.0) + , block_y_locs(netlist.blocks().size(), -1.0) + , block_layer_nums(netlist.blocks().size(), 0.0) + , block_sub_tiles(netlist.blocks().size(), 0) { // Note: All blocks are initialized to: // x_loc = -1.0 // y_loc = -1.0 @@ -84,7 +84,7 @@ struct PartialPlacement { for (APBlockId blk_id : netlist.blocks()) { if (netlist.block_mobility(blk_id) != APBlockMobility::FIXED) continue; - const APFixedBlockLoc &loc = netlist.block_loc(blk_id); + const APFixedBlockLoc& loc = netlist.block_loc(blk_id); if (loc.x != -1) block_x_locs[blk_id] = loc.x; if (loc.y != -1) @@ -201,4 +201,3 @@ struct PartialPlacement { size_t grid_height, size_t grid_num_layers) const; }; - diff --git a/vpr/src/analytical_place/primitive_vector.h b/vpr/src/analytical_place/primitive_vector.h index 1dd7c4d5a4b..d76ae8b509d 100644 --- a/vpr/src/analytical_place/primitive_vector.h +++ b/vpr/src/analytical_place/primitive_vector.h @@ -10,8 +10,11 @@ #pragma once +#include #include #include +#include +#include "vtr_log.h" /** * @brief A sparse vector class to store an M-dimensional quantity of primitives @@ -30,7 +33,7 @@ * Primitive Vectors. */ class PrimitiveVector { -private: + private: /// @brief Storage container for the data of this primitive vector. /// /// This is stored as a map since it is assumed that the vector will be @@ -41,16 +44,31 @@ class PrimitiveVector { /// Perhaps we can just waste the space and use a vector. std::unordered_map data_; -public: + public: /** * @brief Add the value to the given dimension. * * This is a common enough feature to use its own setter. */ inline void add_val_to_dim(float val, size_t dim) { - if (data_.count(dim) == 0) - data_[dim] = 0.f; - data_[dim] += val; + auto it = data_.find(dim); + if (it == data_.end()) + data_.insert({dim, val}); + else { + it->second += val; + } + } + + /** + * @brief Subtract the value to the given dimension. + */ + inline void subtract_val_from_dim(float val, size_t dim) { + auto it = data_.find(dim); + if (it == data_.end()) + data_.insert({dim, -1.0f * val}); + else { + it->second -= val; + } } /** @@ -104,19 +122,26 @@ class PrimitiveVector { */ inline PrimitiveVector& operator+=(const PrimitiveVector& rhs) { for (const auto& p : rhs.data_) { - float dim_val = get_dim_val(p.first); - set_dim_val(p.first, dim_val + p.second); + add_val_to_dim(p.second, p.first); } return *this; } + /** + * @brief Element-wise addition of this with rhs. + */ + inline PrimitiveVector operator+(const PrimitiveVector& rhs) const { + PrimitiveVector res = *this; + res += rhs; + return res; + } + /** * @brief Element-wise de-accumulation of rhs into this. */ inline PrimitiveVector& operator-=(const PrimitiveVector& rhs) { for (const auto& p : rhs.data_) { - float dim_val = get_dim_val(p.first); - set_dim_val(p.first, dim_val - p.second); + subtract_val_from_dim(p.second, p.first); } return *this; } @@ -140,6 +165,25 @@ class PrimitiveVector { return *this; } + /** + * @brief Element-wise division with a scalar. + */ + inline PrimitiveVector& operator/=(float rhs) { + for (auto& p : data_) { + p.second /= rhs; + } + return *this; + } + + /** + * @brief Element-wise division with a scalar. + */ + inline PrimitiveVector operator/(float rhs) const { + PrimitiveVector res = *this; + res /= rhs; + return res; + } + /** * @brief Returns true if any dimension of this vector is less than any * dimension of rhs; false otherwise. @@ -168,12 +212,11 @@ class PrimitiveVector { * is positive, it will not change. */ inline void relu() { - for (auto& p : data_) { - // TODO: Should remove the zero elements from the map to improve - // efficiency. - if (p.second < 0.f) - p.second = 0.f; - } + std::erase_if(data_, [](const std::pair& p) { + // Note: we erase the numbers from the map to improve the performance + // of future operations on this vector. + return p.second <= 0.0f; + }); } /** @@ -234,12 +277,36 @@ class PrimitiveVector { inline void project(const PrimitiveVector& dir) { // For each dimension of this vector, if that dimension is zero in dir // set the dimension to zero. + std::erase_if(data_, [&](const std::pair& p) { + return dir.get_dim_val(p.first) == 0.0f; + }); + } + + /** + * @brief Gets the non-zero dimensions of this vector. + */ + inline std::vector get_non_zero_dims() const { + std::vector non_zero_dims; for (auto& p : data_) { - // TODO: Instead of zeroing the dimension, it should be removed - // from the map. - if (dir.get_dim_val(p.first) == 0.f) - p.second = 0.f; + if (p.second != 0.0f) + non_zero_dims.push_back(p.first); + } + return non_zero_dims; + } + + /** + * @brief Returns true if this and other do not share any non-zero dimensions. + */ + inline bool are_dims_disjoint(const PrimitiveVector& other) const { + for (const auto& p : other.data_) { + // If this and other both have a shared dimension, then they are not + // perpendicular. + if (p.second != 0.0f && get_dim_val(p.first) != 0.0f) { + return false; + } } + // If they do not share any dimensions, then they are perpendicular. + return true; } /** @@ -268,5 +335,13 @@ class PrimitiveVector { } return res; } -}; + /** + * @brief Debug printing method. + */ + inline void print() const { + for (const auto& p : data_) { + VTR_LOG("(%zu, %f)\n", p.first, p.second); + } + } +}; diff --git a/vpr/src/base/CheckSetup.cpp b/vpr/src/base/CheckSetup.cpp index e4a5ab8c8e7..923413ac498 100644 --- a/vpr/src/base/CheckSetup.cpp +++ b/vpr/src/base/CheckSetup.cpp @@ -5,8 +5,6 @@ #include "vpr_types.h" #include "vpr_error.h" #include "globals.h" -#include "read_xml_arch_file.h" - static constexpr int DYMANIC_PORT_RANGE_MIN = 49152; static constexpr int DYNAMIC_PORT_RANGE_MAX = 65535; @@ -36,7 +34,6 @@ void CheckSetup(const t_packer_opts& packer_opts, } } - if ((GLOBAL == router_opts.route_type) && (placer_opts.place_algorithm.is_timing_driven())) { /* Works, but very weird. Can't optimize timing well, since you're @@ -58,16 +55,14 @@ void CheckSetup(const t_packer_opts& packer_opts, "A block location file requires that placement is enabled.\n"); } - if (placer_opts.place_algorithm.is_timing_driven() && - placer_opts.place_static_move_prob.size() > NUM_PL_MOVE_TYPES) { + if (placer_opts.place_algorithm.is_timing_driven() && placer_opts.place_static_move_prob.size() > NUM_PL_MOVE_TYPES) { VPR_FATAL_ERROR(VPR_ERROR_OTHER, "The number of provided placer move probabilities (%d) should equal or less than the total number of supported moves (%d).\n", placer_opts.place_static_move_prob.size(), NUM_PL_MOVE_TYPES); } - if (!placer_opts.place_algorithm.is_timing_driven() && - placer_opts.place_static_move_prob.size() > NUM_PL_NONTIMING_MOVE_TYPES) { + if (!placer_opts.place_algorithm.is_timing_driven() && placer_opts.place_static_move_prob.size() > NUM_PL_NONTIMING_MOVE_TYPES) { VPR_FATAL_ERROR(VPR_ERROR_OTHER, "The number of placer non timing move probabilities (%d) should equal to or less than the total number of supported moves (%d).\n", placer_opts.place_static_move_prob.size(), @@ -87,10 +82,11 @@ void CheckSetup(const t_packer_opts& packer_opts, "Analytical placement should skip packing.\n"); } - // TODO: Should check that read_vpr_constraint_file is non-empty or - // check within analytical placement that the floorplanning has - // some fixed blocks somewhere. Maybe we can live without fixed - // blocks. + // Make sure that the timing tradeoff is valid. + if (ap_opts.ap_timing_tradeoff < 0.0f || ap_opts.ap_timing_tradeoff > 1.0f) { + VPR_FATAL_ERROR(VPR_ERROR_OTHER, + "ap_timing_tradeoff expects a value between 0.0 and 1.0"); + } // TODO: Should we enforce that the size of the device is fixed. This // goes with ensuring that some blocks are fixed. @@ -145,9 +141,9 @@ void CheckSetup(const t_packer_opts& packer_opts, if (server_opts.is_server_mode_enabled) { if (server_opts.port_num < DYMANIC_PORT_RANGE_MIN || server_opts.port_num > DYNAMIC_PORT_RANGE_MAX) { - VPR_FATAL_ERROR(VPR_ERROR_OTHER, - "Specified server port number `--port %d` is out of range [%d-%d]. Please specify a port number within that range.\n", - server_opts.port_num, DYMANIC_PORT_RANGE_MIN, DYNAMIC_PORT_RANGE_MAX); + VPR_FATAL_ERROR(VPR_ERROR_OTHER, + "Specified server port number `--port %d` is out of range [%d-%d]. Please specify a port number within that range.\n", + server_opts.port_num, DYMANIC_PORT_RANGE_MIN, DYNAMIC_PORT_RANGE_MAX); } } } diff --git a/vpr/src/base/SetupGrid.cpp b/vpr/src/base/SetupGrid.cpp index bc88df43135..5de45ed2bf8 100644 --- a/vpr/src/base/SetupGrid.cpp +++ b/vpr/src/base/SetupGrid.cpp @@ -9,12 +9,13 @@ #include #include #include -#include #include +#include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_math.h" #include "vtr_log.h" +#include "stats.h" #include "vpr_types.h" #include "vpr_error.h" @@ -152,7 +153,7 @@ DeviceGrid create_device_grid(const std::string& layout_name, const std::vector< // //We do not support auto layout now // // // VPR_FATAL_ERROR(VPR_ERROR_ARCH, "We do not support auto layout now\n"); - + // } else { // //Use the specified device @@ -606,7 +607,7 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt // vtr::NdMatrix grid_priorities; // int num_layers = (int)grid_def.layers.size(); // vib_grid.resize(std::array{(size_t)num_layers, grid_width, grid_height}); - + // //Track the current priority for each grid location // // Note that we initialize it to the lowest (i.e. most negative) possible value, so // // any user-specified priority will override the default empty grid @@ -1155,59 +1156,6 @@ static void CheckGrid(const DeviceGrid& grid) { } } -float calculate_device_utilization(const DeviceGrid& grid, const std::map& instance_counts) { - //Record the resources of the grid - std::map grid_resources; - for (int layer_num = 0; layer_num < grid.get_num_layers(); ++layer_num) { - for (int x = 0; x < (int)grid.width(); ++x) { - for (int y = 0; y < (int)grid.height(); ++y) { - int width_offset = grid.get_width_offset({x, y, layer_num}); - int height_offset = grid.get_height_offset({x, y, layer_num}); - if (width_offset == 0 && height_offset == 0) { - const auto& type = grid.get_physical_type({x, y, layer_num}); - ++grid_resources[type]; - } - } - } - } - - //Determine the area of grid in tile units - float grid_area = 0.; - for (auto& kv : grid_resources) { - t_physical_tile_type_ptr type = kv.first; - size_t count = kv.second; - - float type_area = type->width * type->height; - - grid_area += type_area * count; - } - - //Determine the area of instances in tile units - float instance_area = 0.; - for (auto& kv : instance_counts) { - if (is_empty_type(kv.first)) { - continue; - } - - t_physical_tile_type_ptr type = pick_physical_type(kv.first); - - size_t count = kv.second; - - float type_area = type->width * type->height; - - //Instances of multi-capaicty blocks take up less space - if (type->capacity != 0) { - type_area /= type->capacity; - } - - instance_area += type_area * count; - } - - float utilization = instance_area / grid_area; - - return utilization; -} - size_t count_grid_tiles(const DeviceGrid& grid) { return grid.get_num_layers() * grid.width() * grid.height(); } diff --git a/vpr/src/base/SetupGrid.h b/vpr/src/base/SetupGrid.h index 53b4cdbf71d..81f97352e33 100644 --- a/vpr/src/base/SetupGrid.h +++ b/vpr/src/base/SetupGrid.h @@ -25,14 +25,6 @@ DeviceGrid create_device_grid(const std::string& layout_name, DeviceGrid create_device_grid(const std::string& layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); -/** - * @brief Calculate the device utilization - * - * Calculate the device utilization (i.e. fraction of used grid tiles) - * foor the specified grid and resource requirements - */ -float calculate_device_utilization(const DeviceGrid& grid, const std::map& instance_counts); - /** * @brief Returns the effective size of the device * (size of the bounding box of non-empty grid tiles) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 53c6831b676..000e1ba2b59 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -1,6 +1,7 @@ #include #include +#include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_util.h" #include "vtr_log.h" @@ -24,6 +25,8 @@ #include "ShowSetup.h" static void SetupNetlistOpts(const t_options& Options, t_netlist_opts& NetlistOpts); +static void SetupAPOpts(const t_options& options, + t_ap_opts& apOpts); static void SetupPackerOpts(const t_options& Options, t_packer_opts* PackerOpts); static void SetupPlacerOpts(const t_options& Options, @@ -43,15 +46,14 @@ static void SetupSwitches(const t_arch& Arch, static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysis_opts); static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch); -static void SetupVibInf(const std::vector& PhysicalTileTypes, - const std::vector& Switches, - const std::vector& Segments, +static void SetupVibInf(const std::vector& PhysicalTileTypes, + const std::vector& Switches, + const std::vector& Segments, std::vector& vib_infs); static void ProcessFromOrToTokens(const std::vector Tokens, const std::vector& PhysicalTileTypes, const std::vector segments, std::vector& froms); static void parse_pin_name(const char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); - /** * @brief Identify which switch must be used for *track* to *IPIN* connections based on architecture file specification. * @param Arch Architecture file specification @@ -141,6 +143,7 @@ void SetupVPR(const t_options* options, fileNameOpts->read_vpr_constraints_file = options->read_vpr_constraints_file; fileNameOpts->write_vpr_constraints_file = options->write_vpr_constraints_file; fileNameOpts->write_constraints_file = options->write_constraints_file; + fileNameOpts->read_flat_place_file = options->read_flat_place_file; fileNameOpts->write_flat_place_file = options->write_flat_place_file; fileNameOpts->write_block_usage = options->write_block_usage; @@ -238,10 +241,14 @@ void SetupVPR(const t_options* options, SetupRoutingArch(*arch, routingArch); SetupTiming(*options, timingenabled, timing); SetupPackerOpts(*options, packerOpts); + SetupAPOpts(*options, *apOpts); routingArch->write_rr_graph_filename = options->write_rr_graph_file; routingArch->read_rr_graph_filename = options->read_rr_graph_file; + routingArch->read_rr_edge_override_filename = options->read_rr_edge_override_file; - SetupVibInf(device_ctx.physical_tile_types, arch->switches, arch->Segments, arch->vib_infs); + if (!arch->vib_infs.empty()) { + SetupVibInf(device_ctx.physical_tile_types, arch->switches, arch->Segments, arch->vib_infs); + } for (auto has_global_routing : arch->layer_global_routing) { device_ctx.inter_cluster_prog_routing_resources.emplace_back(has_global_routing); @@ -368,7 +375,7 @@ static void SetupSwitches(const t_arch& Arch, auto& device_ctx = g_vpr_ctx.mutable_device(); int switches_to_copy = (int)arch_switches.size(); - int num_arch_switches = (int)arch_switches.size();; + int num_arch_switches = (int)arch_switches.size(); find_ipin_cblock_switch_index(Arch, RoutingArch->wire_to_arch_ipin_switch, RoutingArch->wire_to_arch_ipin_switch_between_dice); @@ -561,7 +568,24 @@ static void SetupAnnealSched(const t_options& Options, } /** - * @brief Sets up the s_packer_opts structure based on users inputs and + * @brief Sets up the t_ap_opts structure based on users inputs and + * on the architecture specified. + * + * Error checking, such as checking for conflicting params is assumed + * to be done beforehand + */ +void SetupAPOpts(const t_options& options, + t_ap_opts& apOpts) { + apOpts.analytical_solver_type = options.ap_analytical_solver.value(); + apOpts.partial_legalizer_type = options.ap_partial_legalizer.value(); + apOpts.full_legalizer_type = options.ap_full_legalizer.value(); + apOpts.detailed_placer_type = options.ap_detailed_placer.value(); + apOpts.ap_timing_tradeoff = options.ap_timing_tradeoff.value(); + apOpts.log_verbosity = options.ap_verbosity.value(); +} + +/** + * @brief Sets up the t_packer_opts structure based on users inputs and * on the architecture specified. * * Error checking, such as checking for conflicting params is assumed @@ -578,7 +602,7 @@ void SetupPackerOpts(const t_options& Options, } //TODO: document? - PackerOpts->global_clocks = true; /* DEFAULT */ + PackerOpts->global_clocks = true; /* DEFAULT */ PackerOpts->allow_unrelated_clustering = Options.allow_unrelated_clustering; PackerOpts->connection_driven = Options.connection_driven_clustering; @@ -597,10 +621,6 @@ void SetupPackerOpts(const t_options& Options, PackerOpts->feasible_block_array_size = Options.pack_feasible_block_array_size; PackerOpts->use_attraction_groups = Options.use_attraction_groups; - //TODO: document? - PackerOpts->inter_cluster_net_delay = 1.0; /* DEFAULT */ - PackerOpts->auto_compute_inter_cluster_net_delay = true; - PackerOpts->device_layout = Options.device_layout; PackerOpts->timing_update_type = Options.timing_update_type; @@ -699,6 +719,7 @@ static void SetupPlacerOpts(const t_options& Options, t_placer_opts* PlacerOpts) PlacerOpts->place_constraint_subtile = Options.place_constraint_subtile; PlacerOpts->floorplan_num_horizontal_partitions = Options.floorplan_num_horizontal_partitions; PlacerOpts->floorplan_num_vertical_partitions = Options.floorplan_num_vertical_partitions; + PlacerOpts->place_quench_only = Options.place_quench_only; PlacerOpts->seed = Options.Seed; @@ -773,8 +794,6 @@ static void SetupNocOpts(const t_options& Options, t_noc_opts* NocOpts) { } NocOpts->noc_sat_routing_log_search_progress = Options.noc_sat_routing_log_search_progress; NocOpts->noc_placement_file_name = Options.noc_placement_file_name; - - } static void SetupServerOpts(const t_options& Options, t_server_opts* ServerOpts) { @@ -1017,9 +1036,9 @@ static void do_reachability_analysis(t_physical_tile_type* physical_tile, } } -static void SetupVibInf(const std::vector& PhysicalTileTypes, - const std::vector& switches, - const std::vector& Segments, +static void SetupVibInf(const std::vector& PhysicalTileTypes, + const std::vector& switches, + const std::vector& Segments, std::vector& vib_infs) { VTR_ASSERT(!vib_infs.empty()); for (auto& vib_inf : vib_infs) { @@ -1063,10 +1082,9 @@ static void SetupVibInf(const std::vector& PhysicalTileTyp auto from_tokens = second_stage.from_tokens; for (const auto& from_token : from_tokens) { ProcessFromOrToTokens(from_token, PhysicalTileTypes, Segments, second_stage.froms); - } + } } vib_inf.set_second_stages(second_stages); - } } @@ -1080,8 +1098,7 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s from_inf.type_name = token[0]; from_inf.from_type = MUX; froms.push_back(from_inf); - } - else if (token.size() == 2) { + } else if (token.size() == 2) { std::string from_type_name = token[0]; e_multistage_mux_from_or_to_type from_type; for (int i_phy_type = 0; i_phy_type < (int)PhysicalTileTypes.size(); i_phy_type++) { @@ -1094,7 +1111,7 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s pb_type_name = new char[strlen(Token_char)]; port_name = new char[strlen(Token_char)]; parse_pin_name(Token_char, &start_pin_index, &end_pin_index, pb_type_name, port_name); - + std::vector all_sub_tile_to_tile_pin_indices; for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { int sub_tile_capacity = sub_tile.capacity.total(); @@ -1114,7 +1131,7 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s } for (int pin_num = start; pin_num <= end; ++pin_num) { VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); - for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { + for (int capacity = 0; capacity < sub_tile_capacity; ++capacity) { int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; all_sub_tile_to_tile_pin_indices.push_back(physical_pin_index); @@ -1140,14 +1157,14 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s from_inf.phy_pin_index = all_sub_tile_to_tile_pin_indices[i]; froms.push_back(from_inf); } - + // for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { // //int sub_tile_index = sub_tile.index; // int sub_tile_capacity = sub_tile.capacity.total(); // int i_port = 0; // for (; i_port < (int)sub_tile.ports.size(); ++i_port) { - + // if (!strcmp(sub_tile.ports[i_port].name, port_name)) { // if (start_pin_index == end_pin_index && start_pin_index < 0) { // start_pin_index = 0; @@ -1177,7 +1194,6 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s // } // } // } - } } for (int i_seg_type = 0; i_seg_type < (int)segments.size(); i_seg_type++) { @@ -1197,14 +1213,13 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s from_inf.seg_index = seg_index; froms.push_back(from_inf); } - + break; } } VTR_ASSERT(from_type == PB || from_type == SEGMENT); - - } - else { + + } else { std::string msg = vtr::string_fmt("Failed to parse vib mux from information '%s'", Token.c_str()); VTR_LOGF_ERROR(__FILE__, __LINE__, msg.c_str()); } @@ -1225,9 +1240,8 @@ static void parse_pin_name(const char* src_string, int* start_pin_index, int* en /* Format "pb_type_name.port_name" */ *start_pin_index = *end_pin_index = -1; - strcpy(source_string, src_string); - + for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { if (source_string[ichar] == '.') source_string[ichar] = ' '; @@ -1269,7 +1283,7 @@ static void parse_pin_name(const char* src_string, int* start_pin_index, int* en "The end_pin_index and start_pin_index can be the same.\n", src_string); exit(1); - } + } } if (*end_pin_index < 0 || *start_pin_index < 0) { VTR_LOG_ERROR( diff --git a/vpr/src/base/SetupVibGrid.cpp b/vpr/src/base/SetupVibGrid.cpp index 98bd676f058..7a16df722cd 100644 --- a/vpr/src/base/SetupVibGrid.cpp +++ b/vpr/src/base/SetupVibGrid.cpp @@ -35,7 +35,7 @@ VibDeviceGrid create_vib_device_grid(std::string layout_name, const std::vector< //We do not support auto layout now // VPR_FATAL_ERROR(VPR_ERROR_ARCH, "We do not support auto layout now\n"); - + } else { //Use the specified device @@ -78,7 +78,7 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ vtr::NdMatrix grid_priorities; int num_layers = (int)grid_def.layers.size(); vib_grid.resize(std::array{(size_t)num_layers, grid_width, grid_height}); - + //Track the current priority for each grid location // Note that we initialize it to the lowest (i.e. most negative) possible value, so // any user-specified priority will override the default empty grid @@ -200,7 +200,7 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ //The minimum increment is the block dimension //VTR_ASSERT(type->width > 0); - if (incrx < 1/*size_t(type->width)*/) { + if (incrx < 1 /*size_t(type->width)*/) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification incrx for block type '%s' must be at least" " block width (%d) to avoid overlapping instances (was %s = %d)", @@ -208,7 +208,7 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ } //VTR_ASSERT(type->height > 0); - if (incry < 1/*size_t(type->height)*/) { + if (incry < 1 /*size_t(type->height)*/) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification incry for block type '%s' must be at least" " block height (%d) to avoid overlapping instances (was %s = %d)", @@ -336,13 +336,14 @@ static void set_vib_grid_block_type(int priority, // //We arbitrarily decide to take the 'last applied' wins approach, and warn the user //about the potential ambiguity + std::string type_name = (type == nullptr) ? "nullptr" : type->get_name(); VTR_LOG_WARN( "Ambiguous block type specification at grid location (%zu,%zu)." " Existing block type '%s' at (%zu,%zu) has the same priority (%d) as new overlapping type '%s'." " The last specification will apply.\n", x_root, y_root, max_priority_type_loc.type->get_name().c_str(), max_priority_type_loc.x, max_priority_type_loc.y, - priority, type->get_name().c_str()); + priority, type_name.c_str()); } //Mark all the grid tiles 'covered' by this block with the appropriate type @@ -361,7 +362,7 @@ static void set_vib_grid_block_type(int priority, if (grid_tile != nullptr //&& grid_tile.type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE - ) { + ) { //We are overriding a non-empty block, we need to be careful //to ensure we remove any blocks which will be invalidated when we //overwrite part of their locations diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index b89c21ca4e2..f21200e97ee 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -1,17 +1,15 @@ -#include -#include - -#include "vtr_assert.h" -#include "vtr_log.h" -#include "vpr_types.h" -#include "vpr_error.h" +#include "ShowSetup.h" +#include "ap_flow_enums.h" #include "globals.h" -#include "echo_files.h" -#include "read_options.h" -#include "read_xml_arch_file.h" -#include "ShowSetup.h" +#include "physical_types_util.h" +#include "vpr_error.h" +#include "vpr_types.h" +#include "vtr_assert.h" +#include "vtr_log.h" +#include +#include /******** Function Prototypes ********/ static void ShowPackerOpts(const t_packer_opts& PackerOpts); @@ -254,6 +252,9 @@ static void ShowRouterOpts(const t_router_opts& RouterOpts) { VTR_LOG("RouterOpts.router_algorithm: "); switch (RouterOpts.router_algorithm) { + case NESTED: + VTR_LOG("NESTED\n"); + break; case PARALLEL: VTR_LOG("PARALLEL\n"); break; @@ -597,8 +598,59 @@ static void ShowPlacerOpts(const t_placer_opts& PlacerOpts) { } static void ShowAnalyticalPlacerOpts(const t_ap_opts& APOpts) { - (void)APOpts; - // Currently nothing to show, but will happen eventually. + VTR_LOG("AnalyticalPlacerOpts.analytical_solver_type: "); + switch (APOpts.analytical_solver_type) { + case e_ap_analytical_solver::QP_Hybrid: + VTR_LOG("qp-hybrid\n"); + break; + case e_ap_analytical_solver::LP_B2B: + VTR_LOG("lp-b2b\n"); + break; + default: + VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown analytical_solver_type\n"); + } + + VTR_LOG("AnalyticalPlacerOpts.partial_legalizer_type: "); + switch (APOpts.partial_legalizer_type) { + case e_ap_partial_legalizer::BiPartitioning: + VTR_LOG("bipartitioning\n"); + break; + case e_ap_partial_legalizer::FlowBased: + VTR_LOG("flow-based\n"); + break; + default: + VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown partial_legalizer_type\n"); + } + + VTR_LOG("AnalyticalPlacerOpts.full_legalizer_type: "); + switch (APOpts.full_legalizer_type) { + case e_ap_full_legalizer::Naive: + VTR_LOG("naive\n"); + break; + case e_ap_full_legalizer::APPack: + VTR_LOG("appack\n"); + break; + case e_ap_full_legalizer::Basic_Min_Disturbance: + VTR_LOG("basic-min-disturbance\n"); + break; + default: + VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown full_legalizer_type\n"); + } + + VTR_LOG("AnalyticalPlacerOpts.detailed_placer_type: "); + switch (APOpts.detailed_placer_type) { + case e_ap_detailed_placer::Identity: + VTR_LOG("none\n"); + break; + case e_ap_detailed_placer::Annealer: + VTR_LOG("annealer\n"); + break; + default: + VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown detailed_placer_type\n"); + } + + VTR_LOG("AnalyticalPlacerOpts.ap_timing_tradeoff: %f\n", APOpts.ap_timing_tradeoff); + VTR_LOG("AnalyticalPlacerOpts.log_verbosity: %d\n", APOpts.log_verbosity); } static void ShowNetlistOpts(const t_netlist_opts& NetlistOpts) { @@ -706,7 +758,6 @@ static void ShowPackerOpts(const t_packer_opts& PackerOpts) { } VTR_LOG("PackerOpts.connection_driven: %s", (PackerOpts.connection_driven ? "true\n" : "false\n")); VTR_LOG("PackerOpts.global_clocks: %s", (PackerOpts.global_clocks ? "true\n" : "false\n")); - VTR_LOG("PackerOpts.inter_cluster_net_delay: %f\n", PackerOpts.inter_cluster_net_delay); VTR_LOG("PackerOpts.timing_driven: %s", (PackerOpts.timing_driven ? "true\n" : "false\n")); VTR_LOG("PackerOpts.target_external_pin_util: %s", vtr::join(PackerOpts.target_external_pin_util, " ").c_str()); VTR_LOG("\n"); diff --git a/vpr/src/base/atom_lookup.cpp b/vpr/src/base/atom_lookup.cpp index eb597ff8abd..c487e5e6549 100644 --- a/vpr/src/base/atom_lookup.cpp +++ b/vpr/src/base/atom_lookup.cpp @@ -4,51 +4,6 @@ #include "vtr_optional.h" #include "atom_lookup.h" -/* - * PB - */ -const t_pb* AtomLookup::atom_pb(const AtomBlockId blk_id) const { - auto iter = atom_to_pb_.find(blk_id); - if (iter == atom_to_pb_.end()) { - //Not found - return nullptr; - } - return iter->second; -} - -AtomBlockId AtomLookup::pb_atom(const t_pb* pb) const { - auto iter = atom_to_pb_.find(pb); - if (iter == atom_to_pb_.inverse_end()) { - //Not found - return AtomBlockId::INVALID(); - } - return iter->second; -} - -const t_pb_graph_node* AtomLookup::atom_pb_graph_node(const AtomBlockId blk_id) const { - const t_pb* pb = atom_pb(blk_id); - if (pb) { - //Found - return pb->pb_graph_node; - } - return nullptr; -} - -void AtomLookup::set_atom_pb(const AtomBlockId blk_id, const t_pb* pb) { - //If either of blk_id or pb are not valid, - //remove any mapping - - if (!blk_id && pb) { - //Remove - atom_to_pb_.erase(pb); - } else if (blk_id && !pb) { - //Remove - atom_to_pb_.erase(blk_id); - } else if (blk_id && pb) { - //If both are valid store the mapping - atom_to_pb_.update(blk_id, pb); - } -} /* * PB Pins @@ -112,8 +67,8 @@ void AtomLookup::add_atom_clb_net(const AtomNetId atom_net, const ClusterNetId c clb_net_to_atom_net_[clb_net] = atom_net; } -void AtomLookup::remove_clb_net(const ClusterNetId clb_net){ - if(!clb_net_to_atom_net_.count(clb_net)) +void AtomLookup::remove_clb_net(const ClusterNetId clb_net) { + if (!clb_net_to_atom_net_.count(clb_net)) return; auto atom_net = clb_net_to_atom_net_[clb_net]; @@ -124,11 +79,11 @@ void AtomLookup::remove_clb_net(const ClusterNetId clb_net){ /* Remove mapping for given atom net */ void AtomLookup::remove_atom_net(const AtomNetId atom_net) { - if(!atom_net_to_clb_nets_.count(atom_net)) + if (!atom_net_to_clb_nets_.count(atom_net)) return; auto cluster_nets = atom_net_to_clb_nets_[atom_net]; - for(auto c: cluster_nets){ + for (auto c : cluster_nets) { clb_net_to_atom_net_.erase(c); } atom_net_to_clb_nets_.erase(atom_net); diff --git a/vpr/src/base/atom_lookup.h b/vpr/src/base/atom_lookup.h index fdf17cddd46..8a218fae207 100644 --- a/vpr/src/base/atom_lookup.h +++ b/vpr/src/base/atom_lookup.h @@ -14,6 +14,7 @@ #include "tatum/TimingGraphFwd.hpp" #include "vtr_optional.h" +#include "atom_pb_bimap.h" /** * @brief The AtomLookup class describes the mapping between components in the AtomNetlist @@ -31,23 +32,45 @@ class AtomLookup { */ /** - * @brief Returns the leaf pb associated with the atom blk_id - * @note this is the lowest level pb which corresponds directly to the atom block + * @brief Sets the atom to pb bimap access lock to value. + * If set to true, access to the bimap is prohibited and will result in failing assertions. + * + * @param value Value to set to lock to */ - const t_pb* atom_pb(const AtomBlockId blk_id) const; - - ///@brief Returns the atom block id associated with pb - AtomBlockId pb_atom(const t_pb* pb) const; - - ///@brief Conveneince wrapper around atom_pb to access the associated graph node - const t_pb_graph_node* atom_pb_graph_node(const AtomBlockId blk_id) const; + inline void set_atom_pb_bimap_lock(bool value) { + VTR_ASSERT_SAFE_MSG(lock_atom_pb_bimap_ != value, "Double locking or unlocking the atom pb bimap lock"); + lock_atom_pb_bimap_ = value; + } + + /// @brief Gets the current atom to pb bimap lock value. + inline bool atom_pb_bimap_islocked() const { return lock_atom_pb_bimap_; } + + // All accesses, mutable or immutable, to the atom to pb bimap + // will result in failing assertions if the lock is set to true. + // This is done to make sure there is only a single source of + // data in places that are supposed to use a local data structure + // instead of the global context. + + /// @brief Returns a mutable reference to the atom to pb bimap, provided that access to it is unlocked. It will result in a crash otherwise. + /// @return Mutable reference to the atom pb bimap. + inline AtomPBBimap& mutable_atom_pb_bimap() { + VTR_ASSERT(!lock_atom_pb_bimap_); + return atom_to_pb_bimap_; + } + + /// @brief Returns an immutable reference to the atom to pb bimap, provided that access to it is unlocked. It will result in a crash otherwise. + /// @return Immutable reference to the atom pb bimap. + inline const AtomPBBimap& atom_pb_bimap() const { + VTR_ASSERT(!lock_atom_pb_bimap_); + return atom_to_pb_bimap_; + } /** - * @brief Sets the bidirectional mapping between an atom and pb - * - * If either blk_id or pb are not valid any, existing mapping is removed + * @brief Set atom to pb bimap + * + * @param atom_to_pb Reference to AtomPBBimab to be copied from */ - void set_atom_pb(const AtomBlockId blk_id, const t_pb* pb); + void set_atom_to_pb_bimap(const AtomPBBimap& atom_to_pb) { atom_to_pb_bimap_ = atom_to_pb; } /* * PB Pins @@ -112,7 +135,12 @@ class AtomLookup { private: //Types private: - vtr::bimap atom_to_pb_; + /** + * @brief Allows or disallows access to the AtomPBBimap data. + * Useful to make sure global context is not accessed in places you don't want it to. + */ + bool lock_atom_pb_bimap_ = false; + AtomPBBimap atom_to_pb_bimap_; vtr::vector_map atom_pin_to_pb_graph_pin_; diff --git a/vpr/src/base/blk_loc_registry.cpp b/vpr/src/base/blk_loc_registry.cpp index 70f809cdcd9..2e5b1f2c5bb 100644 --- a/vpr/src/base/blk_loc_registry.cpp +++ b/vpr/src/base/blk_loc_registry.cpp @@ -1,18 +1,66 @@ #include "blk_loc_registry.h" +#include "device_grid.h" #include "move_transactions.h" #include "globals.h" +#include "physical_types_util.h" +#include "vpr_context.h" +#include "vpr_utils.h" BlkLocRegistry::BlkLocRegistry() : expected_transaction_(e_expected_transaction::APPLY) {} +void BlkLocRegistry::init() { + const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; + const DeviceGrid& device_grid = g_vpr_ctx.device().grid; + auto& block_locs = mutable_block_locs(); + auto& grid_blocks = mutable_grid_blocks(); + + /* Initialize the lookup of CLB block positions */ + block_locs.clear(); + block_locs.resize(clb_nlist.blocks().size()); + + /* Initialize the reverse lookup of CLB block positions */ + grid_blocks.init_grid_blocks(device_grid); + + /* Initialize the grid blocks to empty. + * Initialize all the blocks to unplaced. + */ + clear_all_grid_locs(); +} + +void BlkLocRegistry::alloc_and_load_movable_blocks() { + const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; + const auto& logical_block_types = g_vpr_ctx.device().logical_block_types; + const auto& all_block_locs = block_locs(); + auto& movable_blocks = mutable_movable_blocks(); + auto& movable_blocks_per_type = mutable_movable_blocks_per_type(); + + // TODO: Are these clears necessary? + movable_blocks.clear(); + movable_blocks_per_type.clear(); + + movable_blocks_per_type.resize(logical_block_types.size()); + + // Iterate over all clustered blocks and store block ids of movable ones. + for (ClusterBlockId blk_id : clb_nlist.blocks()) { + const t_block_loc& loc = all_block_locs[blk_id]; + if (!loc.is_fixed) { + movable_blocks.push_back(blk_id); + + const t_logical_block_type_ptr block_type = clb_nlist.block_type(blk_id); + movable_blocks_per_type[block_type->index].push_back(blk_id); + } + } +} + const vtr::vector_map& BlkLocRegistry::block_locs() const { - return block_locs_; + return block_locs_; } vtr::vector_map& BlkLocRegistry::mutable_block_locs() { - return block_locs_; + return block_locs_; } const GridBlock& BlkLocRegistry::grid_blocks() const { @@ -44,14 +92,6 @@ int BlkLocRegistry::net_pin_to_tile_pin_index(const ClusterNetId net_id, int net return this->tile_pin_index(pin_id); } -const PlaceMacros& BlkLocRegistry::place_macros() const { - return place_macros_; -} - -PlaceMacros& BlkLocRegistry::mutable_place_macros() { - return place_macros_; -} - void BlkLocRegistry::set_block_location(ClusterBlockId blk_id, const t_pl_loc& location) { const auto& device_ctx = g_vpr_ctx.device(); const auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -201,9 +241,9 @@ void BlkLocRegistry::apply_move_blocks(const t_pl_blocks_to_be_moved& blocks_aff block_locs_[blk].loc = new_loc; // get physical tile type of the old location - t_physical_tile_type_ptr old_type = device_ctx.grid.get_physical_type({old_loc.x,old_loc.y,old_loc.layer}); + t_physical_tile_type_ptr old_type = device_ctx.grid.get_physical_type({old_loc.x, old_loc.y, old_loc.layer}); // get physical tile type of the new location - t_physical_tile_type_ptr new_type = device_ctx.grid.get_physical_type({new_loc.x,new_loc.y, new_loc.layer}); + t_physical_tile_type_ptr new_type = device_ctx.grid.get_physical_type({new_loc.x, new_loc.y, new_loc.layer}); // if physical tile type of old location does not equal physical tile type of new location, sync the new physical pins if (old_type != new_type) { diff --git a/vpr/src/base/blk_loc_registry.h b/vpr/src/base/blk_loc_registry.h index 9d3704f2c1c..145e15867c6 100644 --- a/vpr/src/base/blk_loc_registry.h +++ b/vpr/src/base/blk_loc_registry.h @@ -1,11 +1,10 @@ -#ifndef VTR_BLK_LOC_REGISTRY_H -#define VTR_BLK_LOC_REGISTRY_H + +#pragma once #include "clustered_netlist_fwd.h" #include "vtr_vector_map.h" #include "vpr_types.h" #include "grid_block.h" -#include "place_macro.h" struct t_block_loc; struct t_pl_blocks_to_be_moved; @@ -27,6 +26,15 @@ class BlkLocRegistry { BlkLocRegistry(BlkLocRegistry&&) = delete; BlkLocRegistry& operator=(BlkLocRegistry&&) = delete; + /// @brief Initialize the block loc registry's internal data. Must be called + /// before any other method is called. + void init(); + + /// @brief Iterates over all of the placed blocks and stores block IDs of + /// moveable ones. Must be called after the fixed blocks have been + /// marked and before using the movable_blocks. + void alloc_and_load_movable_blocks(); + private: ///@brief Clustered block placement locations vtr::vector_map block_locs_; @@ -37,14 +45,13 @@ class BlkLocRegistry { ///@brief Clustered pin placement mapping with physical pin vtr::vector_map physical_pins_; - /** - * @brief Contains information about placement macros. - * A placement macro is a set of clustered blocks that must be placed - * in a way that is compliant with relative locations specified by the macro. - */ - PlaceMacros place_macros_; + /// @brief Stores ClusterBlockId of all movable clustered blocks + /// (blocks that are not locked down to a single location) + std::vector movable_blocks_; public: + ///@brief Stores ClusterBlockId of all movable clustered blocks of each block type + std::vector> movable_blocks_per_type_; const vtr::vector_map& block_locs() const; vtr::vector_map& mutable_block_locs(); @@ -60,11 +67,19 @@ class BlkLocRegistry { ///@brief Returns the physical pin of the tile, related to the given ClusterNedId, and the net pin index. int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index) const; - ///@brief Returns a constant reference to placement macros. - const PlaceMacros& place_macros() const; + /// @brief Returns a constant reference to the vector of ClusterBlockIds of all movable clustered blocks. + const std::vector& movable_blocks() const { return movable_blocks_; } + + /// @brief Returns a mutable reference to the vector of ClusterBlockIds of all movable clustered blocks. + std::vector& mutable_movable_blocks() { return movable_blocks_; } - ///@brief Returns a mutable reference to placement macros. - PlaceMacros& mutable_place_macros(); + /// @brief Returns a constant reference to a vector of vectors, where each inner vector contains ClusterBlockIds + /// of movable clustered blocks for a specific block type + const std::vector>& movable_blocks_per_type() const { return movable_blocks_per_type_; } + + /// @brief Returns a mutable reference to a vector of vectors, where each inner vector contains ClusterBlockIds + /// of movable clustered blocks for a specific block type. + std::vector>& mutable_movable_blocks_per_type() { return movable_blocks_per_type_; } /** * @brief Performs error checking to see if location is legal for block type, @@ -149,5 +164,3 @@ class BlkLocRegistry { e_expected_transaction expected_transaction_; }; - -#endif //VTR_BLK_LOC_REGISTRY_H diff --git a/vpr/src/base/check_netlist.cpp b/vpr/src/base/check_netlist.cpp index cd800003a5f..a80e3d7d76c 100644 --- a/vpr/src/base/check_netlist.cpp +++ b/vpr/src/base/check_netlist.cpp @@ -7,6 +7,7 @@ #include #include +#include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -16,7 +17,6 @@ #include "hash.h" #include "vpr_utils.h" #include "check_netlist.h" -#include "read_xml_arch_file.h" #define ERROR_THRESHOLD 100 diff --git a/vpr/src/base/clustered_netlist.cpp b/vpr/src/base/clustered_netlist.cpp index 180b60e35bd..2f2fce860a4 100644 --- a/vpr/src/base/clustered_netlist.cpp +++ b/vpr/src/base/clustered_netlist.cpp @@ -1,7 +1,7 @@ #include "clustered_netlist.h" - +#include "globals.h" +#include "physical_types_util.h" #include "vtr_assert.h" -#include "vpr_error.h" #include @@ -171,7 +171,7 @@ ClusterNetId ClusteredNetlist::create_net(const std::string& name) { void ClusteredNetlist::remove_block_impl(const ClusterBlockId blk_id) { //Remove & invalidate pointers - free_pb(block_pbs_[blk_id]); + free_pb(block_pbs_[blk_id], g_vpr_ctx.mutable_atom().mutable_lookup().mutable_atom_pb_bimap()); delete block_pbs_[blk_id]; block_pbs_.insert(blk_id, NULL); block_types_.insert(blk_id, NULL); diff --git a/vpr/src/base/clustered_netlist_utils.cpp b/vpr/src/base/clustered_netlist_utils.cpp index 8fbdff8b658..798c03ca250 100644 --- a/vpr/src/base/clustered_netlist_utils.cpp +++ b/vpr/src/base/clustered_netlist_utils.cpp @@ -45,8 +45,8 @@ void ClusterAtomsLookup::init_lookup() { cluster_atoms.resize(cluster_ctx.clb_nlist.blocks().size()); - for (auto atom_blk_id : atom_ctx.nlist.blocks()) { - ClusterBlockId clb_index = atom_ctx.lookup.atom_clb(atom_blk_id); + for (auto atom_blk_id : atom_ctx.netlist().blocks()) { + ClusterBlockId clb_index = atom_ctx.lookup().atom_clb(atom_blk_id); /* if this data structure is being built alongside the clustered netlist */ /* e.g. when ingesting and legalizing a flat placement solution, some atoms */ diff --git a/vpr/src/base/flat_placement_types.h b/vpr/src/base/flat_placement_types.h new file mode 100644 index 00000000000..6ece9b2d318 --- /dev/null +++ b/vpr/src/base/flat_placement_types.h @@ -0,0 +1,141 @@ +/** + * @file + * @author Alex Singer + * @date March 2025 + * @brief Declaration of flat placement types used throughout VPR. + */ + +#pragma once + +#include "atom_netlist.h" +#include "vtr_assert.h" +#include "vtr_vector.h" + +/** + * @brief A structure representing a flat placement location on the device. + * + * This is related to the t_pl_loc type; however this uses floating point + * coordinates, allowing for blocks to be placed in illegal positions. + */ +struct t_flat_pl_loc { + float x; /**< The x-coordinate of the location. */ + float y; /**< The y-coordinate of the location. */ + float layer; /**< The layer of the location. */ + + /** + * @brief Adds the coordinates of another t_flat_pl_loc to this one. + * + * @param other The other t_flat_pl_loc whose coordinates are to be added. + * @return A reference to this t_flat_pl_loc after addition. + */ + t_flat_pl_loc& operator+=(const t_flat_pl_loc& other) { + x += other.x; + y += other.y; + layer += other.layer; + return *this; + } + + /** + * @brief Subtracts the coordinates of another t_flat_pl_loc to this one. + */ + t_flat_pl_loc& operator-=(const t_flat_pl_loc& other) { + x -= other.x; + y -= other.y; + layer -= other.layer; + return *this; + } + + /** + * @brief Divides the coordinates of this t_flat_pl_loc by a divisor. + * + * @param divisor The value by which to divide the coordinates. + * @return A reference to this t_flat_pl_loc after division. + */ + t_flat_pl_loc& operator/=(float divisor) { + x /= divisor; + y /= divisor; + layer /= divisor; + return *this; + } +}; + +/** + * @brief Flat placement storage class. + * + * This stores placement information for each atom in the netlist. It contains + * any information that may be used by the packer to better create clusters. + */ +class FlatPlacementInfo { + public: + /// @brief Identifier for an undefined position. + static constexpr float UNDEFINED_POS = -1.f; + /// @brief Identifier for an undefined sub tile. + static constexpr int UNDEFINED_SUB_TILE = -1; + /// @brief Identifier for an undefined site idx. + static constexpr int UNDEFINED_SITE_IDX = -1; + + // The following three floating point numbers describe the flat position of + // an atom block. These are floats instead of integers to allow for flat + // placements which are not quite legal (ok to be off-grid). This allows + // the flat placement to encode information about where atom blocks would + // want to go if they cannot be placed at the grid position they are at. + // (for example, a block placed at (0.9, 0.9) wants to be at tile (0, 0), + // but if thats not possible it would prefer (1, 1) over anything else. + + /// @brief The x-positions of each atom block. Is UNDEFINED_POS if undefined. + vtr::vector blk_x_pos; + /// @brief The y-positions of each atom block. Is UNDEFINED_POS if undefined. + vtr::vector blk_y_pos; + /// @brief The layer of each atom block. Is UNDEFINED_POS if undefined. + vtr::vector blk_layer; + + /// @brief The sub tile location of each atom block. Is UNDEFINED_SUB_TILE + /// if undefined. + vtr::vector blk_sub_tile; + /// @brief The flat site idx of each atom block. This is an optional index + /// into a linearized list of primitive locations within a cluster- + /// level block. Is UNDEFINED_SITE_IDX if undefined. + vtr::vector blk_site_idx; + + /// @brief A flag to signify if this object has been constructed with data + /// or not. This makes it easier to detect if a flat placement exists + /// or not. Is true when a placement has been loaded into this + /// object, false otherwise. + bool valid; + + /** + * @brief Get the flat placement location of the given atom block. + */ + inline t_flat_pl_loc get_pos(AtomBlockId blk_id) const { + VTR_ASSERT_SAFE_MSG(blk_id.is_valid(), "Block ID is invalid"); + VTR_ASSERT_SAFE_MSG(valid, "FlatPlacementInfo not initialized"); + return {blk_x_pos[blk_id], blk_y_pos[blk_id], blk_layer[blk_id]}; + } + + /** + * @brief Default constructor of this class. + * + * Initializes the data structure to invalid so it can be easily checked to + * be uninitialized. + */ + FlatPlacementInfo() + : valid(false) {} + + /** + * @brief Constructs the flat placement with undefined positions for each + * atom block in the atom netlist. + * + * The valid flag is set to true here, since this structure is now + * initialized with data and can be used. + * + * @param atom_netlist + * The netlist of atom blocks in the circuit. + */ + FlatPlacementInfo(const AtomNetlist& atom_netlist) + : blk_x_pos(atom_netlist.blocks().size(), UNDEFINED_POS) + , blk_y_pos(atom_netlist.blocks().size(), UNDEFINED_POS) + , blk_layer(atom_netlist.blocks().size(), UNDEFINED_POS) + , blk_sub_tile(atom_netlist.blocks().size(), UNDEFINED_SUB_TILE) + , blk_site_idx(atom_netlist.blocks().size(), UNDEFINED_SITE_IDX) + , valid(true) {} +}; diff --git a/vpr/src/base/flat_placement_utils.h b/vpr/src/base/flat_placement_utils.h new file mode 100644 index 00000000000..eef37489585 --- /dev/null +++ b/vpr/src/base/flat_placement_utils.h @@ -0,0 +1,20 @@ +/** + * @file + * @author Alex Singer + * @date March 2025 + * @brief Utility methods for working with flat placements. + */ + +#pragma once + +#include +#include "flat_placement_types.h" + +/** + * @brief Returns the manhattan distance (L1 distance) between two flat + * placement locations. + */ +inline float get_manhattan_distance(const t_flat_pl_loc& loc_a, + const t_flat_pl_loc& loc_b) { + return std::abs(loc_a.x - loc_b.x) + std::abs(loc_a.y - loc_b.y) + std::abs(loc_a.layer - loc_b.layer); +} diff --git a/vpr/src/base/gen/vpr_constraints_uxsdcxx.h b/vpr/src/base/gen/vpr_constraints_uxsdcxx.h index d12118cb066..6a835bf5a64 100644 --- a/vpr/src/base/gen/vpr_constraints_uxsdcxx.h +++ b/vpr/src/base/gen/vpr_constraints_uxsdcxx.h @@ -122,9 +122,9 @@ typedef const uint64_t __attribute__((aligned(1))) triehash_uu64; static_assert(alignof(triehash_uu32) == 1, "Unaligned 32-bit access not found."); static_assert(alignof(triehash_uu64) == 1, "Unaligned 64-bit access not found."); #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ -# define onechar(c, s, l) (((uint64_t)(c)) << (s)) +#define onechar(c, s, l) (((uint64_t)(c)) << (s)) #else -# define onechar(c, s, l) (((uint64_t)(c)) << (l - 8 - s)) +#define onechar(c, s, l) (((uint64_t)(c)) << (l - 8 - s)) #endif /* Tokens for attribute and node names. */ @@ -1207,7 +1207,7 @@ inline void attr_error(std::bitset astate, const char* const* lookup, const s } inline void get_line_number(const char* filename, std::ptrdiff_t target_offset, int* line, int* col) { - std::unique_ptr f(fopen(filename, "rb"), fclose); + std::unique_ptr f(fopen(filename, "rb"), fclose); if (!f) { throw std::runtime_error(std::string("Failed to open file") + filename); diff --git a/vpr/src/base/grid_block.cpp b/vpr/src/base/grid_block.cpp index 9053830473e..4a6e35b0aba 100644 --- a/vpr/src/base/grid_block.cpp +++ b/vpr/src/base/grid_block.cpp @@ -1,7 +1,28 @@ #include "grid_block.h" +#include "device_grid.h" #include "globals.h" +#include "physical_types.h" + +void GridBlock::init_grid_blocks(const DeviceGrid& device_grid) { + size_t grid_width = device_grid.width(); + size_t grid_height = device_grid.height(); + size_t num_layers = device_grid.get_num_layers(); + + /* Structure should have the same dimensions as the grid. */ + grid_blocks_.resize({num_layers, grid_width, grid_height}); + + for (size_t layer_num = 0; layer_num < num_layers; layer_num++) { + for (size_t x = 0; x < grid_width; x++) { + for (size_t y = 0; y < grid_height; y++) { + const t_physical_tile_loc tile_loc({(int)x, (int)y, (int)layer_num}); + auto type = device_grid.get_physical_type(tile_loc); + initialized_grid_block_at_location(tile_loc, type->capacity); + } + } + } +} void GridBlock::zero_initialize() { auto& device_ctx = g_vpr_ctx.device(); @@ -55,5 +76,3 @@ int GridBlock::decrement_usage(const t_physical_tile_loc& loc) { return updated_usage; } - - diff --git a/vpr/src/base/grid_block.h b/vpr/src/base/grid_block.h index 12e934f0af9..d66cbc9fa26 100644 --- a/vpr/src/base/grid_block.h +++ b/vpr/src/base/grid_block.h @@ -38,6 +38,14 @@ class GridBlock { grid_blocks_.resize({layers, width, height}); } + /** + * @brief Initialize `grid_blocks`, the inverse structure of `block_locs`. + * + * The container at each grid block location should have a length equal to the + * subtile capacity of that block. Unused subtiles would be marked ClusterBlockId::INVALID(). + */ + void init_grid_blocks(const DeviceGrid& device_grid); + inline void initialized_grid_block_at_location(const t_physical_tile_loc& loc, int num_sub_tiles) { grid_blocks_[loc.layer_num][loc.x][loc.y].blocks.resize(num_sub_tiles, ClusterBlockId::INVALID()); } diff --git a/vpr/src/base/load_flat_place.cpp b/vpr/src/base/load_flat_place.cpp index f34d1f94680..14de1c6da1f 100644 --- a/vpr/src/base/load_flat_place.cpp +++ b/vpr/src/base/load_flat_place.cpp @@ -8,11 +8,40 @@ #include "load_flat_place.h" +#include +#include #include +#include "atom_lookup.h" +#include "atom_netlist.h" #include "clustered_netlist.h" +#include "flat_placement_types.h" #include "globals.h" #include "vpr_context.h" +#include "vpr_error.h" #include "vpr_types.h" +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_vector_map.h" +#include "vtr_version.h" + +/** + * @brief Prints the header for the flat placement file. This includes helpful + * information on how to read the file and when it was generated. + * + * @param fp + * File pointer to the file the cluster is printed to. + */ +static void print_flat_placement_file_header(FILE* fp) { + fprintf(fp, "# Flat Placement File\n"); + fprintf(fp, "# Auto-generated by VPR %s\n", + vtr::VERSION); + fprintf(fp, "# Created: %s\n", + vtr::BUILD_TIMESTAMP); + fprintf(fp, "#\n"); + fprintf(fp, "# This file prints the following information for each atom in the netlist:\n"); + fprintf(fp, "# # \n"); + fprintf(fp, "\n"); +} /** * @brief Prints flat placement file entries for the atoms in one placed @@ -30,7 +59,7 @@ */ static void print_flat_cluster(FILE* fp, ClusterBlockId blk_id, - const vtr::vector_map &block_locs, + const vtr::vector_map& block_locs, const vtr::vector>& atoms_lookup) { // Atom context used to get the atom_pb for each atom in the cluster. // NOTE: This is only used for getting the flat site index. @@ -42,12 +71,13 @@ static void print_flat_cluster(FILE* fp, // Print a line for each atom. for (AtomBlockId atom : atoms_lookup[blk_id]) { // Get the atom pb graph node. - t_pb_graph_node* atom_pbgn = atom_ctx.lookup.atom_pb(atom)->pb_graph_node; + t_pb_graph_node* atom_pbgn = atom_ctx.lookup().atom_pb_bimap().atom_pb(atom)->pb_graph_node; // Print the flat placement information for this atom. - fprintf(fp, "%s %d %d %d %d #%zu %s\n", - atom_ctx.nlist.block_name(atom).c_str(), - blk_loc.x, blk_loc.y, blk_loc.sub_tile, + fprintf(fp, "%s %d %d %d %d %d #%zu %s\n", + atom_ctx.netlist().block_name(atom).c_str(), + blk_loc.x, blk_loc.y, blk_loc.layer, + blk_loc.sub_tile, atom_pbgn->flat_site_index, static_cast(blk_id), atom_pbgn->pb_type->name); @@ -56,7 +86,7 @@ static void print_flat_cluster(FILE* fp, void write_flat_placement(const char* flat_place_file_path, const ClusteredNetlist& cluster_netlist, - const vtr::vector_map &block_locs, + const vtr::vector_map& block_locs, const vtr::vector>& atoms_lookup) { // Writes the flat placement to the given flat_place_file_path. @@ -67,6 +97,9 @@ void write_flat_placement(const char* flat_place_file_path, // Create a file in write mode for the flat placement. FILE* fp = fopen(flat_place_file_path, "w"); + // Add a header to the flat placement file. + print_flat_placement_file_header(fp); + // For each cluster, write out the atoms in the cluster at this cluster's // location. for (ClusterBlockId iblk : cluster_netlist.blocks()) { @@ -77,6 +110,86 @@ void write_flat_placement(const char* flat_place_file_path, fclose(fp); } +FlatPlacementInfo read_flat_placement(const std::string& read_flat_place_file_path, + const AtomNetlist& atom_netlist) { + // Try to open the file, crash if we cannot open the file. + std::ifstream flat_place_file(read_flat_place_file_path); + if (!flat_place_file.is_open()) { + VPR_ERROR(VPR_ERROR_OTHER, "Unable to open flat placement file: %s\n", + read_flat_place_file_path.c_str()); + } + + // Create a FlatPlacementInfo object to hold the flat placement. + FlatPlacementInfo flat_placement_info(atom_netlist); + + // Read each line of the flat placement file. + unsigned line_num = 0; + std::string line; + while (std::getline(flat_place_file, line)) { + // Split the line into tokens (using spaces, tabs, etc. as delimiters). + std::vector tokens = vtr::split(line); + // Skip empty lines + if (tokens.empty()) + continue; + // Skip lines that are only comments. + if (tokens[0][0] == '#') + continue; + // Skip lines with too few arguments. + // Required arguments: + // - Atom name + // - Atom x-pos + // - Atom y-pos + // - Atom layer + // - Atom sub-tile + if (tokens.size() < 5) { + VTR_LOG_WARN("Flat placement file, line %d has too few arguments. " + "Requires at least: \n", + line_num); + continue; + } + + // Get the atom name, which should be the first argument. + AtomBlockId atom_blk_id = atom_netlist.find_block(tokens[0]); + if (!atom_blk_id.is_valid()) { + VTR_LOG_WARN("Flat placement file, line %d atom name does not match " + "any atoms in the atom netlist.\n", + line_num); + continue; + } + + // Check if this atom already has a flat placement + // Using the x_pos and y_pos as identifiers. + if (flat_placement_info.blk_x_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS + || flat_placement_info.blk_y_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS) { + VTR_LOG_WARN("Flat placement file, line %d, atom %s has multiple " + "placement definitions in the flat placement file.\n", + line_num, atom_netlist.block_name(atom_blk_id).c_str()); + continue; + } + + // Get the (x, y, layer) position of the atom. These functions have + // error checking built in. We parse these as floats to allow for + // reading in more global atom positions. + flat_placement_info.blk_x_pos[atom_blk_id] = vtr::atof(tokens[1]); + flat_placement_info.blk_y_pos[atom_blk_id] = vtr::atof(tokens[2]); + flat_placement_info.blk_layer[atom_blk_id] = vtr::atof(tokens[3]); + + // Parse the sub-tile as an integer. + flat_placement_info.blk_sub_tile[atom_blk_id] = vtr::atoi(tokens[4]); + + // If a site index is given, parse the site index as an integer. + if (tokens.size() >= 6 && tokens[5][0] != '#') + flat_placement_info.blk_site_idx[atom_blk_id] = vtr::atoi(tokens[5]); + + // Ignore any further tokens. + + line_num++; + } + + // Return the flat placement info loaded from the file. + return flat_placement_info; +} + /* ingests and legalizes a flat placement file */ bool load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { VTR_LOG("load_flat_placement(); when implemented, this function:"); @@ -88,3 +201,121 @@ bool load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { return false; } +void log_flat_placement_reconstruction_info( + const FlatPlacementInfo& flat_placement_info, + const vtr::vector_map& block_locs, + const vtr::vector>& atoms_lookup, + const AtomLookup& cluster_of_atom_lookup, + const AtomNetlist& atom_netlist, + const ClusteredNetlist& clustered_netlist) { + // Go through each cluster and see how many clusters have atoms that + // do not belong (cluster is imperfect). + unsigned num_imperfect_clusters = 0; + for (ClusterBlockId clb_blk_id : clustered_netlist.blocks()) { + // Get the centroid of the cluster + const auto& clb_atoms = atoms_lookup[clb_blk_id]; + float centroid_x = 0.f; + float centroid_y = 0.f; + float centroid_layer = 0.f; + float centroid_sub_tile = 0.f; + for (AtomBlockId atom_blk_id : clb_atoms) { + // TODO: Currently only handle the case when all of the position + // data is provided. This can be extended, + VTR_ASSERT(flat_placement_info.blk_x_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS); + VTR_ASSERT(flat_placement_info.blk_y_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS); + VTR_ASSERT(flat_placement_info.blk_layer[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS); + VTR_ASSERT(flat_placement_info.blk_sub_tile[atom_blk_id] != FlatPlacementInfo::UNDEFINED_SUB_TILE); + + centroid_x += flat_placement_info.blk_x_pos[atom_blk_id]; + centroid_y += flat_placement_info.blk_y_pos[atom_blk_id]; + centroid_layer += flat_placement_info.blk_layer[atom_blk_id]; + centroid_sub_tile += flat_placement_info.blk_sub_tile[atom_blk_id]; + } + centroid_x /= static_cast(clb_atoms.size()); + centroid_y /= static_cast(clb_atoms.size()); + centroid_layer /= static_cast(clb_atoms.size()); + centroid_sub_tile /= static_cast(clb_atoms.size()); + // Check if every atom in the cluster is within 0.5 units of the + // centroid. + for (AtomBlockId atom_blk_id : clb_atoms) { + // If the atom's flat placement more than half a block in any + // direction from the flat placement centroid, then it does not + // want to be in this cluster. + // FIXME: This should take into account large blocks somehow, just + // being 0.5 tiles away may not be sufficient. + if (std::abs(centroid_x - flat_placement_info.blk_x_pos[atom_blk_id]) > 0.5f || std::abs(centroid_y - flat_placement_info.blk_y_pos[atom_blk_id]) > 0.5f || std::abs(centroid_layer - flat_placement_info.blk_layer[atom_blk_id]) > 0.5f || std::abs(centroid_sub_tile - flat_placement_info.blk_sub_tile[atom_blk_id]) > 0.5f) { + num_imperfect_clusters++; + break; + } + } + } + // Go through each atom and compute how much it has displaced and count + // how many have been displaced beyond some threshold. + constexpr float disp_threashold = 0.5f; + float total_disp = 0.f; + float max_disp = 0.f; + unsigned num_atoms_missplaced = 0; + for (AtomBlockId atom_blk_id : atom_netlist.blocks()) { + // TODO: Currently only handle the case when all of the position + // data is provided. This can be extended, + VTR_ASSERT(flat_placement_info.blk_x_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS); + VTR_ASSERT(flat_placement_info.blk_y_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS); + VTR_ASSERT(flat_placement_info.blk_layer[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS); + VTR_ASSERT(flat_placement_info.blk_sub_tile[atom_blk_id] != FlatPlacementInfo::UNDEFINED_SUB_TILE); + + // Get the (x, y, layer) position of the block. + int blk_x = flat_placement_info.blk_x_pos[atom_blk_id]; + int blk_y = flat_placement_info.blk_y_pos[atom_blk_id]; + int blk_layer = flat_placement_info.blk_layer[atom_blk_id]; + + // Get the (x, y, layer) position of the cluster that contains this block. + ClusterBlockId atom_clb_id = cluster_of_atom_lookup.atom_clb(atom_blk_id); + const t_block_loc& clb_loc = block_locs[atom_clb_id]; + + // Compute the distance between these two positions. + // FIXME: This will overreport large blocks. This should really be + // the distance outside of the tile you want to be placed in. + float dx = blk_x - clb_loc.loc.x; + float dy = blk_y - clb_loc.loc.y; + float dlayer = blk_layer - clb_loc.loc.layer; + // Using the Manhattan distance (L1 norm) + float dist = std::abs(dx) + std::abs(dy) + std::abs(dlayer); + + // Collect the max displacement. + max_disp = std::max(max_disp, dist); + + // Accumulate into the total displacement. + total_disp += dist; + + // Check if this block has been displaced beyond the threshold. + if (dist >= disp_threashold) { + num_atoms_missplaced++; + } + + // TODO: Make this debug option of higher verbosity. Helpful for + // debugging flat placement reconstruction. + /* + * VTR_LOG("%s %d %d %d %d\n", + * g_vpr_ctx.atom().netlist().block_name(atom_blk_id).c_str(), + * clb_loc.loc.x, + * clb_loc.loc.y, + * clb_loc.loc.layer, + * clb_loc.loc.sub_tile); + */ + } + + // Log the flat placement reconstruction info. + size_t num_atoms = atom_netlist.blocks().size(); + size_t num_clusters = clustered_netlist.blocks().size(); + VTR_LOG("Flat Placement Reconstruction Info:\n"); + VTR_LOG("\tPercent of clusters with reconstruction errors: %f\n", + static_cast(num_imperfect_clusters) / static_cast(num_clusters)); + VTR_LOG("\tTotal displacement of initial placement from flat placement: %f\n", + total_disp); + VTR_LOG("\tAverage atom displacement of initial placement from flat placement: %f\n", + total_disp / static_cast(num_atoms)); + VTR_LOG("\tMax atom displacement of initial placement from flat placement: %f\n", + max_disp); + VTR_LOG("\tPercent of atoms misplaced from the flat placement: %f\n", + static_cast(num_atoms_missplaced) / static_cast(num_atoms)); +} diff --git a/vpr/src/base/load_flat_place.h b/vpr/src/base/load_flat_place.h index c70314bb7fc..3c25780fc57 100644 --- a/vpr/src/base/load_flat_place.h +++ b/vpr/src/base/load_flat_place.h @@ -10,14 +10,19 @@ #pragma once +#include #include #include "vtr_vector_map.h" #include "vtr_vector.h" // Forward declarations class AtomBlockId; +class AtomLookup; +class AtomNetlist; class ClusterBlockId; class ClusteredNetlist; +class FlatPlacementInfo; +class Prepacker; struct t_arch; struct t_block_loc; struct t_vpr_setup; @@ -37,11 +42,48 @@ struct t_vpr_setup; */ void write_flat_placement(const char* flat_place_file_path, const ClusteredNetlist& cluster_netlist, - const vtr::vector_map &block_locs, + const vtr::vector_map& block_locs, const vtr::vector>& atoms_lookup); +/** + * @brief Reads a flat placement file generated from a previous run of VTR or + * externally generated. + * + * @param read_flat_place_file_path + * Path to the file to read the flat placement from. + * @param atom_netlist + * The netlist of atom blocks in the circuit. + */ +FlatPlacementInfo read_flat_placement(const std::string& read_flat_place_file_path, + const AtomNetlist& atom_netlist); + /** * @brief A function that loads and legalizes a flat placement file */ bool load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch); +/** + * @brief Logs information on the quality of the clustering and placement + * reconstruction of the given flat placement. + * + * @param flat_placement_info + * The flat placement to log, + * @param block_locs + * The location of each cluster in the netlist. + * @param atoms_lookup + * A lookup between each cluster and the atoms it contains. + * @param cluster_of_atom_lookup + * A lookup between each atom and the cluster that contains it. + * @param atom_netlist + * The netlist of atoms the flat placement was over. + * @param clustered_netlist + * The clustered netlist that the flat placement was used to + * generate. + */ +void log_flat_placement_reconstruction_info( + const FlatPlacementInfo& flat_placement_info, + const vtr::vector_map& block_locs, + const vtr::vector>& atoms_lookup, + const AtomLookup& cluster_of_atom_lookup, + const AtomNetlist& atom_netlist, + const ClusteredNetlist& clustered_netlist); diff --git a/vpr/src/base/netlist_walker.cpp b/vpr/src/base/netlist_walker.cpp index 270a7b6745a..3411210f3cb 100644 --- a/vpr/src/base/netlist_walker.cpp +++ b/vpr/src/base/netlist_walker.cpp @@ -6,7 +6,7 @@ void NetlistWalker::walk() { auto& atom_ctx = g_vpr_ctx.atom(); auto& cluster_ctx = g_vpr_ctx.clustering(); - visitor_.visit_top(atom_ctx.nlist.netlist_name().c_str()); + visitor_.visit_top(atom_ctx.netlist().netlist_name().c_str()); for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { const auto* pb = cluster_ctx.clb_nlist.block_pb(blk_id); diff --git a/vpr/src/base/netlist_writer.cpp b/vpr/src/base/netlist_writer.cpp index d8efdab5b42..53e79a871d9 100644 --- a/vpr/src/base/netlist_writer.cpp +++ b/vpr/src/base/netlist_writer.cpp @@ -1,36 +1,3 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "vtr_assert.h" -#include "vtr_util.h" -#include "vtr_log.h" -#include "vtr_logic.h" -#include "vtr_version.h" - -#include "vpr_error.h" -#include "vpr_types.h" - -#include "read_blif.h" - -#include "netlist_walker.h" -#include "netlist_writer.h" - -#include "globals.h" -#include "atom_netlist.h" -#include "atom_netlist_utils.h" -#include "logic_vec.h" - /** * @file * @@ -89,17 +56,103 @@ * simulation. */ +#include "netlist_writer.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "atom_netlist.h" +#include "atom_netlist_utils.h" +#include "globals.h" +#include "logic_vec.h" +#include "netlist_walker.h" +#include "read_blif.h" +#include "tatum/TimingGraph.hpp" +#include "tatum/TimingGraphFwd.hpp" +#include "vpr_error.h" +#include "vpr_types.h" +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_logic.h" +#include "vtr_version.h" + /* Enable for extra output while calculating LUT masks */ //#define DEBUG_LUT_MASK +namespace { + // //File local type declarations // +/** + * @brief A triple of delay values (all delays should be in seconds). + * + * For delay values in SDF files, three numbers are specified to describe the + * minimum, typical, and maximum delays along a timing edge. + */ +struct DelayTriple { + DelayTriple() = default; + constexpr DelayTriple(double minimum_sec, double typical_sec, double maximum_sec) + : minimum(minimum_sec) + , typical(typical_sec) + , maximum(maximum_sec) {} + + /// @brief The minimum delay along a timing edge. + double minimum = std::numeric_limits::quiet_NaN(); + /// @brief The typical delay along a timing edge. + double typical = std::numeric_limits::quiet_NaN(); + /// @brief The maximum delay along a timing edge. + double maximum = std::numeric_limits::quiet_NaN(); + + /** + * @brief Returns true if the minimum, typical, and maximum delay values have + * been assigned a number. + * + * These values are defaulted to NaN, so this checks if the values have changed. + */ + inline bool has_value() const { + return !std::isnan(minimum) && !std::isnan(typical) && !std::isnan(maximum); + } + + /** + * @brief Convert the triple into a string. This string will be of the form: + * (minimum:typical:maximum) + * + * This string is expected to be written directly into an SDF file. + * + * Since the delays stored in this struct are implied to be in seconds, this + * print method converts the output into picoseconds. + */ + inline std::string str() const { + VTR_ASSERT_MSG(has_value(), + "Cannot create a non-initialized delay triple string"); + + // Convert the delays to picoseconds for printing. + double minimum_ps = minimum * 1e12; + double typical_ps = typical * 1e12; + double maximum_ps = maximum * 1e12; + + // Create the string. + std::stringstream delay_ss; + delay_ss << '(' << minimum_ps << ':' << typical_ps << ':' << maximum_ps << ')'; + return delay_ss.str(); + } +}; + // This pair cointains the following values: // - double: hold, setup or clock-to-q delays of the port // - string: port name of the associated source clock pin of the sequential port -typedef std::pair sequential_port_delay_pair; +typedef std::pair sequential_port_delay_pair; /*enum class PortType { * IN, @@ -110,8 +163,21 @@ typedef std::pair sequential_port_delay_pair; // // File local function declarations // + +/** + * @brief Get the tco delay triple for the given pb_graph pin. + */ +DelayTriple get_pin_tco_delay_triple(const t_pb_graph_pin& pin); + +/** + * @brief Get the edge delay triple for the given edge, as found in the given + * timing graph. + */ +DelayTriple get_edge_delay_triple(tatum::EdgeId edge_id, + const AnalysisDelayCalculator& delay_calc, + const tatum::TimingGraph& timing_graph); + std::string indent(size_t depth); -double get_delay_ps(double delay_sec); void print_blif_port(std::ostream& os, size_t& unconn_count, const std::string& port_name, const std::vector& nets, int depth); void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::string& port_name, const std::vector& nets, PortType type, int depth, struct t_analysis_opts& opts); @@ -138,7 +204,7 @@ class Arc { int src_ipin, /// port_conns, ///::quiet_NaN(), ///::quiet_NaN(), ///::quiet_NaN()) /// port_conns, /// port_connections_; Type type_; vtr::LogicValue initial_value_; - double tcq_; ///pin_count_in_cluster; - tatum::NodeId tnode_id = atom_ctx.lookup.atom_pin_tnode(pin); + tatum::NodeId tnode_id = atom_ctx.lookup().atom_pin_tnode(pin); auto key = std::make_pair(clb_idx, pb_pin_idx); auto value = std::make_pair(key, tnode_id); @@ -859,11 +892,11 @@ class NetlistWriterVisitor : public NetlistVisitor { void visit_atom_impl(const t_pb* atom) override { auto& atom_ctx = g_vpr_ctx.atom(); - auto atom_pb = atom_ctx.lookup.pb_atom(atom); + auto atom_pb = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); if (atom_pb == AtomBlockId::INVALID()) { return; } - const t_model* model = atom_ctx.nlist.block_model(atom_pb); + const t_model* model = atom_ctx.netlist().block_model(atom_pb); if (model->name == std::string(MODEL_INPUT)) { inputs_.emplace_back(make_io(atom, PortType::INPUT)); @@ -1072,10 +1105,7 @@ class NetlistWriterVisitor : public NetlistVisitor { sdf_os_ << indent(depth + 2) << "(DELAY\n"; sdf_os_ << indent(depth + 3) << "(ABSOLUTE\n"; - double delay = get_delay_ps(driver_tnode, sink_tnode); - - std::stringstream delay_triple; - delay_triple << "(" << delay << ":" << delay << ":" << delay << ")"; + DelayTriple delay_triple = get_src_to_sink_delay_triple(driver_tnode, sink_tnode); sdf_os_ << indent(depth + 4) << "(IOPATH datain dataout " << delay_triple.str() << " " << delay_triple.str() << ")\n"; sdf_os_ << indent(depth + 3) << ")\n"; @@ -1234,9 +1264,9 @@ class NetlistWriterVisitor : public NetlistVisitor { net = make_inst_wire(atom_net_id, src_tnode_id, inst_name, PortType::INPUT, 0, pin_idx); //Record the timing arc - float delay = get_delay_ps(src_tnode_id, sink_tnode_id); + DelayTriple delay_triple = get_src_to_sink_delay_triple(src_tnode_id, sink_tnode_id); - Arc timing_arc("in", pin_idx, "out", 0, delay); + Arc timing_arc("in", pin_idx, "out", 0, delay_triple); timing_arcs.push_back(timing_arc); } @@ -1293,6 +1323,7 @@ class NetlistWriterVisitor : public NetlistVisitor { port_conns["D"] = input_net; double tsu = pb_graph_node->input_pins[0][0].tsu; + DelayTriple tsu_triple(tsu, tsu, tsu); //Output (Q) int output_cluster_pin_idx = pb_graph_node->output_pins[0][0].pin_count_in_cluster; //Unique pin index in cluster @@ -1301,7 +1332,7 @@ class NetlistWriterVisitor : public NetlistVisitor { std::string output_net = make_inst_wire(output_atom_net_id, find_tnode(atom, output_cluster_pin_idx), inst_name, PortType::OUTPUT, 0, 0); port_conns["Q"] = output_net; - double tcq = pb_graph_node->output_pins[0][0].tco_max; + DelayTriple tcq_triple = get_pin_tco_delay_triple(pb_graph_node->output_pins[0][0]); //Clock (control) int control_cluster_pin_idx = pb_graph_node->clock_pins[0][0].pin_count_in_cluster; //Unique pin index in cluster @@ -1315,7 +1346,7 @@ class NetlistWriterVisitor : public NetlistVisitor { LatchInst::Type type = LatchInst::Type::RISING_EDGE; vtr::LogicValue init_value = vtr::LogicValue::FALSE; - return std::make_shared(inst_name, port_conns, type, init_value, tcq, tsu); + return std::make_shared(inst_name, port_conns, type, init_value, tcq_triple, tsu_triple); } /** @@ -1395,7 +1426,8 @@ class NetlistWriterVisitor : public NetlistVisitor { } input_port_conns[port_name].push_back(net); - ports_tsu[port_name] = std::make_pair(pin->tsu, pin->associated_clock_pin->port->name); + DelayTriple delay_triple(pin->tsu, pin->tsu, pin->tsu); + ports_tsu[port_name] = std::make_pair(delay_triple, pin->associated_clock_pin->port->name); } } @@ -1431,7 +1463,8 @@ class NetlistWriterVisitor : public NetlistVisitor { "Unrecognized input port class '%s' for primitive '%s' (%s)\n", port_class.c_str(), atom->name, pb_type->name); } output_port_conns[port_name].push_back(net); - ports_tcq[port_name] = std::make_pair(pin->tco_max, pin->associated_clock_pin->port->name); + DelayTriple delay_triple = get_pin_tco_delay_triple(*pin); + ports_tcq[port_name] = std::make_pair(delay_triple, pin->associated_clock_pin->port->name); } } @@ -1487,7 +1520,7 @@ class NetlistWriterVisitor : public NetlistVisitor { params["WIDTH"] = "0"; //Delay matrix[sink_tnode] -> tuple of source_port_name, pin index, delay - std::map>> tnode_delay_matrix; + std::map>> tnode_delay_matrix; //Process the input ports for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) { @@ -1511,12 +1544,11 @@ class NetlistWriterVisitor : public NetlistVisitor { //Delays // - //We record the souce sink tnodes and thier delays here + //We record the source sink tnodes and their delays here for (tatum::EdgeId edge : timing_ctx.graph->node_out_edges(src_tnode)) { - double delay = delay_calc_->max_edge_delay(*timing_ctx.graph, edge); - + DelayTriple delay_triple = get_edge_delay_triple(edge, *delay_calc_, *timing_ctx.graph); auto sink_tnode = timing_ctx.graph->edge_sink_node(edge); - tnode_delay_matrix[sink_tnode].emplace_back(port->name, ipin, delay); + tnode_delay_matrix[sink_tnode].emplace_back(port->name, ipin, delay_triple); } } @@ -1547,8 +1579,8 @@ class NetlistWriterVisitor : public NetlistVisitor { for (auto& data_tuple : tnode_delay_matrix[inode]) { auto src_name = std::get<0>(data_tuple); auto src_ipin = std::get<1>(data_tuple); - auto delay = std::get<2>(data_tuple); - timing_arcs.emplace_back(src_name, src_ipin, port->name, ipin, delay); + auto delay_triple = std::get<2>(data_tuple); + timing_arcs.emplace_back(src_name, src_ipin, port->name, ipin, delay_triple); } } @@ -1583,7 +1615,7 @@ class NetlistWriterVisitor : public NetlistVisitor { params["WIDTH"] = "0"; //Delay matrix[sink_tnode] -> tuple of source_port_name, pin index, delay - std::map>> tnode_delay_matrix; + std::map>> tnode_delay_matrix; //Process the input ports for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) { @@ -1614,10 +1646,9 @@ class NetlistWriterVisitor : public NetlistVisitor { // //We record the souce sink tnodes and thier delays here for (tatum::EdgeId edge : timing_ctx.graph->node_out_edges(src_tnode)) { - double delay = delay_calc_->max_edge_delay(*timing_ctx.graph, edge); - + DelayTriple delay_triple = get_edge_delay_triple(edge, *delay_calc_, *timing_ctx.graph); auto sink_tnode = timing_ctx.graph->edge_sink_node(edge); - tnode_delay_matrix[sink_tnode].emplace_back(port->name, ipin, delay); + tnode_delay_matrix[sink_tnode].emplace_back(port->name, ipin, delay_triple); } } @@ -1687,7 +1718,7 @@ class NetlistWriterVisitor : public NetlistVisitor { std::map ports_tcq; //Delay matrix[sink_tnode] -> tuple of source_port_name, pin index, delay - std::map>> tnode_delay_matrix; + std::map>> tnode_delay_matrix; //Process the input ports for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) { @@ -1713,17 +1744,22 @@ class NetlistWriterVisitor : public NetlistVisitor { // //We record the source's sink tnodes and their delays here for (tatum::EdgeId edge : timing_ctx.graph->node_out_edges(src_tnode)) { - double delay = delay_calc_->max_edge_delay(*timing_ctx.graph, edge); - + DelayTriple delay_triple = get_edge_delay_triple(edge, *delay_calc_, *timing_ctx.graph); auto sink_tnode = timing_ctx.graph->edge_sink_node(edge); - tnode_delay_matrix[sink_tnode].emplace_back(port->name, ipin, delay); + tnode_delay_matrix[sink_tnode].emplace_back(port->name, ipin, delay_triple); } } input_port_conns[port->name].push_back(net); if (pin->type == PB_PIN_SEQUENTIAL) { - if (!std::isnan(pin->tsu)) ports_tsu[port->name] = std::make_pair(pin->tsu, pin->associated_clock_pin->port->name); - if (!std::isnan(pin->thld)) ports_thld[port->name] = std::make_pair(pin->thld, pin->associated_clock_pin->port->name); + if (!std::isnan(pin->tsu)) { + DelayTriple delay_triple(pin->tsu, pin->tsu, pin->tsu); + ports_tsu[port->name] = std::make_pair(delay_triple, pin->associated_clock_pin->port->name); + } + if (!std::isnan(pin->thld)) { + DelayTriple delay_triple(pin->thld, pin->thld, pin->thld); + ports_thld[port->name] = std::make_pair(delay_triple, pin->associated_clock_pin->port->name); + } } } } @@ -1757,7 +1793,10 @@ class NetlistWriterVisitor : public NetlistVisitor { } output_port_conns[port->name].push_back(net); - if (pin->type == PB_PIN_SEQUENTIAL && !std::isnan(pin->tco_max)) ports_tcq[port->name] = std::make_pair(pin->tco_max, pin->associated_clock_pin->port->name); + if (pin->type == PB_PIN_SEQUENTIAL && !std::isnan(pin->tco_max)) { + DelayTriple delay_triple = get_pin_tco_delay_triple(*pin); + ports_tcq[port->name] = std::make_pair(delay_triple, pin->associated_clock_pin->port->name); + } } } @@ -1787,12 +1826,12 @@ class NetlistWriterVisitor : public NetlistVisitor { } auto& atom_ctx = g_vpr_ctx.atom(); - AtomBlockId blk_id = atom_ctx.lookup.pb_atom(atom); - for (auto param : atom_ctx.nlist.block_params(blk_id)) { + AtomBlockId blk_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); + for (auto param : atom_ctx.netlist().block_params(blk_id)) { params[param.first] = param.second; } - for (auto attr : atom_ctx.nlist.block_attrs(blk_id)) { + for (auto attr : atom_ctx.netlist().block_attrs(blk_id)) { attrs[attr.first] = attr.second; } @@ -1809,8 +1848,8 @@ class NetlistWriterVisitor : public NetlistVisitor { tatum::NodeId find_tnode(const t_pb* atom, int cluster_pin_idx) { auto& atom_ctx = g_vpr_ctx.atom(); - AtomBlockId blk_id = atom_ctx.lookup.pb_atom(atom); - ClusterBlockId clb_index = atom_ctx.lookup.atom_clb(blk_id); + AtomBlockId blk_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); + ClusterBlockId clb_index = atom_ctx.lookup().atom_clb(blk_id); auto key = std::make_pair(clb_index, cluster_pin_idx); auto iter = pin_id_to_tnode_lookup_.find(key); @@ -1840,7 +1879,7 @@ class NetlistWriterVisitor : public NetlistVisitor { const t_pb* atom) { //LUT primitive auto& atom_ctx = g_vpr_ctx.atom(); - const t_model* model = atom_ctx.nlist.block_model(atom_ctx.lookup.pb_atom(atom)); + const t_model* model = atom_ctx.netlist().block_model(atom_ctx.lookup().atom_pb_bimap().pb_atom(atom)); VTR_ASSERT(model->name == std::string(MODEL_NAMES)); #ifdef DEBUG_LUT_MASK @@ -1851,7 +1890,7 @@ class NetlistWriterVisitor : public NetlistVisitor { std::vector permute = determine_lut_permutation(num_inputs, atom); //Retrieve the truth table - const auto& truth_table = atom_ctx.nlist.block_truth_table(atom_ctx.lookup.pb_atom(atom)); + const auto& truth_table = atom_ctx.netlist().block_truth_table(atom_ctx.lookup().atom_pb_bimap().pb_atom(atom)); //Apply the permutation auto permuted_truth_table = permute_truth_table(truth_table, num_inputs, permute); @@ -1896,7 +1935,7 @@ class NetlistWriterVisitor : public NetlistVisitor { // //We walk through the logical inputs to this atom (i.e. in the original truth table/netlist) //and find the corresponding input in the implementation atom (i.e. in the current netlist) - auto ports = atom_ctx.nlist.block_input_ports(atom_ctx.lookup.pb_atom(atom_pb)); + auto ports = atom_ctx.netlist().block_input_ports(atom_ctx.lookup().atom_pb_bimap().pb_atom(atom_pb)); if (ports.size() == 1) { const t_pb_graph_node* gnode = atom_pb->pb_graph_node; VTR_ASSERT(gnode->num_input_ports == 1); @@ -1913,16 +1952,16 @@ class NetlistWriterVisitor : public NetlistVisitor { if (impl_input_net_id) { //If there is a valid net connected in the implementation - AtomNetId logical_net_id = atom_ctx.nlist.port_net(port_id, orig_index); + AtomNetId logical_net_id = atom_ctx.netlist().port_net(port_id, orig_index); // Fatal error should be flagged when the net marked in implementation // does not match the net marked in input netlist if (impl_input_net_id != logical_net_id) { VPR_FATAL_ERROR(VPR_ERROR_IMPL_NETLIST_WRITER, "Unmatch:\n\tlogical net is '%s' at pin '%lu'\n\timplmented net is '%s' at pin '%s'\n", - atom_ctx.nlist.net_name(logical_net_id).c_str(), + atom_ctx.netlist().net_name(logical_net_id).c_str(), size_t(orig_index), - atom_ctx.nlist.net_name(impl_input_net_id).c_str(), + atom_ctx.netlist().net_name(impl_input_net_id).c_str(), gpin->to_string().c_str()); } @@ -2080,16 +2119,14 @@ class NetlistWriterVisitor : public NetlistVisitor { return name; } - ///@brief Returns the delay in pico-seconds from source_tnode to sink_tnode - double get_delay_ps(tatum::NodeId source_tnode, tatum::NodeId sink_tnode) { + ///@brief Returns the delay triple from source_tnode to sink_tnode + DelayTriple get_src_to_sink_delay_triple(tatum::NodeId source_tnode, tatum::NodeId sink_tnode) { auto& timing_ctx = g_vpr_ctx.timing(); tatum::EdgeId edge = timing_ctx.graph->find_edge(source_tnode, sink_tnode); VTR_ASSERT(edge); - double delay_sec = delay_calc_->max_edge_delay(*timing_ctx.graph, edge); - - return ::get_delay_ps(delay_sec); //Class overload hides file-scope by default + return get_edge_delay_triple(edge, *delay_calc_, *timing_ctx.graph); } private: //Data @@ -2144,11 +2181,11 @@ class MergedNetlistWriterVisitor : public NetlistWriterVisitor { void visit_atom_impl(const t_pb* atom) override { auto& atom_ctx = g_vpr_ctx.atom(); - auto atom_pb = atom_ctx.lookup.pb_atom(atom); + auto atom_pb = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); if (atom_pb == AtomBlockId::INVALID()) { return; } - const t_model* model = atom_ctx.nlist.block_model(atom_pb); + const t_model* model = atom_ctx.netlist().block_model(atom_pb); if (model->name == std::string(MODEL_INPUT)) { auto merged_io_name = make_io(atom, PortType::INPUT); @@ -2307,50 +2344,33 @@ class MergedNetlistWriterVisitor : public NetlistWriterVisitor { }; // -// Externally Accessible Functions +// File-scope function implementations // -///@brief Main routine for this file. See netlist_writer.h for details. -void netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts) { - std::string verilog_filename = basename + "_post_synthesis.v"; - std::string blif_filename = basename + "_post_synthesis.blif"; - std::string sdf_filename = basename + "_post_synthesis.sdf"; - - VTR_LOG("Writing Implementation Netlist: %s\n", verilog_filename.c_str()); - VTR_LOG("Writing Implementation Netlist: %s\n", blif_filename.c_str()); - VTR_LOG("Writing Implementation SDF : %s\n", sdf_filename.c_str()); - - std::ofstream verilog_os(verilog_filename); - std::ofstream blif_os(blif_filename); - std::ofstream sdf_os(sdf_filename); - - NetlistWriterVisitor visitor(verilog_os, blif_os, sdf_os, delay_calc, opts); - - NetlistWalker nl_walker(visitor); - - nl_walker.walk(); +DelayTriple get_pin_tco_delay_triple(const t_pb_graph_pin& pin) { + DelayTriple delay_triple; + delay_triple.minimum = pin.tco_min; + delay_triple.maximum = pin.tco_max; + // Since Tatum does not provide typical delays, set it to be the average + // of min and max. + delay_triple.typical = (pin.tco_min + pin.tco_max) / 2.0; + return delay_triple; } -///@brief Main routine for this file. See netlist_writer.h for details. -void merged_netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts) { - std::string verilog_filename = basename + "_merged_post_implementation.v"; - - VTR_LOG("Writing Implementation Netlist: %s\n", verilog_filename.c_str()); - - std::ofstream verilog_os(verilog_filename); - // Don't write blif and sdf, pass dummy streams - std::ofstream blif_os; - std::ofstream sdf_os; - - MergedNetlistWriterVisitor visitor(verilog_os, blif_os, sdf_os, delay_calc, opts); - - NetlistWalker nl_walker(visitor); - - nl_walker.walk(); +DelayTriple get_edge_delay_triple(tatum::EdgeId edge_id, + const AnalysisDelayCalculator& delay_calc, + const tatum::TimingGraph& timing_graph) { + double min_edge_delay = delay_calc.min_edge_delay(timing_graph, edge_id); + double max_edge_delay = delay_calc.max_edge_delay(timing_graph, edge_id); + + DelayTriple delay_triple; + delay_triple.minimum = min_edge_delay; + delay_triple.maximum = max_edge_delay; + // Since Tatum does not provide typical delays, set it to be the average + // of min and max. + delay_triple.typical = (min_edge_delay + max_edge_delay) / 2.0; + return delay_triple; } -// -// File-scope function implementations -// ///@brief Returns a blank string for indenting the given depth std::string indent(size_t depth) { @@ -2362,11 +2382,6 @@ std::string indent(size_t depth) { return new_indent; } -///@brief Returns the delay in pico-seconds from a floating point delay -double get_delay_ps(double delay_sec) { - return delay_sec * 1e12; //Scale to picoseconds -} - ///@brief Returns the name of a unique unconnected net std::string create_unconn_net(size_t& unconn_count) { //We increment unconn_count by reference so each @@ -2572,3 +2587,48 @@ std::string escape_sdf_identifier(const std::string identifier) { std::string join_identifier(std::string lhs, std::string rhs) { return lhs + '_' + rhs; } + +} // namespace + +// +// Externally Accessible Functions +// + +///@brief Main routine for this file. See netlist_writer.h for details. +void netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts) { + std::string verilog_filename = basename + "_post_synthesis.v"; + std::string blif_filename = basename + "_post_synthesis.blif"; + std::string sdf_filename = basename + "_post_synthesis.sdf"; + + VTR_LOG("Writing Implementation Netlist: %s\n", verilog_filename.c_str()); + VTR_LOG("Writing Implementation Netlist: %s\n", blif_filename.c_str()); + VTR_LOG("Writing Implementation SDF : %s\n", sdf_filename.c_str()); + + std::ofstream verilog_os(verilog_filename); + std::ofstream blif_os(blif_filename); + std::ofstream sdf_os(sdf_filename); + + NetlistWriterVisitor visitor(verilog_os, blif_os, sdf_os, delay_calc, opts); + + NetlistWalker nl_walker(visitor); + + nl_walker.walk(); +} + +///@brief Main routine for this file. See netlist_writer.h for details. +void merged_netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts) { + std::string verilog_filename = basename + "_merged_post_implementation.v"; + + VTR_LOG("Writing Merged Implementation Netlist: %s\n", verilog_filename.c_str()); + + std::ofstream verilog_os(verilog_filename); + // Don't write blif and sdf, pass dummy streams + std::ofstream blif_os; + std::ofstream sdf_os; + + MergedNetlistWriterVisitor visitor(verilog_os, blif_os, sdf_os, delay_calc, opts); + + NetlistWalker nl_walker(visitor); + + nl_walker.walk(); +} diff --git a/vpr/src/base/netlist_writer.h b/vpr/src/base/netlist_writer.h index 8a8a19976e1..bb1c0fba202 100644 --- a/vpr/src/base/netlist_writer.h +++ b/vpr/src/base/netlist_writer.h @@ -1,29 +1,29 @@ -#ifndef NETLIST_WRITER_H -#define NETLIST_WRITER_H +#pragma once + #include #include -#include - -#include "vtr_logic.h" - #include "AnalysisDelayCalculator.h" /** * @brief Writes out the post-synthesis implementation netlists in BLIF and Verilog formats, * along with an SDF for delay annotations. * + * Here, post-synthesis implementation netlist is the netlist as it appears after + * routing (i.e. implementation is complete). + * * All written filenames end in {basename}_post_synthesis.{fmt} where {basename} is the * basename argument and {fmt} is the file format (e.g. v, blif, sdf) */ -void netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts); +void netlist_writer(const std::string basename, std::shared_ptr delay_calc, t_analysis_opts opts); /** * @brief Writes out the post implementation netlist in Verilog format. * It has its top module ports merged into multi-bit ones. * + * Here, post-synthesis implementation netlist is the netlist as it appears after + * routing (i.e. implementation is complete). + * * Written filename ends in {basename}_merged_post_implementation.v where {basename} is the * basename argument. */ -void merged_netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts); - -#endif +void merged_netlist_writer(const std::string basename, std::shared_ptr delay_calc, t_analysis_opts opts); diff --git a/vpr/src/base/partition_region.cpp b/vpr/src/base/partition_region.cpp index 5014976eec4..068f181b7c2 100644 --- a/vpr/src/base/partition_region.cpp +++ b/vpr/src/base/partition_region.cpp @@ -106,9 +106,9 @@ const PartitionRegion& get_device_partition_region() { VTR_ASSERT_SAFE(device_pr.get_regions().size() == 1); const auto [xmin, ymin, xmax, ymax] = device_pr.get_regions()[0].get_rect().coordinates(); - VTR_ASSERT_SAFE(xmin == 0 && ymin == 0 && xmax == width -1 && ymax == height - 1); + VTR_ASSERT_SAFE(xmin == 0 && ymin == 0 && xmax == width - 1 && ymax == height - 1); const auto [layer_low, layer_high] = device_pr.get_regions()[0].get_layer_range(); VTR_ASSERT_SAFE(layer_low == 0 && layer_high == n_layers - 1); return device_pr; -} \ No newline at end of file +} diff --git a/vpr/src/base/partition_region.h b/vpr/src/base/partition_region.h index 9e46a1a849b..2e9949fceea 100644 --- a/vpr/src/base/partition_region.h +++ b/vpr/src/base/partition_region.h @@ -108,5 +108,4 @@ struct hash { }; } // namespace std - #endif /* PARTITION_REGIONS_H */ diff --git a/vpr/src/base/place_and_route.cpp b/vpr/src/base/place_and_route.cpp index 12c4187709e..9fcf2a78ff5 100644 --- a/vpr/src/base/place_and_route.cpp +++ b/vpr/src/base/place_and_route.cpp @@ -1,14 +1,11 @@ -#include #include -#include -#include #include #include #include -#include "vtr_util.h" -#include "vtr_memory.h" +#include "flat_placement_types.h" +#include "place_macro.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -16,7 +13,6 @@ #include "vpr_utils.h" #include "vpr_error.h" #include "globals.h" -#include "atom_netlist.h" #include "place_and_route.h" #include "place.h" #include "read_place.h" @@ -24,25 +20,15 @@ #include "route.h" #include "route_export.h" #include "draw.h" -#include "stats.h" -#include "check_route.h" #include "rr_graph.h" -#include "net_delay.h" -#include "timing_place.h" #include "read_xml_arch_file.h" -#include "echo_files.h" #include "route_common.h" -#include "place_macro.h" -#include "power.h" -#include "place_util.h" #include "RoutingDelayCalculator.h" -#include "timing_info.h" -#include "tatum/echo_writer.hpp" /******************* Subroutines local to this module ************************/ -static int compute_chan_width(int cfactor, t_chan chan_dist, float distance, float separation, t_graph_type graph_directionality); +static int compute_chan_width(int cfactor, t_chan chan_dist, float distance, float separation, e_graph_type graph_directionality); static float comp_width(t_chan* chan, float x, float separation); /************************* Subroutine Definitions ****************************/ @@ -82,8 +68,8 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, int udsd_multiplier; int warnings; - t_graph_type graph_type; - t_graph_type graph_directionality; + e_graph_type graph_type; + e_graph_type graph_directionality; /* We have chosen to pass placer_opts_ref by reference because of its large size. * * However, since the value is mutated later in the function, we declare a * @@ -94,15 +80,15 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, /* Allocate the major routing structures. */ if (router_opts.route_type == GLOBAL) { - graph_type = GRAPH_GLOBAL; - graph_directionality = GRAPH_BIDIR; + graph_type = e_graph_type::GLOBAL; + graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); /* Branch on tileable routing */ if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { - graph_type = GRAPH_UNIDIR_TILEABLE; + graph_type = e_graph_type::UNIDIR_TILEABLE; } - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } VTR_ASSERT(!net_delay.empty()); @@ -193,6 +179,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, det_routing_arch, segment_inf, arch->directs, + FlatPlacementInfo(), // Pass empty flat placement info. /*is_flat=*/false); } success = route(router_net_list, @@ -331,6 +318,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, try_place(placement_net_list, placer_opts, router_opts, analysis_opts, noc_opts, arch->Chans, det_routing_arch, segment_inf, arch->directs, + FlatPlacementInfo(), // Pass empty flat placement info. /*is_flat=*/false); } @@ -419,6 +407,36 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, return (final); } +t_chan_width setup_chan_width(const t_router_opts& router_opts, + t_chan_width_dist chan_width_dist) { + /*we give plenty of tracks, this increases routability for the */ + /*lookup table generation */ + + e_graph_type graph_directionality; + int width_fac; + + if (router_opts.fixed_channel_width == NO_FIXED_CHANNEL_WIDTH) { + auto& device_ctx = g_vpr_ctx.device(); + + auto type = find_most_common_tile_type(device_ctx.grid); + + width_fac = 4 * type->num_pins; + /*this is 2x the value that binary search starts */ + /*this should be enough to allow most pins to */ + /*connect to tracks in the architecture */ + } else { + width_fac = router_opts.fixed_channel_width; + } + + if (router_opts.route_type == GLOBAL) { + graph_directionality = e_graph_type::BIDIR; + } else { + graph_directionality = e_graph_type::UNIDIR; + } + + return init_chan(width_fac, chan_width_dist, graph_directionality); +} + /** * @brief Assigns widths to channels (in tracks). * @@ -427,7 +445,9 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, * is used to determine if the channel width should be rounded to an * even number. */ -t_chan_width init_chan(int cfactor, const t_chan_width_dist& chan_width_dist, t_graph_type graph_directionality) { +t_chan_width init_chan(int cfactor, + const t_chan_width_dist& chan_width_dist, + e_graph_type graph_directionality) { auto& device_ctx = g_vpr_ctx.mutable_device(); auto& grid = device_ctx.grid; @@ -499,10 +519,10 @@ t_chan_width init_chan(int cfactor, const t_chan_width_dist& chan_width_dist, t_ * @param separation The distance between two channels in the 0 to 1 coordinate system. * @param graph_directionality The directionality of the graph (unidirectional or bidirectional). */ -static int compute_chan_width(int cfactor, t_chan chan_dist, float distance, float separation, t_graph_type graph_directionality) { +static int compute_chan_width(int cfactor, t_chan chan_dist, float distance, float separation, e_graph_type graph_directionality) { int computed_width; computed_width = (int)floor(cfactor * comp_width(&chan_dist, distance, separation) + 0.5); - if ((GRAPH_BIDIR == graph_directionality) || computed_width % 2 == 0) { + if ((e_graph_type::BIDIR == graph_directionality) || computed_width % 2 == 0) { return computed_width; } else { return computed_width - 1; diff --git a/vpr/src/base/place_and_route.h b/vpr/src/base/place_and_route.h index 6f191c0ff9e..e595a2cdedb 100644 --- a/vpr/src/base/place_and_route.h +++ b/vpr/src/base/place_and_route.h @@ -2,11 +2,9 @@ #define VPR_PLACE_AND_ROUTE_H #define INFINITE -1 -#define NOT_FOUND 0 #define WNEED 1 #define WL 2 -#define PROC_TIME 3 #include "vpr_types.h" #include "timing_info.h" @@ -18,7 +16,6 @@ struct t_fmap_cell { int fc; ///& placement_net_list, const std::shared_ptr& delay_calc, bool is_flat); +t_chan_width setup_chan_width(const t_router_opts& router_opts, + t_chan_width_dist chan_width_dist); + t_chan_width init_chan(int cfactor, const t_chan_width_dist& chan_width_dist, - t_graph_type graph_directionality); + e_graph_type graph_directionality); void post_place_sync(); diff --git a/vpr/src/base/read_interchange_netlist.cpp b/vpr/src/base/read_interchange_netlist.cpp index c29cea8326d..ee59c3a76d2 100644 --- a/vpr/src/base/read_interchange_netlist.cpp +++ b/vpr/src/base/read_interchange_netlist.cpp @@ -13,33 +13,33 @@ #ifdef VTR_ENABLE_CAPNPROTO -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include - -# include "LogicalNetlist.capnp.h" -# include "capnp/serialize.h" -# include "capnp/serialize-packed.h" - -# include "vtr_assert.h" -# include "vtr_hash.h" -# include "vtr_util.h" -# include "vtr_log.h" -# include "vtr_logic.h" -# include "vtr_time.h" -# include "vtr_digest.h" - -# include "vpr_types.h" -# include "vpr_error.h" -# include "globals.h" -# include "arch_types.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "LogicalNetlist.capnp.h" +#include "capnp/serialize.h" +#include "capnp/serialize-packed.h" + +#include "vtr_assert.h" +#include "vtr_hash.h" +#include "vtr_util.h" +#include "vtr_log.h" +#include "vtr_logic.h" +#include "vtr_time.h" +#include "vtr_digest.h" + +#include "vpr_types.h" +#include "vpr_error.h" +#include "globals.h" +#include "arch_types.h" struct NetlistReader { public: diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp index 2f0d1ff8716..9c648607cae 100644 --- a/vpr/src/base/read_netlist.cpp +++ b/vpr/src/base/read_netlist.cpp @@ -11,6 +11,7 @@ #include #include +#include "physical_types_util.h" #include "pugixml.hpp" #include "pugixml_loc.hpp" #include "pugixml_util.hpp" @@ -19,7 +20,6 @@ #include "vtr_util.h" #include "vtr_log.h" #include "vtr_digest.h" -#include "vtr_memory.h" #include "vtr_token.h" #include "vpr_types.h" @@ -29,7 +29,6 @@ #include "hash.h" #include "globals.h" #include "atom_netlist.h" -#include "read_xml_util.h" #include "read_netlist.h" #include "pb_type_graph.h" @@ -151,11 +150,11 @@ ClusteredNetlist read_netlist(const char* net_file, //Note that we currently don't require that the atom_netlist_id exists, //to remain compatible with old .net files std::string atom_nl_id = atom_netlist_id.value(); - if (atom_nl_id != atom_ctx.nlist.netlist_id()) { + if (atom_nl_id != atom_ctx.netlist().netlist_id()) { auto msg = vtr::string_fmt( "Netlist was generated from a different atom netlist file" " (loaded atom netlist ID: %s, packed netlist atom netlist ID: %s)", - atom_nl_id.c_str(), atom_ctx.nlist.netlist_id().c_str()); + atom_nl_id.c_str(), atom_ctx.netlist().netlist_id().c_str()); if (verify_file_digests) { vpr_throw(VPR_ERROR_NET_F, netlist_file_name, loc_data.line(top), msg.c_str()); } else { @@ -177,8 +176,8 @@ ClusteredNetlist read_netlist(const char* net_file, /* Parse all CLB blocks and all nets*/ //Reset atom/pb mapping (it is reloaded from the packed netlist file) - for (auto blk_id : atom_ctx.nlist.blocks()) - atom_ctx.lookup.set_atom_pb(blk_id, nullptr); + for (auto blk_id : atom_ctx.netlist().blocks()) + atom_ctx.mutable_lookup().mutable_atom_pb_bimap().set_atom_pb(blk_id, nullptr); //Count the number of blocks for allocation bcount = pugiutil::count_children(top, "block", loc_data, pugiutil::ReqOpt::OPTIONAL); @@ -194,14 +193,14 @@ ClusteredNetlist read_netlist(const char* net_file, VTR_ASSERT(bcount == i); VTR_ASSERT(clb_nlist.blocks().size() == i); VTR_ASSERT(num_primitives >= 0); - VTR_ASSERT(static_cast(num_primitives) == atom_ctx.nlist.blocks().size()); + VTR_ASSERT(static_cast(num_primitives) == atom_ctx.netlist().blocks().size()); /* Error check */ - for (auto blk_id : atom_ctx.nlist.blocks()) { - if (atom_ctx.lookup.atom_pb(blk_id) == nullptr) { + for (auto blk_id : atom_ctx.netlist().blocks()) { + if (atom_ctx.lookup().atom_pb_bimap().atom_pb(blk_id) == nullptr) { VPR_FATAL_ERROR(VPR_ERROR_NET_F, ".blif file and .net file do not match, .net file missing atom %s.\n", - atom_ctx.nlist.block_name(blk_id).c_str()); + atom_ctx.netlist().block_name(blk_id).c_str()); } } /* TODO: Add additional check to make sure net connections match */ @@ -217,30 +216,30 @@ ClusteredNetlist read_netlist(const char* net_file, * check_top_IO_matches_IO_blocks(circuit_inputs, circuit_outputs, circuit_clocks, blist, bcount); */ /* load mapping between external nets and all nets */ - for (auto net_id : atom_ctx.nlist.nets()) { - atom_ctx.lookup.remove_atom_net(net_id); + for (auto net_id : atom_ctx.netlist().nets()) { + atom_ctx.mutable_lookup().remove_atom_net(net_id); } //Save the mapping between clb and atom nets for (auto clb_net_id : clb_nlist.nets()) { - AtomNetId net_id = atom_ctx.nlist.find_net(clb_nlist.net_name(clb_net_id)); + AtomNetId net_id = atom_ctx.netlist().find_net(clb_nlist.net_name(clb_net_id)); VTR_ASSERT(net_id); - atom_ctx.lookup.add_atom_clb_net(net_id, clb_net_id); + atom_ctx.mutable_lookup().add_atom_clb_net(net_id, clb_net_id); } // Mark ignored and global atom nets /* We have to make set the following variables after the mapping between cluster nets and atom nets * is created */ - const AtomNetlist atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist atom_nlist = g_vpr_ctx.atom().netlist(); for (auto clb_net : clb_nlist.nets()) { - AtomNetId atom_net = atom_ctx.lookup.atom_net(clb_net); + AtomNetId atom_net = atom_ctx.lookup().atom_net(clb_net); VTR_ASSERT(atom_net != AtomNetId::INVALID()); if (clb_nlist.net_is_global(clb_net)) { - atom_ctx.nlist.set_net_is_global(atom_net, true); + atom_ctx.mutable_netlist().set_net_is_global(atom_net, true); } if (clb_nlist.net_is_ignored(clb_net)) { - atom_ctx.nlist.set_net_is_ignored(atom_net, true); + atom_ctx.mutable_netlist().set_net_is_ignored(atom_net, true); } } @@ -320,7 +319,7 @@ static void processComplexBlock(pugi::xml_node clb_block, } //Parse all pbs and CB internal nets - atom_ctx.lookup.set_atom_pb(AtomBlockId::INVALID(), clb_nlist->block_pb(index)); + atom_ctx.mutable_lookup().mutable_atom_pb_bimap().set_atom_pb(AtomBlockId::INVALID(), clb_nlist->block_pb(index)); clb_nlist->block_pb(index)->pb_graph_node = clb_nlist->block_type(index)->pb_graph_head; clb_nlist->block_pb(index)->pb_route = alloc_pb_route(clb_nlist->block_pb(index)->pb_graph_node); @@ -466,7 +465,7 @@ static void processPb(pugi::xml_node Parent, const ClusterBlockId index, t_pb* p if (pb_type->num_modes == 0) { /* A primitive type */ - AtomBlockId blk_id = atom_ctx.nlist.find_block(pb->name); + AtomBlockId blk_id = atom_ctx.netlist().find_block(pb->name); if (!blk_id) { VPR_FATAL_ERROR(VPR_ERROR_NET_F, ".net file and .blif file do not match, encountered unknown primitive %s in .net file.\n", @@ -475,11 +474,11 @@ static void processPb(pugi::xml_node Parent, const ClusterBlockId index, t_pb* p //Update atom netlist mapping VTR_ASSERT(blk_id); - atom_ctx.lookup.set_atom_pb(blk_id, pb); - atom_ctx.lookup.set_atom_clb(blk_id, index); + atom_ctx.mutable_lookup().mutable_atom_pb_bimap().set_atom_pb(blk_id, pb); + atom_ctx.mutable_lookup().set_atom_clb(blk_id, index); - auto atom_attrs = atom_ctx.nlist.block_attrs(blk_id); - auto atom_params = atom_ctx.nlist.block_params(blk_id); + auto atom_attrs = atom_ctx.netlist().block_attrs(blk_id); + auto atom_params = atom_ctx.netlist().block_params(blk_id); processAttrsParams(attrs, "attribute", atom_attrs, loc_data); processAttrsParams(params, "parameter", atom_params, loc_data); @@ -543,7 +542,7 @@ static void processPb(pugi::xml_node Parent, const ClusterBlockId index, t_pb* p pb->child_pbs[i][pb_index].name = vtr::strdup(name.value()); /* Parse all pbs and CB internal nets*/ - atom_ctx.lookup.set_atom_pb(AtomBlockId::INVALID(), &pb->child_pbs[i][pb_index]); + atom_ctx.mutable_lookup().mutable_atom_pb_bimap().set_atom_pb(AtomBlockId::INVALID(), &pb->child_pbs[i][pb_index]); auto mode = child.attribute("mode"); pb->child_pbs[i][pb_index].mode = 0; @@ -565,7 +564,7 @@ static void processPb(pugi::xml_node Parent, const ClusterBlockId index, t_pb* p } else { /* physical block has no used primitives but it may have used routing */ pb->child_pbs[i][pb_index].name = nullptr; - atom_ctx.lookup.set_atom_pb(AtomBlockId::INVALID(), &pb->child_pbs[i][pb_index]); + atom_ctx.mutable_lookup().mutable_atom_pb_bimap().set_atom_pb(AtomBlockId::INVALID(), &pb->child_pbs[i][pb_index]); auto lookahead1 = pugiutil::get_first_child(child, "outputs", loc_data, pugiutil::OPTIONAL); if (lookahead1) { @@ -705,7 +704,7 @@ static void processPorts(pugi::xml_node Parent, t_pb* pb, t_pb_routes& pb_route, if (strcmp(pins[i].c_str(), "open") != 0) { //For connected pins look-up the inter-block net index associated with it - AtomNetId net_id = atom_ctx.nlist.find_net(pins[i].c_str()); + AtomNetId net_id = atom_ctx.netlist().find_net(pins[i].c_str()); if (!net_id) { VPR_FATAL_ERROR(VPR_ERROR_NET_F, ".blif and .net do not match, unknown net %s found in .net file.\n.", @@ -785,7 +784,7 @@ static void processPorts(pugi::xml_node Parent, t_pb* pb, t_pb_routes& pb_route, const t_pb_graph_pin* pb_gpin = &pb->pb_graph_node->output_pins[out_port][i]; int rr_node_index = pb_gpin->pin_count_in_cluster; if (strcmp(pins[i].c_str(), "open") != 0) { - AtomNetId net_id = atom_ctx.nlist.find_net(pins[i].c_str()); + AtomNetId net_id = atom_ctx.netlist().find_net(pins[i].c_str()); if (!net_id) { VPR_FATAL_ERROR(VPR_ERROR_NET_F, ".blif and .net do not match, unknown net %s found in .net file.\n", @@ -939,8 +938,8 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) { if (pb->pb_route.count(pb_graph_pin->pin_count_in_cluster)) { AtomNetId atom_net_id = pb->pb_route[pb_graph_pin->pin_count_in_cluster].atom_net_id; if (atom_net_id) { - add_net_to_hash(ext_nhash, atom_ctx.nlist.net_name(atom_net_id).c_str(), &ext_ncount); - clb_net_id = clb_nlist.create_net(atom_ctx.nlist.net_name(atom_net_id)); + add_net_to_hash(ext_nhash, atom_ctx.netlist().net_name(atom_net_id).c_str(), &ext_ncount); + clb_net_id = clb_nlist.create_net(atom_ctx.netlist().net_name(atom_net_id)); clb_nlist.create_pin(input_port_id, (BitIndex)k, clb_net_id, PinType::SINK, ipin); } } @@ -958,11 +957,11 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) { if (pb->pb_route.count(pb_graph_pin->pin_count_in_cluster)) { AtomNetId atom_net_id = pb->pb_route[pb_graph_pin->pin_count_in_cluster].atom_net_id; if (atom_net_id) { - add_net_to_hash(ext_nhash, atom_ctx.nlist.net_name(atom_net_id).c_str(), &ext_ncount); - clb_net_id = clb_nlist.create_net(atom_ctx.nlist.net_name(atom_net_id)); + add_net_to_hash(ext_nhash, atom_ctx.netlist().net_name(atom_net_id).c_str(), &ext_ncount); + clb_net_id = clb_nlist.create_net(atom_ctx.netlist().net_name(atom_net_id)); - AtomPinId atom_net_driver = atom_ctx.nlist.net_driver(atom_net_id); - bool driver_is_constant = atom_ctx.nlist.pin_is_constant(atom_net_driver); + AtomPinId atom_net_driver = atom_ctx.netlist().net_driver(atom_net_id); + bool driver_is_constant = atom_ctx.netlist().pin_is_constant(atom_net_driver); clb_nlist.create_pin(output_port_id, (BitIndex)k, clb_net_id, PinType::DRIVER, ipin, driver_is_constant); @@ -983,8 +982,8 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) { if (pb->pb_route.count(pb_graph_pin->pin_count_in_cluster)) { AtomNetId atom_net_id = pb->pb_route[pb_graph_pin->pin_count_in_cluster].atom_net_id; if (atom_net_id) { - add_net_to_hash(ext_nhash, atom_ctx.nlist.net_name(atom_net_id).c_str(), &ext_ncount); - clb_net_id = clb_nlist.create_net(atom_ctx.nlist.net_name(atom_net_id)); + add_net_to_hash(ext_nhash, atom_ctx.netlist().net_name(atom_net_id).c_str(), &ext_ncount); + clb_net_id = clb_nlist.create_net(atom_ctx.netlist().net_name(atom_net_id)); clb_nlist.create_pin(clock_port_id, (BitIndex)k, clb_net_id, PinType::SINK, ipin); } } @@ -1122,8 +1121,8 @@ static size_t mark_constant_generators_rec(const t_pb* pb, const t_pb_routes& pb if (!pb_route.count(cluster_pin_idx)) continue; if (pb_route[cluster_pin_idx].atom_net_id) { AtomNetId net_id = pb_route[pb->pb_graph_node->output_pins[i][j].pin_count_in_cluster].atom_net_id; - AtomPinId driver_pin_id = atom_ctx.nlist.net_driver(net_id); - VTR_ASSERT(atom_ctx.nlist.pin_is_constant(driver_pin_id)); + AtomPinId driver_pin_id = atom_ctx.netlist().net_driver(net_id); + VTR_ASSERT(atom_ctx.netlist().pin_is_constant(driver_pin_id)); } } } @@ -1180,18 +1179,18 @@ static void load_atom_index_for_pb_pin(t_pb_routes& pb_route, int ipin) { static void load_atom_pin_mapping(const ClusteredNetlist& clb_nlist) { auto& atom_ctx = g_vpr_ctx.atom(); - for (const AtomBlockId blk : atom_ctx.nlist.blocks()) { - const t_pb* pb = atom_ctx.lookup.atom_pb(blk); + for (const AtomBlockId blk : atom_ctx.netlist().blocks()) { + const t_pb* pb = atom_ctx.lookup().atom_pb_bimap().atom_pb(blk); VTR_ASSERT_MSG(pb, "Atom block must have a matching PB"); const t_pb_graph_node* gnode = pb->pb_graph_node; - VTR_ASSERT_MSG(gnode->pb_type->model == atom_ctx.nlist.block_model(blk), + VTR_ASSERT_MSG(gnode->pb_type->model == atom_ctx.netlist().block_model(blk), "Atom block PB must match BLIF model"); for (int iport = 0; iport < gnode->num_input_ports; ++iport) { if (gnode->num_input_pins[iport] <= 0) continue; - const AtomPortId port = atom_ctx.nlist.find_atom_port(blk, gnode->input_pins[iport][0].port->model_port); + const AtomPortId port = atom_ctx.netlist().find_atom_port(blk, gnode->input_pins[iport][0].port->model_port); if (!port) continue; for (int ipin = 0; ipin < gnode->num_input_pins[iport]; ++ipin) { @@ -1205,7 +1204,7 @@ static void load_atom_pin_mapping(const ClusteredNetlist& clb_nlist) { for (int iport = 0; iport < gnode->num_output_ports; ++iport) { if (gnode->num_output_pins[iport] <= 0) continue; - const AtomPortId port = atom_ctx.nlist.find_atom_port(blk, gnode->output_pins[iport][0].port->model_port); + const AtomPortId port = atom_ctx.netlist().find_atom_port(blk, gnode->output_pins[iport][0].port->model_port); if (!port) continue; for (int ipin = 0; ipin < gnode->num_output_pins[iport]; ++ipin) { @@ -1219,7 +1218,7 @@ static void load_atom_pin_mapping(const ClusteredNetlist& clb_nlist) { for (int iport = 0; iport < gnode->num_clock_ports; ++iport) { if (gnode->num_clock_pins[iport] <= 0) continue; - const AtomPortId port = atom_ctx.nlist.find_atom_port(blk, gnode->clock_pins[iport][0].port->model_port); + const AtomPortId port = atom_ctx.netlist().find_atom_port(blk, gnode->clock_pins[iport][0].port->model_port); if (!port) continue; for (int ipin = 0; ipin < gnode->num_clock_pins[iport]; ++ipin) { @@ -1235,9 +1234,9 @@ static void load_atom_pin_mapping(const ClusteredNetlist& clb_nlist) { void set_atom_pin_mapping(const ClusteredNetlist& clb_nlist, const AtomBlockId atom_blk, const AtomPortId atom_port, const t_pb_graph_pin* gpin) { auto& atom_ctx = g_vpr_ctx.mutable_atom(); - VTR_ASSERT(atom_ctx.nlist.port_block(atom_port) == atom_blk); + VTR_ASSERT(atom_ctx.netlist().port_block(atom_port) == atom_blk); - ClusterBlockId clb_index = atom_ctx.lookup.atom_clb(atom_blk); + ClusterBlockId clb_index = atom_ctx.lookup().atom_clb(atom_blk); VTR_ASSERT(clb_index != ClusterBlockId::INVALID()); const t_pb* clb_pb = clb_nlist.block_pb(clb_index); @@ -1251,17 +1250,17 @@ void set_atom_pin_mapping(const ClusteredNetlist& clb_nlist, const AtomBlockId a return; } - const t_pb* atom_pb = atom_ctx.lookup.atom_pb(atom_blk); + const t_pb* atom_pb = atom_ctx.lookup().atom_pb_bimap().atom_pb(atom_blk); //This finds the index within the atom port to which the current gpin //is mapped. Note that this accounts for any applied pin rotations //(e.g. on LUT inputs) BitIndex atom_pin_bit_index = atom_pb->atom_pin_bit_index(gpin); - AtomPinId atom_pin = atom_ctx.nlist.port_pin(atom_port, atom_pin_bit_index); + AtomPinId atom_pin = atom_ctx.netlist().port_pin(atom_port, atom_pin_bit_index); - VTR_ASSERT(pb_route->atom_net_id == atom_ctx.nlist.pin_net(atom_pin)); + VTR_ASSERT(pb_route->atom_net_id == atom_ctx.netlist().pin_net(atom_pin)); //Save the mapping - atom_ctx.lookup.set_atom_pin_pb_graph_pin(atom_pin, gpin); + atom_ctx.mutable_lookup().set_atom_pin_pb_graph_pin(atom_pin, gpin); } diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 200b549bfd0..aa6d52eb93e 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -5,9 +5,10 @@ #include "argparse.hpp" +#include "ap_flow_enums.h" #include "vtr_log.h" -#include "vtr_util.h" #include "vtr_path.h" +#include "vtr_util.h" #include using argparse::ConvertedValue; @@ -132,6 +133,151 @@ struct ParseCircuitFormat { return {"auto", "blif", "eblif", "fpga-interchange"}; } }; + +struct ParseAPAnalyticalSolver { + ConvertedValue from_str(const std::string& str) { + ConvertedValue conv_value; + if (str == "qp-hybrid") + conv_value.set_value(e_ap_analytical_solver::QP_Hybrid); + else if (str == "lp-b2b") + conv_value.set_value(e_ap_analytical_solver::LP_B2B); + else { + std::stringstream msg; + msg << "Invalid conversion from '" << str << "' to e_ap_analytical_solver (expected one of: " << argparse::join(default_choices(), ", ") << ")"; + conv_value.set_error(msg.str()); + } + return conv_value; + } + + ConvertedValue to_str(e_ap_analytical_solver val) { + ConvertedValue conv_value; + switch (val) { + case e_ap_analytical_solver::QP_Hybrid: + conv_value.set_value("qp-hybrid"); + break; + case e_ap_analytical_solver::LP_B2B: + conv_value.set_value("lp-b2b"); + break; + default: + VTR_ASSERT(false); + } + return conv_value; + } + + std::vector default_choices() { + return {"qp-hybrid", "lp-b2b"}; + } +}; + +struct ParseAPPartialLegalizer { + ConvertedValue from_str(const std::string& str) { + ConvertedValue conv_value; + if (str == "bipartitioning") + conv_value.set_value(e_ap_partial_legalizer::BiPartitioning); + else if (str == "flow-based") + conv_value.set_value(e_ap_partial_legalizer::FlowBased); + else { + std::stringstream msg; + msg << "Invalid conversion from '" << str << "' to e_ap_partial_legalizer (expected one of: " << argparse::join(default_choices(), ", ") << ")"; + conv_value.set_error(msg.str()); + } + return conv_value; + } + + ConvertedValue to_str(e_ap_partial_legalizer val) { + ConvertedValue conv_value; + switch (val) { + case e_ap_partial_legalizer::BiPartitioning: + conv_value.set_value("bipartitioning"); + break; + case e_ap_partial_legalizer::FlowBased: + conv_value.set_value("flow-based"); + break; + default: + VTR_ASSERT(false); + } + return conv_value; + } + + std::vector default_choices() { + return {"bipartitioning", "flow-based"}; + } +}; + +struct ParseAPFullLegalizer { + ConvertedValue from_str(const std::string& str) { + ConvertedValue conv_value; + if (str == "naive") + conv_value.set_value(e_ap_full_legalizer::Naive); + else if (str == "appack") + conv_value.set_value(e_ap_full_legalizer::APPack); + else if (str == "basic-min-disturbance") + conv_value.set_value(e_ap_full_legalizer::Basic_Min_Disturbance); + else { + std::stringstream msg; + msg << "Invalid conversion from '" << str << "' to e_ap_full_legalizer (expected one of: " << argparse::join(default_choices(), ", ") << ")"; + conv_value.set_error(msg.str()); + } + return conv_value; + } + + ConvertedValue to_str(e_ap_full_legalizer val) { + ConvertedValue conv_value; + switch (val) { + case e_ap_full_legalizer::Naive: + conv_value.set_value("naive"); + break; + case e_ap_full_legalizer::APPack: + conv_value.set_value("appack"); + break; + case e_ap_full_legalizer::Basic_Min_Disturbance: + conv_value.set_value("basic-min-disturbance"); + default: + VTR_ASSERT(false); + } + return conv_value; + } + + std::vector default_choices() { + return {"naive", "appack", "basic-min-disturbance"}; + } +}; + +struct ParseAPDetailedPlacer { + ConvertedValue from_str(const std::string& str) { + ConvertedValue conv_value; + if (str == "none") + conv_value.set_value(e_ap_detailed_placer::Identity); + else if (str == "annealer") + conv_value.set_value(e_ap_detailed_placer::Annealer); + else { + std::stringstream msg; + msg << "Invalid conversion from '" << str << "' to e_ap_detailed_placer (expected one of: " << argparse::join(default_choices(), ", ") << ")"; + conv_value.set_error(msg.str()); + } + return conv_value; + } + + ConvertedValue to_str(e_ap_detailed_placer val) { + ConvertedValue conv_value; + switch (val) { + case e_ap_detailed_placer::Identity: + conv_value.set_value("none"); + break; + case e_ap_detailed_placer::Annealer: + conv_value.set_value("annealer"); + break; + default: + VTR_ASSERT(false); + } + return conv_value; + } + + std::vector default_choices() { + return {"none", "annealer"}; + } +}; + struct ParseRoutePredictor { ConvertedValue from_str(const std::string& str) { ConvertedValue conv_value; @@ -171,7 +317,9 @@ struct ParseRoutePredictor { struct ParseRouterAlgorithm { ConvertedValue from_str(const std::string& str) { ConvertedValue conv_value; - if (str == "parallel") + if (str == "nested") + conv_value.set_value(NESTED); + else if (str == "parallel") conv_value.set_value(PARALLEL); else if (str == "parallel_decomp") conv_value.set_value(PARALLEL_DECOMP); @@ -187,8 +335,12 @@ struct ParseRouterAlgorithm { ConvertedValue to_str(e_router_algorithm val) { ConvertedValue conv_value; - if (val == PARALLEL) + if (val == NESTED) + conv_value.set_value("nested"); + else if (val == PARALLEL) conv_value.set_value("parallel"); + else if (val == PARALLEL_DECOMP) + conv_value.set_value("parallel_decomp"); else { VTR_ASSERT(val == TIMING_DRIVEN); conv_value.set_value("timing_driven"); @@ -1617,19 +1769,26 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .show_in(argparse::ShowIn::HELP_ONLY); file_grp.add_argument(args.read_rr_graph_file, "--read_rr_graph") - .help( - "The routing resource graph file to load." - " The loaded routing resource graph overrides any routing architecture specified in the architecture file.") + .help("The routing resource graph file to load. " + "The loaded routing resource graph overrides any routing architecture specified in the architecture file.") .metavar("RR_GRAPH_FILE") .show_in(argparse::ShowIn::HELP_ONLY); + file_grp.add_argument(args.read_rr_edge_override_file, "--read_rr_edge_override") + .help("The routing resource edge attributes override file to load. " + "This file overrides edge attributes in the routing resource graph. " + "The user can use the architecture file to specify nominal switch delays, " + "while this file can be used to override the nominal delays to make it more accurate " + "for specific edges.") + .show_in(argparse::ShowIn::HELP_ONLY); + file_grp.add_argument(args.write_rr_graph_file, "--write_rr_graph") - .help("Writes the routing resource graph to the specified file") + .help("Writes the routing resource graph to the specified file.") .metavar("RR_GRAPH_FILE") .show_in(argparse::ShowIn::HELP_ONLY); file_grp.add_argument(args.write_initial_place_file, "--write_initial_place_file") - .help("Writes out the the placement chosen by the initial placement algorithm to the specified file") + .help("Writes out the the placement chosen by the initial placement algorithm to the specified file.") .metavar("INITIAL_PLACE_FILE") .show_in(argparse::ShowIn::HELP_ONLY); @@ -1652,6 +1811,11 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("fix_clusters.out") .show_in(argparse::ShowIn::HELP_ONLY); + file_grp.add_argument(args.read_flat_place_file, "--read_flat_place") + .help( + "Reads VPR's (or reconstructed external) placement solution in flat placement file format; this file lists cluster and intra-cluster placement coordinates for each atom and can be used to reconstruct a clustering and placement solution.") + .show_in(argparse::ShowIn::HELP_ONLY); + file_grp.add_argument(args.write_flat_place_file, "--write_flat_place") .help( "VPR's (or reconstructed external) placement solution in flat placement file format; this file lists cluster and intra-cluster placement coordinates for each atom and can be used to reconstruct a clustering and placement solution.") @@ -1739,6 +1903,56 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("1") .show_in(argparse::ShowIn::HELP_ONLY); + auto& ap_grp = parser.add_argument_group("analytical placement options"); + + ap_grp.add_argument(args.ap_analytical_solver, "--ap_analytical_solver") + .help( + "Controls which Analytical Solver the Global Placer will use in the AP Flow.\n" + " * qp-hybrid: olves for a placement that minimizes the quadratic HPWL of the flat placement using a hybrid clique/star net model.\n" + " * lp-b2b: Solves for a placement that minimizes the linear HPWL of theflat placement using the Bound2Bound net model.") + .default_value("lp-b2b") + .show_in(argparse::ShowIn::HELP_ONLY); + + ap_grp.add_argument(args.ap_partial_legalizer, "--ap_partial_legalizer") + .help( + "Controls which Partial Legalizer the Global Placer will use in the AP Flow.\n" + " * bipartitioning: Creates minimum windows around over-dense regions of the device bi-partitions the atoms in these windows such that the region is no longer over-dense and the atoms are in tiles that they can be placed into.\n" + " * flow-based: Flows atoms from regions that are overfilled to regions that are underfilled.") + .default_value("bipartitioning") + .show_in(argparse::ShowIn::HELP_ONLY); + + ap_grp.add_argument(args.ap_full_legalizer, "--ap_full_legalizer") + .help( + "Controls which Full Legalizer to use in the AP Flow.\n" + " * naive: Use a Naive Full Legalizer which will try to create clusters exactly where their atoms are placed.\n" + " * appack: Use APPack, which takes the Packer in VPR and uses the flat atom placement to create better clusters.\n" + " * basic-min-disturbance: Use the Basic Min. Disturbance Full Legalizer which tries to reconstruct a clustered placement that is as close to the incoming flat placement as possible.") + .default_value("appack") + .show_in(argparse::ShowIn::HELP_ONLY); + + ap_grp.add_argument(args.ap_detailed_placer, "--ap_detailed_placer") + .help( + "Controls which Detailed Placer to use in the AP Flow.\n" + " * none: Do not perform any detailed placement. i.e. the output of the full legalizer will be produced by the AP flow without modification.\n" + " * annealer: Use the Annealer from the Placement stage as a Detailed Placer. This will use the same Placer Options from the Place stage to configure the annealer.") + .default_value("annealer") + .show_in(argparse::ShowIn::HELP_ONLY); + + ap_grp.add_argument(args.ap_timing_tradeoff, "--ap_timing_tradeoff") + .help( + "Controls the trade-off between wirelength (HPWL) and delay minimization in the AP flow.\n" + "A value of 0.0 makes the AP flow focus completely on wirelength minimization, while a value of 1.0 makes the AP flow focus completely on timing optimization.") + .default_value("0.5") + .show_in(argparse::ShowIn::HELP_ONLY); + + ap_grp.add_argument(args.ap_verbosity, "--ap_verbosity") + .help( + "Controls how verbose the AP flow's log messages will be. Higher " + "values produce more output (useful for debugging the AP " + "algorithms).") + .default_value("1") + .show_in(argparse::ShowIn::HELP_ONLY); + auto& pack_grp = parser.add_argument_group("packing options"); pack_grp.add_argument(args.connection_driven_clustering, "--connection_driven_clustering") @@ -2043,7 +2257,6 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value({"100"}) .show_in(argparse::ShowIn::HELP_ONLY); - place_grp.add_argument(args.place_high_fanout_net, "--place_high_fanout_net") .help( "Sets the assumed high fanout net during placement. " @@ -2067,7 +2280,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio place_grp.add_argument(args.RL_agent_placement, "--RL_agent_placement") .help( - "Uses a Reinforcement Learning (RL) agent in choosing the appropiate move type in placement." + "Uses a Reinforcement Learning (RL) agent in choosing the appropriate move type in placement." "It activates the RL agent placement instead of using fixed probability for each move type.") .default_value("on") .show_in(argparse::ShowIn::HELP_ONLY); @@ -2082,7 +2295,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio place_grp.add_argument(args.place_checkpointing, "--place_checkpointing") .help( "Enable Placement checkpoints. This means saving the placement and restore it if it's better than later placements." - "Only effective if agnet's 2nd state is activated.") + "Only effective if agent's 2nd state is activated.") .default_value("on") .show_in(argparse::ShowIn::HELP_ONLY); @@ -2096,7 +2309,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio place_grp.add_argument(args.place_agent_gamma, "--place_agent_gamma") .help( "Controls how quickly the agent's memory decays. " - "Values between [0., 1.] specify the fraction of weight in the exponentially weighted reward average applied to moves which occured greater than moves_per_temp moves ago." + "Values between [0., 1.] specify the fraction of weight in the exponentially weighted reward average applied to moves which occurred greater than moves_per_temp moves ago." "Values < 0 cause the unweighted reward sample average to be used (all samples are weighted equally)") .default_value("0.05") .show_in(argparse::ShowIn::HELP_ONLY); @@ -2159,13 +2372,12 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("0") .show_in(argparse::ShowIn::HELP_ONLY); - /* - * place_grp.add_argument(args.place_timing_cost_func, "--place_timing_cost_func") - * .help( - * "which timing cost function to use") - * .default_value("0") - * .show_in(argparse::ShowIn::HELP_ONLY); - */ + place_grp.add_argument(args.place_quench_only, "--place_quench_only") + .help( + "Skip the placement annealing phase and go straight to the placement quench.") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + place_grp.add_argument(args.place_agent_algorithm, "--place_agent_algorithm") .help("Controls which placement RL agent is used") .default_value("softmax") @@ -2219,13 +2431,13 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .show_in(argparse::ShowIn::HELP_ONLY); place_timing_grp.add_argument(args.inner_loop_recompute_divider, "--inner_loop_recompute_divider") - .help("Controls how many timing analysies are perform per temperature during placement") + .help("Controls how many timing analyses are performed per temperature during placement") .default_value("0") .show_in(argparse::ShowIn::HELP_ONLY); place_timing_grp.add_argument(args.quench_recompute_divider, "--quench_recompute_divider") .help( - "Controls how many timing analysies are perform during the final placement quench (t=0)." + "Controls how many timing analyses are performed during the final placement quench (t=0)." " If unspecified, uses the value from --inner_loop_recompute_divider") .default_value("0") .show_in(argparse::ShowIn::HELP_ONLY); @@ -2295,7 +2507,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .show_in(argparse::ShowIn::HELP_ONLY); place_timing_grp.add_argument(args.post_place_timing_report_file, "--post_place_timing_report") - .help("Name of the post-placement timing report file (not generated if unspecfied)") + .help("Name of the post-placement timing report file (not generated if unspecified)") .default_value("") .show_in(argparse::ShowIn::HELP_ONLY); @@ -2405,9 +2617,10 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio "Specifies the router algorithm to use.\n" " * timing driven: focuses on routability and circuit speed [default]\n" " * parallel: timing_driven with nets in different regions of the chip routed in parallel\n" - " * parallel_decomp: timing_driven with additional parallelism obtained by decomposing high-fanout nets, possibly reducing quality\n") + " * parallel_decomp: timing_driven with additional parallelism obtained by decomposing high-fanout nets, possibly reducing quality\n" + " * nested: parallel with parallelized path search\n") .default_value("timing_driven") - .choices({"parallel", "parallel_decomp", "timing_driven"}) + .choices({"nested", "parallel", "parallel_decomp", "timing_driven"}) .show_in(argparse::ShowIn::HELP_ONLY); route_grp.add_argument(args.min_incremental_reroute_fanout, "--min_incremental_reroute_fanout") @@ -2460,23 +2673,22 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio route_grp.add_argument(args.router_opt_choke_points, "--router_opt_choke_points") .help( "" - "Some FPGA architectures with limited fan-out options within a cluster (e.g. fracturable LUTs with shared pins) do" - " not converge well in routing unless these fan-out choke points are discovered and optimized for during net routing." + "Some FPGA architectures with limited fan-out options within a cluster (e.g. fracturable LUTs with shared pins) do" + " not converge well in routing unless these fan-out choke points are discovered and optimized for during net routing." " This option helps router convergence for such architectures.") .default_value("on") .show_in(argparse::ShowIn::HELP_ONLY); - route_grp.add_argument(args.route_verbosity, "--route_verbosity") .help("Controls the verbosity of routing's output. Higher values produce more output (useful for debugging routing problems)") .default_value("1") .show_in(argparse::ShowIn::HELP_ONLY); route_grp.add_argument(args.custom_3d_sb_fanin_fanout, "--custom_3d_sb_fanin_fanout") - .help( - "Specifies the number of tracks that can drive a 3D switch block connection" - "and the number of tracks that can be driven by a 3D switch block connection") - .default_value("1") - .show_in(argparse::ShowIn::HELP_ONLY); + .help( + "Specifies the number of tracks that can drive a 3D switch block connection" + "and the number of tracks that can be driven by a 3D switch block connection") + .default_value("1") + .show_in(argparse::ShowIn::HELP_ONLY); auto& route_timing_grp = parser.add_argument_group("timing-driven routing options"); @@ -2893,13 +3105,13 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("0.25") .show_in(argparse::ShowIn::HELP_ONLY); - noc_grp.add_argument(args.noc_centroid_weight, "--noc_centroid_weight") + noc_grp.add_argument(args.noc_centroid_weight, "--noc_centroid_weight") .help( "Sets the minimum fraction of swaps attempted by the placer that are NoC blocks." "This value is an integer ranging from 0-100. 0 means NoC blocks will be moved at the same rate as other blocks. 100 means all swaps attempted by the placer are NoC router blocks.") .default_value("0") .show_in(argparse::ShowIn::HELP_ONLY); - + noc_grp.add_argument(args.noc_swap_percentage, "--noc_swap_percentage") .help( "Sets the minimum fraction of swaps attempted by the placer that are NoC blocks. " @@ -2952,7 +3164,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio server_grp.add_argument(args.is_server_mode_enabled, "--server") .help("Run in server mode." - "Accept client application connection and respond to requests." ) + "Accept client application connection and respond to requests.") .action(argparse::Action::STORE_TRUE) .default_value("off"); @@ -3157,7 +3369,7 @@ void set_conditional_defaults(t_options& args) { bool verify_args(const t_options& args) { /* - * Check for conflicting paramaters or dependencies where one parameter set requires another parameter to be included + * Check for conflicting parameters or dependencies where one parameter set requires another parameter to be included */ if (args.read_rr_graph_file.provenance() == Provenance::SPECIFIED && args.RouteChanWidth.provenance() != Provenance::SPECIFIED) { diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 2a9a5a1ce00..42ce1f5c359 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -4,6 +4,7 @@ #include "vpr_types.h" #include "constant_nets.h" +#include "ap_flow_enums.h" #include "argparse_value.hpp" #include "argparse.hpp" @@ -28,11 +29,13 @@ struct t_options { argparse::ArgValue constraints_file; argparse::ArgValue write_rr_graph_file; argparse::ArgValue read_rr_graph_file; + argparse::ArgValue read_rr_edge_override_file; argparse::ArgValue write_initial_place_file; argparse::ArgValue read_initial_place_file; argparse::ArgValue read_vpr_constraints_file; argparse::ArgValue write_vpr_constraints_file; argparse::ArgValue write_constraints_file; + argparse::ArgValue read_flat_place_file; argparse::ArgValue write_flat_place_file; argparse::ArgValue write_placement_delay_lookup; @@ -94,6 +97,14 @@ struct t_options { argparse::ArgValue sweep_constant_primary_outputs; argparse::ArgValue netlist_verbosity; + /* Analytical Placement options */ + argparse::ArgValue ap_analytical_solver; + argparse::ArgValue ap_partial_legalizer; + argparse::ArgValue ap_full_legalizer; + argparse::ArgValue ap_detailed_placer; + argparse::ArgValue ap_verbosity; + argparse::ArgValue ap_timing_tradeoff; + /* Clustering options */ argparse::ArgValue connection_driven_clustering; argparse::ArgValue allow_unrelated_clustering; @@ -148,6 +159,7 @@ struct t_options { argparse::ArgValue place_constraint_subtile; argparse::ArgValue floorplan_num_horizontal_partitions; argparse::ArgValue floorplan_num_vertical_partitions; + argparse::ArgValue place_quench_only; argparse::ArgValue placer_debug_block; argparse::ArgValue placer_debug_net; diff --git a/vpr/src/base/read_place.cpp b/vpr/src/base/read_place.cpp index 5813a780a26..5b07ef33f28 100644 --- a/vpr/src/base/read_place.cpp +++ b/vpr/src/base/read_place.cpp @@ -97,7 +97,7 @@ static void read_place_header(std::ifstream& placement_file, std::streampos file_pos = placement_file.tellg(); while (std::getline(placement_file, line) && (!seen_netlist_id || !seen_grid_dimensions)) { //Parse line-by-line - ++lineno; + ++lineno; std::vector tokens = vtr::split(line); @@ -107,9 +107,7 @@ static void read_place_header(std::ifstream& placement_file, } else if (tokens[0][0] == '#') { continue; //Skip commented lines - } else if (tokens.size() == 4 && - tokens[0] == "Netlist_File:" && - tokens[2] == "Netlist_ID:") { + } else if (tokens.size() == 4 && tokens[0] == "Netlist_File:" && tokens[2] == "Netlist_ID:") { //Check that the netlist used to generate this placement matches the one loaded // //NOTE: this is an optional check which causes no errors if this line is missing. @@ -142,12 +140,12 @@ static void read_place_header(std::ifstream& placement_file, seen_netlist_id = true; - } else if (tokens.size() == 7 && - tokens[0] == "Array" && - tokens[1] == "size:" && - tokens[3] == "x" && - tokens[5] == "logic" && - tokens[6] == "blocks") { + } else if (tokens.size() == 7 + && tokens[0] == "Array" + && tokens[1] == "size:" + && tokens[3] == "x" + && tokens[5] == "logic" + && tokens[6] == "blocks") { //Load the device grid dimensions size_t place_file_width = vtr::atou(tokens[2]); @@ -184,8 +182,8 @@ static void read_place_header(std::ifstream& placement_file, "--verify_file_digests command line option is off."); } - if ((tokens.size() == 4 || (tokens.size() > 4 && tokens[4][0] == '#')) || - (tokens.size() == 5 || (tokens.size() > 5 && tokens[5][0] == '#'))) { + if ((tokens.size() == 4 || (tokens.size() > 4 && tokens[4][0] == '#')) + || (tokens.size() == 5 || (tokens.size() > 5 && tokens[5][0] == '#'))) { placement_file.seekg(file_pos); break; } @@ -236,8 +234,8 @@ static std::string read_place_body(std::ifstream& placement_file, } else if (tokens[0][0] == '#') { continue; //Skip commented lines - } else if ((tokens.size() == 4 || (tokens.size() > 4 && tokens[4][0] == '#')) || - (tokens.size() == 5 || (tokens.size() > 5 && tokens[5][0] == '#'))) { + } else if ((tokens.size() == 4 || (tokens.size() > 4 && tokens[4][0] == '#')) + || (tokens.size() == 5 || (tokens.size() > 5 && tokens[5][0] == '#'))) { //Load the block location // // If the place file corresponds to a 3D architecture, it should contain 5 tokens of actual data, with an optional 6th (commented) token indicating VPR's internal block number. @@ -275,22 +273,22 @@ static std::string read_place_body(std::ifstream& placement_file, //If block name is not found in cluster netlist check if it is in atom netlist if (blk_id == ClusterBlockId::INVALID()) { - AtomBlockId atom_blk_id = atom_ctx.nlist.find_block(block_name); + AtomBlockId atom_blk_id = atom_ctx.netlist().find_block(block_name); if (atom_blk_id == AtomBlockId::INVALID()) { VTR_LOG_WARN("Block %s has an invalid name and it is going to be skipped.\n", c_block_name); continue; } else { - blk_id = atom_ctx.lookup.atom_clb(atom_blk_id); //getting the ClusterBlockId of the cluster that the atom is in + blk_id = atom_ctx.lookup().atom_clb(atom_blk_id); //getting the ClusterBlockId of the cluster that the atom is in } } //Check if block is listed multiple times with conflicting locations in constraints file if (seen_blocks[blk_id] > 0) { - if (block_x != block_locs[blk_id].loc.x || - block_y != block_locs[blk_id].loc.y || - sub_tile_index != block_locs[blk_id].loc.sub_tile || - block_layer != block_locs[blk_id].loc.layer) { + if (block_x != block_locs[blk_id].loc.x + || block_y != block_locs[blk_id].loc.y + || sub_tile_index != block_locs[blk_id].loc.sub_tile + || block_layer != block_locs[blk_id].loc.layer) { std::string cluster_name = cluster_ctx.clb_nlist.block_name(blk_id); VPR_THROW(VPR_ERROR_PLACE, "The location of cluster %s (#%d) is specified %d times in the constraints file with conflicting locations. \n" @@ -310,8 +308,8 @@ static std::string read_place_body(std::ifstream& placement_file, const t_pl_loc& constraint_loc = block_locs[blk_id].loc; if (loc != constraint_loc) { VPR_THROW(VPR_ERROR_PLACE, - "The new location assigned to cluster #%d is (%d,%d,%d,%d), which is inconsistent with the location specified in the constraint file (%d,%d,%d,%d).", - blk_id, loc.x, loc.y, loc.layer, loc.sub_tile, constraint_loc.x, constraint_loc.y, constraint_loc.layer, constraint_loc.sub_tile); + "The new location assigned to cluster #%d is (%d,%d,%d,%d), which is inconsistent with the location specified in the constraint file (%d,%d,%d,%d).", + blk_id, loc.x, loc.y, loc.layer, loc.sub_tile, constraint_loc.x, constraint_loc.y, constraint_loc.layer, constraint_loc.sub_tile); } } blk_loc_registry.set_block_location(blk_id, loc); diff --git a/vpr/src/base/read_place.h b/vpr/src/base/read_place.h index 088f17dd546..9fa6eee6328 100644 --- a/vpr/src/base/read_place.h +++ b/vpr/src/base/read_place.h @@ -5,7 +5,6 @@ #include - class PlacerState; class ClusterBlockId; struct t_block_loc; diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp index b88a7d76949..ead89961aa1 100644 --- a/vpr/src/base/read_route.cpp +++ b/vpr/src/base/read_route.cpp @@ -21,30 +21,23 @@ #include #include -#include "atom_netlist.h" -#include "atom_netlist_utils.h" -#include "rr_graph.h" +#include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_digest.h" #include "vtr_util.h" -#include "tatum/echo_writer.hpp" #include "vtr_log.h" #include "check_route.h" #include "route_common.h" #include "vpr_types.h" #include "globals.h" -#include "vpr_api.h" #include "read_place.h" #include "vpr_types.h" #include "vpr_utils.h" #include "vpr_error.h" -#include "place_and_route.h" -#include "timing_place.h" -#include "route_export.h" -#include "echo_files.h" #include "route_common.h" #include "route_tree.h" #include "read_route.h" +#include "d_ary_heap.h" #include "old_traceback.h" @@ -104,7 +97,7 @@ bool read_route(const char* route_file, const t_router_opts& router_opts, bool v /*Allocate necessary routing structures*/ alloc_and_load_rr_node_route_structs(); - const Netlist<>& router_net_list = (flat_router) ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + const Netlist<>& router_net_list = (flat_router) ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; init_route_structs(router_net_list, router_opts.bb_factor, router_opts.has_choke_point, @@ -212,7 +205,6 @@ static void process_nets(const Netlist<>& net_list, std::ifstream& fp, ClusterNe process_nodes(net_list, fp, inet, filename, lineno); } input_tokens.clear(); - return; } static void process_nodes(const Netlist<>& net_list, std::ifstream& fp, ClusterNetId inet, const char* filename, int& lineno) { diff --git a/vpr/src/base/region.cpp b/vpr/src/base/region.cpp index 7cc6280626b..ff4040e8ff7 100644 --- a/vpr/src/base/region.cpp +++ b/vpr/src/base/region.cpp @@ -44,8 +44,7 @@ void Region::set_sub_tile(int sub_tile) { bool Region::empty() const { const auto [layer_low, layer_high] = layer_range_; - return (rect_.xmax() < rect_.xmin() || rect_.ymax() < rect_.ymin() || - layer_high < layer_low); + return (rect_.xmax() < rect_.xmin() || rect_.ymax() < rect_.ymin() || layer_high < layer_low); } bool Region::is_loc_in_reg(t_pl_loc loc) const { @@ -83,7 +82,7 @@ Region intersection(const Region& r1, const Region& r2) { auto [r2_layer_low, r2_layer_high] = r2.get_layer_range(); auto [intersect_layer_begin, intersect_layer_end] = std::make_pair(std::max(r1_layer_low, r2_layer_low), - std::min(r1_layer_high, r2_layer_high)); + std::min(r1_layer_high, r2_layer_high)); // check that the give layer range start from a lower layer and end at a higher or the same layer // negative layer means that the given Region object is an empty region diff --git a/vpr/src/base/region.h b/vpr/src/base/region.h index 18a179af19a..08959f1bdc6 100644 --- a/vpr/src/base/region.h +++ b/vpr/src/base/region.h @@ -77,9 +77,7 @@ class Region { bool is_loc_in_reg(t_pl_loc loc) const; bool operator==(const Region& reg) const { - return (reg.rect_ == rect_ && - reg.layer_range_ == layer_range_ && - reg.get_sub_tile() == sub_tile_); + return (reg.rect_ == rect_ && reg.layer_range_ == layer_range_ && reg.get_sub_tile() == sub_tile_); } private: @@ -99,7 +97,7 @@ class Region { */ std::pair layer_range_; - int sub_tile_; ///< users will optionally select a subtile + int sub_tile_; ///< users will optionally select a subtile }; /** diff --git a/vpr/src/base/setup_noc.cpp b/vpr/src/base/setup_noc.cpp index ff05687c414..75313969312 100644 --- a/vpr/src/base/setup_noc.cpp +++ b/vpr/src/base/setup_noc.cpp @@ -38,7 +38,7 @@ void setup_noc(const t_arch& arch) { VPR_FATAL_ERROR(VPR_ERROR_OTHER, "The Provided NoC topology information in the architecture file " "uses less number of routers than what is available in the FPGA device."); - } else if (noc_router_tiles.empty()) { // case where no physical router tiles were found + } else if (noc_router_tiles.empty()) { // case where no physical router tiles were found VPR_FATAL_ERROR(VPR_ERROR_OTHER, "No physical NoC routers were found on the FPGA device. " "Either the provided name for the physical router tile was incorrect or the FPGA device has no routers."); @@ -169,7 +169,7 @@ void create_noc_routers(const t_noc_inf& noc_info, error_case_physical_router_index_1 = closest_physical_router; error_case_physical_router_index_2 = curr_physical_router_index; - // case where the current logical router is closest to the physical router tile + // case where the current logical router is closest to the physical router tile } else if (curr_calculated_distance < shortest_distance) { // update the shortest distance and then the closest router shortest_distance = curr_calculated_distance; diff --git a/vpr/src/base/setup_noc.h b/vpr/src/base/setup_noc.h index 4052ec4d940..9b728e0f0ab 100644 --- a/vpr/src/base/setup_noc.h +++ b/vpr/src/base/setup_noc.h @@ -39,7 +39,7 @@ // a data structure to store the position information of a noc router in the FPGA device struct t_noc_router_tile_position { - t_noc_router_tile_position(int x, int y, int layer_num, float centroid_x, float centroid_y) + t_noc_router_tile_position(int x, int y, int layer_num, float centroid_x, float centroid_y) noexcept : grid_width_position(x) , grid_height_position(y) , layer_position(layer_num) @@ -131,4 +131,4 @@ void create_noc_routers(const t_noc_inf& noc_info, */ void create_noc_links(const t_noc_inf& noc_info, NocStorage* noc_model); -#endif \ No newline at end of file +#endif diff --git a/vpr/src/base/stats.cpp b/vpr/src/base/stats.cpp index bda53d16a56..774235bf2cc 100644 --- a/vpr/src/base/stats.cpp +++ b/vpr/src/base/stats.cpp @@ -1,6 +1,12 @@ -#include + +#include "stats.h" + #include +#include +#include +#include +#include "physical_types_util.h" #include "route_tree.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -14,34 +20,45 @@ #include "rr_graph_area.h" #include "segment_stats.h" #include "channel_stats.h" -#include "stats.h" -#include "net_delay.h" -#include "read_xml_arch_file.h" -#include "echo_files.h" - -#include "timing_info.h" -#include "RoutingDelayCalculator.h" - -#include "timing_util.h" -#include "tatum/TimingReporter.hpp" /********************** Subroutines local to this module *********************/ +/** + * @brief Loads the two arrays passed in with the total occupancy at each of the + * channel segments in the FPGA. + */ static void load_channel_occupancies(const Netlist<>& net_list, vtr::Matrix& chanx_occ, vtr::Matrix& chany_occ); +/** + * @brief Writes channel occupancy data to a file. + * + * Each row contains: + * - (x, y) coordinate + * - Occupancy count + * - Occupancy percentage (occupancy / capacity) + * - Channel capacity + * + * @param filename Output file path. + * @param occupancy Matrix of occupancy counts. + * @param capacity_list List of channel capacities (per y for chanx, per x for chany). + */ +static void write_channel_occupancy_table(const std::string_view filename, + const vtr::Matrix& occupancy, + const std::vector& capacity_list); + +/** + * @brief Figures out maximum, minimum and average number of bends + * and net length in the routing. + */ static void length_and_bends_stats(const Netlist<>& net_list, bool is_flat); +///@brief Determines how many tracks are used in each channel. static void get_channel_occupancy_stats(const Netlist<>& net_list, bool /***/); /************************* Subroutine definitions ****************************/ -/** - * @brief Prints out various statistics about the current routing. - * - * Both a routing and an rr_graph must exist when you call this routine. - */ void routing_stats(const Netlist<>& net_list, bool full_stats, enum e_route_type route_type, @@ -113,10 +130,6 @@ void routing_stats(const Netlist<>& net_list, } } -/** - * @brief Figures out maximum, minimum and average number of bends - * and net length in the routing. - */ void length_and_bends_stats(const Netlist<>& net_list, bool is_flat) { int max_bends = 0; int total_bends = 0; @@ -176,9 +189,8 @@ void length_and_bends_stats(const Netlist<>& net_list, bool is_flat) { VTR_LOG("Total number of nets absorbed: %d\n", num_absorbed_nets); } -///@brief Determines how many tracks are used in each channel. static void get_channel_occupancy_stats(const Netlist<>& net_list, bool /***/) { - auto& device_ctx = g_vpr_ctx.device(); + const auto& device_ctx = g_vpr_ctx.device(); auto chanx_occ = vtr::Matrix({{ device_ctx.grid.width(), //[0 .. device_ctx.grid.width() - 1] (length of x channel) @@ -191,8 +203,12 @@ static void get_channel_occupancy_stats(const Netlist<>& net_list, bool /***/) { device_ctx.grid.height() //[0 .. device_ctx.grid.height() - 1] (length of y channel) }}, 0); + load_channel_occupancies(net_list, chanx_occ, chany_occ); + write_channel_occupancy_table("chanx_occupancy.txt", chanx_occ, device_ctx.chan_width.x_list); + write_channel_occupancy_table("chany_occupancy.txt", chany_occ, device_ctx.chan_width.y_list); + VTR_LOG("\n"); VTR_LOG("X - Directed channels: j max occ ave occ capacity\n"); VTR_LOG(" ---- ------- ------- --------\n"); @@ -233,16 +249,50 @@ static void get_channel_occupancy_stats(const Netlist<>& net_list, bool /***/) { VTR_LOG("\n"); } -/** - * @brief Loads the two arrays passed in with the total occupancy at each of the - * channel segments in the FPGA. - */ +static void write_channel_occupancy_table(const std::string_view filename, + const vtr::Matrix& occupancy, + const std::vector& capacity_list) { + constexpr int w_coord = 6; + constexpr int w_value = 12; + constexpr int w_percent = 12; + + std::ofstream file(filename.data()); + if (!file.is_open()) { + VTR_LOG_WARN("Failed to open %s for writing.\n", filename.data()); + return; + } + + file << std::setw(w_coord) << "x" + << std::setw(w_coord) << "y" + << std::setw(w_value) << "occupancy" + << std::setw(w_percent) << "%" + << std::setw(w_value) << "capacity" + << "\n"; + + for (size_t y = 0; y < occupancy.dim_size(1); ++y) { + int capacity = capacity_list[y]; + for (size_t x = 0; x < occupancy.dim_size(0); ++x) { + int occ = occupancy[x][y]; + float percent = capacity > 0 ? static_cast(occ) / capacity * 100.0f : 0.0f; + + file << std::setw(w_coord) << x + << std::setw(w_coord) << y + << std::setw(w_value) << occ + << std::setw(w_percent) << std::fixed << std::setprecision(3) << percent + << std::setw(w_value) << capacity + << "\n"; + } + } + + file.close(); +} + static void load_channel_occupancies(const Netlist<>& net_list, vtr::Matrix& chanx_occ, vtr::Matrix& chany_occ) { - auto& device_ctx = g_vpr_ctx.device(); + const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - auto& route_ctx = g_vpr_ctx.routing(); + const auto& route_ctx = g_vpr_ctx.routing(); /* First set the occupancy of everything to zero. */ chanx_occ.fill(0); @@ -258,7 +308,7 @@ static void load_channel_occupancies(const Netlist<>& net_list, if (!tree) continue; - for (auto& rt_node : tree.value().all_nodes()) { + for (const RouteTreeNode& rt_node : tree.value().all_nodes()) { RRNodeId inode = rt_node.inode; t_rr_type rr_type = rr_graph.node_type(inode); @@ -284,11 +334,9 @@ void get_num_bends_and_length(ParentNetId inet, int* bends_ptr, int* len_ptr, in auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - int bends, length, segments; - - bends = 0; - length = 0; - segments = 0; + int bends = 0; + int length = 0; + int segments = 0; const vtr::optional& tree = route_ctx.route_trees[inet]; if (!tree) { @@ -344,7 +392,7 @@ void print_wirelen_prob_dist(bool is_flat) { norm_fac = 0.; for (auto net_id : cluster_ctx.clb_nlist.nets()) { - auto par_net_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup, net_id, is_flat); + auto par_net_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup(), net_id, is_flat); if (!cluster_ctx.clb_nlist.net_is_ignored(net_id) && cluster_ctx.clb_nlist.net_sinks(net_id).size() != 0) { get_num_bends_and_length(par_net_id, &bends, &length, &segments, &is_absorbed); @@ -446,13 +494,137 @@ int count_netlist_clocks() { std::set clock_names; //Loop through each clock pin and record the names in clock_names - for (auto blk_id : atom_ctx.nlist.blocks()) { - for (auto pin_id : atom_ctx.nlist.block_clock_pins(blk_id)) { - auto net_id = atom_ctx.nlist.pin_net(pin_id); - clock_names.insert(atom_ctx.nlist.net_name(net_id)); + for (auto blk_id : atom_ctx.netlist().blocks()) { + for (auto pin_id : atom_ctx.netlist().block_clock_pins(blk_id)) { + auto net_id = atom_ctx.netlist().pin_net(pin_id); + clock_names.insert(atom_ctx.netlist().net_name(net_id)); } } //Since std::set does not include duplicates, the number of clocks is the size of the set return static_cast(clock_names.size()); } + +float calculate_device_utilization(const DeviceGrid& grid, const std::map& instance_counts) { + //Record the resources of the grid + std::map grid_resources; + for (int layer_num = 0; layer_num < grid.get_num_layers(); ++layer_num) { + for (int x = 0; x < (int)grid.width(); ++x) { + for (int y = 0; y < (int)grid.height(); ++y) { + int width_offset = grid.get_width_offset({x, y, layer_num}); + int height_offset = grid.get_height_offset({x, y, layer_num}); + if (width_offset == 0 && height_offset == 0) { + const auto& type = grid.get_physical_type({x, y, layer_num}); + ++grid_resources[type]; + } + } + } + } + + //Determine the area of grid in tile units + float grid_area = 0.; + for (auto& kv : grid_resources) { + t_physical_tile_type_ptr type = kv.first; + size_t count = kv.second; + + float type_area = type->width * type->height; + + grid_area += type_area * count; + } + + //Determine the area of instances in tile units + float instance_area = 0.; + for (auto& kv : instance_counts) { + if (is_empty_type(kv.first)) { + continue; + } + + t_physical_tile_type_ptr type = pick_physical_type(kv.first); + + size_t count = kv.second; + + float type_area = type->width * type->height; + + //Instances of multi-capaicty blocks take up less space + if (type->capacity != 0) { + type_area /= type->capacity; + } + + instance_area += type_area * count; + } + + float utilization = instance_area / grid_area; + + return utilization; +} + +void print_resource_usage() { + auto& device_ctx = g_vpr_ctx.device(); + const auto& clb_netlist = g_vpr_ctx.clustering().clb_nlist; + std::map num_type_instances; + for (auto blk_id : clb_netlist.blocks()) { + num_type_instances[clb_netlist.block_type(blk_id)]++; + } + + VTR_LOG("\n"); + VTR_LOG("Resource usage...\n"); + for (const auto& type : device_ctx.logical_block_types) { + if (is_empty_type(&type)) continue; + size_t num_instances = num_type_instances.count(&type) > 0 ? num_type_instances.at(&type) : 0; + VTR_LOG("\tNetlist\n\t\t%d\tblocks of type: %s\n", + num_instances, type.name.c_str()); + + VTR_LOG("\tArchitecture\n"); + for (const auto equivalent_tile : type.equivalent_tiles) { + //get the number of equivalent tile across all layers + num_instances = device_ctx.grid.num_instances(equivalent_tile, -1); + + VTR_LOG("\t\t%d\tblocks of type: %s\n", + num_instances, equivalent_tile->name.c_str()); + } + } + VTR_LOG("\n"); +} + +void print_device_utilization(const float target_device_utilization) { + auto& device_ctx = g_vpr_ctx.device(); + const auto& clb_netlist = g_vpr_ctx.clustering().clb_nlist; + std::map num_type_instances; + for (auto blk_id : clb_netlist.blocks()) { + num_type_instances[clb_netlist.block_type(blk_id)]++; + } + + float device_utilization = calculate_device_utilization(device_ctx.grid, num_type_instances); + VTR_LOG("Device Utilization: %.2f (target %.2f)\n", device_utilization, target_device_utilization); + for (const auto& type : device_ctx.physical_tile_types) { + if (is_empty_type(&type)) { + continue; + } + + if (device_ctx.grid.num_instances(&type, -1) != 0) { + VTR_LOG("\tPhysical Tile %s:\n", type.name.c_str()); + + auto equivalent_sites = get_equivalent_sites_set(&type); + + for (auto logical_block : equivalent_sites) { + float util = 0.; + size_t num_inst = device_ctx.grid.num_instances(&type, -1); + if (num_inst != 0) { + size_t num_netlist_instances = num_type_instances.count(logical_block) > 0 ? num_type_instances.at(logical_block) : 0; + util = float(num_netlist_instances) / num_inst; + } + VTR_LOG("\tBlock Utilization: %.2f Logical Block: %s\n", util, logical_block->name.c_str()); + } + } + } + VTR_LOG("\n"); + + if (!device_ctx.grid.limiting_resources().empty()) { + std::vector limiting_block_names; + for (auto blk_type : device_ctx.grid.limiting_resources()) { + limiting_block_names.emplace_back(blk_type->name); + } + VTR_LOG("FPGA size limited by block type(s): %s\n", vtr::join(limiting_block_names, " ").c_str()); + VTR_LOG("\n"); + } +} diff --git a/vpr/src/base/stats.h b/vpr/src/base/stats.h index d02cae8f9a0..5f9e50e0700 100644 --- a/vpr/src/base/stats.h +++ b/vpr/src/base/stats.h @@ -3,7 +3,13 @@ #include #include #include "vpr_types.h" +#include "netlist.h" +/** + * @brief Prints out various statistics about the current routing. + * + * Both a routing and an rr_graph must exist when you call this routine. + */ void routing_stats(const Netlist<>& net_list, bool full_stats, enum e_route_type route_type, @@ -24,28 +30,20 @@ void get_num_bends_and_length(ParentNetId inet, int* bends, int* length, int* se int count_netlist_clocks(); /** - * @brief template functions must be defined in header, or explicitely - * instantiated in definition file (defeats the point of template) + * @brief Calculate the device utilization + * + * Calculate the device utilization (i.e. fraction of used grid tiles) + * for the specified grid and resource requirements + */ +float calculate_device_utilization(const DeviceGrid& grid, const std::map& instance_counts); + +/** + * @brief Prints the number of resources in the netlist and the number of available resources in the architecture. + */ +void print_resource_usage(); + +/** + * @brief Prints the device utilization + * @param target_device_utilization The target device utilization set by the user */ -template -double linear_regression_vector(const std::vector& vals, size_t start_x = 0) { - // returns slope; index is x, val is y - size_t n{vals.size() - start_x}; - - double x_avg{0}, y_avg{0}; - for (size_t x = start_x; x < vals.size(); ++x) { - x_avg += x; - y_avg += vals[x]; - } - x_avg /= (double)n; - y_avg /= (double)n; - - double numerator = 0, denominator = 0; - for (size_t x = start_x; x < vals.size(); ++x) { - numerator += (x - x_avg) * (vals[x] - y_avg); - denominator += (x - x_avg) * (x - x_avg); - } - - if (denominator == 0) return std::numeric_limits::max(); - return numerator / denominator; -} +void print_device_utilization(const float target_device_utilization); diff --git a/vpr/src/base/user_route_constraints.cpp b/vpr/src/base/user_route_constraints.cpp index 67cabe6b20e..b6d3f1b0384 100644 --- a/vpr/src/base/user_route_constraints.cpp +++ b/vpr/src/base/user_route_constraints.cpp @@ -72,4 +72,4 @@ const std::string UserRouteConstraints::get_routing_network_name_by_net_name(std int UserRouteConstraints::get_num_route_constraints(void) const { return route_constraints_.size(); -} \ No newline at end of file +} diff --git a/vpr/src/base/user_route_constraints.h b/vpr/src/base/user_route_constraints.h index ec925d7887d..62ba08cda1d 100644 --- a/vpr/src/base/user_route_constraints.h +++ b/vpr/src/base/user_route_constraints.h @@ -153,4 +153,4 @@ class UserRouteConstraints { */ std::unordered_map route_constraints_; }; -#endif /* USER_ROUTE_CONSTRAINTS_H */ \ No newline at end of file +#endif /* USER_ROUTE_CONSTRAINTS_H */ diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 1560b03e90f..6b2acb57dcf 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -14,12 +14,17 @@ #include #include #include +#include +#include +#include "PreClusterTimingManager.h" +#include "flat_placement_types.h" #include "cluster_util.h" +#include "physical_types.h" +#include "place_macro.h" #include "verify_placement.h" #include "vpr_context.h" #include "vtr_assert.h" -#include "vtr_math.h" #include "vtr_log.h" #include "vtr_version.h" #include "vtr_time.h" @@ -30,7 +35,6 @@ #include "atom_netlist.h" #include "read_netlist.h" #include "check_netlist.h" -#include "read_blif.h" #include "draw.h" #include "place_and_route.h" #include "pack.h" @@ -67,7 +71,6 @@ #include "atom_netlist_utils.h" #include "output_clustering.h" #include "vpr_constraints_reader.h" -#include "place_constraints.h" #include "place_util.h" #include "timing_fail_error.h" #include "analytical_placement_flow.h" @@ -93,9 +96,9 @@ #include "load_flat_place.h" #ifdef VPR_USE_TBB -# define TBB_PREVIEW_GLOBAL_CONTROL 1 /* Needed for compatibility with old TBB versions */ -# include -# include +#define TBB_PREVIEW_GLOBAL_CONTROL 1 /* Needed for compatibility with old TBB versions */ +#include +#include #endif #ifndef NO_SERVER @@ -109,12 +112,6 @@ static void free_complex_block_types(); static void free_device(const t_det_routing_arch& routing_arch); static void free_circuit(); -static void get_intercluster_switch_fanin_estimates(const t_vpr_setup& vpr_setup, - const t_arch& arch, - const int wire_segment_length, - int* opin_switch_fanin, - int* wire_switch_fanin, - int* ipin_switch_fanin); /* Local subroutines end */ ///@brief Display general VPR information @@ -320,13 +317,13 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a /* Read blif file and sweep unused components */ auto& atom_ctx = g_vpr_ctx.mutable_atom(); - atom_ctx.nlist = read_and_process_circuit(options->circuit_format, *vpr_setup, *arch); + atom_ctx.mutable_netlist() = read_and_process_circuit(options->circuit_format, *vpr_setup, *arch); if (vpr_setup->PowerOpts.do_power) { //Load the net activity file for power estimation vtr::ScopedStartFinishTimer t("Load Activity File"); auto& power_ctx = g_vpr_ctx.mutable_power(); - power_ctx.atom_net_power = read_activity(atom_ctx.nlist, vpr_setup->FileNameOpts.ActFile.c_str()); + power_ctx.atom_net_power = read_activity(atom_ctx.netlist(), vpr_setup->FileNameOpts.ActFile.c_str()); } //Initialize timing graph and constraints @@ -334,17 +331,17 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a auto& timing_ctx = g_vpr_ctx.mutable_timing(); { vtr::ScopedStartFinishTimer t("Build Timing Graph"); - timing_ctx.graph = TimingGraphBuilder(atom_ctx.nlist, atom_ctx.lookup).timing_graph(options->allow_dangling_combinational_nodes); + timing_ctx.graph = TimingGraphBuilder(atom_ctx.netlist(), atom_ctx.mutable_lookup()).timing_graph(options->allow_dangling_combinational_nodes); VTR_LOG(" Timing Graph Nodes: %zu\n", timing_ctx.graph->nodes().size()); VTR_LOG(" Timing Graph Edges: %zu\n", timing_ctx.graph->edges().size()); VTR_LOG(" Timing Graph Levels: %zu\n", timing_ctx.graph->levels().size()); } { - print_netlist_clock_info(atom_ctx.nlist); + print_netlist_clock_info(atom_ctx.netlist()); } { vtr::ScopedStartFinishTimer t("Load Timing Constraints"); - timing_ctx.constraints = read_sdc(vpr_setup->Timing, atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph); + timing_ctx.constraints = read_sdc(vpr_setup->Timing, atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph); } { set_terminate_if_timing_fails(options->terminate_if_timing_fails); @@ -389,9 +386,16 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { } } - // For the time being, we decided to create the flat graph after placement is done. Thus, the is_flat parameter for this function - //, since it is called before routing, should be false. - vpr_create_device(vpr_setup, arch, false); + vpr_create_device(vpr_setup, arch); + // If packing is not skipped, cluster netlist contain valid information, so + // we can print the resource usage and device utilization + if (vpr_setup.PackerOpts.doPacking != STAGE_SKIP) { + float target_device_utilization = vpr_setup.PackerOpts.target_device_utilization; + // Print the number of resources in netlist and number of resources available in architecture + print_resource_usage(); + // Print the device utilization + print_device_utilization(target_device_utilization); + } // TODO: Placer still assumes that cluster net list is used - graphics can not work with flat routing yet vpr_init_graphics(vpr_setup, arch, false); @@ -409,8 +413,23 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { { // Analytical Place if (vpr_setup.APOpts.doAP == STAGE_DO) { + // Passing flat placement input if provided and not loaded yet. + if (!vpr_setup.FileNameOpts.read_flat_place_file.empty() && !g_vpr_ctx.atom().flat_placement_info().valid) { + g_vpr_ctx.mutable_atom().mutable_flat_placement_info() = read_flat_placement(vpr_setup.FileNameOpts.read_flat_place_file, + g_vpr_ctx.atom().netlist()); + } + // TODO: Make this return a bool if the placement was successful or not. run_analytical_placement_flow(vpr_setup); + + // Write out a flat placement file at the end of Analytical Placement + // flow if the option is specified. + if (!vpr_setup.FileNameOpts.write_flat_place_file.empty()) { + write_flat_placement(vpr_setup.FileNameOpts.write_flat_place_file.c_str(), + g_vpr_ctx.clustering().clb_nlist, + g_vpr_ctx.placement().block_locs(), + g_vpr_ctx.clustering().atoms_lookup); + } } // Print the placement generated by AP to a .place file. auto& filename_opts = vpr_setup.FileNameOpts; @@ -424,7 +443,7 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { } bool is_flat = vpr_setup.RouterOpts.flat_routing; - const Netlist<>& router_net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + const Netlist<>& router_net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; RouteStatus route_status; { //Route route_status = vpr_route_flow(router_net_list, vpr_setup, arch, is_flat); @@ -439,7 +458,7 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { return route_status.success(); } -void vpr_create_device(t_vpr_setup& vpr_setup, const t_arch& arch, bool is_flat) { +void vpr_create_device(t_vpr_setup& vpr_setup, const t_arch& arch) { vtr::ScopedStartFinishTimer timer("Create Device"); vpr_create_device_grid(vpr_setup, arch); @@ -448,7 +467,9 @@ void vpr_create_device(t_vpr_setup& vpr_setup, const t_arch& arch, bool is_flat) vpr_setup_noc(vpr_setup, arch); if (vpr_setup.PlacerOpts.place_chan_width != NO_FIXED_CHANNEL_WIDTH) { - vpr_create_rr_graph(vpr_setup, arch, vpr_setup.PlacerOpts.place_chan_width, is_flat); + // The RR graph built by this function should contain only the intra-cluster resources. + // If the flat router is used, additional resources are added when routing begins. + vpr_create_rr_graph(vpr_setup, arch, vpr_setup.PlacerOpts.place_chan_width, false); } } @@ -491,59 +512,6 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) { */ size_t num_grid_tiles = count_grid_tiles(device_ctx.grid); VTR_LOG("FPGA sized to %zu x %zu: %zu grid tiles (%s)\n", device_ctx.grid.width(), device_ctx.grid.height(), num_grid_tiles, device_ctx.grid.name().c_str()); - - VTR_LOG("\n"); - VTR_LOG("Resource usage...\n"); - for (const auto& type : device_ctx.logical_block_types) { - if (is_empty_type(&type)) continue; - - VTR_LOG("\tNetlist\n\t\t%d\tblocks of type: %s\n", - num_type_instances[&type], type.name.c_str()); - - VTR_LOG("\tArchitecture\n"); - for (const auto equivalent_tile : type.equivalent_tiles) { - auto num_instances = 0; - //get the number of equivalent tile across all layers - num_instances = (int)device_ctx.grid.num_instances(equivalent_tile, -1); - - VTR_LOG("\t\t%d\tblocks of type: %s\n", - num_instances, equivalent_tile->name.c_str()); - } - } - VTR_LOG("\n"); - - float device_utilization = calculate_device_utilization(device_ctx.grid, num_type_instances); - VTR_LOG("Device Utilization: %.2f (target %.2f)\n", device_utilization, target_device_utilization); - for (const auto& type : device_ctx.physical_tile_types) { - if (is_empty_type(&type)) { - continue; - } - - if (device_ctx.grid.num_instances(&type, -1) != 0) { - VTR_LOG("\tPhysical Tile %s:\n", type.name.c_str()); - - auto equivalent_sites = get_equivalent_sites_set(&type); - - for (auto logical_block : equivalent_sites) { - float util = 0.; - size_t num_inst = device_ctx.grid.num_instances(&type, -1); - if (num_inst != 0) { - util = float(num_type_instances[logical_block]) / num_inst; - } - VTR_LOG("\tBlock Utilization: %.2f Logical Block: %s\n", util, logical_block->name.c_str()); - } - } - } - VTR_LOG("\n"); - - if (!device_ctx.grid.limiting_resources().empty()) { - std::vector limiting_block_names; - for (auto blk_type : device_ctx.grid.limiting_resources()) { - limiting_block_names.emplace_back(blk_type->name); - } - VTR_LOG("FPGA size limited by block type(s): %s\n", vtr::join(limiting_block_names, " ").c_str()); - VTR_LOG("\n"); - } } void vpr_setup_clock_networks(t_vpr_setup& vpr_setup, const t_arch& Arch) { @@ -644,60 +612,39 @@ bool vpr_pack_flow(t_vpr_setup& vpr_setup, const t_arch& arch) { bool vpr_pack(t_vpr_setup& vpr_setup, const t_arch& arch) { vtr::ScopedStartFinishTimer timer("Packing"); - /* If needed, estimate inter-cluster delay. Assume the average routing hop goes out of - * a block through an opin switch to a length-4 wire, then through a wire switch to another - * length-4 wire, then through a wire-to-ipin-switch into another block. */ - int wire_segment_length = 4; - - float inter_cluster_delay = UNDEFINED; - if (vpr_setup.PackerOpts.timing_driven - && vpr_setup.PackerOpts.auto_compute_inter_cluster_net_delay) { - /* We want to determine a reasonable fan-in to the opin, wire, and ipin switches, based - * on which the intercluster delays can be estimated. The fan-in of a switch influences its - * delay. - * - * The fan-in of the switch depends on the architecture (unidirectional/bidirectional), as - * well as Fc_in/out and Fs */ - int opin_switch_fanin, wire_switch_fanin, ipin_switch_fanin; - get_intercluster_switch_fanin_estimates(vpr_setup, arch, wire_segment_length, &opin_switch_fanin, - &wire_switch_fanin, &ipin_switch_fanin); - - float Tdel_opin_switch, R_opin_switch, Cout_opin_switch; - float opin_switch_del = get_arch_switch_info(arch.Segments[0].arch_opin_switch, opin_switch_fanin, - Tdel_opin_switch, R_opin_switch, Cout_opin_switch); - - float Tdel_wire_switch, R_wire_switch, Cout_wire_switch; - float wire_switch_del = get_arch_switch_info(arch.Segments[0].arch_wire_switch, wire_switch_fanin, - Tdel_wire_switch, R_wire_switch, Cout_wire_switch); - - float Tdel_wtoi_switch, R_wtoi_switch, Cout_wtoi_switch; - float wtoi_switch_del = get_arch_switch_info(vpr_setup.RoutingArch.wire_to_arch_ipin_switch, ipin_switch_fanin, - Tdel_wtoi_switch, R_wtoi_switch, Cout_wtoi_switch); - - float Rmetal = arch.Segments[0].Rmetal; - float Cmetal = arch.Segments[0].Cmetal; - - /* The delay of a wire with its driving switch is the switch delay plus the - * product of the equivalent resistance and capacitance experienced by the wire. */ - - float first_wire_seg_delay = opin_switch_del - + (R_opin_switch + Rmetal * (float)wire_segment_length / 2) - * (Cout_opin_switch + Cmetal * (float)wire_segment_length); - float second_wire_seg_delay = wire_switch_del - + (R_wire_switch + Rmetal * (float)wire_segment_length / 2) - * (Cout_wire_switch + Cmetal * (float)wire_segment_length); - inter_cluster_delay = 4 - * (first_wire_seg_delay + second_wire_seg_delay - + wtoi_switch_del); /* multiply by 4 to get a more conservative estimate */ + // Read in the flat placement if a flat placement file is provided and it + // has not been loaded already. + if (!vpr_setup.FileNameOpts.read_flat_place_file.empty() && !g_vpr_ctx.atom().flat_placement_info().valid) { + g_vpr_ctx.mutable_atom().mutable_flat_placement_info() = read_flat_placement(vpr_setup.FileNameOpts.read_flat_place_file, + g_vpr_ctx.atom().netlist()); } - return try_pack(&vpr_setup.PackerOpts, &vpr_setup.AnalysisOpts, - &arch, vpr_setup.user_models, - vpr_setup.library_models, inter_cluster_delay, - vpr_setup.PackerRRGraph); + // Run the prepacker, packing the atoms into molecules. + // The Prepacker object performs prepacking and stores the pack molecules. + // As long as the molecules are used, this object must persist. + const Prepacker prepacker(g_vpr_ctx.atom().netlist(), + g_vpr_ctx.device().logical_block_types); + + // Setup pre-clustering timing analysis + PreClusterTimingManager pre_cluster_timing_manager(vpr_setup.PackerOpts.timing_driven, + g_vpr_ctx.atom().netlist(), + g_vpr_ctx.atom().lookup(), + prepacker, + vpr_setup.PackerOpts.timing_update_type, + arch, + vpr_setup.RoutingArch, + vpr_setup.PackerOpts.device_layout, + vpr_setup.AnalysisOpts); + + return try_pack(vpr_setup.PackerOpts, vpr_setup.AnalysisOpts, + arch, + vpr_setup.PackerRRGraph, + prepacker, + pre_cluster_timing_manager, + g_vpr_ctx.atom().flat_placement_info()); } -void vpr_load_packing(t_vpr_setup& vpr_setup, const t_arch& arch) { +void vpr_load_packing(const t_vpr_setup& vpr_setup, const t_arch& arch) { vtr::ScopedStartFinishTimer timer("Load packing"); VTR_ASSERT_MSG(!vpr_setup.FileNameOpts.NetFile.empty(), @@ -718,8 +665,8 @@ void vpr_load_packing(t_vpr_setup& vpr_setup, const t_arch& arch) { /* Load the mapping between clusters and their atoms */ init_clb_atoms_lookup(cluster_ctx.atoms_lookup, atom_ctx, cluster_ctx.clb_nlist); - process_constant_nets(g_vpr_ctx.mutable_atom().nlist, - atom_ctx.lookup, + process_constant_nets(g_vpr_ctx.mutable_atom().mutable_netlist(), + atom_ctx.lookup(), cluster_ctx.clb_nlist, vpr_setup.constant_net_method, vpr_setup.PackerOpts.pack_verbosity); @@ -729,8 +676,9 @@ void vpr_load_packing(t_vpr_setup& vpr_setup, const t_arch& arch) { report_packing_pin_usage(ofs, g_vpr_ctx); } - // Load cluster_constraints data structure. - load_cluster_constraints(); + // Ater the clustered netlist has been loaded, update the floorplanning + // constraints with the new information. + g_vpr_ctx.mutable_floorplanning().update_floorplanning_context_post_pack(); /* Sanity check the resulting netlist */ check_netlist(vpr_setup.PackerOpts.pack_verbosity); @@ -789,7 +737,9 @@ bool vpr_load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { return true; } -bool vpr_place_flow(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& arch) { +bool vpr_place_flow(const Netlist<>& net_list, + t_vpr_setup& vpr_setup, + const t_arch& arch) { VTR_LOG("\n"); const auto& placer_opts = vpr_setup.PlacerOpts; const auto& filename_opts = vpr_setup.FileNameOpts; @@ -804,7 +754,7 @@ bool vpr_place_flow(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_a VTR_ASSERT(placer_opts.doPlacement == STAGE_LOAD); //Load a previous placement - vpr_load_placement(vpr_setup, arch); + vpr_load_placement(vpr_setup, arch.directs); } post_place_sync(); @@ -829,7 +779,9 @@ bool vpr_place_flow(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_a return true; } -void vpr_place(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& arch) { +void vpr_place(const Netlist<>& net_list, + t_vpr_setup& vpr_setup, + const t_arch& arch) { bool is_flat = false; if (vpr_setup.PlacerOpts.place_algorithm.is_timing_driven()) { // Prime lookahead cache to avoid adding lookahead computation cost to @@ -844,6 +796,13 @@ void vpr_place(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& is_flat); } + // Read in the flat placement if a flat placement file is provided and it + // has not been loaded already. + if (!vpr_setup.FileNameOpts.read_flat_place_file.empty() && !g_vpr_ctx.atom().flat_placement_info().valid) { + g_vpr_ctx.mutable_atom().mutable_flat_placement_info() = read_flat_placement(vpr_setup.FileNameOpts.read_flat_place_file, + g_vpr_ctx.atom().netlist()); + } + try_place(net_list, vpr_setup.PlacerOpts, vpr_setup.RouterOpts, @@ -853,6 +812,7 @@ void vpr_place(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& &vpr_setup.RoutingArch, vpr_setup.Segments, arch.directs, + g_vpr_ctx.atom().flat_placement_info(), is_flat); auto& filename_opts = vpr_setup.FileNameOpts; @@ -866,7 +826,8 @@ void vpr_place(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& block_locs); } -void vpr_load_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { +void vpr_load_placement(t_vpr_setup& vpr_setup, + const std::vector directs) { vtr::ScopedStartFinishTimer timer("Load Placement"); const auto& device_ctx = g_vpr_ctx.device(); @@ -874,8 +835,15 @@ void vpr_load_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { auto& blk_loc_registry = place_ctx.mutable_blk_loc_registry(); const auto& filename_opts = vpr_setup.FileNameOpts; - //Initialize placement data structures, which will be filled when loading placement - init_placement_context(blk_loc_registry, arch.directs); + //Initialize the block location registry, which will be filled when loading placement + blk_loc_registry.init(); + + // Alloc and load the placement macros. + place_ctx.place_macros = std::make_unique(directs, + device_ctx.physical_tile_types, + g_vpr_ctx.clustering().clb_nlist, + g_vpr_ctx.atom().netlist(), + g_vpr_ctx.atom().lookup()); //Load an existing placement from a file place_ctx.placement_id = read_place(filename_opts.NetFile.c_str(), filename_opts.PlaceFile.c_str(), @@ -927,7 +895,7 @@ RouteStatus vpr_route_flow(const Netlist<>& net_list, std::shared_ptr routing_delay_calc = nullptr; if (vpr_setup.Timing.timing_analysis_enabled) { auto& atom_ctx = g_vpr_ctx.atom(); - routing_delay_calc = std::make_shared(atom_ctx.nlist, atom_ctx.lookup, net_delay, is_flat); + routing_delay_calc = std::make_shared(atom_ctx.netlist(), atom_ctx.lookup(), net_delay, is_flat); timing_info = make_setup_hold_timing_info(routing_delay_calc, router_opts.timing_update_type); #ifndef NO_SERVER if (g_vpr_ctx.server().gate_io.is_running()) { @@ -1118,7 +1086,7 @@ RouteStatus vpr_load_routing(t_vpr_setup& vpr_setup, //Load the routing from a file bool is_legal = read_route(filename_opts.RouteFile.c_str(), vpr_setup.RouterOpts, filename_opts.verify_file_digests, is_flat); - const Netlist<>& router_net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + const Netlist<>& router_net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; if (vpr_setup.Timing.timing_analysis_enabled) { //Update timing info load_net_delay_from_routing(router_net_list, @@ -1135,17 +1103,18 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi auto det_routing_arch = &vpr_setup.RoutingArch; auto& router_opts = vpr_setup.RouterOpts; - t_graph_type graph_type; - t_graph_type graph_directionality; + e_graph_type graph_type; + e_graph_type graph_directionality; if (router_opts.route_type == GLOBAL) { - graph_type = GRAPH_GLOBAL; - graph_directionality = GRAPH_BIDIR; + graph_type = e_graph_type::GLOBAL; + graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); - if ((UNI_DIRECTIONAL == det_routing_arch->directionality) && (true == det_routing_arch->tileable)) { - graph_type = GRAPH_UNIDIR_TILEABLE; + graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + /* Branch on tileable routing */ + if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + graph_type = e_graph_type::UNIDIR_TILEABLE; } + graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } t_chan_width chan_width = init_chan(chan_width_fac, arch.Chans, graph_directionality); @@ -1199,100 +1168,6 @@ void vpr_close_graphics(const t_vpr_setup& /*vpr_setup*/) { free_draw_structs(); } -/** - * Since the parameters of a switch may change as a function of its fanin, - * to get an estimation of inter-cluster delays we need a reasonable estimation - * of the fan-ins of switches that connect clusters together. These switches are - * 1) opin to wire switch - * 2) wire to wire switch - * 3) wire to ipin switch - * We can estimate the fan-in of these switches based on the Fc_in/Fc_out of - * a logic block, and the switch block Fs value - */ -static void get_intercluster_switch_fanin_estimates(const t_vpr_setup& vpr_setup, - const t_arch& arch, - const int wire_segment_length, - int* opin_switch_fanin, - int* wire_switch_fanin, - int* ipin_switch_fanin) { - e_directionality directionality; - int Fs; - float Fc_in, Fc_out; - int W = 100; //W is unknown pre-packing, so *if* we need W here, we will assume a value of 100 - - directionality = vpr_setup.RoutingArch.directionality; - Fs = vpr_setup.RoutingArch.Fs; - Fc_in = 0, Fc_out = 0; - - //Build a dummy 10x10 device to determine the 'best' block type to use - auto grid = create_device_grid(vpr_setup.device_layout, arch.grid_layouts, 10, 10); - - auto type = find_most_common_tile_type(grid); - /* get Fc_in/out for most common block (e.g. logic blocks) */ - VTR_ASSERT(!type->fc_specs.empty()); - - //Estimate the maximum Fc_in/Fc_out - - for (const t_fc_specification& fc_spec : type->fc_specs) { - float Fc = fc_spec.fc_value; - - if (fc_spec.fc_value_type == e_fc_value_type::ABSOLUTE) { - //Convert to estimated fractional - Fc /= W; - } - VTR_ASSERT_MSG(Fc >= 0 && Fc <= 1., "Fc should be fractional"); - - for (int ipin : fc_spec.pins) { - e_pin_type pin_type = get_pin_type_from_pin_physical_num(type, ipin); - - if (pin_type == DRIVER) { - Fc_out = std::max(Fc, Fc_out); - } else { - VTR_ASSERT(pin_type == RECEIVER); - Fc_in = std::max(Fc, Fc_in); - } - } - } - - /* Estimates of switch fan-in are done as follows: - * 1) opin to wire switch: - * 2 CLBs connect to a channel, each with #opins/4 pins. Each pin has Fc_out*W - * switches, and then we assume the switches are distributed evenly over the W wires. - * In the unidirectional case, all these switches are then crammed down to W/wire_segment_length wires. - * - * Unidirectional: 2 * #opins_per_side * Fc_out * wire_segment_length - * Bidirectional: 2 * #opins_per_side * Fc_out - * - * 2) wire to wire switch - * A wire segment in a switchblock connects to Fs other wires. Assuming these connections are evenly - * distributed, each target wire receives Fs connections as well. In the unidirectional case, - * source wires can only connect to W/wire_segment_length wires. - * - * Unidirectional: Fs * wire_segment_length - * Bidirectional: Fs - * - * 3) wire to ipin switch - * An input pin of a CLB simply receives Fc_in connections. - * - * Unidirectional: Fc_in - * Bidirectional: Fc_in - */ - - /* Fan-in to opin/ipin/wire switches depends on whether the architecture is unidirectional/bidirectional */ - (*opin_switch_fanin) = 2 * type->num_drivers / 4 * Fc_out; - (*wire_switch_fanin) = Fs; - (*ipin_switch_fanin) = Fc_in; - if (directionality == UNI_DIRECTIONAL) { - /* adjustments to opin-to-wire and wire-to-wire switch fan-ins */ - (*opin_switch_fanin) *= wire_segment_length; - (*wire_switch_fanin) *= wire_segment_length; - } else if (directionality == BI_DIRECTIONAL) { - /* no adjustments need to be made here */ - } else { - VPR_FATAL_ERROR(VPR_ERROR_PACK, "Unrecognized directionality: %d\n", (int)directionality); - } -} - ///@brief Free architecture data structures void free_device(const t_det_routing_arch& /*routing_arch*/) { auto& device_ctx = g_vpr_ctx.mutable_device(); @@ -1328,8 +1203,8 @@ void free_circuit() { static void free_atoms() { auto& atom_ctx = g_vpr_ctx.mutable_atom(); - atom_ctx.nlist = AtomNetlist(); - atom_ctx.lookup = AtomLookup(); + atom_ctx.mutable_netlist() = AtomNetlist(); + atom_ctx.mutable_lookup() = AtomLookup(); } static void free_placement() { @@ -1505,12 +1380,12 @@ bool vpr_analysis_flow(const Netlist<>& net_list, if (is_flat) { sync_netlists_to_routing_flat(); } else { - sync_netlists_to_routing(net_list, - g_vpr_ctx.device(), - g_vpr_ctx.mutable_atom(), - g_vpr_ctx.mutable_clustering(), - g_vpr_ctx.placement(), - vpr_setup.PackerOpts.pack_verbosity > 2); + sync_netlists_to_routing(net_list, + g_vpr_ctx.device(), + g_vpr_ctx.mutable_atom(), + g_vpr_ctx.mutable_clustering(), + g_vpr_ctx.placement(), + vpr_setup.PackerOpts.pack_verbosity > 2); } } else { VTR_LOG_WARN("Sychronization between packing and routing results is not applied due to users select to skip it\n"); @@ -1518,8 +1393,8 @@ bool vpr_analysis_flow(const Netlist<>& net_list, std::string post_routing_packing_output_file_name = vpr_setup.PackerOpts.output_file + ".post_routing"; write_packing_results_to_xml(vpr_setup.PackerOpts.global_clocks, - Arch.architecture_id, - post_routing_packing_output_file_name.c_str()); + Arch.architecture_id, + post_routing_packing_output_file_name.c_str()); } else { VTR_LOG_WARN("Synchronization between packing and routing results is not applied due to illegal circuit implementation\n"); } @@ -1565,7 +1440,7 @@ void vpr_analysis(const Netlist<>& net_list, load_net_delay_from_routing(net_list, net_delay); //Do final timing analysis - auto analysis_delay_calc = std::make_shared(atom_ctx.nlist, atom_ctx.lookup, net_delay, vpr_setup.RouterOpts.flat_routing); + auto analysis_delay_calc = std::make_shared(atom_ctx.netlist(), atom_ctx.lookup(), net_delay, vpr_setup.RouterOpts.flat_routing); auto timing_info = make_setup_hold_timing_info(analysis_delay_calc, vpr_setup.AnalysisOpts.timing_update_type); timing_info->update(); @@ -1584,13 +1459,13 @@ void vpr_analysis(const Netlist<>& net_list, //Write the post-synthesis netlist if (vpr_setup.AnalysisOpts.gen_post_synthesis_netlist) { - netlist_writer(atom_ctx.nlist.netlist_name(), analysis_delay_calc, + netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, vpr_setup.AnalysisOpts); } //Write the post-implementation merged netlist if (vpr_setup.AnalysisOpts.gen_post_implementation_merged_netlist) { - merged_netlist_writer(atom_ctx.nlist.netlist_name(), analysis_delay_calc, vpr_setup.AnalysisOpts); + merged_netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, vpr_setup.AnalysisOpts); } //Do power analysis diff --git a/vpr/src/base/vpr_api.h b/vpr/src/base/vpr_api.h index 93cf2d12cc1..7eda169ba5e 100644 --- a/vpr/src/base/vpr_api.h +++ b/vpr/src/base/vpr_api.h @@ -63,7 +63,7 @@ bool vpr_pack_flow(t_vpr_setup& vpr_setup, const t_arch& arch); bool vpr_pack(t_vpr_setup& vpr_setup, const t_arch& arch); ///@brief Loads a previous packing -void vpr_load_packing(t_vpr_setup& vpr_setup, const t_arch& arch); +void vpr_load_packing(const t_vpr_setup& vpr_setup, const t_arch& arch); ///@brief Reconstructs a packing and placement solution from a flat placement file bool vpr_load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch); @@ -71,13 +71,18 @@ bool vpr_load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch); /* Placement */ ///@brief Perform, load or skip the placement stage -bool vpr_place_flow(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& arch); +bool vpr_place_flow(const Netlist<>& net_list, + t_vpr_setup& vpr_setup, + const t_arch& arch); ///@brief Perform placement -void vpr_place(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& arch); +void vpr_place(const Netlist<>& net_list, + t_vpr_setup& vpr_setup, + const t_arch& arch); ///@brief Loads a previous placement -void vpr_load_placement(t_vpr_setup& vpr_setup, const t_arch& arch); +void vpr_load_placement(t_vpr_setup& vpr_setup, + const std::vector directs); /* Routing */ @@ -133,7 +138,7 @@ void vpr_analysis(const Netlist<>& net_list, /* Device creating */ ///@brief Create the device (grid + rr graph) -void vpr_create_device(t_vpr_setup& vpr_setup, const t_arch& Arch, bool is_flat); +void vpr_create_device(t_vpr_setup& vpr_setup, const t_arch& Arch); ///@brief Create the device grid void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch); diff --git a/vpr/src/base/vpr_constraints_serializer.h b/vpr/src/base/vpr_constraints_serializer.h index 9cfd47829c2..409a7702661 100644 --- a/vpr/src/base/vpr_constraints_serializer.h +++ b/vpr/src/base/vpr_constraints_serializer.h @@ -129,7 +129,7 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase +#include "compressed_grid.h" +#include "globals.h" +#include "physical_types.h" +#include "place_constraints.h" +#include "place_macro.h" +#include "vpr_types.h" +#include "vtr_memory.h" + +/** + * @brief determine the type of the bounding box used by the placer to predict + * the wirelength. + * + * @param place_bb_mode The bounding box mode passed by the CLI + * @param rr_graph The routing resource graph + */ +static bool is_cube_bb(const e_place_bounding_box_mode place_bb_mode, + const RRGraphView& rr_graph); + +void FloorplanningContext::update_floorplanning_context_post_pack() { + // Initialize the cluster_constraints using the constraints loaded from the + // user and clustering generated from packing. + load_cluster_constraints(); +} + +void FloorplanningContext::update_floorplanning_context_pre_place(const PlaceMacros& place_macros) { + // Go through cluster blocks to calculate the tightest placement + // floorplan constraint for each constrained block. + propagate_place_constraints(place_macros); + + // Compute and store compressed floorplanning constraints. + alloc_and_load_compressed_cluster_constraints(); +} + +void FloorplanningContext::clean_floorplanning_context_post_place() { + // The cluster constraints are loaded in propagate_place_constraints and are + // not used outside of placement. + vtr::release_memory(cluster_constraints); + + // The compressed cluster constraints are loaded in alloc_and_load_compressed + // cluster_constraints and are not used outside of placement. + vtr::release_memory(compressed_cluster_constraints); +} + +void PlacementContext::init_placement_context(const t_placer_opts& placer_opts, + const std::vector& directs) { + const AtomContext& atom_ctx = g_vpr_ctx.atom(); + const ClusteringContext& cluster_ctx = g_vpr_ctx.clustering(); + const DeviceContext& device_ctx = g_vpr_ctx.device(); + + cube_bb = is_cube_bb(placer_opts.place_bounding_box_mode, device_ctx.rr_graph); + + compressed_block_grids = create_compressed_block_grids(); + + // Alloc and load the placement macros. + place_macros = std::make_unique(directs, + device_ctx.physical_tile_types, + cluster_ctx.clb_nlist, + atom_ctx.netlist(), + atom_ctx.lookup()); +} + +static bool is_cube_bb(const e_place_bounding_box_mode place_bb_mode, + const RRGraphView& rr_graph) { + bool cube_bb; + const int number_layers = g_vpr_ctx.device().grid.get_num_layers(); + + if (place_bb_mode == e_place_bounding_box_mode::AUTO_BB) { + // If the auto_bb is used, we analyze the RR graph to see whether is there any inter-layer connection that is not + // originated from OPIN. If there is any, cube BB is chosen, otherwise, per-layer bb is chosen. + if (number_layers > 1 && inter_layer_connections_limited_to_opin(rr_graph)) { + cube_bb = false; + } else { + cube_bb = true; + } + } else if (place_bb_mode == e_place_bounding_box_mode::CUBE_BB) { + // The user has specifically asked for CUBE_BB + cube_bb = true; + } else { + // The user has specifically asked for PER_LAYER_BB + VTR_ASSERT_SAFE(place_bb_mode == e_place_bounding_box_mode::PER_LAYER_BB); + cube_bb = false; + } + + return cube_bb; +} + +void PlacementContext::clean_placement_context_post_place() { + // The compressed block grids are currently only used during placement. + vtr::release_memory(compressed_block_grids); +} diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 1472aa054af..dcab8832f53 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -5,19 +5,20 @@ #include #include -#include "prepack.h" +#include "flat_placement_types.h" +#include "physical_types.h" +#include "place_macro.h" +#include "user_place_constraints.h" +#include "user_route_constraints.h" #include "vpr_types.h" -#include "vtr_ndmatrix.h" #include "vtr_optional.h" #include "vtr_vector.h" #include "vtr_vector_map.h" #include "atom_netlist.h" #include "clustered_netlist.h" #include "rr_graph_view.h" -#include "rr_graph_storage.h" #include "rr_graph_builder.h" #include "rr_node.h" -#include "rr_rc_data.h" #include "tatum/TimingGraph.hpp" #include "tatum/TimingConstraints.hpp" #include "power.h" @@ -27,10 +28,7 @@ #include "clock_connection_builders.h" #include "route_tree.h" #include "router_lookahead.h" -#include "place_macro.h" #include "compressed_grid.h" -#include "metadata_storage.h" -#include "vpr_constraints.h" #include "noc_storage.h" #include "noc_traffic_flows.h" #include "noc_routing.h" @@ -69,16 +67,50 @@ struct Context { * * This should contain only data structures related to user specified netlist * being implemented by VPR onto the target device. + * + * This class provides two categories of getter functions that give mutable or + * immutable reference to the global state. If you need read-only access, use + * the normal getter functions and if you need write access to the context use + * the mutable functions. */ struct AtomContext : public Context { /******************************************************************** * Atom Netlist ********************************************************************/ + private: /// @brief Atom netlist - AtomNetlist nlist; - + AtomNetlist nlist_; /// @brief Mappings to/from the Atom Netlist to physically described .blif models - AtomLookup lookup; + AtomLookup lookup_; + /// @brief Placement information on each atom known (from a file or another + /// algorithm) before packing and the cluster-level placement. + FlatPlacementInfo flat_placement_info_; + + public: + /** + * @brief Immutable reference to the AtomNetlist + */ + inline const AtomNetlist& netlist() const { return nlist_; } + /** + * @brief Mutable reference to the AtomNetlist + */ + inline AtomNetlist& mutable_netlist() { return nlist_; } + /** + * @brief Immutable reference to the AtomLookup + */ + inline const AtomLookup& lookup() const { return lookup_; } + /** + * @brief Mutable reference to the AtomLookup + */ + inline AtomLookup& mutable_lookup() { return lookup_; } + /** + * @brief Immutable reference to the FlatPlacementInfo + */ + inline const FlatPlacementInfo& flat_placement_info() const { return flat_placement_info_; } + /** + * @brief Mutable reference to the FlatPlacementInfo + */ + inline FlatPlacementInfo& mutable_flat_placement_info() { return flat_placement_info_; } }; /** @@ -246,12 +278,15 @@ struct DeviceContext : public Context { ********************************************************************/ t_clock_arch* clock_arch; - /** - * @brief Name of rrgraph file read (if any). - * - * Used to determine when reading rrgraph if file is already loaded. - */ - std::string read_rr_graph_filename; + /// @brief Name of rrgraph file read (if any). + /// Used to determine if the specified rr-graph file is already loaded, + /// so we can avoid redundant reading of the rr-graph + std::string loaded_rr_graph_filename; + + /// @brief Name of rrgraph edge override file read (if any). + /// Used to determine if the specified rr-graph edge override file is already loaded, + /// so we can avoid redundant reading of the rr-graph + std::string loaded_rr_edge_override_filename; /******************************************************************* * Place Related @@ -344,15 +379,62 @@ struct PlacementContext : public Context { BlkLocRegistry blk_loc_registry_; public: + /** + * @brief Initialize the variables stored within the placement context. This + * must be called before performing placement, but must be called + * after the clusters are loaded. + * + * @param placer_opts + * The options passed into the placer. + * @param directs + * A list of the direct connections in the architecture. + */ + void init_placement_context(const t_placer_opts& placer_opts, + const std::vector& directs); - const vtr::vector_map& block_locs() const { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.block_locs(); } - vtr::vector_map& mutable_block_locs() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.mutable_block_locs(); } - const GridBlock& grid_blocks() const { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.grid_blocks(); } - GridBlock& mutable_grid_blocks() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.mutable_grid_blocks(); } - vtr::vector_map& mutable_physical_pins() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.mutable_physical_pins(); } - const vtr::vector_map& physical_pins() const { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.physical_pins(); } - BlkLocRegistry& mutable_blk_loc_registry() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_; } - const BlkLocRegistry& blk_loc_registry() const { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_; } + /** + * @brief Clean variables from the placement context which are not used + * outside of placement. + * + * There are some variables that are stored in the placement context and are + * only used in placement; while there are some that are used outside of + * placement. This method frees up the memory of the variables used only + * within placement. + */ + void clean_placement_context_post_place(); + + const vtr::vector_map& block_locs() const { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_.block_locs(); + } + vtr::vector_map& mutable_block_locs() { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_.mutable_block_locs(); + } + const GridBlock& grid_blocks() const { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_.grid_blocks(); + } + GridBlock& mutable_grid_blocks() { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_.mutable_grid_blocks(); + } + vtr::vector_map& mutable_physical_pins() { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_.mutable_physical_pins(); + } + const vtr::vector_map& physical_pins() const { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_.physical_pins(); + } + BlkLocRegistry& mutable_blk_loc_registry() { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_; + } + const BlkLocRegistry& blk_loc_registry() const { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_; + } /** * @brief Makes blk_loc_registry_ inaccessible through the getter methods. @@ -361,7 +443,10 @@ struct PlacementContext : public Context { * guarantee that the placement stage code does not access block location variables * stored in the global state. */ - void lock_loc_vars() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); loc_vars_are_accessible_ = false; } + void lock_loc_vars() { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + loc_vars_are_accessible_ = false; + } /** * @brief Makes blk_loc_registry_ accessible through the getter methods. @@ -369,13 +454,20 @@ struct PlacementContext : public Context { * This method should be called at the end of the placement stage to * make the block location information accessible for subsequent stages. */ - void unlock_loc_vars() { VTR_ASSERT_SAFE(!loc_vars_are_accessible_); loc_vars_are_accessible_ = true; } - - ///@brief Stores ClusterBlockId of all movable clustered blocks (blocks that are not locked down to a single location) - std::vector movable_blocks; + void unlock_loc_vars() { + VTR_ASSERT_SAFE(!loc_vars_are_accessible_); + loc_vars_are_accessible_ = true; + } - ///@brief Stores ClusterBlockId of all movable clustered of each block type - std::vector> movable_blocks_per_type; + /** + * @brief Collection of all the placement macros in the netlist. A placement + * macro is a set of clustered blocks that must be placed in a way + * that is compliant with relative locations specified by the macro. + * Macros are used during placement and are not modified after they + * are created. + * This is created at the start of placement. + */ + std::unique_ptr place_macros; /** * @brief Compressed grid space for each block type @@ -472,7 +564,7 @@ struct RoutingContext : public Context { * @brief User specified routing constraints */ UserRouteConstraints constraints; - + /** Is flat routing enabled? */ bool is_flat; }; @@ -484,6 +576,42 @@ struct RoutingContext : public Context { * to certain regions on the chip. */ struct FloorplanningContext : public Context { + /** + * @brief Update the floorplanning constraints after a clustering has been + * created. + * + * After clustering, the constraints of contained atoms are used to compute + * the constraints of clusters. + * + * This must be called before using the cluster_constraints. + */ + void update_floorplanning_context_post_pack(); + + /** + * @brief Update the floorplanning constraints before placement. + * + * Placement groups clusters together into macros which must be placed + * together. This imposes more constraints onto the clusters which needs to + * be updated. + * + * This must be called before placement, but after the placement context is + * initialized. + * + * @param place_macros + * Macros of clusters which must be placed together. Initialized in the + * placement context. + */ + void update_floorplanning_context_pre_place(const PlaceMacros& place_macros); + + /** + * @brief Clean the floorplanning constraints after placement. + * + * After placement, many of the variables in this class will no longer be + * used (since the placement is no longer changing, the constraints are no + * longer needed). This method will free up the memory used by this class. + */ + void clean_floorplanning_context_post_place(); + /** * @brief Stores groups of constrained atoms, areas where the atoms are constrained to * @@ -524,8 +652,6 @@ struct FloorplanningContext : public Context { * */ std::vector> compressed_cluster_constraints; - - std::vector overfull_partition_regions; }; /** @@ -553,7 +679,7 @@ struct NocContext : public Context { * * Contains all of the traffic flows that describe which pairs of logical routers are * communicating and also some metrics and constraints on the data transfer between the two routers. - * + * * * This is created from a user supplied .flows file. */ diff --git a/vpr/src/base/vpr_signal_handler.cpp b/vpr/src/base/vpr_signal_handler.cpp index 66cb879ff79..9be73206bd1 100644 --- a/vpr/src/base/vpr_signal_handler.cpp +++ b/vpr/src/base/vpr_signal_handler.cpp @@ -21,7 +21,7 @@ #include #ifdef VPR_USE_SIGACTION -# include +#include #endif void vpr_signal_handler(int signal); diff --git a/vpr/src/base/vpr_tatum_error.cpp b/vpr/src/base/vpr_tatum_error.cpp index ea106def804..ed75818444c 100644 --- a/vpr/src/base/vpr_tatum_error.cpp +++ b/vpr/src/base/vpr_tatum_error.cpp @@ -16,19 +16,19 @@ std::string format_tatum_error(const tatum::Error& error) { } if (error.node) { - AtomPinId pin = atom_ctx.lookup.tnode_atom_pin(error.node); + AtomPinId pin = atom_ctx.lookup().tnode_atom_pin(error.node); if (pin) { - msg += "Netlist Pin: '" + atom_ctx.nlist.pin_name(pin) + "', "; + msg += "Netlist Pin: '" + atom_ctx.netlist().pin_name(pin) + "', "; - const t_pb_graph_pin* gpin = atom_ctx.lookup.atom_pin_pb_graph_pin(pin); + const t_pb_graph_pin* gpin = atom_ctx.lookup().atom_pin_pb_graph_pin(pin); if (gpin) { msg += "Graph node pin: '" + gpin->to_string() + "', "; } - AtomBlockId blk = atom_ctx.nlist.pin_block(pin); + AtomBlockId blk = atom_ctx.netlist().pin_block(pin); if (blk) { - msg += "Netlist Block: '" + atom_ctx.nlist.block_name(blk) + "', "; - ClusterBlockId clb_idx = atom_ctx.lookup.atom_clb(blk); + msg += "Netlist Block: '" + atom_ctx.netlist().block_name(blk) + "', "; + ClusterBlockId clb_idx = atom_ctx.lookup().atom_clb(blk); if (clb_idx) { const t_pb* pb = cluster_ctx.clb_nlist.block_pb(clb_idx); if (pb) { @@ -49,18 +49,18 @@ std::string format_tatum_error(const tatum::Error& error) { tatum::NodeId src_node = timing_ctx.graph->edge_src_node(error.edge); tatum::NodeId sink_node = timing_ctx.graph->edge_sink_node(error.edge); - AtomPinId src_pin = atom_ctx.lookup.tnode_atom_pin(src_node); - AtomPinId sink_pin = atom_ctx.lookup.tnode_atom_pin(sink_node); + AtomPinId src_pin = atom_ctx.lookup().tnode_atom_pin(src_node); + AtomPinId sink_pin = atom_ctx.lookup().tnode_atom_pin(sink_node); if (src_pin && sink_pin) { msg += "Between netlist pins "; - msg += "'" + atom_ctx.nlist.pin_name(src_pin) + "' -> '" + atom_ctx.nlist.pin_name(sink_pin) + "'"; + msg += "'" + atom_ctx.netlist().pin_name(src_pin) + "' -> '" + atom_ctx.netlist().pin_name(sink_pin) + "'"; - AtomNetId src_net = atom_ctx.nlist.pin_net(src_pin); - AtomNetId sink_net = atom_ctx.nlist.pin_net(sink_pin); + AtomNetId src_net = atom_ctx.netlist().pin_net(src_pin); + AtomNetId sink_net = atom_ctx.netlist().pin_net(sink_pin); if (src_net && src_net == sink_net) { - msg += " via net '" + atom_ctx.nlist.net_name(src_net) + "'"; + msg += " via net '" + atom_ctx.netlist().net_name(src_net) + "'"; } msg += ", "; diff --git a/vpr/src/base/vpr_types.cpp b/vpr/src/base/vpr_types.cpp index f1401bd5f51..22a644a2d07 100644 --- a/vpr/src/base/vpr_types.cpp +++ b/vpr/src/base/vpr_types.cpp @@ -1,4 +1,5 @@ #include +#include #include "vpr_types.h" #include "globals.h" @@ -451,4 +452,3 @@ BitIndex t_pb::atom_pin_bit_index(const t_pb_graph_pin* gpin) const { void t_pb::set_atom_pin_bit_index(const t_pb_graph_pin* gpin, BitIndex atom_pin_bit_idx) { pin_rotations_[gpin] = atom_pin_bit_idx; } - diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 3a19b6fb06c..44d12cedf36 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -29,6 +29,7 @@ #include #include #include +#include "ap_flow_enums.h" #include "arch_types.h" #include "atom_netlist_fwd.h" #include "clustered_netlist_fwd.h" @@ -92,15 +93,6 @@ constexpr bool VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR = true; constexpr bool VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR = false; #endif -#define MAX_SHORT 32767 - -/* Values large enough to be way out of range for any data, but small enough - * to allow a small number to be added to them without going out of range. */ -#define HUGE_POSITIVE_FLOAT 1.e30 - -/* Used to avoid floating-point errors when comparing values close to 0 */ -#define EPSILON 1.e-15 - /* * Files */ @@ -113,7 +105,7 @@ constexpr bool VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR = false; #define NOT_VALID (-10000) /* Marks gains that aren't valid */ /* Ensure no gain can ever be this negative! */ #ifndef UNDEFINED -# define UNDEFINED (-1) +#define UNDEFINED (-1) #endif ///@brief Router lookahead types. @@ -251,10 +243,8 @@ class t_pack_high_fanout_thresholds { /* these are defined later, but need to declare here because it is used */ class t_rr_node; -class t_pack_molecule; struct t_pb_stats; struct t_pb_route; -struct t_chain_info; typedef vtr::flat_map2 t_pb_routes; @@ -366,74 +356,6 @@ struct t_pb_route { const t_pb_graph_pin* pb_graph_pin = nullptr; ///block_id - * chain_info : if this is a molecule representing a chained pack pattern, this data structure will - * hold the data shared between all molecules forming a chain together. - * num_blocks : maximum number of atom blocks that can fit in this molecule - * root : index of the pack_pattern->root_block in the atom_blocks_ids. root_block_id = atom_block_ids[root] - * base_gain : intrinsic "goodness" score for molecule independent of rest of netlist - * next : next molecule in the linked list - */ -class t_pack_molecule { - public: - /* general molecule info */ - float base_gain; - enum e_pack_pattern_molecule_type type; - - /* large molecules info */ - t_pack_patterns* pack_pattern; - int root; - int num_blocks; - std::vector atom_block_ids; - std::shared_ptr chain_info; - - t_pack_molecule* next; - // a molecule is chain is it is a forced pack and its pack pattern is chain - bool is_chain() const { return type == MOLECULE_FORCED_PACK && pack_pattern->is_chain; } -}; - -/** - * @brief Holds information to be shared between molecules that represent the same chained pack pattern. - * - * For example, molecules that are representing a long carry chain that spans multiple logic blocks. - * - * Data members: - * is_long_chain : is this a long that is divided on multiple clusters (divided on multiple molecules). - * chain_id : is used to access the chain_root_pins vector in the t_pack_patterns of the molecule. To get - * the starting point of this chain in the cluster. This id is useful when we have multiple - * (architectural) carry chains in a logic block, for example. It lets us see which of the chains - * is being used for this long (netlist) chain, so we continue to use that chain in the packing - * of other molecules of this long chain. - * first_packed_molecule : first molecule to be packed out of the molecules forming this chain. This is the molecule - * setting the value of the chain_id. - */ -struct t_chain_info { - bool is_long_chain = false; - int chain_id = -1; - t_pack_molecule* first_packed_molecule = nullptr; -}; - /****************************************************************** * Timing data types *******************************************************************/ @@ -755,6 +677,7 @@ struct t_file_name_opts { std::string read_vpr_constraints_file; std::string write_vpr_constraints_file; std::string write_constraints_file; + std::string read_flat_place_file; std::string write_flat_place_file; std::string write_block_usage; bool verify_file_digests; @@ -794,9 +717,7 @@ struct t_packer_opts { enum e_cluster_seed cluster_seed_type; float alpha; float beta; - float inter_cluster_net_delay; float target_device_utilization; - bool auto_compute_inter_cluster_net_delay; e_unrelated_clustering allow_unrelated_clustering; bool connection_driven; int pack_verbosity; @@ -813,7 +734,7 @@ struct t_packer_opts { bool use_attraction_groups; int pack_num_moves; std::string pack_move_type; - bool load_flat_placement; + bool load_flat_placement = false; }; /** @@ -991,11 +912,6 @@ enum class e_move_type; * @param timing_tradeoff * When in CRITICALITY_TIMING_PLACE mode, what is the * tradeoff between timing and wiring costs. - * @param place_cost_exp - * Wiring cost is divided by the average channel width over - * a net's bounding box taken to this exponent. - * Only impacts devices with different channel widths in - * different directions or regions. (Default: 1) * @param place_chan_width * The channel width assumed if only one placement is performed. * @param pad_loc_type @@ -1043,7 +959,7 @@ enum class e_move_type; struct t_placer_opts { t_place_algorithm place_algorithm; t_place_algorithm place_quench_algorithm; - t_annealing_sched anneal_sched; /// switchblocks; /* Xifan Tang: subtype of switch blocks. @@ -1429,151 +1345,40 @@ struct t_det_routing_arch { bool concat_pass_wire; short global_route_switch; + + /// Index of a zero delay switch (used to connect things that should have no delay). short delayless_switch; + + /// Keeps track of the type of architecture switch that connects wires to ipins int wire_to_arch_ipin_switch; + + /// Keeps track of the type of architecture switch that connects + /// wires from another die to ipins in different die int wire_to_arch_ipin_switch_between_dice = -1; + + /// keeps track of the type of RR graph switch + /// that connects wires to ipins in the RR graph int wire_to_rr_ipin_switch; + + /// keeps track of the type of RR graph switch that connects wires + /// from another die to ipins in different die in the RR graph int wire_to_rr_ipin_switch_between_dice = -1; + + /// Resistance (in Ohms) of a minimum width nmos transistor. + /// Used only in the FPGA area model. float R_minW_nmos; + + /// Resistance (in Ohms) of a minimum width pmos transistor. float R_minW_pmos; + /// File to read the RR graph from (overrides architecture) std::string read_rr_graph_filename; + /// File to write the RR graph to after generation std::string write_rr_graph_filename; + /// File to read the RR graph edge attribute overrides. + std::string read_rr_edge_override_filename; }; -/** - * @brief Lists detailed information about segmentation. [0 .. W-1]. - * - * @param length length of segment. - * @param start index at which a segment starts in channel 0. - * @param longline true if this segment spans the entire channel. - * @param sb [0..length]: true for every channel intersection, relative to the - * segment start, at which there is a switch box. - * @param cb [0..length-1]: true for every logic block along the segment at - * which there is a connection box. - * @param arch_wire_switch Index of the switch type that connects other wires - * *to* this segment. Note that this index is in relation - * to the switches from the architecture file, not the - * expanded list of switches that is built at the end of - * build_rr_graph. - * @param arch_opin_switch Index of the switch type that connects output pins - * (OPINs) *to* this segment. Note that this index is in - * relation to the switches from the architecture file, - * not the expanded list of switches that is is built - * at the end of build_rr_graph - * @param arch_opin_between_dice_switch Index of the switch type that connects output - * pins (OPINs) *to* this segment from *another dice*. - * Note that this index is in relation to the switches from - * the architecture file, not the expanded list of switches that is built - * at the end of build_rr_graph - * @param Cmetal Capacitance of a routing track, per unit logic block length. - * @param Rmetal Resistance of a routing track, per unit logic block length. - * @param direction The direction of a routing track. - * @param index index of the segment type used for this track. - * Note that this index will store the index of the segment - * relative to its **parallel** segment types, not all segments - * as stored in device_ctx. Look in rr_graph.cpp: build_rr_graph - * for details but here is an example: say our segment_inf_vec in - * device_ctx is as follows: [seg_a_x, seg_b_x, seg_a_y, seg_b_y] - * when building the rr_graph, static segment_inf_vectors will be - * created for each direction, thus you will have the following - * 2 vectors: X_vec =[seg_a_x,seg_b_x] and Y_vec = [seg_a_y,seg_b_y]. - * As a result, e.g. seg_b_y::index == 1 (index in Y_vec) - * and != 3 (index in device_ctx segment_inf_vec). - * @param abs_index index is relative to the segment_inf vec as stored in device_ctx. - * Note that the above vector is **unifies** both x-parallel and - * y-parallel segments and is loaded up originally in read_xml_arch_file.cpp - * - * @param type_name_ptr pointer to name of the segment type this track belongs - * to. points to the appropriate name in s_segment_inf - */ -struct t_seg_details { - int length = 0; - int start = 0; - bool longline = false; - std::unique_ptr sb; - std::unique_ptr cb; - short arch_wire_switch = 0; - short arch_opin_switch = 0; - short arch_opin_between_dice_switch = 0; - float Rmetal = 0; - float Cmetal = 0; - bool twisted = false; - enum Direction direction = Direction::NONE; - int group_start = 0; - int group_size = 0; - int seg_start = 0; - int seg_end = 0; - int index = 0; - int abs_index = 0; - float Cmetal_per_m = 0; ///length) - , seg_detail_(init_seg_details) {} - - public: - int length() const { return length_; } - int seg_start() const { return seg_start_; } - int seg_end() const { return seg_end_; } - - int start() const { return seg_detail_->start; } - bool longline() const { return seg_detail_->longline; } - - int group_start() const { return seg_detail_->group_start; } - int group_size() const { return seg_detail_->group_size; } - - bool cb(int pos) const { return seg_detail_->cb[pos]; } - bool sb(int pos) const { return seg_detail_->sb[pos]; } - - float Rmetal() const { return seg_detail_->Rmetal; } - float Cmetal() const { return seg_detail_->Cmetal; } - float Cmetal_per_m() const { return seg_detail_->Cmetal_per_m; } - - short arch_wire_switch() const { return seg_detail_->arch_wire_switch; } - short arch_opin_switch() const { return seg_detail_->arch_opin_switch; } - short arch_opin_between_dice_switch() const { return seg_detail_->arch_opin_between_dice_switch; } - - Direction direction() const { return seg_detail_->direction; } - - int index() const { return seg_detail_->index; } - int abs_index() const { return seg_detail_->abs_index; } - - const vtr::string_view type_name() const { - return vtr::string_view( - seg_detail_->type_name.data(), - seg_detail_->type_name.size()); - } - - public: //Modifiers - void set_length(int new_len) { length_ = new_len; } - void set_seg_start(int new_start) { seg_start_ = new_start; } - void set_seg_end(int new_end) { seg_end_ = new_end; } - - private: - //The only unique information about a channel segment is it's start/end - //and length. All other information is shared across segment types, - //so we use a flyweight to the t_seg_details which defines that info. - // - //To preserve the illusion of uniqueness we wrap all t_seg_details members - //so it appears transparent -- client code of this class doesn't need to - //know about t_seg_details. - int length_ = -1; - int seg_start_ = -1; - int seg_end_ = -1; - const t_seg_details* seg_detail_ = nullptr; -}; - -/* Defines a 3-D array of t_chan_seg_details data structures (one per-each horizontal and vertical channel) - * once allocated in rr_graph2.cpp, is can be accessed like: [0..grid.width()][0..grid.height()][0..num_tracks-1] - */ -typedef vtr::NdMatrix t_chan_details; - constexpr bool is_pin(e_rr_type type) { return (type == IPIN || type == OPIN); } constexpr bool is_chan(e_rr_type type) { return (type == CHANX || type == CHANY); } constexpr bool is_src_sink(e_rr_type type) { return (type == SOURCE || type == SINK); } @@ -1659,7 +1464,7 @@ typedef t_routing_status t_atom_net_routing_status; /** Edge between two RRNodes */ struct t_node_edge { - t_node_edge(RRNodeId fnode, RRNodeId tnode) + t_node_edge(RRNodeId fnode, RRNodeId tnode) noexcept : from_node(fnode) , to_node(tnode) {} @@ -1672,10 +1477,18 @@ struct t_node_edge { } }; -///@brief Non-configurably connected nodes and edges in the RR graph +/** + * @brief Groups of non-configurably connected nodes and edges in the RR graph. + * @note Each group is represented by a node set and an edge set, stored at the same index. + * + * For example, in an architecture with L-shaped wires formed by an x- and y-directed segment + * connected by an electrical short, each L-shaped wire corresponds to a new group. The group's + * index provides access to its node set (containing two RRNodeIds) and edge set (containing two + * directed edge in opposite directions). + */ struct t_non_configurable_rr_sets { - std::set> node_sets; - std::set> edge_sets; + std::vector> node_sets; + std::vector> edge_sets; }; ///@brief Power estimation options @@ -1687,11 +1500,11 @@ struct t_power_opts { * @param max= Maximum channel width between x_max and y_max. * @param x_min= Minimum channel width of horizontal channels. Initialized when init_chan() is invoked in rr_graph2.cpp * @param y_min= Same as above but for vertical channels. - * @param x_max= Maximum channel width of horiozntal channels. Initialized when init_chan() is invoked in rr_graph2.cpp + * @param x_max= Maximum channel width of horizontal channels. Initialized when init_chan() is invoked in rr_graph2.cpp * @param y_max= Same as above but for vertical channels. * @param x_list= Stores the channel width of all horizontal channels and thus goes from [0..grid.height()] * (imagine a 2D Cartesian grid with horizontal lines starting at every grid point on a line parallel to the y-axis) - * @param y_list= Stores the channel width of all verical channels and thus goes from [0..grid.width()] + * @param y_list= Stores the channel width of all vertical channels and thus goes from [0..grid.width()] * (imagine a 2D Cartesian grid with vertical lines starting at every grid point on a line parallel to the x-axis) */ diff --git a/vpr/src/draw/buttons.cpp b/vpr/src/draw/buttons.cpp index ae48bdbc7b9..db64d45c5de 100644 --- a/vpr/src/draw/buttons.cpp +++ b/vpr/src/draw/buttons.cpp @@ -10,16 +10,16 @@ * Last updated: Aug 2019 */ -# include "draw_global.h" -# include "draw.h" -# include "draw_toggle_functions.h" -# include "buttons.h" -# include "intra_logic_block.h" -# include "clustered_netlist.h" +#include "draw_global.h" +#include "draw.h" +#include "draw_toggle_functions.h" +#include "buttons.h" +#include "intra_logic_block.h" +#include "clustered_netlist.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" //location of spin buttons, combo boxes, and labels on grid gint box_width = 1; diff --git a/vpr/src/draw/buttons.h b/vpr/src/draw/buttons.h index 853ad4cb50b..ce7d2910130 100644 --- a/vpr/src/draw/buttons.h +++ b/vpr/src/draw/buttons.h @@ -3,11 +3,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" void delete_button(const char* button_name); GtkWidget* find_button(const char* button_name); diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index 46bdd750ca9..5dc0c09523e 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -55,20 +55,20 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif - -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" -# include "draw_rr.h" +#if defined(X11) && !defined(__MINGW32__) +#include +#endif + +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" +#include "draw_rr.h" /****************************** Define Macros *******************************/ -# define DEFAULT_RR_NODE_COLOR ezgl::BLACK -# define OLD_BLK_LOC_COLOR blk_GOLD -# define NEW_BLK_LOC_COLOR blk_GREEN +#define DEFAULT_RR_NODE_COLOR ezgl::BLACK +#define OLD_BLK_LOC_COLOR blk_GOLD +#define NEW_BLK_LOC_COLOR blk_GREEN //#define TIME_DRAWSCREEN /* Enable if want to track runtime for drawscreen() */ void act_on_key_press(ezgl::application* /*app*/, GdkEventKey* /*event*/, char* key_name); @@ -569,7 +569,7 @@ void init_draw_coords(float clb_width, const BlkLocRegistry& blk_loc_registry) { draw_state->draw_rr_node[inode].node_highlighted = false; } } - draw_coords->tile_width = clb_width; + draw_coords->set_tile_width(clb_width); draw_coords->pin_size = 0.3; for (const auto& type : device_ctx.physical_tile_types) { auto num_pins = type.num_pins; @@ -795,9 +795,9 @@ void act_on_mouse_move(ezgl::application* app, GdkEventButton* /* event */, doub ezgl::point2d atom_pin_draw_coord(AtomPinId pin) { auto& atom_ctx = g_vpr_ctx.atom(); - AtomBlockId blk = atom_ctx.nlist.pin_block(pin); - ClusterBlockId clb_index = atom_ctx.lookup.atom_clb(blk); - const t_pb_graph_node* pg_gnode = atom_ctx.lookup.atom_pb_graph_node(blk); + AtomBlockId blk = atom_ctx.netlist().pin_block(pin); + ClusterBlockId clb_index = atom_ctx.lookup().atom_clb(blk); + const t_pb_graph_node* pg_gnode = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(blk); t_draw_coords* draw_coords = get_draw_coords_vars(); ezgl::rectangle pb_bbox = draw_coords->get_absolute_pb_bbox(clb_index, @@ -1326,7 +1326,7 @@ static void run_graphics_commands(const std::string& commands) { ezgl::point2d tnode_draw_coord(tatum::NodeId node) { auto& atom_ctx = g_vpr_ctx.atom(); - AtomPinId pin = atom_ctx.lookup.tnode_atom_pin(node); + AtomPinId pin = atom_ctx.lookup().tnode_atom_pin(node); return atom_pin_draw_coord(pin); } @@ -1422,7 +1422,7 @@ size_t get_max_fanout() { max_fanout = std::max(max_fanout, clb_nlist.net_sinks(net_id).size()); auto& atom_ctx = g_vpr_ctx.atom(); - auto& atom_nlist = atom_ctx.nlist; + auto& atom_nlist = atom_ctx.netlist(); size_t max_fanout2 = 0; for (AtomNetId net_id : atom_nlist.nets()) max_fanout2 = std::max(max_fanout2, atom_nlist.net_sinks(net_id).size()); diff --git a/vpr/src/draw/draw.h b/vpr/src/draw/draw.h index 355b2891931..adfb6fd47be 100644 --- a/vpr/src/draw/draw.h +++ b/vpr/src/draw/draw.h @@ -26,16 +26,16 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" - -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" -# include "search_bar.h" -# include "draw_debug.h" -# include "manual_moves.h" -# include "vtr_ndoffsetmatrix.h" +#include "draw_global.h" + +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" +#include "search_bar.h" +#include "draw_debug.h" +#include "manual_moves.h" +#include "vtr_ndoffsetmatrix.h" extern ezgl::application::settings settings; extern ezgl::application application; diff --git a/vpr/src/draw/draw_basic.cpp b/vpr/src/draw/draw_basic.cpp index 482fbf178e3..2981dd308aa 100644 --- a/vpr/src/draw/draw_basic.cpp +++ b/vpr/src/draw/draw_basic.cpp @@ -7,9 +7,9 @@ #include #include +#include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_ndoffsetmatrix.h" -#include "vtr_log.h" #include "vtr_color_map.h" #include "vpr_utils.h" @@ -22,7 +22,6 @@ #include "draw_rr_edges.h" #include "draw_basic.h" #include "draw_triangle.h" -#include "read_xml_arch_file.h" #include "draw_global.h" #include "move_utils.h" #include "route_export.h" @@ -32,19 +31,19 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" /****************************** Define Macros *******************************/ -# define DEFAULT_RR_NODE_COLOR ezgl::BLACK -# define OLD_BLK_LOC_COLOR blk_GOLD -# define NEW_BLK_LOC_COLOR blk_GREEN +#define DEFAULT_RR_NODE_COLOR ezgl::BLACK +#define OLD_BLK_LOC_COLOR blk_GOLD +#define NEW_BLK_LOC_COLOR blk_GREEN constexpr float EMPTY_BLOCK_LIGHTEN_FACTOR = 0.20; @@ -239,7 +238,7 @@ void drawnets(ezgl::renderer* g) { ClusterBlockId b2 = cluster_ctx.clb_nlist.pin_block(pin_id); //the layer of the pin block (net sinks) - sink_block_layer_num =block_locs[b2].loc.layer; + sink_block_layer_num = block_locs[b2].loc.layer; t_draw_layer_display element_visibility = get_element_visibility_and_transparency(driver_block_layer_num, sink_block_layer_num); @@ -384,7 +383,7 @@ void draw_routing_costs(ezgl::renderer* g) { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.routing(); g->set_line_width(0); - + VTR_ASSERT(!route_ctx.rr_node_route_inf.empty()); float min_cost = std::numeric_limits::infinity(); @@ -777,7 +776,9 @@ void draw_placement_macros(ezgl::renderer* g) { t_draw_coords* draw_coords = get_draw_coords_vars(); const auto& block_locs = draw_state->get_graphics_blk_loc_registry_ref().block_locs(); - const auto& place_macros = draw_state->get_graphics_blk_loc_registry_ref().place_macros(); + + VTR_ASSERT(g_vpr_ctx.placement().place_macros); + const PlaceMacros& place_macros = *g_vpr_ctx.placement().place_macros; for (const t_pl_macro& pl_macro : place_macros.macros()) { @@ -1086,7 +1087,7 @@ void draw_crit_path(ezgl::renderer* g) { /** * @brief Draw critical path elements. - * + * * This function draws critical path elements based on the provided timing paths * and indexes map. It is primarily used in server mode, where items are drawn upon request. */ @@ -1094,19 +1095,19 @@ void draw_crit_path_elements(const std::vector& paths, const t_draw_state* draw_state = get_draw_state_vars(); const ezgl::color contour_color{0, 0, 0, 40}; - auto draw_flyline_timing_edge_helper_fn = [](ezgl::renderer* renderer, const ezgl::color& color, ezgl::line_dash line_style, int line_width, float delay, - const tatum::NodeId& prev_node, const tatum::NodeId& node, bool skip_draw_delays=false) { + auto draw_flyline_timing_edge_helper_fn = [](ezgl::renderer* renderer, const ezgl::color& color, ezgl::line_dash line_style, int line_width, float delay, + const tatum::NodeId& prev_node, const tatum::NodeId& node, bool skip_draw_delays = false) { renderer->set_color(color); renderer->set_line_dash(line_style); renderer->set_line_width(line_width); draw_flyline_timing_edge(tnode_draw_coord(prev_node), - tnode_draw_coord(node), delay, renderer, skip_draw_delays); + tnode_draw_coord(node), delay, renderer, skip_draw_delays); renderer->set_line_dash(ezgl::line_dash::none); - renderer->set_line_width(0); + renderer->set_line_width(0); }; - for (const auto& [path_index, element_indexes]: indexes) { + for (const auto& [path_index, element_indexes] : indexes) { if (path_index < paths.size()) { const tatum::TimingPath& path = paths[path_index]; @@ -1116,7 +1117,7 @@ void draw_crit_path_elements(const std::vector& paths, const int element_counter = 0; for (const tatum::TimingPathElem& elem : path.data_arrival_path().elements()) { bool draw_current_element = element_indexes.empty() || element_indexes.find(element_counter) != element_indexes.end(); - + // draw element tatum::NodeId node = elem.node(); float arr_time = elem.tag().time(); @@ -1131,9 +1132,9 @@ void draw_crit_path_elements(const std::vector& paths, const float delay = arr_time - prev_arr_time; if ((draw_state->show_crit_path == DRAW_CRIT_PATH_FLYLINES) || (draw_state->show_crit_path == DRAW_CRIT_PATH_FLYLINES_DELAYS)) { if (draw_current_element) { - draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::none, /*line_width*/4, delay, prev_node, node); + draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::none, /*line_width*/ 4, delay, prev_node, node); } else if (draw_crit_path_contour) { - draw_flyline_timing_edge_helper_fn(g, contour_color, ezgl::line_dash::none, /*line_width*/1, delay, prev_node, node, /*skip_draw_delays*/true); + draw_flyline_timing_edge_helper_fn(g, contour_color, ezgl::line_dash::none, /*line_width*/ 1, delay, prev_node, node, /*skip_draw_delays*/ true); } } else { VTR_ASSERT(draw_state->show_crit_path != DRAW_NO_CRIT_PATH); @@ -1142,13 +1143,13 @@ void draw_crit_path_elements(const std::vector& paths, const //Draw the routed version of the timing edge draw_routed_timing_edge_connection(prev_node, node, color, g); - draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::asymmetric_5_3, /*line_width*/3, delay, prev_node, node); + draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::asymmetric_5_3, /*line_width*/ 3, delay, prev_node, node); } else if (draw_crit_path_contour) { - draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::asymmetric_5_3, /*line_width*/3, delay, prev_node, node, /*skip_draw_delays*/true); + draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::asymmetric_5_3, /*line_width*/ 3, delay, prev_node, node, /*skip_draw_delays*/ true); } } } - + prev_node = node; prev_arr_time = arr_time; // end draw element @@ -1164,9 +1165,9 @@ int get_timing_path_node_layer_num(tatum::NodeId node) { const auto& block_locs = draw_state->get_graphics_blk_loc_registry_ref().block_locs(); const auto& atom_ctx = g_vpr_ctx.atom(); - AtomPinId atom_pin = atom_ctx.lookup.tnode_atom_pin(node); - AtomBlockId atom_block = atom_ctx.nlist.pin_block(atom_pin); - ClusterBlockId clb_block = atom_ctx.lookup.atom_clb(atom_block); + AtomPinId atom_pin = atom_ctx.lookup().tnode_atom_pin(node); + AtomBlockId atom_block = atom_ctx.netlist().pin_block(atom_pin); + ClusterBlockId clb_block = atom_ctx.lookup().atom_clb(atom_block); return block_locs[clb_block].loc.layer; } @@ -1184,7 +1185,7 @@ bool is_flyline_valid_to_draw(int src_layer, int sink_layer) { } //Draws critical path shown as flylines. -void draw_flyline_timing_edge(ezgl::point2d start, ezgl::point2d end, float incr_delay, ezgl::renderer* g, bool skip_draw_delays/*=false*/) { +void draw_flyline_timing_edge(ezgl::point2d start, ezgl::point2d end, float incr_delay, ezgl::renderer* g, bool skip_draw_delays /*=false*/) { g->draw_line(start, end); draw_triangle_along_line(g, start, end, 0.95, 40 * DEFAULT_ARROW_SIZE); draw_triangle_along_line(g, start, end, 0.05, 40 * DEFAULT_ARROW_SIZE); @@ -1193,7 +1194,7 @@ void draw_flyline_timing_edge(ezgl::point2d start, ezgl::point2d end, float incr == DRAW_CRIT_PATH_FLYLINES_DELAYS || get_draw_state_vars()->show_crit_path == DRAW_CRIT_PATH_ROUTING_DELAYS) - && !skip_draw_delays; + && !skip_draw_delays; if (draw_delays) { //Determine the strict bounding box based on the lines start/end float min_x = std::min(start.x, end.x); @@ -1264,8 +1265,8 @@ void draw_routed_timing_edge_connection(tatum::NodeId src_tnode, auto& cluster_ctx = g_vpr_ctx.clustering(); auto& timing_ctx = g_vpr_ctx.timing(); - AtomPinId atom_src_pin = atom_ctx.lookup.tnode_atom_pin(src_tnode); - AtomPinId atom_sink_pin = atom_ctx.lookup.tnode_atom_pin(sink_tnode); + AtomPinId atom_src_pin = atom_ctx.lookup().tnode_atom_pin(src_tnode); + AtomPinId atom_sink_pin = atom_ctx.lookup().tnode_atom_pin(sink_tnode); std::vector points; points.push_back(atom_pin_draw_coord(atom_src_pin)); @@ -1283,16 +1284,16 @@ void draw_routed_timing_edge_connection(tatum::NodeId src_tnode, //TODO: most of this code is highly similar to code in PostClusterDelayCalculator, refactor // into a common method for walking the clustered netlist, this would also (potentially) // allow us to grab the component delays - AtomBlockId atom_src_block = atom_ctx.nlist.pin_block(atom_src_pin); - AtomBlockId atom_sink_block = atom_ctx.nlist.pin_block(atom_sink_pin); + AtomBlockId atom_src_block = atom_ctx.netlist().pin_block(atom_src_pin); + AtomBlockId atom_sink_block = atom_ctx.netlist().pin_block(atom_sink_pin); - ClusterBlockId clb_src_block = atom_ctx.lookup.atom_clb(atom_src_block); + ClusterBlockId clb_src_block = atom_ctx.lookup().atom_clb(atom_src_block); VTR_ASSERT(clb_src_block != ClusterBlockId::INVALID()); - ClusterBlockId clb_sink_block = atom_ctx.lookup.atom_clb( + ClusterBlockId clb_sink_block = atom_ctx.lookup().atom_clb( atom_sink_block); VTR_ASSERT(clb_sink_block != ClusterBlockId::INVALID()); - const t_pb_graph_pin* sink_gpin = atom_ctx.lookup.atom_pin_pb_graph_pin( + const t_pb_graph_pin* sink_gpin = atom_ctx.lookup().atom_pin_pb_graph_pin( atom_sink_pin); VTR_ASSERT(sink_gpin); diff --git a/vpr/src/draw/draw_basic.h b/vpr/src/draw/draw_basic.h index d939b43b8ec..65d42836948 100644 --- a/vpr/src/draw/draw_basic.h +++ b/vpr/src/draw/draw_basic.h @@ -34,11 +34,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" /* Draws the blocks placed on the proper clbs. Occupied blocks are darker colours * * while empty ones are lighter colours and have a dashed border. * @@ -130,7 +130,7 @@ void draw_crit_path_elements(const std::vector& paths, const bool is_flyline_valid_to_draw(int src_layer, int sink_layer); /* Draws critical path shown as flylines. Takes in start and end coordinates, time delay, & renderer.*/ -void draw_flyline_timing_edge(ezgl::point2d start, ezgl::point2d end, float incr_delay, ezgl::renderer* g, bool skip_draw_delays=false); +void draw_flyline_timing_edge(ezgl::point2d start, ezgl::point2d end, float incr_delay, ezgl::renderer* g, bool skip_draw_delays = false); /* Collects all the drawing locations associated with the timing edge between start and end. * Only traces interconnect edges in detail, and treats all others as flylines. diff --git a/vpr/src/draw/draw_color.h b/vpr/src/draw/draw_color.h index f9258dadbef..4dcc5e5dbe8 100644 --- a/vpr/src/draw/draw_color.h +++ b/vpr/src/draw/draw_color.h @@ -10,9 +10,9 @@ #ifndef NO_GRAPHICS -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" static constexpr ezgl::color blk_BISQUE(0xFF, 0xE4, 0xC4); static constexpr ezgl::color blk_LIGHTGREY(0xD3, 0xD3, 0xD3); diff --git a/vpr/src/draw/draw_debug.cpp b/vpr/src/draw/draw_debug.cpp index aeee39b1501..89566863c5e 100644 --- a/vpr/src/draw/draw_debug.cpp +++ b/vpr/src/draw/draw_debug.cpp @@ -46,16 +46,16 @@ void draw_debug_window() { GtkWidget* mainGrid = gtk_grid_new(); gtk_widget_set_margin_top(mainGrid, 30); gtk_widget_set_margin_bottom(mainGrid, 30); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(mainGrid, 30); -# else +#else gtk_widget_set_margin_left(mainGrid, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(mainGrid, 20); -# else +#else gtk_widget_set_margin_right(mainGrid, 20); -# endif +#endif //create all labels GtkWidget* placerOpts = gtk_label_new(NULL); @@ -71,39 +71,39 @@ void draw_debug_window() { gtk_widget_set_margin_top(bplist, 30); GtkWidget* movesLabel = gtk_label_new("Number of moves to proceed"); gtk_widget_set_halign(movesLabel, GTK_ALIGN_END); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(movesLabel, 8); -# else +#else gtk_widget_set_margin_right(movesLabel, 8); -# endif +#endif GtkWidget* tempsLabel = gtk_label_new("Temperatures to proceed:"); gtk_widget_set_halign(tempsLabel, GTK_ALIGN_END); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(tempsLabel, 8); -# else +#else gtk_widget_set_margin_right(tempsLabel, 8); -# endif +#endif GtkWidget* blockLabel = gtk_label_new("Stop at from_block"); gtk_widget_set_halign(blockLabel, GTK_ALIGN_END); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(blockLabel, 8); -# else +#else gtk_widget_set_margin_right(blockLabel, 8); -# endif +#endif GtkWidget* iterLabel = gtk_label_new("Stop at router iteration"); gtk_widget_set_halign(iterLabel, GTK_ALIGN_END); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(iterLabel, 8); -# else +#else gtk_widget_set_margin_right(iterLabel, 8); -# endif +#endif GtkWidget* netLabel = gtk_label_new("Stop at route_net_id"); gtk_widget_set_halign(netLabel, GTK_ALIGN_END); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(netLabel, 8); -# else +#else gtk_widget_set_margin_right(netLabel, 8); -# endif +#endif GtkWidget* star = gtk_label_new("*for handling multiple breakpoints at once using an expression can be more accurate"); gtk_widget_set_margin_top(star, 15); @@ -111,51 +111,51 @@ void draw_debug_window() { GtkWidget* setM = gtk_button_new_with_label("Set"); gtk_widget_set_halign(setM, GTK_ALIGN_START); gtk_widget_set_margin_bottom(setM, 10); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(setM, 10); -# else +#else gtk_widget_set_margin_left(setM, 10); -# endif +#endif GtkWidget* setT = gtk_button_new_with_label("Set"); gtk_widget_set_halign(setT, GTK_ALIGN_START); gtk_widget_set_margin_bottom(setT, 10); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(setT, 10); -# else +#else gtk_widget_set_margin_left(setT, 10); -# endif +#endif GtkWidget* setB = gtk_button_new_with_label("Set"); gtk_widget_set_halign(setB, GTK_ALIGN_START); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(setB, 10); -# else +#else gtk_widget_set_margin_left(setB, 10); -# endif +#endif GtkWidget* setI = gtk_button_new_with_label("Set"); gtk_widget_set_halign(setI, GTK_ALIGN_START); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(setI, 10); -# else +#else gtk_widget_set_margin_left(setI, 10); -# endif +#endif GtkWidget* setN = gtk_button_new_with_label("Set"); gtk_widget_set_halign(setN, GTK_ALIGN_START); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(setN, 10); -# else +#else gtk_widget_set_margin_left(setN, 10); -# endif +#endif GtkWidget* advanced = gtk_button_new_with_label("Advanced"); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(advanced, 60); -# else +#else gtk_widget_set_margin_left(advanced, 60); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(advanced, 10); -# else +#else gtk_widget_set_margin_right(advanced, 10); -# endif +#endif gtk_widget_set_margin_top(advanced, 20); //create all entries @@ -273,39 +273,39 @@ void advanced_button_callback() { gtk_widget_set_halign(expander, GTK_ALIGN_START); //set margins -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(instructions, 30); -# else +#else gtk_widget_set_margin_left(instructions, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(instructions, 30); -# else +#else gtk_widget_set_margin_right(instructions, 30); -# endif +#endif gtk_widget_set_margin_top(instructions, 30); gtk_widget_set_margin_bottom(instructions, 30); gtk_widget_set_margin_bottom(expression_here, 5); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(entry, 30); -# else +#else gtk_widget_set_margin_left(entry, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(set, 30); -# else +#else gtk_widget_set_margin_right(set, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(set, 40); -# else +#else gtk_widget_set_margin_left(set, 40); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(expander, 10); -# else +#else gtk_widget_set_margin_left(expander, 10); -# endif +#endif gtk_widget_set_margin_top(expander, 20); //grid settings @@ -350,11 +350,11 @@ void refresh_bpList() { if (draw_state->list_of_breakpoints[i].active) gtk_toggle_button_set_active((GtkToggleButton*)checkbox, TRUE); gtk_grid_attach((GtkGrid*)draw_debug_glob_vars.bpGrid, checkbox, 1, i, 1, 1); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(checkbox, 290 - draw_debug_glob_vars.bp_labels[i].size()); -# else +#else gtk_widget_set_margin_left(checkbox, 290 - draw_debug_glob_vars.bp_labels[i].size()); -# endif +#endif gtk_widget_set_halign(checkbox, GTK_ALIGN_END); gtk_widget_set_valign(checkbox, GTK_ALIGN_CENTER); @@ -368,11 +368,11 @@ void refresh_bpList() { gtk_grid_attach((GtkGrid*)draw_debug_glob_vars.bpGrid, deleteButton, 2, i, 1, 1); gtk_widget_set_halign(deleteButton, GTK_ALIGN_END); gtk_widget_set_valign(deleteButton, GTK_ALIGN_CENTER); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(deleteButton, 10); -# else +#else gtk_widget_set_margin_left(deleteButton, 10); -# endif +#endif gtk_widget_show_all(draw_debug_glob_vars.bpGrid); } @@ -393,11 +393,11 @@ void add_to_bpList(std::string bpDescription) { gtk_widget_set_name(checkbox, c.c_str()); gtk_toggle_button_set_active((GtkToggleButton*)checkbox, TRUE); gtk_grid_attach((GtkGrid*)draw_debug_glob_vars.bpGrid, checkbox, 1, draw_debug_glob_vars.bpList_row, 1, 1); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(checkbox, 290 - bpDescription.size()); -# else +#else gtk_widget_set_margin_left(checkbox, 290 - bpDescription.size()); -# endif +#endif gtk_widget_set_halign(checkbox, GTK_ALIGN_END); gtk_widget_set_valign(checkbox, GTK_ALIGN_CENTER); @@ -411,11 +411,11 @@ void add_to_bpList(std::string bpDescription) { gtk_grid_attach((GtkGrid*)draw_debug_glob_vars.bpGrid, deleteButton, 2, draw_debug_glob_vars.bpList_row, 1, 1); gtk_widget_set_halign(deleteButton, GTK_ALIGN_END); gtk_widget_set_valign(deleteButton, GTK_ALIGN_CENTER); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(deleteButton, 10); -# else +#else gtk_widget_set_margin_left(deleteButton, 10); -# endif +#endif gtk_widget_show_all(draw_debug_glob_vars.bpGrid); } @@ -539,16 +539,16 @@ void invalid_breakpoint_entry_window(std::string error) { //label settings GtkWidget* label = gtk_label_new(error.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(label, 30); -# else +#else gtk_widget_set_margin_left(label, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(label, 30); -# else +#else gtk_widget_set_margin_right(label, 30); -# endif +#endif gtk_widget_set_margin_top(label, 30); gtk_widget_set_margin_bottom(label, 30); gtk_grid_attach((GtkGrid*)grid, label, 0, 0, 1, 1); @@ -556,16 +556,16 @@ void invalid_breakpoint_entry_window(std::string error) { //button settings GtkWidget* button = gtk_button_new_with_label("OK"); gtk_widget_set_margin_bottom(button, 30); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(button, 30); -# else +#else gtk_widget_set_margin_right(button, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(button, 30); -# else +#else gtk_widget_set_margin_left(button, 30); -# endif +#endif gtk_grid_attach((GtkGrid*)grid, button, 0, 1, 1, 1); g_signal_connect(button, "clicked", G_CALLBACK(ok_close_window), window); @@ -586,47 +586,47 @@ void breakpoint_info_window(std::string bpDescription, BreakpointState draw_brea //label settings GtkWidget* label = gtk_label_new(bpDescription.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(label, 30); -# else +#else gtk_widget_set_margin_left(label, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(label, 30); -# else +#else gtk_widget_set_margin_right(label, 30); -# endif +#endif gtk_widget_set_margin_top(label, 30); gtk_widget_set_margin_bottom(label, 30); gtk_grid_attach((GtkGrid*)grid, label, 0, 0, 1, 1); GtkWidget* curr_info = gtk_label_new(NULL); gtk_label_set_markup((GtkLabel*)curr_info, "Current Information"); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(curr_info, 30); -# else +#else gtk_widget_set_margin_left(curr_info, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(curr_info, 30); -# else +#else gtk_widget_set_margin_right(curr_info, 30); -# endif +#endif gtk_widget_set_margin_bottom(curr_info, 15); gtk_grid_attach((GtkGrid*)grid, curr_info, 0, 1, 1, 1); //info grid GtkWidget* info_grid = gtk_grid_new(); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(info_grid, 30); -# else +#else gtk_widget_set_margin_left(info_grid, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(info_grid, 30); -# else +#else gtk_widget_set_margin_right(info_grid, 30); -# endif +#endif gtk_widget_set_margin_bottom(info_grid, 20); //images @@ -634,67 +634,67 @@ void breakpoint_info_window(std::string bpDescription, BreakpointState draw_brea GtkWidget* t = gtk_image_new_from_file("src/draw/t.png"); GtkWidget* r = gtk_image_new_from_file("src/draw/r.png"); GtkWidget* n = gtk_image_new_from_file("src/draw/n.png"); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(n, 18); -# else +#else gtk_widget_set_margin_left(n, 18); -# endif +#endif GtkWidget* i = gtk_image_new_from_file("src/draw/i.png"); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(i, 16); -# else +#else gtk_widget_set_margin_left(i, 16); -# endif +#endif GtkWidget* b = gtk_image_new_from_file("src/draw/b.png"); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(b, 18); -# else +#else gtk_widget_set_margin_left(b, 18); -# endif +#endif //info grid labels std::string move_num = "move_num: " + std::to_string(draw_breakpoint_state.move_num); GtkWidget* move_info = gtk_label_new(move_num.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(move_info, 5); -# else +#else gtk_widget_set_margin_left(move_info, 5); -# endif +#endif gtk_widget_set_halign(move_info, GTK_ALIGN_START); std::string temp_count = "temp_count: " + std::to_string(draw_breakpoint_state.temp_count); GtkWidget* temp_info = gtk_label_new(temp_count.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(temp_info, 5); -# else +#else gtk_widget_set_margin_left(temp_info, 5); -# endif +#endif gtk_widget_set_halign(temp_info, GTK_ALIGN_START); std::string in_blocks_affected = "in_blocks_affected: " + std::to_string(get_bp_state_globals()->get_glob_breakpoint_state()->block_affected); GtkWidget* ba_info = gtk_label_new(in_blocks_affected.c_str()); gtk_widget_set_halign(ba_info, GTK_ALIGN_START); std::string block_id = "from_block: " + std::to_string(draw_breakpoint_state.from_block); GtkWidget* block_info = gtk_label_new(block_id.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(block_info, 5); -# else +#else gtk_widget_set_margin_left(block_info, 5); -# endif +#endif gtk_widget_set_halign(block_info, GTK_ALIGN_START); std::string router_iter = "router_iter: " + std::to_string(draw_breakpoint_state.router_iter); GtkWidget* ri_info = gtk_label_new(router_iter.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(ri_info, 5); -# else +#else gtk_widget_set_margin_left(ri_info, 5); -# endif +#endif gtk_widget_set_halign(ri_info, GTK_ALIGN_START); std::string net_id = "rouet_net_id: " + std::to_string(draw_breakpoint_state.route_net_id); GtkWidget* net_info = gtk_label_new(net_id.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(net_info, 5); -# else +#else gtk_widget_set_margin_left(net_info, 5); -# endif +#endif gtk_widget_set_halign(net_info, GTK_ALIGN_START); //attach to grid diff --git a/vpr/src/draw/draw_debug.h b/vpr/src/draw/draw_debug.h index c88f146cdb8..f79d7740d7b 100644 --- a/vpr/src/draw/draw_debug.h +++ b/vpr/src/draw/draw_debug.h @@ -9,19 +9,19 @@ #ifndef NO_GRAPHICS -# include "breakpoint.h" -# include "draw_global.h" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "breakpoint.h" +#include "draw_global.h" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" -# include -# include -# include -# include -# include -# include -# include -# include +#include +#include +#include +#include +#include +#include +#include +#include /** debugger functions **/ void draw_debug_window(); diff --git a/vpr/src/draw/draw_floorplanning.cpp b/vpr/src/draw/draw_floorplanning.cpp index 9e56cfda5ac..e22c6446f7a 100644 --- a/vpr/src/draw/draw_floorplanning.cpp +++ b/vpr/src/draw/draw_floorplanning.cpp @@ -18,13 +18,16 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif -static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* current_pb, - const t_pb* pb_to_draw, const ezgl::rectangle& parent_bbox, - const t_logical_block_type_ptr type, ezgl::color color, +static void draw_internal_pb(const ClusterBlockId clb_index, + t_pb* current_pb, + const t_pb* pb_to_draw, + const ezgl::rectangle& parent_bbox, + const t_logical_block_type_ptr type, + ezgl::color color, ezgl::renderer* g); const std::vector kelly_max_contrast_colors_no_black = { @@ -52,8 +55,8 @@ const std::vector kelly_max_contrast_colors_no_black = { ezgl::color(43, 61, 38) //olive green }; -# define DEFAULT_HIGHLIGHT_ALPHA 30 -# define CLICKED_HIGHLIGHT_ALPHA 100 +#define DEFAULT_HIGHLIGHT_ALPHA 30 +#define CLICKED_HIGHLIGHT_ALPHA 100 //Keeps track of how translucent each partition should be drawn on screen. static std::vector highlight_alpha; @@ -149,10 +152,10 @@ void draw_constrained_atoms(ezgl::renderer* g) { auto atoms = constraints.get_part_atoms((PartitionId)partitionID); for (const AtomBlockId atom_id : atoms) { - if (atom_ctx.lookup.atom_pb(atom_id) != nullptr) { - const t_pb* pb = atom_ctx.lookup.atom_pb(atom_id); + if (atom_ctx.lookup().atom_pb_bimap().atom_pb(atom_id) != nullptr) { + const t_pb* pb = atom_ctx.lookup().atom_pb_bimap().atom_pb(atom_id); auto color = kelly_max_contrast_colors_no_black[partitionID % (kelly_max_contrast_colors_no_black.size())]; - ClusterBlockId clb_index = atom_ctx.lookup.atom_clb(atom_id); + ClusterBlockId clb_index = atom_ctx.lookup().atom_clb(atom_id); auto type = cluster_ctx.clb_nlist.block_type(clb_index); draw_internal_pb(clb_index, cluster_ctx.clb_nlist.block_pb(clb_index), pb, ezgl::rectangle({0, 0}, 0, 0), type, color, g); @@ -167,7 +170,8 @@ static void draw_internal_pb(const ClusterBlockId clb_index, const t_pb* pb_to_draw, const ezgl::rectangle& parent_bbox, const t_logical_block_type_ptr type, - ezgl::color color, ezgl::renderer* g) { + ezgl::color color, + ezgl::renderer* g) { t_draw_coords* draw_coords = get_draw_coords_vars(); t_draw_state* draw_state = get_draw_state_vars(); @@ -306,7 +310,7 @@ static GtkTreeModel* create_and_fill_model() { -1); for (AtomBlockId const_atom : atoms) { - std::string atom_name = (atom_ctx.lookup.atom_pb(const_atom))->name; + std::string atom_name = (atom_ctx.lookup().atom_pb_bimap().atom_pb(const_atom))->name; gtk_tree_store_append(store, &child_iter, &iter); gtk_tree_store_set(store, &child_iter, COL_NAME, atom_name.c_str(), diff --git a/vpr/src/draw/draw_floorplanning.h b/vpr/src/draw/draw_floorplanning.h index f45b398e4d8..feae6ec127c 100644 --- a/vpr/src/draw/draw_floorplanning.h +++ b/vpr/src/draw/draw_floorplanning.h @@ -6,11 +6,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" ///@brief Iterates through all partitions described in the constraints file and highlights their respective partitions void highlight_all_regions(ezgl::renderer* g); diff --git a/vpr/src/draw/draw_global.cpp b/vpr/src/draw/draw_global.cpp index 391b659bbcf..9fc5e0b5834 100644 --- a/vpr/src/draw/draw_global.cpp +++ b/vpr/src/draw/draw_global.cpp @@ -12,8 +12,8 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" -# include "draw_types.h" +#include "draw_global.h" +#include "draw_types.h" /*************************** Variables Definition ***************************/ diff --git a/vpr/src/draw/draw_global.h b/vpr/src/draw/draw_global.h index f1eec3967f5..e53b628cc73 100644 --- a/vpr/src/draw/draw_global.h +++ b/vpr/src/draw/draw_global.h @@ -15,13 +15,13 @@ #ifndef NO_GRAPHICS -# include "draw_types.h" +#include "draw_types.h" constexpr float DEFAULT_ARROW_SIZE = 0.3; // a very small area, in (screen pixels)^2 // used for level of detail culling -# define MIN_VISIBLE_AREA 3.0 +#define MIN_VISIBLE_AREA 3.0 t_draw_coords* get_draw_coords_vars(); diff --git a/vpr/src/draw/draw_mux.cpp b/vpr/src/draw/draw_mux.cpp index e83fde50296..7d03e2f468b 100644 --- a/vpr/src/draw/draw_mux.cpp +++ b/vpr/src/draw/draw_mux.cpp @@ -14,9 +14,9 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif //#define TIME_DRAWSCREEN /* Enable if want to track runtime for drawscreen() */ diff --git a/vpr/src/draw/draw_mux.h b/vpr/src/draw/draw_mux.h index dbfcf2b4d30..cb62427f339 100644 --- a/vpr/src/draw/draw_mux.h +++ b/vpr/src/draw/draw_mux.h @@ -31,11 +31,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" /** * @brief Draws a mux with width = height * 0.4 and scale (slope of the muxes sides) = 0.6, labelled with its size. diff --git a/vpr/src/draw/draw_noc.cpp b/vpr/src/draw/draw_noc.cpp index d112cb7cae5..a988d7b4d65 100644 --- a/vpr/src/draw/draw_noc.cpp +++ b/vpr/src/draw/draw_noc.cpp @@ -1,12 +1,12 @@ #ifndef NO_GRAPHICS -# include "draw_noc.h" -# include "globals.h" -# include "noc_storage.h" -# include "vpr_error.h" -# include "vtr_math.h" -# include "draw_basic.h" +#include "draw_basic.h" +#include "draw_noc.h" +#include "globals.h" +#include "noc_storage.h" +#include "physical_types_util.h" +#include "vtr_math.h" void draw_noc(ezgl::renderer* g) { t_draw_state* draw_state = get_draw_state_vars(); @@ -475,4 +475,4 @@ void shift_noc_link(noc_link_draw_coords& link_coords, NocLinkShift link_shift_d } } -#endif \ No newline at end of file +#endif diff --git a/vpr/src/draw/draw_noc.h b/vpr/src/draw/draw_noc.h index f3de82a3e3b..e24ae6b1db2 100644 --- a/vpr/src/draw/draw_noc.h +++ b/vpr/src/draw/draw_noc.h @@ -29,7 +29,7 @@ #ifndef NO_GRAPHICS -# include "draw.h" +#include "draw.h" // defines the area of the marker that represents connection points between links // area is equivalent to the %x of the area of the router @@ -243,4 +243,4 @@ void shift_noc_link(noc_link_draw_coords& link_coords, NocLinkShift link_shift_d #endif -#endif \ No newline at end of file +#endif diff --git a/vpr/src/draw/draw_rr.cpp b/vpr/src/draw/draw_rr.cpp index 62534bb0cc3..a47c76d3032 100644 --- a/vpr/src/draw/draw_rr.cpp +++ b/vpr/src/draw/draw_rr.cpp @@ -28,12 +28,12 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif /****************************** Define Macros *******************************/ -# define DEFAULT_RR_NODE_COLOR ezgl::BLACK +#define DEFAULT_RR_NODE_COLOR ezgl::BLACK //The arrow head position for turning/straight-thru connections in a switch box constexpr float SB_EDGE_TURN_ARROW_POSITION = 0.2; diff --git a/vpr/src/draw/draw_rr.h b/vpr/src/draw/draw_rr.h index 7ed40ffd61b..9c19f6bc951 100644 --- a/vpr/src/draw/draw_rr.h +++ b/vpr/src/draw/draw_rr.h @@ -32,20 +32,20 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" - -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" -# include "search_bar.h" -# include "draw_debug.h" -# include "manual_moves.h" - -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" +#include "draw_global.h" + +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" +#include "search_bar.h" +#include "draw_debug.h" +#include "manual_moves.h" + +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" /* Draws the routing resources that exist in the FPGA, if the user wants * * them drawn. */ diff --git a/vpr/src/draw/draw_rr_edges.cpp b/vpr/src/draw/draw_rr_edges.cpp index 0815be661a6..793487d04ab 100644 --- a/vpr/src/draw/draw_rr_edges.cpp +++ b/vpr/src/draw/draw_rr_edges.cpp @@ -1,20 +1,17 @@ /*draw_rr_edges.cpp contains all functions that draw lines between RR nodes.*/ #include +#include "physical_types_util.h" #include "vtr_assert.h" -#include "vtr_color_map.h" #include "vpr_utils.h" #include "vpr_error.h" #include "globals.h" -#include "draw_color.h" -#include "draw.h" #include "draw_rr.h" #include "draw_rr_edges.h" #include "draw_triangle.h" #include "draw_searchbar.h" -#include "read_xml_arch_file.h" #include "draw_global.h" #include "draw_basic.h" @@ -22,9 +19,9 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, short switch_type, ezgl::renderer* g) { t_draw_state* draw_state = get_draw_state_vars(); @@ -184,7 +181,7 @@ void draw_chanx_to_chanx_edge(RRNodeId from_node, RRNodeId to_node, short switch + draw_coords->get_tile_width(); x2 = to_chan.left(); - } /* The following then is executed when from_xlow == to_xlow */ + } /* The following then is executed when from_xlow == to_xlow */ else if (to_xhigh > from_xhigh) { /* Draw from right edge of one to other */ x1 = from_chan.right(); x2 = draw_coords->tile_x[from_xhigh + 1]; diff --git a/vpr/src/draw/draw_rr_edges.h b/vpr/src/draw/draw_rr_edges.h index 9068b31b4fe..8ea7a383dcb 100644 --- a/vpr/src/draw/draw_rr_edges.h +++ b/vpr/src/draw/draw_rr_edges.h @@ -32,20 +32,20 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" - -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" -# include "search_bar.h" -# include "draw_debug.h" -# include "manual_moves.h" - -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" +#include "draw_global.h" + +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" +#include "search_bar.h" +#include "draw_debug.h" +#include "manual_moves.h" + +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, short switch_type, ezgl::renderer* g); void draw_chanx_to_chanx_edge(RRNodeId from_node, RRNodeId to_node, short switch_type, ezgl::renderer* g); diff --git a/vpr/src/draw/draw_searchbar.cpp b/vpr/src/draw/draw_searchbar.cpp index a90583f42ce..270435fe04f 100644 --- a/vpr/src/draw/draw_searchbar.cpp +++ b/vpr/src/draw/draw_searchbar.cpp @@ -1,18 +1,16 @@ /*draw_searchbar.cpp contains all functions related to searchbar actions.*/ #include -#include #include "netlist_fwd.h" +#include "physical_types_util.h" #include "vpr_utils.h" #include "globals.h" -#include "draw_color.h" #include "draw.h" #include "draw_rr.h" #include "draw_basic.h" #include "draw_searchbar.h" -#include "read_xml_arch_file.h" #include "draw_global.h" #include "intra_logic_block.h" @@ -20,13 +18,13 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif /****************************** Define Macros *******************************/ -# define DEFAULT_RR_NODE_COLOR ezgl::BLACK +#define DEFAULT_RR_NODE_COLOR ezgl::BLACK /* This function computes and returns the boundary coordinates of a channel * wire segment. This can be used for drawing a wire or determining if a @@ -144,7 +142,7 @@ void highlight_nets(char* message, RRNodeId hit_node, bool is_flat) { t_draw_state* draw_state = get_draw_state_vars(); for (auto net_id : cluster_ctx.clb_nlist.nets()) { - ParentNetId parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup, net_id, is_flat); + ParentNetId parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup(), net_id, is_flat); if (!route_ctx.route_trees[parent_id]) continue; diff --git a/vpr/src/draw/draw_searchbar.h b/vpr/src/draw/draw_searchbar.h index e4dade9bb58..25a135be153 100644 --- a/vpr/src/draw/draw_searchbar.h +++ b/vpr/src/draw/draw_searchbar.h @@ -33,20 +33,20 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" - -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" -# include "search_bar.h" -# include "draw_debug.h" -# include "manual_moves.h" - -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" +#include "draw_global.h" + +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" +#include "search_bar.h" +#include "draw_debug.h" +#include "manual_moves.h" + +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" /* This function computes and returns the boundary coordinates of a channel * wire segment. This can be used for drawing a wire or determining if a diff --git a/vpr/src/draw/draw_toggle_functions.cpp b/vpr/src/draw/draw_toggle_functions.cpp index 968808c2906..ddd518cf4a5 100644 --- a/vpr/src/draw/draw_toggle_functions.cpp +++ b/vpr/src/draw/draw_toggle_functions.cpp @@ -18,9 +18,9 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif //The arrow head position for turning/straight-thru connections in a switch box constexpr float SB_EDGE_TURN_ARROW_POSITION = 0.2; diff --git a/vpr/src/draw/draw_toggle_functions.h b/vpr/src/draw/draw_toggle_functions.h index 7b8330396b7..e6c9114900e 100644 --- a/vpr/src/draw/draw_toggle_functions.h +++ b/vpr/src/draw/draw_toggle_functions.h @@ -38,20 +38,20 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" - -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" -# include "search_bar.h" -# include "draw_debug.h" -# include "manual_moves.h" - -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" +#include "draw_global.h" + +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" +#include "search_bar.h" +#include "draw_debug.h" +#include "manual_moves.h" + +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" /* Callback function for main.ui created toggle_nets button in ui_setup.cpp. Controls whether or not nets are visualized. * Toggles value of draw_state->show_nets.*/ diff --git a/vpr/src/draw/draw_triangle.cpp b/vpr/src/draw/draw_triangle.cpp index 82b5bd45376..83ccd1af7f1 100644 --- a/vpr/src/draw/draw_triangle.cpp +++ b/vpr/src/draw/draw_triangle.cpp @@ -7,14 +7,13 @@ #include "draw_triangle.h" #include "draw_global.h" - #ifndef NO_GRAPHICS //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif /** * Retrieves the current zoom level based on the visible world and screen dimensions. diff --git a/vpr/src/draw/draw_triangle.h b/vpr/src/draw/draw_triangle.h index 0ddf12218ec..9c0116f0c5a 100644 --- a/vpr/src/draw/draw_triangle.h +++ b/vpr/src/draw/draw_triangle.h @@ -33,20 +33,20 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" -# include "search_bar.h" -# include "draw_debug.h" -# include "manual_moves.h" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" +#include "search_bar.h" +#include "draw_debug.h" +#include "manual_moves.h" -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" /** * Retrieves the current zoom level based on the visible world and screen dimensions. diff --git a/vpr/src/draw/draw_types.cpp b/vpr/src/draw/draw_types.cpp index b3909c5fd7c..03940843648 100644 --- a/vpr/src/draw/draw_types.cpp +++ b/vpr/src/draw/draw_types.cpp @@ -1,12 +1,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" -# include "draw_types.h" -# include "draw_toggle_functions.h" -# include "globals.h" -# include "vpr_utils.h" -# include "draw.h" -# include +#include "draw.h" +#include "draw_global.h" +#include "draw_types.h" +#include "globals.h" +#include "physical_types_util.h" +#include "vpr_utils.h" /******************************************* * begin t_draw_state function definitions * diff --git a/vpr/src/draw/draw_types.h b/vpr/src/draw/draw_types.h index 1f6689e63f4..8d96ceaf732 100644 --- a/vpr/src/draw/draw_types.h +++ b/vpr/src/draw/draw_types.h @@ -20,20 +20,20 @@ #ifndef NO_GRAPHICS -# include -# include -# include "clustered_netlist.h" -# include "timing_info_fwd.h" -# include "vtr_util.h" -# include "vpr_types.h" -# include "vtr_color_map.h" -# include "vtr_vector.h" -# include "breakpoint.h" -# include "manual_moves.h" - -# include "ezgl/point.hpp" -# include "ezgl/rectangle.hpp" -# include "ezgl/color.hpp" +#include +#include +#include "clustered_netlist.h" +#include "timing_info_fwd.h" +#include "vtr_util.h" +#include "vpr_types.h" +#include "vtr_color_map.h" +#include "vtr_vector.h" +#include "breakpoint.h" +#include "manual_moves.h" + +#include "ezgl/point.hpp" +#include "ezgl/rectangle.hpp" +#include "ezgl/color.hpp" enum e_draw_crit_path { DRAW_NO_CRIT_PATH, @@ -410,6 +410,11 @@ struct t_draw_coords { ///@brief constructor t_draw_coords(); + ///@brief Sets the tile width + inline void set_tile_width(float new_tile_width) { + tile_width = new_tile_width; + } + ///@brief returns tile width float get_tile_width(); diff --git a/vpr/src/draw/gtkcomboboxhelper.cpp b/vpr/src/draw/gtkcomboboxhelper.cpp index 6da464289ca..4892fb0afc3 100644 --- a/vpr/src/draw/gtkcomboboxhelper.cpp +++ b/vpr/src/draw/gtkcomboboxhelper.cpp @@ -58,4 +58,4 @@ gint get_item_index_by_text(gpointer combo_box, const gchar* target_item) { return result_index; } -#endif // NO_GRAPHICS \ No newline at end of file +#endif // NO_GRAPHICS diff --git a/vpr/src/draw/hsl.cpp b/vpr/src/draw/hsl.cpp index b5f8403e724..4a909e77252 100644 --- a/vpr/src/draw/hsl.cpp +++ b/vpr/src/draw/hsl.cpp @@ -1,8 +1,8 @@ #ifndef NO_GRAPHICS -# include +#include -# include "hsl.h" +#include "hsl.h" float hue2rgb(float v1, float v2, float vH); diff --git a/vpr/src/draw/hsl.h b/vpr/src/draw/hsl.h index e7d6d4508d2..589266bc6e4 100644 --- a/vpr/src/draw/hsl.h +++ b/vpr/src/draw/hsl.h @@ -9,7 +9,7 @@ #ifndef NO_GRAPHICS -# include "ezgl/color.hpp" +#include "ezgl/color.hpp" struct hsl { double h; // hue a fraction between 0 and 1 diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index c1ee67c7590..375eee6f151 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -20,21 +20,21 @@ #ifndef NO_GRAPHICS -# include -# include -# include - -# include "vtr_assert.h" -# include "vtr_memory.h" - -# include "intra_logic_block.h" -# include "globals.h" -# include "atom_netlist.h" -# include "vpr_utils.h" -# include "draw_global.h" -# include "draw.h" -# include "draw_triangle.h" -# include "draw_color.h" +#include +#include +#include + +#include "vtr_assert.h" +#include "vtr_memory.h" + +#include "intra_logic_block.h" +#include "globals.h" +#include "atom_netlist.h" +#include "vpr_utils.h" +#include "draw_global.h" +#include "draw.h" +#include "draw_triangle.h" +#include "draw_color.h" /************************* Subroutines local to this file. *******************************/ @@ -45,12 +45,12 @@ std::vector collect_pb_atoms(const t_pb* pb); void collect_pb_atoms_recurr(const t_pb* pb, std::vector& atoms); t_pb* highlight_sub_block_helper(const ClusterBlockId clb_index, t_pb* pb, const ezgl::point2d& local_pt, int max_depth); -# ifndef NO_GRAPHICS +#ifndef NO_GRAPHICS static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezgl::rectangle& parent_bbox, const t_logical_block_type_ptr type, ezgl::renderer* g); void draw_atoms_fanin_fanout_flylines(const std::vector& atoms, ezgl::renderer* g); void draw_selected_pb_flylines(ezgl::renderer* g); void draw_one_logical_connection(const AtomPinId src_pin, const AtomPinId sink_pin, ezgl::renderer* g); -# endif /* NO_GRAPHICS */ +#endif /* NO_GRAPHICS */ /************************* Subroutine definitions begin *********************************/ @@ -141,7 +141,7 @@ void draw_internal_init_blk() { //draw_state->max_sub_blk_lvl -= 1; } -# ifndef NO_GRAPHICS +#ifndef NO_GRAPHICS void draw_internal_draw_subblk(ezgl::renderer* g) { t_draw_state* draw_state = get_draw_state_vars(); if (!draw_state->show_blk_internal) { @@ -192,7 +192,7 @@ void draw_internal_draw_subblk(ezgl::renderer* g) { //(inputs: blue, outputs: red, internal: orange) draw_selected_pb_flylines(g); } -# endif /* NO_GRAPHICS */ +#endif /* NO_GRAPHICS */ /* This function traverses through the pb_graph of a certain physical block type and * finds the maximum sub-block levels for that type. @@ -326,7 +326,7 @@ draw_internal_calc_coords(int type_descrip_index, t_pb_graph_node* pb_graph_node *blk_height = child_height; } -# ifndef NO_GRAPHICS +#ifndef NO_GRAPHICS /* Helper subroutine to draw all sub-blocks. This function traverses through the pb_graph * which a netlist block can map to, and draws each sub-block inside its parent block. With * each click on the "Blk Internal" button, a new level is shown. @@ -471,7 +471,7 @@ void draw_selected_pb_flylines(ezgl::renderer* g) { void draw_atoms_fanin_fanout_flylines(const std::vector& atoms, ezgl::renderer* g) { std::set atoms_set(atoms.begin(), atoms.end()); - auto& atom_nl = g_vpr_ctx.atom().nlist; + auto& atom_nl = g_vpr_ctx.atom().netlist(); g->set_line_dash(ezgl::line_dash::none); g->set_line_width(2); @@ -517,7 +517,7 @@ void draw_atoms_fanin_fanout_flylines(const std::vector& atoms, ezg } } } -# endif /* NO_GRAPHICS */ +#endif /* NO_GRAPHICS */ std::vector collect_pb_atoms(const t_pb* pb) { std::vector atoms; @@ -530,13 +530,13 @@ void collect_pb_atoms_recurr(const t_pb* pb, std::vector& atoms) { if (pb->is_primitive()) { //Base case - AtomBlockId blk = atom_ctx.lookup.pb_atom(pb); + AtomBlockId blk = atom_ctx.lookup().atom_pb_bimap().pb_atom(pb); if (blk) { atoms.push_back(blk); } } else { //Recurse - VTR_ASSERT_DEBUG(atom_ctx.lookup.pb_atom(pb) == AtomBlockId::INVALID()); + VTR_ASSERT_DEBUG(atom_ctx.lookup().atom_pb_bimap().pb_atom(pb) == AtomBlockId::INVALID()); for (int itype = 0; itype < pb->get_num_child_types(); ++itype) { for (int ichild = 0; ichild < pb->get_num_children_of_type(itype); ++ichild) { @@ -546,7 +546,7 @@ void collect_pb_atoms_recurr(const t_pb* pb, std::vector& atoms) { } } -# ifndef NO_GRAPHICS +#ifndef NO_GRAPHICS void draw_logical_connections(ezgl::renderer* g) { const t_selected_sub_block_info& sel_subblk_info = get_selected_sub_block_info(); t_draw_state* draw_state = get_draw_state_vars(); @@ -560,14 +560,14 @@ void draw_logical_connections(ezgl::renderer* g) { int transparency_factor; // iterate over all the atom nets - for (auto net_id : atom_ctx.nlist.nets()) { - if ((int)atom_ctx.nlist.net_pins(net_id).size() - 1 > draw_state->draw_net_max_fanout) { + for (auto net_id : atom_ctx.netlist().nets()) { + if ((int)atom_ctx.netlist().net_pins(net_id).size() - 1 > draw_state->draw_net_max_fanout) { continue; } - AtomPinId driver_pin_id = atom_ctx.nlist.net_driver(net_id); - AtomBlockId src_blk_id = atom_ctx.nlist.pin_block(driver_pin_id); - ClusterBlockId src_clb = atom_ctx.lookup.atom_clb(src_blk_id); + AtomPinId driver_pin_id = atom_ctx.netlist().net_driver(net_id); + AtomBlockId src_blk_id = atom_ctx.netlist().pin_block(driver_pin_id); + ClusterBlockId src_clb = atom_ctx.lookup().atom_clb(src_blk_id); int src_layer_num = block_locs[src_clb].loc.layer; //To only show primitive nets that are connected to currently active layers on the screen @@ -575,15 +575,15 @@ void draw_logical_connections(ezgl::renderer* g) { continue; /* Don't Draw */ } - const t_pb_graph_node* src_pb_gnode = atom_ctx.lookup.atom_pb_graph_node(src_blk_id); + const t_pb_graph_node* src_pb_gnode = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(src_blk_id); bool src_is_selected = sel_subblk_info.is_in_selected_subtree(src_pb_gnode, src_clb); bool src_is_src_of_selected = sel_subblk_info.is_source_of_selected(src_pb_gnode, src_clb); // iterate over the sinks - for (auto sink_pin_id : atom_ctx.nlist.net_sinks(net_id)) { - AtomBlockId sink_blk_id = atom_ctx.nlist.pin_block(sink_pin_id); - const t_pb_graph_node* sink_pb_gnode = atom_ctx.lookup.atom_pb_graph_node(sink_blk_id); - ClusterBlockId sink_clb = atom_ctx.lookup.atom_clb(sink_blk_id); + for (auto sink_pin_id : atom_ctx.netlist().net_sinks(net_id)) { + AtomBlockId sink_blk_id = atom_ctx.netlist().pin_block(sink_pin_id); + const t_pb_graph_node* sink_pb_gnode = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(sink_blk_id); + ClusterBlockId sink_clb = atom_ctx.lookup().atom_clb(sink_blk_id); int sink_layer_num = block_locs[sink_clb].loc.layer; t_draw_layer_display element_visibility = get_element_visibility_and_transparency(src_layer_num, sink_layer_num); @@ -610,7 +610,7 @@ void draw_logical_connections(ezgl::renderer* g) { } } } -# endif /* NO_GRAPHICS */ +#endif /* NO_GRAPHICS */ /** * Helper function for draw_one_logical_connection(...). @@ -627,21 +627,21 @@ void draw_logical_connections(ezgl::renderer* g) { void find_pin_index_at_model_scope(const AtomPinId pin_id, const AtomBlockId blk_id, int* pin_index, int* total_pins) { auto& atom_ctx = g_vpr_ctx.atom(); - AtomPortId port_id = atom_ctx.nlist.pin_port(pin_id); - const t_model_ports* model_port = atom_ctx.nlist.port_model(port_id); + AtomPortId port_id = atom_ctx.netlist().pin_port(pin_id); + const t_model_ports* model_port = atom_ctx.netlist().port_model(port_id); //Total up the port widths // Note that we do this on the model since the atom netlist doesn't include unused ports int pin_cnt = 0; *pin_index = -1; //initialize - const t_model* model = atom_ctx.nlist.block_model(blk_id); + const t_model* model = atom_ctx.netlist().block_model(blk_id); for (const t_model_ports* port : {model->inputs, model->outputs}) { while (port) { if (port == model_port) { //This is the port the pin is associated with, record it's index //Get the pin index in the port - int atom_port_index = atom_ctx.nlist.pin_port_bit(pin_id); + int atom_port_index = atom_ctx.netlist().pin_port_bit(pin_id); //The index of this pin in the model is the pins counted so-far //(i.e. across previous ports) plus the index in the port @@ -660,7 +660,7 @@ void find_pin_index_at_model_scope(const AtomPinId pin_id, const AtomBlockId blk *total_pins = pin_cnt; } -# ifndef NO_GRAPHICS +#ifndef NO_GRAPHICS /** * Draws ONE logical connection from src_pin in src_lblk to sink_pin in sink_lblk. * The *_abs_bbox parameters are for mild optimization, as the absolute bbox can be calculated @@ -674,7 +674,7 @@ void draw_one_logical_connection(const AtomPinId src_pin, const AtomPinId sink_p g->draw_line(src_point, sink_point); const auto& atom_ctx = g_vpr_ctx.atom(); - if (atom_ctx.lookup.atom_clb(atom_ctx.nlist.pin_block(src_pin)) == atom_ctx.lookup.atom_clb(atom_ctx.nlist.pin_block(sink_pin))) { + if (atom_ctx.lookup().atom_clb(atom_ctx.netlist().pin_block(src_pin)) == atom_ctx.lookup().atom_clb(atom_ctx.netlist().pin_block(sink_pin))) { // if they are in the same clb, put one arrow in the center float center_x = (src_point.x + sink_point.x) / 2; float center_y = (src_point.y + sink_point.y) / 2; @@ -689,7 +689,7 @@ void draw_one_logical_connection(const AtomPinId src_pin, const AtomPinId sink_p draw_triangle_along_line(g, src_point, sink_point, 0.95); } } -# endif /* NO_GRAPHICS */ +#endif /* NO_GRAPHICS */ int highlight_sub_block(const ezgl::point2d& point_in_clb, ClusterBlockId clb_index, t_pb* pb) { t_draw_state* draw_state = get_draw_state_vars(); @@ -805,32 +805,32 @@ void t_selected_sub_block_info::set(t_pb* new_selected_sub_block, const ClusterB if (has_selection()) { add_all_children(selected_pb, containing_block_index, in_selected_subtree); - for (auto blk_id : atom_ctx.nlist.blocks()) { - const ClusterBlockId clb = atom_ctx.lookup.atom_clb(blk_id); - const t_pb_graph_node* pb_graph_node = atom_ctx.lookup.atom_pb_graph_node(blk_id); + for (auto blk_id : atom_ctx.netlist().blocks()) { + const ClusterBlockId clb = atom_ctx.lookup().atom_clb(blk_id); + const t_pb_graph_node* pb_graph_node = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(blk_id); // find the atom block that corrisponds to this pb. if (is_in_selected_subtree(pb_graph_node, clb)) { //Collect the sources of all nets driving this node - for (auto pin_id : atom_ctx.nlist.block_input_pins(blk_id)) { - AtomNetId net_id = atom_ctx.nlist.pin_net(pin_id); - AtomPinId driver_pin_id = atom_ctx.nlist.net_driver(net_id); + for (auto pin_id : atom_ctx.netlist().block_input_pins(blk_id)) { + AtomNetId net_id = atom_ctx.netlist().pin_net(pin_id); + AtomPinId driver_pin_id = atom_ctx.netlist().net_driver(net_id); - AtomBlockId src_blk = atom_ctx.nlist.pin_block(driver_pin_id); + AtomBlockId src_blk = atom_ctx.netlist().pin_block(driver_pin_id); - const ClusterBlockId src_clb = atom_ctx.lookup.atom_clb(src_blk); - const t_pb_graph_node* src_pb_graph_node = atom_ctx.lookup.atom_pb_graph_node(src_blk); + const ClusterBlockId src_clb = atom_ctx.lookup().atom_clb(src_blk); + const t_pb_graph_node* src_pb_graph_node = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(src_blk); sources.insert(gnode_clb_pair(src_pb_graph_node, src_clb)); } //Collect the sinks of all nets driven by this node - for (auto pin_id : atom_ctx.nlist.block_output_pins(blk_id)) { - AtomNetId net_id = atom_ctx.nlist.pin_net(pin_id); - for (auto sink_pin_id : atom_ctx.nlist.net_sinks(net_id)) { - AtomBlockId sink_blk = atom_ctx.nlist.pin_block(sink_pin_id); + for (auto pin_id : atom_ctx.netlist().block_output_pins(blk_id)) { + AtomNetId net_id = atom_ctx.netlist().pin_net(pin_id); + for (auto sink_pin_id : atom_ctx.netlist().net_sinks(net_id)) { + AtomBlockId sink_blk = atom_ctx.netlist().pin_block(sink_pin_id); - const ClusterBlockId sink_clb = atom_ctx.lookup.atom_clb(sink_blk); - const t_pb_graph_node* sink_pb_graph_node = atom_ctx.lookup.atom_pb_graph_node(sink_blk); + const ClusterBlockId sink_clb = atom_ctx.lookup().atom_clb(sink_blk); + const t_pb_graph_node* sink_pb_graph_node = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(sink_blk); sinks.insert(gnode_clb_pair(sink_pb_graph_node, sink_clb)); } @@ -881,8 +881,8 @@ t_selected_sub_block_info::clb_pin_tuple::clb_pin_tuple(ClusterBlockId clb_index t_selected_sub_block_info::clb_pin_tuple::clb_pin_tuple(const AtomPinId atom_pin) { auto& atom_ctx = g_vpr_ctx.atom(); - clb_index = atom_ctx.lookup.atom_clb(atom_ctx.nlist.pin_block(atom_pin)); - pb_gnode = atom_ctx.lookup.atom_pb_graph_node(atom_ctx.nlist.pin_block(atom_pin)); + clb_index = atom_ctx.lookup().atom_clb(atom_ctx.netlist().pin_block(atom_pin)); + pb_gnode = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(atom_ctx.netlist().pin_block(atom_pin)); } bool t_selected_sub_block_info::clb_pin_tuple::operator==(const clb_pin_tuple& rhs) const { @@ -905,7 +905,7 @@ bool t_selected_sub_block_info::gnode_clb_pair::operator==(const gnode_clb_pair& /** * @brief Recursively looks through pb graph to find block w. given name - * + * * @param name name of block being searched for * @param pb current node to be examined * @return t_pb* t_pb ptr of block w. name "name". Returns nullptr if nothing found diff --git a/vpr/src/draw/intra_logic_block.h b/vpr/src/draw/intra_logic_block.h index 320a3c9f406..7ad0bf9bba5 100644 --- a/vpr/src/draw/intra_logic_block.h +++ b/vpr/src/draw/intra_logic_block.h @@ -20,17 +20,17 @@ #ifndef NO_GRAPHICS -# include "vpr_types.h" -# include "draw_types.h" -# include "atom_netlist_fwd.h" -# include +#include "vpr_types.h" +#include "draw_types.h" +#include "atom_netlist_fwd.h" +#include -# include "ezgl/point.hpp" +#include "ezgl/point.hpp" -# ifndef NO_GRAPHICS -# include "ezgl/graphics.hpp" -# include "ezgl/application.hpp" -# endif /* NO_GRAPHICS */ +#ifndef NO_GRAPHICS +#include "ezgl/graphics.hpp" +#include "ezgl/application.hpp" +#endif /* NO_GRAPHICS */ struct t_selected_sub_block_info { struct clb_pin_tuple { @@ -112,9 +112,9 @@ void draw_internal_init_blk(); /* Top-level drawing routine for internal sub-blocks. The function traverses through all * grid tiles and calls helper function to draw inside each block. */ -# ifndef NO_GRAPHICS +#ifndef NO_GRAPHICS void draw_internal_draw_subblk(ezgl::renderer* g); -# endif /* NO_GRAPHICS */ +#endif /* NO_GRAPHICS */ /* Determines which part of a block to highlight, and stores it, * so that the other subblock drawing functions will obey it. diff --git a/vpr/src/draw/manual_moves.cpp b/vpr/src/draw/manual_moves.cpp index 6a98d6ee419..972b2a36bd7 100644 --- a/vpr/src/draw/manual_moves.cpp +++ b/vpr/src/draw/manual_moves.cpp @@ -17,6 +17,7 @@ #include "draw.h" #include "draw_searchbar.h" #include "buttons.h" +#include "physical_types_util.h" #ifndef NO_GRAPHICS diff --git a/vpr/src/draw/manual_moves.h b/vpr/src/draw/manual_moves.h index 45739549c85..e5c152275d4 100644 --- a/vpr/src/draw/manual_moves.h +++ b/vpr/src/draw/manual_moves.h @@ -13,17 +13,17 @@ /** This file contains all functions for manual moves **/ #ifndef NO_GRAPHICS -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "manual_move_generator.h" - -# include "move_utils.h" -# include -# include -# include -# include -# include -# include +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "manual_move_generator.h" + +#include "move_utils.h" +#include +#include +#include +#include +#include +#include /** * @brief ManualMovesInfo struct diff --git a/vpr/src/draw/save_graphics.cpp b/vpr/src/draw/save_graphics.cpp index 84b1599f30f..657c6626b42 100644 --- a/vpr/src/draw/save_graphics.cpp +++ b/vpr/src/draw/save_graphics.cpp @@ -1,14 +1,10 @@ #ifndef NO_GRAPHICS -# include -# include - -# include "globals.h" -# include "draw.h" -# include "draw_global.h" -# include "save_graphics.h" -# include "vtr_path.h" -# include "search_bar.h" +#include + +#include "draw.h" +#include "save_graphics.h" +#include "search_bar.h" extern ezgl::rectangle initial_world; diff --git a/vpr/src/draw/save_graphics.h b/vpr/src/draw/save_graphics.h index 0ea5b183de0..f9a6ec2fbb1 100644 --- a/vpr/src/draw/save_graphics.h +++ b/vpr/src/draw/save_graphics.h @@ -9,11 +9,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" void save_graphics(std::string extension, std::string file_name); void save_graphics_dialog_box(GtkWidget* /*widget*/, ezgl::application* /*app*/); diff --git a/vpr/src/draw/search_bar.cpp b/vpr/src/draw/search_bar.cpp index ada698cf136..9a93be2274d 100644 --- a/vpr/src/draw/search_bar.cpp +++ b/vpr/src/draw/search_bar.cpp @@ -15,42 +15,42 @@ #include "physical_types.h" #ifndef NO_GRAPHICS -# include -# include - -# include "vtr_assert.h" -# include "vtr_ndoffsetmatrix.h" -# include "vtr_memory.h" -# include "vtr_log.h" -# include "vtr_color_map.h" - -# include "vpr_utils.h" -# include "vpr_error.h" - -# include "globals.h" -# include "draw_color.h" -# include "draw.h" -# include "draw_basic.h" -# include "draw_rr.h" -# include "draw_searchbar.h" -# include "read_xml_arch_file.h" -# include "draw_global.h" -# include "intra_logic_block.h" -# include "atom_netlist.h" -# include "tatum/report/TimingPathCollector.hpp" -# include "hsl.h" -# include "route_export.h" -# include "search_bar.h" +#include +#include + +#include "vtr_assert.h" +#include "vtr_ndoffsetmatrix.h" +#include "vtr_memory.h" +#include "vtr_log.h" +#include "vtr_color_map.h" + +#include "vpr_utils.h" +#include "vpr_error.h" + +#include "globals.h" +#include "draw_color.h" +#include "draw.h" +#include "draw_basic.h" +#include "draw_rr.h" +#include "draw_searchbar.h" +#include "read_xml_arch_file.h" +#include "draw_global.h" +#include "intra_logic_block.h" +#include "atom_netlist.h" +#include "tatum/report/TimingPathCollector.hpp" +#include "hsl.h" +#include "route_export.h" +#include "search_bar.h" //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" extern std::string rr_highlight_message; @@ -112,9 +112,9 @@ void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app) { std::string block_name; ss >> block_name; - AtomBlockId atom_blk_id = atom_ctx.nlist.find_block(block_name); + AtomBlockId atom_blk_id = atom_ctx.netlist().find_block(block_name); if (atom_blk_id != AtomBlockId::INVALID()) { - ClusterBlockId cluster_block_id = atom_ctx.lookup.atom_clb(atom_blk_id); + ClusterBlockId cluster_block_id = atom_ctx.lookup().atom_clb(atom_blk_id); if (!highlight_atom_block(atom_blk_id, cluster_block_id, app)) { highlight_cluster_block(cluster_block_id); } @@ -151,15 +151,15 @@ void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app) { //So we only need to search this one std::string net_name; ss >> net_name; - AtomNetId atom_net_id = atom_ctx.nlist.find_net(net_name); + AtomNetId atom_net_id = atom_ctx.netlist().find_net(net_name); if (atom_net_id == AtomNetId::INVALID()) { warning_dialog_box("Invalid Net Name"); return; //name not exist } - const auto clb_nets = atom_ctx.lookup.clb_nets(atom_net_id); - for(auto clb_net_id: clb_nets.value()){ + const auto clb_nets = atom_ctx.lookup().clb_nets(atom_net_id); + for (auto clb_net_id : clb_nets.value()) { highlight_nets(clb_net_id); } } @@ -319,7 +319,7 @@ bool highlight_atom_block(AtomBlockId atom_blk, ClusterBlockId cl_blk, ezgl::app t_pb* pb = cl_ctx.clb_nlist.block_pb(cl_blk); //Getting the pb* for the atom block - auto atom_block_pb = find_atom_block_in_pb(atom_ctx.nlist.block_name(atom_blk), pb); + auto atom_block_pb = find_atom_block_in_pb(atom_ctx.netlist().block_name(atom_blk), pb); if (!atom_block_pb) return false; //If no block found, returning false //Ensuring that block is drawn at current zoom lvl, returning false if not diff --git a/vpr/src/draw/search_bar.h b/vpr/src/draw/search_bar.h index 8108bfa8c4a..5aafd49435d 100644 --- a/vpr/src/draw/search_bar.h +++ b/vpr/src/draw/search_bar.h @@ -12,12 +12,12 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app); bool highlight_rr_nodes(RRNodeId hit_node); @@ -53,4 +53,4 @@ GdkEvent simulate_keypress(char key, GdkWindow* window); std::string get_search_type(ezgl::application* app); #endif /* NO_GRAPHICS */ -#endif /* SEARCH_BAR_H */ \ No newline at end of file +#endif /* SEARCH_BAR_H */ diff --git a/vpr/src/draw/ui_setup.cpp b/vpr/src/draw/ui_setup.cpp index 61e05c9be3e..d62d8210e63 100644 --- a/vpr/src/draw/ui_setup.cpp +++ b/vpr/src/draw/ui_setup.cpp @@ -4,24 +4,24 @@ * @author Sebastian Lievano * @date July 4th, 2022 * @brief Manages setup for main.ui created buttons - * + * * This file contains the various setup functions for all of the ui functions. * As of June 2022, gtk ui items are to be created through Glade/main.ui file (see Docs) * Each function here initializes a different set of ui buttons, connecting their callback functions */ -# include "draw_global.h" -# include "draw.h" -# include "draw_toggle_functions.h" -# include "buttons.h" -# include "intra_logic_block.h" -# include "clustered_netlist.h" -# include "ui_setup.h" -# include "save_graphics.h" - -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "draw_global.h" +#include "draw.h" +#include "draw_toggle_functions.h" +#include "buttons.h" +#include "intra_logic_block.h" +#include "clustered_netlist.h" +#include "ui_setup.h" +#include "save_graphics.h" + +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" void basic_button_setup(ezgl::application* app) { //button to enter window_mode, created in main.ui GtkButton* window = (GtkButton*)app->get_object("Window"); @@ -45,7 +45,7 @@ void basic_button_setup(ezgl::application* app) { /* * @brief sets up net related buttons and connects their signals - * + * * Sets up the toggle nets combo box, net alpha spin button, and max fanout * spin button which are created in main.ui file. Found in Net Settings dropdown * @param app ezgl::application ptr @@ -70,11 +70,11 @@ void net_button_setup(ezgl::application* app) { /* * @brief sets up block related buttons, connects their signals - * + * * Connects signals and sets init. values for blk internals spin button, * blk pin util combo box,placement macros combo box, and noc combo bx created in * main.ui. Found in Block Settings dropdown - * @param app + * @param app */ void block_button_setup(ezgl::application* app) { t_draw_state* draw_state = get_draw_state_vars(); @@ -105,10 +105,10 @@ void block_button_setup(ezgl::application* app) { /** * @brief configures and connects signals/functions for routing buttons - * + * * Connects signals/sets default values for toggleRRButton, ToggleCongestion, - * ToggleCongestionCost, ToggleRoutingBBox, RoutingExpansionCost, ToggleRoutingUtil - * buttons. + * ToggleCongestionCost, ToggleRoutingBBox, RoutingExpansionCost, ToggleRoutingUtil + * buttons. */ void routing_button_setup(ezgl::application* app) { auto& route_ctx = g_vpr_ctx.routing(); @@ -216,7 +216,7 @@ void search_setup(ezgl::application* app) { /* * @brief connects critical path button to its cbk fn - * + * * @param app ezgl application */ void crit_path_button_setup(ezgl::application* app) { @@ -242,7 +242,7 @@ void hide_crit_path_routing(ezgl::application* app, bool hide) { } /* * @brief Hides the widget with the given name - * + * * @param widgetName string of widget name in main.ui * @param app ezgl app */ @@ -261,7 +261,7 @@ void show_widget(std::string widgetName, ezgl::application* app) { /** * @brief loads atom and cluster lvl names into gtk list store item used for completion - * + * * @param app ezgl application used for ui */ void load_block_names(ezgl::application* app) { @@ -276,17 +276,17 @@ void load_block_names(ezgl::application* app) { 0, (cluster_ctx.clb_nlist.block_name(id)).c_str(), -1); i++; } - for (AtomBlockId id : atom_ctx.nlist.blocks()) { + for (AtomBlockId id : atom_ctx.netlist().blocks()) { gtk_list_store_append(blockStorage, &iter); gtk_list_store_set(blockStorage, &iter, - 0, (atom_ctx.nlist.block_name(id)).c_str(), -1); + 0, (atom_ctx.netlist().block_name(id)).c_str(), -1); i++; } } /* * @brief loads atom net names into gtk list store item used for completion - * + * * @param app ezgl application used for ui */ void load_net_names(ezgl::application* app) { @@ -295,10 +295,10 @@ void load_net_names(ezgl::application* app) { GtkTreeIter iter; //Loading net names int i = 0; - for (AtomNetId id : atom_ctx.nlist.nets()) { + for (AtomNetId id : atom_ctx.netlist().nets()) { gtk_list_store_append(netStorage, &iter); gtk_list_store_set(netStorage, &iter, - 0, (atom_ctx.nlist.net_name(id)).c_str(), -1); + 0, (atom_ctx.netlist().net_name(id)).c_str(), -1); i++; } } diff --git a/vpr/src/draw/ui_setup.h b/vpr/src/draw/ui_setup.h index 40f2045ed91..3b543adb493 100644 --- a/vpr/src/draw/ui_setup.h +++ b/vpr/src/draw/ui_setup.h @@ -14,11 +14,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" /** * @brief configures basic buttons @@ -101,4 +101,4 @@ void show_widget(std::string widgetName, ezgl::application* app); #endif /* NO_GRAPHICS */ -#endif /* UISETUP_H */ \ No newline at end of file +#endif /* UISETUP_H */ diff --git a/vpr/src/noc/bfs_routing.cpp b/vpr/src/noc/bfs_routing.cpp index a72ec6b29e4..ef7d5c00d0e 100644 --- a/vpr/src/noc/bfs_routing.cpp +++ b/vpr/src/noc/bfs_routing.cpp @@ -129,4 +129,4 @@ void BFSRouting::generate_route(NocRouterId start_router_id, // now get the parent of the router we moved to curr_intermediate_router_parent_link = router_parent_link.find(curr_intermediate_router); } -} \ No newline at end of file +} diff --git a/vpr/src/noc/bfs_routing.h b/vpr/src/noc/bfs_routing.h index ca28a8ca3fd..7d881bed8b1 100644 --- a/vpr/src/noc/bfs_routing.h +++ b/vpr/src/noc/bfs_routing.h @@ -87,4 +87,4 @@ class BFSRouting : public NocRouting { const std::unordered_map& router_parent_link); }; -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/channel_dependency_graph.cpp b/vpr/src/noc/channel_dependency_graph.cpp index 31bd4052485..f85de80c0ac 100644 --- a/vpr/src/noc/channel_dependency_graph.cpp +++ b/vpr/src/noc/channel_dependency_graph.cpp @@ -125,4 +125,4 @@ bool ChannelDependencyGraph::has_cycles() { // if no vertex in the graph points to at least one of its ancestors, the graph does not have any cycles return false; -} \ No newline at end of file +} diff --git a/vpr/src/noc/negative_first_routing.cpp b/vpr/src/noc/negative_first_routing.cpp index e45df009122..30098587dff 100644 --- a/vpr/src/noc/negative_first_routing.cpp +++ b/vpr/src/noc/negative_first_routing.cpp @@ -74,9 +74,9 @@ const std::vector& NegativeFirstRouting::get_legal_ bool NegativeFirstRouting::is_turn_legal(const std::array, 3>& noc_routers, const NocStorage& noc_model) const { - const auto[x1, y1, z1] = noc_routers[0].get().get_router_physical_location(); - const auto[x2, y2, z2] = noc_routers[1].get().get_router_physical_location(); - const auto[x3, y3, z3] = noc_routers[2].get().get_router_physical_location(); + const auto [x1, y1, z1] = noc_routers[0].get().get_router_physical_location(); + const auto [x2, y2, z2] = noc_routers[1].get().get_router_physical_location(); + const auto [x3, y3, z3] = noc_routers[2].get().get_router_physical_location(); // check if the given routers can be traversed one after another VTR_ASSERT(vtr::exactly_k_conditions(2, x1 == x2, y1 == y2, z1 == z2)); @@ -89,8 +89,7 @@ bool NegativeFirstRouting::is_turn_legal(const std::array x1 && y3 < y2) || (y2 > y1 && x3 < x2) || (z2 > z1 && x3 < x2) || - (x2 > x1 && z3 < z2) || (z2 > z1 && y3 < y2) || (y2 > y1 && z3 < z2)) { + if ((x2 > x1 && y3 < y2) || (y2 > y1 && x3 < x2) || (z2 > z1 && x3 < x2) || (x2 > x1 && z3 < z2) || (z2 > z1 && y3 < y2) || (y2 > y1 && z3 < z2)) { return false; } } else { diff --git a/vpr/src/noc/noc_data_types.h b/vpr/src/noc/noc_data_types.h index 6317db4ae09..85752445245 100644 --- a/vpr/src/noc/noc_data_types.h +++ b/vpr/src/noc/noc_data_types.h @@ -28,4 +28,4 @@ typedef vtr::StrongId NocTrafficFlowId; struct noc_group_id_tag; typedef vtr::StrongId NocGroupId; -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/noc_link.cpp b/vpr/src/noc/noc_link.cpp index f272023dbfc..8175964dc21 100644 --- a/vpr/src/noc/noc_link.cpp +++ b/vpr/src/noc/noc_link.cpp @@ -1,13 +1,12 @@ #include "noc_link.h" // constructor -NocLink::NocLink(NocLinkId link_id, NocRouterId source, NocRouterId sink, - double bw, double lat) +NocLink::NocLink(NocLinkId link_id, NocRouterId source, NocRouterId sink, double bw, double lat) : id(link_id) , source_router(source) , sink_router(sink) , bandwidth(bw) - , latency(lat) { } + , latency(lat) {} // getters NocRouterId NocLink::get_source_router() const { @@ -46,4 +45,3 @@ NocLinkId NocLink::get_link_id() const { NocLink::operator NocLinkId() const { return get_link_id(); } - diff --git a/vpr/src/noc/noc_link.h b/vpr/src/noc/noc_link.h index 3f56e763726..ba7ba01fbba 100644 --- a/vpr/src/noc/noc_link.h +++ b/vpr/src/noc/noc_link.h @@ -50,11 +50,10 @@ class NocLink { NocRouterId sink_router; /*!< The router which uses this link as an incoming edge*/ double bandwidth; /*!< Represents the maximum bits per second that can be transmitted over the link without causing congestion*/ - double latency; /*!< The zero-load latency of this link in seconds.*/ + double latency; /*!< The zero-load latency of this link in seconds.*/ public: - NocLink(NocLinkId link_id, NocRouterId source_router, NocRouterId sink_router, - double bw, double lat); + NocLink(NocLinkId link_id, NocRouterId source_router, NocRouterId sink_router, double bw, double lat); // getters @@ -122,4 +121,4 @@ class NocLink { operator NocLinkId() const; }; -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/noc_router.cpp b/vpr/src/noc/noc_router.cpp index 4af296c02ef..d2b18ec6b40 100644 --- a/vpr/src/noc/noc_router.cpp +++ b/vpr/src/noc/noc_router.cpp @@ -2,13 +2,15 @@ // constructor NocRouter::NocRouter(int id, - int grid_position_x, int grid_position_y, int layer_position, + int grid_position_x, + int grid_position_y, + int layer_position, double latency) : router_user_id(id) , router_grid_position_x(grid_position_x) , router_grid_position_y(grid_position_y) , router_layer_position(layer_position) - , router_latency(latency){ + , router_latency(latency) { // initialize variables router_block_ref = ClusterBlockId(0); } @@ -45,4 +47,4 @@ ClusterBlockId NocRouter::get_router_block_ref() const { // setters void NocRouter::set_router_block_ref(ClusterBlockId router_block_ref_id) { router_block_ref = router_block_ref_id; -} \ No newline at end of file +} diff --git a/vpr/src/noc/noc_router.h b/vpr/src/noc/noc_router.h index 968ff5206b7..e7a2b04ab0e 100644 --- a/vpr/src/noc/noc_router.h +++ b/vpr/src/noc/noc_router.h @@ -62,7 +62,9 @@ class NocRouter { public: NocRouter(int id, - int grid_position_x, int grid_position_y, int layer_position, + int grid_position_x, + int grid_position_y, + int layer_position, double latency); // getters @@ -117,4 +119,4 @@ class NocRouter { void set_router_block_ref(ClusterBlockId router_block_ref_id); }; -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/noc_routing_algorithm_creator.cpp b/vpr/src/noc/noc_routing_algorithm_creator.cpp index e52be823ae3..15cbbf5bbfb 100644 --- a/vpr/src/noc/noc_routing_algorithm_creator.cpp +++ b/vpr/src/noc/noc_routing_algorithm_creator.cpp @@ -8,7 +8,6 @@ #include "odd_even_routing.h" #include "vpr_error.h" - std::unique_ptr NocRoutingAlgorithmCreator::create_routing_algorithm(const std::string& routing_algorithm_name, const NocStorage& noc_model) { std::unique_ptr noc_routing_algorithm; @@ -30,4 +29,4 @@ std::unique_ptr NocRoutingAlgorithmCreator::create_routing_algorithm } return noc_routing_algorithm; -} \ No newline at end of file +} diff --git a/vpr/src/noc/noc_routing_algorithm_creator.h b/vpr/src/noc/noc_routing_algorithm_creator.h index 8cb9b777949..4c33d13f590 100644 --- a/vpr/src/noc/noc_routing_algorithm_creator.h +++ b/vpr/src/noc/noc_routing_algorithm_creator.h @@ -8,9 +8,10 @@ * * Overview * ======== - * There are a number of different available NoC routing algorithms. This class is a factory object for the NocRouting abstract class. This class constructs - * the appropriate routing algorithm based on the user specification in the - * command line. The user identifies a + * There are a number of different available NoC routing algorithms. + * This class is a factory object for the NocRouting abstract class. + * This class constructs the appropriate routing algorithm based on + * the user specification in the command line. The user identifies a * specific routing algorithm in the command line by providing a string * (which is the name of routing algorithm). * Then the corresponding routing algorithm is created here based on the diff --git a/vpr/src/noc/noc_storage.cpp b/vpr/src/noc/noc_storage.cpp index 58e79d46b03..4cf62e8b173 100644 --- a/vpr/src/noc/noc_storage.cpp +++ b/vpr/src/noc/noc_storage.cpp @@ -3,7 +3,6 @@ #include "vtr_assert.h" #include "vpr_error.h" - #include NocStorage::NocStorage() { @@ -106,7 +105,9 @@ bool NocStorage::is_noc_3d() const { // setters for the NoC void NocStorage::add_router(int id, - int grid_position_x, int grid_position_y, int layer_position, + int grid_position_x, + int grid_position_y, + int layer_position, double latency) { VTR_ASSERT_MSG(!built_noc, "NoC already built, cannot modify further."); @@ -183,9 +184,9 @@ bool NocStorage::remove_link(NocRouterId src_router_id, NocRouterId sink_router_ if (it == source_router_outgoing_links.end()) { VTR_LOG_WARN("No link could be found among outgoing links of source router with id(%d) " - "that that connects to the sink router with id (%d).\n", - (size_t)src_router_id, - (size_t)sink_router_id); + "that that connects to the sink router with id (%d).\n", + (size_t)src_router_id, + (size_t)sink_router_id); } source_router_outgoing_links.erase(it, source_router_outgoing_links.end()); @@ -196,9 +197,9 @@ bool NocStorage::remove_link(NocRouterId src_router_id, NocRouterId sink_router_ if (it == sink_router_incoming_links.end()) { VTR_LOG_WARN("No link could be found among incoming links of sink router with id(%d) " - "that that connects to the source router with id (%d).\n", - (size_t)sink_router_id, - (size_t)src_router_id); + "that that connects to the source router with id (%d).\n", + (size_t)sink_router_id, + (size_t)src_router_id); } sink_router_incoming_links.erase(it, sink_router_incoming_links.end()); @@ -256,6 +257,7 @@ void NocStorage::clear_noc() { link_storage.clear(); router_outgoing_links_list.clear(); router_incoming_links_list.clear(); + router_id_conversion_table.clear(); grid_location_to_router_id.clear(); built_noc = false; diff --git a/vpr/src/noc/noc_storage.h b/vpr/src/noc/noc_storage.h index 89dcf87bbac..deabfd27853 100644 --- a/vpr/src/noc/noc_storage.h +++ b/vpr/src/noc/noc_storage.h @@ -317,10 +317,9 @@ class NocStorage { * requested NoC links * @return A const */ - template class Container, typename... Ts> + template class Container, typename... Ts> const std::vector>& get_noc_links(const Container& noc_link_ids) const; - /** * @brief Given source and sink router identifiers, this function * finds a link connecting these routers and returns its identifier. @@ -385,7 +384,9 @@ class NocStorage { * when it is routed through this router. */ void add_router(int id, - int grid_position_x, int grid_position_y, int layer_position, + int grid_position_x, + int grid_position_y, + int layer_position, double latency); /** @@ -560,8 +561,7 @@ class NocStorage { void echo_noc(char* file_name) const; }; - -template class Container, typename... Ts> +template class Container, typename... Ts> const std::vector>& NocStorage::get_noc_links(const Container& noc_link_ids) const { returnable_noc_link_const_refs_.clear(); @@ -574,4 +574,3 @@ const std::vector>& NocStorage::get_noc_li } #endif - diff --git a/vpr/src/noc/noc_traffic_flows.cpp b/vpr/src/noc/noc_traffic_flows.cpp index 310eacd2f16..b0d7cfe1b46 100644 --- a/vpr/src/noc/noc_traffic_flows.cpp +++ b/vpr/src/noc/noc_traffic_flows.cpp @@ -49,7 +49,6 @@ const vtr::vector& NocTrafficFlows::get_al return noc_traffic_flows; } - // setters for the traffic flows void NocTrafficFlows::create_noc_traffic_flow(const std::string& source_router_module_name, @@ -189,4 +188,3 @@ void NocTrafficFlows::echo_noc_traffic_flows(char* file_name) { vtr::fclose(fp); } - diff --git a/vpr/src/noc/noc_traffic_flows.h b/vpr/src/noc/noc_traffic_flows.h index 53aa62709a3..a05a2e37696 100644 --- a/vpr/src/noc/noc_traffic_flows.h +++ b/vpr/src/noc/noc_traffic_flows.h @@ -68,7 +68,13 @@ struct t_noc_traffic_flow { int traffic_flow_priority; /** Constructor initializes all variables*/ - t_noc_traffic_flow(std::string source_router_name, std::string sink_router_name, ClusterBlockId source_router_id, ClusterBlockId sink_router_id, double flow_bandwidth, double max_flow_latency, int flow_priority) + t_noc_traffic_flow(std::string source_router_name, + std::string sink_router_name, + ClusterBlockId source_router_id, + ClusterBlockId sink_router_id, + double flow_bandwidth, + double max_flow_latency, + int flow_priority) noexcept : source_router_module_name(std::move(source_router_name)) , sink_router_module_name(std::move(sink_router_name)) , source_router_cluster_id(source_router_id) @@ -295,7 +301,6 @@ class NocTrafficFlows { */ void echo_noc_traffic_flows(char* file_name); - /** * @brief Defines the latency constraint of a traffic flow * when not provided by the user. @@ -310,4 +315,4 @@ class NocTrafficFlows { static constexpr double DEFAULT_MAX_TRAFFIC_FLOW_LATENCY = 1.; }; -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/north_last_routing.cpp b/vpr/src/noc/north_last_routing.cpp index fd3c1183201..82b1bd4b7f5 100644 --- a/vpr/src/noc/north_last_routing.cpp +++ b/vpr/src/noc/north_last_routing.cpp @@ -72,7 +72,6 @@ bool NorthLastRouting::is_turn_legal(const std::array z1 && x3 < x2) || (z2 > z1 && x3 > x2) || (z2 > z1 && y3 < y2) || - (y2 > y1 && z3 < z2) || (y2 > y1 && x3 < x2) || (y2 > y1 && x3 > x2)) { + if ((z2 > z1 && x3 < x2) || (z2 > z1 && x3 > x2) || (z2 > z1 && y3 < y2) || (y2 > y1 && z3 < z2) || (y2 > y1 && x3 < x2) || (y2 > y1 && x3 > x2)) { return false; } } else { @@ -90,6 +88,5 @@ bool NorthLastRouting::is_turn_legal(const std::array& OddEvenRouting::get_legal_direct if (noc_model.is_noc_3d()) { determine_legal_directions_3d(compressed_src_loc, compressed_curr_loc, compressed_dst_loc, prev_dir); - } else { // 2D NoC + } else { // 2D NoC determine_legal_directions_2d(compressed_src_loc, compressed_curr_loc, compressed_dst_loc, prev_dir); } @@ -120,7 +120,6 @@ bool OddEvenRouting::is_turn_legal(const std::array z1 && y3 < y2) || (z2 < z1 && y3 < y2)) { @@ -131,7 +130,7 @@ bool OddEvenRouting::is_turn_legal(const std::array 0) { diff --git a/vpr/src/noc/odd_even_routing.h b/vpr/src/noc/odd_even_routing.h index ce84c74c264..da61c5f3e9b 100644 --- a/vpr/src/noc/odd_even_routing.h +++ b/vpr/src/noc/odd_even_routing.h @@ -25,7 +25,6 @@ class OddEvenRouting : public TurnModelRouting { ~OddEvenRouting() override; private: - const std::vector& get_legal_directions(NocRouterId src_router_id, NocRouterId curr_router_id, NocRouterId dst_router_id, diff --git a/vpr/src/noc/read_xml_noc_traffic_flows_file.cpp b/vpr/src/noc/read_xml_noc_traffic_flows_file.cpp index 3f12c02ed2d..6b3df6c7ad9 100644 --- a/vpr/src/noc/read_xml_noc_traffic_flows_file.cpp +++ b/vpr/src/noc/read_xml_noc_traffic_flows_file.cpp @@ -1,5 +1,6 @@ #include "read_xml_noc_traffic_flows_file.h" +#include "physical_types_util.h" void read_xml_noc_traffic_flows_file(const char* noc_flows_file) { // start by checking that the provided file is a ".flows" file @@ -274,7 +275,7 @@ bool check_that_all_router_blocks_have_an_associated_traffic_flow(NocContext& no /* * Go through the router subtiles and get the router logical block types the subtiles support. Then determine how many of each router logical block types there are in the clustered netlist. The accumulated sum of all these clusters is the total number of router blocks in the design. */ - for (const auto & noc_router_subtile : *noc_router_subtiles) { + for (const auto& noc_router_subtile : *noc_router_subtiles) { for (auto router_logical_block : noc_router_subtile.equivalent_sites) { // get the number of logical blocks in the design of the current logical block type number_of_router_blocks_in_design += clustered_netlist_stats.num_blocks_type[router_logical_block->index]; @@ -316,4 +317,4 @@ std::vector get_cluster_blocks_compatible_with_noc_router_tiles( } return cluster_blocks_compatible_with_noc_router_tiles; -} \ No newline at end of file +} diff --git a/vpr/src/noc/read_xml_noc_traffic_flows_file.h b/vpr/src/noc/read_xml_noc_traffic_flows_file.h index 2d8b348ad71..b53a0e432be 100644 --- a/vpr/src/noc/read_xml_noc_traffic_flows_file.h +++ b/vpr/src/noc/read_xml_noc_traffic_flows_file.h @@ -257,4 +257,4 @@ bool check_that_all_router_blocks_have_an_associated_traffic_flow(NocContext& no */ std::vector get_cluster_blocks_compatible_with_noc_router_tiles(const ClusteringContext& cluster_ctx, t_physical_tile_type_ptr noc_router_tile_type); -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/sat_routing.cpp b/vpr/src/noc/sat_routing.cpp index 354620c6cfa..0ccf1426720 100644 --- a/vpr/src/noc/sat_routing.cpp +++ b/vpr/src/noc/sat_routing.cpp @@ -1,6 +1,5 @@ #ifdef ENABLE_NOC_SAT_ROUTING - #include "sat_routing.h" #include "turn_model_routing.h" @@ -22,7 +21,6 @@ namespace orsat = operations_research::sat; */ typedef std::unordered_map, orsat::BoolVar> t_flow_link_var_map; - /** * @brief Creates a boolean variable for each (traffic flow, link) pair. * It also create integer variables for latency-constrained traffic flows. @@ -38,7 +36,7 @@ typedef std::unordered_map, orsat::BoolVa */ static void create_flow_link_vars(orsat::CpModelBuilder& cp_model, t_flow_link_var_map& flow_link_vars, - std::map& latency_overrun_vars); + std::map& latency_overrun_vars); /** * @brief Translates a latency constraint for a traffic flow to the maximum number @@ -84,7 +82,7 @@ static std::vector get_flow_link_vars(const t_flow_link_var_map& */ static void constrain_latency_overrun_vars(orsat::CpModelBuilder& cp_model, t_flow_link_var_map& flow_link_vars, - std::map& latency_overrun_vars); + std::map& latency_overrun_vars); /** * @brief Forbids specific turns that traffic flows can take. @@ -118,7 +116,7 @@ static void forbid_illegal_turns(t_flow_link_var_map& flow_link_vars, * @param bandwidth_resolution Specifies the resolution by which bandwidth * values are quantized. */ -static void create_congested_link_vars(vtr::vector& congested_link_vars, +static void create_congested_link_vars(vtr::vector& congested_link_vars, t_flow_link_var_map& flow_link_vars, orsat::CpModelBuilder& cp_model, int bandwidth_resolution); @@ -172,8 +170,8 @@ static void add_continuity_constraints(t_flow_link_var_map& flow_link_vars, */ static orsat::LinearExpr create_objective(orsat::CpModelBuilder& cp_model, t_flow_link_var_map& flow_link_vars, - std::map& latency_overrun_vars, - vtr::vector& congested_link_vars, + std::map& latency_overrun_vars, + vtr::vector& congested_link_vars, int bandwidth_resolution, int latency_overrun_weight, int congestion_weight, @@ -211,7 +209,6 @@ static vtr::vector> convert_vars_to_rou */ static std::vector sort_noc_links_in_chain_order(const std::vector& links); - static std::vector get_flow_link_vars(const t_flow_link_var_map& map, const std::vector& traffic_flow_ids, const std::vector& noc_link_ids) { @@ -233,7 +230,7 @@ static void forbid_illegal_turns(t_flow_link_var_map& flow_link_vars, const auto& noc_ctx = g_vpr_ctx.noc(); const auto& traffic_flow_storage = noc_ctx.noc_traffic_flows_storage; - auto noc_routing_alg = dynamic_cast (noc_ctx.noc_flows_router.get()); + auto noc_routing_alg = dynamic_cast(noc_ctx.noc_flows_router.get()); // ensure that the routing algorithm is a turn model algorithm VTR_ASSERT(noc_routing_alg != nullptr); @@ -256,7 +253,7 @@ static vtr::vector quantize_traffic_flow_bandwidths(int b //TODO: support heterogeneous bandwidth const auto& noc_links = noc_ctx.noc_model.get_noc_links(); const double link_bandwidth = noc_links.front().get_bandwidth(); - auto it = std::adjacent_find(noc_links.begin(), noc_links.end(), [](const NocLink& a, const NocLink& b){ + auto it = std::adjacent_find(noc_links.begin(), noc_links.end(), [](const NocLink& a, const NocLink& b) { return a.get_bandwidth() != b.get_bandwidth(); }); @@ -281,10 +278,10 @@ static vtr::vector quantize_traffic_flow_bandwidths(int b rescaled_traffic_flow_bandwidths[traffic_flow_id] = rescaled_bandwidth; } - return rescaled_traffic_flow_bandwidths; + return rescaled_traffic_flow_bandwidths; } -static void create_congested_link_vars(vtr::vector& congested_link_vars, +static void create_congested_link_vars(vtr::vector& congested_link_vars, t_flow_link_var_map& flow_link_vars, orsat::CpModelBuilder& cp_model, int bandwidth_resolution) { @@ -351,7 +348,6 @@ static void add_continuity_constraints(t_flow_link_var_map& flow_link_vars, continue; } - // for each intermediate router, at most one incoming link can be activated to route this traffic flow const auto& incoming_links = noc_ctx.noc_model.get_noc_router_incoming_links(noc_router_id); auto incoming_vars = get_flow_link_vars(flow_link_vars, {traffic_flow_id}, incoming_links); @@ -386,8 +382,8 @@ static std::vector sort_noc_links_in_chain_order(const std::vector src_map; - std::unordered_map is_dst; + std::unordered_map src_map; + std::unordered_map is_dst; for (const auto l : links) { NocRouterId src_router_id = noc_model.get_single_noc_link(l).get_source_router(); NocRouterId dst_router_id = noc_model.get_single_noc_link(l).get_sink_router(); @@ -426,8 +422,7 @@ static vtr::vector> convert_vars_to_rou const auto& noc_ctx = g_vpr_ctx.noc(); const auto& traffic_flow_storage = noc_ctx.noc_traffic_flows_storage; - VTR_ASSERT(response.status() == orsat::CpSolverStatus::FEASIBLE || - response.status() == orsat::CpSolverStatus::OPTIMAL); + VTR_ASSERT(response.status() == orsat::CpSolverStatus::FEASIBLE || response.status() == orsat::CpSolverStatus::OPTIMAL); vtr::vector> routes; routes.resize(traffic_flow_storage.get_number_of_traffic_flows()); @@ -449,7 +444,7 @@ static vtr::vector> convert_vars_to_rou static void create_flow_link_vars(orsat::CpModelBuilder& cp_model, t_flow_link_var_map& flow_link_vars, - std::map& latency_overrun_vars) { + std::map& latency_overrun_vars) { const auto& noc_ctx = g_vpr_ctx.noc(); const auto& noc_model = noc_ctx.noc_model; const auto& traffic_flow_storage = noc_ctx.noc_traffic_flows_storage; @@ -467,12 +462,14 @@ static void create_flow_link_vars(orsat::CpModelBuilder& cp_model, size_t max_n_cols = std::max_element(compressed_noc_grid.compressed_to_grid_x.begin(), compressed_noc_grid.compressed_to_grid_x.end(), [](const std::vector& a, const std::vector& b) { return a.size() < b.size(); - })->size(); + }) + ->size(); size_t max_n_rows = std::max_element(compressed_noc_grid.compressed_to_grid_y.begin(), compressed_noc_grid.compressed_to_grid_y.end(), [](const std::vector& a, const std::vector& b) { return a.size() < b.size(); - })->size(); + }) + ->size(); /* For specifying the domain, assume that the longest traffic flow route starts from * one corner and terminates at the opposite corner. Assuming minimal routing, such a @@ -523,7 +520,7 @@ static int comp_max_number_of_traversed_links(NocTrafficFlowId traffic_flow_id) } auto link_it = std::find_if(noc_links.begin(), noc_links.end(), [noc_link_latency](const NocLink& l) { - return (noc_link_latency != l.get_latency()); + return (noc_link_latency != l.get_latency()); }); if (link_it != noc_links.end()) { @@ -544,7 +541,7 @@ static int comp_max_number_of_traversed_links(NocTrafficFlowId traffic_flow_id) static void constrain_latency_overrun_vars(orsat::CpModelBuilder& cp_model, t_flow_link_var_map& flow_link_vars, - std::map& latency_overrun_vars) { + std::map& latency_overrun_vars) { const auto& noc_ctx = g_vpr_ctx.noc(); const auto& noc_model = noc_ctx.noc_model; @@ -569,8 +566,8 @@ static void constrain_latency_overrun_vars(orsat::CpModelBuilder& cp_model, static orsat::LinearExpr create_objective(orsat::CpModelBuilder& cp_model, t_flow_link_var_map& flow_link_vars, - std::map& latency_overrun_vars, - vtr::vector& congested_link_vars, + std::map& latency_overrun_vars, + vtr::vector& congested_link_vars, int bandwidth_resolution, int latency_overrun_weight, int congestion_weight, @@ -603,7 +600,6 @@ static orsat::LinearExpr create_objective(orsat::CpModelBuilder& cp_model, agg_bw_expr = 0; } - orsat::LinearExpr congested_link_sum = orsat::LinearExpr::Sum(congested_link_vars); congested_link_sum *= congestion_weight; @@ -611,7 +607,6 @@ static orsat::LinearExpr create_objective(orsat::CpModelBuilder& cp_model, return objective; } - vtr::vector> noc_sat_route(bool minimize_aggregate_bandwidth, const t_noc_opts& noc_opts, int seed) { @@ -666,8 +661,7 @@ vtr::vector> noc_sat_route(bool minimiz orsat::CpSolverResponse response = orsat::SolveCpModel(cp_model.Build(), &model); - if (response.status() == orsat::CpSolverStatus::FEASIBLE || - response.status() == orsat::CpSolverStatus::OPTIMAL) { + if (response.status() == orsat::CpSolverStatus::FEASIBLE || response.status() == orsat::CpSolverStatus::OPTIMAL) { auto routes = convert_vars_to_routes(flow_link_vars, response); return routes; } @@ -676,4 +670,4 @@ vtr::vector> noc_sat_route(bool minimiz return {}; } -#endif //ENABLE_NOC_SAT_ROUTING \ No newline at end of file +#endif //ENABLE_NOC_SAT_ROUTING diff --git a/vpr/src/noc/sat_routing.h b/vpr/src/noc/sat_routing.h index 945b5a0aabe..60f9a900fb0 100644 --- a/vpr/src/noc/sat_routing.h +++ b/vpr/src/noc/sat_routing.h @@ -66,6 +66,5 @@ struct hash> { }; } // namespace std - #endif -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/turn_model_routing.cpp b/vpr/src/noc/turn_model_routing.cpp index d9b169a0896..398af104844 100644 --- a/vpr/src/noc/turn_model_routing.cpp +++ b/vpr/src/noc/turn_model_routing.cpp @@ -78,12 +78,12 @@ void TurnModelRouting::route_flow(NocRouterId src_router_id, flow_route.push_back(next_link); prev_dir = next_step_direction; } else { - VPR_FATAL_ERROR(VPR_ERROR_OTHER, "No route could be found from starting router with ID:'%d' " + VPR_FATAL_ERROR(VPR_ERROR_OTHER, + "No route could be found from starting router with ID:'%d' " "and the destination router with ID:'%d' using the XY-Routing algorithm.", src_router.get_router_user_id(), dst_router.get_router_user_id()); } - } } @@ -200,7 +200,7 @@ uint32_t TurnModelRouting::murmur3_32(const std::vector& key, uint32_t // A swap is *not* necessary here because the preceding loop already // places the low bytes in the low places according to whatever endianness // we use. Swaps only apply when the memory is copied in a chunk. -// h ^= murmur_32_scramble(0); + // h ^= murmur_32_scramble(0); /* Finalize. */ h ^= key.size() * 4; h ^= h >> 16; @@ -325,7 +325,6 @@ TurnModelRouting::Direction TurnModelRouting::select_next_direction(const std::v int hash_val_remainder = hash_val % manhattan_dist; - TurnModelRouting::Direction selected_direction = TurnModelRouting::Direction::INVALID; if (hash_val_remainder < delta_x) { diff --git a/vpr/src/noc/turn_model_routing.h b/vpr/src/noc/turn_model_routing.h index ce061a56eed..7263c3d813d 100644 --- a/vpr/src/noc/turn_model_routing.h +++ b/vpr/src/noc/turn_model_routing.h @@ -122,14 +122,14 @@ class TurnModelRouting : public NocRouting { * choose to travel. */ enum class Direction { - WEST, /*!< Moving towards the negative X-axis*/ - EAST, /*!< Moving towards the positive X-axis*/ - NORTH, /*!< Moving towards the positive Y-axis*/ - SOUTH, /*!< Moving towards the negative Y-axis*/ - UP, /*!< Moving towards the positive Z-axis*/ - DOWN, /*!< Moving towards the negative Z-axis*/ + WEST, /*!< Moving towards the negative X-axis*/ + EAST, /*!< Moving towards the positive X-axis*/ + NORTH, /*!< Moving towards the positive Y-axis*/ + SOUTH, /*!< Moving towards the negative Y-axis*/ + UP, /*!< Moving towards the positive Z-axis*/ + DOWN, /*!< Moving towards the negative Z-axis*/ N_DIRECTIONS, - INVALID /*!< Invalid direction*/ + INVALID /*!< Invalid direction*/ }; /** @@ -209,7 +209,6 @@ class TurnModelRouting : public NocRouting { std::unordered_set& visited_routers, const NocStorage& noc_model); - /** * @brief Computes MurmurHash3 for an array of 32-bit words initialized * with seed. As discussed in the comment at the top of this file, @@ -274,7 +273,6 @@ class TurnModelRouting : public NocRouting { private: std::vector inputs_to_murmur3_hasher{4}; - }; #endif //VTR_TURN_MODEL_ROUTING_H diff --git a/vpr/src/noc/west_first_routing.cpp b/vpr/src/noc/west_first_routing.cpp index 95853c7e0c0..c47bfbf1456 100644 --- a/vpr/src/noc/west_first_routing.cpp +++ b/vpr/src/noc/west_first_routing.cpp @@ -48,10 +48,10 @@ const std::vector& WestFirstRouting::get_legal_dire returned_legal_direction.push_back(TurnModelRouting::Direction::DOWN); } } - } else { // 2D NoC + } else { // 2D NoC if (dst_router_pos.x < curr_router_pos.x) { returned_legal_direction.push_back(TurnModelRouting::Direction::WEST); - } else { // to the east or the same column + } else { // to the east or the same column if (dst_router_pos.x > curr_router_pos.x) { // not the same column returned_legal_direction.push_back(TurnModelRouting::Direction::EAST); } @@ -82,13 +82,11 @@ bool WestFirstRouting::is_turn_legal(const std::array z1 && x3 < x2) || (z2 < z1 && x3 < x2) || (z2 > z1 && y3 < y2) || - (z2 < z1 && y3 < y2) || (y2 > y1 && x3 < x2) || (x2 > x1 && y3 > y2)) { + if ((z2 > z1 && x3 < x2) || (z2 < z1 && x3 < x2) || (z2 > z1 && y3 < y2) || (z2 < z1 && y3 < y2) || (y2 > y1 && x3 < x2) || (x2 > x1 && y3 > y2)) { return false; } - } else { // 2D NoC + } else { // 2D NoC /* In the west-first routing algorithm, once the traffic flow * moved in a vertical direction, it is no longer allowed to move * towards west. Therefore, if the first link was travelling in a @@ -99,6 +97,5 @@ bool WestFirstRouting::is_turn_legal(const std::array& XYRouting::get_legal_directions( * the current router has the same x-coordinate as the * destination. Then we start moving along the y-axis. * Finally, we move along the z-axis. - */ + */ if (dst_router_pos.x > curr_router_pos.x) { return east_direction; @@ -82,4 +82,4 @@ bool XYRouting::is_turn_legal(const std::array east_direction{TurnModelRouting::Direction::EAST}; - const std::vector west_direction {TurnModelRouting::Direction::WEST}; - const std::vector north_direction {TurnModelRouting::Direction::NORTH}; - const std::vector south_direction {TurnModelRouting::Direction::SOUTH}; - const std::vector up_direction {TurnModelRouting::Direction::UP}; - const std::vector down_direction {TurnModelRouting::Direction::DOWN}; - const std::vector no_direction {}; - + const std::vector west_direction{TurnModelRouting::Direction::WEST}; + const std::vector north_direction{TurnModelRouting::Direction::NORTH}; + const std::vector south_direction{TurnModelRouting::Direction::SOUTH}; + const std::vector up_direction{TurnModelRouting::Direction::UP}; + const std::vector down_direction{TurnModelRouting::Direction::DOWN}; + const std::vector no_direction{}; }; -#endif \ No newline at end of file +#endif diff --git a/vpr/src/pack/appack_context.h b/vpr/src/pack/appack_context.h new file mode 100644 index 00000000000..0461f26b320 --- /dev/null +++ b/vpr/src/pack/appack_context.h @@ -0,0 +1,160 @@ +/** + * @file + * @author Alex Siner + * @date March 2025 + * @brief Declaration of the APPack Context object which stores all the + * information used to configure APPack in the packer. + */ + +#pragma once + +#include +#include +#include "device_grid.h" +#include "flat_placement_types.h" +#include "physical_types.h" +#include "vpr_context.h" +#include "vpr_utils.h" + +/** + * @brief Configuration options for APPack. + * + * APPack is an upgrade to the AAPack algorithm which uses an atom-level placement + * to inform the packer into creating better clusters. These options configure + * how APPack interprets the flat placement information. + */ +struct t_appack_options { + // Constructor for the appack options. + t_appack_options(const FlatPlacementInfo& flat_placement_info, + const DeviceGrid& device_grid) { + // If the flat placement info is valid, we want to use APPack. + // TODO: Should probably check that all the information is valid here. + use_appack = flat_placement_info.valid; + + // Set the max candidate distance as being some fraction of the longest + // distance on the device (from the bottom corner to the top corner). + // We also use an offset for the minimum this distance can be to prevent + // small devices from finding candidates. + float max_candidate_distance_scale = 0.1f; + float max_candidate_distance_offset = 15.0f; + // Longest L1 distance on the device. + float longest_distance = device_grid.width() + device_grid.height(); + max_candidate_distance = std::max(max_candidate_distance_scale * longest_distance, + max_candidate_distance_offset); + + // Infer the logical block type in the architecture. This will be used + // for the max candidate distance optimization to use a more aggressive + // distance. + t_logical_block_type_ptr logic_block_type = infer_logic_block_type(device_grid); + if (logic_block_type != nullptr) + logic_block_type_index = logic_block_type->index; + } + + // Whether to use APPack or not. + // This is initialized in the constructor based on if the flat placement + // info is valid or not. + bool use_appack = false; + + // =========== Cluster location ======================================== // + // What is the location of the cluster being created relative to the + // molecules being packed into it. + enum class e_cl_loc_ty { + CENTROID, /**< The location of the cluster is the centroid of the molecules which have been packed into it. */ + SEED /**< The location of the cluster is the location of the first molecule packed into it. */ + }; + static constexpr e_cl_loc_ty cluster_location_ty = e_cl_loc_ty::CENTROID; + + // =========== Candidate gain attenuation ============================== // + // These terms are used to update the gain of a given candidate based on + // its distance (d) relative to the location of the cluster being constructed. + // gain_new = attenuation * gain_original + // We use the following gain attenuation function: + // attenuation = { 1 - (quad_fac * d)^2 if d < dist_th + // { 1 / sqrt(d - sqrt_offset) if d >= dist_th + // The numbers below were empirically found to work well. + + // Distance threshold which decides when to use quadratic decay or inverted + // sqrt decay. If the distance is less than this threshold, quadratic decay + // is used. Inverted sqrt is used otherwise. + static constexpr float dist_th = 1.75f; + // Attenuation value at the threshold. + static constexpr float attenuation_th = 0.35f; + + // Using the distance threshold and the attenuation value at that point, we + // can compute the other two terms. This is to keep the attenuation function + // smooth. + // Horizontal offset to the inverted sqrt decay. + static constexpr float sqrt_offset = dist_th - ((1.0f / attenuation_th) * (1.0f / attenuation_th)); + // Squared scaling factor for the quadratic decay term. + static constexpr float quad_fac_sqr = (1.0f - attenuation_th) / (dist_th * dist_th); + + // =========== Candidate selection distance ============================ // + // When selecting candidates, what distance from the cluster will we + // consider? Any candidate beyond this distance will not be proposed. + // This is set in the constructor. + // TODO: It may be a good idea to have max different distances for different + // types of molecules / clusters. For example, CLBs vs DSPs + float max_candidate_distance = std::numeric_limits::max(); + + // A scaling applied to the max candidate distance of all clusters that are + // not logic blocks. + static constexpr float max_candidate_distance_non_lb_scale = 3.5f; + + // TODO: This should be an option similar to the target pin utilization + // so we can specify the max distance per block type! + int logic_block_type_index = -1; + + // =========== Unrelated clustering ==================================== // + // After searching for candidates by connectivity and timing, the user may + // turn on unrelated clustering, which will allow molecules which are + // unrelated to the cluster being created to be attempted to be packed in. + // APPack uses flat placement information to decide which unrelated + // molecules to try. + + // APPack will search for unrelated molecules in the tile which contains + // the flat location of the cluster. It will then look farther out, tile + // by tile. This parameter is the maximum distance from the cluster's tile + // that APPack will search. Setting this to 0 would only allow APPack to + // search within the cluster's tile. Setting this to a higher number would + // allow APPack to search farther away; but may bring in molecules which + // do not "want" to be in the cluster. + static constexpr float max_unrelated_tile_distance = 5.0f; + + // Unrelated clustering occurs after all other candidate selection methods + // have failed. This parameter sets how many time we will attempt unrelated + // clustering between failures of unrelated clustering. If this is set to + // 1, and unrelated clustering failed for a cluster, it will not be attempted + // again for that cluster (note: if it succeeds, the number of attempts get + // reset). + // NOTE: A similar option exists in the candidate selector class. This was + // duplicated since it is very likely that APPack would need a + // different value for this option than the non-APPack flow. + static constexpr int max_unrelated_clustering_attempts = 10; + + // TODO: Investigate adding flat placement info to seed selection. +}; + +/** + * @brief State relating to APPack. + * + * This class is intended to contain information on using flat placement + * information in packing. + */ +struct APPackContext : public Context { + /** + * @brief Constructor for the APPack context. + */ + APPackContext(const FlatPlacementInfo& fplace_info, const DeviceGrid& device_grid) + : appack_options(fplace_info, device_grid) + , flat_placement_info(fplace_info) {} + + /** + * @brief Options used to configure APPack. + */ + t_appack_options appack_options; + + /** + * @brief The flat placement information passed into APPack. + */ + const FlatPlacementInfo& flat_placement_info; +}; diff --git a/vpr/src/pack/atom_pb_bimap.cpp b/vpr/src/pack/atom_pb_bimap.cpp new file mode 100644 index 00000000000..df837cfea6b --- /dev/null +++ b/vpr/src/pack/atom_pb_bimap.cpp @@ -0,0 +1,65 @@ +/** + * @file + * @author Amir Poolad + * @date March 2025 + * @brief The code for the AtomPBBimap class. + * + * This file implements the various functions of the AtomPBBimap class. + */ + +#include "atom_pb_bimap.h" +#include "atom_netlist.h" + +AtomPBBimap::AtomPBBimap(const vtr::bimap& atom_to_pb) { + atom_to_pb_ = atom_to_pb; +} + +const t_pb* AtomPBBimap::atom_pb(const AtomBlockId blk_id) const { + auto iter = atom_to_pb_.find(blk_id); + if (iter == atom_to_pb_.end()) { + //Not found + return nullptr; + } + return iter->second; +} + +AtomBlockId AtomPBBimap::pb_atom(const t_pb* pb) const { + auto iter = atom_to_pb_.find(pb); + if (iter == atom_to_pb_.inverse_end()) { + //Not found + return AtomBlockId::INVALID(); + } + return iter->second; +} + +const t_pb_graph_node* AtomPBBimap::atom_pb_graph_node(const AtomBlockId blk_id) const { + const t_pb* pb = atom_pb(blk_id); + if (pb) { + //Found + return pb->pb_graph_node; + } + return nullptr; +} + +void AtomPBBimap::set_atom_pb(const AtomBlockId blk_id, const t_pb* pb) { + //If either of blk_id or pb are not valid, + //remove any mapping + if (!blk_id && pb) { + //Remove + atom_to_pb_.erase(pb); + } else if (blk_id && !pb) { + //Remove + atom_to_pb_.erase(blk_id); + } else if (blk_id && pb) { + //If both are valid store the mapping + atom_to_pb_.update(blk_id, pb); + } +} + +void AtomPBBimap::reset_bimap() { + atom_to_pb_.clear(); +} + +bool AtomPBBimap::is_empty() const { + return atom_to_pb_.empty(); +} diff --git a/vpr/src/pack/atom_pb_bimap.h b/vpr/src/pack/atom_pb_bimap.h new file mode 100644 index 00000000000..d8623543910 --- /dev/null +++ b/vpr/src/pack/atom_pb_bimap.h @@ -0,0 +1,58 @@ +/** + * @file + * @author Amir Poolad + * @date March 2025 + * @brief The declaration of the AtomPBBimap class. + * + * This file declares a class called AtomPBBimap that + * contains a two way mapping between AtomBlockIds and pb types. + */ + +#pragma once + +#include "vpr_types.h" + +// Forward declaration +class t_pb_graph_node; + +/** + * @brief Class that holds a bimap between atoms and pb types. + * This means that you can get a pb from an atom and the + * other way around. + * + * Used in the global AtomLookup context and in ClusterLegalizer + */ +class AtomPBBimap { + public: + AtomPBBimap() = default; + AtomPBBimap(const vtr::bimap& atom_to_pb); + + /** + * @brief Returns the leaf pb associated with the atom blk_id + * @note this is the lowest level pb which corresponds directly to the atom block + */ + const t_pb* atom_pb(const AtomBlockId blk_id) const; + + ///@brief Returns the atom block id associated with pb + AtomBlockId pb_atom(const t_pb* pb) const; + + ///@brief Conveneince wrapper around atom_pb to access the associated graph node + const t_pb_graph_node* atom_pb_graph_node(const AtomBlockId blk_id) const; + + /** + * @brief Sets the bidirectional mapping between an atom and pb + * + * If either blk_id or pb are not valid any, existing mapping is removed + */ + void set_atom_pb(const AtomBlockId blk_id, const t_pb* pb); + + /// @brief Sets the pb for all blocks in the netlist to nullptr. + void reset_bimap(); + + /// @brief Returns if the bimap is empty + bool is_empty() const; + + private: + /// @brief Two way map between AtomBlockIds and t_pb + vtr::bimap atom_to_pb_; +}; diff --git a/vpr/src/pack/attraction_groups.cpp b/vpr/src/pack/attraction_groups.cpp index 8d151c6c6aa..caba76fecb9 100644 --- a/vpr/src/pack/attraction_groups.cpp +++ b/vpr/src/pack/attraction_groups.cpp @@ -7,7 +7,7 @@ AttractionInfo::AttractionInfo(bool attraction_groups_on) { int num_parts = floorplanning_ctx.constraints.get_num_partitions(); //Initialize every atom to have no attraction group id - int num_atoms = atom_ctx.nlist.blocks().size(); + int num_atoms = atom_ctx.netlist().blocks().size(); atom_attraction_group.resize(num_atoms); fill(atom_attraction_group.begin(), atom_attraction_group.end(), AttractGroupId::INVALID()); @@ -33,7 +33,7 @@ AttractionInfo::AttractionInfo(bool attraction_groups_on) { } } -void AttractionInfo::create_att_groups_for_overfull_regions() { +void AttractionInfo::create_att_groups_for_overfull_regions(const std::vector& overfull_partition_regions) { const auto& floorplanning_ctx = g_vpr_ctx.floorplanning(); auto& atom_ctx = g_vpr_ctx.atom(); int num_parts = floorplanning_ctx.constraints.get_num_partitions(); @@ -43,13 +43,11 @@ void AttractionInfo::create_att_groups_for_overfull_regions() { attraction_groups.clear(); //Initialize every atom to have no attraction group id - int num_atoms = atom_ctx.nlist.blocks().size(); + int num_atoms = atom_ctx.netlist().blocks().size(); atom_attraction_group.resize(num_atoms); fill(atom_attraction_group.begin(), atom_attraction_group.end(), AttractGroupId::INVALID()); - const std::vector& overfull_prs = floorplanning_ctx.overfull_partition_regions; - /* * Create an attraction group for each partition that overlaps with at least one overfull partition */ @@ -58,7 +56,7 @@ void AttractionInfo::create_att_groups_for_overfull_regions() { const Partition& part = floorplanning_ctx.constraints.get_partition(partid); - for (const PartitionRegion& overfull_pr : overfull_prs) { + for (const PartitionRegion& overfull_pr : overfull_partition_regions) { PartitionRegion intersect_pr = intersection(part.get_part_region(), overfull_pr); if (!intersect_pr.empty()) { AttractionGroup group_info; @@ -87,7 +85,7 @@ void AttractionInfo::create_att_groups_for_all_regions() { attraction_groups.clear(); //Initialize every atom to have no attraction group id - int num_atoms = atom_ctx.nlist.blocks().size(); + int num_atoms = atom_ctx.netlist().blocks().size(); atom_attraction_group.resize(num_atoms); fill(atom_attraction_group.begin(), atom_attraction_group.end(), AttractGroupId::INVALID()); diff --git a/vpr/src/pack/attraction_groups.h b/vpr/src/pack/attraction_groups.h index ae2409cf772..d0d79c721b6 100644 --- a/vpr/src/pack/attraction_groups.h +++ b/vpr/src/pack/attraction_groups.h @@ -12,6 +12,9 @@ #include "vtr_vector.h" #include "atom_netlist_fwd.h" +// Forward declarations +class PartitionRegion; + /** * @file * @brief This file defines the AttractionInfo class, which is used to store atoms in attraction groups, which are @@ -53,7 +56,7 @@ class AttractionInfo { * Create attraction groups for the partitions that contain overfull regions (i.e. * The region has more blocks of a certain type assigned to than are actually available). */ - void create_att_groups_for_overfull_regions(); + void create_att_groups_for_overfull_regions(const std::vector& overfull_partition_regions); /* * Create attraction groups for all partitions. diff --git a/vpr/src/pack/cluster_feasibility_filter.cpp b/vpr/src/pack/cluster_feasibility_filter.cpp index c8ecb987f00..dec597aa41e 100644 --- a/vpr/src/pack/cluster_feasibility_filter.cpp +++ b/vpr/src/pack/cluster_feasibility_filter.cpp @@ -333,16 +333,14 @@ static void expand_pb_graph_node_and_load_output_to_input_connections(t_pb_graph reference_pin->list_of_connectable_input_pin_ptrs[depth][i] = temp[i]; reference_pin->list_of_connectable_input_pin_ptrs[depth][reference_pin->num_connectable_primitive_input_pins[depth] - - 1] - = current_pb_graph_pin; + - 1] = current_pb_graph_pin; } else { reference_pin->list_of_connectable_input_pin_ptrs[depth] = new t_pb_graph_pin*[reference_pin->num_connectable_primitive_input_pins[depth]]; } reference_pin->list_of_connectable_input_pin_ptrs[depth][reference_pin->num_connectable_primitive_input_pins[depth] - - 1] - = current_pb_graph_pin; + - 1] = current_pb_graph_pin; } } } diff --git a/vpr/src/pack/cluster_legalizer.cpp b/vpr/src/pack/cluster_legalizer.cpp index 399b0e271cc..282b0fe8d1c 100644 --- a/vpr/src/pack/cluster_legalizer.cpp +++ b/vpr/src/pack/cluster_legalizer.cpp @@ -17,6 +17,7 @@ #include #include "atom_lookup.h" #include "atom_netlist.h" +#include "cad_types.h" #include "cluster_placement.h" #include "cluster_router.h" #include "globals.h" @@ -37,43 +38,6 @@ #include "vtr_vector.h" #include "vtr_vector_map.h" -/** - * @brief Counts the total number of logic models that the architecture can - * implement. - * - * @param user_models A linked list of logic models. - * @return The total number of models in the linked list - */ -static size_t count_models(const t_model* user_models) { - if (user_models == nullptr) - return 0; - - size_t n_models = 0; - const t_model* cur_model = user_models; - while (cur_model != nullptr) { - n_models++; - cur_model = cur_model->next; - } - - return n_models; -} - -/* - * @brief Gets the max cluster size that any logical block can have. - * - * This is the maximum number of primitives any cluster can contain. - */ -static size_t calc_max_cluster_size(const std::vector& logical_block_types) { - size_t max_cluster_size = 0; - for (const t_logical_block_type& blk_type : logical_block_types) { - if (is_empty_type(&blk_type)) - continue; - int cur_cluster_size = get_max_primitives_in_pb_type(blk_type.pb_type); - max_cluster_size = std::max(max_cluster_size, cur_cluster_size); - } - return max_cluster_size; -} - /* * @brief Allocates the stats stored within the pb of a cluster. * @@ -97,24 +61,24 @@ static void alloc_and_load_pb_stats(t_pb* pb) { * @brief Check the atom blocks of a cluster pb. Used in the verify method. */ /* TODO: May want to check that all atom blocks are actually reached */ -static void check_cluster_atom_blocks(t_pb* pb, std::unordered_set& blocks_checked) { +static void check_cluster_atom_blocks(t_pb* pb, std::unordered_set& blocks_checked, const AtomPBBimap& atom_pb_lookup) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); const t_pb_type* pb_type = pb->pb_graph_node->pb_type; if (pb_type->num_modes == 0) { /* primitive */ - AtomBlockId blk_id = atom_ctx.lookup.pb_atom(pb); + AtomBlockId blk_id = atom_pb_lookup.pb_atom(pb); if (blk_id) { if (blocks_checked.count(blk_id)) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "pb %s contains atom block %s but atom block is already contained in another pb.\n", - pb->name, atom_ctx.nlist.block_name(blk_id).c_str()); + pb->name, atom_ctx.netlist().block_name(blk_id).c_str()); } blocks_checked.insert(blk_id); - if (pb != atom_ctx.lookup.atom_pb(blk_id)) { + if (pb != atom_pb_lookup.atom_pb(blk_id)) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "pb %s contains atom block %s but atom block does not link to pb.\n", - pb->name, atom_ctx.nlist.block_name(blk_id).c_str()); + pb->name, atom_ctx.netlist().block_name(blk_id).c_str()); } } } else { @@ -125,7 +89,7 @@ static void check_cluster_atom_blocks(t_pb* pb, std::unordered_set& if (pb->child_pbs[i] != nullptr) { if (pb->child_pbs[i][j].name != nullptr) { has_child = true; - check_cluster_atom_blocks(&pb->child_pbs[i][j], blocks_checked); + check_cluster_atom_blocks(&pb->child_pbs[i][j], blocks_checked, atom_pb_lookup); } } } @@ -199,8 +163,8 @@ static bool check_cluster_floorplanning(AtomBlockId atom_blk_id, // the Cluster's new PartitionRegion. if (cluster_pr.empty()) { VTR_LOGV(log_verbosity > 3, - "\t\t\t Intersect: Atom block %d has floorplanning constraints\n", - atom_blk_id); + "\t\t\t Intersect: Atom block %d has floorplanning constraints\n", + atom_blk_id); cluster_pr = atom_pr; cluster_pr_needs_update = true; return true; @@ -214,8 +178,8 @@ static bool check_cluster_floorplanning(AtomBlockId atom_blk_id, // Cluster due to floorplanning constraints. if (cluster_pr.empty()) { VTR_LOGV(log_verbosity > 3, - "\t\t\t Intersect: Atom block %d failed floorplanning check for cluster\n", - atom_blk_id); + "\t\t\t Intersect: Atom block %d failed floorplanning check for cluster\n", + atom_blk_id); cluster_pr_needs_update = false; return false; } @@ -290,22 +254,24 @@ static bool check_cluster_noc_group(AtomBlockId atom_blk_id, * outside the cluster) and returns the status of the placement accordingly. */ static enum e_block_pack_status check_chain_root_placement_feasibility(const t_pb_graph_node* pb_graph_node, - const t_pack_molecule* molecule, - const AtomBlockId blk_id) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); + const t_chain_info& prepack_chain_info, + const t_clustering_chain_info& clustering_chain_info, + t_pack_patterns* mol_pack_patterns, + const AtomBlockId blk_id) { + const AtomNetlist& atom_netlist = g_vpr_ctx.atom().netlist(); enum e_block_pack_status block_pack_status = e_block_pack_status::BLK_PASSED; - bool is_long_chain = molecule->chain_info->is_long_chain; + bool is_long_chain = prepack_chain_info.is_long_chain; - const auto& chain_root_pins = molecule->pack_pattern->chain_root_pins; + const auto& chain_root_pins = mol_pack_patterns->chain_root_pins; t_model_ports* root_port = chain_root_pins[0][0]->port->model_port; AtomNetId chain_net_id; - auto port_id = atom_ctx.nlist.find_atom_port(blk_id, root_port); + auto port_id = atom_netlist.find_atom_port(blk_id, root_port); if (port_id) { - chain_net_id = atom_ctx.nlist.port_net(port_id, chain_root_pins[0][0]->pin_number); + chain_net_id = atom_netlist.port_net(port_id, chain_root_pins[0][0]->pin_number); } // if this block is part of a long chain or it is driven by a cluster @@ -315,7 +281,7 @@ static enum e_block_pack_status check_chain_root_placement_feasibility(const t_p // driven by a global gnd or vdd. Therefore even if this is not a long chain // but its input pin is driven by a net, the placement legality is checked. if (is_long_chain || chain_net_id) { - auto chain_id = molecule->chain_info->chain_id; + auto chain_id = clustering_chain_info.chain_id; // if this chain has a chain id assigned to it (implies is_long_chain too) if (chain_id != -1) { // the chosen primitive should be a valid starting point for the chain @@ -390,8 +356,8 @@ static bool primitive_memory_sibling_feasible(const AtomBlockId blk_id, const t_ //driving the output net //Get the ports from each primitive - auto blk_port_id = atom_ctx.nlist.find_atom_port(blk_id, port); - auto sib_port_id = atom_ctx.nlist.find_atom_port(sibling_blk_id, port); + auto blk_port_id = atom_ctx.netlist().find_atom_port(blk_id, port); + auto sib_port_id = atom_ctx.netlist().find_atom_port(sibling_blk_id, port); //Check that all nets (including unconnected nets) match for (int ipin = 0; ipin < port->size; ++ipin) { @@ -404,10 +370,10 @@ static bool primitive_memory_sibling_feasible(const AtomBlockId blk_id, const t_ //Note that if the port did not exist, the net is left //as invalid/disconneced if (blk_port_id) { - blk_net_id = atom_ctx.nlist.port_net(blk_port_id, ipin); + blk_net_id = atom_ctx.netlist().port_net(blk_port_id, ipin); } if (sib_port_id) { - sib_net_id = atom_ctx.nlist.port_net(sib_port_id, ipin); + sib_net_id = atom_ctx.netlist().port_net(sib_port_id, ipin); } //The sibling and block must have the same (possibly disconnected) @@ -426,14 +392,12 @@ static bool primitive_memory_sibling_feasible(const AtomBlockId blk_id, const t_ /* * @brief Check if the given atom is feasible in the given pb. */ -static bool primitive_feasible(const AtomBlockId blk_id, t_pb* cur_pb) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); - +static bool primitive_feasible(const AtomBlockId blk_id, t_pb* cur_pb, const AtomPBBimap& atom_to_pb) { const t_pb_type* cur_pb_type = cur_pb->pb_graph_node->pb_type; VTR_ASSERT(cur_pb_type->num_modes == 0); /* primitive */ - AtomBlockId cur_pb_blk_id = atom_ctx.lookup.pb_atom(cur_pb); + AtomBlockId cur_pb_blk_id = atom_to_pb.pb_atom(cur_pb); if (cur_pb_blk_id && cur_pb_blk_id != blk_id) { /* This pb already has a different logical block */ return false; @@ -444,7 +408,8 @@ static bool primitive_feasible(const AtomBlockId blk_id, t_pb* cur_pb) { * - all siblings must share all nets, including open nets, with the exception of data nets */ /* find sibling if one exists */ - AtomBlockId sibling_memory_blk_id = find_memory_sibling(cur_pb); + const t_pb* sibling_memory_pb = find_memory_sibling(cur_pb); + AtomBlockId sibling_memory_blk_id = atom_to_pb.pb_atom(sibling_memory_pb); if (sibling_memory_blk_id) { //There is a sibling, see if the current block is feasible with it @@ -467,17 +432,15 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, const AtomBlockId blk_id, t_pb* cb, t_pb** parent, - const int max_models, - const int max_cluster_size, const LegalizationClusterId cluster_id, vtr::vector_map& atom_cluster, - const t_intra_cluster_placement_stats* cluster_placement_stats_ptr, - const t_pack_molecule* molecule, + const PackMoleculeId molecule_id, t_lb_router_data* router_data, int verbosity, - const int feasible_block_array_size) { + const Prepacker& prepacker, + const vtr::vector_map& clustering_chain_info, + AtomPBBimap& atom_to_pb) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); - AtomContext& mutable_atom_ctx = g_vpr_ctx.mutable_atom(); VTR_ASSERT_SAFE(cb != nullptr); e_block_pack_status block_pack_status = e_block_pack_status::BLK_PASSED; @@ -487,10 +450,11 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, if (pb_graph_node->parent_pb_graph_node != cb->pb_graph_node) { t_pb* my_parent = nullptr; block_pack_status = try_place_atom_block_rec(pb_graph_node->parent_pb_graph_node, blk_id, cb, - &my_parent, max_models, max_cluster_size, cluster_id, + &my_parent, cluster_id, atom_cluster, - cluster_placement_stats_ptr, molecule, router_data, - verbosity, feasible_block_array_size); + molecule_id, router_data, + verbosity, + prepacker, clustering_chain_info, atom_to_pb); parent_pb = my_parent; } else { parent_pb = cb; @@ -500,7 +464,7 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, VTR_ASSERT(parent_pb != nullptr); if (parent_pb->child_pbs == nullptr) { VTR_ASSERT(parent_pb->name == nullptr); - parent_pb->name = vtr::strdup(atom_ctx.nlist.block_name(blk_id).c_str()); + parent_pb->name = vtr::strdup(atom_ctx.netlist().block_name(blk_id).c_str()); parent_pb->mode = pb_graph_node->pb_type->parent_mode->index; set_reset_pb_modes(router_data, parent_pb, true); const t_mode* mode = &parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode]; @@ -548,12 +512,12 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, bool is_primitive = (pb_type->num_modes == 0); if (is_primitive) { - VTR_ASSERT(!atom_ctx.lookup.pb_atom(pb) - && atom_ctx.lookup.atom_pb(blk_id) == nullptr + VTR_ASSERT(!atom_to_pb.pb_atom(pb) + && atom_to_pb.atom_pb(blk_id) == nullptr && atom_cluster[blk_id] == LegalizationClusterId::INVALID()); /* try pack to location */ VTR_ASSERT(pb->name == nullptr); - pb->name = vtr::strdup(atom_ctx.nlist.block_name(blk_id).c_str()); + pb->name = vtr::strdup(atom_ctx.netlist().block_name(blk_id).c_str()); //Update the atom netlist mappings atom_cluster[blk_id] = cluster_id; @@ -562,27 +526,34 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, // TODO: It would be a good idea to remove the use of this global // variables to prevent external users from modifying this by // mistake. - mutable_atom_ctx.lookup.set_atom_pb(blk_id, pb); + atom_to_pb.set_atom_pb(blk_id, pb); - add_atom_as_target(router_data, blk_id); - if (!primitive_feasible(blk_id, pb)) { + add_atom_as_target(router_data, blk_id, atom_to_pb); + if (!primitive_feasible(blk_id, pb, atom_to_pb)) { /* failed location feasibility check, revert pack */ block_pack_status = e_block_pack_status::BLK_FAILED_FEASIBLE; } // if this block passed and is part of a chained molecule - if (block_pack_status == e_block_pack_status::BLK_PASSED && molecule->is_chain()) { - auto molecule_root_block = molecule->atom_block_ids[molecule->root]; + const t_pack_molecule& molecule = prepacker.get_molecule(molecule_id); + if (block_pack_status == e_block_pack_status::BLK_PASSED && molecule.is_chain()) { + auto molecule_root_block = molecule.atom_block_ids[molecule.root]; // if this is the root block of the chain molecule check its placmeent feasibility if (blk_id == molecule_root_block) { - block_pack_status = check_chain_root_placement_feasibility(pb_graph_node, molecule, blk_id); + VTR_ASSERT(molecule.chain_id.is_valid()); + const t_chain_info& prepack_chain_info = prepacker.get_molecule_chain_info(molecule.chain_id); + block_pack_status = check_chain_root_placement_feasibility(pb_graph_node, + prepack_chain_info, + clustering_chain_info[molecule.chain_id], + molecule.pack_pattern, + blk_id); } } VTR_LOGV(verbosity > 4 && block_pack_status == e_block_pack_status::BLK_PASSED, "\t\t\tPlaced atom '%s' (%s) at %s\n", - atom_ctx.nlist.block_name(blk_id).c_str(), - atom_ctx.nlist.block_model(blk_id)->name, + atom_ctx.netlist().block_name(blk_id).c_str(), + atom_ctx.netlist().block_model(blk_id)->name, pb->hierarchical_type_name().c_str()); } @@ -628,13 +599,13 @@ static void reset_lookahead_pins_used(t_pb* cur_pb) { * @brief Checks if the sinks of the given net are reachable from the driver * pb gpin. */ -static int net_sinks_reachable_in_cluster(const t_pb_graph_pin* driver_pb_gpin, const int depth, const AtomNetId net_id) { +static int net_sinks_reachable_in_cluster(const t_pb_graph_pin* driver_pb_gpin, const int depth, const AtomNetId net_id, const AtomPBBimap& atom_to_pb) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); //Record the sink pb graph pins we are looking for std::unordered_set sink_pb_gpins; - for (const AtomPinId pin_id : atom_ctx.nlist.net_sinks(net_id)) { - const t_pb_graph_pin* sink_pb_gpin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, pin_id); + for (const AtomPinId pin_id : atom_ctx.netlist().net_sinks(net_id)) { + const t_pb_graph_pin* sink_pb_gpin = find_pb_graph_pin(atom_ctx.netlist(), atom_to_pb, pin_id); VTR_ASSERT(sink_pb_gpin); sink_pb_gpins.insert(sink_pb_gpin); @@ -647,7 +618,7 @@ static int net_sinks_reachable_in_cluster(const t_pb_graph_pin* driver_pb_gpin, if (sink_pb_gpins.count(reachable_pb_gpin)) { ++num_reachable_sinks; - if (num_reachable_sinks == atom_ctx.nlist.net_sinks(net_id).size()) { + if (num_reachable_sinks == atom_ctx.netlist().net_sinks(net_id).size()) { return true; } } @@ -660,20 +631,20 @@ static int net_sinks_reachable_in_cluster(const t_pb_graph_pin* driver_pb_gpin, * @brief Returns the pb_graph_pin of the atom pin defined by the driver_pin_id in the driver_pb */ static t_pb_graph_pin* get_driver_pb_graph_pin(const t_pb* driver_pb, const AtomPinId driver_pin_id) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); + const AtomNetlist& atom_netlist = g_vpr_ctx.atom().netlist(); const auto driver_pb_type = driver_pb->pb_graph_node->pb_type; int output_port = 0; // find the port of the pin driving the net as well as the port model - auto driver_port_id = atom_ctx.nlist.pin_port(driver_pin_id); - auto driver_model_port = atom_ctx.nlist.port_model(driver_port_id); + auto driver_port_id = atom_netlist.pin_port(driver_pin_id); + auto driver_model_port = atom_netlist.port_model(driver_port_id); // find the port id of the port containing the driving pin in the driver_pb_type for (int i = 0; i < driver_pb_type->num_ports; i++) { auto& prim_port = driver_pb_type->ports[i]; if (prim_port.type == OUT_PORT) { if (prim_port.model_port == driver_model_port) { // get the output pb_graph_pin driving this input net - return &(driver_pb->pb_graph_node->output_pins[output_port][atom_ctx.nlist.pin_port_bit(driver_pin_id)]); + return &(driver_pb->pb_graph_node->output_pins[output_port][atom_netlist.pin_port_bit(driver_pin_id)]); } output_port++; } @@ -694,7 +665,8 @@ static t_pb_graph_pin* get_driver_pb_graph_pin(const t_pb* driver_pb, const Atom static void compute_and_mark_lookahead_pins_used_for_pin(const t_pb_graph_pin* pb_graph_pin, const t_pb* primitive_pb, const AtomNetId net_id, - const vtr::vector_map& atom_cluster) { + const vtr::vector_map& atom_cluster, + const AtomPBBimap& atom_to_pb) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); // starting from the parent pb of the input primitive go up in the hierarchy till the root block @@ -703,17 +675,17 @@ static void compute_and_mark_lookahead_pins_used_for_pin(const t_pb_graph_pin* p const auto pin_class = pb_graph_pin->parent_pin_class[depth]; VTR_ASSERT(pin_class != OPEN); - const auto driver_blk_id = atom_ctx.nlist.net_driver_block(net_id); + const auto driver_blk_id = atom_ctx.netlist().net_driver_block(net_id); // if this primitive pin is an input pin if (pb_graph_pin->port->type == IN_PORT) { /* find location of net driver if exist in clb, NULL otherwise */ // find the driver of the input net connected to the pin being studied - const auto driver_pin_id = atom_ctx.nlist.net_driver(net_id); + const auto driver_pin_id = atom_ctx.netlist().net_driver(net_id); // find the id of the atom occupying the input primitive_pb - const auto prim_blk_id = atom_ctx.lookup.pb_atom(primitive_pb); + const auto prim_blk_id = atom_to_pb.pb_atom(primitive_pb); // find the pb block occupied by the driving atom - const auto driver_pb = atom_ctx.lookup.atom_pb(driver_blk_id); + const auto driver_pb = atom_to_pb.atom_pb(driver_blk_id); // pb_graph_pin driving net_id in the driver pb block t_pb_graph_pin* output_pb_graph_pin = nullptr; // if the driver block is in the same clb as the input primitive block @@ -761,7 +733,7 @@ static void compute_and_mark_lookahead_pins_used_for_pin(const t_pb_graph_pin* p */ bool net_exits_cluster = true; - int num_net_sinks = static_cast(atom_ctx.nlist.net_sinks(net_id).size()); + int num_net_sinks = static_cast(atom_ctx.netlist().net_sinks(net_id).size()); if (pb_graph_pin->num_connectable_primitive_input_pins[depth] >= num_net_sinks) { //It is possible the net is completely absorbed in the cluster, @@ -785,8 +757,8 @@ static void compute_and_mark_lookahead_pins_used_for_pin(const t_pb_graph_pin* p //Check if all the net sinks are, in fact, inside this cluster bool all_sinks_in_cur_cluster = true; LegalizationClusterId driver_cluster = atom_cluster[driver_blk_id]; - for (auto pin_id : atom_ctx.nlist.net_sinks(net_id)) { - auto sink_blk_id = atom_ctx.nlist.pin_block(pin_id); + for (auto pin_id : atom_ctx.netlist().net_sinks(net_id)) { + auto sink_blk_id = atom_ctx.netlist().pin_block(pin_id); if (atom_cluster[sink_blk_id] != driver_cluster) { all_sinks_in_cur_cluster = false; break; @@ -801,7 +773,7 @@ static void compute_and_mark_lookahead_pins_used_for_pin(const t_pb_graph_pin* p //the net does not exit the cluster /* TODO: I should cache the absorbed outputs, once net is absorbed, * net is forever absorbed, no point in rechecking every time */ - if (net_sinks_reachable_in_cluster(pb_graph_pin, depth, net_id)) { + if (net_sinks_reachable_in_cluster(pb_graph_pin, depth, net_id, atom_to_pb)) { //All the sinks are reachable inside the cluster net_exits_cluster = false; } @@ -816,23 +788,23 @@ static void compute_and_mark_lookahead_pins_used_for_pin(const t_pb_graph_pin* p } } - /* * @brief Determine if pins of speculatively packed pb are legal */ static void compute_and_mark_lookahead_pins_used(const AtomBlockId blk_id, - const vtr::vector_map& atom_cluster) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); + const vtr::vector_map& atom_cluster, + const AtomPBBimap& atom_to_pb) { + const AtomNetlist& atom_netlist = g_vpr_ctx.atom().netlist(); - const t_pb* cur_pb = atom_ctx.lookup.atom_pb(blk_id); + const t_pb* cur_pb = atom_to_pb.atom_pb(blk_id); VTR_ASSERT(cur_pb != nullptr); /* Walk through inputs, outputs, and clocks marking pins off of the same class */ - for (auto pin_id : atom_ctx.nlist.block_pins(blk_id)) { - auto net_id = atom_ctx.nlist.pin_net(pin_id); + for (auto pin_id : atom_netlist.block_pins(blk_id)) { + auto net_id = atom_netlist.pin_net(pin_id); - const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, pin_id); - compute_and_mark_lookahead_pins_used_for_pin(pb_graph_pin, cur_pb, net_id, atom_cluster); + const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_netlist, atom_to_pb, pin_id); + compute_and_mark_lookahead_pins_used_for_pin(pb_graph_pin, cur_pb, net_id, atom_cluster, atom_to_pb); } } @@ -843,9 +815,8 @@ static void compute_and_mark_lookahead_pins_used(const AtomBlockId blk_id, * number of pb_graph pins. Can use hash tables or make incremental if becomes an issue. */ static void try_update_lookahead_pins_used(t_pb* cur_pb, - const vtr::vector_map& atom_cluster) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); - + const vtr::vector_map& atom_cluster, + const AtomPBBimap& atom_to_pb) { // run recursively till a leaf (primitive) pb block is reached const t_pb_type* pb_type = cur_pb->pb_graph_node->pb_type; if (pb_type->num_modes > 0 && cur_pb->name != nullptr) { @@ -853,7 +824,7 @@ static void try_update_lookahead_pins_used(t_pb* cur_pb, for (int i = 0; i < pb_type->modes[cur_pb->mode].num_pb_type_children; i++) { if (cur_pb->child_pbs[i] != nullptr) { for (int j = 0; j < pb_type->modes[cur_pb->mode].pb_type_children[i].num_pb; j++) { - try_update_lookahead_pins_used(&cur_pb->child_pbs[i][j], atom_cluster); + try_update_lookahead_pins_used(&cur_pb->child_pbs[i][j], atom_cluster, atom_to_pb); } } } @@ -861,9 +832,9 @@ static void try_update_lookahead_pins_used(t_pb* cur_pb, } else { // find if this child (primitive) pb block has an atom mapped to it, // if yes compute and mark lookahead pins used for that pb block - AtomBlockId blk_id = atom_ctx.lookup.pb_atom(cur_pb); + AtomBlockId blk_id = atom_to_pb.pb_atom(cur_pb); if (pb_type->blif_model != nullptr && blk_id) { - compute_and_mark_lookahead_pins_used(blk_id, atom_cluster); + compute_and_mark_lookahead_pins_used(blk_id, atom_cluster, atom_to_pb); } } } @@ -932,26 +903,31 @@ static bool check_lookahead_pins_used(t_pb* cur_pb, t_ext_pin_util max_external_ return true; } -/** - * @brief This function takes a chain molecule, and the pb_graph_node that is - * chosen for packing the molecule's root block. Using the given - * root_primitive, this function will identify which chain id this - * molecule is being mapped to and will update the chain id value inside - * the chain info data structure of this molecule. - */ -static void update_molecule_chain_info(t_pack_molecule* chain_molecule, const t_pb_graph_node* root_primitive) { - VTR_ASSERT(chain_molecule->chain_info->chain_id == -1 && chain_molecule->chain_info->is_long_chain); +void ClusterLegalizer::update_clustering_chain_info(PackMoleculeId chain_molecule_id, + const t_pb_graph_node* root_primitive) { + // Get the molecule + VTR_ASSERT(chain_molecule_id.is_valid()); + const t_pack_molecule& chain_molecule = prepacker_.get_molecule(chain_molecule_id); + + // Get the ID of the chain it is a part of + MoleculeChainId chain_id = chain_molecule.chain_id; + VTR_ASSERT(chain_id.is_valid()); - auto chain_root_pins = chain_molecule->pack_pattern->chain_root_pins; + // Get the prepacking and clustering information on this chain. + const t_chain_info& prepack_chain_info = prepacker_.get_molecule_chain_info(chain_id); + t_clustering_chain_info& clustering_chain_info = clustering_chain_info_[chain_id]; + VTR_ASSERT(clustering_chain_info.chain_id == -1 && prepack_chain_info.is_long_chain); + // Update the clustering chain information. // long chains should only be placed at the beginning of the chain // Since for long chains the molecule size is already equal to the // total number of adders in the cluster. Therefore, it should // always be placed at the very first adder in this cluster. + auto chain_root_pins = chain_molecule.pack_pattern->chain_root_pins; for (size_t chainId = 0; chainId < chain_root_pins.size(); chainId++) { if (chain_root_pins[chainId][0]->parent_node == root_primitive) { - chain_molecule->chain_info->chain_id = chainId; - chain_molecule->chain_info->first_packed_molecule = chain_molecule; + clustering_chain_info.chain_id = chainId; + clustering_chain_info.first_packed_molecule = chain_molecule_id; return; } } @@ -959,28 +935,27 @@ static void update_molecule_chain_info(t_pack_molecule* chain_molecule, const t_ VTR_ASSERT(false); } -/* - * @brief Reset molecule information created while trying to cluster it. - * - * This code only resets information that has to do with long chains. - * - * TODO: This information should not be stored in the molecule, but should be - * stored in the ClusterLegalizer class instead. - * - * TODO: This code may be removable. Tried turning it off and found no test - * failures or QoR degredations. Should be investigated in more detail. - */ -static void reset_molecule_info(t_pack_molecule* mol) { +void ClusterLegalizer::reset_molecule_info(PackMoleculeId mol_id) { + VTR_ASSERT(mol_id.is_valid()); + // when invalidating a molecule check if it's a chain molecule // that is part of a long chain. If so, check if this molecule // has modified the chain_id value based on the stale packing // then reset the chain id and the first packed molecule pointer // this is packing is being reset - if (mol->is_chain() - && mol->chain_info->is_long_chain - && mol->chain_info->first_packed_molecule == mol) { - mol->chain_info->first_packed_molecule = nullptr; - mol->chain_info->chain_id = -1; + const t_pack_molecule& mol = prepacker_.get_molecule(mol_id); + if (!mol.is_chain()) + return; + + VTR_ASSERT(mol.chain_id.is_valid()); + const t_chain_info& prepack_chain_info = prepacker_.get_molecule_chain_info(mol.chain_id); + if (!prepack_chain_info.is_long_chain) + return; + + t_clustering_chain_info& clustering_chain_info = clustering_chain_info_[mol.chain_id]; + if (clustering_chain_info.first_packed_molecule == mol_id) { + clustering_chain_info.first_packed_molecule = PackMoleculeId::INVALID(); + clustering_chain_info.chain_id = -1; } } @@ -989,16 +964,14 @@ static void reset_molecule_info(t_pack_molecule* mol) { */ static void revert_place_atom_block(const AtomBlockId blk_id, t_lb_router_data* router_data, - vtr::vector_map& atom_cluster) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); - AtomContext& mutable_atom_ctx = g_vpr_ctx.mutable_atom(); - + vtr::vector_map& atom_cluster, + AtomPBBimap& atom_to_pb) { //We cast away const here since we may free the pb, and it is //being removed from the active mapping. // //In general most code works fine accessing cosnt t_pb*, - //which is why we store them as such in atom_ctx.lookup - t_pb* pb = const_cast(atom_ctx.lookup.atom_pb(blk_id)); + //which is why we store them as such in atom_ctx.lookup() + t_pb* pb = const_cast(atom_to_pb.atom_pb(blk_id)); if (pb != nullptr) { /* When freeing molecules, the current block might already have been freed by a prior revert @@ -1006,7 +979,7 @@ static void revert_place_atom_block(const AtomBlockId blk_id, */ t_pb* next = pb->parent_pb; - free_pb(pb); + free_pb(pb, atom_to_pb); pb = next; while (pb != nullptr) { @@ -1022,7 +995,7 @@ static void revert_place_atom_block(const AtomBlockId blk_id, /* If the code gets here, then that means that placing the initial seed molecule * failed, don't free the actual complex block itself as the seed needs to find * another placement */ - free_pb(pb); + free_pb(pb, atom_to_pb); } } pb = next; @@ -1031,7 +1004,7 @@ static void revert_place_atom_block(const AtomBlockId blk_id, //Update the atom netlist mapping atom_cluster[blk_id] = LegalizationClusterId::INVALID(); - mutable_atom_ctx.lookup.set_atom_pb(blk_id, nullptr); + atom_to_pb.set_atom_pb(blk_id, nullptr); } /* @@ -1139,14 +1112,14 @@ static bool cleanup_pb(t_pb* pb) { return can_free; } -e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecule, +e_block_pack_status ClusterLegalizer::try_pack_molecule(PackMoleculeId molecule_id, LegalizationCluster& cluster, LegalizationClusterId cluster_id, const t_ext_pin_util& max_external_pin_util) { // Try to pack the molecule into a cluster with this pb type. // Safety debugs. - VTR_ASSERT_DEBUG(molecule != nullptr); + VTR_ASSERT_DEBUG(molecule_id.is_valid()); VTR_ASSERT_DEBUG(cluster.pb != nullptr); VTR_ASSERT_DEBUG(cluster.type != nullptr); @@ -1159,15 +1132,19 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul // - Checking if the atom can be placed in the cluster for floorplanning // constraints. const FloorplanningContext& floorplanning_ctx = g_vpr_ctx.floorplanning(); + + // Get the molecule object. + const t_pack_molecule& molecule = prepacker_.get_molecule(molecule_id); + if (log_verbosity_ > 3) { - AtomBlockId root_atom = molecule->atom_block_ids[molecule->root]; + AtomBlockId root_atom = molecule.atom_block_ids[molecule.root]; VTR_LOG("\t\tTry pack molecule: '%s' (%s)", - atom_ctx.nlist.block_name(root_atom).c_str(), - atom_ctx.nlist.block_model(root_atom)->name); - VTR_LOGV(molecule->pack_pattern, + atom_ctx.netlist().block_name(root_atom).c_str(), + atom_ctx.netlist().block_model(root_atom)->name); + VTR_LOGV(molecule.pack_pattern, " molecule_type %s molecule_size %zu", - molecule->pack_pattern->name, - molecule->atom_block_ids.size()); + molecule.pack_pattern->name, + molecule.atom_block_ids.size()); VTR_LOG("\n"); } @@ -1176,7 +1153,7 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul // molecules to be placed in this cluster. To avoid possibly creating cluster level // blocks that have incompatible placement constraints or form very long placement // macros that limit placement flexibility. - if (cluster.placement_stats->has_long_chain && molecule->is_chain() && molecule->chain_info->is_long_chain) { + if (cluster.placement_stats->has_long_chain && molecule.is_chain() && prepacker_.get_molecule_chain_info(molecule.chain_id).is_long_chain) { VTR_LOGV(log_verbosity_ > 4, "\t\t\tFAILED Placement Feasibility Filter: Only one long chain per cluster is allowed\n"); return e_block_pack_status::BLK_FAILED_FEASIBLE; } @@ -1187,40 +1164,39 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul PartitionRegion new_cluster_pr = cluster.pr; // TODO: This can be made more efficient by pre-computing the intersection // of all the atoms' PRs in the molecule. - int molecule_size = get_array_size_of_molecule(molecule); - for (int i_mol = 0; i_mol < molecule_size; i_mol++) { + for (AtomBlockId atom_blk_id : molecule.atom_block_ids) { + if (!atom_blk_id.is_valid()) + continue; + // Try to intersect with atom PartitionRegion if atom exists - AtomBlockId atom_blk_id = molecule->atom_block_ids[i_mol]; - if (atom_blk_id) { - bool cluster_pr_needs_update = false; - bool block_pack_floorplan_status = check_cluster_floorplanning(atom_blk_id, - new_cluster_pr, - floorplanning_ctx.constraints, - log_verbosity_, - cluster_pr_needs_update); - if (!block_pack_floorplan_status) { - return e_block_pack_status::BLK_FAILED_FLOORPLANNING; - } + bool cluster_pr_needs_update = false; + bool block_pack_floorplan_status = check_cluster_floorplanning(atom_blk_id, + new_cluster_pr, + floorplanning_ctx.constraints, + log_verbosity_, + cluster_pr_needs_update); + if (!block_pack_floorplan_status) { + return e_block_pack_status::BLK_FAILED_FLOORPLANNING; + } - if (cluster_pr_needs_update) { - cluster_pr_update_check = true; - } + if (cluster_pr_needs_update) { + cluster_pr_update_check = true; } } // Check if all atoms in the molecule can be added to the cluster without // NoC group conflicts NocGroupId new_cluster_noc_grp_id = cluster.noc_grp_id; - for (int i_mol = 0; i_mol < molecule_size; i_mol++) { - AtomBlockId atom_blk_id = molecule->atom_block_ids[i_mol]; - if (atom_blk_id) { - bool block_pack_noc_grp_status = check_cluster_noc_group(atom_blk_id, - new_cluster_noc_grp_id, - atom_noc_grp_id_, - log_verbosity_); - if (!block_pack_noc_grp_status) { - return e_block_pack_status::BLK_FAILED_NOC_GROUP; - } + for (AtomBlockId atom_blk_id : molecule.atom_block_ids) { + if (!atom_blk_id.is_valid()) + continue; + + bool block_pack_noc_grp_status = check_cluster_noc_group(atom_blk_id, + new_cluster_noc_grp_id, + atom_noc_grp_id_, + log_verbosity_); + if (!block_pack_noc_grp_status) { + return e_block_pack_status::BLK_FAILED_NOC_GROUP; } } @@ -1228,19 +1204,20 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul e_block_pack_status block_pack_status = e_block_pack_status::BLK_STATUS_UNDEFINED; while (block_pack_status != e_block_pack_status::BLK_PASSED) { if (!get_next_primitive_list(cluster.placement_stats, - molecule, - primitives_list.data())) { + molecule_id, + primitives_list, + prepacker_)) { VTR_LOGV(log_verbosity_ > 3, "\t\tFAILED No candidate primitives available\n"); block_pack_status = e_block_pack_status::BLK_FAILED_FEASIBLE; break; /* no more candidate primitives available, this molecule will not pack, return fail */ } block_pack_status = e_block_pack_status::BLK_PASSED; - int failed_location = 0; - for (int i_mol = 0; i_mol < molecule_size && block_pack_status == e_block_pack_status::BLK_PASSED; i_mol++) { - VTR_ASSERT((primitives_list[i_mol] == nullptr) == (!molecule->atom_block_ids[i_mol])); + size_t failed_location = 0; + for (size_t i_mol = 0; i_mol < molecule.atom_block_ids.size() && block_pack_status == e_block_pack_status::BLK_PASSED; i_mol++) { + VTR_ASSERT((primitives_list[i_mol] == nullptr) == (!molecule.atom_block_ids[i_mol])); failed_location = i_mol + 1; - AtomBlockId atom_blk_id = molecule->atom_block_ids[i_mol]; + AtomBlockId atom_blk_id = molecule.atom_block_ids[i_mol]; if (!atom_blk_id.is_valid()) continue; // NOTE: This parent variable is only used in the recursion of this @@ -1250,21 +1227,20 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul atom_blk_id, cluster.pb, &parent, - num_models_, - max_cluster_size_, cluster_id, atom_cluster_, - cluster.placement_stats, - molecule, + molecule_id, cluster.router_data, log_verbosity_, - feasible_block_array_size_); + prepacker_, + clustering_chain_info_, + mutable_atom_pb_lookup()); } if (enable_pin_feasibility_filter_ && block_pack_status == e_block_pack_status::BLK_PASSED) { // Check if pin usage is feasible for the current packing assignment reset_lookahead_pins_used(cluster.pb); - try_update_lookahead_pins_used(cluster.pb, atom_cluster_); + try_update_lookahead_pins_used(cluster.pb, atom_cluster_, atom_pb_lookup()); if (!check_lookahead_pins_used(cluster.pb, max_external_pin_util)) { VTR_LOGV(log_verbosity_ > 4, "\t\t\tFAILED Pin Feasibility Filter\n"); block_pack_status = e_block_pack_status::BLK_FAILED_FEASIBLE; @@ -1322,14 +1298,14 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul * TODO: SW Engineering note - may want to update cluster stats here too instead of doing it outside */ VTR_ASSERT(block_pack_status == e_block_pack_status::BLK_PASSED); - if (molecule->is_chain()) { + if (molecule.is_chain()) { /* Chained molecules often take up lots of area and are important, * if a chain is packed in, want to rename logic block to match chain name */ - AtomBlockId chain_root_blk_id = molecule->atom_block_ids[molecule->pack_pattern->root_block->block_id]; - t_pb* cur_pb = atom_ctx.lookup.atom_pb(chain_root_blk_id)->parent_pb; + AtomBlockId chain_root_blk_id = molecule.atom_block_ids[molecule.pack_pattern->root_block->block_id]; + t_pb* cur_pb = atom_pb_lookup().atom_pb(chain_root_blk_id)->parent_pb; while (cur_pb != nullptr) { free(cur_pb->name); - cur_pb->name = vtr::strdup(atom_ctx.nlist.block_name(chain_root_blk_id).c_str()); + cur_pb->name = vtr::strdup(atom_ctx.netlist().block_name(chain_root_blk_id).c_str()); cur_pb = cur_pb->parent_pb; } // if this molecule is part of a chain, mark the cluster as having a long chain @@ -1337,10 +1313,13 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul // If so, update the chain id for this chain of molecules to make sure all // molecules will be packed to the same chain id and can reach each other using // the chain direct links between clusters - if (molecule->chain_info->is_long_chain) { + VTR_ASSERT(molecule.chain_id.is_valid()); + const t_chain_info& prepack_chain_info = prepacker_.get_molecule_chain_info(molecule.chain_id); + if (prepack_chain_info.is_long_chain) { cluster.placement_stats->has_long_chain = true; - if (molecule->chain_info->chain_id == -1) { - update_molecule_chain_info(molecule, primitives_list[molecule->root]); + const t_clustering_chain_info& clustering_chain_info = clustering_chain_info_[molecule.chain_id]; + if (clustering_chain_info.chain_id == -1) { + update_clustering_chain_info(molecule_id, primitives_list[molecule.root]); } } } @@ -1356,10 +1335,10 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul cluster.noc_grp_id = new_cluster_noc_grp_id; // Insert the molecule into the cluster for bookkeeping. - cluster.molecules.push_back(molecule); + cluster.molecules.push_back(molecule_id); - for (int i = 0; i < molecule_size; i++) { - AtomBlockId atom_blk_id = molecule->atom_block_ids[i]; + for (size_t i = 0; i < molecule.atom_block_ids.size(); i++) { + AtomBlockId atom_blk_id = molecule.atom_block_ids[i]; if (!atom_blk_id.is_valid()) continue; @@ -1368,7 +1347,7 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul atom_cluster_[atom_blk_id] = cluster_id; // Update the num child blocks in pb - const t_pb* atom_pb = atom_ctx.lookup.atom_pb(atom_blk_id); + const t_pb* atom_pb = atom_pb_lookup().atom_pb(atom_blk_id); VTR_ASSERT_SAFE(atom_pb != nullptr); t_pb* cur_pb = atom_pb->parent_pb; while (cur_pb != nullptr) { @@ -1384,19 +1363,19 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul if (block_pack_status != e_block_pack_status::BLK_PASSED) { /* Pack unsuccessful, undo inserting molecule into cluster */ - for (int i = 0; i < failed_location; i++) { - AtomBlockId atom_blk_id = molecule->atom_block_ids[i]; + for (size_t i = 0; i < failed_location; i++) { + AtomBlockId atom_blk_id = molecule.atom_block_ids[i]; if (atom_blk_id) { - remove_atom_from_target(cluster.router_data, atom_blk_id); + remove_atom_from_target(cluster.router_data, atom_blk_id, atom_pb_lookup()); } } - for (int i = 0; i < failed_location; i++) { - AtomBlockId atom_blk_id = molecule->atom_block_ids[i]; + for (size_t i = 0; i < failed_location; i++) { + AtomBlockId atom_blk_id = molecule.atom_block_ids[i]; if (atom_blk_id) { - revert_place_atom_block(atom_blk_id, cluster.router_data, atom_cluster_); + revert_place_atom_block(atom_blk_id, cluster.router_data, atom_cluster_, mutable_atom_pb_lookup()); } } - reset_molecule_info(molecule); + reset_molecule_info(molecule_id); /* Packing failed, but a part of the pb tree is still allocated and pbs have their modes set. * Before trying to pack next molecule the unused pbs need to be freed and, the most important, @@ -1415,20 +1394,19 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul } std::tuple -ClusterLegalizer::start_new_cluster(t_pack_molecule* molecule, +ClusterLegalizer::start_new_cluster(PackMoleculeId molecule_id, t_logical_block_type_ptr cluster_type, int cluster_mode) { // Safety asserts to ensure the API is being called with valid arguments. - VTR_ASSERT_DEBUG(molecule != nullptr); + VTR_ASSERT_DEBUG(molecule_id.is_valid()); VTR_ASSERT_DEBUG(cluster_type != nullptr); VTR_ASSERT_DEBUG(cluster_mode < cluster_type->pb_graph_head->pb_type->num_modes); // Ensure that the molecule has not already been placed. - VTR_ASSERT_SAFE(molecule_cluster_.find(molecule) == molecule_cluster_.end() || - !molecule_cluster_[molecule].is_valid()); + VTR_ASSERT_SAFE(!molecule_cluster_[molecule_id].is_valid()); // Safety asserts to ensure that the API was initialized properly. VTR_ASSERT_DEBUG(lb_type_rr_graphs_ != nullptr); - const AtomNetlist& atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); // Create the physical block for this cluster based on the type. t_pb* cluster_pb = new t_pb; @@ -1458,7 +1436,7 @@ ClusterLegalizer::start_new_cluster(t_pack_molecule* molecule, // (meaning all cluster pins are allowed to be used). const t_ext_pin_util FULL_EXTERNAL_PIN_UTIL(1., 1.); LegalizationClusterId new_cluster_id = LegalizationClusterId(legalization_cluster_ids_.size()); - e_block_pack_status pack_status = try_pack_molecule(molecule, + e_block_pack_status pack_status = try_pack_molecule(molecule_id, new_cluster, new_cluster_id, FULL_EXTERNAL_PIN_UTIL); @@ -1466,7 +1444,8 @@ ClusterLegalizer::start_new_cluster(t_pack_molecule* molecule, if (pack_status == e_block_pack_status::BLK_PASSED) { // Give the new cluster pb a name. The current convention is to name the // cluster after the root atom of the first molecule packed into it. - AtomBlockId root_atom = molecule->atom_block_ids[molecule->root]; + const t_pack_molecule& molecule = prepacker_.get_molecule(molecule_id); + AtomBlockId root_atom = molecule.atom_block_ids[molecule.root]; const std::string& root_atom_name = atom_nlist.block_name(root_atom); if (new_cluster.pb->name != nullptr) free(new_cluster.pb->name); @@ -1475,10 +1454,10 @@ ClusterLegalizer::start_new_cluster(t_pack_molecule* molecule, legalization_cluster_ids_.push_back(new_cluster_id); legalization_clusters_.push_back(std::move(new_cluster)); // Update the molecule to cluster map. - molecule_cluster_[molecule] = new_cluster_id; + molecule_cluster_[molecule_id] = new_cluster_id; } else { // Delete the new_cluster. - free_pb(new_cluster.pb); + free_pb(new_cluster.pb, mutable_atom_pb_lookup()); delete new_cluster.pb; free_router_data(new_cluster.router_data); free_cluster_placement_stats(new_cluster.placement_stats); @@ -1488,32 +1467,31 @@ ClusterLegalizer::start_new_cluster(t_pack_molecule* molecule, return {pack_status, new_cluster_id}; } -e_block_pack_status ClusterLegalizer::add_mol_to_cluster(t_pack_molecule* molecule, +e_block_pack_status ClusterLegalizer::add_mol_to_cluster(PackMoleculeId molecule_id, LegalizationClusterId cluster_id) { // Safety asserts to make sure the inputs are valid. VTR_ASSERT_SAFE(cluster_id.is_valid() && (size_t)cluster_id < legalization_clusters_.size()); VTR_ASSERT(legalization_cluster_ids_[cluster_id].is_valid() && "Cannot add to a destroyed cluster"); // Ensure that the molecule has not already been placed. - VTR_ASSERT(molecule_cluster_.find(molecule) == molecule_cluster_.end() || - !molecule_cluster_[molecule].is_valid()); + VTR_ASSERT(!molecule_cluster_[molecule_id].is_valid()); // Safety asserts to ensure that the API was initialized properly. VTR_ASSERT_DEBUG(lb_type_rr_graphs_ != nullptr); // Get the cluster. LegalizationCluster& cluster = legalization_clusters_[cluster_id]; VTR_ASSERT(cluster.router_data != nullptr && cluster.placement_stats != nullptr - && "Cannot add molecule to cleaned cluster!"); + && "Cannot add molecule to cleaned cluster!"); // Set the target_external_pin_util. t_ext_pin_util target_ext_pin_util = target_external_pin_util_.get_pin_util(cluster.type->name); // Try to pack the molecule into the cluster. - e_block_pack_status pack_status = try_pack_molecule(molecule, + e_block_pack_status pack_status = try_pack_molecule(molecule_id, cluster, cluster_id, target_ext_pin_util); // If the packing was successful, set the molecules' cluster to this one. if (pack_status == e_block_pack_status::BLK_PASSED) - molecule_cluster_[molecule] = cluster_id; + molecule_cluster_[molecule_id] = cluster_id; return pack_status; } @@ -1525,24 +1503,23 @@ void ClusterLegalizer::destroy_cluster(LegalizationClusterId cluster_id) { // Get the cluster. LegalizationCluster& cluster = legalization_clusters_[cluster_id]; // Remove all molecules from the cluster. - for (t_pack_molecule* mol : cluster.molecules) { - VTR_ASSERT_SAFE(molecule_cluster_.find(mol) != molecule_cluster_.end() && - molecule_cluster_[mol] == cluster_id); - molecule_cluster_[mol] = LegalizationClusterId::INVALID(); + for (PackMoleculeId mol_id : cluster.molecules) { + VTR_ASSERT_SAFE(molecule_cluster_[mol_id] == cluster_id); + molecule_cluster_[mol_id] = LegalizationClusterId::INVALID(); // Revert the placement of all blocks in the molecule. - int molecule_size = get_array_size_of_molecule(mol); - for (int i = 0; i < molecule_size; i++) { - AtomBlockId atom_blk_id = mol->atom_block_ids[i]; + const t_pack_molecule& mol = prepacker_.get_molecule(mol_id); + for (AtomBlockId atom_blk_id : mol.atom_block_ids) { if (atom_blk_id) { - revert_place_atom_block(atom_blk_id, cluster.router_data, atom_cluster_); + revert_place_atom_block(atom_blk_id, cluster.router_data, atom_cluster_, mutable_atom_pb_lookup()); } } - reset_molecule_info(mol); + reset_molecule_info(mol_id); + molecule_cluster_[mol_id] = LegalizationClusterId::INVALID(); } cluster.molecules.clear(); // Free the rest of the cluster data. // Casting things to nullptr for safety just in case someone is trying to use it. - free_pb(cluster.pb); + free_pb(cluster.pb, mutable_atom_pb_lookup()); delete cluster.pb; cluster.pb = nullptr; free_router_data(cluster.router_data); @@ -1563,10 +1540,11 @@ void ClusterLegalizer::compress() { legalization_cluster_ids_ = clean_and_reorder_ids(cluster_id_map); legalization_clusters_ = clean_and_reorder_values(legalization_clusters_, cluster_id_map); // Update the reverse lookups. - for (auto& it : molecule_cluster_) { - if (!it.second.is_valid()) + for (PackMoleculeId mol_id : prepacker_.molecules()) { + LegalizationClusterId old_cluster_id = molecule_cluster_[mol_id]; + if (!old_cluster_id.is_valid()) continue; - molecule_cluster_[it.first] = cluster_id_map[it.second]; + molecule_cluster_[mol_id] = cluster_id_map[old_cluster_id]; } for (size_t i = 0; i < atom_cluster_.size(); i++) { AtomBlockId atom_blk_id = AtomBlockId(i); @@ -1587,7 +1565,7 @@ void ClusterLegalizer::clean_cluster(LegalizationClusterId cluster_id) { // Get the cluster. LegalizationCluster& cluster = legalization_clusters_[cluster_id]; VTR_ASSERT(cluster.router_data != nullptr && cluster.placement_stats != nullptr - && "Should not clean an already cleaned cluster!"); + && "Should not clean an already cleaned cluster!"); // Free the pb stats. free_pb_stats_recursive(cluster.pb); // Load the pb_route so we can free the cluster router data. @@ -1618,16 +1596,13 @@ bool ClusterLegalizer::check_cluster_legality(LegalizationClusterId cluster_id) ClusterLegalizer::ClusterLegalizer(const AtomNetlist& atom_netlist, const Prepacker& prepacker, - const std::vector& logical_block_types, std::vector* lb_type_rr_graphs, - const t_model* user_models, - const t_model* library_models, const std::vector& target_external_pin_util_str, const t_pack_high_fanout_thresholds& high_fanout_thresholds, ClusterLegalizationStrategy cluster_legalization_strategy, bool enable_pin_feasibility_filter, - int feasible_block_array_size, - int log_verbosity) : prepacker_(prepacker) { + int log_verbosity) + : prepacker_(prepacker) { // Verify that the inputs are valid. VTR_ASSERT_SAFE(lb_type_rr_graphs != nullptr); @@ -1635,18 +1610,16 @@ ClusterLegalizer::ClusterLegalizer(const AtomNetlist& atom_netlist, // NOTE: Be careful with this constructor, it may throw a VPR_FATAL_ERROR. target_external_pin_util_ = t_ext_pin_util_targets(target_external_pin_util_str); + // Resize the molecule_cluster lookup to make the accesses much cheaper. + molecule_cluster_.resize(prepacker_.molecules().size(), LegalizationClusterId::INVALID()); // Resize the atom_cluster lookup to make the accesses much cheaper. atom_cluster_.resize(atom_netlist.blocks().size(), LegalizationClusterId::INVALID()); + // Default the clustering chain info for each chain. + clustering_chain_info_.resize(prepacker_.get_num_molecule_chains()); // Pre-compute the max size of any molecule. max_molecule_size_ = prepacker.get_max_molecule_size(); - // Calculate the max cluster size - // - Limit maximum number of elements for each cluster to MAX_SHORT - max_cluster_size_ = calc_max_cluster_size(logical_block_types); - VTR_ASSERT(max_cluster_size_ < MAX_SHORT); // Get a reference to the rr graphs. lb_type_rr_graphs_ = lb_type_rr_graphs; - // Get the number of models in the architecture. - num_models_ = count_models(user_models) + count_models(library_models); // Find all NoC router atoms. std::vector noc_atoms = find_noc_router_atoms(atom_netlist); update_noc_reachability_partitions(noc_atoms, @@ -1656,8 +1629,9 @@ ClusterLegalizer::ClusterLegalizer(const AtomNetlist& atom_netlist, // Copy the options passed by the user cluster_legalization_strategy_ = cluster_legalization_strategy; enable_pin_feasibility_filter_ = enable_pin_feasibility_filter; - feasible_block_array_size_ = feasible_block_array_size; log_verbosity_ = log_verbosity; + VTR_ASSERT(g_vpr_ctx.atom().lookup().atom_pb_bimap().is_empty()); + atom_pb_lookup_ = AtomPBBimap(); } void ClusterLegalizer::reset() { @@ -1667,9 +1641,8 @@ void ClusterLegalizer::reset() { continue; destroy_cluster(cluster_id); } + mutable_atom_pb_lookup().reset_bimap(); compress(); - // Reset the molecule_cluster map - molecule_cluster_.clear(); } void ClusterLegalizer::verify() { @@ -1683,25 +1656,25 @@ void ClusterLegalizer::verify() { /* * Check that each atom block connects to one physical primitive and that the primitive links up to the parent clb */ - for (auto blk_id : atom_ctx.nlist.blocks()) { + for (auto blk_id : atom_ctx.netlist().blocks()) { //Each atom should be part of a pb - const t_pb* atom_pb = atom_ctx.lookup.atom_pb(blk_id); + const t_pb* atom_pb = atom_pb_lookup().atom_pb(blk_id); if (!atom_pb) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "Atom block %s is not mapped to a pb\n", - atom_ctx.nlist.block_name(blk_id).c_str()); + atom_ctx.netlist().block_name(blk_id).c_str()); } //Check the reverse mapping is consistent - if (atom_ctx.lookup.pb_atom(atom_pb) != blk_id) { + if (atom_pb_lookup().pb_atom(atom_pb) != blk_id) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "pb %s does not contain atom block %s but atom block %s maps to pb.\n", atom_pb->name, - atom_ctx.nlist.block_name(blk_id).c_str(), - atom_ctx.nlist.block_name(blk_id).c_str()); + atom_ctx.netlist().block_name(blk_id).c_str(), + atom_ctx.netlist().block_name(blk_id).c_str()); } - VTR_ASSERT(atom_ctx.nlist.block_name(blk_id) == atom_pb->name); + VTR_ASSERT(atom_ctx.netlist().block_name(blk_id) == atom_pb->name); const t_pb* cur_pb = atom_pb; while (cur_pb->parent_pb) { @@ -1713,7 +1686,7 @@ void ClusterLegalizer::verify() { if (cluster_id == LegalizationClusterId::INVALID()) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "Atom %s is not mapped to a CLB\n", - atom_ctx.nlist.block_name(blk_id).c_str()); + atom_ctx.netlist().block_name(blk_id).c_str()); } if (cur_pb != get_cluster_pb(cluster_id)) { @@ -1727,22 +1700,21 @@ void ClusterLegalizer::verify() { for (LegalizationClusterId cluster_id : clusters()) { if (!cluster_id.is_valid()) continue; - check_cluster_atom_blocks(get_cluster_pb(cluster_id), - atoms_checked); + check_cluster_atom_blocks(get_cluster_pb(cluster_id), atoms_checked, atom_pb_lookup()); } - for (auto blk_id : atom_ctx.nlist.blocks()) { + for (auto blk_id : atom_ctx.netlist().blocks()) { if (!atoms_checked.count(blk_id)) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "Atom block %s not found in any cluster.\n", - atom_ctx.nlist.block_name(blk_id).c_str()); + atom_ctx.netlist().block_name(blk_id).c_str()); } } } -bool ClusterLegalizer::is_molecule_compatible(t_pack_molecule* molecule, +bool ClusterLegalizer::is_molecule_compatible(PackMoleculeId molecule_id, LegalizationClusterId cluster_id) const { - VTR_ASSERT_SAFE(molecule != nullptr); + VTR_ASSERT_SAFE(molecule_id.is_valid()); VTR_ASSERT_SAFE(cluster_id.is_valid() && (size_t)cluster_id < legalization_clusters_.size()); // Go through each atom in the molecule and check if there exists a free // primitive for that atom block. @@ -1753,7 +1725,8 @@ bool ClusterLegalizer::is_molecule_compatible(t_pack_molecule* molecule, // would be more robust, but checking individual atoms is faster. const LegalizationCluster& cluster = legalization_clusters_[cluster_id]; - for (AtomBlockId atom_blk_id : molecule->atom_block_ids) { + const t_pack_molecule& molecule = prepacker_.get_molecule(molecule_id); + for (AtomBlockId atom_blk_id : molecule.atom_block_ids) { // FIXME: Why is it possible that molecules contain invalid block IDs? // This should be fixed! if (!atom_blk_id.is_valid()) @@ -1773,8 +1746,7 @@ bool ClusterLegalizer::is_molecule_compatible(t_pack_molecule* molecule, return true; } -size_t ClusterLegalizer::get_num_cluster_inputs_available( - LegalizationClusterId cluster_id) const { +size_t ClusterLegalizer::get_num_cluster_inputs_available(LegalizationClusterId cluster_id) const { VTR_ASSERT_SAFE(cluster_id.is_valid() && (size_t)cluster_id < legalization_clusters_.size()); const LegalizationCluster& cluster = legalization_clusters_[cluster_id]; @@ -1807,4 +1779,3 @@ ClusterLegalizer::~ClusterLegalizer() { destroy_cluster(cluster_id); } } - diff --git a/vpr/src/pack/cluster_legalizer.h b/vpr/src/pack/cluster_legalizer.h index ef3ec64f7b2..67bc00a95ec 100644 --- a/vpr/src/pack/cluster_legalizer.h +++ b/vpr/src/pack/cluster_legalizer.h @@ -12,17 +12,19 @@ #pragma once -#include #include #include "atom_netlist_fwd.h" #include "noc_data_types.h" #include "partition_region.h" +#include "prepack.h" #include "vpr_types.h" #include "vtr_range.h" #include "vtr_strong_id.h" #include "vtr_vector.h" #include "vtr_vector_map.h" +#include "atom_pb_bimap.h" +// Forward declarations class Prepacker; class t_intra_cluster_placement_stats; class t_pb_graph_node; @@ -34,23 +36,49 @@ struct t_lb_router_data; struct legalization_cluster_id_tag; typedef vtr::StrongId LegalizationClusterId; +/** + * @brief Holds information to be shared between molecules that represent the + * same chained pack pattern, specifically for packing. + * + * For example, molecules that are representing a long carry chain that spans + * multiple logic blocks. + * + * This is holding clustering-specific information on the chains. General + * information on chains is found in the t_chain_info type. + */ +struct t_clustering_chain_info { + /// @brief An ID into the chain_root_pins vector in the t_pack_patterns of + /// the molecule. + /// + /// Used to get the starting point of this chain in the cluster. This ID is + /// useful when we have multiple (architectural) carry chains in a logic + /// block, for example. It lets us see which of the chains is being used for + /// this long (netlist) chain, so we continue to use that chain in the + /// packing of other molecules of this long chain. + int chain_id = -1; + + /// @brief First molecule to be packed out of the molecules forming this + /// chain. This is the molecule setting the value of the chain_id. + PackMoleculeId first_packed_molecule; +}; + /// @brief The different legalization strategies the cluster legalizer can perform. /// /// Allows the user of the API to select how thorough the legalizer should be /// when adding molecules into clusters. enum class ClusterLegalizationStrategy { - FULL, // Run the full legalizer (including intra-lb routing) - SKIP_INTRA_LB_ROUTE // Do all legality checks except intra-lb routing + FULL, // Run the full legalizer (including intra-lb routing) + SKIP_INTRA_LB_ROUTE // Do all legality checks except intra-lb routing }; /// @brief The status of the cluster legalization. enum class e_block_pack_status { - BLK_PASSED, // Passed legalization. - BLK_FAILED_FEASIBLE, // Failed due to block not feasibly being able to go in the cluster. - BLK_FAILED_ROUTE, // Failed due to intra-lb routing failure. - BLK_FAILED_FLOORPLANNING, // Failed due to not being compatible with the cluster's current PartitionRegion. - BLK_FAILED_NOC_GROUP, // Failed due to not being compatible with the cluster's NoC group. - BLK_STATUS_UNDEFINED // Undefined status. Something went wrong. + BLK_PASSED, // Passed legalization. + BLK_FAILED_FEASIBLE, // Failed due to block not feasibly being able to go in the cluster. + BLK_FAILED_ROUTE, // Failed due to intra-lb routing failure. + BLK_FAILED_FLOORPLANNING, // Failed due to not being compatible with the cluster's current PartitionRegion. + BLK_FAILED_NOC_GROUP, // Failed due to not being compatible with the cluster's NoC group. + BLK_STATUS_UNDEFINED // Undefined status. Something went wrong. }; /* @@ -62,7 +90,7 @@ struct LegalizationCluster { /// @brief A list of the molecules in the cluster. By design, a cluster will /// only contain molecules which have been previously legalized into /// the cluster using a legalization strategy. - std::vector molecules; + std::vector molecules; /// @brief The logical block of this cluster. /// TODO: We should be more careful with how this is allocated. Instead of @@ -164,15 +192,14 @@ struct LegalizationCluster { * // new_cluster_id now contains a fully legalized cluster. */ class ClusterLegalizer { -public: + public: // Iterator for the legalization cluster IDs typedef typename vtr::vector_map::const_iterator cluster_iterator; // Range for the legalization cluster IDs typedef typename vtr::Range cluster_range; -private: - + private: /* * @brief Helper method that tries to pack the given molecule into a cluster. * @@ -186,13 +213,29 @@ class ClusterLegalizer { * @param max_external_pin_util The max external pin utilization for a * cluster of this type. */ - e_block_pack_status try_pack_molecule(t_pack_molecule* molecule, + e_block_pack_status try_pack_molecule(PackMoleculeId molecule_id, LegalizationCluster& cluster, LegalizationClusterId cluster_id, const t_ext_pin_util& max_external_pin_util); -public: + /** + * @brief This function takes a chain molecule, and the pb_graph_node that is + * chosen for packing the molecule's root block. Using the given + * root_primitive, this function will identify which chain id this + * molecule is being mapped to and will update the chain id value inside + * the chain info data structure of this molecule. + */ + void update_clustering_chain_info(PackMoleculeId chain_molecule_id, + const t_pb_graph_node* root_primitive); + /* + * @brief Reset molecule information created while trying to cluster it. + * + * This code only resets information that has to do with long chains. + */ + void reset_molecule_info(PackMoleculeId mol_id); + + public: // Explicitly deleted default constructor. Need to use other constructor to // initialize state correctly. ClusterLegalizer() = delete; @@ -202,57 +245,39 @@ class ClusterLegalizer { * * Allocates internal state. * - * @param atom_netlist The complete atom netlist. Used to allocate - * internal structures to the correct size. - * @param prepacker The prepacker object used to prepack the atoms - * into molecules. A reference to this object is - * stored internally to be used to lookup the - * molecules of atoms. - * @param logical_block_types Used to allocate internal objects. Used to - * get the max number of primitives in any block - * type. - * @param lb_type_rr_graphs The routing resource graph internal to the - * different cluster types. A reference is stored - * in the class to be used to allocate and load - * the router data. - * @param user_models A linked list of the user models. Used to allocate - * an internal structure. - * @param library_models A linked list of the library models. Used to - * allocate an internal structure. - * @param target_external_pin_util_str A string used to initialize the - * target external pin utilization of - * each cluster type. - * @param high_fanout_thresholds An object that stores the thresholds for - * a net to be considered high fanout for - * different block types. - * @param cluster_legalization_strategy The legalization strategy to be - * used when creating clusters and - * adding molecules to clusters. - * Controls the checks that are performed. - * @param enable_pin_feasibility_filter A flag to turn on/off the check for - * pin usage feasibility. - * @param feasible_block_array_size The largest number of feasible blocks - * that can be stored in a cluster. Used - * to allocate an internal structure. - * @param log_verbosity Controls how verbose the log messages will - * be within this class. - * - * TODO: A lot of these arguments are only used to allocate C-style arrays - * since the original author was avoiding dynamic allocations. It may - * be more space efficient (and cleaner) to make these dynamic arrays - * and not pass these arguments in. + * @param atom_netlist + * The complete atom netlist. Used to allocate internal structures + * to the correct size. + * @param prepacker + * The prepacker object used to prepack the atoms into molecules. + * A reference to this object is stored internally to be used to + * lookup the molecules of atoms. + * @param lb_type_rr_graphs + * The routing resource graph internal to the different cluster + * types. A reference is stored in the class to be used to allocate + * and load the router data. + * @param target_external_pin_util_str + * A string used to initialize the target external pin utilization + * of each cluster type. + * @param high_fanout_thresholds + * An object that stores the thresholds for a net to be considered + * high fanout for different block types. + * @param cluster_legalization_strategy + * The legalization strategy to be used when creating clusters and + * adding molecules to clusters. Controls the checks that are + * performed. + * @param enable_pin_feasibility_filter + * A flag to turn on/off the check for pin usage feasibility. + * @param log_verbosity + * Controls how verbose the log messages will be within this class. */ ClusterLegalizer(const AtomNetlist& atom_netlist, const Prepacker& prepacker, - const std::vector& logical_block_types, std::vector* lb_type_rr_graphs, - const t_model* user_models, - const t_model* library_models, const std::vector& target_external_pin_util_str, const t_pack_high_fanout_thresholds& high_fanout_thresholds, ClusterLegalizationStrategy cluster_legalization_strategy, bool enable_pin_feasibility_filter, - int feasible_block_array_size, int log_verbosity); // This class allocates and deallocates memory within. This class should not @@ -272,7 +297,7 @@ class ClusterLegalizer { * status will return the reason and the ID would be invalid. */ std::tuple - start_new_cluster(t_pack_molecule* molecule, + start_new_cluster(PackMoleculeId molecule_id, t_logical_block_type_ptr cluster_type, int cluster_mode); @@ -292,7 +317,7 @@ class ClusterLegalizer { * @return The status of the pack (if the addition was successful and * if not why). */ - e_block_pack_status add_mol_to_cluster(t_pack_molecule* molecule, + e_block_pack_status add_mol_to_cluster(PackMoleculeId molecule_id, LegalizationClusterId cluster_id); /* @@ -396,7 +421,7 @@ class ClusterLegalizer { * go in a cluster. By calling it you can save runtime for impossible cases * vs. calling the full checks. */ - bool is_molecule_compatible(t_pack_molecule* molecule, + bool is_molecule_compatible(PackMoleculeId molecule_id, LegalizationClusterId cluster_id) const; /// @brief Gets the top-level pb of the given cluster. @@ -421,6 +446,13 @@ class ClusterLegalizer { return cluster.pr; } + /// @brief Gets the molecules currently packed within the given cluster. + inline const std::vector& get_cluster_molecules(LegalizationClusterId cluster_id) const { + VTR_ASSERT_SAFE(cluster_id.is_valid() && (size_t)cluster_id < legalization_clusters_.size()); + const LegalizationCluster& cluster = legalization_clusters_[cluster_id]; + return cluster.molecules; + } + /// @brief Gets the current number of molecules in the cluster. inline size_t get_num_molecules_in_cluster(LegalizationClusterId cluster_id) const { VTR_ASSERT_SAFE(cluster_id.is_valid() && (size_t)cluster_id < legalization_clusters_.size()); @@ -446,17 +478,11 @@ class ClusterLegalizer { /// @brief Returns true if the given molecule has been packed into a /// cluster, false otherwise. - inline bool is_mol_clustered(t_pack_molecule* mol) const { - VTR_ASSERT_SAFE(mol != nullptr); + inline bool is_mol_clustered(PackMoleculeId mol_id) const { + VTR_ASSERT_SAFE(mol_id.is_valid()); // Check if the molecule has been assigned a cluster. It has not been - // assigned a cluster if it does not have an entry in the map or if the - // ID of the cluster it is assigned to is invalid. - const auto iter = molecule_cluster_.find(mol); - if (iter == molecule_cluster_.end()) - return false; - if (!iter->second.is_valid()) - return false; - return true; + // assigned a cluster if it is assigned to a valid cluster. + return molecule_cluster_[mol_id].is_valid(); } /// @brief Returns a reference to the target_external_pin_util object. This @@ -465,14 +491,6 @@ class ClusterLegalizer { return target_external_pin_util_; } - /// @bried Gets the max size a cluster could physically be. - /// - /// This is the maximum number of primitives any cluster could ever have - /// in the architecture. - inline size_t get_max_cluster_size() const { - return max_cluster_size_; - } - /* * @brief Set the legalization strategy of the cluster legalizer. * @@ -503,16 +521,22 @@ class ClusterLegalizer { log_verbosity_ = verbosity; } + inline const AtomPBBimap& atom_pb_lookup() const { return atom_pb_lookup_; } + inline AtomPBBimap& mutable_atom_pb_lookup() { return atom_pb_lookup_; } + /// @brief Destructor of the class. Frees allocated data. ~ClusterLegalizer(); -private: + private: /// @brief A vector of the legalization cluster IDs. If any of them are /// invalid, then that means that the cluster has been destroyed. vtr::vector_map legalization_cluster_ids_; /// @brief Lookup table for which cluster each molecule is in. - std::unordered_map molecule_cluster_; + vtr::vector_map molecule_cluster_; + + /// @brief Clustering chain information for each of the chains in the prepacker. + vtr::vector_map clustering_chain_info_; /// @brief List of all legalization clusters. vtr::vector_map legalization_clusters_; @@ -537,20 +561,12 @@ class ClusterLegalizer { /// expensive to calculate from the prepacker. size_t max_molecule_size_; - /// @brief The max number of primitives a cluster could physically have. - /// This is used to allocate dynamic arrays. - size_t max_cluster_size_; - /// @brief A vector of routing resource nodes within each logical block type /// [0 .. num_logical_block_types-1] /// TODO: This really should not be a pointer to a vector... I think this is /// meant to be a vector of vectors... std::vector* lb_type_rr_graphs_ = nullptr; - /// @brief The total number of models (user + library) in the architecture. - /// Used to allocate space in dynamic data structures. - size_t num_models_; - /// @brief The current legalization strategy of the cluster legalizer. ClusterLegalizationStrategy cluster_legalization_strategy_; @@ -564,11 +580,6 @@ class ClusterLegalizer { /// option of the same name. bool enable_pin_feasibility_filter_; - /// @brief The max size of the priority queue for candidates that pass the - /// early filter legality test but not the more detailed routing - /// filter. This matches the packer option of the same name. - int feasible_block_array_size_; - /// @brief Used to set the verbosity of log messages in the legalizer. Used /// for debugging. When log_verbosity > 3, the legalizer will print /// messages when a molecule is successful during legalization. When @@ -580,5 +591,8 @@ class ClusterLegalizer { /// @brief The prepacker object that stores the molecules which will be /// legalized into clusters. const Prepacker& prepacker_; -}; + /// @brief A two way map between AtomBlockIds and pb types. This is a copy + /// of the AtomPBBimap in the global context's AtomLookup + AtomPBBimap atom_pb_lookup_; +}; diff --git a/vpr/src/pack/cluster_placement.cpp b/vpr/src/pack/cluster_placement.cpp index 917545cd3ba..297212c4ff1 100644 --- a/vpr/src/pack/cluster_placement.cpp +++ b/vpr/src/pack/cluster_placement.cpp @@ -20,6 +20,7 @@ #include "cluster_placement.h" #include "hash.h" #include "physical_types.h" +#include "prepack.h" #include "vpr_types.h" #include "vpr_utils.h" #include "vtr_assert.h" @@ -43,14 +44,16 @@ static void update_primitive_cost_or_status(t_intra_cluster_placement_stats* clu bool valid); static float try_place_molecule(t_intra_cluster_placement_stats* cluster_placement_stats, - const t_pack_molecule* molecule, + PackMoleculeId molecule_id, t_pb_graph_node* root, - t_pb_graph_node** primitives_list); + std::vector& primitives_list, + const Prepacker& prepacker); static bool expand_forced_pack_molecule_placement(t_intra_cluster_placement_stats* cluster_placement_stats, - const t_pack_molecule* molecule, + PackMoleculeId molecule_id, const t_pack_pattern_block* pack_pattern_block, - t_pb_graph_node** primitives_list, + std::vector& primitives_list, + const Prepacker& prepacker, float* cost); static t_pb_graph_pin* expand_pack_molecule_pin_edge(int pattern_id, @@ -147,14 +150,14 @@ void t_intra_cluster_placement_stats::free_primitives() { } t_intra_cluster_placement_stats* alloc_and_load_cluster_placement_stats(t_logical_block_type_ptr cluster_type, - int cluster_mode) { + int cluster_mode) { t_intra_cluster_placement_stats* cluster_placement_stats = new t_intra_cluster_placement_stats; *cluster_placement_stats = t_intra_cluster_placement_stats(); // TODO: This initialization may be able to be made more efficient. // The reset and setting the mode can be done while loading the placement // stats. if (!is_empty_type(cluster_type)) { - cluster_placement_stats->curr_molecule = nullptr; + cluster_placement_stats->curr_molecule = PackMoleculeId::INVALID(); load_cluster_placement_stats_for_pb_graph_node(cluster_placement_stats, cluster_type->pb_graph_head); } @@ -173,19 +176,19 @@ void free_cluster_placement_stats(t_intra_cluster_placement_stats* cluster_place } bool get_next_primitive_list(t_intra_cluster_placement_stats* cluster_placement_stats, - const t_pack_molecule* molecule, - t_pb_graph_node** primitives_list, + PackMoleculeId molecule_id, + std::vector& primitives_list, + const Prepacker& prepacker, int force_site) { std::unordered_multimap::iterator best; - int i; float cost, lowest_cost; int best_pb_type_index = -1; - if (cluster_placement_stats->curr_molecule != molecule) { + if (cluster_placement_stats->curr_molecule != molecule_id) { /* New block, requeue tried primitives and in-flight primitives */ cluster_placement_stats->flush_intermediate_queues(); - cluster_placement_stats->curr_molecule = molecule; + cluster_placement_stats->curr_molecule = molecule_id; } else { /* Hack! Same failed molecule may re-enter if upper stream functions suck, * I'm going to make the molecule selector more intelligent. @@ -207,13 +210,14 @@ bool get_next_primitive_list(t_intra_cluster_placement_stats* cluster_placement_ // Intialize variables bool found_best = false; - lowest_cost = HUGE_POSITIVE_FLOAT; + lowest_cost = std::numeric_limits::max(); // Iterate over each primitive block type in the current cluster_placement_stats - for (i = 0; i < cluster_placement_stats->num_pb_types; i++) { + for (int i = 0; i < cluster_placement_stats->num_pb_types; i++) { if (!cluster_placement_stats->valid_primitives[i].empty()) { t_cluster_placement_primitive* cur_cluster_placement_primitive = cluster_placement_stats->valid_primitives[i].begin()->second; - if (primitive_type_feasible(molecule->atom_block_ids[molecule->root], cur_cluster_placement_primitive->pb_graph_node->pb_type)) { + const t_pack_molecule& molecule = prepacker.get_molecule(molecule_id); + if (primitive_type_feasible(molecule.atom_block_ids[molecule.root], cur_cluster_placement_primitive->pb_graph_node->pb_type)) { // Iterate over the unordered_multimap of the valid primitives of a specific pb primitive type for (auto it = cluster_placement_stats->valid_primitives[i].begin(); it != cluster_placement_stats->valid_primitives[i].end(); /*loop increment is done inside the loop*/) { //Lazily remove invalid primitives @@ -233,10 +237,11 @@ bool get_next_primitive_list(t_intra_cluster_placement_stats* cluster_placement_ } if (force_site == it->second->pb_graph_node->flat_site_index) { cost = try_place_molecule(cluster_placement_stats, - molecule, + molecule_id, it->second->pb_graph_node, - primitives_list); - if (cost < HUGE_POSITIVE_FLOAT) { + primitives_list, + prepacker); + if (cost < std::numeric_limits::max()) { cluster_placement_stats->move_primitive_to_inflight(i, it); return true; } else { @@ -250,9 +255,10 @@ bool get_next_primitive_list(t_intra_cluster_placement_stats* cluster_placement_ /* try place molecule at root location cur */ cost = try_place_molecule(cluster_placement_stats, - molecule, + molecule_id, it->second->pb_graph_node, - primitives_list); + primitives_list, + prepacker); // if the cost is lower than the best, or is equal to the best but this // primitive is more available in the cluster mark it as the best primitive @@ -275,15 +281,17 @@ bool get_next_primitive_list(t_intra_cluster_placement_stats* cluster_placement_ if (!found_best) { /* failed to find a placement */ - for (i = 0; i < molecule->num_blocks; i++) { + const t_pack_molecule& molecule = prepacker.get_molecule(molecule_id); + for (size_t i = 0; i < molecule.atom_block_ids.size(); i++) { primitives_list[i] = nullptr; } } else { /* populate primitive list with best */ cost = try_place_molecule(cluster_placement_stats, - molecule, + molecule_id, best->second->pb_graph_node, - primitives_list); + primitives_list, + prepacker); VTR_ASSERT(cost == lowest_cost); /* take out best node and put it in flight */ @@ -313,7 +321,7 @@ static void reset_cluster_placement_stats(t_intra_cluster_placement_stats* clust primitive.second->valid = true; } } - cluster_placement_stats->curr_molecule = nullptr; + cluster_placement_stats->curr_molecule = PackMoleculeId::INVALID(); cluster_placement_stats->has_long_chain = false; } @@ -444,20 +452,18 @@ static void update_primitive_cost_or_status(t_intra_cluster_placement_stats* clu const t_pb_graph_node* pb_graph_node, const float incremental_cost, const bool valid) { - int i, j, k; - t_cluster_placement_primitive* placement_primitive; if (pb_graph_node->is_primitive()) { /* is primitive */ - placement_primitive = cluster_placement_stats->get_pb_graph_node_placement_primitive(pb_graph_node); + t_cluster_placement_primitive* placement_primitive = cluster_placement_stats->get_pb_graph_node_placement_primitive(pb_graph_node); if (valid) { placement_primitive->incremental_cost += incremental_cost; } else { placement_primitive->valid = false; } } else { - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; j++) { - for (k = 0; k < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; k++) { + for (int i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (int j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; j++) { + for (int k = 0; k < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; k++) { update_primitive_cost_or_status(cluster_placement_stats, &pb_graph_node->child_pb_graph_nodes[i][j][k], incremental_cost, valid); @@ -471,38 +477,40 @@ static void update_primitive_cost_or_status(t_intra_cluster_placement_stats* clu * Try place molecule at root location, populate primitives list with locations of placement if successful */ static float try_place_molecule(t_intra_cluster_placement_stats* cluster_placement_stats, - const t_pack_molecule* molecule, + PackMoleculeId molecule_id, t_pb_graph_node* root, - t_pb_graph_node** primitives_list) { - int list_size, i; - float cost = HUGE_POSITIVE_FLOAT; - list_size = get_array_size_of_molecule(molecule); + std::vector& primitives_list, + const Prepacker& prepacker) { + float cost = std::numeric_limits::max(); + const t_pack_molecule& molecule = prepacker.get_molecule(molecule_id); + size_t list_size = molecule.atom_block_ids.size(); - if (primitive_type_feasible(molecule->atom_block_ids[molecule->root], + if (primitive_type_feasible(molecule.atom_block_ids[molecule.root], root->pb_type)) { t_cluster_placement_primitive* root_placement_primitive = cluster_placement_stats->get_pb_graph_node_placement_primitive(root); if (root_placement_primitive->valid) { - for (i = 0; i < list_size; i++) { + for (size_t i = 0; i < list_size; i++) { primitives_list[i] = nullptr; } cost = root_placement_primitive->base_cost + root_placement_primitive->incremental_cost; - primitives_list[molecule->root] = root; - if (molecule->type == MOLECULE_FORCED_PACK) { + primitives_list[molecule.root] = root; + if (molecule.type == e_pack_pattern_molecule_type::MOLECULE_FORCED_PACK) { if (!expand_forced_pack_molecule_placement(cluster_placement_stats, - molecule, - molecule->pack_pattern->root_block, + molecule_id, + molecule.pack_pattern->root_block, primitives_list, + prepacker, &cost)) { - return HUGE_POSITIVE_FLOAT; + return std::numeric_limits::max(); } } - for (i = 0; i < list_size; i++) { - VTR_ASSERT((primitives_list[i] == nullptr) == (!molecule->atom_block_ids[i])); - for (int j = 0; j < list_size; j++) { + for (size_t i = 0; i < list_size; i++) { + VTR_ASSERT((primitives_list[i] == nullptr) == (!molecule.atom_block_ids[i])); + for (size_t j = 0; j < list_size; j++) { if (i != j) { if (primitives_list[i] != nullptr && primitives_list[i] == primitives_list[j]) { - return HUGE_POSITIVE_FLOAT; + return std::numeric_limits::max(); } } } @@ -517,9 +525,10 @@ static float try_place_molecule(t_intra_cluster_placement_stats* cluster_placeme * Assumes molecule and pack pattern connections have fan-out 1 */ static bool expand_forced_pack_molecule_placement(t_intra_cluster_placement_stats* cluster_placement_stats, - const t_pack_molecule* molecule, + PackMoleculeId molecule_id, const t_pack_pattern_block* pack_pattern_block, - t_pb_graph_node** primitives_list, + std::vector& primitives_list, + const Prepacker& prepacker, float* cost) { t_pb_graph_node* pb_graph_node = primitives_list[pack_pattern_block->block_id]; t_pb_graph_node* next_primitive; @@ -534,7 +543,8 @@ static bool expand_forced_pack_molecule_placement(t_intra_cluster_placement_stat } else { next_block = cur->from_block; } - if (primitives_list[next_block->block_id] == nullptr && molecule->atom_block_ids[next_block->block_id]) { + const t_pack_molecule& molecule = prepacker.get_molecule(molecule_id); + if (primitives_list[next_block->block_id] == nullptr && molecule.atom_block_ids[next_block->block_id]) { /* first time visiting location */ /* find next primitive based on pattern connections, expand next primitive if not visited */ @@ -563,12 +573,12 @@ static bool expand_forced_pack_molecule_placement(t_intra_cluster_placement_stat if (next_pin != nullptr) { next_primitive = next_pin->parent_node; /* Check for legality of placement, if legal, expand from legal placement, if not, return false */ - if (molecule->atom_block_ids[next_block->block_id] && primitives_list[next_block->block_id] == nullptr) { + if (molecule.atom_block_ids[next_block->block_id] && primitives_list[next_block->block_id] == nullptr) { t_cluster_placement_primitive* next_placement_primitive = cluster_placement_stats->get_pb_graph_node_placement_primitive(next_primitive); - if (next_placement_primitive->valid && primitive_type_feasible(molecule->atom_block_ids[next_block->block_id], next_primitive->pb_type)) { + if (next_placement_primitive->valid && primitive_type_feasible(molecule.atom_block_ids[next_block->block_id], next_primitive->pb_type)) { primitives_list[next_block->block_id] = next_primitive; *cost += next_placement_primitive->base_cost + next_placement_primitive->incremental_cost; - if (!expand_forced_pack_molecule_placement(cluster_placement_stats, molecule, next_block, primitives_list, cost)) { + if (!expand_forced_pack_molecule_placement(cluster_placement_stats, molecule_id, next_block, primitives_list, prepacker, cost)) { return false; } } else { @@ -685,15 +695,6 @@ static t_pb_graph_pin* expand_pack_molecule_pin_edge(const int pattern_id, return dest_pin; } -/* Determine max index + 1 of molecule */ -int get_array_size_of_molecule(const t_pack_molecule* molecule) { - if (molecule->type == MOLECULE_FORCED_PACK) { - return molecule->pack_pattern->num_blocks; - } else { - return molecule->num_blocks; - } -} - /* Given atom block, determines if a free primitive exists for it */ bool exists_free_primitive_for_atom_block(t_intra_cluster_placement_stats* cluster_placement_stats, const AtomBlockId blk_id) { diff --git a/vpr/src/pack/cluster_placement.h b/vpr/src/pack/cluster_placement.h index f3d840457ca..2f3e438b0fd 100644 --- a/vpr/src/pack/cluster_placement.h +++ b/vpr/src/pack/cluster_placement.h @@ -9,7 +9,10 @@ #include #include #include "physical_types.h" -#include "vpr_types.h" +#include "prepack.h" + +// Forward declarations +class AtomBlockId; /** * @brief Stats keeper for placement within the cluster during packing @@ -18,9 +21,9 @@ */ class t_intra_cluster_placement_stats { public: - int num_pb_types; ///& primitives_list, + const Prepacker& prepacker, int force_site = -1); /** @@ -173,11 +177,6 @@ bool get_next_primitive_list( void commit_primitive(t_intra_cluster_placement_stats* cluster_placement_stats, const t_pb_graph_node* primitive); -/** - * @brief Determine max index + 1 of molecule - */ -int get_array_size_of_molecule(const t_pack_molecule* molecule); - /** * @brief Given atom block, determines if a free primitive exists for it, */ diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp index 1f10e556ad1..92d4b183dc5 100644 --- a/vpr/src/pack/cluster_router.cpp +++ b/vpr/src/pack/cluster_router.cpp @@ -34,6 +34,7 @@ #include "pb_type_graph.h" #include "lb_type_rr_graph.h" #include "cluster_router.h" +#include "atom_pb_bimap.h" /* #define PRINT_INTRA_LB_ROUTE */ @@ -74,10 +75,10 @@ class reservable_pq : public std::priority_queue { ******************************************************************************************/ static void free_lb_net_rt(t_lb_trace* lb_trace); static void free_lb_trace(t_lb_trace* lb_trace); -static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id); -static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id); +static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id, const AtomPBBimap& atom_to_pb); +static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id, const AtomPBBimap& atom_to_pb); -static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data); +static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data, const AtomPBBimap& atom_to_pb); static void commit_remove_rt(t_lb_trace* rt, t_lb_router_data* router_data, e_commit_remove op, std::unordered_map* mode_map, t_mode_selection_status* mode_status); static bool is_skip_route_net(t_lb_trace* rt, t_lb_router_data* router_data); @@ -248,17 +249,17 @@ static bool check_edge_for_route_conflicts(std::unordered_map& atoms_added = *router_data->atoms_added; if (atoms_added.count(blk_id) > 0) { - VPR_FATAL_ERROR(VPR_ERROR_PACK, "Atom %s added twice to router\n", atom_ctx.nlist.block_name(blk_id).c_str()); + VPR_FATAL_ERROR(VPR_ERROR_PACK, "Atom %s added twice to router\n", atom_ctx.netlist().block_name(blk_id).c_str()); } - pb = atom_ctx.lookup.atom_pb(blk_id); + pb = atom_to_pb.atom_pb(blk_id); VTR_ASSERT(pb); @@ -266,20 +267,20 @@ void add_atom_as_target(t_lb_router_data* router_data, const AtomBlockId blk_id) set_reset_pb_modes(router_data, pb, true); - for (auto pin_id : atom_ctx.nlist.block_pins(blk_id)) { - add_pin_to_rt_terminals(router_data, pin_id); + for (auto pin_id : atom_ctx.netlist().block_pins(blk_id)) { + add_pin_to_rt_terminals(router_data, pin_id, atom_to_pb); } - fix_duplicate_equivalent_pins(router_data); + fix_duplicate_equivalent_pins(router_data, atom_to_pb); } /* Remove pins of netlist atom from current routing drivers/targets */ -void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId blk_id) { +void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId blk_id, const AtomPBBimap& atom_to_pb) { auto& atom_ctx = g_vpr_ctx.atom(); std::map& atoms_added = *router_data->atoms_added; - const t_pb* pb = atom_ctx.lookup.atom_pb(blk_id); + const t_pb* pb = atom_to_pb.atom_pb(blk_id); if (atoms_added.count(blk_id) == 0) { return; @@ -287,8 +288,8 @@ void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId bl set_reset_pb_modes(router_data, pb, false); - for (auto pin_id : atom_ctx.nlist.block_pins(blk_id)) { - remove_pin_from_rt_terminals(router_data, pin_id); + for (auto pin_id : atom_ctx.netlist().block_pins(blk_id)) { + remove_pin_from_rt_terminals(router_data, pin_id, atom_to_pb); } atoms_added.erase(blk_id); @@ -356,7 +357,7 @@ static bool try_expand_nodes(t_lb_router_data* router_data, if (verbosity > 3) { //Print detailed debug info - auto& atom_nlist = g_vpr_ctx.atom().nlist; + auto& atom_nlist = g_vpr_ctx.atom().netlist(); AtomNetId net_id = lb_net->atom_net_id; AtomPinId driver_pin = lb_net->atom_pins[0]; AtomPinId sink_pin = lb_net->atom_pins[itarget]; @@ -507,7 +508,7 @@ bool try_intra_lb_route(t_lb_router_data* router_data, --inet; auto& atom_ctx = g_vpr_ctx.atom(); VTR_LOGV(verbosity > 3, "Net '%s' is impossible to route within proposed %s cluster\n", - atom_ctx.nlist.net_name(lb_nets[inet].atom_net_id).c_str(), router_data->lb_type->name.c_str()); + atom_ctx.netlist().net_name(lb_nets[inet].atom_net_id).c_str(), router_data->lb_type->name.c_str()); is_routed = false; } router_data->pres_con_fac *= router_data->params.pres_fac_mult; @@ -625,7 +626,7 @@ static void free_lb_trace(t_lb_trace* lb_trace) { /* Given a pin of a net, assign route tree terminals for it * Assumes that pin is not already assigned */ -static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id) { +static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id, const AtomPBBimap& atom_to_pb) { std::vector& lb_nets = *router_data->intra_lb_nets; std::vector& lb_type_graph = *router_data->lb_type_graph; t_logical_block_type_ptr lb_type = router_data->lb_type; @@ -633,11 +634,11 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin unsigned int ipos; auto& atom_ctx = g_vpr_ctx.atom(); - const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, pin_id); + const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.netlist(), atom_to_pb, pin_id); VTR_ASSERT(pb_graph_pin); - AtomPortId port_id = atom_ctx.nlist.pin_port(pin_id); - AtomNetId net_id = atom_ctx.nlist.pin_net(pin_id); + AtomPortId port_id = atom_ctx.netlist().pin_port(pin_id); + AtomNetId net_id = atom_ctx.netlist().pin_net(pin_id); if (!net_id) { //No net connected to this pin, so nothing to route @@ -675,7 +676,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin int source_terminal = get_lb_type_rr_graph_ext_source_index(lb_type); lb_nets[ipos].terminals.push_back(source_terminal); - AtomPinId net_driver_pin_id = atom_ctx.nlist.net_driver(net_id); + AtomPinId net_driver_pin_id = atom_ctx.netlist().net_driver(net_id); lb_nets[ipos].atom_pins.push_back(net_driver_pin_id); VTR_ASSERT_MSG(lb_type_graph[lb_nets[ipos].terminals[0]].type == LB_SOURCE, "Driver must be a source"); @@ -683,11 +684,11 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size()); - if (atom_ctx.nlist.port_type(port_id) == PortType::OUTPUT) { + if (atom_ctx.netlist().port_type(port_id) == PortType::OUTPUT) { //The current pin is the net driver, overwrite the default driver at index 0 VTR_ASSERT_MSG(lb_nets[ipos].terminals[0] == get_lb_type_rr_graph_ext_source_index(lb_type), "Default driver must be external source"); - VTR_ASSERT(atom_ctx.nlist.pin_type(pin_id) == PinType::DRIVER); + VTR_ASSERT(atom_ctx.netlist().pin_type(pin_id) == PinType::DRIVER); //Override the default since this is the driver, and it is within the cluster lb_nets[ipos].terminals[0] = pb_graph_pin->pin_count_in_cluster; @@ -696,7 +697,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin VTR_ASSERT_MSG(lb_type_graph[lb_nets[ipos].terminals[0]].type == LB_SOURCE, "Driver must be a source"); int sink_terminal = OPEN; - if (lb_nets[ipos].terminals.size() < atom_ctx.nlist.net_pins(net_id).size()) { + if (lb_nets[ipos].terminals.size() < atom_ctx.netlist().net_pins(net_id).size()) { //Not all of the pins are within the cluster if (lb_nets[ipos].terminals.size() == 1) { //Only the source has been specified so far, must add cluster-external sink @@ -724,9 +725,9 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin } } else { //This is an input to a primitive - VTR_ASSERT(atom_ctx.nlist.port_type(port_id) == PortType::INPUT - || atom_ctx.nlist.port_type(port_id) == PortType::CLOCK); - VTR_ASSERT(atom_ctx.nlist.pin_type(pin_id) == PinType::SINK); + VTR_ASSERT(atom_ctx.netlist().port_type(port_id) == PortType::INPUT + || atom_ctx.netlist().port_type(port_id) == PortType::CLOCK); + VTR_ASSERT(atom_ctx.netlist().pin_type(pin_id) == PinType::SINK); //Get the rr node index associated with the pin int pin_index = pb_graph_pin->pin_count_in_cluster; @@ -738,7 +739,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin int sink_index = lb_type_graph[pin_index].outedges[0][0].node_index; VTR_ASSERT(lb_type_graph[sink_index].type == LB_SINK); - if (lb_nets[ipos].terminals.size() == atom_ctx.nlist.net_pins(net_id).size() && lb_nets[ipos].terminals[1] == get_lb_type_rr_graph_ext_sink_index(lb_type)) { + if (lb_nets[ipos].terminals.size() == atom_ctx.netlist().net_pins(net_id).size() && lb_nets[ipos].terminals[1] == get_lb_type_rr_graph_ext_sink_index(lb_type)) { /* If all sinks of net are all contained in the logic block, then the net does * not need to route out of the logic block, so can replace the external sink * with this last sink terminal */ @@ -753,7 +754,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size()); int num_lb_terminals = lb_nets[ipos].terminals.size(); - VTR_ASSERT(num_lb_terminals <= (int)atom_ctx.nlist.net_pins(net_id).size()); + VTR_ASSERT(num_lb_terminals <= (int)atom_ctx.netlist().net_pins(net_id).size()); VTR_ASSERT(num_lb_terminals >= 0); #ifdef VTR_ASSERT_SAFE_ENABLED @@ -767,7 +768,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin //Net driver VTR_ASSERT_SAFE_MSG(lb_type_graph[inode].type == LB_SOURCE, "Driver must be a source RR node"); VTR_ASSERT_SAFE_MSG(atom_pin, "Driver have an associated atom pin"); - VTR_ASSERT_SAFE_MSG(atom_ctx.nlist.pin_type(atom_pin) == PinType::DRIVER, "Source RR must be associated with a driver pin in atom netlist"); + VTR_ASSERT_SAFE_MSG(atom_ctx.netlist().pin_type(atom_pin) == PinType::DRIVER, "Source RR must be associated with a driver pin in atom netlist"); if (inode == get_lb_type_rr_graph_ext_source_index(lb_type)) { ++num_extern_sources; } @@ -781,7 +782,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin ++num_extern_sinks; } else { VTR_ASSERT_SAFE_MSG(atom_pin, "Intra-cluster sink must have an associated atom pin"); - VTR_ASSERT_SAFE_MSG(atom_ctx.nlist.pin_type(atom_pin) == PinType::SINK, "Intra-cluster Sink RR must be associated with a sink pin in atom netlist"); + VTR_ASSERT_SAFE_MSG(atom_ctx.netlist().pin_type(atom_pin) == PinType::SINK, "Intra-cluster Sink RR must be associated with a sink pin in atom netlist"); } } } @@ -792,7 +793,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin /* Given a pin of a net, remove route tree terminals from it */ -static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id) { +static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id, const AtomPBBimap& atom_to_pb) { std::vector& lb_nets = *router_data->intra_lb_nets; std::vector& lb_type_graph = *router_data->lb_type_graph; t_logical_block_type_ptr lb_type = router_data->lb_type; @@ -800,10 +801,10 @@ static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const At unsigned int ipos; auto& atom_ctx = g_vpr_ctx.atom(); - const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, pin_id); + const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.netlist(), atom_to_pb, pin_id); - AtomPortId port_id = atom_ctx.nlist.pin_port(pin_id); - AtomNetId net_id = atom_ctx.nlist.pin_net(pin_id); + AtomPortId port_id = atom_ctx.netlist().pin_port(pin_id); + AtomNetId net_id = atom_ctx.netlist().pin_net(pin_id); if (!net_id) { /* This is not a valid net */ @@ -824,7 +825,7 @@ static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const At VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size()); - auto port_type = atom_ctx.nlist.port_type(port_id); + auto port_type = atom_ctx.netlist().port_type(port_id); if (port_type == PortType::OUTPUT) { /* Net driver pin takes 0th position in terminals */ int sink_terminal; @@ -917,7 +918,7 @@ static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const At //To work around this, we fix all but one of these duplicate connections to route to specific pins, //(instead of the common sink). This ensures a legal routing is produced and that the duplicate pins //are not 'missing' in the clustered netlist. -static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data) { +static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data, const AtomPBBimap& atom_to_pb) { auto& atom_ctx = g_vpr_ctx.atom(); std::vector& lb_type_graph = *router_data->lb_type_graph; @@ -943,7 +944,7 @@ static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data) { AtomPinId atom_pin = lb_nets[ilb_net].atom_pins[iterm]; VTR_ASSERT(atom_pin); - const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, atom_pin); + const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.netlist(), atom_to_pb, atom_pin); VTR_ASSERT(pb_graph_pin); if (pb_graph_pin->port->equivalent == PortEquivalence::NONE) continue; //Only need to remap equivalent ports @@ -955,7 +956,7 @@ static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data) { "Found duplicate nets connected to logically equivalent pins. " "Remapping intra lb net %d (atom net %zu '%s') from common sink " "pb_route %d to fixed pin pb_route %d\n", - ilb_net, size_t(lb_nets[ilb_net].atom_net_id), atom_ctx.nlist.net_name(lb_nets[ilb_net].atom_net_id).c_str(), + ilb_net, size_t(lb_nets[ilb_net].atom_net_id), atom_ctx.netlist().net_name(lb_nets[ilb_net].atom_net_id).c_str(), kv.first, pin_index); VTR_ASSERT(lb_type_graph[pin_index].type == LB_INTERMEDIATE); @@ -1290,7 +1291,7 @@ static void print_route(FILE* fp, t_lb_router_data* router_data) { for (unsigned int inet = 0; inet < lb_nets.size(); inet++) { AtomNetId net_id = lb_nets[inet].atom_net_id; - fprintf(fp, "net %s num targets %d \n", atom_ctx.nlist.net_name(net_id).c_str(), (int)lb_nets[inet].terminals.size()); + fprintf(fp, "net %s num targets %d \n", atom_ctx.netlist().net_name(net_id).c_str(), (int)lb_nets[inet].terminals.size()); fprintf(fp, "\tS"); print_trace(fp, lb_nets[inet].rt_tree, router_data); fprintf(fp, "\n\n"); @@ -1486,7 +1487,7 @@ static std::string describe_congested_rr_nodes(const std::vector& congested for (auto itr = range.first; itr != range.second; ++itr) { AtomNetId net = itr->second; description += vtr::string_fmt("\tNet: %s\n", - atom_ctx.nlist.net_name(net).c_str()); + atom_ctx.netlist().net_name(net).c_str()); } } diff --git a/vpr/src/pack/cluster_router.h b/vpr/src/pack/cluster_router.h index 4f88f1c0b6a..0b40f84c627 100644 --- a/vpr/src/pack/cluster_router.h +++ b/vpr/src/pack/cluster_router.h @@ -16,8 +16,8 @@ void free_router_data(t_lb_router_data* router_data); void free_intra_lb_nets(std::vector* intra_lb_nets); /* Routing Functions */ -void add_atom_as_target(t_lb_router_data* router_data, const AtomBlockId blk_id); -void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId blk_id); +void add_atom_as_target(t_lb_router_data* router_data, const AtomBlockId blk_id, const AtomPBBimap& atom_to_pb); +void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId blk_id, const AtomPBBimap& atom_to_pb); void set_reset_pb_modes(t_lb_router_data* router_data, const t_pb* pb, const bool set); bool try_intra_lb_route(t_lb_router_data* router_data, int verbosity, t_mode_selection_status* mode_status); void reset_intra_lb_route(t_lb_router_data* router_data); diff --git a/vpr/src/pack/cluster_util.cpp b/vpr/src/pack/cluster_util.cpp index 736bde0ef59..dd307168a36 100644 --- a/vpr/src/pack/cluster_util.cpp +++ b/vpr/src/pack/cluster_util.cpp @@ -2,17 +2,13 @@ #include #include -#include "PreClusterTimingGraphResolver.h" -#include "PreClusterDelayCalculator.h" #include "atom_netlist.h" #include "attraction_groups.h" #include "cluster_legalizer.h" #include "clustered_netlist.h" -#include "concrete_timing_info.h" +#include "globals.h" #include "output_clustering.h" #include "prepack.h" -#include "tatum/TimingReporter.hpp" -#include "tatum/echo_writer.hpp" #include "vpr_context.h" /*Print the contents of each cluster to an echo file*/ @@ -33,7 +29,7 @@ static void echo_clusters(char* filename, const ClusterLegalizer& cluster_legali cluster_atoms.insert({cluster_id, std::vector()}); } - for (auto atom_blk_id : atom_ctx.nlist.blocks()) { + for (auto atom_blk_id : atom_ctx.netlist().blocks()) { LegalizationClusterId cluster_id = cluster_legalizer.get_atom_cluster(atom_blk_id); cluster_atoms[cluster_id].push_back(atom_blk_id); @@ -48,7 +44,7 @@ static void echo_clusters(char* filename, const ClusterLegalizer& cluster_legali for (auto j = 0; j < num_atoms; j++) { AtomBlockId atom_id = cluster_atom.second[j]; - fprintf(fp, "\t %s \n", atom_ctx.nlist.block_name(atom_id).c_str()); + fprintf(fp, "\t %s \n", atom_ctx.netlist().block_name(atom_id).c_str()); } } @@ -67,58 +63,6 @@ static void echo_clusters(char* filename, const ClusterLegalizer& cluster_legali fclose(fp); } -void calc_init_packing_timing(const t_packer_opts& packer_opts, - const t_analysis_opts& analysis_opts, - const Prepacker& prepacker, - std::shared_ptr& clustering_delay_calc, - std::shared_ptr& timing_info, - vtr::vector& atom_criticality) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); - - /* - * Initialize the timing analyzer - */ - clustering_delay_calc = std::make_shared(atom_ctx.nlist, atom_ctx.lookup, packer_opts.inter_cluster_net_delay, prepacker); - timing_info = make_setup_timing_info(clustering_delay_calc, packer_opts.timing_update_type); - - //Calculate the initial timing - timing_info->update(); - - if (isEchoFileEnabled(E_ECHO_PRE_PACKING_TIMING_GRAPH)) { - auto& timing_ctx = g_vpr_ctx.timing(); - tatum::write_echo(getEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH), - *timing_ctx.graph, *timing_ctx.constraints, *clustering_delay_calc, timing_info->analyzer()); - - tatum::NodeId debug_tnode = id_or_pin_name_to_tnode(analysis_opts.echo_dot_timing_graph_node); - write_setup_timing_graph_dot(getEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH) + std::string(".dot"), - *timing_info, debug_tnode); - } - - { - auto& timing_ctx = g_vpr_ctx.timing(); - PreClusterTimingGraphResolver resolver(atom_ctx.nlist, - atom_ctx.lookup, *timing_ctx.graph, *clustering_delay_calc); - resolver.set_detail_level(analysis_opts.timing_report_detail); - - tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, - *timing_ctx.constraints); - - timing_reporter.report_timing_setup( - "pre_pack.report_timing.setup.rpt", - *timing_info->setup_analyzer(), - analysis_opts.timing_report_npaths); - } - - //Calculate true criticalities of each block - for (AtomBlockId blk : atom_ctx.nlist.blocks()) { - for (AtomPinId in_pin : atom_ctx.nlist.block_input_pins(blk)) { - //Max criticality over incoming nets - float crit = timing_info->setup_pin_criticality(in_pin); - atom_criticality[blk] = std::max(atom_criticality[blk], crit); - } - } -} - void check_and_output_clustering(ClusterLegalizer& cluster_legalizer, const t_packer_opts& packer_opts, const std::unordered_set& is_clock, @@ -163,8 +107,7 @@ void print_pack_status(int tot_num_molecules, int num_clusters_created = cluster_legalizer.clusters().size(); - if (mols_since_last_print >= int_molecule_increment || - num_molecules_processed == tot_num_molecules) { + if (mols_since_last_print >= int_molecule_increment || num_molecules_processed == tot_num_molecules) { VTR_LOG( "%6d/%-6d %3d%% " "%26d " @@ -210,7 +153,7 @@ void rebuild_attraction_groups(AttractionInfo& attraction_groups, std::map> identify_primitive_candidate_block_types() { std::map> model_candidates; - const AtomNetlist& atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); const DeviceContext& device_ctx = g_vpr_ctx.device(); std::set unique_models; @@ -452,13 +395,12 @@ void init_clb_atoms_lookup(vtr::vector& clustering_delay_calc, - std::shared_ptr& timing_info, - vtr::vector& atom_criticality); - /* * @brief Check clustering legality and output it. */ diff --git a/vpr/src/pack/constraints_report.cpp b/vpr/src/pack/constraints_report.cpp index 4d6b9a87e57..2c25cb5f8af 100644 --- a/vpr/src/pack/constraints_report.cpp +++ b/vpr/src/pack/constraints_report.cpp @@ -1,16 +1,12 @@ #include "constraints_report.h" #include "cluster_legalizer.h" -#include "globals.h" #include "grid_tile_lookup.h" -bool floorplan_constraints_regions_overfull(const ClusterLegalizer& cluster_legalizer) { +bool floorplan_constraints_regions_overfull(std::vector& overfull_partition_regions, + const ClusterLegalizer& cluster_legalizer, + const std::vector& logical_block_types) { GridTileLookup grid_tiles; - auto& floorplanning_ctx = g_vpr_ctx.mutable_floorplanning(); - auto& device_ctx = g_vpr_ctx.device(); - - const std::vector& block_types = device_ctx.logical_block_types; - // keep record of how many blocks of each type are assigned to each PartitionRegion std::unordered_map> pr_count_info; @@ -22,7 +18,7 @@ bool floorplan_constraints_regions_overfull(const ClusterLegalizer& cluster_lega t_logical_block_type_ptr bt = cluster_legalizer.get_cluster_type(cluster_id); auto got = pr_count_info.find(pr); if (got == pr_count_info.end()) { - std::vector block_type_counts(block_types.size(), 0); + std::vector block_type_counts(logical_block_types.size(), 0); block_type_counts[bt->index]++; pr_count_info.insert({pr, block_type_counts}); } else { @@ -35,7 +31,7 @@ bool floorplan_constraints_regions_overfull(const ClusterLegalizer& cluster_lega for (const auto& [pr, block_type_counts] : pr_count_info) { const std::vector& regions = pr.get_regions(); - for (const t_logical_block_type& block_type : block_types) { + for (const t_logical_block_type& block_type : logical_block_types) { int num_assigned_blocks = block_type_counts[block_type.index]; int num_tiles = std::accumulate(regions.begin(), regions.end(), 0, [&grid_tiles, &block_type](int acc, const Region& reg) -> int { return acc + grid_tiles.region_tile_count(reg, &block_type); @@ -43,10 +39,11 @@ bool floorplan_constraints_regions_overfull(const ClusterLegalizer& cluster_lega if (num_assigned_blocks > num_tiles) { floorplan_regions_overfull = true; - floorplanning_ctx.overfull_partition_regions.push_back(pr); - VTR_LOG("\n\nA partition including the following regions has been assigned %d blocks of type %s, " - "but only has %d tiles of that type\n", - num_assigned_blocks, block_type.name.c_str(), num_tiles); + overfull_partition_regions.push_back(pr); + VTR_LOG( + "\n\nA partition including the following regions has been assigned %d blocks of type %s, " + "but only has %d tiles of that type\n", + num_assigned_blocks, block_type.name.c_str(), num_tiles); for (const Region& reg : regions) { const vtr::Rect& rect = reg.get_rect(); const auto [layer_low, layer_high] = reg.get_layer_range(); @@ -55,7 +52,6 @@ bool floorplan_constraints_regions_overfull(const ClusterLegalizer& cluster_lega rect.xmax(), rect.ymax(), layer_high, reg.get_sub_tile()); } - } } } diff --git a/vpr/src/pack/constraints_report.h b/vpr/src/pack/constraints_report.h index c10d1183238..779f629ba69 100644 --- a/vpr/src/pack/constraints_report.h +++ b/vpr/src/pack/constraints_report.h @@ -2,10 +2,13 @@ * floorplan regions have been packed with too many clusters. */ -#ifndef VPR_SRC_PACK_CONSTRAINTS_REPORT_H_ -#define VPR_SRC_PACK_CONSTRAINTS_REPORT_H_ +#pragma once + +#include class ClusterLegalizer; +class PartitionRegion; +struct t_logical_block_type; /** * @brief Check if any constraint partition regions are overfull, @@ -23,8 +26,10 @@ class ClusterLegalizer; * VPR can still work if these assumptions do not hold true, but for tight overlapping * partitions, the placement engine may fail to find a legal placement. * + * Adds the overfilled partition regions to the overfull_partition_regions vector. + * * @return True if there is at least one overfull partition. */ -bool floorplan_constraints_regions_overfull(const ClusterLegalizer& cluster_legalizer); - -#endif /* VPR_SRC_PACK_CONSTRAINTS_REPORT_H_ */ +bool floorplan_constraints_regions_overfull(std::vector& overfull_partition_regions, + const ClusterLegalizer& cluster_legalizer, + const std::vector& logical_block_types); diff --git a/vpr/src/pack/greedy_candidate_selector.cpp b/vpr/src/pack/greedy_candidate_selector.cpp index 1b74a44aa66..b202035ec59 100644 --- a/vpr/src/pack/greedy_candidate_selector.cpp +++ b/vpr/src/pack/greedy_candidate_selector.cpp @@ -7,16 +7,24 @@ #include "greedy_candidate_selector.h" #include +#include +#include +#include +#include "PreClusterTimingManager.h" +#include "appack_context.h" +#include "flat_placement_types.h" +#include "flat_placement_utils.h" #include "atom_netlist.h" #include "attraction_groups.h" #include "cluster_legalizer.h" #include "cluster_placement.h" -#include "globals.h" +#include "greedy_clusterer.h" #include "prepack.h" #include "timing_info.h" -#include "vpr_context.h" #include "vpr_types.h" #include "vtr_assert.h" +#include "vtr_ndmatrix.h" +#include "vtr_vector.h" /* * @brief Get gain of packing molecule into current cluster. @@ -28,12 +36,14 @@ * * TODO: Confirm that this comment is correct. */ -static float get_molecule_gain(t_pack_molecule* molecule, +static float get_molecule_gain(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats, AttractGroupId cluster_attraction_group_id, AttractionInfo& attraction_groups, int num_molecule_failures, - const AtomNetlist& atom_netlist); + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const APPackContext& appack_ctx); /* * @brief Remove blk from list of feasible blocks sorted according to gain. @@ -42,94 +52,177 @@ static float get_molecule_gain(t_pack_molecule* molecule, * has been found to be illegal, we don't repeatedly consider it. */ static void remove_molecule_from_pb_stats_candidates( - t_pack_molecule* molecule, - ClusterGainStats& cluster_gain_stats); + PackMoleculeId molecule_id, + ClusterGainStats& cluster_gain_stats); /* * @brief Add blk to list of feasible blocks sorted according to gain. */ static void add_molecule_to_pb_stats_candidates( - t_pack_molecule* molecule, - ClusterGainStats& cluster_gain_stats, - int max_queue_size, - AttractionInfo& attraction_groups, - const AtomNetlist& atom_netlist); + PackMoleculeId molecule_id, + ClusterGainStats& cluster_gain_stats, + t_logical_block_type_ptr cluster_type, + int max_queue_size, + AttractionInfo& attraction_groups, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const APPackContext& appack_ctx); + +/** + * @brief Get the flat placement position of the given molecule. + */ +static t_flat_pl_loc get_molecule_pos(PackMoleculeId molecule_id, + const Prepacker& prepacker, + const APPackContext& appack_ctx) { + VTR_ASSERT_SAFE_MSG(appack_ctx.appack_options.use_appack, "APPack is not enabled"); + VTR_ASSERT_SAFE_MSG(molecule_id.is_valid(), "Molecule ID is invalid"); + AtomBlockId root_blk_id = prepacker.get_molecule_root_atom(molecule_id); + return appack_ctx.flat_placement_info.get_pos(root_blk_id); +} GreedyCandidateSelector::GreedyCandidateSelector( - const AtomNetlist& atom_netlist, - const Prepacker& prepacker, - const t_packer_opts& packer_opts, - bool allow_unrelated_clustering, - const t_molecule_stats& max_molecule_stats, - const std::map>& primitive_candidate_block_types, - const t_pack_high_fanout_thresholds& high_fanout_thresholds, - const std::unordered_set& is_clock, - const std::unordered_set& is_global, - const std::unordered_set& net_output_feeds_driving_block_input, - const SetupTimingInfo& timing_info, - int log_verbosity) - : atom_netlist_(atom_netlist), - packer_opts_(packer_opts), - allow_unrelated_clustering_(allow_unrelated_clustering), - log_verbosity_(log_verbosity), - primitive_candidate_block_types_(primitive_candidate_block_types), - high_fanout_thresholds_(high_fanout_thresholds), - is_clock_(is_clock), - is_global_(is_global), - net_output_feeds_driving_block_input_(net_output_feeds_driving_block_input), - timing_info_(timing_info) { - // Initialize the list of molecules to pack, the clustering data, and the - // net info. - - // Initialize unrelated clustering data. + const AtomNetlist& atom_netlist, + const Prepacker& prepacker, + const t_packer_opts& packer_opts, + bool allow_unrelated_clustering, + const t_molecule_stats& max_molecule_stats, + const std::map>& primitive_candidate_block_types, + const t_pack_high_fanout_thresholds& high_fanout_thresholds, + const std::unordered_set& is_clock, + const std::unordered_set& is_global, + const std::unordered_set& net_output_feeds_driving_block_input, + const PreClusterTimingManager& pre_cluster_timing_manager, + const APPackContext& appack_ctx, + int log_verbosity) + : atom_netlist_(atom_netlist) + , prepacker_(prepacker) + , packer_opts_(packer_opts) + , allow_unrelated_clustering_(allow_unrelated_clustering) + , log_verbosity_(log_verbosity) + , primitive_candidate_block_types_(primitive_candidate_block_types) + , high_fanout_thresholds_(high_fanout_thresholds) + , is_clock_(is_clock) + , is_global_(is_global) + , net_output_feeds_driving_block_input_(net_output_feeds_driving_block_input) + , pre_cluster_timing_manager_(pre_cluster_timing_manager) + , appack_ctx_(appack_ctx) + , rng_(0) { + + // Initialize unrelated clustering data if unrelated clustering is enabled. if (allow_unrelated_clustering_) { + initialize_unrelated_clustering_data(max_molecule_stats); + } + + /* TODO: This is memory inefficient, fix if causes problems */ + /* Store stats on nets used by packed block, useful for determining transitively connected blocks + * (eg. [A1, A2, ..]->[B1, B2, ..]->C implies cluster [A1, A2, ...] and C have a weak link) */ + clb_inter_blk_nets_.resize(atom_netlist.blocks().size()); +} + +void GreedyCandidateSelector::initialize_unrelated_clustering_data(const t_molecule_stats& max_molecule_stats) { + // Create a sorted list of molecules, sorted on decreasing molecule base + // gain. (Highest gain). + std::vector molecules_vector; + molecules_vector.assign(prepacker_.molecules().begin(), prepacker_.molecules().end()); + std::stable_sort(molecules_vector.begin(), + molecules_vector.end(), + [&](PackMoleculeId a_id, PackMoleculeId b_id) { + const t_pack_molecule& a = prepacker_.get_molecule(a_id); + const t_pack_molecule& b = prepacker_.get_molecule(b_id); + + return a.base_gain > b.base_gain; + }); + + if (appack_ctx_.appack_options.use_appack) { + /** + * For APPack, we build a spatial data structure where for each 1x1 grid + * position on the FPGA, we maintain lists of molecule candidates. + * The lists are in order of number of used external pins by the molecule. + * Within each list, the molecules are sorted by their base gain. + */ + // Get the max x, y, and layer from the flat placement. + t_flat_pl_loc max_loc({0.0f, 0.0f, 0.0f}); + for (PackMoleculeId mol_id : molecules_vector) { + t_flat_pl_loc mol_pos = get_molecule_pos(mol_id, prepacker_, appack_ctx_); + max_loc.x = std::max(max_loc.x, mol_pos.x); + max_loc.y = std::max(max_loc.y, mol_pos.y); + max_loc.layer = std::max(max_loc.layer, mol_pos.layer); + } + + VTR_ASSERT_MSG(max_loc.layer == 0, + "APPack unrelated clustering does not support 3D " + "FPGAs yet"); + + // Initialize the data structure with empty arrays with enough space + // for each molecule. + size_t flat_grid_width = max_loc.x + 1; + size_t flat_grid_height = max_loc.y + 1; + appack_unrelated_clustering_data_ = + vtr::NdMatrix>, 2>({flat_grid_width, + flat_grid_height}); + for (size_t x = 0; x < flat_grid_width; x++) { + for (size_t y = 0; y < flat_grid_height; y++) { + // Resize to the maximum number of used external pins. This is + // to ensure that every molecule below can be inserted into a + // valid list based on their number of external pins. + appack_unrelated_clustering_data_[x][y].resize(max_molecule_stats.num_used_ext_pins + 1); + } + } + + // Fill the grid with molecule information. + // Note: These molecules are sorted based on their base gain. They are + // inserted in such a way that the highest gain molecules appear + // first in the lists below. + for (PackMoleculeId mol_id : molecules_vector) { + t_flat_pl_loc mol_pos = get_molecule_pos(mol_id, prepacker_, appack_ctx_); + + //Figure out how many external inputs are used by this molecule + t_molecule_stats molecule_stats = prepacker_.calc_molecule_stats(mol_id, atom_netlist_); + int ext_inps = molecule_stats.num_used_ext_inputs; + + //Insert the molecule into the unclustered lists by number of external inputs + auto& tile_uc_data = appack_unrelated_clustering_data_[mol_pos.x][mol_pos.y]; + tile_uc_data[ext_inps].push_back(mol_id); + } + } else { + // When not performing APPack, allocate and load a similar data structure + // without spatial information. + /* alloc and load list of molecules to pack */ unrelated_clustering_data_.resize(max_molecule_stats.num_used_ext_inputs + 1); - // Create a sorted list of molecules, sorted on decreasing molecule base - // gain. (Highest gain). - std::vector molecules_vector = prepacker.get_molecules_vector(); - std::stable_sort(molecules_vector.begin(), - molecules_vector.end(), - [](t_pack_molecule* a, t_pack_molecule* b) { - return a->base_gain > b->base_gain; - }); - // Push back the each molecule into the unrelated clustering data vector // for their external inputs. This creates individual sorted lists of // molecules for each number of used external inputs. - for (t_pack_molecule* mol : molecules_vector) { + for (PackMoleculeId mol_id : molecules_vector) { //Figure out how many external inputs are used by this molecule - t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(mol, atom_netlist); + t_molecule_stats molecule_stats = prepacker_.calc_molecule_stats(mol_id, atom_netlist_); int ext_inps = molecule_stats.num_used_ext_inputs; //Insert the molecule into the unclustered lists by number of external inputs - unrelated_clustering_data_[ext_inps].push_back(mol); + unrelated_clustering_data_[ext_inps].push_back(mol_id); } } - - /* TODO: This is memory inefficient, fix if causes problems */ - /* Store stats on nets used by packed block, useful for determining transitively connected blocks - * (eg. [A1, A2, ..]->[B1, B2, ..]->C implies cluster [A1, A2, ...] and C have a weak link) */ - clb_inter_blk_nets_.resize(atom_netlist.blocks().size()); } GreedyCandidateSelector::~GreedyCandidateSelector() { } ClusterGainStats GreedyCandidateSelector::create_cluster_gain_stats( - t_pack_molecule* cluster_seed_mol, - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups) { + PackMoleculeId cluster_seed_mol_id, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { // Initialize the cluster gain stats. ClusterGainStats cluster_gain_stats; + cluster_gain_stats.seed_molecule_id = cluster_seed_mol_id; cluster_gain_stats.num_feasible_blocks = NOT_VALID; + cluster_gain_stats.has_done_connectivity_and_timing = false; // TODO: The reason this is being resized and not reserved is due to legacy // code which should be updated. cluster_gain_stats.feasible_blocks.resize(packer_opts_.feasible_block_array_size); for (int i = 0; i < packer_opts_.feasible_block_array_size; i++) - cluster_gain_stats.feasible_blocks[i] = nullptr; + cluster_gain_stats.feasible_blocks[i] = PackMoleculeId::INVALID(); cluster_gain_stats.tie_break_high_fanout_net = AtomNetId::INVALID(); cluster_gain_stats.explore_transitive_fanout = true; @@ -138,21 +231,41 @@ ClusterGainStats GreedyCandidateSelector::create_cluster_gain_stats( // TODO: We may want to update the cluster gain stats different, knowing // that this candidate was the seed molecule. update_cluster_gain_stats_candidate_success(cluster_gain_stats, - cluster_seed_mol, + cluster_seed_mol_id, cluster_id, cluster_legalizer, attraction_groups); + // If a flat placement is provided, set the centroid to be the location of + // the seed molecule. + if (appack_ctx_.appack_options.use_appack) { + t_flat_pl_loc seed_mol_pos = get_molecule_pos(cluster_seed_mol_id, + prepacker_, + appack_ctx_); + cluster_gain_stats.flat_cluster_position = seed_mol_pos; + cluster_gain_stats.mol_pos_sum = seed_mol_pos; + } + + // Mark if this cluster is a memory block. We detect this by checking if the + // class type of the seed primitive pb is a memory class. + // This is used by APPack to turn off certain optimizations which interfere + // with RAM packing. + const auto& seed_mol = prepacker_.get_molecule(cluster_seed_mol_id); + AtomBlockId seed_atom = seed_mol.atom_block_ids[seed_mol.root]; + const auto seed_pb = cluster_legalizer.atom_pb_lookup().atom_pb(seed_atom); + cluster_gain_stats.is_memory = seed_pb->pb_graph_node->pb_type->class_type == MEMORY_CLASS; + // Return the cluster gain stats. return cluster_gain_stats; } void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( - ClusterGainStats& cluster_gain_stats, - t_pack_molecule* successful_mol, - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups) { + ClusterGainStats& cluster_gain_stats, + PackMoleculeId successful_mol_id, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { + VTR_ASSERT(successful_mol_id.is_valid()); // TODO: If this threshold lookup gets expensive, move outside. int high_fanout_net_threshold = high_fanout_thresholds_.get_threshold(cluster_legalizer.get_cluster_type(cluster_id)->name); @@ -162,9 +275,8 @@ void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( // pins, and clock structures, in order to reflect the new content of the // cluster. Also keeps track of which attraction group the cluster belongs // to. - int molecule_size = get_array_size_of_molecule(successful_mol); - for (int iblock = 0; iblock < molecule_size; iblock++) { - AtomBlockId blk_id = successful_mol->atom_block_ids[iblock]; + const t_pack_molecule& successful_mol = prepacker_.get_molecule(successful_mol_id); + for (AtomBlockId blk_id : successful_mol.atom_block_ids) { if (!blk_id) { continue; } @@ -174,6 +286,7 @@ void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( /* reset list of feasible blocks */ cluster_gain_stats.num_feasible_blocks = NOT_VALID; + cluster_gain_stats.has_done_connectivity_and_timing = false; /* TODO: Allow clusters to have more than one attraction group. */ if (atom_grp_id.is_valid()) cluster_gain_stats.attraction_grp_id = atom_grp_id; @@ -224,26 +337,47 @@ void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( e_net_relation_to_clustered_block::INPUT); } + // TODO: For flat placement reconstruction, should we mark the molecules + // in the same tile as the seed of this cluster? + update_total_gain(cluster_gain_stats, attraction_groups); } // if this molecule came from the transitive fanout candidates remove it - cluster_gain_stats.transitive_fanout_candidates.erase(successful_mol->atom_block_ids[successful_mol->root]); + cluster_gain_stats.transitive_fanout_candidates.erase(successful_mol.atom_block_ids[successful_mol.root]); cluster_gain_stats.explore_transitive_fanout = true; // Whenever a new molecule has been clustered, reset the number of // unrelated clustering attempts. num_unrelated_clustering_attempts_ = 0; + + // If using APPack, update the position of the cluster based on the addition + // of this molecule. + if (appack_ctx_.appack_options.use_appack) { + t_flat_pl_loc successful_mol_pos = get_molecule_pos(successful_mol_id, + prepacker_, + appack_ctx_); + // Accumulate the molecules position into the position sum. + cluster_gain_stats.mol_pos_sum += successful_mol_pos; + + if (appack_ctx_.appack_options.cluster_location_ty == t_appack_options::e_cl_loc_ty::CENTROID) { + // If the cluster's position is defined as the centroid of the + // positions of the mols it contains, compute the new centroid. + cluster_gain_stats.flat_cluster_position = cluster_gain_stats.mol_pos_sum; + size_t num_mols_in_cluster = cluster_legalizer.get_num_molecules_in_cluster(cluster_id); + cluster_gain_stats.flat_cluster_position /= static_cast(num_mols_in_cluster); + } + } } void GreedyCandidateSelector::mark_and_update_partial_gain( - ClusterGainStats& cluster_gain_stats, - AtomNetId net_id, - e_gain_update gain_flag, - AtomBlockId clustered_blk_id, - const ClusterLegalizer& cluster_legalizer, - int high_fanout_net_threshold, - e_net_relation_to_clustered_block net_relation_to_clustered_block) { + ClusterGainStats& cluster_gain_stats, + AtomNetId net_id, + e_gain_update gain_flag, + AtomBlockId clustered_blk_id, + const ClusterLegalizer& cluster_legalizer, + int high_fanout_net_threshold, + e_net_relation_to_clustered_block net_relation_to_clustered_block) { if (int(atom_netlist_.net_sinks(net_id).size()) > high_fanout_net_threshold) { /* Optimization: It can be too runtime costly for marking all sinks for @@ -310,17 +444,13 @@ void GreedyCandidateSelector::mark_and_update_partial_gain( cluster_gain_stats.num_pins_of_net_in_pb[net_id]++; } -/* - * @brief Determine if atom block is in pb. - * - * TODO: This would make more sense in the cluster legalizer class. +/** + * @brief Determine if pb is a child of cluster_pb. */ -static bool is_atom_blk_in_pb(const AtomBlockId blk_id, const t_pb* pb) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); - - const t_pb* cur_pb = atom_ctx.lookup.atom_pb(blk_id); +static bool is_pb_in_cluster_pb(const t_pb* pb, const t_pb* cluster_pb) { + const t_pb* cur_pb = pb; while (cur_pb) { - if (cur_pb == pb) { + if (cur_pb == cluster_pb) { return true; } cur_pb = cur_pb->parent_pb; @@ -329,20 +459,15 @@ static bool is_atom_blk_in_pb(const AtomBlockId blk_id, const t_pb* pb) { } void GreedyCandidateSelector::update_connection_gain_values( - ClusterGainStats& cluster_gain_stats, - AtomNetId net_id, - AtomBlockId clustered_blk_id, - const ClusterLegalizer& cluster_legalizer, - e_net_relation_to_clustered_block net_relation_to_clustered_block) { + ClusterGainStats& cluster_gain_stats, + AtomNetId net_id, + AtomBlockId clustered_blk_id, + const ClusterLegalizer& cluster_legalizer, + e_net_relation_to_clustered_block net_relation_to_clustered_block) { /*This function is called when the connection_gain values on the net net_id *require updating. */ - // Atom Context used to lookup the atom pb. - // TODO: Should investigate this. Using the atom pb in this class is very - // strange. - const AtomContext& atom_ctx = g_vpr_ctx.atom(); - int num_internal_connections, num_open_connections, num_stuck_connections; num_internal_connections = num_open_connections = num_stuck_connections = 0; @@ -351,8 +476,12 @@ void GreedyCandidateSelector::update_connection_gain_values( /* may wish to speed things up by ignoring clock nets since they are high fanout */ for (AtomPinId pin_id : atom_netlist_.net_pins(net_id)) { AtomBlockId blk_id = atom_netlist_.pin_block(pin_id); - if (cluster_legalizer.get_atom_cluster(blk_id) == legalization_cluster_id - && is_atom_blk_in_pb(blk_id, atom_ctx.lookup.atom_pb(clustered_blk_id))) { + // TODO: Should investigate this. Using the atom pb bimap through is_atom_blk_in_cluster_block + // in this class is very strange + const t_pb* pin_block_pb = cluster_legalizer.atom_pb_lookup().atom_pb(blk_id); + const t_pb* cluster_pb = cluster_legalizer.atom_pb_lookup().atom_pb(clustered_blk_id); + + if (cluster_legalizer.get_atom_cluster(blk_id) == legalization_cluster_id && is_pb_in_cluster_pb(pin_block_pb, cluster_pb)) { num_internal_connections++; } else if (!cluster_legalizer.is_atom_clustered(blk_id)) { num_open_connections++; @@ -402,10 +531,10 @@ void GreedyCandidateSelector::update_connection_gain_values( } void GreedyCandidateSelector::update_timing_gain_values( - ClusterGainStats& cluster_gain_stats, - AtomNetId net_id, - const ClusterLegalizer& cluster_legalizer, - e_net_relation_to_clustered_block net_relation_to_clustered_block) { + ClusterGainStats& cluster_gain_stats, + AtomNetId net_id, + const ClusterLegalizer& cluster_legalizer, + e_net_relation_to_clustered_block net_relation_to_clustered_block) { /*This function is called when the timing_gain values on the atom net *net_id requires updating. */ @@ -416,12 +545,15 @@ void GreedyCandidateSelector::update_timing_gain_values( if (net_output_feeds_driving_block_input_.count(net_id) != 0) pins = atom_netlist_.net_sinks(net_id); + // Get the setup timing info used to compute timing gain terms. + const SetupTimingInfo& timing_info = pre_cluster_timing_manager_.get_timing_info(); + if (net_relation_to_clustered_block == e_net_relation_to_clustered_block::OUTPUT && !is_global_.count(net_id)) { for (AtomPinId pin_id : pins) { AtomBlockId blk_id = atom_netlist_.pin_block(pin_id); if (!cluster_legalizer.is_atom_clustered(blk_id)) { - double timing_gain = timing_info_.setup_pin_criticality(pin_id); + double timing_gain = timing_info.setup_pin_criticality(pin_id); if (cluster_gain_stats.timing_gain.count(blk_id) == 0) { cluster_gain_stats.timing_gain[blk_id] = 0; @@ -441,7 +573,7 @@ void GreedyCandidateSelector::update_timing_gain_values( if (!cluster_legalizer.is_atom_clustered(new_blk_id)) { for (AtomPinId pin_id : atom_netlist_.net_sinks(net_id)) { - double timing_gain = timing_info_.setup_pin_criticality(pin_id); + double timing_gain = timing_info.setup_pin_criticality(pin_id); if (cluster_gain_stats.timing_gain.count(new_blk_id) == 0) { cluster_gain_stats.timing_gain[new_blk_id] = 0; @@ -466,6 +598,9 @@ void GreedyCandidateSelector::update_total_gain(ClusterGainStats& cluster_gain_s if (cluster_gain_stats.sharing_gain.count(blk_id) == 0) { cluster_gain_stats.sharing_gain[blk_id] = 0; } + if (cluster_gain_stats.timing_gain.count(blk_id) == 0) { + cluster_gain_stats.timing_gain[blk_id] = 0; + } AttractGroupId atom_grp_id = attraction_groups.get_atom_attraction_group(blk_id); if (atom_grp_id != AttractGroupId::INVALID() && atom_grp_id == cluster_att_grp_id) { @@ -486,39 +621,40 @@ void GreedyCandidateSelector::update_total_gain(ClusterGainStats& cluster_gain_s if (packer_opts_.connection_driven) { /*try to absorb as many connections as possible*/ cluster_gain_stats.gain[blk_id] = ((1 - packer_opts_.beta) - * (float)cluster_gain_stats.sharing_gain[blk_id] - + packer_opts_.beta * (float)cluster_gain_stats.connection_gain[blk_id]) - / (num_used_pins); + * (float)cluster_gain_stats.sharing_gain[blk_id] + + packer_opts_.beta * (float)cluster_gain_stats.connection_gain[blk_id]) + / (num_used_pins); } else { cluster_gain_stats.gain[blk_id] = ((float)cluster_gain_stats.sharing_gain[blk_id]) - / (num_used_pins); + / (num_used_pins); } /* Add in timing driven cost into cost function */ if (packer_opts_.timing_driven) { cluster_gain_stats.gain[blk_id] = packer_opts_.alpha - * cluster_gain_stats.timing_gain[blk_id] - + (1.0 - packer_opts_.alpha) * (float)cluster_gain_stats.gain[blk_id]; + * cluster_gain_stats.timing_gain[blk_id] + + (1.0 - packer_opts_.alpha) * (float)cluster_gain_stats.gain[blk_id]; } } } -void GreedyCandidateSelector::update_cluster_gain_stats_candidate_failed(ClusterGainStats& cluster_gain_stats, - t_pack_molecule* failed_mol) { - auto got = cluster_gain_stats.atom_failures.find(failed_mol->atom_block_ids[0]); - if (got == cluster_gain_stats.atom_failures.end()) { - cluster_gain_stats.atom_failures.insert({failed_mol->atom_block_ids[0], 1}); +void GreedyCandidateSelector::update_cluster_gain_stats_candidate_failed( + ClusterGainStats& cluster_gain_stats, + PackMoleculeId failed_mol_id) { + VTR_ASSERT(failed_mol_id.is_valid()); + auto got = cluster_gain_stats.mol_failures.find(failed_mol_id); + if (got == cluster_gain_stats.mol_failures.end()) { + cluster_gain_stats.mol_failures.insert({failed_mol_id, 1}); } else { got->second++; } } -t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer, - const Prepacker& prepacker, - AttractionInfo& attraction_groups) { +PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { /* Finds the block with the greatest gain that satisfies the * input, clock and capacity constraints of a cluster that are * passed in. If no suitable block is found it returns nullptr. @@ -546,11 +682,12 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( // 1. Find unpacked molecules based on criticality and strong connectedness (connected by low fanout nets) with current cluster if (cluster_gain_stats.num_feasible_blocks == NOT_VALID) { + cluster_gain_stats.num_feasible_blocks = 0; add_cluster_molecule_candidates_by_connectivity_and_timing(cluster_gain_stats, cluster_id, - prepacker, cluster_legalizer, attraction_groups); + cluster_gain_stats.has_done_connectivity_and_timing = true; } if (packer_opts_.prioritize_transitive_connectivity) { @@ -558,7 +695,6 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.explore_transitive_fanout) { add_cluster_molecule_candidates_by_transitive_connectivity(cluster_gain_stats, cluster_id, - prepacker, cluster_legalizer, attraction_groups); } @@ -567,7 +703,6 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.tie_break_high_fanout_net) { add_cluster_molecule_candidates_by_highfanout_connectivity(cluster_gain_stats, cluster_id, - prepacker, cluster_legalizer, attraction_groups); } @@ -576,7 +711,6 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.tie_break_high_fanout_net) { add_cluster_molecule_candidates_by_highfanout_connectivity(cluster_gain_stats, cluster_id, - prepacker, cluster_legalizer, attraction_groups); } @@ -585,7 +719,6 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.explore_transitive_fanout) { add_cluster_molecule_candidates_by_transitive_connectivity(cluster_gain_stats, cluster_id, - prepacker, cluster_legalizer, attraction_groups); } @@ -595,13 +728,13 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( if (cluster_gain_stats.num_feasible_blocks == 0) { add_cluster_molecule_candidates_by_attraction_group(cluster_gain_stats, cluster_id, - prepacker, cluster_legalizer, attraction_groups); } + /* Grab highest gain molecule */ // If this was a vector, this would just be a pop_back. - t_pack_molecule* best_molecule = nullptr; + PackMoleculeId best_molecule = PackMoleculeId::INVALID(); if (cluster_gain_stats.num_feasible_blocks > 0) { cluster_gain_stats.num_feasible_blocks--; int index = cluster_gain_stats.num_feasible_blocks; @@ -611,16 +744,24 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( // If we are allowing unrelated clustering and no molecule has been found, // get unrelated candidate for cluster. - if (allow_unrelated_clustering_ && best_molecule == nullptr) { - if (num_unrelated_clustering_attempts_ < max_unrelated_clustering_attempts_) { - best_molecule = get_unrelated_candidate_for_cluster(cluster_id, - cluster_legalizer); - num_unrelated_clustering_attempts_++; - VTR_LOGV(best_molecule && log_verbosity_ > 2, - "\tFound unrelated molecule to cluster\n"); + if (allow_unrelated_clustering_ && best_molecule == PackMoleculeId::INVALID()) { + const t_appack_options& appack_options = appack_ctx_.appack_options; + if (appack_options.use_appack) { + if (num_unrelated_clustering_attempts_ < appack_options.max_unrelated_clustering_attempts) { + best_molecule = get_unrelated_candidate_for_cluster_appack(cluster_gain_stats, + cluster_id, + cluster_legalizer); + num_unrelated_clustering_attempts_++; + } } else { - num_unrelated_clustering_attempts_ = 0; + if (num_unrelated_clustering_attempts_ < max_unrelated_clustering_attempts_) { + best_molecule = get_unrelated_candidate_for_cluster(cluster_id, + cluster_legalizer); + num_unrelated_clustering_attempts_++; + } } + VTR_LOGV(best_molecule && log_verbosity_ > 2, + "\tFound unrelated molecule to cluster\n"); } else { VTR_LOGV(!best_molecule && log_verbosity_ > 2, "\tNo related molecule found and unrelated clustering disabled\n"); @@ -630,68 +771,65 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( } void GreedyCandidateSelector::add_cluster_molecule_candidates_by_connectivity_and_timing( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups) { - VTR_ASSERT(cluster_gain_stats.num_feasible_blocks == NOT_VALID); - - cluster_gain_stats.num_feasible_blocks = 0; + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { cluster_gain_stats.explore_transitive_fanout = true; /* If no legal molecules found, enable exploration of molecules two hops away */ for (AtomBlockId blk_id : cluster_gain_stats.marked_blocks) { // Get the molecule that contains this block. - t_pack_molecule* molecule = prepacker.get_atom_molecule(blk_id); + PackMoleculeId molecule_id = prepacker_.get_atom_molecule(blk_id); // Add the molecule as a candidate if the molecule is not clustered and // is compatible with this cluster (using simple checks). - if (!cluster_legalizer.is_mol_clustered(molecule) && - cluster_legalizer.is_molecule_compatible(molecule, legalization_cluster_id)) { - add_molecule_to_pb_stats_candidates(molecule, + if (!cluster_legalizer.is_mol_clustered(molecule_id) && cluster_legalizer.is_molecule_compatible(molecule_id, legalization_cluster_id)) { + add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, + cluster_legalizer.get_cluster_type(legalization_cluster_id), packer_opts_.feasible_block_array_size, attraction_groups, - atom_netlist_); + prepacker_, + atom_netlist_, + appack_ctx_); } } } void GreedyCandidateSelector::add_cluster_molecule_candidates_by_transitive_connectivity( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups) { + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { //TODO: For now, only done by fan-out; should also consider fan-in cluster_gain_stats.explore_transitive_fanout = false; /* First time finding transitive fanout candidates therefore alloc and load them */ load_transitive_fanout_candidates(cluster_gain_stats, legalization_cluster_id, - prepacker, cluster_legalizer); /* Only consider candidates that pass a very simple legality check */ for (const auto& transitive_candidate : cluster_gain_stats.transitive_fanout_candidates) { - t_pack_molecule* molecule = transitive_candidate.second; - if (!cluster_legalizer.is_mol_clustered(molecule) && - cluster_legalizer.is_molecule_compatible(molecule, legalization_cluster_id)) { - add_molecule_to_pb_stats_candidates(molecule, + PackMoleculeId molecule_id = transitive_candidate.second; + if (!cluster_legalizer.is_mol_clustered(molecule_id) && cluster_legalizer.is_molecule_compatible(molecule_id, legalization_cluster_id)) { + add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, + cluster_legalizer.get_cluster_type(legalization_cluster_id), std::min(packer_opts_.feasible_block_array_size, AAPACK_MAX_TRANSITIVE_EXPLORE), attraction_groups, - atom_netlist_); + prepacker_, + atom_netlist_, + appack_ctx_); } } } void GreedyCandidateSelector::add_cluster_molecule_candidates_by_highfanout_connectivity( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups) { + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { /* Because the packer ignores high fanout nets when marking what blocks * to consider, use one of the ignored high fanout net to fill up lightly * related blocks */ @@ -706,15 +844,17 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_highfanout_conn AtomBlockId blk_id = atom_netlist_.pin_block(pin_id); - t_pack_molecule* molecule = prepacker.get_atom_molecule(blk_id); - if (!cluster_legalizer.is_mol_clustered(molecule) && - cluster_legalizer.is_molecule_compatible(molecule, legalization_cluster_id)) { - add_molecule_to_pb_stats_candidates(molecule, + PackMoleculeId molecule_id = prepacker_.get_atom_molecule(blk_id); + if (!cluster_legalizer.is_mol_clustered(molecule_id) && cluster_legalizer.is_molecule_compatible(molecule_id, legalization_cluster_id)) { + add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, + cluster_legalizer.get_cluster_type(legalization_cluster_id), std::min(packer_opts_.feasible_block_array_size, AAPACK_MAX_HIGH_FANOUT_EXPLORE), attraction_groups, - atom_netlist_); + prepacker_, + atom_netlist_, + appack_ctx_); count++; } } @@ -722,11 +862,10 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_highfanout_conn } void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_group( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups) { + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { auto cluster_type = cluster_legalizer.get_cluster_type(legalization_cluster_id); /* @@ -766,42 +905,38 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou if (num_available_atoms < attraction_group_num_atoms_threshold_) { for (AtomBlockId atom_id : available_atoms) { //Only consider molecules that are unpacked and of the correct type - t_pack_molecule* molecule = prepacker.get_atom_molecule(atom_id); - if (!cluster_legalizer.is_mol_clustered(molecule) && - cluster_legalizer.is_molecule_compatible(molecule, legalization_cluster_id)) { - add_molecule_to_pb_stats_candidates(molecule, + PackMoleculeId molecule_id = prepacker_.get_atom_molecule(atom_id); + if (!cluster_legalizer.is_mol_clustered(molecule_id) && cluster_legalizer.is_molecule_compatible(molecule_id, legalization_cluster_id)) { + add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, + cluster_legalizer.get_cluster_type(legalization_cluster_id), packer_opts_.feasible_block_array_size, attraction_groups, - atom_netlist_); + prepacker_, + atom_netlist_, + appack_ctx_); } } return; } - int min = 0; - int max = num_available_atoms - 1; - for (int j = 0; j < attraction_group_num_atoms_threshold_; j++) { - // FIXME: This is a non-deterministic random number generator and it is - // overkill to what this needs to be. Should use vtr::irand which - // would be faster. - std::random_device rd; - std::mt19937 gen(rd()); - std::uniform_int_distribution<> distr(min, max); - int selected_atom = distr(gen); + //Get a random atom between 0 and the number of available atoms - 1 + int selected_atom = rng_.irand(num_available_atoms - 1); AtomBlockId blk_id = available_atoms[selected_atom]; //Only consider molecules that are unpacked and of the correct type - t_pack_molecule* molecule = prepacker.get_atom_molecule(blk_id); - if (!cluster_legalizer.is_mol_clustered(molecule) && - cluster_legalizer.is_molecule_compatible(molecule, legalization_cluster_id)) { - add_molecule_to_pb_stats_candidates(molecule, + PackMoleculeId molecule_id = prepacker_.get_atom_molecule(blk_id); + if (!cluster_legalizer.is_mol_clustered(molecule_id) && cluster_legalizer.is_molecule_compatible(molecule_id, legalization_cluster_id)) { + add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, + cluster_legalizer.get_cluster_type(legalization_cluster_id), packer_opts_.feasible_block_array_size, attraction_groups, - atom_netlist_); + prepacker_, + atom_netlist_, + appack_ctx_); } } } @@ -809,11 +944,40 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou /* * @brief Add blk to list of feasible blocks sorted according to gain. */ -static void add_molecule_to_pb_stats_candidates(t_pack_molecule* molecule, +static void add_molecule_to_pb_stats_candidates(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats, + t_logical_block_type_ptr cluster_type, int max_queue_size, AttractionInfo& attraction_groups, - const AtomNetlist& atom_netlist) { + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const APPackContext& appack_ctx) { + + // If using APPack, before adding this molecule to the candidates, check to + // see if the molecule is too far away from the position of the cluster. + // If so, do not add it to the list of candidates. + if (appack_ctx.appack_options.use_appack) { + // If this cluster is a memory block, do not drop candidates based on + // distance. Was found to create too many RAM blocks. + if (!cluster_gain_stats.is_memory) { + // Get the max dist for this block type. + float max_dist = appack_ctx.appack_options.max_candidate_distance; + // If this cluster is anything but a logic block type, then scale + // up the max distance. + if (cluster_type->index != appack_ctx.appack_options.logic_block_type_index) + max_dist *= appack_ctx.appack_options.max_candidate_distance_non_lb_scale; + + // If the distance from the cluster to the candidate is too large, + // do not add this molecule to the list of candidates. + const t_flat_pl_loc mol_loc = get_molecule_pos(molecule_id, + prepacker, + appack_ctx); + float dist = get_manhattan_distance(mol_loc, cluster_gain_stats.flat_cluster_position); + if (dist > max_dist) + return; + } + } + int num_molecule_failures = 0; AttractGroupId cluster_att_grp = cluster_gain_stats.attraction_grp_id; @@ -823,55 +987,56 @@ static void add_molecule_to_pb_stats_candidates(t_pack_molecule* molecule, * more molecules helps to achieve this purpose. */ if (attraction_groups.num_attraction_groups() > 0) { - auto got = cluster_gain_stats.atom_failures.find(molecule->atom_block_ids[0]); - if (got == cluster_gain_stats.atom_failures.end()) { + VTR_ASSERT(molecule_id.is_valid()); + auto got = cluster_gain_stats.mol_failures.find(molecule_id); + if (got == cluster_gain_stats.mol_failures.end()) { num_molecule_failures = 0; } else { num_molecule_failures = got->second; } if (num_molecule_failures > 0) { - remove_molecule_from_pb_stats_candidates(molecule, cluster_gain_stats); + remove_molecule_from_pb_stats_candidates(molecule_id, cluster_gain_stats); return; } } for (int i = 0; i < cluster_gain_stats.num_feasible_blocks; i++) { - if (cluster_gain_stats.feasible_blocks[i] == molecule) { + if (cluster_gain_stats.feasible_blocks[i] == molecule_id) { return; // already in queue, do nothing } } if (cluster_gain_stats.num_feasible_blocks >= max_queue_size - 1) { /* maximum size for array, remove smallest gain element and sort */ - if (get_molecule_gain(molecule, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, atom_netlist) > get_molecule_gain(cluster_gain_stats.feasible_blocks[0], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, atom_netlist)) { + if (get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) > get_molecule_gain(cluster_gain_stats.feasible_blocks[0], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { /* single loop insertion sort */ int j; for (j = 0; j < cluster_gain_stats.num_feasible_blocks - 1; j++) { - if (get_molecule_gain(molecule, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, atom_netlist) <= get_molecule_gain(cluster_gain_stats.feasible_blocks[j + 1], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, atom_netlist)) { - cluster_gain_stats.feasible_blocks[j] = molecule; + if (get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) <= get_molecule_gain(cluster_gain_stats.feasible_blocks[j + 1], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { + cluster_gain_stats.feasible_blocks[j] = molecule_id; break; } else { cluster_gain_stats.feasible_blocks[j] = cluster_gain_stats.feasible_blocks[j + 1]; } } if (j == cluster_gain_stats.num_feasible_blocks - 1) { - cluster_gain_stats.feasible_blocks[j] = molecule; + cluster_gain_stats.feasible_blocks[j] = molecule_id; } } } else { /* Expand array and single loop insertion sort */ int j; for (j = cluster_gain_stats.num_feasible_blocks - 1; j >= 0; j--) { - if (get_molecule_gain(cluster_gain_stats.feasible_blocks[j], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, atom_netlist) > get_molecule_gain(molecule, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, atom_netlist)) { + if (get_molecule_gain(cluster_gain_stats.feasible_blocks[j], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) > get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { cluster_gain_stats.feasible_blocks[j + 1] = cluster_gain_stats.feasible_blocks[j]; } else { - cluster_gain_stats.feasible_blocks[j + 1] = molecule; + cluster_gain_stats.feasible_blocks[j + 1] = molecule_id; break; } } if (j < 0) { - cluster_gain_stats.feasible_blocks[0] = molecule; + cluster_gain_stats.feasible_blocks[0] = molecule_id; } cluster_gain_stats.num_feasible_blocks++; } @@ -883,14 +1048,14 @@ static void add_molecule_to_pb_stats_candidates(t_pack_molecule* molecule, * Useful for removing blocks that are repeatedly failing. If a block * has been found to be illegal, we don't repeatedly consider it. */ -static void remove_molecule_from_pb_stats_candidates(t_pack_molecule* molecule, +static void remove_molecule_from_pb_stats_candidates(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats) { int molecule_index; bool found_molecule = false; //find the molecule index for (int i = 0; i < cluster_gain_stats.num_feasible_blocks; i++) { - if (cluster_gain_stats.feasible_blocks[i] == molecule) { + if (cluster_gain_stats.feasible_blocks[i] == molecule_id) { found_molecule = true; molecule_index = i; } @@ -916,68 +1081,97 @@ static void remove_molecule_from_pb_stats_candidates(t_pack_molecule* molecule, * + molecule_base_gain*some_factor * - introduced_input_nets_of_unrelated_blocks_pulled_in_by_molecule*some_other_factor */ -static float get_molecule_gain(t_pack_molecule* molecule, +static float get_molecule_gain(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats, AttractGroupId cluster_attraction_group_id, AttractionInfo& attraction_groups, int num_molecule_failures, - const AtomNetlist& atom_netlist) { + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const APPackContext& appack_ctx) { + VTR_ASSERT(molecule_id.is_valid()); + const t_pack_molecule& molecule = prepacker.get_molecule(molecule_id); + float gain = 0; constexpr float attraction_group_penalty = 0.1; int num_introduced_inputs_of_indirectly_related_block = 0; - for (int i = 0; i < get_array_size_of_molecule(molecule); i++) { - AtomBlockId blk_id = molecule->atom_block_ids[i]; - if (blk_id) { - if (cluster_gain_stats.gain.count(blk_id) > 0) { - gain += cluster_gain_stats.gain[blk_id]; - } else { - /* This block has no connection with current cluster, penalize molecule for having this block - */ - for (auto pin_id : atom_netlist.block_input_pins(blk_id)) { - auto net_id = atom_netlist.pin_net(pin_id); - VTR_ASSERT(net_id); - - auto driver_pin_id = atom_netlist.net_driver(net_id); - VTR_ASSERT(driver_pin_id); - - auto driver_blk_id = atom_netlist.pin_block(driver_pin_id); - - num_introduced_inputs_of_indirectly_related_block++; - for (int iblk = 0; iblk < get_array_size_of_molecule(molecule); iblk++) { - if (molecule->atom_block_ids[iblk] && driver_blk_id == molecule->atom_block_ids[iblk]) { - //valid block which is driver (and hence not an input) - num_introduced_inputs_of_indirectly_related_block--; - break; - } + for (AtomBlockId blk_id : molecule.atom_block_ids) { + if (!blk_id.is_valid()) + continue; + + if (cluster_gain_stats.gain.count(blk_id) > 0) { + gain += cluster_gain_stats.gain[blk_id]; + } else { + /* This block has no connection with current cluster, penalize molecule for having this block + */ + for (auto pin_id : atom_netlist.block_input_pins(blk_id)) { + auto net_id = atom_netlist.pin_net(pin_id); + VTR_ASSERT(net_id); + + auto driver_pin_id = atom_netlist.net_driver(net_id); + VTR_ASSERT(driver_pin_id); + + auto driver_blk_id = atom_netlist.pin_block(driver_pin_id); + + num_introduced_inputs_of_indirectly_related_block++; + for (AtomBlockId blk_id_2 : molecule.atom_block_ids) { + if (blk_id_2.is_valid() && driver_blk_id == blk_id_2) { + //valid block which is driver (and hence not an input) + num_introduced_inputs_of_indirectly_related_block--; + break; } } } - AttractGroupId atom_grp_id = attraction_groups.get_atom_attraction_group(blk_id); - if (atom_grp_id == cluster_attraction_group_id && cluster_attraction_group_id != AttractGroupId::INVALID()) { - float att_grp_gain = attraction_groups.get_attraction_group_gain(atom_grp_id); - gain += att_grp_gain; - } else if (cluster_attraction_group_id != AttractGroupId::INVALID() && atom_grp_id != cluster_attraction_group_id) { - gain -= attraction_group_penalty; - } + } + AttractGroupId atom_grp_id = attraction_groups.get_atom_attraction_group(blk_id); + if (atom_grp_id == cluster_attraction_group_id && cluster_attraction_group_id != AttractGroupId::INVALID()) { + float att_grp_gain = attraction_groups.get_attraction_group_gain(atom_grp_id); + gain += att_grp_gain; + } else if (cluster_attraction_group_id != AttractGroupId::INVALID() && atom_grp_id != cluster_attraction_group_id) { + gain -= attraction_group_penalty; } } - gain += molecule->base_gain * 0.0001; /* Use base gain as tie breaker TODO: need to sweep this value and perhaps normalize */ + gain += molecule.base_gain * 0.0001; /* Use base gain as tie breaker TODO: need to sweep this value and perhaps normalize */ gain -= num_introduced_inputs_of_indirectly_related_block * (0.001); if (num_molecule_failures > 0 && attraction_groups.num_attraction_groups() > 0) { gain -= 0.1 * num_molecule_failures; } + // If using APPack, attenuate the gain. + // NOTE: We do not perform gain attenuation if the current cluster is a memory. + // It was found that attenuation caused RAMs to have issues packing. + // FIXME: What to do when the gain is negative? Should we divide by the attenuation? + // Also what happens when we try to merge in atoms from the flat placement + // which are not connected to anything inside the cluster? + const t_appack_options& appack_options = appack_ctx.appack_options; + if (appack_options.use_appack && gain > 0.f && !cluster_gain_stats.is_memory) { + // Get the position of the molecule + t_flat_pl_loc target_loc = get_molecule_pos(molecule_id, prepacker, appack_ctx); + + // Compute the gain attenuatation term. + float dist = get_manhattan_distance(cluster_gain_stats.flat_cluster_position, target_loc); + float gain_mult = 1.0f; + if (dist < appack_options.dist_th) { + gain_mult = 1.0f - (appack_options.quad_fac_sqr * dist * dist); + } else { + gain_mult = 1.0f / std::sqrt(dist - appack_options.sqrt_offset); + } + VTR_ASSERT_SAFE(gain_mult >= 0.0f && gain_mult <= 1.0f); + + // Update the gain. + gain *= gain_mult; + } + return gain; } void GreedyCandidateSelector::load_transitive_fanout_candidates( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer) { + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer) { // iterate over all the nets that have pins in this cluster for (AtomNetId net_id : cluster_gain_stats.marked_nets) { // only consider small nets to constrain runtime @@ -1011,18 +1205,19 @@ void GreedyCandidateSelector::load_transitive_fanout_candidates( } else { cluster_gain_stats.gain[blk_id] += 0.001; } - t_pack_molecule* molecule = prepacker.get_atom_molecule(blk_id); - VTR_ASSERT(!cluster_legalizer.is_mol_clustered(molecule)); - transitive_fanout_candidates.insert({molecule->atom_block_ids[molecule->root], molecule}); + PackMoleculeId molecule_id = prepacker_.get_atom_molecule(blk_id); + VTR_ASSERT(!cluster_legalizer.is_mol_clustered(molecule_id)); + const t_pack_molecule& molecule = prepacker_.get_molecule(molecule_id); + transitive_fanout_candidates.insert({molecule.atom_block_ids[molecule.root], molecule_id}); } } } } } -t_pack_molecule* GreedyCandidateSelector::get_unrelated_candidate_for_cluster( - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer) { +PackMoleculeId GreedyCandidateSelector::get_unrelated_candidate_for_cluster( + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer) { // Necessary data structures are only allocated in unrelated clustering is // on. VTR_ASSERT(allow_unrelated_clustering_); @@ -1039,31 +1234,140 @@ t_pack_molecule* GreedyCandidateSelector::get_unrelated_candidate_for_cluster( for (int ext_inps = inputs_avail; ext_inps >= 0; ext_inps--) { // Get the molecule by the number of external inputs. - t_pack_molecule* molecule = nullptr; - for (t_pack_molecule* mol : unrelated_clustering_data_[ext_inps]) { + PackMoleculeId molecule = PackMoleculeId::INVALID(); + for (PackMoleculeId mol_id : unrelated_clustering_data_[ext_inps]) { /* TODO: Get better candidate atom block in future, eg. return most timing critical or some other smarter metric */ - if (!cluster_legalizer.is_mol_clustered(mol)) { + if (!cluster_legalizer.is_mol_clustered(mol_id)) { /* TODO: I should be using a better filtering check especially when I'm * dealing with multiple clock/multiple global reset signals where the clock/reset * packed in matters, need to do later when I have the circuits to check my work */ - if (cluster_legalizer.is_molecule_compatible(mol, cluster_id)) { - molecule = mol; + if (cluster_legalizer.is_molecule_compatible(mol_id, cluster_id)) { + molecule = mol_id; break; } } } // If a molecule could be found, return it. - if (molecule != nullptr) + if (molecule.is_valid()) return molecule; } // If no molecule could be found, return nullptr. - return nullptr; + return PackMoleculeId::INVALID(); +} + +PackMoleculeId GreedyCandidateSelector::get_unrelated_candidate_for_cluster_appack( + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer) { + + /** + * For APPack, we want to find a close candidate with the highest number + * of available inputs which could be packed into the given cluster. + * We will search for candidates in a BFS manner, where we will search in + * the same 1x1 grid location of the cluster for a compatible candidate, and + * will then search out if none can be found. + * + * Here, a molecule is compatible if: + * - It has not been clustered already + * - The number of inputs it has available is less than or equal to the + * number of inputs available in the cluster. + * - It has not tried to be packed in this cluster before. + * - It is compatible with the cluster. + */ + + VTR_ASSERT_MSG(allow_unrelated_clustering_, + "Cannot get unrelated candidates when unrelated clustering " + "is disabled"); + + VTR_ASSERT_MSG(appack_ctx_.appack_options.use_appack, + "APPack is disabled, cannot get unrelated clusters using " + "flat placement information"); + + // The cluster will likely have more inputs available than a single molecule + // would have available (clusters have more pins). Clamp the inputs available + // to the max number of inputs a molecule could have. + size_t inputs_avail = cluster_legalizer.get_num_cluster_inputs_available(cluster_id); + VTR_ASSERT_SAFE(!appack_unrelated_clustering_data_.empty()); + size_t max_molecule_inputs_avail = appack_unrelated_clustering_data_[0][0].size() - 1; + if (inputs_avail >= max_molecule_inputs_avail) { + inputs_avail = max_molecule_inputs_avail; + } + + // Create a queue of locations to search and a map of visited grid locations. + std::queue search_queue; + vtr::NdMatrix visited({appack_unrelated_clustering_data_.dim_size(0), + appack_unrelated_clustering_data_.dim_size(1)}, + false); + // Push the position of the cluster to the queue. + search_queue.push(cluster_gain_stats.flat_cluster_position); + + while (!search_queue.empty()) { + // Pop a position to search from the queue. + const t_flat_pl_loc& node_loc = search_queue.front(); + VTR_ASSERT_SAFE(node_loc.layer == 0); + + // If this position is too far from the source, skip it. + float dist = get_manhattan_distance(node_loc, cluster_gain_stats.flat_cluster_position); + if (dist > 1) { + search_queue.pop(); + continue; + } + + // If this position has been visited, skip it. + if (visited[node_loc.x][node_loc.y]) { + search_queue.pop(); + continue; + } + visited[node_loc.x][node_loc.y] = true; + + // Explore this position from highest number of inputs available to lowest. + const auto& uc_data = appack_unrelated_clustering_data_[node_loc.x][node_loc.y]; + VTR_ASSERT_SAFE(inputs_avail < uc_data.size()); + for (int ext_inps = inputs_avail; ext_inps >= 0; ext_inps--) { + // Get the molecule by the number of external inputs. + for (PackMoleculeId mol_id : uc_data[ext_inps]) { + // If this molecule has been clustered, skip it. + if (cluster_legalizer.is_mol_clustered(mol_id)) + continue; + // If this molecule has tried to be packed before and failed + // do not try it. This also means that this molecule may be + // related to this cluster in some way. + if (cluster_gain_stats.mol_failures.find(mol_id) != cluster_gain_stats.mol_failures.end()) + continue; + // If this molecule is not compatible with the current cluster + // skip it. + if (!cluster_legalizer.is_molecule_compatible(mol_id, cluster_id)) + continue; + // Return this molecule as the unrelated candidate. + return mol_id; + } + } + + // Push the neighbors of the position to the queue. + // Note: Here, we are using the manhattan distance, so we do not push + // the diagonals. We also want to try the direct neighbors first + // since they should be closer. + if (node_loc.x >= 1.0f) + search_queue.push({node_loc.x - 1, node_loc.y, node_loc.layer}); + if (node_loc.x <= visited.dim_size(0) - 2) + search_queue.push({node_loc.x + 1, node_loc.y, node_loc.layer}); + if (node_loc.y >= 1.0f) + search_queue.push({node_loc.x, node_loc.y - 1, node_loc.layer}); + if (node_loc.y <= visited.dim_size(1) - 2) + search_queue.push({node_loc.x, node_loc.y + 1, node_loc.layer}); + + // Pop the position off the queue. + search_queue.pop(); + } + + // No molecule could be found. Return an invalid ID. + return PackMoleculeId::INVALID(); } void GreedyCandidateSelector::update_candidate_selector_finalize_cluster( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId cluster_id) { + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId cluster_id) { // store info that will be used later in packing. for (const AtomNetId mnet_id : cluster_gain_stats.marked_nets) { int external_terminals = atom_netlist_.net_pins(mnet_id).size() - cluster_gain_stats.num_pins_of_net_in_pb[mnet_id]; @@ -1078,4 +1382,3 @@ void GreedyCandidateSelector::update_candidate_selector_finalize_cluster( } } } - diff --git a/vpr/src/pack/greedy_candidate_selector.h b/vpr/src/pack/greedy_candidate_selector.h index 881e41a4224..2b3eb23a1f5 100644 --- a/vpr/src/pack/greedy_candidate_selector.h +++ b/vpr/src/pack/greedy_candidate_selector.h @@ -12,18 +12,23 @@ #include #include #include +#include "flat_placement_types.h" #include "attraction_groups.h" #include "cluster_legalizer.h" +#include "greedy_clusterer.h" #include "physical_types.h" +#include "prepack.h" +#include "vtr_ndmatrix.h" #include "vtr_vector.h" +#include "vtr_random.h" // Forward declarations class AtomNetlist; class AttractionInfo; +class FlatPlacementInfo; +class PreClusterTimingManager; class Prepacker; -class SetupTimingInfo; class t_pack_high_fanout_thresholds; -class t_pack_molecule; struct t_model; struct t_molecule_stats; struct t_packer_opts; @@ -36,6 +41,14 @@ struct t_packer_opts; * into the given cluster. */ struct ClusterGainStats { + /// @brief The seed molecule used to create this cluster. + PackMoleculeId seed_molecule_id = PackMoleculeId::INVALID(); + + /// @brief Has this cluster tried to get candidates by connectivity and + /// timing yet. This helps ensure that we only do that once per + /// cluster candidate proposal. + bool has_done_connectivity_and_timing = false; + /// @brief Attraction (inverse of cost) function. std::unordered_map gain; @@ -49,12 +62,12 @@ struct ClusterGainStats { /// consideration. std::unordered_map sharing_gain; - /// @brief Stores the number of times atoms have failed to be packed into - /// the cluster. + /// @brief Stores the number of times molecules have failed to be packed + /// into the cluster. /// - /// key: root block id of the molecule, value: number of times the molecule - /// has failed to be packed into the cluster. - std::unordered_map atom_failures; + /// key: molecule id, value: number of times the molecule has failed to be + /// packed into the cluster. + std::unordered_map mol_failures; /// @brief List of nets with the num_pins_of_net_in_pb and gain entries /// altered (i.e. have some gain-related connection to the current @@ -73,7 +86,7 @@ struct ClusterGainStats { /// @brief Holding transitive fanout candidates key: root block id of the /// molecule, value: pointer to the molecule. // TODO: This should be an unordered map, unless stability is desired. - std::map transitive_fanout_candidates; + std::map transitive_fanout_candidates; /// @brief How many pins of each atom net are contained in the currently open pb? std::unordered_map num_pins_of_net_in_pb; @@ -87,8 +100,31 @@ struct ClusterGainStats { /// /// Sorted in ascending gain order so that the last cluster_ctx.blocks is /// the most desirable (this makes it easy to pop blocks off the list. - std::vector feasible_blocks; + std::vector feasible_blocks; int num_feasible_blocks; + + /// @brief The flat placement location of this cluster. + /// + /// This is some function of the positions of the molecules which have been + /// packed into this cluster. How this position is computed is decided by + /// the appack_options passed into the candidate selector class. + /// + /// This is only set and used when APPack is used. + t_flat_pl_loc flat_cluster_position; + + /// @brief The sum of the positions of all molecules in this cluster. + /// + /// This sum can be useful for quickly computing the centroid of this + /// cluster. This sum is updated whenever a molecule is successfully added + /// to the cluster. + /// + /// This is only set and used when APPack is used. + t_flat_pl_loc mol_pos_sum; + + /// @brief Flag to indicate if this cluster is a memory or not. This is + /// set when the stats are created based on the primitive pb type + /// of the seed. + bool is_memory = false; }; /** @@ -111,7 +147,7 @@ struct ClusterGainStats { * ClusterGainStats cluster_gain_stats = candidate_selector.create_cluster_gain_stats(...); * * // Select a candidate to pack into the cluster using the gain stats. - * t_pack_molecule* candidate_mol = candidate_selector.get_next_candidate_for_cluster(cluster_gain_stats, ...); + * PackMoleculeId candidate_mol = candidate_selector.get_next_candidate_for_cluster(cluster_gain_stats, ...); * * // ... (Try to pack the candidate into the cluster) * @@ -129,7 +165,7 @@ struct ClusterGainStats { * candidate_selector.update_candidate_selector_finalize_cluster(cluster_gain_stats, ...); */ class GreedyCandidateSelector { -private: + private: /// @brief How many unrelated candidates can be proposed and not clustered /// in a row. So if an unrelated candidate is successfully clustered, /// the counter is reset. @@ -150,7 +186,7 @@ class GreedyCandidateSelector { /// atoms in the group, or a randomly selected number of them. static constexpr int attraction_group_num_atoms_threshold_ = 500; -public: + public: ~GreedyCandidateSelector(); /** @@ -189,9 +225,13 @@ class GreedyCandidateSelector { * The set of nets whose output feeds the block that drives * itself. This may cause double-counting in the gain * calculations and needs special handling. - * @param timing_info - * Setup timing info for this Atom Netlist. Used to incorporate - * timing / criticality into the gain calculation. + * @param pre_cluster_timing_manager + * Timing manager that holds the information on timing of + * different connections in the circuit. Used for computing + * the timing gain terms. + * @param appack_ctx + * The APPack context which contains options for the flat + * placement guided packing. * @param log_verbosity * The verbosity of log messages in the candidate selector. */ @@ -205,7 +245,8 @@ class GreedyCandidateSelector { const std::unordered_set& is_clock, const std::unordered_set& is_global, const std::unordered_set& net_output_feeds_driving_block_input, - const SetupTimingInfo& timing_info, + const PreClusterTimingManager& pre_cluster_timing_manager, + const APPackContext& appack_ctx, int log_verbosity); /** @@ -229,10 +270,10 @@ class GreedyCandidateSelector { * other. */ ClusterGainStats create_cluster_gain_stats( - t_pack_molecule* cluster_seed_mol, - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups); + PackMoleculeId cluster_seed_mol_id, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /** * @brief Update the cluster gain stats given that the successful_mol was @@ -254,11 +295,11 @@ class GreedyCandidateSelector { * other. */ void update_cluster_gain_stats_candidate_success( - ClusterGainStats& cluster_gain_stats, - t_pack_molecule* successful_mol, - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups); + ClusterGainStats& cluster_gain_stats, + PackMoleculeId successful_mol_id, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /** * @brief Update the cluster gain stats given that the failed_mol was not @@ -273,8 +314,8 @@ class GreedyCandidateSelector { * The molecule that failed to pack into the cluster. */ void update_cluster_gain_stats_candidate_failed( - ClusterGainStats& cluster_gain_stats, - t_pack_molecule* failed_mol); + ClusterGainStats& cluster_gain_stats, + PackMoleculeId failed_mol_id); /** * @brief Given the cluster_gain_stats, select the next candidate molecule @@ -289,19 +330,15 @@ class GreedyCandidateSelector { * The legalization cluster id for the cluster. * @param cluster_legalizer * The legalizer used to create the cluster. - * @param prepacker - * The prepacker used to generate pack-pattern molecules of the - * atoms in the netlist. * @param attraction_groups * Groups of primitives that have extra attraction to each * other. */ - t_pack_molecule* get_next_candidate_for_cluster( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer, - const Prepacker& prepacker, - AttractionInfo& attraction_groups); + PackMoleculeId get_next_candidate_for_cluster( + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /** * @brief Finalize the creation of a cluster. @@ -319,10 +356,27 @@ class GreedyCandidateSelector { * The legalization cluster id of the cluster to finalize. */ void update_candidate_selector_finalize_cluster( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId cluster_id); + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId cluster_id); + + private: + // ===================================================================== // + // Initializing Data Structures + // ===================================================================== // + + /** + * @brief Initialize data structures used for unrelated clustering. + * + * This must be called before using the get_unrelated_candidate methods. + * + * @param max_molecule_stats + * The maximum molecule statistics over all molecules in the design. + * This is used to allocate the data-structures used for unrelated + * clustering. + */ + void initialize_unrelated_clustering_data( + const t_molecule_stats& max_molecule_stats); -private: // ===================================================================== // // Cluster Gain Stats Updating // ===================================================================== // @@ -332,8 +386,8 @@ class GreedyCandidateSelector { * updated when a block is marked. */ enum class e_gain_update : bool { - GAIN, // Update the gains of affected blocks. - NO_GAIN // Do not update the gains of affected blocks. + GAIN, // Update the gains of affected blocks. + NO_GAIN // Do not update the gains of affected blocks. }; /** @@ -341,8 +395,8 @@ class GreedyCandidateSelector { * updating the connection gain values. */ enum class e_net_relation_to_clustered_block : bool { - INPUT, // This is an input net. - OUTPUT // This is an output net. + INPUT, // This is an input net. + OUTPUT // This is an output net. }; /** @@ -392,11 +446,10 @@ class GreedyCandidateSelector { * the list of feasible blocks. */ void add_cluster_molecule_candidates_by_connectivity_and_timing( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups); + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /** * @brief Score unclustered atoms that are two hops away from current @@ -411,32 +464,29 @@ class GreedyCandidateSelector { * This is used when adding molecule candidates by transistive connectivity. */ void load_transitive_fanout_candidates( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer); + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer); /* * @brief Add molecules based on transitive connections (eg. 2 hops away) * with current cluster. */ void add_cluster_molecule_candidates_by_transitive_connectivity( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups); + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /* * @brief Add molecules based on weak connectedness (connected by high * fanout nets) with current cluster. */ void add_cluster_molecule_candidates_by_highfanout_connectivity( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups); + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /* * @brief If the current cluster being packed has an attraction group @@ -450,19 +500,31 @@ class GreedyCandidateSelector { * candidates will vary each time you call this function. */ void add_cluster_molecule_candidates_by_attraction_group( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups); + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /** * @brief Finds a molecule to propose which is unrelated but may be good to * cluster. */ - t_pack_molecule* get_unrelated_candidate_for_cluster( - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer); + PackMoleculeId get_unrelated_candidate_for_cluster( + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer); + + /** + * @brief Finds a molecule to propose which is unrelated to the current + * cluster but may be good to pack. + * + * This uses flat placement information to choose a good candidate. + * + * This returns an invalid molecule ID if a candidate cannot be found. + */ + PackMoleculeId get_unrelated_candidate_for_cluster_appack( + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer); // ===================================================================== // // Internal Variables @@ -471,6 +533,9 @@ class GreedyCandidateSelector { /// @brief The atom netlist to cluster over. const AtomNetlist& atom_netlist_; + /// @brief The prepacker used to pack atoms into molecule pack patterns. + const Prepacker& prepacker_; + /// @brief The packer options used to configure the clusterer. const t_packer_opts& packer_opts_; @@ -501,8 +566,9 @@ class GreedyCandidateSelector { /// drive them. const std::unordered_set& net_output_feeds_driving_block_input_; - /// @brief Setup timing info used to help select critical candidates to pack. - const SetupTimingInfo& timing_info_; + /// @brief The pre-clustering timing manager which holds the timing information + /// of the primitive netlist. + const PreClusterTimingManager& pre_cluster_timing_manager_; /// @brief Inter-block nets within a finalized cluster. Used for finding /// transitive candidates. @@ -511,10 +577,30 @@ class GreedyCandidateSelector { /// @brief Data pre-computed to help select unrelated molecules. This is a /// list of list of molecules sorted by their gain, where the first /// dimension is the number of external outputs of the molecule. - std::vector> unrelated_clustering_data_; + std::vector> unrelated_clustering_data_; + + /// @brief Data pre-computed to help select unrelated molecules when APPack + /// is being used. This is the same data as unrelated_clustering_data_, + /// but it is spatially distributed over the device. + /// For each grid location on the device (x, y), this provides a list of + /// molecules sorted by their gain, where the first dimension is the number + /// of external outputs of the molecule. + /// When APPack is not used, this will be uninitialized. + /// [0..flat_grid_width][0..flat_grid_height][0..max_num_used_ext_pins] + /// Here, flat_grid width/height is the maximum x and y positions given in + /// the flat placement. + vtr::NdMatrix>, 2> appack_unrelated_clustering_data_; + + /// @brief The APPack state which contains the options used to configure + /// APPack and the flat placement. + const APPackContext& appack_ctx_; /// @brief A count on the number of unrelated clustering attempts which /// have been performed. int num_unrelated_clustering_attempts_ = 0; -}; + /// @brief Random number generator used by the clusterer. Currently this + /// is used only when selecting atoms from attraction groups, but + /// could be used for other purposes in the future. + vtr::RngContainer rng_; +}; diff --git a/vpr/src/pack/greedy_clusterer.cpp b/vpr/src/pack/greedy_clusterer.cpp index dd2c9fb4551..7673005af93 100644 --- a/vpr/src/pack/greedy_clusterer.cpp +++ b/vpr/src/pack/greedy_clusterer.cpp @@ -41,15 +41,14 @@ #include #include #include +#include "appack_context.h" #include "SetupGrid.h" #include "atom_netlist.h" #include "attraction_groups.h" #include "cluster_legalizer.h" #include "cluster_util.h" -#include "constraints_report.h" #include "greedy_candidate_selector.h" #include "greedy_seed_selector.h" -#include "pack_types.h" #include "physical_types.h" #include "prepack.h" #include "vpr_context.h" @@ -79,23 +78,26 @@ GreedyClusterer::GreedyClusterer(const t_packer_opts& packer_opts, const t_arch& arch, const t_pack_high_fanout_thresholds& high_fanout_thresholds, const std::unordered_set& is_clock, - const std::unordered_set& is_global) - : packer_opts_(packer_opts), - analysis_opts_(analysis_opts), - atom_netlist_(atom_netlist), - arch_(arch), - high_fanout_thresholds_(high_fanout_thresholds), - is_clock_(is_clock), - is_global_(is_global), - primitive_candidate_block_types_(identify_primitive_candidate_block_types()), - log_verbosity_(packer_opts.pack_verbosity), - net_output_feeds_driving_block_input_(identify_net_output_feeds_driving_block_input(atom_netlist)) { - + const std::unordered_set& is_global, + const PreClusterTimingManager& pre_cluster_timing_manager, + const APPackContext& appack_ctx) + : packer_opts_(packer_opts) + , analysis_opts_(analysis_opts) + , atom_netlist_(atom_netlist) + , arch_(arch) + , high_fanout_thresholds_(high_fanout_thresholds) + , is_clock_(is_clock) + , is_global_(is_global) + , pre_cluster_timing_manager_(pre_cluster_timing_manager) + , appack_ctx_(appack_ctx) + , primitive_candidate_block_types_(identify_primitive_candidate_block_types()) + , log_verbosity_(packer_opts.pack_verbosity) + , net_output_feeds_driving_block_input_(identify_net_output_feeds_driving_block_input(atom_netlist)) { } std::map GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, - Prepacker& prepacker, + const Prepacker& prepacker, bool allow_unrelated_clustering, bool balance_block_type_utilization, AttractionInfo& attraction_groups, @@ -111,19 +113,7 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, // The clustering stats holds information used for logging the progress // of the clustering to the user. t_cluster_progress_stats clustering_stats; - clustering_stats.num_molecules = prepacker.get_num_molecules(); - - // TODO: Create a ClusteringTimingManager class. - // This code relies on the prepacker, once the prepacker is moved to - // the constructor, this code can also move to the constructor. - std::shared_ptr clustering_delay_calc; - std::shared_ptr timing_info; - // Default criticalities set to zero (e.g. if not timing driven) - vtr::vector atom_criticality(atom_netlist_.blocks().size(), 0.f); - if (packer_opts_.timing_driven) { - calc_init_packing_timing(packer_opts_, analysis_opts_, prepacker, - clustering_delay_calc, timing_info, atom_criticality); - } + clustering_stats.num_molecules = prepacker.molecules().size(); // Calculate the max molecule stats, which is used for gain calculation. const t_molecule_stats max_molecule_stats = prepacker.calc_max_molecule_stats(atom_netlist_); @@ -140,7 +130,8 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, is_clock_, is_global_, net_output_feeds_driving_block_input_, - *timing_info, + pre_cluster_timing_manager_, + appack_ctx_, log_verbosity_); // Create the greedy seed selector. @@ -148,11 +139,11 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, prepacker, packer_opts_.cluster_seed_type, max_molecule_stats, - atom_criticality); + pre_cluster_timing_manager_); // Pick the first seed molecule. - t_pack_molecule* seed_mol = seed_selector.get_next_seed(prepacker, - cluster_legalizer); + PackMoleculeId seed_mol_id = seed_selector.get_next_seed(prepacker, + cluster_legalizer); /**************************************************************** * Clustering @@ -162,9 +153,9 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, // Continue clustering as long as a valid seed is returned from the seed // selector. - while (seed_mol != nullptr) { + while (seed_mol_id.is_valid()) { // Check to ensure that this molecule is unclustered. - VTR_ASSERT(!cluster_legalizer.is_mol_clustered(seed_mol)); + VTR_ASSERT(!cluster_legalizer.is_mol_clustered(seed_mol_id)); // The basic algorithm: // 1) Try to put all the molecules in that you can without doing the @@ -175,34 +166,34 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, // Try to grow a cluster from the seed molecule without doing intra-lb // route for each molecule (i.e. just use faster but not fully // conservative legality checks). - LegalizationClusterId new_cluster_id = try_grow_cluster(seed_mol, - candidate_selector, - ClusterLegalizationStrategy::SKIP_INTRA_LB_ROUTE, - cluster_legalizer, - prepacker, - balance_block_type_utilization, - attraction_groups, - num_used_type_instances, - mutable_device_ctx); + LegalizationClusterId new_cluster_id = try_grow_cluster(seed_mol_id, + candidate_selector, + ClusterLegalizationStrategy::SKIP_INTRA_LB_ROUTE, + cluster_legalizer, + prepacker, + balance_block_type_utilization, + attraction_groups, + num_used_type_instances, + mutable_device_ctx); if (!new_cluster_id.is_valid()) { // If the previous strategy failed, try to grow the cluster again, // but this time perform full legalization for each molecule added // to the cluster. - new_cluster_id = try_grow_cluster(seed_mol, - candidate_selector, - ClusterLegalizationStrategy::FULL, - cluster_legalizer, - prepacker, - balance_block_type_utilization, - attraction_groups, - num_used_type_instances, - mutable_device_ctx); + new_cluster_id = try_grow_cluster(seed_mol_id, + candidate_selector, + ClusterLegalizationStrategy::FULL, + cluster_legalizer, + prepacker, + balance_block_type_utilization, + attraction_groups, + num_used_type_instances, + mutable_device_ctx); } // Ensure that the seed was packed successfully. VTR_ASSERT(new_cluster_id.is_valid()); - VTR_ASSERT(cluster_legalizer.is_mol_clustered(seed_mol)); + VTR_ASSERT(cluster_legalizer.is_mol_clustered(seed_mol_id)); // Update the clustering progress stats. size_t num_molecules_in_cluster = cluster_legalizer.get_num_molecules_in_cluster(new_cluster_id); @@ -220,8 +211,8 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, cluster_legalizer); // Pick new seed. - seed_mol = seed_selector.get_next_seed(prepacker, - cluster_legalizer); + seed_mol_id = seed_selector.get_next_seed(prepacker, + cluster_legalizer); } // If this architecture has LE physical block, report its usage. @@ -230,44 +221,43 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, return num_used_type_instances; } -LegalizationClusterId GreedyClusterer::try_grow_cluster( - t_pack_molecule* seed_mol, - GreedyCandidateSelector& candidate_selector, - ClusterLegalizationStrategy strategy, - ClusterLegalizer& cluster_legalizer, - Prepacker& prepacker, - bool balance_block_type_utilization, - AttractionInfo& attraction_groups, - std::map& num_used_type_instances, - DeviceContext& mutable_device_ctx) { +LegalizationClusterId GreedyClusterer::try_grow_cluster(PackMoleculeId seed_mol_id, + GreedyCandidateSelector& candidate_selector, + ClusterLegalizationStrategy strategy, + ClusterLegalizer& cluster_legalizer, + const Prepacker& prepacker, + bool balance_block_type_utilization, + AttractionInfo& attraction_groups, + std::map& num_used_type_instances, + DeviceContext& mutable_device_ctx) { // Check to ensure that this molecule is unclustered. - VTR_ASSERT(!cluster_legalizer.is_mol_clustered(seed_mol)); + VTR_ASSERT(!cluster_legalizer.is_mol_clustered(seed_mol_id)); // Set the legalization strategy of the cluster legalizer. cluster_legalizer.set_legalization_strategy(strategy); // Use the seed to start a new cluster. - LegalizationClusterId legalization_cluster_id = start_new_cluster(seed_mol, + LegalizationClusterId legalization_cluster_id = start_new_cluster(seed_mol_id, cluster_legalizer, + prepacker, balance_block_type_utilization, num_used_type_instances, mutable_device_ctx); // Create the cluster gain stats. This updates the gains in the candidate // selector due to a new molecule being clustered. - ClusterGainStats cluster_gain_stats = candidate_selector.create_cluster_gain_stats(seed_mol, + ClusterGainStats cluster_gain_stats = candidate_selector.create_cluster_gain_stats(seed_mol_id, legalization_cluster_id, cluster_legalizer, attraction_groups); // Select the first candidate molecule to try to add to this cluster. - t_pack_molecule* candidate_mol = candidate_selector.get_next_candidate_for_cluster( - cluster_gain_stats, - legalization_cluster_id, - cluster_legalizer, - prepacker, - attraction_groups); + PackMoleculeId candidate_mol_id = candidate_selector.get_next_candidate_for_cluster( + cluster_gain_stats, + legalization_cluster_id, + cluster_legalizer, + attraction_groups); /* * When attraction groups are created, the purpose is to pack more densely by adding more molecules @@ -286,11 +276,12 @@ LegalizationClusterId GreedyClusterer::try_grow_cluster( // 1) No candidate molecule is proposed. // 2) The same candidate was proposed multiple times. int num_repeated_molecules = 0; - while (candidate_mol != nullptr && num_repeated_molecules < max_num_repeated_molecules) { + while (candidate_mol_id.is_valid() && num_repeated_molecules < max_num_repeated_molecules) { // Try to cluster the candidate molecule into the cluster. - bool success = try_add_candidate_mol_to_cluster(candidate_mol, + bool success = try_add_candidate_mol_to_cluster(candidate_mol_id, legalization_cluster_id, - cluster_legalizer); + cluster_legalizer, + prepacker); // If the candidate molecule was clustered successfully, update // the cluster stats. @@ -298,7 +289,7 @@ LegalizationClusterId GreedyClusterer::try_grow_cluster( // If the last candidate was clustered successfully, update the // gains in the candidate selector. candidate_selector.update_cluster_gain_stats_candidate_success(cluster_gain_stats, - candidate_mol, + candidate_mol_id, legalization_cluster_id, cluster_legalizer, attraction_groups); @@ -306,22 +297,21 @@ LegalizationClusterId GreedyClusterer::try_grow_cluster( // If the last candidate was not clustered successfully, update the // gains in the candidate selector accordingly. candidate_selector.update_cluster_gain_stats_candidate_failed(cluster_gain_stats, - candidate_mol); + candidate_mol_id); } // Get the next candidate molecule. - t_pack_molecule* prev_candidate_mol = candidate_mol; - candidate_mol = candidate_selector.get_next_candidate_for_cluster( - cluster_gain_stats, - legalization_cluster_id, - cluster_legalizer, - prepacker, - attraction_groups); + PackMoleculeId prev_candidate_mol_id = candidate_mol_id; + candidate_mol_id = candidate_selector.get_next_candidate_for_cluster( + cluster_gain_stats, + legalization_cluster_id, + cluster_legalizer, + attraction_groups); // If the next candidate molecule is the same as the previous // candidate molecule, increment the number of repeated // molecules counter. - if (candidate_mol == prev_candidate_mol) + if (candidate_mol_id == prev_candidate_mol_id) num_repeated_molecules++; } @@ -363,14 +353,18 @@ LegalizationClusterId GreedyClusterer::try_grow_cluster( } LegalizationClusterId GreedyClusterer::start_new_cluster( - t_pack_molecule* seed_mol, - ClusterLegalizer& cluster_legalizer, - bool balance_block_type_utilization, - std::map& num_used_type_instances, - DeviceContext& mutable_device_ctx) { + PackMoleculeId seed_mol_id, + ClusterLegalizer& cluster_legalizer, + const Prepacker& prepacker, + bool balance_block_type_utilization, + std::map& num_used_type_instances, + DeviceContext& mutable_device_ctx) { + + VTR_ASSERT(seed_mol_id.is_valid()); + const t_pack_molecule& seed_mol = prepacker.get_molecule(seed_mol_id); /* Allocate a dummy initial cluster and load a atom block as a seed and check if it is legal */ - AtomBlockId root_atom = seed_mol->atom_block_ids[seed_mol->root]; + AtomBlockId root_atom = seed_mol.atom_block_ids[seed_mol.root]; const std::string& root_atom_name = atom_netlist_.block_name(root_atom); const t_model* root_model = atom_netlist_.block_model(root_atom); @@ -402,8 +396,8 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( if (log_verbosity_ > 2) { VTR_LOG("\tSeed: '%s' (%s)", root_atom_name.c_str(), root_model->name); - VTR_LOGV(seed_mol->pack_pattern, " molecule_type %s molecule_size %zu", - seed_mol->pack_pattern->name, seed_mol->atom_block_ids.size()); + VTR_LOGV(seed_mol.pack_pattern, " molecule_type %s molecule_size %zu", + seed_mol.pack_pattern->name, seed_mol.atom_block_ids.size()); VTR_LOG("\n"); } @@ -415,7 +409,7 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( //Try packing into each mode e_block_pack_status pack_result = e_block_pack_status::BLK_STATUS_UNDEFINED; for (int j = 0; j < type->pb_graph_head->pb_type->num_modes && !success; j++) { - std::tie(pack_result, new_cluster_id) = cluster_legalizer.start_new_cluster(seed_mol, type, j); + std::tie(pack_result, new_cluster_id) = cluster_legalizer.start_new_cluster(seed_mol_id, type, j); success = (pack_result == e_block_pack_status::BLK_PASSED); } @@ -431,11 +425,11 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( if (!success) { //Explored all candidates - if (seed_mol->type == MOLECULE_FORCED_PACK) { + if (seed_mol.type == e_pack_pattern_molecule_type::MOLECULE_FORCED_PACK) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "Can not find any logic block that can implement molecule.\n" "\tPattern %s %s\n", - seed_mol->pack_pattern->name, + seed_mol.pack_pattern->name, root_atom_name.c_str()); } else { VPR_FATAL_ERROR(VPR_ERROR_PACK, @@ -478,15 +472,16 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( return new_cluster_id; } -bool GreedyClusterer::try_add_candidate_mol_to_cluster(t_pack_molecule* candidate_mol, +bool GreedyClusterer::try_add_candidate_mol_to_cluster(PackMoleculeId candidate_mol_id, LegalizationClusterId legalization_cluster_id, - ClusterLegalizer& cluster_legalizer) { - VTR_ASSERT(candidate_mol != nullptr); - VTR_ASSERT(!cluster_legalizer.is_mol_clustered(candidate_mol)); + ClusterLegalizer& cluster_legalizer, + const Prepacker& prepacker) { + VTR_ASSERT(candidate_mol_id.is_valid()); + VTR_ASSERT(!cluster_legalizer.is_mol_clustered(candidate_mol_id)); VTR_ASSERT(legalization_cluster_id.is_valid()); - e_block_pack_status pack_status = cluster_legalizer.add_mol_to_cluster(candidate_mol, - legalization_cluster_id); + e_block_pack_status pack_status = cluster_legalizer.add_mol_to_cluster(candidate_mol_id, + legalization_cluster_id); // Print helpful debugging log messages. if (log_verbosity_ > 2) { @@ -511,14 +506,15 @@ bool GreedyClusterer::try_add_candidate_mol_to_cluster(t_pack_molecule* candidat break; } // Get the block name and model name - AtomBlockId blk_id = candidate_mol->atom_block_ids[candidate_mol->root]; + const t_pack_molecule& candidate_mol = prepacker.get_molecule(candidate_mol_id); + AtomBlockId blk_id = candidate_mol.atom_block_ids[candidate_mol.root]; VTR_ASSERT(blk_id.is_valid()); std::string blk_name = atom_netlist_.block_name(blk_id); const t_model* blk_model = atom_netlist_.block_model(blk_id); VTR_LOG("'%s' (%s)", blk_name.c_str(), blk_model->name); - VTR_LOGV(candidate_mol->pack_pattern, " molecule %s molecule_size %zu", - candidate_mol->pack_pattern->name, - candidate_mol->atom_block_ids.size()); + VTR_LOGV(candidate_mol.pack_pattern, " molecule %s molecule_size %zu", + candidate_mol.pack_pattern->name, + candidate_mol.atom_block_ids.size()); VTR_LOG("\n"); fflush(stdout); } @@ -565,4 +561,3 @@ void GreedyClusterer::report_le_physical_block_usage(const ClusterLegalizer& clu print_le_count(num_logic_le, num_reg_le, num_logic_and_reg_le, le_pb_type); } } - diff --git a/vpr/src/pack/greedy_clusterer.h b/vpr/src/pack/greedy_clusterer.h index eb1dff3afdf..4c805ffa594 100644 --- a/vpr/src/pack/greedy_clusterer.h +++ b/vpr/src/pack/greedy_clusterer.h @@ -13,17 +13,17 @@ #include #include "cluster_legalizer.h" #include "physical_types.h" +#include "prepack.h" // Forward declarations +class APPackContext; class AtomNetId; class AtomNetlist; class AttractionInfo; class DeviceContext; class GreedyCandidateSelector; -class Prepacker; -class SetupTimingInfo; +class PreClusterTimingManager; class t_pack_high_fanout_thresholds; -class t_pack_molecule; struct t_analysis_opts; struct t_clustering_data; struct t_packer_opts; @@ -42,7 +42,7 @@ struct t_packer_opts; * internal molecules, and to the outputs of the clusters. */ class GreedyClusterer { -public: + public: /** * @brief Constructor of the Greedy Clusterer class. * @@ -76,6 +76,14 @@ class GreedyClusterer { * The set of global nets in the Atom Netlist. These will be * routed on special dedicated networks, and hence are less * relavent to locality / attraction. + * @param pre_cluster_timing_manager + * Timing manager class which holds the timing information of + * the primitive netlist. Used by the seed selector to select + * critical seeds and the candidate selector to select + * timing critical candidates. + * @param appack_ctx + * The APPack state. This contains the options used to + * configure APPack and the flat placement. */ GreedyClusterer(const t_packer_opts& packer_opts, const t_analysis_opts& analysis_opts, @@ -83,7 +91,9 @@ class GreedyClusterer { const t_arch& arch, const t_pack_high_fanout_thresholds& high_fanout_thresholds, const std::unordered_set& is_clock, - const std::unordered_set& is_global); + const std::unordered_set& is_global, + const PreClusterTimingManager& pre_cluster_timing_manager, + const APPackContext& appack_ctx); /** * @brief Performs clustering on the pack molecules formed by the prepacker. @@ -125,13 +135,13 @@ class GreedyClusterer { */ std::map do_clustering(ClusterLegalizer& cluster_legalizer, - Prepacker& prepacker, + const Prepacker& prepacker, bool allow_unrelated_clustering, bool balance_block_type_utilization, AttractionInfo& attraction_groups, DeviceContext& mutable_device_ctx); -private: + private: /** * @brief Given a seed molecule and a legalization strategy, tries to grow * a cluster greedily, starting with the provided seed and adding @@ -148,11 +158,11 @@ class GreedyClusterer { * legalizer for each molecule added. This cannot fail (assuming the seed * can exist in a cluster), so it will always return a valid cluster ID. */ - LegalizationClusterId try_grow_cluster(t_pack_molecule* seed_mol, + LegalizationClusterId try_grow_cluster(PackMoleculeId seed_mol_id, GreedyCandidateSelector& candidate_selector, ClusterLegalizationStrategy strategy, ClusterLegalizer& cluster_legalizer, - Prepacker& prepacker, + const Prepacker& prepacker, bool balance_block_type_utilization, AttractionInfo& attraction_groups, std::map& num_used_type_instances, @@ -172,8 +182,9 @@ class GreedyClusterer { * device grid if it find thats more clusters of specific logical block * types have been created than the device can support. */ - LegalizationClusterId start_new_cluster(t_pack_molecule* seed_mol, + LegalizationClusterId start_new_cluster(PackMoleculeId seed_mol_id, ClusterLegalizer& cluster_legalizer, + const Prepacker& prepacker, bool balance_block_type_utilization, std::map& num_used_type_instances, DeviceContext& mutable_device_ctx); @@ -183,9 +194,10 @@ class GreedyClusterer { * Returns true if the molecule was clustered successfully, false * otherwise. */ - bool try_add_candidate_mol_to_cluster(t_pack_molecule* candidate_mol, + bool try_add_candidate_mol_to_cluster(PackMoleculeId candidate_mol_id, LegalizationClusterId legalization_cluster_id, - ClusterLegalizer& cluster_legalizer); + ClusterLegalizer& cluster_legalizer, + const Prepacker& prepacker); /** * @brief Log the physical block usage of the logic element in the @@ -227,6 +239,13 @@ class GreedyClusterer { /// @brief A set of atom nets which are considered as global nets. const std::unordered_set& is_global_; + /// @brief Timing manager class which holds the primitive-level timing information. + const PreClusterTimingManager& pre_cluster_timing_manager_; + + /// @brief The APPack state. This is used by the candidate selector to try + /// and propose better candidates based on a flat placement. + const APPackContext& appack_ctx_; + /// @brief Pre-computed logical block types for each model in the architecture. const std::map> primitive_candidate_block_types_; @@ -246,4 +265,3 @@ class GreedyClusterer { /// is an input, so this should take care of all multiple connections. const std::unordered_set net_output_feeds_driving_block_input_; }; - diff --git a/vpr/src/pack/greedy_seed_selector.cpp b/vpr/src/pack/greedy_seed_selector.cpp index 24a57930f71..c9d1b9397c5 100644 --- a/vpr/src/pack/greedy_seed_selector.cpp +++ b/vpr/src/pack/greedy_seed_selector.cpp @@ -8,14 +8,21 @@ #include "greedy_seed_selector.h" #include +#include +#include "PreClusterTimingManager.h" +#include "flat_placement_types.h" #include "atom_netlist.h" #include "cluster_legalizer.h" +#include "device_grid.h" #include "echo_files.h" +#include "globals.h" +#include "greedy_clusterer.h" #include "prepack.h" #include "vpr_error.h" #include "vpr_types.h" #include "vtr_assert.h" #include "vtr_math.h" +#include "vtr_ndmatrix.h" #include "vtr_vector.h" /** @@ -40,22 +47,20 @@ static inline float get_seed_gain(AtomBlockId blk_id, // Intuition: molecules that use more inputs can be difficult to legally // pack into partially full clusters. Use them as seeds // instead. - case e_cluster_seed::MAX_INPUTS: - { - const t_pack_molecule* blk_mol = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol, atom_netlist); + case e_cluster_seed::MAX_INPUTS: { + PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); return molecule_stats.num_used_ext_inputs; } // By blended gain (criticality and inputs used). - case e_cluster_seed::BLEND: - { + case e_cluster_seed::BLEND: { // Score seed gain of each block as a weighted sum of timing // criticality, number of tightly coupled blocks connected to // it, and number of external inputs. float seed_blend_fac = 0.5f; - const t_pack_molecule* blk_mol = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol, atom_netlist); + PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); VTR_ASSERT(max_molecule_stats.num_used_ext_inputs > 0); float used_ext_input_pin_ratio = vtr::safe_ratio(molecule_stats.num_used_ext_inputs, max_molecule_stats.num_used_ext_inputs); @@ -67,25 +72,22 @@ static inline float get_seed_gain(AtomBlockId blk_id, // By pins per molecule (i.e. available pins on primitives, not pins in use). // Intuition (a weak one): primitive types with more pins might be // harder to pack. - case e_cluster_seed::MAX_PINS: - { - const t_pack_molecule* blk_mol = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol, atom_netlist); + case e_cluster_seed::MAX_PINS: { + PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); return molecule_stats.num_pins; } // By input pins per molecule (i.e. available pins on primitives, not pins in use). // Intuition (a weak one): primitive types with more input pins might be // harder to pack. - case e_cluster_seed::MAX_INPUT_PINS: - { - const t_pack_molecule* blk_mol = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol, atom_netlist); + case e_cluster_seed::MAX_INPUT_PINS: { + PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); return molecule_stats.num_input_pins; } - case e_cluster_seed::BLEND2: - { - const t_pack_molecule* mol = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(mol, atom_netlist); + case e_cluster_seed::BLEND2: { + PackMoleculeId mol_id = prepacker.get_atom_molecule(blk_id); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(mol_id, atom_netlist); float pin_ratio = vtr::safe_ratio(molecule_stats.num_pins, max_molecule_stats.num_pins); float input_pin_ratio = vtr::safe_ratio(molecule_stats.num_input_pins, max_molecule_stats.num_input_pins); @@ -166,10 +168,21 @@ GreedySeedSelector::GreedySeedSelector(const AtomNetlist& atom_netlist, const Prepacker& prepacker, const e_cluster_seed seed_type, const t_molecule_stats& max_molecule_stats, - const vtr::vector& atom_criticality) - : seed_atoms_(atom_netlist.blocks().begin(), atom_netlist.blocks().end()) { + const PreClusterTimingManager& pre_cluster_timing_manager) + : seed_atoms_(atom_netlist.blocks().begin(), atom_netlist.blocks().end()) { // Seed atoms list is initialized with all atoms in the atom netlist. + // Pre-compute the criticality of each atom + // Default criticalities set to zero (e.g. if not timing driven) + vtr::vector atom_criticality(atom_netlist.blocks().size(), 0.0f); + if (pre_cluster_timing_manager.is_valid()) { + // If the timing manager is valid (meaning the packing is timing driven) + // compute the criticality of each atom. + for (AtomBlockId atom_blk_id : atom_netlist.blocks()) { + atom_criticality[atom_blk_id] = pre_cluster_timing_manager.calc_atom_setup_criticality(atom_blk_id, atom_netlist); + } + } + // Maintain a lookup table of the seed gain for each atom. This will be // used to sort the seed atoms. // Initially all gains are zero. @@ -210,8 +223,8 @@ GreedySeedSelector::GreedySeedSelector(const AtomNetlist& atom_netlist, seed_index_ = 0; } -t_pack_molecule* GreedySeedSelector::get_next_seed(const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer) { +PackMoleculeId GreedySeedSelector::get_next_seed(const Prepacker& prepacker, + const ClusterLegalizer& cluster_legalizer) { while (seed_index_ < seed_atoms_.size()) { // Get the current seed atom at the seed index and increment the // seed index. @@ -227,14 +240,13 @@ t_pack_molecule* GreedySeedSelector::get_next_seed(const Prepacker& prepacker, // Get the molecule that contains this atom and return it as the // next seed. - t_pack_molecule* seed_molecule = prepacker.get_atom_molecule(seed_blk_id); - VTR_ASSERT(!cluster_legalizer.is_mol_clustered(seed_molecule)); - return seed_molecule; + PackMoleculeId seed_molecule_id = prepacker.get_atom_molecule(seed_blk_id); + VTR_ASSERT(!cluster_legalizer.is_mol_clustered(seed_molecule_id)); + return seed_molecule_id; } // If the previous loop does not return a molecule, it implies that all // atoms have been clustered or have already been proposed as a seed. // Return nullptr to signify that there are no further seeds. - return nullptr; + return PackMoleculeId::INVALID(); } - diff --git a/vpr/src/pack/greedy_seed_selector.h b/vpr/src/pack/greedy_seed_selector.h index f6eee80da4b..5f152f65236 100644 --- a/vpr/src/pack/greedy_seed_selector.h +++ b/vpr/src/pack/greedy_seed_selector.h @@ -8,12 +8,13 @@ #pragma once +#include "prepack.h" #include "vpr_types.h" // Forward declarations class AtomNetlist; class ClusterLegalizer; -class Prepacker; +class PreClusterTimingManager; struct t_molecule_stats; /** @@ -27,7 +28,7 @@ struct t_molecule_stats; * or has already been clustered. */ class GreedySeedSelector { -public: + public: /** * @brief Constructor of the Greedy Seed Selector class. Pre-computes the * gains of each molecule internally to make getting seeds later very @@ -44,18 +45,19 @@ class GreedySeedSelector { * @param max_molecule_stats * The maximum stats over all molecules. Used for normalizing * terms in the gain. - * @param atom_criticality - * The timing criticality of each atom. + * @param pre_cluster_timing_manager + * Timing manager class for the primitive netlist. Used to + * compute the criticalities of seeds. */ GreedySeedSelector(const AtomNetlist& atom_netlist, const Prepacker& prepacker, const e_cluster_seed seed_type, const t_molecule_stats& max_molecule_stats, - const vtr::vector& atom_criticality); + const PreClusterTimingManager& pre_cluster_timing_manager); /** * @brief Propose a new seed molecule to start a new cluster with. If no - * unclustered molecules exist, will return nullptr. + * unclustered molecules exist, will return an invalid ID. * * This method will never return a molecule which has already been clustered * (according to the cluster legalizer) and will never propose a molecule @@ -71,14 +73,13 @@ class GreedySeedSelector { * clusters. This is used to check if a molecule has already * been clustered or not. */ - t_pack_molecule* get_next_seed(const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer); + PackMoleculeId get_next_seed(const Prepacker& prepacker, + const ClusterLegalizer& cluster_legalizer); // TODO: Maybe create an update_seed_gains method to update the seed atoms // list using current clustering information. -private: - + private: /// @brief The index of the next seed to propose in the seed_atoms vector. /// This is set to 0 in the constructor and incremented as more seeds /// are proposed. @@ -94,4 +95,3 @@ class GreedySeedSelector { // used. std::vector seed_atoms_; }; - diff --git a/vpr/src/pack/noc_aware_cluster_util.cpp b/vpr/src/pack/noc_aware_cluster_util.cpp index d807e5aa187..aba034992f2 100644 --- a/vpr/src/pack/noc_aware_cluster_util.cpp +++ b/vpr/src/pack/noc_aware_cluster_util.cpp @@ -70,7 +70,7 @@ void update_noc_reachability_partitions(const std::vector& noc_atom atom_noc_grp_id[current_atom] = noc_grp_id; - for(auto pin : atom_netlist.block_pins(current_atom)) { + for (auto pin : atom_netlist.block_pins(current_atom)) { AtomNetId net_id = atom_netlist.pin_net(pin); size_t net_fanout = atom_netlist.net_sinks(net_id).size(); @@ -91,9 +91,7 @@ void update_noc_reachability_partitions(const std::vector& noc_atom atom_visited[sink_atom_id] = true; } } - } } - } } diff --git a/vpr/src/pack/noc_aware_cluster_util.h b/vpr/src/pack/noc_aware_cluster_util.h index 6f930a21944..a414d147bcf 100644 --- a/vpr/src/pack/noc_aware_cluster_util.h +++ b/vpr/src/pack/noc_aware_cluster_util.h @@ -32,7 +32,6 @@ class t_pack_high_fanout_thresholds; */ std::vector find_noc_router_atoms(const AtomNetlist& atom_netlist); - /** * @brief Runs BFS starting from NoC routers to find all connected * components that include a NoC router. Each connected component diff --git a/vpr/src/pack/output_clustering.cpp b/vpr/src/pack/output_clustering.cpp index 83949655b2b..60a371aee46 100644 --- a/vpr/src/pack/output_clustering.cpp +++ b/vpr/src/pack/output_clustering.cpp @@ -12,6 +12,7 @@ #include "cluster_legalizer.h" #include "clustered_netlist.h" #include "physical_types.h" +#include "physical_types_util.h" #include "prepack.h" #include "vpr_context.h" #include "vtr_assert.h" @@ -29,7 +30,6 @@ #include "vpr_utils.h" #include "pack.h" - static void print_clustering_stats_header(); static void print_clustering_stats(std::string_view block_name, int num_block_type, float num_inputs_clocks, float num_outputs); @@ -84,7 +84,6 @@ static void count_stats_from_legalizer(const ClusterLegalizer& cluster_legalizer } num_clb_types[logical_block->index]++; } - } static void count_stats_from_netlist(std::unordered_map& nets_absorbed, @@ -112,7 +111,7 @@ static void count_stats_from_netlist(std::unordered_map& nets_a } else { ClusterNetId clb_net_id = clb_nlist.block_net(blk_id, ipin); if (clb_net_id != ClusterNetId::INVALID()) { - AtomNetId net_id = atom_ctx.lookup.atom_net(clb_net_id); + AtomNetId net_id = atom_ctx.lookup().atom_net(clb_net_id); VTR_ASSERT(net_id); nets_absorbed[net_id] = false; @@ -132,7 +131,7 @@ static void count_stats_from_netlist(std::unordered_map& nets_a * internal connections are printed out. */ static void print_stats(const ClusterLegalizer* cluster_legalizer_ptr, bool from_legalizer) { const DeviceContext& device_ctx = g_vpr_ctx.device(); - const AtomNetlist& atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); int* num_clb_types = new int[device_ctx.logical_block_types.size()]; int* num_clb_inputs_used = new int[device_ctx.logical_block_types.size()]; @@ -208,10 +207,10 @@ static void print_clustering_stats(std::string_view block_name, int num_block_ty } static const char* clustering_xml_net_text(AtomNetId net_id) { - /* This routine prints out the atom_ctx.nlist net name (or open). - * net_num is the index of the atom_ctx.nlist net to be printed + /* This routine prints out the atom_ctx.netlist() net name (or open). + * net_num is the index of the atom_ctx.netlist() net to be printed */ - const AtomNetlist& atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); if (!net_id) { return "open"; @@ -431,18 +430,18 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty block_node.append_attribute("mode") = mode->name; } else { const auto& atom_ctx = g_vpr_ctx.atom(); - AtomBlockId atom_blk = atom_ctx.nlist.find_block(pb->name); + AtomBlockId atom_blk = atom_ctx.netlist().find_block(pb->name); VTR_ASSERT(atom_blk); pugi::xml_node attrs_node = block_node.append_child("attributes"); - for (const auto& attr : atom_ctx.nlist.block_attrs(atom_blk)) { + for (const auto& attr : atom_ctx.netlist().block_attrs(atom_blk)) { pugi::xml_node attr_node = attrs_node.append_child("attribute"); attr_node.append_attribute("name") = attr.first.c_str(); attr_node.text().set(attr.second.c_str()); } pugi::xml_node params_node = block_node.append_child("parameters"); - for (const auto& param : atom_ctx.nlist.block_params(atom_blk)) { + for (const auto& param : atom_ctx.netlist().block_params(atom_blk)) { pugi::xml_node param_node = params_node.append_child("parameter"); param_node.append_attribute("name") = param.first.c_str(); param_node.text().set(param.second.c_str()); @@ -480,10 +479,10 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty //This is a primitive with equivalent inputs auto& atom_ctx = g_vpr_ctx.atom(); - AtomBlockId atom_blk = atom_ctx.nlist.find_block(pb->name); + AtomBlockId atom_blk = atom_ctx.netlist().find_block(pb->name); VTR_ASSERT(atom_blk); - AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, pb_type->ports[i].model_port); + AtomPortId atom_port = atom_ctx.netlist().find_atom_port(atom_blk, pb_type->ports[i].model_port); if (atom_port) { //Port exists (some LUTs may have no input and hence no port in the atom netlist) @@ -503,10 +502,10 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty //This physical pin is in use, find the original pin in the atom netlist AtomPinId orig_pin; - for (AtomPinId atom_pin : atom_ctx.nlist.port_pins(atom_port)) { + for (AtomPinId atom_pin : atom_ctx.netlist().port_pins(atom_port)) { if (recorded_pins.count(atom_pin)) continue; //Don't add pins twice - AtomNetId atom_pin_net = atom_ctx.nlist.pin_net(atom_pin); + AtomNetId atom_pin_net = atom_ctx.netlist().pin_net(atom_pin); if (atom_pin_net == atom_net) { recorded_pins.insert(atom_pin); @@ -517,7 +516,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty VTR_ASSERT(orig_pin); //The physical pin j, maps to a pin in the atom netlist - pin_map_list.push_back(vtr::string_fmt("%d", atom_ctx.nlist.pin_port_bit(orig_pin))); + pin_map_list.push_back(vtr::string_fmt("%d", atom_ctx.netlist().pin_port_bit(orig_pin))); } else { //The physical pin is disconnected pin_map_list.push_back("open"); @@ -643,7 +642,7 @@ static void clustering_xml_blocks_from_netlist(pugi::xml_node& block_node, * the cluster, in essentially a graph based format. */ void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, bool global_clocks, const std::unordered_set& is_clock, const std::string& architecture_id, const char* out_fname, bool skip_clustering, bool from_legalizer) { const DeviceContext& device_ctx = g_vpr_ctx.device(); - const AtomNetlist& atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); IntraLbPbPinLookup pb_graph_pin_lookup_from_index_by_type(device_ctx.logical_block_types); @@ -722,7 +721,7 @@ void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, bool global_cloc * but remove all the requirements on input data structures that * have to be built with other APIs * - * As such, this function is expected to be a standard API + * As such, this function is expected to be a standard API * which can be called anytime and anywhere after packing is finished. ********************************************************************/ void write_packing_results_to_xml(const bool& global_clocks, diff --git a/vpr/src/pack/pack.cpp b/vpr/src/pack/pack.cpp index e9ba3f7f7e3..ec96e7c4d7c 100644 --- a/vpr/src/pack/pack.cpp +++ b/vpr/src/pack/pack.cpp @@ -1,14 +1,21 @@ -#include +#include "pack.h" + +#include +#include "PreClusterTimingManager.h" #include "SetupGrid.h" +#include "appack_context.h" #include "attraction_groups.h" #include "cluster_legalizer.h" #include "cluster_util.h" #include "constraints_report.h" +#include "flat_placement_types.h" #include "globals.h" #include "greedy_clusterer.h" -#include "pack.h" +#include "partition_region.h" #include "prepack.h" +#include "stats.h" +#include "verify_flat_placement.h" #include "vpr_context.h" #include "vpr_error.h" #include "vpr_types.h" @@ -20,13 +27,13 @@ static bool try_size_device_grid(const t_arch& arch, float target_device_utilization, const std::string& device_layout_name); -bool try_pack(t_packer_opts* packer_opts, - const t_analysis_opts* analysis_opts, - const t_arch* arch, - const t_model* user_models, - const t_model* library_models, - float interc_delay, - std::vector* lb_type_rr_graphs) { +bool try_pack(const t_packer_opts& packer_opts, + const t_analysis_opts& analysis_opts, + const t_arch& arch, + std::vector* lb_type_rr_graphs, + const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, + const FlatPlacementInfo& flat_placement_info) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); const DeviceContext& device_ctx = g_vpr_ctx.device(); // The clusterer modifies the device context by increasing the size of the @@ -34,15 +41,15 @@ bool try_pack(t_packer_opts* packer_opts, DeviceContext& mutable_device_ctx = g_vpr_ctx.mutable_device(); std::unordered_set is_clock, is_global; - VTR_LOG("Begin packing '%s'.\n", packer_opts->circuit_file_name.c_str()); + VTR_LOG("Begin packing '%s'.\n", packer_opts.circuit_file_name.c_str()); is_clock = alloc_and_load_is_clock(); is_global.insert(is_clock.begin(), is_clock.end()); size_t num_p_inputs = 0; size_t num_p_outputs = 0; - for (auto blk_id : atom_ctx.nlist.blocks()) { - auto type = atom_ctx.nlist.block_type(blk_id); + for (auto blk_id : atom_ctx.netlist().blocks()) { + auto type = atom_ctx.netlist().block_type(blk_id); if (type == AtomBlockType::INPAD) { ++num_p_inputs; } else if (type == AtomBlockType::OUTPAD) { @@ -53,74 +60,85 @@ bool try_pack(t_packer_opts* packer_opts, VTR_LOG("\n"); VTR_LOG("After removing unused inputs...\n"); VTR_LOG("\ttotal blocks: %zu, total nets: %zu, total inputs: %zu, total outputs: %zu\n", - atom_ctx.nlist.blocks().size(), atom_ctx.nlist.nets().size(), num_p_inputs, num_p_outputs); - - // Run the prepacker, packing the atoms into molecules. - // The Prepacker object performs prepacking and stores the pack molecules. - // As long as the molecules are used, this object must persist. - VTR_LOG("Begin prepacking.\n"); - Prepacker prepacker; - prepacker.init(atom_ctx.nlist, device_ctx.logical_block_types); + atom_ctx.netlist().blocks().size(), atom_ctx.netlist().nets().size(), num_p_inputs, num_p_outputs); /* We keep attraction groups off in the first iteration, and * only turn on in later iterations if some floorplan regions turn out to be overfull. */ AttractionInfo attraction_groups(false); - VTR_LOG("%d attraction groups were created during prepacking.\n", attraction_groups.num_attraction_groups()); - VTR_LOG("Finish prepacking.\n"); - if (packer_opts->auto_compute_inter_cluster_net_delay) { - packer_opts->inter_cluster_net_delay = interc_delay; - VTR_LOG("Using inter-cluster delay: %g\n", packer_opts->inter_cluster_net_delay); + // We keep track of the overfilled partition regions from all pack iterations in + // this vector. This is so that if the first iteration fails due to overfilled + // partition regions, and it fails again, we can carry over the previous failed + // partition regions to the current iteration. + std::vector overfull_partition_regions; + + // Verify that the Flat Placement is valid for packing. + if (flat_placement_info.valid) { + unsigned num_errors = verify_flat_placement_for_packing(flat_placement_info, + atom_ctx.netlist(), + prepacker); + if (num_errors == 0) { + VTR_LOG("Completed flat placement consistency check successfully.\n"); + } else { + // TODO: In the future, we can just erase the flat placement and + // continue. It depends on what we want to happen if the + // flat placement is not valid. + VPR_ERROR(VPR_ERROR_PACK, + "%u errors found while performing flat placement " + "consistency check. Aborting program.\n", + num_errors); + } } // During clustering, a block is related to un-clustered primitives with nets. // This relation has three types: low fanout, high fanout, and transitive // high_fanout_thresholds stores the threshold for nets to a block type to // be considered high fanout. - t_pack_high_fanout_thresholds high_fanout_thresholds(packer_opts->high_fanout_threshold); + t_pack_high_fanout_thresholds high_fanout_thresholds(packer_opts.high_fanout_threshold); bool allow_unrelated_clustering = false; - if (packer_opts->allow_unrelated_clustering == e_unrelated_clustering::ON) { + if (packer_opts.allow_unrelated_clustering == e_unrelated_clustering::ON) { allow_unrelated_clustering = true; - } else if (packer_opts->allow_unrelated_clustering == e_unrelated_clustering::OFF) { + } else if (packer_opts.allow_unrelated_clustering == e_unrelated_clustering::OFF) { allow_unrelated_clustering = false; } bool balance_block_type_util = false; - if (packer_opts->balance_block_type_utilization == e_balance_block_type_util::ON) { + if (packer_opts.balance_block_type_utilization == e_balance_block_type_util::ON) { balance_block_type_util = true; - } else if (packer_opts->balance_block_type_utilization == e_balance_block_type_util::OFF) { + } else if (packer_opts.balance_block_type_utilization == e_balance_block_type_util::OFF) { balance_block_type_util = false; } int pack_iteration = 1; - // Initialize the cluster legalizer. - ClusterLegalizer cluster_legalizer(atom_ctx.nlist, + ClusterLegalizer cluster_legalizer(atom_ctx.netlist(), prepacker, - device_ctx.logical_block_types, lb_type_rr_graphs, - user_models, - library_models, - packer_opts->target_external_pin_util, + packer_opts.target_external_pin_util, high_fanout_thresholds, ClusterLegalizationStrategy::SKIP_INTRA_LB_ROUTE, - packer_opts->enable_pin_feasibility_filter, - packer_opts->feasible_block_array_size, - packer_opts->pack_verbosity); - + packer_opts.enable_pin_feasibility_filter, + packer_opts.pack_verbosity); VTR_LOG("Packing with pin utilization targets: %s\n", cluster_legalizer.get_target_external_pin_util().to_string().c_str()); VTR_LOG("Packing with high fanout thresholds: %s\n", high_fanout_thresholds.to_string().c_str()); + // Construct the APPack Context. + APPackContext appack_ctx(flat_placement_info, device_ctx.grid); + // Initialize the greedy clusterer. - GreedyClusterer clusterer(*packer_opts, - *analysis_opts, - atom_ctx.nlist, - *arch, + GreedyClusterer clusterer(packer_opts, + analysis_opts, + atom_ctx.netlist(), + arch, high_fanout_thresholds, is_clock, - is_global); + is_global, + pre_cluster_timing_manager, + appack_ctx); + + g_vpr_ctx.mutable_atom().mutable_lookup().set_atom_pb_bimap_lock(true); while (true) { //Cluster the netlist @@ -135,13 +153,16 @@ bool try_pack(t_packer_opts* packer_opts, mutable_device_ctx); //Try to size/find a device - bool fits_on_device = try_size_device_grid(*arch, num_used_type_instances, packer_opts->target_device_utilization, packer_opts->device_layout); + bool fits_on_device = try_size_device_grid(arch, num_used_type_instances, packer_opts.target_device_utilization, packer_opts.device_layout); /* We use this bool to determine the cause for the clustering not being dense enough. If the clustering * is not dense enough and there are floorplan constraints, it is presumed that the constraints are the cause * of the floorplan not fitting, so attraction groups are turned on for later iterations. */ - bool floorplan_regions_overfull = floorplan_constraints_regions_overfull(cluster_legalizer); + bool floorplan_regions_overfull = floorplan_constraints_regions_overfull(overfull_partition_regions, + cluster_legalizer, + device_ctx.logical_block_types); + bool floorplan_not_fitting = (floorplan_regions_overfull || g_vpr_ctx.floorplanning().constraints.get_num_partitions() > 0); if (fits_on_device && !floorplan_regions_overfull) { @@ -150,11 +171,11 @@ bool try_pack(t_packer_opts* packer_opts, //1st pack attempt was unsuccessful (i.e. not dense enough) and we have control of unrelated clustering // //Turn it on to increase packing density - if (packer_opts->allow_unrelated_clustering == e_unrelated_clustering::AUTO) { + if (packer_opts.allow_unrelated_clustering == e_unrelated_clustering::AUTO) { VTR_ASSERT(allow_unrelated_clustering == false); allow_unrelated_clustering = true; } - if (packer_opts->balance_block_type_utilization == e_balance_block_type_util::AUTO) { + if (packer_opts.balance_block_type_utilization == e_balance_block_type_util::AUTO) { VTR_ASSERT(balance_block_type_util == false); balance_block_type_util = true; } @@ -173,13 +194,13 @@ bool try_pack(t_packer_opts* packer_opts, */ } else if (pack_iteration == 1 && floorplan_not_fitting) { VTR_LOG("Floorplan regions are overfull: trying to pack again using cluster attraction groups. \n"); - attraction_groups.create_att_groups_for_overfull_regions(); + attraction_groups.create_att_groups_for_overfull_regions(overfull_partition_regions); attraction_groups.set_att_group_pulls(1); } else if (pack_iteration >= 2 && pack_iteration < 5 && floorplan_not_fitting) { if (pack_iteration == 2) { VTR_LOG("Floorplan regions are overfull: trying to pack again with more attraction groups exploration. \n"); - attraction_groups.create_att_groups_for_overfull_regions(); + attraction_groups.create_att_groups_for_overfull_regions(overfull_partition_regions); VTR_LOG("Pack iteration is %d\n", pack_iteration); } else if (pack_iteration == 3) { attraction_groups.create_att_groups_for_all_regions(); @@ -229,20 +250,11 @@ bool try_pack(t_packer_opts* packer_opts, VPR_FATAL_ERROR(VPR_ERROR_OTHER, "Failed to find device which satisfies resource requirements required: %s (available %s)", resource_reqs.c_str(), resource_avail.c_str()); } - //Reset clustering for re-packing - for (auto blk : g_vpr_ctx.atom().nlist.blocks()) { - g_vpr_ctx.mutable_atom().lookup.set_atom_clb(blk, ClusterBlockId::INVALID()); - g_vpr_ctx.mutable_atom().lookup.set_atom_pb(blk, nullptr); - } - for (auto net : g_vpr_ctx.atom().nlist.nets()) { - g_vpr_ctx.mutable_atom().lookup.remove_atom_net(net); - } + //Reset floorplanning constraints for re-packing g_vpr_ctx.mutable_floorplanning().cluster_constraints.clear(); - //attraction_groups.reset_attraction_groups(); // Reset the cluster legalizer for re-clustering. cluster_legalizer.reset(); - ++pack_iteration; } @@ -260,9 +272,10 @@ bool try_pack(t_packer_opts* packer_opts, * } */ /******************** End **************************/ - + g_vpr_ctx.mutable_atom().mutable_lookup().set_atom_pb_bimap_lock(false); + g_vpr_ctx.mutable_atom().mutable_lookup().set_atom_to_pb_bimap(cluster_legalizer.atom_pb_lookup()); //check clustering and output it - check_and_output_clustering(cluster_legalizer, *packer_opts, is_clock, arch); + check_and_output_clustering(cluster_legalizer, packer_opts, is_clock, &arch); VTR_LOG("\n"); VTR_LOG("Netlist conversion complete.\n"); @@ -271,24 +284,6 @@ bool try_pack(t_packer_opts* packer_opts, return true; } -float get_arch_switch_info(short switch_index, int switch_fanin, float& Tdel_switch, float& R_switch, float& Cout_switch) { - /* Fetches delay, resistance and output capacitance of the architecture switch at switch_index. - * Returns the total delay through the switch. Used to calculate inter-cluster net delay. */ - - /* The intrinsic delay may depend on fanin to the switch. If the delay map of a - * switch from the architecture file has multiple (#inputs, delay) entries, we - * interpolate/extrapolate to get the delay at 'switch_fanin'. */ - auto& device_ctx = g_vpr_ctx.device(); - - Tdel_switch = device_ctx.arch_switch_inf[switch_index].Tdel(switch_fanin); - R_switch = device_ctx.arch_switch_inf[switch_index].R; - Cout_switch = device_ctx.arch_switch_inf[switch_index].Cout; - - /* The delay through a loaded switch is its intrinsic (unloaded) - * delay plus the product of its resistance and output capacitance. */ - return Tdel_switch + R_switch * Cout_switch; -} - std::unordered_set alloc_and_load_is_clock() { /* Looks through all the atom blocks to find and mark all the clocks, by setting * the corresponding entry by adding the clock to is_clock. @@ -299,9 +294,9 @@ std::unordered_set alloc_and_load_is_clock() { /* Want to identify all the clock nets. */ auto& atom_ctx = g_vpr_ctx.atom(); - for (auto blk_id : atom_ctx.nlist.blocks()) { - for (auto pin_id : atom_ctx.nlist.block_clock_pins(blk_id)) { - auto net_id = atom_ctx.nlist.pin_net(pin_id); + for (auto blk_id : atom_ctx.netlist().blocks()) { + for (auto pin_id : atom_ctx.netlist().block_clock_pins(blk_id)) { + auto net_id = atom_ctx.netlist().pin_net(pin_id); if (!is_clock.count(net_id)) { is_clock.insert(net_id); } @@ -358,4 +353,3 @@ static bool try_size_device_grid(const t_arch& arch, return fits_on_device; } - diff --git a/vpr/src/pack/pack.h b/vpr/src/pack/pack.h index 842feb0aacd..64189ea4ee9 100644 --- a/vpr/src/pack/pack.h +++ b/vpr/src/pack/pack.h @@ -5,21 +5,43 @@ #include class AtomNetId; +class FlatPlacementInfo; +class PreClusterTimingManager; +class Prepacker; struct t_analysis_opts; struct t_arch; struct t_lb_type_rr_node; -struct t_model; struct t_packer_opts; -bool try_pack(t_packer_opts* packer_opts, - const t_analysis_opts* analysis_opts, - const t_arch* arch, - const t_model* user_models, - const t_model* library_models, - float interc_delay, - std::vector* lb_type_rr_graphs); - -float get_arch_switch_info(short switch_index, int switch_fanin, float& Tdel_switch, float& R_switch, float& Cout_switch); +/** + * @brief Try to pack the atom netlist into legal clusters on the given + * architecture. Will return true if successful, false otherwise. + * + * @param packer_opts + * Options passed by the user to configure the packing algorithm. + * @param analysis_opts + * Options passed by the user to configure how analysis is + * performed in the packer. + * @param arch + * The architecture to create clusters for. + * @param lb_type_rr_graphs + * @param prepacker + * The prepacker used to form atoms into molecules prior to packing. + * @param pre_cluster_timing_manager + * Manager object to store the pre-computed timing delay calculations. + * Used to inform the packer of timing critical paths. + * @param flat_placement_info + * Flat (primitive-level) placement information that may be + * provided by the user as a hint for packing. Will be invalid if + * there is no flat placement information provided. + */ +bool try_pack(const t_packer_opts& packer_opts, + const t_analysis_opts& analysis_opts, + const t_arch& arch, + std::vector* lb_type_rr_graphs, + const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, + const FlatPlacementInfo& flat_placement_info); std::unordered_set alloc_and_load_is_clock(); diff --git a/vpr/src/pack/pack_types.h b/vpr/src/pack/pack_types.h index 44fa9107966..8ebaf22b26b 100644 --- a/vpr/src/pack/pack_types.h +++ b/vpr/src/pack/pack_types.h @@ -69,7 +69,7 @@ struct t_lb_type_rr_node { t_pb_graph_pin* pb_graph_pin; /* pb_graph_pin associated with this lb_rr_node if exists, NULL otherwise */ float intrinsic_cost; /* cost of this node */ - t_lb_type_rr_node() { + t_lb_type_rr_node() noexcept { capacity = 0; num_modes = 0; num_fanout = nullptr; @@ -130,7 +130,7 @@ struct t_intra_lb_net { std::vector fixed_terminals; /* Marks a terminal as having a fixed target (i.e. a pin not a sink) */ t_lb_trace* rt_tree; /* Route tree head */ - t_intra_lb_net() { + t_intra_lb_net() noexcept { atom_net_id = AtomNetId::INVALID(); rt_tree = nullptr; } diff --git a/vpr/src/pack/pb_type_graph.cpp b/vpr/src/pack/pb_type_graph.cpp index 0c6745b85e2..02784e4321a 100644 --- a/vpr/src/pack/pb_type_graph.cpp +++ b/vpr/src/pack/pb_type_graph.cpp @@ -394,7 +394,6 @@ static void alloc_and_load_pb_graph(t_pb_graph_node* pb_graph_node, load_power_structures); } - // update the total number of primitives of that type if (pb_graph_node->is_primitive()) { int total_count = 1; @@ -1498,7 +1497,7 @@ static bool realloc_and_load_pb_graph_pin_ptrs_at_var(const int line_num, if (prev_num_pins > 0) { std::vector temp(*pb_graph_pins, *pb_graph_pins + prev_num_pins); - delete[] * pb_graph_pins; + delete[] *pb_graph_pins; *pb_graph_pins = new t_pb_graph_pin*[*num_pins]; for (i = 0; i < prev_num_pins; i++) (*pb_graph_pins)[i] = temp[i]; @@ -1946,18 +1945,18 @@ const t_pb_graph_edge* get_edge_between_pins(const t_pb_graph_pin* driver_pin, c /* Date:June 8th, 2024 * Author: Kate Thurmer * Purpose: This subroutine computes the index of a pb graph node at its - level of the pb hierarchy; it is computed by the parent and - passed to each child of each child pb type. When the child is - a primitive, the computed indes is its flat site index. - For example, if there are 10 ALMs, each with 2 FFs and 2 LUTs, - then the ALM at index N, when calling this function for - its FF child at index M, would compute the child's index as: - N*(FFs per ALM) + M - e.g. for FF[1] in ALM[5], this returns - 5*(2 FFS per ALM) + 1 = 11 + * level of the pb hierarchy; it is computed by the parent and + * passed to each child of each child pb type. When the child is + * a primitive, the computed indes is its flat site index. + * For example, if there are 10 ALMs, each with 2 FFs and 2 LUTs, + * then the ALM at index N, when calling this function for + * its FF child at index M, would compute the child's index as: + * N*(FFs per ALM) + M + * e.g. for FF[1] in ALM[5], this returns + * 5*(2 FFS per ALM) + 1 = 11 */ static int compute_flat_index_for_child_node(int num_children_of_type, int parent_flat_index, int child_index) { - return parent_flat_index*num_children_of_type + child_index; + return parent_flat_index * num_children_of_type + child_index; } diff --git a/vpr/src/pack/post_routing_pb_pin_fixup.cpp b/vpr/src/pack/post_routing_pb_pin_fixup.cpp index 78084d56df3..d217f07a83d 100644 --- a/vpr/src/pack/post_routing_pb_pin_fixup.cpp +++ b/vpr/src/pack/post_routing_pb_pin_fixup.cpp @@ -1,15 +1,14 @@ /******************************************************************** - * This file includes functions to fix up the pb pin mapping results + * This file includes functions to fix up the pb pin mapping results * after routing optimization *******************************************************************/ /* Headers from vtrutil library */ +#include "physical_types_util.h" #include "vtr_time.h" #include "vtr_assert.h" #include "vtr_log.h" -#include "vpr_error.h" #include "vpr_utils.h" -#include "rr_graph2.h" #include "annotate_routing.h" @@ -19,7 +18,7 @@ #include "globals.h" /******************************************************************** - * Give a given pin index, find the side where this pin is located + * Give a given pin index, find the side where this pin is located * on the physical tile * Note: * - Need to check if the pin_width_offset and pin_height_offset @@ -41,7 +40,7 @@ static std::vector find_physical_tile_pin_side(t_physical_tile_type_ptr /******************************************************************** * Fix up the pb pin mapping results for a given clustered block - * 1. For each input/output pin of a clustered pb, + * 1. For each input/output pin of a clustered pb, * - find a corresponding node in RRGraph object * - find the net id for the node in routing context * - find the net id for the node in clustering context @@ -66,15 +65,15 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li /* Narrow down side search for grids * The wanted side depends on the location of the grid. - * In particular for perimeter grid, + * In particular for perimeter grid, * ------------------------------------------------------- * Grid location | IPIN side * ------------------------------------------------------- - * TOP | BOTTOM + * TOP | BOTTOM * ------------------------------------------------------- - * RIGHT | LEFT + * RIGHT | LEFT * ------------------------------------------------------- - * BOTTOM | TOP + * BOTTOM | TOP * ------------------------------------------------------- * LEFT | RIGHT * ------------------------------------------------------- @@ -173,7 +172,7 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li * In general, there is only one valid rr_node among all the sides. * However, we have an exception in the Stratix-IV arch modeling, * where a pb_pin may exist in two different sides but - * router will only map to 1 rr_node + * router will only map to 1 rr_node * Therefore, it is better to compare the routing nets * for all the sides and pick * - The unique valid net id (others should be all invalid) @@ -247,7 +246,7 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li } /******************************************************************** - * Find an unused pb_route from the other pins in this port + * Find an unused pb_route from the other pins in this port * The pb_route should be remapped to an invalid net, becoming unused * at post routing stage. * @@ -272,7 +271,7 @@ static int find_target_pb_route_from_equivalent_pins(const AtomContext& atom_ctx } /* Limitation: bypass output pins now - * TODO: This is due to the 'instance' equivalence port + * TODO: This is due to the 'instance' equivalence port * where outputs may be swapped. This definitely requires re-run of packing * It can not be solved by swapping routing traces now */ @@ -317,7 +316,7 @@ static int find_target_pb_route_from_equivalent_pins(const AtomContext& atom_ctx VTR_LOGV(verbose, "Found %lu candidates to remap net '%s' at clustered block '%s' pin '%s'\n", pb_route_indices.size(), - atom_ctx.nlist.net_name(target_net).c_str(), + atom_ctx.netlist().net_name(target_net).c_str(), clustering_ctx.clb_nlist.block_pb(blk_id)->name, source_pb_graph_pin->to_string().c_str()); @@ -367,7 +366,7 @@ static const t_pb_graph_pin* find_unused_pb_graph_pin_in_the_same_port(const t_p VTR_LOG("\tUnused\n"); } else { VTR_LOG("\tmapped to net '%s'\n", - g_vpr_ctx.atom().nlist.net_name(pb_routes.at(cand_pb_route_id).atom_net_id).c_str()); + g_vpr_ctx.atom().netlist().net_name(pb_routes.at(cand_pb_route_id).atom_net_id).c_str()); } } @@ -410,7 +409,7 @@ static t_pb_graph_pin* find_used_sink_pb_pin(t_pb_graph_pin* driver_pb_pin, /******************************************************************** * Try to find the atom pin that is mapped to the sink pb_graph_pin - * which can be traced back through the pb routing tree + * which can be traced back through the pb routing tree * * Note: * - This function assumes only 1 sink node to be found @@ -419,13 +418,13 @@ static t_pb_graph_pin* find_used_sink_pb_pin(t_pb_graph_pin* driver_pb_pin, * * Top-level pb_type * +---------------------------- - * | +------------------------ + * | +------------------------ * | | Primitive pb_type * | | +------------------ * | | | - * driver +---+---->| sink pb_pin <------> atom_pin + * driver +---+---->| sink pb_pin <------> atom_pin * pb_route | - * + * *******************************************************************/ static AtomPinId find_mapped_atom_pin(const AtomContext& atom_ctx, const IntraLbPbPinLookup& intra_lb_pb_pin_lookup, @@ -451,9 +450,9 @@ static AtomPinId find_mapped_atom_pin(const AtomContext& atom_ctx, const t_pb_graph_pin* sink_pb_pin = intra_lb_pb_pin_lookup.pb_gpin(logical_type->index, sink_pb_route_id); const t_pb* leaf_pb = pb->find_pb(sink_pb_pin->parent_node); - const AtomPortId& atom_port = atom_ctx.nlist.find_atom_port(atom_ctx.lookup.pb_atom(leaf_pb), sink_pb_pin->port->model_port); + const AtomPortId& atom_port = atom_ctx.netlist().find_atom_port(atom_ctx.lookup().atom_pb_bimap().pb_atom(leaf_pb), sink_pb_pin->port->model_port); BitIndex atom_pin_bit_index = leaf_pb->atom_pin_bit_index(sink_pb_pin); - AtomPinId mapped_atom_pin = atom_ctx.nlist.port_pin(atom_port, atom_pin_bit_index); + AtomPinId mapped_atom_pin = atom_ctx.netlist().port_pin(atom_port, atom_pin_bit_index); return mapped_atom_pin; } @@ -462,20 +461,20 @@ static AtomPinId find_mapped_atom_pin(const AtomContext& atom_ctx, * Cache the mapping from atom pin to pb_graph pin for remapped nets * in current routing traces * - * Note: + * Note: * - The pb_route_id is the routing trace id for top-level pins ONLY! * - This is only applicable to the following case: * * Top-level pb_type * +---------------------------- - * | +------------------------ + * | +------------------------ * | | Primitive pb_type * | | +------------------ * | | | * driver +---+---->| sink * | * - * + * * Anything violates the assumption will be NOT be cached!!! *******************************************************************/ static std::map> cache_atom_pin_to_pb_pin_mapping(const AtomContext& atom_ctx, @@ -522,7 +521,7 @@ static std::map> cache_atom_pin /* Sometimes the routing traces is not what we target, skip caching */ if (orig_mapped_atom_pin) { - atom_pin_to_pb_pin_mapping[pb_route_id] = std::make_pair(orig_mapped_atom_pin, atom_ctx.lookup.atom_pin_pb_graph_pin(orig_mapped_atom_pin)); + atom_pin_to_pb_pin_mapping[pb_route_id] = std::make_pair(orig_mapped_atom_pin, atom_ctx.lookup().atom_pin_pb_graph_pin(orig_mapped_atom_pin)); } } @@ -530,7 +529,7 @@ static std::map> cache_atom_pin } /******************************************************************** - * Spot the original pb_graph_pin that is mapped + * Spot the original pb_graph_pin that is mapped * to a given net from the other equivalent pins in this port *******************************************************************/ static const t_pb_graph_pin* find_mapped_equivalent_pb_pin_by_net(t_pb* pb, @@ -577,7 +576,7 @@ static void rec_remove_downstream_pb_routes(t_pb_routes& curr_pb_routes, /******************************************************************** * Update routing traces for regular nets of a logical block - * This function should NOT + * This function should NOT * - create a routing traces but use the new routing traces * from the inputs * - modify any routing traces for global nets, @@ -603,7 +602,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom } /* Limitation: bypass output pins now - * TODO: This is due to the 'instance' equivalence port + * TODO: This is due to the 'instance' equivalence port * where outputs may be swapped. This definitely requires re-run of packing * It can not be solved by swapping routing traces now */ @@ -626,7 +625,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom VTR_ASSERT_SAFE(remapped_result != clustering_ctx.post_routing_clb_pin_nets[blk_id].end()); /* Cache the remapped net id */ - AtomNetId remapped_net = atom_ctx.lookup.atom_net(remapped_result->second); + AtomNetId remapped_net = atom_ctx.lookup().atom_net(remapped_result->second); /* Skip those pins become unmapped after remapping */ if (!remapped_net) { @@ -648,15 +647,15 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom VTR_LOGV(verbose, "Remapping routing trace for net '%s'\n", - atom_ctx.nlist.net_name(remapped_net).c_str()); + atom_ctx.netlist().net_name(remapped_net).c_str()); /* Spot the routing trace - * Two conditions could happen: + * Two conditions could happen: * - There is already a routing trace for this pin: * we just rename the net id * - There is no routed path for this pin: * we have to find a routing trace which is used by another pin - * in the same port (every pin in this port should be logic equivalent) + * in the same port (every pin in this port should be logic equivalent) * Rename the net id and pb_graph_node pins */ int pb_route_id = find_target_pb_route_from_equivalent_pins(atom_ctx, @@ -688,7 +687,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom /* Check if the sink pb_pins are accessible from the driver pb_pin * - If not accessible, remove the associated sink pin_pins - * - We will add the only accessible pin if and only if + * - We will add the only accessible pin if and only if * the driver pb_pin has only 1 fan-out according to the pb_graph * * Note: @@ -698,14 +697,14 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom * * Top-level pb_type * +---------------------------- - * | +------------------------ + * | +------------------------ * | | Primitive pb_type * | | +------------------ * | | | * driver +---+---->| sink * | * - * + * * Anything violates the assumption will be errored out! */ new_pb_route.sink_pb_pin_ids.clear(); @@ -741,7 +740,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom for (const int& sink_pb_route : new_pb_route.sink_pb_pin_ids) { if (0 == new_pb_routes.count(sink_pb_route)) { /* A new sink pb_pin requires a new pb_route to be added - * This could lead to a chain effect to add new pb_routes + * This could lead to a chain effect to add new pb_routes * We keep adding the pb_pin until we reach a primitive pb_type * All the sink pb_pin of the pb_route to be added * must meet the following requirements @@ -779,14 +778,14 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom "Add a new trace '%d' linked to pin '%s' for net '%s'.\n", new_sink_pb_route_id, new_sink_pb_pin_to_add->to_string().c_str(), - atom_ctx.nlist.net_name(remapped_net).c_str()); + atom_ctx.netlist().net_name(remapped_net).c_str()); /* Update the pins to add for next round */ new_driver_pb_pin = new_sink_pb_pin_to_add->pin_count_in_cluster; new_sink_pb_pin_to_add = next_sink_pb_pin_to_add; } /* The chain effect will lead to a remapping to atom net pins - * Fix the atom net lookup + * Fix the atom net lookup */ VTR_ASSERT(1 == pb->pb_route.at(pb_route_id).sink_pb_pin_ids.size()); const AtomPinId& orig_mapped_atom_pin = previous_atom_pin_to_pb_pin_mapping.at(pb_route_id).first; @@ -795,17 +794,17 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom VTR_LOGV(verbose, "Redirect atom pin '%lu' mapping from '%s' to '%s' for net '%s'.\n", size_t(orig_mapped_atom_pin), - atom_ctx.lookup.atom_pin_pb_graph_pin(orig_mapped_atom_pin)->to_string().c_str(), + atom_ctx.lookup().atom_pin_pb_graph_pin(orig_mapped_atom_pin)->to_string().c_str(), new_sink_pb_pin_to_add->to_string().c_str(), - atom_ctx.nlist.net_name(remapped_net).c_str()); + atom_ctx.netlist().net_name(remapped_net).c_str()); /* Update the pin binding in atom netlist fast look-up */ - atom_ctx.lookup.set_atom_pin_pb_graph_pin(orig_mapped_atom_pin, new_sink_pb_pin_to_add); - VTR_ASSERT(new_sink_pb_pin_to_add == atom_ctx.lookup.atom_pin_pb_graph_pin(orig_mapped_atom_pin)); + atom_ctx.mutable_lookup().set_atom_pin_pb_graph_pin(orig_mapped_atom_pin, new_sink_pb_pin_to_add); + VTR_ASSERT(new_sink_pb_pin_to_add == atom_ctx.lookup().atom_pin_pb_graph_pin(orig_mapped_atom_pin)); /* Update the pin rotation map */ t_pb* atom_pb = pb->find_mutable_pb(new_sink_pb_pin_to_add->parent_node); - atom_pb->set_atom_pin_bit_index(new_sink_pb_pin_to_add, atom_ctx.nlist.pin_port_bit(orig_mapped_atom_pin)); + atom_pb->set_atom_pin_bit_index(new_sink_pb_pin_to_add, atom_ctx.netlist().pin_port_bit(orig_mapped_atom_pin)); } else { new_pb_routes[sink_pb_route].driver_pb_pin_id = pb_graph_pin->pin_count_in_cluster; @@ -829,7 +828,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom } /* Since this routing trace was mapped to another net, - * we have to spot the original pb_graph_pin that is mapped + * we have to spot the original pb_graph_pin that is mapped * to this net (from the other equivalent pins in this port) * Then we can find out the atom pin that is linked to the remapped net */ @@ -841,17 +840,17 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom VTR_LOGV(verbose, "Redirect atom pin '%lu' mapping from '%s' to '%s' for net '%s'.\n", size_t(orig_mapped_atom_pin), - atom_ctx.lookup.atom_pin_pb_graph_pin(orig_mapped_atom_pin)->to_string().c_str(), + atom_ctx.lookup().atom_pin_pb_graph_pin(orig_mapped_atom_pin)->to_string().c_str(), next_pb_pin->to_string().c_str(), - atom_ctx.nlist.net_name(remapped_net).c_str()); + atom_ctx.netlist().net_name(remapped_net).c_str()); /* Update the pin binding in atom netlist fast look-up */ - atom_ctx.lookup.set_atom_pin_pb_graph_pin(orig_mapped_atom_pin, next_pb_pin); - VTR_ASSERT(next_pb_pin == atom_ctx.lookup.atom_pin_pb_graph_pin(orig_mapped_atom_pin)); + atom_ctx.mutable_lookup().set_atom_pin_pb_graph_pin(orig_mapped_atom_pin, next_pb_pin); + VTR_ASSERT(next_pb_pin == atom_ctx.lookup().atom_pin_pb_graph_pin(orig_mapped_atom_pin)); /* Update the pin rotation map */ t_pb* atom_pb = pb->find_mutable_pb(next_pb_pin->parent_node); - atom_pb->set_atom_pin_bit_index(next_pb_pin, atom_ctx.nlist.pin_port_bit(orig_mapped_atom_pin)); + atom_pb->set_atom_pin_bit_index(next_pb_pin, atom_ctx.netlist().pin_port_bit(orig_mapped_atom_pin)); } } } @@ -861,7 +860,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom "Remap clustered block '%s' routing trace[%d] to net '%s'\n", clustering_ctx.clb_nlist.block_pb(blk_id)->name, pb_graph_pin->pin_count_in_cluster, - atom_ctx.nlist.net_name(remapped_net).c_str()); + atom_ctx.netlist().net_name(remapped_net).c_str()); /* Update fixup counter */ num_fixup++; @@ -870,7 +869,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom /******************************************************************** * Update routing traces for global nets of a logical block - * This function should NOT + * This function should NOT * - create a routing traces but use the new routing traces * from the inputs * - modify any routing traces for non-global nets, @@ -891,7 +890,7 @@ static void update_cluster_global_routing_traces_with_post_routing_results(const const t_pb_graph_pin* pb_graph_pin = get_pb_graph_node_pin_from_block_pin(blk_id, pb_type_pin); /* Limitation: bypass output pins now - * TODO: This is due to the 'instance' equivalence port + * TODO: This is due to the 'instance' equivalence port * where outputs may be swapped. This definitely requires re-run of packing * It can not be solved by swapping routing traces now */ @@ -913,7 +912,7 @@ static void update_cluster_global_routing_traces_with_post_routing_results(const continue; } - AtomNetId global_atom_net_id = atom_ctx.lookup.atom_net(global_net_id); + AtomNetId global_atom_net_id = atom_ctx.lookup().atom_net(global_net_id); auto remapped_result = clustering_ctx.post_routing_clb_pin_nets.at(blk_id).find(pb_graph_pin->pin_count_in_cluster); @@ -928,7 +927,7 @@ static void update_cluster_global_routing_traces_with_post_routing_results(const VTR_LOGV(verbose, "Remapping clustered block '%s' global net '%s' to unused pin as %s\r", clustering_ctx.clb_nlist.block_pb(blk_id)->name, - atom_ctx.nlist.net_name(global_atom_net_id).c_str(), + atom_ctx.netlist().net_name(global_atom_net_id).c_str(), pb_graph_pin->to_string().c_str()); const t_pb_graph_pin* unused_pb_graph_pin = find_unused_pb_graph_pin_in_the_same_port(pb_graph_pin, new_pb_routes, global_atom_net_id); @@ -959,7 +958,7 @@ static void update_cluster_global_routing_traces_with_post_routing_results(const VTR_LOGV(verbose, "Remap clustered block '%s' global net '%s' to pin '%s'\n", clustering_ctx.clb_nlist.block_pb(blk_id)->name, - atom_ctx.nlist.net_name(global_atom_net_id).c_str(), + atom_ctx.netlist().net_name(global_atom_net_id).c_str(), unused_pb_graph_pin->to_string().c_str()); /* Update fixup counter */ @@ -972,7 +971,7 @@ static void update_cluster_global_routing_traces_with_post_routing_results(const * This function will directly update the nets of routing traces * stored in the clustered block by considering the post-routing results * - * Note: + * Note: * - This function should be called AFTER the function * update_cluster_pin_with_post_routing_results() *******************************************************************/ @@ -1033,8 +1032,8 @@ void sync_netlists_to_routing(const Netlist<>& net_list, /* Create net-to-rr_node mapping */ vtr::vector rr_node_nets = annotate_rr_node_nets(clustering_ctx, - device_ctx, - verbose); + device_ctx, + verbose); IntraLbPbPinLookup intra_lb_pb_pin_lookup(device_ctx.logical_block_types); diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 9cda9de0360..05912f70b12 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -27,6 +27,7 @@ #include "vpr_utils.h" #include "vtr_assert.h" #include "vtr_range.h" +#include "vtr_time.h" #include "vtr_util.h" #include "vtr_vector.h" @@ -39,13 +40,6 @@ static void free_list_of_pack_patterns(std::vector& list_of_pac static void free_pack_pattern(t_pack_patterns* pack_pattern); -static t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_pack_patterns, - vtr::vector& expected_lowest_cost_pb_gnode, - const int num_packing_patterns, - std::multimap& atom_molecules, - const AtomNetlist& atom_nlist, - const std::vector& logical_block_types); - static void discover_pattern_names_in_pb_graph_node(t_pb_graph_node* pb_graph_node, std::unordered_map& pattern_names); @@ -53,20 +47,18 @@ static void forward_infer_pattern(t_pb_graph_pin* pb_graph_pin); static void backward_infer_pattern(t_pb_graph_pin* pb_graph_pin); -static std::vector alloc_and_init_pattern_list_from_hash(std::unordered_map pattern_names); +static std::vector alloc_and_init_pattern_list_from_hash(const std::unordered_map& pattern_names); static t_pb_graph_edge* find_expansion_edge_of_pattern(const int pattern_index, const t_pb_graph_node* pb_graph_node); static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansion_edge, - t_pack_patterns* list_of_packing_patterns, - const int curr_pattern_index, + t_pack_patterns& packing_pattern, int* L_num_blocks, const bool make_root_of_chain); static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansion_edge, - t_pack_patterns* list_of_packing_patterns, - const int curr_pattern_index, + t_pack_patterns& packing_pattern, t_pb_graph_pin* destination_pin, t_pack_pattern_block* destination_block, int* L_num_blocks); @@ -75,21 +67,15 @@ static int compare_pack_pattern(const t_pack_patterns* pattern_a, const t_pack_p static void free_pack_pattern_block(t_pack_pattern_block* pattern_block, t_pack_pattern_block** pattern_block_list); -static t_pack_molecule* try_create_molecule(t_pack_patterns* list_of_pack_patterns, - const int pack_pattern_index, - AtomBlockId blk_id, - std::multimap& atom_molecules, - const AtomNetlist& atom_nlist); - -static bool try_expand_molecule(t_pack_molecule* molecule, +static bool try_expand_molecule(t_pack_molecule& molecule, const AtomBlockId blk_id, - const std::multimap& atom_molecules, + const std::multimap& atom_molecules, const AtomNetlist& atom_nlist); static void print_pack_molecules(const char* fname, - const t_pack_patterns* list_of_pack_patterns, + const std::vector& list_of_pack_patterns, const int num_pack_patterns, - const t_pack_molecule* list_of_molecules, + const vtr::vector_map& pack_molecules, const AtomNetlist& atom_nlist); static t_pb_graph_node* get_expected_lowest_cost_primitive_for_atom_block(const AtomBlockId blk_id, @@ -99,7 +85,7 @@ static t_pb_graph_node* get_expected_lowest_cost_primitive_for_atom_block_in_pb_ static AtomBlockId find_new_root_atom_for_chain(const AtomBlockId blk_id, const t_pack_patterns* list_of_pack_patterns, - const std::multimap& atom_molecules, + const std::multimap& atom_molecules, const AtomNetlist& atom_nlist); static std::vector find_end_of_path(t_pb_graph_pin* input_pin, int pattern_index); @@ -114,8 +100,10 @@ static void update_chain_root_pins(t_pack_patterns* chain_pattern, static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, std::vector& connected_primitive_pins); static void init_molecule_chain_info(const AtomBlockId blk_id, - t_pack_molecule* molecule, - const std::multimap& atom_molecules, + t_pack_molecule& molecule, + const vtr::vector_map& pack_molecules, + const std::multimap& atom_molecules, + vtr::vector& chain_info, const AtomNetlist& atom_nlist); static AtomBlockId get_sink_block(const AtomBlockId block_id, @@ -146,7 +134,6 @@ static void print_chain_starting_points(t_pack_patterns* chain_pattern); */ static std::vector alloc_and_load_pack_patterns(const std::vector& logical_block_types) { int L_num_blocks; - std::vector list_of_packing_patterns; t_pb_graph_edge* expansion_edge; /* alloc and initialize array of packing patterns based on architecture complex blocks */ @@ -155,7 +142,7 @@ static std::vector alloc_and_load_pack_patterns(const std::vect discover_pattern_names_in_pb_graph_node(type.pb_graph_head, pattern_names); } - list_of_packing_patterns = alloc_and_init_pattern_list_from_hash(pattern_names); + std::vector packing_patterns = alloc_and_init_pattern_list_from_hash(pattern_names); /* load packing patterns by traversing the edges to find edges belonging to pattern */ for (size_t i = 0; i < pattern_names.size(); i++) { @@ -167,30 +154,30 @@ static std::vector alloc_and_load_pack_patterns(const std::vect } L_num_blocks = 0; - list_of_packing_patterns[i].base_cost = 0; + packing_patterns[i].base_cost = 0; // use the found expansion edge to build the pack pattern backward_expand_pack_pattern_from_edge(expansion_edge, - list_of_packing_patterns.data(), i, nullptr, nullptr, &L_num_blocks); - list_of_packing_patterns[i].num_blocks = L_num_blocks; + packing_patterns[i], nullptr, nullptr, &L_num_blocks); + packing_patterns[i].num_blocks = L_num_blocks; /* Default settings: A section of a netlist must match all blocks in a pack * pattern before it can be made a molecule except for carry-chains. * For carry-chains, since carry-chains are typically quite flexible in terms * of size, it is optional whether or not an atom in a netlist matches any * particular block inside the chain */ - list_of_packing_patterns[i].is_block_optional = new bool[L_num_blocks]; + packing_patterns[i].is_block_optional = new bool[L_num_blocks]; for (int k = 0; k < L_num_blocks; k++) { - list_of_packing_patterns[i].is_block_optional[k] = false; - if (list_of_packing_patterns[i].is_chain && list_of_packing_patterns[i].root_block->block_id != k) { - list_of_packing_patterns[i].is_block_optional[k] = true; + packing_patterns[i].is_block_optional[k] = false; + if (packing_patterns[i].is_chain && packing_patterns[i].root_block->block_id != k) { + packing_patterns[i].is_block_optional[k] = true; } } // if this is a chain pattern (extends between complex blocks), check if there // are multiple equivalent chains with different starting and ending points - if (list_of_packing_patterns[i].is_chain) { - find_all_equivalent_chains(&list_of_packing_patterns[i], type.pb_graph_head); - print_chain_starting_points(&list_of_packing_patterns[i]); + if (packing_patterns[i].is_chain) { + find_all_equivalent_chains(&packing_patterns[i], type.pb_graph_head); + print_chain_starting_points(&packing_patterns[i]); } // if pack pattern i is found to belong to current block type, go to next pack pattern @@ -200,12 +187,12 @@ static std::vector alloc_and_load_pack_patterns(const std::vect //Sanity check, every pattern should have a root block for (size_t i = 0; i < pattern_names.size(); ++i) { - if (list_of_packing_patterns[i].root_block == nullptr) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find root block for pack pattern %s", list_of_packing_patterns[i].name); + if (packing_patterns[i].root_block == nullptr) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find root block for pack pattern %s", packing_patterns[i].name); } } - return list_of_packing_patterns; + return packing_patterns; } /** @@ -356,7 +343,7 @@ static void backward_infer_pattern(t_pb_graph_pin* pb_graph_pin) { * Allocates memory for models and loads the name of the packing pattern * so that it can be identified and loaded with more complete information later */ -static std::vector alloc_and_init_pattern_list_from_hash(std::unordered_map pattern_names) { +static std::vector alloc_and_init_pattern_list_from_hash(const std::unordered_map& pattern_names) { std::vector nlist(pattern_names.size()); for (const auto& curr_pattern : pattern_names) { @@ -478,8 +465,7 @@ static t_pb_graph_edge* find_expansion_edge_of_pattern(const int pattern_index, * future multi-fanout support easier) so this function will not update connections */ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansion_edge, - t_pack_patterns* list_of_packing_patterns, - const int curr_pattern_index, + t_pack_patterns& packing_pattern, int* L_num_blocks, bool make_root_of_chain) { int i, j, k; @@ -487,6 +473,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi bool found; /* Error checking, ensure only one fan-out for each pattern net */ t_pack_pattern_block* destination_block = nullptr; t_pb_graph_node* destination_pb_graph_node = nullptr; + int curr_pattern_index = packing_pattern.index; found = expansion_edge->infer_pattern; // if the pack pattern shouldn't be inferred check if the expansion @@ -521,7 +508,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi // 2) assign an id to this pattern block, 3) increment the number of found blocks belonging to this // pattern and 4) expand all its edges to find the other primitives that belong to this pattern destination_block = new t_pack_pattern_block(); - list_of_packing_patterns[curr_pattern_index].base_cost += compute_primitive_base_cost(destination_pb_graph_node); + packing_pattern.base_cost += compute_primitive_base_cost(destination_pb_graph_node); destination_block->block_id = *L_num_blocks; (*L_num_blocks)++; destination_pb_graph_node->temp_scratch_pad = (void*)destination_block; @@ -533,8 +520,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi for (ipin = 0; ipin < destination_pb_graph_node->num_input_pins[iport]; ipin++) { for (iedge = 0; iedge < destination_pb_graph_node->input_pins[iport][ipin].num_input_edges; iedge++) { backward_expand_pack_pattern_from_edge(destination_pb_graph_node->input_pins[iport][ipin].input_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, &destination_pb_graph_node->input_pins[iport][ipin], destination_block, L_num_blocks); } @@ -546,8 +532,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi for (ipin = 0; ipin < destination_pb_graph_node->num_output_pins[iport]; ipin++) { for (iedge = 0; iedge < destination_pb_graph_node->output_pins[iport][ipin].num_output_edges; iedge++) { forward_expand_pack_pattern_from_edge(destination_pb_graph_node->output_pins[iport][ipin].output_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, L_num_blocks, false); + packing_pattern, L_num_blocks, false); } } } @@ -557,8 +542,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi for (ipin = 0; ipin < destination_pb_graph_node->num_clock_pins[iport]; ipin++) { for (iedge = 0; iedge < destination_pb_graph_node->clock_pins[iport][ipin].num_input_edges; iedge++) { backward_expand_pack_pattern_from_edge(destination_pb_graph_node->clock_pins[iport][ipin].input_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, &destination_pb_graph_node->clock_pins[iport][ipin], destination_block, L_num_blocks); } @@ -570,8 +554,8 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi if (((t_pack_pattern_block*)destination_pb_graph_node->temp_scratch_pad)->pattern_index == curr_pattern_index) { // if this pb_graph_node is known to be the root of the chain, update the root block and root pin if (make_root_of_chain == true) { - list_of_packing_patterns[curr_pattern_index].chain_root_pins = {{expansion_edge->output_pins[i]}}; - list_of_packing_patterns[curr_pattern_index].root_block = destination_block; + packing_pattern.chain_root_pins = {{expansion_edge->output_pins[i]}}; + packing_pattern.root_block = destination_block; } } @@ -581,8 +565,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi for (j = 0; j < expansion_edge->output_pins[i]->num_output_edges; j++) { if (expansion_edge->output_pins[i]->output_edges[j]->infer_pattern == true) { forward_expand_pack_pattern_from_edge(expansion_edge->output_pins[i]->output_edges[j], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, L_num_blocks, make_root_of_chain); } else { @@ -597,12 +580,11 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi expansion_edge->output_pins[i]->parent_node->placement_index, expansion_edge->output_pins[i]->port->name, expansion_edge->output_pins[i]->pin_number, - list_of_packing_patterns[curr_pattern_index].name); + packing_pattern.name); } found = true; forward_expand_pack_pattern_from_edge(expansion_edge->output_pins[i]->output_edges[j], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, L_num_blocks, make_root_of_chain); } @@ -620,8 +602,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi * destination blocks */ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansion_edge, - t_pack_patterns* list_of_packing_patterns, - const int curr_pattern_index, + t_pack_patterns& packing_pattern, t_pb_graph_pin* destination_pin, t_pack_pattern_block* destination_block, int* L_num_blocks) { @@ -631,6 +612,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans t_pack_pattern_block* source_block = nullptr; t_pb_graph_node* source_pb_graph_node = nullptr; t_pack_pattern_connections* pack_pattern_connection = nullptr; + int curr_pattern_index = packing_pattern.index; found = expansion_edge->infer_pattern; // if the pack pattern shouldn't be inferred check if the expansion @@ -664,13 +646,13 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans source_block = new t_pack_pattern_block(); source_block->block_id = *L_num_blocks; (*L_num_blocks)++; - list_of_packing_patterns[curr_pattern_index].base_cost += compute_primitive_base_cost(source_pb_graph_node); + packing_pattern.base_cost += compute_primitive_base_cost(source_pb_graph_node); source_pb_graph_node->temp_scratch_pad = (void*)source_block; source_block->pattern_index = curr_pattern_index; source_block->pb_type = source_pb_graph_node->pb_type; - if (list_of_packing_patterns[curr_pattern_index].root_block == nullptr) { - list_of_packing_patterns[curr_pattern_index].root_block = source_block; + if (packing_pattern.root_block == nullptr) { + packing_pattern.root_block = source_block; } // explore the inputs of this primitive @@ -678,8 +660,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans for (ipin = 0; ipin < source_pb_graph_node->num_input_pins[iport]; ipin++) { for (iedge = 0; iedge < source_pb_graph_node->input_pins[iport][ipin].num_input_edges; iedge++) { backward_expand_pack_pattern_from_edge(source_pb_graph_node->input_pins[iport][ipin].input_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, &source_pb_graph_node->input_pins[iport][ipin], source_block, L_num_blocks); @@ -692,8 +673,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans for (ipin = 0; ipin < source_pb_graph_node->num_output_pins[iport]; ipin++) { for (iedge = 0; iedge < source_pb_graph_node->output_pins[iport][ipin].num_output_edges; iedge++) { forward_expand_pack_pattern_from_edge(source_pb_graph_node->output_pins[iport][ipin].output_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, L_num_blocks, false); } @@ -705,8 +685,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans for (ipin = 0; ipin < source_pb_graph_node->num_clock_pins[iport]; ipin++) { for (iedge = 0; iedge < source_pb_graph_node->clock_pins[iport][ipin].num_input_edges; iedge++) { backward_expand_pack_pattern_from_edge(source_pb_graph_node->clock_pins[iport][ipin].input_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, &source_pb_graph_node->clock_pins[iport][ipin], source_block, L_num_blocks); @@ -749,11 +728,10 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans if (expansion_edge->input_pins[i]->parent_node->pb_type->parent_mode == nullptr) { // This pack pattern extends to CLB (root pb block) input pin, // thus it extends across multiple logic blocks, treat as a chain - list_of_packing_patterns[curr_pattern_index].is_chain = true; + packing_pattern.is_chain = true; // since this input pin has not driving nets, expand in the forward direction instead forward_expand_pack_pattern_from_edge(expansion_edge, - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, L_num_blocks, true); } @@ -764,8 +742,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans // if pattern should be inferred for this edge continue the expansion backwards if (expansion_edge->input_pins[i]->input_edges[j]->infer_pattern == true) { backward_expand_pack_pattern_from_edge(expansion_edge->input_pins[i]->input_edges[j], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, destination_pin, destination_block, L_num_blocks); @@ -778,8 +755,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans /* Check assumption that each forced net has only one fan-out */ found = true; backward_expand_pack_pattern_from_edge(expansion_edge->input_pins[i]->input_edges[j], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, destination_pin, destination_block, L_num_blocks); @@ -799,29 +775,18 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans * 3. Chained molecules are molecules that follow a carry-chain style pattern, * ie. a single linear chain that can be split across multiple complex blocks */ -static t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_pack_patterns, - vtr::vector& expected_lowest_cost_pb_gnode, - const int num_packing_patterns, - std::multimap& atom_molecules, - const AtomNetlist& atom_nlist, - const std::vector& logical_block_types) { - int i, j, best_pattern; - t_pack_molecule* list_of_molecules_head; - t_pack_molecule* cur_molecule; - bool* is_used; - - is_used = new bool[num_packing_patterns]; - for (i = 0; i < num_packing_patterns; i++) - is_used[i] = false; - - cur_molecule = list_of_molecules_head = nullptr; +void Prepacker::alloc_and_load_pack_molecules(std::multimap& atom_molecules_multimap, + const AtomNetlist& atom_nlist, + const std::vector& logical_block_types) { + std::vector is_used(list_of_pack_patterns.size(), false); /* Find forced pack patterns * Simplifying assumptions: Each atom can map to at most one molecule, * use first-fit mapping based on priority of pattern * TODO: Need to investigate better mapping strategies than first-fit */ - for (i = 0; i < num_packing_patterns; i++) { + size_t num_packing_patterns = list_of_pack_patterns.size(); + for (size_t i = 0; i < num_packing_patterns; i++) { /* Skip pack patterns for modes that are disabled for packing, * Ensure no resources in unpackable modes will be mapped during pre-packing stage */ @@ -830,8 +795,8 @@ static t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_p continue; } - best_pattern = 0; - for (j = 1; j < num_packing_patterns; j++) { + size_t best_pattern = 0; + for (size_t j = 1; j < num_packing_patterns; j++) { if (is_used[best_pattern]) { best_pattern = j; } else if (is_used[j] == false && compare_pack_pattern(&list_of_pack_patterns[j], &list_of_pack_patterns[best_pattern]) == 1) { @@ -845,34 +810,38 @@ static t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_p for (auto blk_iter = blocks.begin(); blk_iter != blocks.end(); ++blk_iter) { auto blk_id = *blk_iter; - cur_molecule = try_create_molecule(list_of_pack_patterns, best_pattern, blk_id, atom_molecules, atom_nlist); - if (cur_molecule != nullptr) { - cur_molecule->next = list_of_molecules_head; - /* In the event of multiple molecules with the same atom block pattern, - * bias to use the molecule with less costly physical resources first */ - /* TODO: Need to normalize magical number 100 */ - cur_molecule->base_gain = cur_molecule->num_blocks - (cur_molecule->pack_pattern->base_cost / 100); - list_of_molecules_head = cur_molecule; - - //Note: atom_molecules is an (ordered) multimap so the last molecule - // inserted for a given blk_id will be the last valid element - // in the equal_range - auto rng = atom_molecules.equal_range(blk_id); //The range of molecules matching this block - bool range_empty = (rng.first == rng.second); - bool cur_was_last_inserted = false; - if (!range_empty) { - auto last_valid_iter = --rng.second; //Iterator to last element (only valid if range is not empty) - cur_was_last_inserted = (last_valid_iter->second == cur_molecule); - } - if (range_empty || !cur_was_last_inserted) { - /* molecule did not cover current atom (possibly because molecule created is - * part of a long chain that extends past multiple logic blocks), try again */ - --blk_iter; - } + PackMoleculeId cur_molecule_id = try_create_molecule(best_pattern, + blk_id, + atom_molecules_multimap, + atom_nlist); + + // If the molecule could not be created, move to the next block. + if (!cur_molecule_id.is_valid()) + continue; + + /* In the event of multiple molecules with the same atom block pattern, + * bias to use the molecule with less costly physical resources first */ + /* TODO: Need to normalize magical number 100 */ + t_pack_molecule& cur_molecule = pack_molecules_[cur_molecule_id]; + cur_molecule.base_gain = cur_molecule.atom_block_ids.size() - (cur_molecule.pack_pattern->base_cost / 100); + + //Note: atom_molecules is an (ordered) multimap so the last molecule + // inserted for a given blk_id will be the last valid element + // in the equal_range + auto rng = atom_molecules_multimap.equal_range(blk_id); //The range of molecules matching this block + bool range_empty = (rng.first == rng.second); + bool cur_was_last_inserted = false; + if (!range_empty) { + auto last_valid_iter = --rng.second; //Iterator to last element (only valid if range is not empty) + cur_was_last_inserted = (last_valid_iter->second == cur_molecule_id); + } + if (range_empty || !cur_was_last_inserted) { + /* molecule did not cover current atom (possibly because molecule created is + * part of a long chain that extends past multiple logic blocks), try again */ + --blk_iter; } } } - delete[] is_used; /* List all atom blocks as a molecule for blocks that do not belong to any molecules. * This allows the packer to be consistent as it now packs molecules only instead of atoms and molecules @@ -883,14 +852,6 @@ static t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_p for (auto blk_id : atom_nlist.blocks()) { t_pb_graph_node* best = get_expected_lowest_cost_primitive_for_atom_block(blk_id, logical_block_types); if (!best) { - /* Free the molecules in the linked list to avoid memory leakage */ - cur_molecule = list_of_molecules_head; - while (cur_molecule) { - t_pack_molecule* molecule_to_free = cur_molecule; - cur_molecule = cur_molecule->next; - delete molecule_to_free; - } - VPR_FATAL_ERROR(VPR_ERROR_PACK, "Failed to find any location to pack primitive of type '%s' in architecture", atom_nlist.block_model(blk_id)->name); } @@ -899,33 +860,32 @@ static t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_p expected_lowest_cost_pb_gnode[blk_id] = best; - auto rng = atom_molecules.equal_range(blk_id); + auto rng = atom_molecules_multimap.equal_range(blk_id); bool rng_empty = (rng.first == rng.second); if (rng_empty) { - cur_molecule = new t_pack_molecule; - cur_molecule->type = MOLECULE_SINGLE_ATOM; - cur_molecule->num_blocks = 1; - cur_molecule->root = 0; - cur_molecule->pack_pattern = nullptr; + PackMoleculeId new_molecule_id = PackMoleculeId(pack_molecules_.size()); + t_pack_molecule new_molecule; + new_molecule.type = e_pack_pattern_molecule_type::MOLECULE_SINGLE_ATOM; + new_molecule.root = 0; + new_molecule.pack_pattern = nullptr; - cur_molecule->atom_block_ids = {blk_id}; + new_molecule.atom_block_ids = {blk_id}; - cur_molecule->next = list_of_molecules_head; - cur_molecule->base_gain = 1; - list_of_molecules_head = cur_molecule; + new_molecule.base_gain = 1; + new_molecule.chain_id = MoleculeChainId::INVALID(); - atom_molecules.insert({blk_id, cur_molecule}); + atom_molecules_multimap.insert({blk_id, new_molecule_id}); + pack_molecules_.push_back(std::move(new_molecule)); + pack_molecule_ids_.push_back(new_molecule_id); } } if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS)) { print_pack_molecules(getEchoFileName(E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS), list_of_pack_patterns, num_packing_patterns, - list_of_molecules_head, + pack_molecules_, atom_nlist); } - - return list_of_molecules_head; } static void free_pack_pattern_block(t_pack_pattern_block* pattern_block, t_pack_pattern_block** pattern_block_list) { @@ -959,59 +919,59 @@ static void free_pack_pattern_block(t_pack_pattern_block* pattern_block, t_pack_ * * Side Effect: If successful, link atom to molecule */ -static t_pack_molecule* try_create_molecule(t_pack_patterns* list_of_pack_patterns, - const int pack_pattern_index, - AtomBlockId blk_id, - std::multimap& atom_molecules, - const AtomNetlist& atom_nlist) { - t_pack_molecule* molecule; - +PackMoleculeId Prepacker::try_create_molecule(const int pack_pattern_index, + AtomBlockId blk_id, + std::multimap& atom_molecules_multimap, + const AtomNetlist& atom_nlist) { auto pack_pattern = &list_of_pack_patterns[pack_pattern_index]; // Check pack pattern validity if (pack_pattern == nullptr || pack_pattern->num_blocks == 0 || pack_pattern->root_block == nullptr) { - return nullptr; + return PackMoleculeId::INVALID(); } // If a chain pattern extends beyond a single logic block, we must find // the furthest blk_id up the chain that is not mapped to a molecule yet. if (pack_pattern->is_chain) { - blk_id = find_new_root_atom_for_chain(blk_id, pack_pattern, atom_molecules, atom_nlist); - if (!blk_id) return nullptr; + blk_id = find_new_root_atom_for_chain(blk_id, pack_pattern, atom_molecules_multimap, atom_nlist); + if (!blk_id) return PackMoleculeId::INVALID(); } - molecule = new t_pack_molecule; - molecule->type = MOLECULE_FORCED_PACK; - molecule->pack_pattern = pack_pattern; - molecule->atom_block_ids = std::vector(pack_pattern->num_blocks); //Initializes invalid - molecule->num_blocks = pack_pattern->num_blocks; - molecule->root = pack_pattern->root_block->block_id; + PackMoleculeId new_molecule_id = PackMoleculeId(pack_molecules_.size()); + t_pack_molecule molecule; + molecule.base_gain = 0.f; + molecule.type = e_pack_pattern_molecule_type::MOLECULE_FORCED_PACK; + molecule.pack_pattern = pack_pattern; + molecule.atom_block_ids = std::vector(pack_pattern->num_blocks); //Initializes invalid + molecule.root = pack_pattern->root_block->block_id; + molecule.chain_id = MoleculeChainId::INVALID(); - if (try_expand_molecule(molecule, blk_id, atom_molecules, atom_nlist)) { - // Success! commit molecule + if (!try_expand_molecule(molecule, blk_id, atom_molecules_multimap, atom_nlist)) { + // Failed to create molecule + return PackMoleculeId::INVALID(); + } - // update chain info for chain molecules - if (molecule->pack_pattern->is_chain) { - init_molecule_chain_info(blk_id, molecule, atom_molecules, atom_nlist); - } + // Success! commit molecule - // update the atom_molcules with the atoms that are mapped to this molecule - for (int i = 0; i < molecule->pack_pattern->num_blocks; i++) { - auto blk_id2 = molecule->atom_block_ids[i]; - if (!blk_id2) { - VTR_ASSERT(molecule->pack_pattern->is_block_optional[i]); - continue; - } + // update chain info for chain molecules + if (molecule.pack_pattern->is_chain) { + init_molecule_chain_info(blk_id, molecule, pack_molecules_, atom_molecules_multimap, chain_info_, atom_nlist); + } - atom_molecules.insert({blk_id2, molecule}); + // update the atom_molcules with the atoms that are mapped to this molecule + for (int i = 0; i < molecule.pack_pattern->num_blocks; i++) { + auto blk_id2 = molecule.atom_block_ids[i]; + if (!blk_id2) { + VTR_ASSERT(molecule.pack_pattern->is_block_optional[i]); + continue; } - } else { - // Failed to create molecule - delete molecule; - return nullptr; + + atom_molecules_multimap.insert({blk_id2, new_molecule_id}); } - return molecule; + pack_molecules_.push_back(std::move(molecule)); + pack_molecule_ids_.push_back(new_molecule_id); + return new_molecule_id; } /** @@ -1027,15 +987,15 @@ static t_pack_molecule* try_create_molecule(t_pack_patterns* list_of_pack_patter * atom_molecules : map of atom block ids that are assigned a molecule and a pointer to this molecule * blk_id : chosen to be the root of this molecule and the code is expanding from */ -static bool try_expand_molecule(t_pack_molecule* molecule, +static bool try_expand_molecule(t_pack_molecule& molecule, const AtomBlockId blk_id, - const std::multimap& atom_molecules, + const std::multimap& atom_molecules, const AtomNetlist& atom_nlist) { // root block of the pack pattern, which is the starting point of this pattern - const auto pattern_root_block = molecule->pack_pattern->root_block; + const auto pattern_root_block = molecule.pack_pattern->root_block; // bool array indicating whether a position in a pack pattern is optional or should // be filled with an atom for legality - const auto is_block_optional = molecule->pack_pattern->is_block_optional; + const auto is_block_optional = molecule.pack_pattern->is_block_optional; // create a queue of pattern block and atom block id suggested for this block std::queue> pattern_block_queue; @@ -1054,7 +1014,7 @@ static bool try_expand_molecule(t_pack_molecule* molecule, pattern_block_queue.pop(); // get the atom block id of the atom occupying this primitive position in this molecule - auto molecule_atom_block_id = molecule->atom_block_ids[pattern_block->block_id]; + auto molecule_atom_block_id = molecule.atom_block_ids[pattern_block->block_id]; // if this primitive position in this molecule is already visited and // matches block in the atom netlist go to the next node in the queue @@ -1078,7 +1038,7 @@ static bool try_expand_molecule(t_pack_molecule* molecule, } // set this node in the molecule as visited - molecule->atom_block_ids[pattern_block->block_id] = block_id; + molecule.atom_block_ids[pattern_block->block_id] = block_id; // starting from the first connections, add all the connections of this block to the queue auto block_connection = pattern_block->connections; @@ -1178,13 +1138,12 @@ static AtomBlockId get_driving_block(const AtomBlockId block_id, } static void print_pack_molecules(const char* fname, - const t_pack_patterns* list_of_pack_patterns, + const std::vector& list_of_pack_patterns, const int num_pack_patterns, - const t_pack_molecule* list_of_molecules, + const vtr::vector_map& pack_molecules, const AtomNetlist& atom_nlist) { int i; FILE* fp; - const t_pack_molecule* list_of_molecules_current; fp = std::fopen(fname, "w"); fprintf(fp, "# of pack patterns %d\n", num_pack_patterns); @@ -1198,24 +1157,23 @@ static void print_pack_molecules(const char* fname, list_of_pack_patterns[i].root_block->pb_type->name); } - list_of_molecules_current = list_of_molecules; - while (list_of_molecules_current != nullptr) { - if (list_of_molecules_current->type == MOLECULE_SINGLE_ATOM) { + for (const t_pack_molecule& molecule : pack_molecules) { + if (molecule.type == e_pack_pattern_molecule_type::MOLECULE_SINGLE_ATOM) { fprintf(fp, "\nmolecule type: atom\n"); fprintf(fp, "\tpattern index %d: atom block %s\n", i, - atom_nlist.block_name(list_of_molecules_current->atom_block_ids[0]).c_str()); - } else if (list_of_molecules_current->type == MOLECULE_FORCED_PACK) { + atom_nlist.block_name(molecule.atom_block_ids[0]).c_str()); + } else if (molecule.type == e_pack_pattern_molecule_type::MOLECULE_FORCED_PACK) { fprintf(fp, "\nmolecule type: %s\n", - list_of_molecules_current->pack_pattern->name); - for (i = 0; i < list_of_molecules_current->pack_pattern->num_blocks; + molecule.pack_pattern->name); + for (i = 0; i < molecule.pack_pattern->num_blocks; i++) { - if (!list_of_molecules_current->atom_block_ids[i]) { + if (!molecule.atom_block_ids[i]) { fprintf(fp, "\tpattern index %d: empty \n", i); } else { fprintf(fp, "\tpattern index %d: atom block %s", i, - atom_nlist.block_name(list_of_molecules_current->atom_block_ids[i]).c_str()); - if (list_of_molecules_current->pack_pattern->root_block->block_id == i) { + atom_nlist.block_name(molecule.atom_block_ids[i]).c_str()); + if (molecule.pack_pattern->root_block->block_id == i) { fprintf(fp, " root node\n"); } else { fprintf(fp, "\n"); @@ -1225,7 +1183,6 @@ static void print_pack_molecules(const char* fname, } else { VTR_ASSERT(0); } - list_of_molecules_current = list_of_molecules_current->next; } fclose(fp); @@ -1332,7 +1289,7 @@ static int compare_pack_pattern(const t_pack_patterns* pattern_a, const t_pack_p */ static AtomBlockId find_new_root_atom_for_chain(const AtomBlockId blk_id, const t_pack_patterns* list_of_pack_patterns, - const std::multimap& atom_molecules, + const std::multimap& atom_molecules, const AtomNetlist& atom_nlist) { AtomBlockId new_root_blk_id; t_pb_graph_pin* root_ipin; @@ -1630,14 +1587,16 @@ static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input * and so on. */ static void init_molecule_chain_info(const AtomBlockId blk_id, - t_pack_molecule* molecule, - const std::multimap &atom_molecules, + t_pack_molecule& molecule, + const vtr::vector_map& pack_molecules, + const std::multimap& atom_molecules, + vtr::vector& chain_info, const AtomNetlist& atom_nlist) { // the input molecule to this function should have a pack // pattern assigned to it and the input block should be valid - VTR_ASSERT(molecule->pack_pattern && blk_id); + VTR_ASSERT(molecule.pack_pattern && blk_id); - auto root_ipin = molecule->pack_pattern->chain_root_pins[0][0]; + auto root_ipin = molecule.pack_pattern->chain_root_pins[0][0]; auto model_pin = root_ipin->port->model_port; auto pin_bit = root_ipin->pin_number; @@ -1652,18 +1611,23 @@ static void init_molecule_chain_info(const AtomBlockId blk_id, // if either there is no driver to the block input pin or // if the driver is not part of a molecule if (!driver_atom_id || itr == atom_molecules.end()) { - // allocate chain info - molecule->chain_info = std::make_shared(); - // this is not the first molecule to be created for this chain + MoleculeChainId new_chain_id = MoleculeChainId(chain_info.size()); + t_chain_info new_chain_info; + new_chain_info.is_long_chain = false; + chain_info.push_back(std::move(new_chain_info)); + molecule.chain_id = new_chain_id; } else { + // this is not the first molecule to be created for this chain // molecule driving blk_id - auto prev_molecule = itr->second; + PackMoleculeId prev_molecule_id = itr->second; + VTR_ASSERT(prev_molecule_id.is_valid()); + const t_pack_molecule& prev_molecule = pack_molecules[prev_molecule_id]; // molecule should have chain_info associated with it - VTR_ASSERT(prev_molecule && prev_molecule->chain_info); + VTR_ASSERT(prev_molecule.chain_id.is_valid()); // this molecule is now known to belong to a long chain - prev_molecule->chain_info->is_long_chain = true; - // this new molecule should share the same chain_info - molecule->chain_info = prev_molecule->chain_info; + chain_info[prev_molecule.chain_id].is_long_chain = true; + // this new molecule should share the same chain + molecule.chain_id = prev_molecule.chain_id; } } @@ -1689,55 +1653,44 @@ static void print_chain_starting_points(t_pack_patterns* chain_pattern) { VTR_LOG("\n"); } -/** - * This function frees the linked list of pack molecules. - */ -static void free_pack_molecules(t_pack_molecule* list_of_pack_molecules) { - t_pack_molecule* cur_pack_molecule = list_of_pack_molecules; - while (cur_pack_molecule != nullptr) { - cur_pack_molecule = list_of_pack_molecules->next; - delete list_of_pack_molecules; - list_of_pack_molecules = cur_pack_molecule; - } -} - -void Prepacker::init(const AtomNetlist& atom_nlist, const std::vector& logical_block_types) { - VTR_ASSERT(list_of_pack_molecules == nullptr && "Prepacker cannot be initialized twice."); +Prepacker::Prepacker(const AtomNetlist& atom_nlist, + const std::vector& logical_block_types) { + vtr::ScopedStartFinishTimer prepacker_timer("Prepacker"); // Allocate the pack patterns from the logical block types. list_of_pack_patterns = alloc_and_load_pack_patterns(logical_block_types); // Use the pack patterns to allocate and load the pack molecules. - std::multimap atom_molecules_multimap; + std::multimap atom_molecules_multimap; expected_lowest_cost_pb_gnode.resize(atom_nlist.blocks().size(), nullptr); - list_of_pack_molecules = alloc_and_load_pack_molecules(list_of_pack_patterns.data(), - expected_lowest_cost_pb_gnode, - list_of_pack_patterns.size(), - atom_molecules_multimap, - atom_nlist, - logical_block_types); + alloc_and_load_pack_molecules(atom_molecules_multimap, + atom_nlist, + logical_block_types); // The multimap is a legacy thing. Since blocks can be part of multiple pack // patterns, during prepacking a block may be contained within multiple // molecules. However, by the end of prepacking, molecules should be // combined such that each block is contained in one and only one molecule. - atom_molecules.resize(atom_nlist.blocks().size(), nullptr); + atom_molecule_.resize(atom_nlist.blocks().size(), PackMoleculeId::INVALID()); for (AtomBlockId blk_id : atom_nlist.blocks()) { // Every atom block should be packed into a single molecule (no more // or less). VTR_ASSERT(atom_molecules_multimap.count(blk_id) == 1); - atom_molecules[blk_id] = atom_molecules_multimap.find(blk_id)->second; + atom_molecule_[blk_id] = atom_molecules_multimap.find(blk_id)->second; } } // TODO: Since this is constant per molecule, it may make sense to precompute // this information and store it in the prepacker class. This may be // expensive to calculate for large molecules. -t_molecule_stats Prepacker::calc_molecule_stats(const t_pack_molecule* molecule, +t_molecule_stats Prepacker::calc_molecule_stats(PackMoleculeId molecule_id, const AtomNetlist& atom_nlist) const { + VTR_ASSERT(molecule_id.is_valid()); t_molecule_stats molecule_stats; + const t_pack_molecule& molecule = pack_molecules_[molecule_id]; + //Calculate the number of available pins on primitives within the molecule - for (auto blk : molecule->atom_block_ids) { + for (auto blk : molecule.atom_block_ids) { if (!blk) continue; ++molecule_stats.num_blocks; //Record number of valid blocks in molecule @@ -1755,8 +1708,8 @@ t_molecule_stats Prepacker::calc_molecule_stats(const t_pack_molecule* molecule, molecule_stats.num_pins = molecule_stats.num_input_pins + molecule_stats.num_output_pins; //Calculate the number of externally used pins - std::set molecule_atoms(molecule->atom_block_ids.begin(), molecule->atom_block_ids.end()); - for (auto blk : molecule->atom_block_ids) { + std::set molecule_atoms(molecule.atom_block_ids.begin(), molecule.atom_block_ids.end()); + for (auto blk : molecule.atom_block_ids) { if (!blk) continue; for (auto pin : atom_nlist.block_pins(blk)) { @@ -1803,11 +1756,9 @@ t_molecule_stats Prepacker::calc_molecule_stats(const t_pack_molecule* molecule, t_molecule_stats Prepacker::calc_max_molecule_stats(const AtomNetlist& atom_nlist) const { t_molecule_stats max_molecules_stats; - t_pack_molecule* molecule_head = list_of_pack_molecules; - for (auto cur_molecule = molecule_head; cur_molecule != nullptr; cur_molecule = cur_molecule->next) { + for (PackMoleculeId molecule_id : molecules()) { //Calculate per-molecule statistics - (void)atom_nlist; - t_molecule_stats cur_molecule_stats = calc_molecule_stats(cur_molecule, atom_nlist); + t_molecule_stats cur_molecule_stats = calc_molecule_stats(molecule_id, atom_nlist); //Record the maximums (member-wise) over all molecules max_molecules_stats.num_blocks = std::max(max_molecules_stats.num_blocks, cur_molecule_stats.num_blocks); @@ -1824,15 +1775,8 @@ t_molecule_stats Prepacker::calc_max_molecule_stats(const AtomNetlist& atom_nlis return max_molecules_stats; } -void Prepacker::reset() { +Prepacker::~Prepacker() { // When the prepacker is reset (or destroyed), clean up the internal data // members. free_list_of_pack_patterns(list_of_pack_patterns); - free_pack_molecules(list_of_pack_molecules); - // Reset everything to default state. - list_of_pack_patterns.clear(); - list_of_pack_molecules = nullptr; - atom_molecules.clear(); - expected_lowest_cost_pb_gnode.clear(); } - diff --git a/vpr/src/pack/prepack.h b/vpr/src/pack/prepack.h index 810c79bd19c..5222046ddb6 100644 --- a/vpr/src/pack/prepack.h +++ b/vpr/src/pack/prepack.h @@ -7,19 +7,111 @@ * 2) Carry-chains */ -#ifndef PREPACK_H -#define PREPACK_H +#pragma once #include -#include "vpr_types.h" +#include "atom_netlist_fwd.h" +#include "cad_types.h" #include "vtr_assert.h" +#include "vtr_range.h" +#include "vtr_strong_id.h" #include "vtr_vector.h" +#include "vtr_vector_map.h" -class AtomNetlist; -class AtomBlockId; -struct t_molecule_stats; +// Forward declarations +class t_pack_molecule; struct t_logical_block_type; +// A unique ID used to identify a molecule generated by the prepacker. +struct pack_molecule_id_tag; +typedef vtr::StrongId PackMoleculeId; + +// A unique ID used to identify a chain of molecules generated by the prepacker. +struct molecule_chain_id_tag; +typedef vtr::StrongId MoleculeChainId; + +/** + * @brief Holds general information to be shared between molecules that + * represent the same chained pack pattern. + * + * For example, molecules that are representing a long carry chain that spans + * multiple logic blocks. + */ +struct t_chain_info { + /// @brief Is this a long chain that is divided on multiple clusters + /// (divided on multiple molecules). + bool is_long_chain = false; +}; + +/** + * @brief Describes the molecule pack pattern type. + */ +enum class e_pack_pattern_molecule_type : bool { + MOLECULE_SINGLE_ATOM, ///root_block in the atom_blocks_ids. + /// root_block_id = atom_block_ids[root] + int root; + + /// @brief [0..num_blocks-1] IDs of atom blocks that implements this molecule, + /// indexed by t_pack_pattern_block->block_id. + /// + /// This vector may contain invalid atom block ids (when the molecule does + /// not completely fill the pattern). + std::vector atom_block_ids; + + /// @brief The unique ID of the chain this molecule is a part of if is_chain. + /// If this molecule is not part of a chain, this would be invalid. + /// + /// Multiple molecules may point to the same chain. + MoleculeChainId chain_id; + + // ========================================================================= + // Class methods + // ========================================================================= + + // A molecule is a chain if it is a forced pack and its pack pattern is a chain + inline bool is_chain() const { + return type == e_pack_pattern_molecule_type::MOLECULE_FORCED_PACK && pack_pattern->is_chain; + } +}; + /** * @brief Statistics on a molecule. * @@ -69,7 +161,7 @@ struct t_molecule_stats { * // Initialize device and atom netlist * // ... * Prepacker prepacker; - * prepacker.init(atom_ctx.nlist, device_ctx.logical_block_types); + * prepacker.init(atom_ctx.netlist(), device_ctx.logical_block_types); * // ... * // Use the prepacked molecules. * // ... @@ -78,17 +170,23 @@ struct t_molecule_stats { * */ class Prepacker { -public: - // The constructor is default, the init method performs prepacking. - Prepacker() = default; + public: + // Iterator for the pack molecule IDs + typedef typename vtr::vector_map::const_iterator molecule_iterator; + + // Range for the pack molecule IDs + typedef typename vtr::Range molecule_range; // This class maintains pointers to internal data structures, and as such // should not be copied or moved (prevents unsafe accesses). Prepacker(const Prepacker&) = delete; Prepacker& operator=(const Prepacker&) = delete; + // Destructor of the class. + ~Prepacker(); + /** - * @brief Performs prepacking. + * @brief Construtor. Performs prepacking. * * Initializes the prepacker by performing prepacking and allocating the * necessary data strucutres. @@ -96,19 +194,28 @@ class Prepacker { * @param atom_nlist The atom netlist to prepack. * @param logical_block_types A list of the logical block types on the device. */ - void init(const AtomNetlist& atom_nlist, const std::vector &logical_block_types); + Prepacker(const AtomNetlist& atom_nlist, + const std::vector& logical_block_types); + + /** + * @brief A range of all prepacked molecules. Every atom should exist in one + * of these molecules. + */ + inline molecule_range molecules() const { + return vtr::make_range(pack_molecule_ids_.begin(), pack_molecule_ids_.end()); + } /** * @brief Get the cluster molecule containing the given atom block. * * @param blk_id The atom block to get the molecule of. */ - inline t_pack_molecule* get_atom_molecule(AtomBlockId blk_id) const { + inline PackMoleculeId get_atom_molecule(AtomBlockId blk_id) const { // Safety debug to ensure the blk is valid and has a molecule entry. - VTR_ASSERT_SAFE(blk_id.is_valid() && (size_t)blk_id < atom_molecules.size()); + VTR_ASSERT_SAFE(blk_id.is_valid() && (size_t)blk_id < atom_molecule_.size()); // Safety debug to ensure the molecule is valid - VTR_ASSERT_DEBUG(atom_molecules[blk_id] != nullptr); - return atom_molecules[blk_id]; + VTR_ASSERT_DEBUG(atom_molecule_[blk_id].is_valid()); + return atom_molecule_[blk_id]; } /** @@ -125,34 +232,10 @@ class Prepacker { return expected_lowest_cost_pb_gnode[blk_id]; } - /** - * @brief Returns the total number of molecules in the prepacker. - */ - inline size_t get_num_molecules() const { - size_t num_molecules = 0; - t_pack_molecule* molecule_head = list_of_pack_molecules; - for (auto cur_molecule = molecule_head; cur_molecule != nullptr; cur_molecule = cur_molecule->next) { - ++num_molecules; - } - return num_molecules; - } - - /** - * @brief Returns all of the molecules as a vector. - */ - inline std::vector get_molecules_vector() const { - std::vector molecules; - t_pack_molecule* molecule_head = list_of_pack_molecules; - for (auto cur_molecule = molecule_head; cur_molecule != nullptr; cur_molecule = cur_molecule->next) { - molecules.push_back(cur_molecule); - } - return molecules; - } - /* * @brief Calculates molecule statistics for a single molecule. */ - t_molecule_stats calc_molecule_stats(const t_pack_molecule* molecule, + t_molecule_stats calc_molecule_stats(PackMoleculeId molecule_id, const AtomNetlist& atom_netlist) const; /** @@ -165,37 +248,93 @@ class Prepacker { */ inline size_t get_max_molecule_size() const { size_t max_molecule_size = 1; - t_pack_molecule* molecule_head = list_of_pack_molecules; - for (auto cur_molecule = molecule_head; cur_molecule != nullptr; cur_molecule = cur_molecule->next) { - max_molecule_size = std::max(max_molecule_size, cur_molecule->num_blocks); + for (const t_pack_molecule& molecule : pack_molecules_) { + max_molecule_size = std::max(max_molecule_size, molecule.atom_block_ids.size()); } return max_molecule_size; } /** - * @brief Resets the prepacker object. Clearing all state. - * - * This resets the prepacker, allowing it to prepack again and also freeing - * any state. + * @brief Get information about the molecule associated with the given ID. + */ + inline const t_pack_molecule& get_molecule(PackMoleculeId molecule_id) const { + VTR_ASSERT(molecule_id.is_valid()); + return pack_molecules_[molecule_id]; + } + + /** + * @brief Get the root atom of this molecule. + */ + inline AtomBlockId get_molecule_root_atom(PackMoleculeId molecule_id) const { + VTR_ASSERT_SAFE_MSG(molecule_id.is_valid(), "Invalid molecule ID"); + const t_pack_molecule& mol = get_molecule(molecule_id); + return mol.atom_block_ids[mol.root]; + } + + /** + * @brief Get information about the chain associated with the given ID. + */ + inline const t_chain_info& get_molecule_chain_info(MoleculeChainId chain_id) const { + VTR_ASSERT(chain_id.is_valid()); + return chain_info_[chain_id]; + } + + /** + * @brief Get the number of unique molecule chains from the prepacker. */ - void reset(); + inline size_t get_num_molecule_chains() const { + return chain_info_.size(); + } - /// @brief Destructor of the prepacker class. Calls the reset method. - ~Prepacker() { reset(); } + /** + * @brief Get a list of all the pack patterns in the architecture. + */ + inline const std::vector& get_all_pack_patterns() const { + return list_of_pack_patterns; + } -private: + private: /** - * @brief A linked list of all the packing molecules that are loaded in - * prepacking stage. + * Pre-pack atoms in netlist to molecules + * 1. Single atoms are by definition a molecule. + * 2. Forced pack molecules are groupings of atoms that matches a t_pack_pattern definition. + * 3. Chained molecules are molecules that follow a carry-chain style pattern, + * ie. a single linear chain that can be split across multiple complex blocks + */ + void alloc_and_load_pack_molecules(std::multimap& atom_molecules_multimap, + const AtomNetlist& atom_nlist, + const std::vector& logical_block_types); + + /** + * Given a pattern and an atom block to serve as the root block, determine if + * the candidate atom block serving as the root node matches the pattern. + * If yes, return the molecule with this atom block as the root, if not, return NULL * - * All of the molecules in the prepacker are allocated into this linked list - * and must be freed eventually. + * Limitations: Currently assumes that forced pack nets must be single-fanout as + * this covers all the reasonable architectures we wanted. More complicated + * structures should probably be handled either downstream (general packing) + * or upstream (in tech mapping). + * If this limitation is too constraining, code is designed so that this limitation can be removed * - * TODO: Should use a vtr::vector instead of a linked list for storage. Then - * instead of pointers, IDs can be used to manipulate the molecules - * which would be safer. + * Side Effect: If successful, link atom to molecule + */ + PackMoleculeId try_create_molecule(const int pack_pattern_index, + AtomBlockId blk_id, + std::multimap& atom_molecules_multimap, + const AtomNetlist& atom_nlist); + + private: + /** + * @brief Collection of all molecule IDs. If an entry in this map is invalid + * it means that the molecule should be destroyed. + */ + vtr::vector_map pack_molecule_ids_; + + /** + * @brief Lookup between each molecule ID and the information associated with + * that molecule. */ - t_pack_molecule* list_of_pack_molecules = nullptr; + vtr::vector_map pack_molecules_; /** * @brief The molecules associated with each atom block. @@ -203,7 +342,7 @@ class Prepacker { * This vector is loaded in the init method and cleared in the reset method. * The pointers in this vector are shared with list_of_pack_molecules. */ - vtr::vector atom_molecules; + vtr::vector atom_molecule_; /// @brief A vector of the expected lowest cost physical block graph node. vtr::vector expected_lowest_cost_pb_gnode; @@ -212,6 +351,10 @@ class Prepacker { /// molecules keep pointers to this vector, so this needs to remain /// for the lifetime of the molecules. std::vector list_of_pack_patterns; -}; -#endif + /** + * @brief Lookup between each chain ID and the information associated with + * that chain. + */ + vtr::vector chain_info_; +}; diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.cpp b/vpr/src/pack/sync_netlists_to_routing_flat.cpp index 8aa54bb7f1a..0e6be438300 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.cpp +++ b/vpr/src/pack/sync_netlists_to_routing_flat.cpp @@ -1,23 +1,19 @@ /** -* @file sync_netlists_to_routing_flat.cpp -* -* @brief Implementation for \see sync_netlists_to_routing_flat(). -*/ + * @file sync_netlists_to_routing_flat.cpp + * + * @brief Implementation for \see sync_netlists_to_routing_flat(). + */ #include "clustered_netlist_fwd.h" -#include "clustered_netlist_utils.h" #include "logic_types.h" #include "netlist_fwd.h" #include "physical_types.h" +#include "physical_types_util.h" #include "vtr_time.h" #include "vtr_assert.h" -#include "vtr_log.h" -#include "annotate_routing.h" #include "globals.h" -#include "vpr_error.h" #include "vpr_utils.h" -#include "rr_graph2.h" #include "sync_netlists_to_routing_flat.h" @@ -44,20 +40,19 @@ static void sync_clustered_netlist_to_routing(void); * (i.e. the primitive has equivalent input pins and flat routing used a different pin) */ static void fixup_atom_pb_graph_pin_mapping(void); - /* Function definitions */ /** Is the clock net found in the routing results? * (If not, clock_modeling is probably ideal and we should preserve clock routing while rebuilding.) */ -inline bool is_clock_net_routed(void){ +inline bool is_clock_net_routed(void) { auto& atom_ctx = g_vpr_ctx.atom(); auto& route_ctx = g_vpr_ctx.routing(); - for(auto net_id: atom_ctx.nlist.nets()){ + for (auto net_id : atom_ctx.netlist().nets()) { auto& tree = route_ctx.route_trees[net_id]; - if(!tree) + if (!tree) continue; - if(route_ctx.is_clock_net[net_id]) /* Clock net has routing */ + if (route_ctx.is_clock_net[net_id]) /* Clock net has routing */ return true; } @@ -65,7 +60,7 @@ inline bool is_clock_net_routed(void){ } /** Get the ClusterBlockId for a given RRNodeId. */ -inline ClusterBlockId get_cluster_block_from_rr_node(RRNodeId inode){ +inline ClusterBlockId get_cluster_block_from_rr_node(RRNodeId inode) { auto& device_ctx = g_vpr_ctx.device(); auto& place_ctx = g_vpr_ctx.placement(); auto& rr_graph = device_ctx.rr_graph; @@ -85,38 +80,36 @@ inline ClusterBlockId get_cluster_block_from_rr_node(RRNodeId inode){ int width_offset = device_ctx.grid.get_width_offset(node_phy_tile_loc); int height_offset = device_ctx.grid.get_height_offset(node_phy_tile_loc); - ClusterBlockId clb = place_ctx.grid_blocks().block_at_location({ - rr_graph.node_xlow(inode) - width_offset, - rr_graph.node_ylow(inode) - height_offset, - subtile, - rr_graph.node_layer(inode) - }); + ClusterBlockId clb = place_ctx.grid_blocks().block_at_location({rr_graph.node_xlow(inode) - width_offset, + rr_graph.node_ylow(inode) - height_offset, + subtile, + rr_graph.node_layer(inode)}); return clb; } -static void get_intra_cluster_connections(const RouteTree& tree, std::vector>& out_connections){ +static void get_intra_cluster_connections(const RouteTree& tree, std::vector>& out_connections) { auto& rr_graph = g_vpr_ctx.device().rr_graph; - for(auto& node: tree.all_nodes()){ + for (auto& node : tree.all_nodes()) { const auto& parent = node.parent(); - if(!parent) /* Root */ + if (!parent) /* Root */ continue; /* Find the case where both nodes are IPIN/OPINs and on the same block */ auto type = rr_graph.node_type(node.inode); auto parent_type = rr_graph.node_type(parent->inode); - if((type == IPIN || type == OPIN) && (parent_type == IPIN || parent_type == OPIN)){ + if ((type == IPIN || type == OPIN) && (parent_type == IPIN || parent_type == OPIN)) { auto clb = get_cluster_block_from_rr_node(node.inode); auto parent_clb = get_cluster_block_from_rr_node(parent->inode); - if(clb == parent_clb) + if (clb == parent_clb) out_connections.push_back({parent->inode, node.inode}); } } } -static void route_intra_cluster_conn(const t_pb_graph_pin* source_pin, const t_pb_graph_pin* sink_pin, AtomNetId net_id, t_pb* out_pb){ +static void route_intra_cluster_conn(const t_pb_graph_pin* source_pin, const t_pb_graph_pin* sink_pin, AtomNetId net_id, t_pb* out_pb) { std::unordered_set visited; std::deque queue; std::unordered_map prev; @@ -126,31 +119,31 @@ static void route_intra_cluster_conn(const t_pb_graph_pin* source_pin, const t_p queue.push_back(source_pin); prev[source_pin] = NULL; - while(!queue.empty()){ + while (!queue.empty()) { const t_pb_graph_pin* cur_pin = queue.front(); queue.pop_front(); - if(visited.count(cur_pin)) + if (visited.count(cur_pin)) continue; visited.insert(cur_pin); /* Backtrack and return */ - if(cur_pin == sink_pin){ + if (cur_pin == sink_pin) { break; } - for(auto& edge: cur_pin->output_edges){ + for (auto& edge : cur_pin->output_edges) { VTR_ASSERT(edge->num_output_pins == 1); queue.push_back(edge->output_pins[0]); prev[edge->output_pins[0]] = cur_pin; } } - + VTR_ASSERT_MSG(visited.count(sink_pin), "Couldn't find sink pin"); /* Collect path: we need to build pb_routes from source to sink */ std::vector path; const t_pb_graph_pin* cur_pin = sink_pin; - while(cur_pin != source_pin){ + while (cur_pin != source_pin) { path.push_back(cur_pin); cur_pin = prev[cur_pin]; } @@ -158,25 +151,24 @@ static void route_intra_cluster_conn(const t_pb_graph_pin* source_pin, const t_p /* Output the path into out_pb, starting from source. This is where the pb_route is updated */ int prev_pin_id = -1; - for(auto it = path.rbegin(); it != path.rend(); ++it){ + for (auto it = path.rbegin(); it != path.rend(); ++it) { cur_pin = *it; int cur_pin_id = cur_pin->pin_count_in_cluster; t_pb_route* cur_pb_route; - if(out_pb_routes.count(cur_pin_id)) + if (out_pb_routes.count(cur_pin_id)) cur_pb_route = &out_pb_routes[cur_pin_id]; else { t_pb_route pb_route = { net_id, -1, {}, - cur_pin - }; + cur_pin}; out_pb_routes.insert(std::make_pair<>(cur_pin_id, pb_route)); cur_pb_route = &out_pb_routes[cur_pin_id]; } - if(prev_pin_id != -1){ + if (prev_pin_id != -1) { t_pb_route& prev_pb_route = out_pb_routes[prev_pin_id]; prev_pb_route.sink_pb_pin_ids.push_back(cur_pin_id); cur_pb_route->driver_pb_pin_id = prev_pb_route.pb_graph_pin->pin_count_in_cluster; @@ -186,7 +178,7 @@ static void route_intra_cluster_conn(const t_pb_graph_pin* source_pin, const t_p } } -static void sync_pb_routes_to_routing(void){ +static void sync_pb_routes_to_routing(void) { auto& device_ctx = g_vpr_ctx.device(); auto& atom_ctx = g_vpr_ctx.atom(); auto& cluster_ctx = g_vpr_ctx.mutable_clustering(); @@ -202,20 +194,20 @@ static void sync_pb_routes_to_routing(void){ * Otherwise we won't have data to rebuild them */ std::vector pins_to_erase; auto& pb_routes = cluster_ctx.clb_nlist.block_pb(clb_blk_id)->pb_route; - for(auto& [pin, pb_route]: pb_routes){ - if(clock_net_is_routed || !route_ctx.is_clock_net[pb_route.atom_net_id]) + for (auto& [pin, pb_route] : pb_routes) { + if (clock_net_is_routed || !route_ctx.is_clock_net[pb_route.atom_net_id]) pins_to_erase.push_back(pin); } - for(int pin: pins_to_erase){ + for (int pin : pins_to_erase) { pb_routes.erase(pin); } } /* Go through each route tree and rebuild the pb_routes */ - for(ParentNetId net_id: atom_ctx.nlist.nets()){ + for (ParentNetId net_id : atom_ctx.netlist().nets()) { auto& tree = route_ctx.route_trees[net_id]; - if(!tree) + if (!tree) continue; /* No routing at this ParentNetId */ /* Get all intrablock connections */ @@ -223,26 +215,24 @@ static void sync_pb_routes_to_routing(void){ get_intra_cluster_connections(tree.value(), conns_to_restore); /* Restore the connections */ - for(auto [source_inode, sink_inode]: conns_to_restore){ + for (auto [source_inode, sink_inode] : conns_to_restore) { ClusterBlockId clb = get_cluster_block_from_rr_node(source_inode); - auto physical_tile = device_ctx.grid.get_physical_type({ - rr_graph.node_xlow(source_inode), - rr_graph.node_ylow(source_inode), - rr_graph.node_layer(source_inode) - }); + auto physical_tile = device_ctx.grid.get_physical_type({rr_graph.node_xlow(source_inode), + rr_graph.node_ylow(source_inode), + rr_graph.node_layer(source_inode)}); int source_pin = rr_graph.node_pin_num(source_inode); int sink_pin = rr_graph.node_pin_num(sink_inode); /* Look up pb graph pins from pb type if pin is not on tile, look up from block otherwise */ - const t_pb_graph_pin* source_pb_graph_pin, *sink_pb_graph_pin; - if(is_pin_on_tile(physical_tile, sink_pin)){ + const t_pb_graph_pin *source_pb_graph_pin, *sink_pb_graph_pin; + if (is_pin_on_tile(physical_tile, sink_pin)) { sink_pb_graph_pin = get_pb_graph_node_pin_from_block_pin(clb, sink_pin); - }else{ + } else { sink_pb_graph_pin = get_pb_pin_from_pin_physical_num(physical_tile, sink_pin); } - if(is_pin_on_tile(physical_tile, source_pin)){ + if (is_pin_on_tile(physical_tile, source_pin)) { source_pb_graph_pin = get_pb_graph_node_pin_from_block_pin(clb, source_pin); - }else{ + } else { source_pb_graph_pin = get_pb_pin_from_pin_physical_num(physical_tile, source_pin); } @@ -255,20 +245,20 @@ static void sync_pb_routes_to_routing(void){ } /** Rebuild the ClusterNetId <-> AtomNetId lookup after compressing the ClusterNetlist. - * Needs the old ClusterNetIds in atom_ctx.lookup. Won't work after calling compress() twice, + * Needs the old ClusterNetIds in atom_ctx.lookup(). Won't work after calling compress() twice, * since we won't have access to the old IDs in the IdRemapper anywhere. */ -inline void rebuild_atom_nets_lookup(ClusteredNetlist::IdRemapper& remapped){ +inline void rebuild_atom_nets_lookup(ClusteredNetlist::IdRemapper& remapped) { auto& atom_ctx = g_vpr_ctx.mutable_atom(); - auto& atom_lookup = atom_ctx.lookup; + auto& atom_lookup = atom_ctx.mutable_lookup(); - for(auto parent_net_id: atom_ctx.nlist.nets()){ + for (auto parent_net_id : atom_ctx.netlist().nets()) { auto atom_net_id = convert_to_atom_net_id(parent_net_id); auto old_clb_nets_opt = atom_lookup.clb_nets(atom_net_id); - if(!old_clb_nets_opt) + if (!old_clb_nets_opt) continue; std::vector old_clb_nets = old_clb_nets_opt.value(); atom_lookup.remove_atom_net(atom_net_id); - for(auto old_clb_net: old_clb_nets){ + for (auto old_clb_net : old_clb_nets) { ClusterNetId new_clb_net = remapped.new_net_id(old_clb_net); atom_lookup.add_atom_clb_net(atom_net_id, new_clb_net); } @@ -276,7 +266,7 @@ inline void rebuild_atom_nets_lookup(ClusteredNetlist::IdRemapper& remapped){ } /** Regenerate clustered netlist nets from routing results */ -static void sync_clustered_netlist_to_routing(void){ +static void sync_clustered_netlist_to_routing(void) { auto& cluster_ctx = g_vpr_ctx.mutable_clustering(); auto& place_ctx = g_vpr_ctx.mutable_placement(); auto& route_ctx = g_vpr_ctx.routing(); @@ -284,7 +274,7 @@ static void sync_clustered_netlist_to_routing(void){ auto& device_ctx = g_vpr_ctx.device(); auto& rr_graph = device_ctx.rr_graph; auto& atom_ctx = g_vpr_ctx.mutable_atom(); - auto& atom_lookup = atom_ctx.lookup; + auto& atom_lookup = atom_ctx.lookup(); bool clock_net_is_routed = is_clock_net_routed(); @@ -295,25 +285,25 @@ static void sync_clustered_netlist_to_routing(void){ std::vector pins_to_remove; std::vector ports_to_remove; - for(auto net_id: clb_netlist.nets()){ + for (auto net_id : clb_netlist.nets()) { auto atom_net_id = atom_lookup.atom_net(net_id); - if(!clock_net_is_routed && route_ctx.is_clock_net[atom_net_id]) + if (!clock_net_is_routed && route_ctx.is_clock_net[atom_net_id]) continue; nets_to_remove.push_back(net_id); } - for(auto pin_id: clb_netlist.pins()){ + for (auto pin_id : clb_netlist.pins()) { ClusterNetId clb_net_id = clb_netlist.pin_net(pin_id); auto atom_net_id = atom_lookup.atom_net(clb_net_id); - if(!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) + if (!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) continue; pins_to_remove.push_back(pin_id); } - for(auto port_id: clb_netlist.ports()){ + for (auto port_id : clb_netlist.ports()) { ClusterNetId clb_net_id = clb_netlist.port_net(port_id, 0); auto atom_net_id = atom_lookup.atom_net(clb_net_id); - if(!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) + if (!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) continue; ports_to_remove.push_back(port_id); @@ -321,14 +311,14 @@ static void sync_clustered_netlist_to_routing(void){ /* ClusteredNetlist's iterators rely on internal lookups, so we mark for removal * while iterating, then remove in bulk */ - for(auto net_id: nets_to_remove){ + for (auto net_id : nets_to_remove) { clb_netlist.remove_net(net_id); - atom_lookup.remove_clb_net(net_id); + atom_ctx.mutable_lookup().remove_clb_net(net_id); } - for(auto pin_id: pins_to_remove){ + for (auto pin_id : pins_to_remove) { clb_netlist.remove_pin(pin_id); } - for(auto port_id: ports_to_remove){ + for (auto port_id : ports_to_remove) { clb_netlist.remove_port(port_id); } @@ -338,51 +328,49 @@ static void sync_clustered_netlist_to_routing(void){ /* 3. Walk each routing in the atom netlist. If a node is on the tile, add a ClusterPinId for it. * Add the associated net and port too if they don't exist */ - for(auto parent_net_id: atom_ctx.nlist.nets()){ + for (auto parent_net_id : atom_ctx.netlist().nets()) { auto& tree = route_ctx.route_trees[parent_net_id]; AtomNetId atom_net_id = convert_to_atom_net_id(parent_net_id); ClusterNetId clb_net_id; int clb_nets_so_far = 0; - for(auto& rt_node: tree->all_nodes()){ + for (auto& rt_node : tree->all_nodes()) { auto node_type = rr_graph.node_type(rt_node.inode); - if(node_type != IPIN && node_type != OPIN) + if (node_type != IPIN && node_type != OPIN) continue; - auto physical_tile = device_ctx.grid.get_physical_type({ - rr_graph.node_xlow(rt_node.inode), - rr_graph.node_ylow(rt_node.inode), - rr_graph.node_layer(rt_node.inode) - }); + auto physical_tile = device_ctx.grid.get_physical_type({rr_graph.node_xlow(rt_node.inode), + rr_graph.node_ylow(rt_node.inode), + rr_graph.node_layer(rt_node.inode)}); int pin_index = rr_graph.node_pin_num(rt_node.inode); ClusterBlockId clb = get_cluster_block_from_rr_node(rt_node.inode); - if(!is_pin_on_tile(physical_tile, pin_index)) + if (!is_pin_on_tile(physical_tile, pin_index)) continue; /* OPIN on the tile: create a new clb_net_id and add all ports & pins into here * Due to how the route tree is traversed, all nodes until the next OPIN on the tile will * be under this OPIN, so this is valid (we don't need to get the branch explicitly) */ - if(node_type == OPIN){ + if (node_type == OPIN) { std::string net_name; - net_name = atom_ctx.nlist.net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far); + net_name = atom_ctx.netlist().net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far); clb_net_id = clb_netlist.create_net(net_name); - atom_lookup.add_atom_clb_net(atom_net_id, clb_net_id); + atom_ctx.mutable_lookup().add_atom_clb_net(atom_net_id, clb_net_id); clb_nets_so_far++; } t_pb_graph_pin* pb_graph_pin = get_pb_graph_node_pin_from_block_pin(clb, pin_index); ClusterPortId port_id = clb_netlist.find_port(clb, pb_graph_pin->port->name); - if(!port_id){ + if (!port_id) { PortType port_type; - if(pb_graph_pin->port->is_clock) + if (pb_graph_pin->port->is_clock) port_type = PortType::CLOCK; - else if(pb_graph_pin->port->type == IN_PORT) + else if (pb_graph_pin->port->type == IN_PORT) port_type = PortType::INPUT; - else if(pb_graph_pin->port->type == OUT_PORT) + else if (pb_graph_pin->port->type == OUT_PORT) port_type = PortType::OUTPUT; else VTR_ASSERT_MSG(false, "Unsupported port type"); @@ -402,40 +390,40 @@ static void sync_clustered_netlist_to_routing(void){ auto& blk_loc_registry = place_ctx.mutable_blk_loc_registry(); auto& physical_pins = place_ctx.mutable_physical_pins(); physical_pins.clear(); - for(auto clb: clb_netlist.blocks()){ + for (auto clb : clb_netlist.blocks()) { blk_loc_registry.place_sync_external_block_connections(clb); } } -static void fixup_atom_pb_graph_pin_mapping(void){ +static void fixup_atom_pb_graph_pin_mapping(void) { auto& cluster_ctx = g_vpr_ctx.clustering(); auto& atom_ctx = g_vpr_ctx.mutable_atom(); - for(ClusterBlockId clb: cluster_ctx.clb_nlist.blocks()){ + for (ClusterBlockId clb : cluster_ctx.clb_nlist.blocks()) { /* Collect all innermost pb routes */ std::vector sink_pb_route_ids; t_pb* clb_pb = cluster_ctx.clb_nlist.block_pb(clb); - for(auto [pb_route_id, pb_route]: clb_pb->pb_route){ - if(pb_route.sink_pb_pin_ids.empty()) + for (auto [pb_route_id, pb_route] : clb_pb->pb_route) { + if (pb_route.sink_pb_pin_ids.empty()) sink_pb_route_ids.push_back(pb_route_id); } - for(int sink_pb_route_id: sink_pb_route_ids){ + for (int sink_pb_route_id : sink_pb_route_ids) { t_pb_route& pb_route = clb_pb->pb_route.at(sink_pb_route_id); const t_pb_graph_pin* atom_pbg_pin = pb_route.pb_graph_pin; t_pb* atom_pb = clb_pb->find_mutable_pb(atom_pbg_pin->parent_node); - AtomBlockId atb = atom_ctx.lookup.pb_atom(atom_pb); - if(!atb) + AtomBlockId atb = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom_pb); + if (!atb) continue; /* Find atom port from pbg pin's model port */ - AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atb, atom_pbg_pin->port->model_port); - for(AtomPinId atom_pin: atom_ctx.nlist.port_pins(atom_port)){ + AtomPortId atom_port = atom_ctx.netlist().find_atom_port(atb, atom_pbg_pin->port->model_port); + for (AtomPinId atom_pin : atom_ctx.netlist().port_pins(atom_port)) { /* Match net IDs from pb_route and atom netlist and connect in lookup */ - if(pb_route.atom_net_id == atom_ctx.nlist.pin_net(atom_pin)){ - atom_ctx.lookup.set_atom_pin_pb_graph_pin(atom_pin, atom_pbg_pin); - atom_pb->set_atom_pin_bit_index(atom_pbg_pin, atom_ctx.nlist.pin_port_bit(atom_pin)); + if (pb_route.atom_net_id == atom_ctx.netlist().pin_net(atom_pin)) { + atom_ctx.mutable_lookup().set_atom_pin_pb_graph_pin(atom_pin, atom_pbg_pin); + atom_pb->set_atom_pin_bit_index(atom_pbg_pin, atom_ctx.netlist().pin_port_bit(atom_pin)); } } } diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.h b/vpr/src/pack/sync_netlists_to_routing_flat.h index 9403eb1c2a9..0c1bc7d77d3 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.h +++ b/vpr/src/pack/sync_netlists_to_routing_flat.h @@ -1,6 +1,6 @@ #include "netlist.h" - /******************************************************************** +/******************************************************************** * Top-level function to synchronize packing results to routing results. * Flat routing invalidates the ClusteredNetlist since nets may be routed * inside or outside a block and changes virtually all intrablock routing. diff --git a/vpr/src/pack/verify_clustering.cpp b/vpr/src/pack/verify_clustering.cpp index a833ce473d6..ec08e10a40b 100644 --- a/vpr/src/pack/verify_clustering.cpp +++ b/vpr/src/pack/verify_clustering.cpp @@ -107,7 +107,7 @@ static bool is_atom_pb_in_cluster_pb(AtomBlockId atom_blk_id, const AtomLookup& atom_lookup, const ClusteredNetlist& clb_nlist) { // Get the pbs - const t_pb* atom_pb = atom_lookup.atom_pb(atom_blk_id); + const t_pb* atom_pb = atom_lookup.atom_pb_bimap().atom_pb(atom_blk_id); const t_pb* cluster_pb = clb_nlist.block_pb(clb_blk_id); // For the atom pb to be a part of the cluster pb, the atom pb must be a // descendent of the cluster pb (the cluster pb is the ancestor to all atom @@ -179,7 +179,7 @@ static unsigned check_clustering_pb_consistency(const ClusteredNetlist& clb_nlis ClusterBlockId atom_clb_blk_id = atom_lookup.atom_clb(atom_blk_id); if (!atom_clb_blk_id.is_valid()) continue; - const t_pb* atom_pb = atom_lookup.atom_pb(atom_blk_id); + const t_pb* atom_pb = atom_lookup.atom_pb_bimap().atom_pb(atom_blk_id); // Make sure the atom's pb exists if (atom_pb == nullptr) { VTR_LOG_ERROR( @@ -188,7 +188,7 @@ static unsigned check_clustering_pb_consistency(const ClusteredNetlist& clb_nlis num_errors++; } else { // Sanity check: atom_pb == pb_atom - if (atom_lookup.pb_atom(atom_pb) != atom_blk_id) { + if (atom_lookup.atom_pb_bimap().pb_atom(atom_pb) != atom_blk_id) { VTR_LOG_ERROR( "Atom block %zu in cluster block %zu has a pb which " "belongs to another atom.\n", @@ -243,10 +243,10 @@ static unsigned check_clustering_pb_consistency(const ClusteredNetlist& clb_nlis * @return The number of errors in the clustering floorplanning. */ static unsigned check_clustering_floorplanning_consistency( - const ClusteredNetlist& clb_nlist, - const vtr::vector>& clb_atoms, - const vtr::vector& cluster_constraints, - const UserPlaceConstraints& constraints) { + const ClusteredNetlist& clb_nlist, + const vtr::vector>& clb_atoms, + const vtr::vector& cluster_constraints, + const UserPlaceConstraints& constraints) { unsigned num_errors = 0; // Check that each cluster has a constraint. if (cluster_constraints.size() != clb_nlist.blocks().size()) { @@ -435,10 +435,9 @@ unsigned verify_clustering(const ClusteredNetlist& clb_nlist, unsigned verify_clustering(const VprContext& ctx) { // Verify the clustering within the given context. return verify_clustering(ctx.clustering().clb_nlist, - ctx.atom().nlist, - ctx.atom().lookup, + ctx.atom().netlist(), + ctx.atom().lookup(), ctx.clustering().atoms_lookup, ctx.floorplanning().cluster_constraints, ctx.floorplanning().constraints); } - diff --git a/vpr/src/pack/verify_clustering.h b/vpr/src/pack/verify_clustering.h index f9ae0d95ed2..f13de9a6d48 100644 --- a/vpr/src/pack/verify_clustering.h +++ b/vpr/src/pack/verify_clustering.h @@ -82,4 +82,3 @@ unsigned verify_clustering(const ClusteredNetlist& clb_nlist, * log messages for each error found. */ unsigned verify_clustering(const VprContext& ctx); - diff --git a/vpr/src/pack/verify_flat_placement.cpp b/vpr/src/pack/verify_flat_placement.cpp new file mode 100644 index 00000000000..76a893d66a6 --- /dev/null +++ b/vpr/src/pack/verify_flat_placement.cpp @@ -0,0 +1,100 @@ + +#include "verify_flat_placement.h" +#include "flat_placement_types.h" +#include "atom_netlist.h" +#include "atom_netlist_fwd.h" +#include "prepack.h" +#include "vpr_types.h" +#include "vtr_log.h" + +unsigned verify_flat_placement_for_packing(const FlatPlacementInfo& flat_placement_info, + const AtomNetlist& atom_netlist, + const Prepacker& prepacker) { + unsigned num_errors = 0; + + // Quick check to ensure that the flat placement info has the correct size + // for each piece of information. + if (flat_placement_info.blk_x_pos.size() != atom_netlist.blocks().size() + || flat_placement_info.blk_y_pos.size() != atom_netlist.blocks().size() + || flat_placement_info.blk_layer.size() != atom_netlist.blocks().size() + || flat_placement_info.blk_sub_tile.size() != atom_netlist.blocks().size() + || flat_placement_info.blk_site_idx.size() != atom_netlist.blocks().size()) { + VTR_LOG_ERROR( + "The number of blocks in the flat placement does not match the " + "number of blocks in the atom netlist.\n"); + num_errors++; + // Return here since this error can cause issues below. + return num_errors; + } + + // 1. Verify that every atom has an (x, y, layer) position on the device. + // + // TODO: In the future, we may be able to allow some blocks to have + // undefined positions. + for (AtomBlockId blk_id : atom_netlist.blocks()) { + if (flat_placement_info.blk_x_pos[blk_id] == FlatPlacementInfo::UNDEFINED_POS + || flat_placement_info.blk_y_pos[blk_id] == FlatPlacementInfo::UNDEFINED_POS + || flat_placement_info.blk_layer[blk_id] == FlatPlacementInfo::UNDEFINED_POS) { + VTR_LOG_ERROR( + "Atom block %s has an undefined position in the flat placement.\n", + atom_netlist.block_name(blk_id).c_str()); + num_errors++; + } + } + + // 2. Verify that every atom block has non-negative position values. + // + // Since the device may not be sized yet, we cannot check if the positions + // are within the bounds of the device, but if any position value is + // negative (and is not undefined) we know that it is invalid. + for (AtomBlockId blk_id : atom_netlist.blocks()) { + float blk_x_pos = flat_placement_info.blk_x_pos[blk_id]; + float blk_y_pos = flat_placement_info.blk_y_pos[blk_id]; + float blk_layer = flat_placement_info.blk_layer[blk_id]; + int blk_sub_tile = flat_placement_info.blk_sub_tile[blk_id]; + int blk_site_idx = flat_placement_info.blk_site_idx[blk_id]; + if ((blk_x_pos < 0.f && blk_x_pos != FlatPlacementInfo::UNDEFINED_POS) + || (blk_y_pos < 0.f && blk_y_pos != FlatPlacementInfo::UNDEFINED_POS) + || (blk_layer < 0.f && blk_layer != FlatPlacementInfo::UNDEFINED_POS) + || (blk_sub_tile < 0 && blk_sub_tile != FlatPlacementInfo::UNDEFINED_SUB_TILE) + || (blk_site_idx < 0 && blk_site_idx != FlatPlacementInfo::UNDEFINED_SITE_IDX)) { + VTR_LOG_ERROR( + "Atom block %s is placed at an invalid position on the FPGA.\n", + atom_netlist.block_name(blk_id).c_str()); + num_errors++; + } + } + + // 3. Verify that every atom in each molecule has the same position. + // + // TODO: In the future, we can support if some of the atoms are undefined, + // but that can be fixed-up before calling this method. + for (PackMoleculeId mol_id : prepacker.molecules()) { + const t_pack_molecule& mol = prepacker.get_molecule(mol_id); + AtomBlockId root_blk_id = mol.atom_block_ids[mol.root]; + float root_pos_x = flat_placement_info.blk_x_pos[root_blk_id]; + float root_pos_y = flat_placement_info.blk_y_pos[root_blk_id]; + float root_layer = flat_placement_info.blk_layer[root_blk_id]; + int root_sub_tile = flat_placement_info.blk_sub_tile[root_blk_id]; + for (AtomBlockId mol_blk_id : mol.atom_block_ids) { + if (!mol_blk_id.is_valid()) + continue; + if (flat_placement_info.blk_x_pos[mol_blk_id] != root_pos_x || flat_placement_info.blk_y_pos[mol_blk_id] != root_pos_y || flat_placement_info.blk_layer[mol_blk_id] != root_layer || flat_placement_info.blk_sub_tile[mol_blk_id] != root_sub_tile) { + VTR_LOG_ERROR( + "Molecule with root atom block %s contains atom block %s " + "which is not at the same position as the root atom " + "block.\n", + atom_netlist.block_name(root_blk_id).c_str(), + atom_netlist.block_name(mol_blk_id).c_str()); + num_errors++; + } + } + } + + // TODO: May want to verify that the layer is all 0 in the case of 2D FPGAs. + + // TODO: Should verify that the fixed block constraints are observed. + // It is ill-formed for a flat placement to disagree with the constraints. + + return num_errors; +} diff --git a/vpr/src/pack/verify_flat_placement.h b/vpr/src/pack/verify_flat_placement.h new file mode 100644 index 00000000000..44bfb47f3fd --- /dev/null +++ b/vpr/src/pack/verify_flat_placement.h @@ -0,0 +1,37 @@ +/** + * @file + * @author Alex Singer + * @date January 2025 + * @brief Independent verify methods to check invariants on the flat + * placement that has been passed into the packer. This checks for + * invalid data so this does not have to be checked during packing. + */ + +#pragma once + +// Forward declarations +class FlatPlacementInfo; +class AtomNetlist; +class Prepacker; + +/** + * @brief Verify the flat placement for use in the packer. + * + * This method will check the following invariants: + * 1. Every atom has a defined x and y position. + * 2. Every atom has non-negative placement information values. + * 3. Every molecule has atoms that have the same placement information. + * + * This method will log error messages for each issue it finds and will return + * a count of the number of errors. + * + * @param flat_placement_info + * The flat placement to verify. + * @param atom_netlist + * The netlist of atoms in the circuits. + * @param prepacker + * The prepacker object used to prepack the atoms into molecules. + */ +unsigned verify_flat_placement_for_packing(const FlatPlacementInfo& flat_placement_info, + const AtomNetlist& atom_netlist, + const Prepacker& prepacker); diff --git a/vpr/src/place/RL_agent_util.cpp b/vpr/src/place/RL_agent_util.cpp index b33e05f077a..54ca3601545 100644 --- a/vpr/src/place/RL_agent_util.cpp +++ b/vpr/src/place/RL_agent_util.cpp @@ -1,8 +1,13 @@ #include "RL_agent_util.h" + +#include "place_macro.h" +#include "simpleRL_move_generator.h" #include "static_move_generator.h" -#include "manual_move_generator.h" +#include "placer_state.h" std::pair, std::unique_ptr> create_move_generators(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, const t_placer_opts& placer_opts, int move_lim, double noc_attraction_weight, @@ -10,7 +15,6 @@ std::pair, std::unique_ptr> create e_reward_function reward_fun = string_to_reward(placer_opts.place_reward_fun); std::pair, std::unique_ptr> move_generators; - if (!placer_opts.RL_agent_placement) { // RL agent is disabled auto move_types = placer_opts.place_static_move_prob; move_types.resize((int)e_move_type::NUMBER_OF_AUTO_MOVES, 0.0f); @@ -22,8 +26,8 @@ std::pair, std::unique_ptr> create move_name.c_str(), placer_opts.place_static_move_prob[move_type]); } - move_generators.first = std::make_unique(placer_state, reward_fun, rng, placer_opts.place_static_move_prob); - move_generators.second = std::make_unique(placer_state, reward_fun, rng, placer_opts.place_static_move_prob); + move_generators.first = std::make_unique(placer_state, place_macros, net_cost_handler, reward_fun, rng, placer_opts.place_static_move_prob); + move_generators.second = std::make_unique(placer_state, place_macros, net_cost_handler, reward_fun, rng, placer_opts.place_static_move_prob); } else { //RL based placement /* For the non timing driven placement: the agent has a single state * * - Available moves are (Uniform / Median / Centroid) * @@ -60,6 +64,13 @@ std::pair, std::unique_ptr> create second_state_avail_moves.push_back(e_move_type::NOC_ATTRACTION_CENTROID); } + std::vector num_movable_blocks_per_type; + std::ranges::transform(placer_state.blk_loc_registry().movable_blocks_per_type(), + std::back_inserter(num_movable_blocks_per_type), + [](const auto& innerVec) noexcept { + return innerVec.size(); + }); + if (placer_opts.place_agent_algorithm == e_agent_algorithm::E_GREEDY) { std::unique_ptr karmed_bandit_agent1, karmed_bandit_agent2; //agent's 1st state @@ -68,16 +79,20 @@ std::pair, std::unique_ptr> create karmed_bandit_agent1 = std::make_unique(first_state_avail_moves, e_agent_space::MOVE_BLOCK_TYPE, placer_opts.place_agent_epsilon, - rng); + rng, + num_movable_blocks_per_type); } else { VTR_LOG("Using simple RL 'Epsilon Greedy agent' for choosing move types\n"); karmed_bandit_agent1 = std::make_unique(first_state_avail_moves, e_agent_space::MOVE_TYPE, placer_opts.place_agent_epsilon, - rng); + rng, + num_movable_blocks_per_type); } karmed_bandit_agent1->set_step(placer_opts.place_agent_gamma, move_lim); move_generators.first = std::make_unique(placer_state, + place_macros, + net_cost_handler, reward_fun, rng, karmed_bandit_agent1, @@ -87,9 +102,12 @@ std::pair, std::unique_ptr> create karmed_bandit_agent2 = std::make_unique(second_state_avail_moves, e_agent_space::MOVE_TYPE, placer_opts.place_agent_epsilon, - rng); + rng, + num_movable_blocks_per_type); karmed_bandit_agent2->set_step(placer_opts.place_agent_gamma, move_lim); move_generators.second = std::make_unique(placer_state, + place_macros, + net_cost_handler, reward_fun, rng, karmed_bandit_agent2, @@ -102,15 +120,19 @@ std::pair, std::unique_ptr> create VTR_LOG("Using simple RL 'Softmax agent' for choosing move and block types\n"); karmed_bandit_agent1 = std::make_unique(first_state_avail_moves, e_agent_space::MOVE_BLOCK_TYPE, - rng); + rng, + num_movable_blocks_per_type); } else { VTR_LOG("Using simple RL 'Softmax agent' for choosing move types\n"); karmed_bandit_agent1 = std::make_unique(first_state_avail_moves, e_agent_space::MOVE_TYPE, - rng); + rng, + num_movable_blocks_per_type); } karmed_bandit_agent1->set_step(placer_opts.place_agent_gamma, move_lim); move_generators.first = std::make_unique(placer_state, + place_macros, + net_cost_handler, reward_fun, rng, karmed_bandit_agent1, @@ -119,9 +141,12 @@ std::pair, std::unique_ptr> create //agent's 2nd state karmed_bandit_agent2 = std::make_unique(second_state_avail_moves, e_agent_space::MOVE_TYPE, - rng); + rng, + num_movable_blocks_per_type); karmed_bandit_agent2->set_step(placer_opts.place_agent_gamma, move_lim); move_generators.second = std::make_unique(placer_state, + place_macros, + net_cost_handler, reward_fun, rng, karmed_bandit_agent2, @@ -149,4 +174,4 @@ MoveGenerator& select_move_generator(std::unique_ptr& move_genera else return *move_generator2; } -} \ No newline at end of file +} diff --git a/vpr/src/place/RL_agent_util.h b/vpr/src/place/RL_agent_util.h index 0ec801e8000..511cd73d0d6 100644 --- a/vpr/src/place/RL_agent_util.h +++ b/vpr/src/place/RL_agent_util.h @@ -3,6 +3,8 @@ #include "move_generator.h" +class PlaceMacros; + //enum represents the available agent states enum class e_agent_state { EARLY_IN_THE_ANNEAL, @@ -27,6 +29,8 @@ enum class e_agent_state { * */ std::pair, std::unique_ptr> create_move_generators(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, const t_placer_opts& placer_opts, int move_lim, double noc_attraction_weight, diff --git a/vpr/src/place/analytic_placer.cpp b/vpr/src/place/analytic_placer.cpp index b4ac4400f0f..a0897af6785 100644 --- a/vpr/src/place/analytic_placer.cpp +++ b/vpr/src/place/analytic_placer.cpp @@ -1,29 +1,30 @@ +#include "place_macro.h" #ifdef ENABLE_ANALYTIC_PLACE -# include "analytic_placer.h" +#include "analytic_placer.h" // The eigen library contains a warning in GCC13 for a null dereference. This // causes the CI build to fail due to the warning. Ignoring the warning for // these include files. Using push to return to the state of GCC diagnostics. #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wnull-dereference" -# include -# include +#include +#include // Pop the GCC diagnostics state back to what it was before. #pragma GCC diagnostic pop -# include -# include -# include +#include +#include +#include -# include "vpr_types.h" -# include "vtr_time.h" -# include "read_place.h" -# include "globals.h" -# include "vtr_log.h" -# include "cut_spreader.h" -# include "vpr_utils.h" -# include "place_util.h" +#include "vpr_types.h" +#include "vtr_time.h" +#include "read_place.h" +#include "globals.h" +#include "vtr_log.h" +#include "cut_spreader.h" +#include "vpr_utils.h" +#include "place_util.h" // Templated struct for constructing and solving matrix equations in analytic placer template @@ -122,8 +123,10 @@ constexpr int HEAP_STALLED_ITERATIONS_STOP = 15; * Placement & device info is accessed via g_vpr_ctx */ -AnalyticPlacer::AnalyticPlacer(BlkLocRegistry& blk_loc_registry) - : blk_loc_registry_ref_(blk_loc_registry) { +AnalyticPlacer::AnalyticPlacer(BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros) + : blk_loc_registry_ref_(blk_loc_registry) + , place_macros_(place_macros) { //Eigen::initParallel(); // TODO: PlacerHeapCfg should be externally configured & supplied @@ -297,12 +300,11 @@ void AnalyticPlacer::build_legal_locations() { void AnalyticPlacer::init() { const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; auto& init_block_locs = blk_loc_registry_ref_.block_locs(); - auto& place_macros = blk_loc_registry_ref_.place_macros(); for (auto blk_id : clb_nlist.blocks()) { blk_locs.insert(blk_id, BlockLocation{}); blk_locs[blk_id].loc = init_block_locs[blk_id].loc; // transfer of initial placement - row_num.insert(blk_id, DONT_SOLVE); // no blocks are moved by default, until they are setup in setup_solve_blks() + row_num.insert(blk_id, DONT_SOLVE); // no blocks are moved by default, until they are setup in setup_solve_blks() } // only blocks with connections are considered @@ -319,7 +321,7 @@ void AnalyticPlacer::init() { if (!init_block_locs[blk_id].is_fixed && has_connections(blk_id)) // not fixed and has connections // matrix equation is formulated based on connections, so requires at least one connection - if (place_macros.get_imacro_from_iblk(blk_id) == NO_MACRO || place_macros.macro_head(blk_id) == blk_id) { + if (place_macros_.get_imacro_from_iblk(blk_id) == NO_MACRO || place_macros_.macro_head(blk_id) == blk_id) { // not in macro or head of macro // for macro, only the head (base) block of the macro is a free variable, the location of other macro // blocks can be calculated using offset of the head. They are not free variables in the equation system @@ -379,7 +381,6 @@ int AnalyticPlacer::total_hpwl() { */ void AnalyticPlacer::setup_solve_blks(t_logical_block_type_ptr blkTypes) { const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = blk_loc_registry_ref_.place_macros(); int row = 0; solve_blks.clear(); @@ -395,9 +396,9 @@ void AnalyticPlacer::setup_solve_blks(t_logical_block_type_ptr blkTypes) { } } // update row_num of macro members - for (auto& macro : blk_loc_registry_ref_.place_macros().macros()) { + for (auto& macro : place_macros_.macros()) { for (auto& member : macro.members) { - row_num[member.blk_index] = row_num[place_macros.macro_head(member.blk_index)]; + row_num[member.blk_index] = row_num[place_macros_.macro_head(member.blk_index)]; } } } @@ -408,7 +409,7 @@ void AnalyticPlacer::setup_solve_blks(t_logical_block_type_ptr blkTypes) { * when formulating the matrix equations), an update for members is necessary */ void AnalyticPlacer::update_macros() { - for (auto& macro : blk_loc_registry_ref_.place_macros().macros()) { + for (auto& macro : place_macros_.macros()) { ClusterBlockId head_id = macro.members[0].blk_index; bool mac_can_be_placed = macro_can_be_placed(macro, blk_locs[head_id].loc, true, blk_loc_registry_ref_); @@ -471,8 +472,6 @@ void AnalyticPlacer::stamp_weight_on_matrix(EquationSystem& es, ClusterBlockId var, ClusterBlockId eqn, double weight) { - const auto& place_macros = blk_loc_registry_ref_.place_macros(); - // Return the x or y position of a block auto blk_p = [&](ClusterBlockId blk_id) { return dir ? blk_locs[blk_id].loc.y : blk_locs[blk_id].loc.x; }; @@ -486,8 +485,8 @@ void AnalyticPlacer::stamp_weight_on_matrix(EquationSystem& es, } else { // var is not movable, stamp weight on rhs vector es.add_rhs(eqn_row, -v_pos * weight); } - if (place_macros.get_imacro_from_iblk(var) != NO_MACRO) { // var is part of a macro, stamp on rhs vector - auto& members = place_macros[place_macros.get_imacro_from_iblk(var)].members; + if (place_macros_.get_imacro_from_iblk(var) != NO_MACRO) { // var is part of a macro, stamp on rhs vector + auto& members = place_macros_[place_macros_.get_imacro_from_iblk(var)].members; for (auto& member : members) { // go through macro members to find the right member block if (member.blk_index == var) es.add_rhs(eqn_row, -(dir ? member.offset.y : member.offset.x) * weight); diff --git a/vpr/src/place/analytic_placer.h b/vpr/src/place/analytic_placer.h index b73b3486f57..86e31481858 100644 --- a/vpr/src/place/analytic_placer.h +++ b/vpr/src/place/analytic_placer.h @@ -82,9 +82,10 @@ * https://github.com/YosysHQ/nextpnr */ -# include "vpr_context.h" -# include "timing_place.h" -# include "PlacementDelayCalculator.h" +#include "vpr_context.h" +#include "PlacementDelayCalculator.h" + +class PlaceMacros; /* * @brief Templated struct for constructing and solving matrix equations in analytic placer @@ -99,7 +100,6 @@ extern int DONT_SOLVE; // sentinel for blks not part of a placement macro extern int NO_MACRO; - class AnalyticPlacer { public: /* @@ -107,7 +107,7 @@ class AnalyticPlacer { * To tune these parameters, change directly in constructor */ AnalyticPlacer() = delete; - explicit AnalyticPlacer(BlkLocRegistry& blk_loc_registry); + explicit AnalyticPlacer(BlkLocRegistry& blk_loc_registry, const PlaceMacros& place_macros); /* * @brief main function of analytic placement @@ -168,6 +168,9 @@ class AnalyticPlacer { // reference to the placement location variables BlkLocRegistry& blk_loc_registry_ref_; + // Reference to the placement macros. + const PlaceMacros& place_macros_; + /* * The set of blks of different types to be placed by AnalyticPlacement process, * i.e. the free variable blocks. diff --git a/vpr/src/place/annealer.cpp b/vpr/src/place/annealer.cpp index b18f60b27bd..949dfe5b4c1 100644 --- a/vpr/src/place/annealer.cpp +++ b/vpr/src/place/annealer.cpp @@ -6,6 +6,7 @@ #include "globals.h" #include "draw_global.h" +#include "place_macro.h" #include "vpr_types.h" #include "place_util.h" #include "placer_state.h" @@ -16,6 +17,8 @@ #include "read_place.h" #include "placer_breakpoint.h" #include "RL_agent_util.h" +#include "PlacerSetupSlacks.h" +#include "PlacerCriticalities.h" /**************************************************************************/ /*************** Static Function Declarations *****************************/ @@ -135,7 +138,6 @@ bool t_annealing_state::outer_loop_update(float success_rate, auto& cluster_ctx = g_vpr_ctx.clustering(); float t_exit = 0.005 * costs.cost / cluster_ctx.clb_nlist.nets().size(); - VTR_ASSERT_SAFE(placer_opts.anneal_sched.type == e_sched_type::AUTO_SCHED); // Automatically adjust alpha according to success rate. if (success_rate > 0.96) { @@ -187,6 +189,7 @@ void t_annealing_state::update_crit_exponent(const t_placer_opts& placer_opts) { PlacementAnnealer::PlacementAnnealer(const t_placer_opts& placer_opts, PlacerState& placer_state, + const PlaceMacros& place_macros, t_placer_costs& costs, NetCostHandler& net_cost_handler, std::optional& noc_cost_handler, @@ -202,6 +205,7 @@ PlacementAnnealer::PlacementAnnealer(const t_placer_opts& placer_opts, int move_lim) : placer_opts_(placer_opts) , placer_state_(placer_state) + , place_macros_(place_macros) , costs_(costs) , net_cost_handler_(net_cost_handler) , noc_cost_handler_(noc_cost_handler) @@ -209,7 +213,7 @@ PlacementAnnealer::PlacementAnnealer(const t_placer_opts& placer_opts, , rng_(rng) , move_generator_1_(std::move(move_generator_1)) , move_generator_2_(std::move(move_generator_2)) - , manual_move_generator_(placer_state, rng) + , manual_move_generator_(placer_state, place_macros, net_cost_handler, rng) , agent_state_(e_agent_state::EARLY_IN_THE_ANNEAL) , delay_model_(delay_model) , criticalities_(criticalities) @@ -219,8 +223,7 @@ PlacementAnnealer::PlacementAnnealer(const t_placer_opts& placer_opts, , move_stats_file_(nullptr, vtr::fclose) , outer_crit_iter_count_(1) , blocks_affected_(placer_state.block_locs().size()) - , quench_started_(false) -{ + , quench_started_(false) { const auto& device_ctx = g_vpr_ctx.device(); float first_crit_exponent; @@ -230,7 +233,9 @@ PlacementAnnealer::PlacementAnnealer(const t_placer_opts& placer_opts, first_crit_exponent = 0.f; } - int first_move_lim = get_initial_move_lim(placer_opts, placer_opts_.anneal_sched); + int first_move_lim = get_place_inner_loop_num_move(placer_opts, placer_opts_.anneal_sched); + + VTR_LOG("Moves per temperature: %d\n", first_move_lim); if (placer_opts.inner_loop_recompute_divider != 0) { inner_recompute_limit_ = static_cast(0.5 + (float)first_move_lim / (float)placer_opts.inner_loop_recompute_divider); @@ -252,10 +257,14 @@ PlacementAnnealer::PlacementAnnealer(const t_placer_opts& placer_opts, tot_iter_ = 0; // Get the first range limiter - placer_state_.mutable_move().first_rlim = (float)std::max(device_ctx.grid.width() - 1, device_ctx.grid.height() - 1); - - annealing_state_ = t_annealing_state(EPSILON, // Set the temperature low to ensure that initial placement quality will be preserved - placer_state_.move().first_rlim, + MoveGenerator::first_rlim = (float)std::max(device_ctx.grid.width() - 1, device_ctx.grid.height() - 1); + + // In automatic schedule we do a number of random moves before starting the main annealer + // to get an estimate for the initial temperature. We set this temperature low + // to ensure that initial placement quality will be preserved + constexpr float pre_annealing_temp = 1.e-15f; + annealing_state_ = t_annealing_state(pre_annealing_temp, + MoveGenerator::first_rlim, first_move_lim, first_crit_exponent); @@ -364,7 +373,6 @@ e_move_result PlacementAnnealer::try_swap_(MoveGenerator& move_generator, double bb_delta_c = 0; //Change in the bounding box (wiring) cost. double timing_delta_c = 0; //Change in the timing cost (delay * criticality). - /* Allow some fraction of moves to not be restricted by rlim, * in the hopes of better escaping local minima. */ float rlim; @@ -386,12 +394,12 @@ e_move_result PlacementAnnealer::try_swap_(MoveGenerator& move_generator, if (manual_move_enabled) { #ifndef NO_GRAPHICS create_move_outcome = manual_move_display_and_propose(manual_move_generator_, blocks_affected_, - proposed_action.move_type, rlim, placer_opts_, - criticalities_); + proposed_action.move_type, rlim, + placer_opts_, criticalities_); #endif //NO_GRAPHICS } else if (router_block_move) { // generate a move where two random router blocks are swapped - create_move_outcome = propose_router_swap(blocks_affected_, rlim, blk_loc_registry, rng_); + create_move_outcome = propose_router_swap(blocks_affected_, rlim, blk_loc_registry, place_macros_, rng_); proposed_action.move_type = e_move_type::UNIFORM; } else { //Generate a new move (perturbation) used to explore the space of possible placements @@ -488,7 +496,7 @@ e_move_result PlacementAnnealer::try_swap_(MoveGenerator& move_generator, criticalities_->disable_update(); setup_slacks_->enable_update(); update_timing_classes(crit_params, timing_info_, criticalities_, - setup_slacks_, pin_timing_invalidator_, placer_state_); + setup_slacks_, pin_timing_invalidator_); /* Get the setup slack analysis cost */ //TODO: calculate a weighted average of the slack cost and wiring cost @@ -553,7 +561,7 @@ e_move_result PlacementAnnealer::try_swap_(MoveGenerator& move_generator, // Update clb data structures since we kept the move. blk_loc_registry.commit_move_blocks(blocks_affected_); - if (noc_opts_.noc){ + if (noc_opts_.noc) { noc_cost_handler_->commit_noc_costs(); costs_ += noc_delta_c; } @@ -592,7 +600,7 @@ e_move_result PlacementAnnealer::try_swap_(MoveGenerator& move_generator, // Revert the timing update update_timing_classes(crit_params, timing_info_, criticalities_, - setup_slacks_, pin_timing_invalidator_, placer_state_); + setup_slacks_, pin_timing_invalidator_); VTR_ASSERT_SAFE_MSG( verify_connection_setup_slacks(setup_slacks_, placer_state_), @@ -632,7 +640,6 @@ e_move_result PlacementAnnealer::try_swap_(MoveGenerator& move_generator, stop_placement_and_check_breakpoints(blocks_affected_, move_outcome, delta_c, bb_delta_c, timing_delta_c); #endif - // Clear the data structure containing block move info blocks_affected_.clear_move_blocks(); @@ -646,8 +653,7 @@ void PlacementAnnealer::outer_loop_update_timing_info() { if (placer_opts_.place_algorithm.is_timing_driven()) { /* At each temperature change we update these values to be used * for normalizing the tradeoff between timing and wirelength (bb) */ - if (outer_crit_iter_count_ >= placer_opts_.recompute_crit_iter || - placer_opts_.inner_loop_recompute_divider != 0) { + if (outer_crit_iter_count_ >= placer_opts_.recompute_crit_iter || placer_opts_.inner_loop_recompute_divider != 0) { PlaceCritParams crit_params{annealing_state_.crit_exponent, placer_opts_.place_crit_limit}; @@ -746,9 +752,7 @@ void PlacementAnnealer::placement_inner_loop() { // update the RL agent's state if (!quench_started_) { - if (placer_opts_.place_algorithm.is_timing_driven() && - placer_opts_.place_agent_multistate && - agent_state_ == e_agent_state::EARLY_IN_THE_ANNEAL) { + if (placer_opts_.place_algorithm.is_timing_driven() && placer_opts_.place_agent_multistate && agent_state_ == e_agent_state::EARLY_IN_THE_ANNEAL) { if (annealing_state_.alpha < 0.85 && annealing_state_.alpha > 0.6) { agent_state_ = e_agent_state::LATE_IN_THE_ANNEAL; VTR_LOG("Agent's 2nd state: \n"); @@ -760,7 +764,6 @@ void PlacementAnnealer::placement_inner_loop() { ++annealing_state_.num_temps; } - int PlacementAnnealer::get_total_iteration() const { return tot_iter_; } @@ -842,8 +845,7 @@ void PlacementAnnealer::LOG_MOVE_STATS_PROPOSED() { } } -void PlacementAnnealer::LOG_MOVE_STATS_OUTCOME(double delta_cost, double delta_bb_cost, double delta_td_cost, - const char* outcome, const char* reason) { +void PlacementAnnealer::LOG_MOVE_STATS_OUTCOME(double delta_cost, double delta_bb_cost, double delta_td_cost, const char* outcome, const char* reason) { if (move_stats_file_) { fprintf(move_stats_file_.get(), "%g,%g,%g," diff --git a/vpr/src/place/annealer.h b/vpr/src/place/annealer.h index fd9b0dbd928..66abceea1e3 100644 --- a/vpr/src/place/annealer.h +++ b/vpr/src/place/annealer.h @@ -10,6 +10,7 @@ #include #include +class PlaceMacros; class PlacerState; class t_placer_costs; struct t_placer_opts; @@ -17,6 +18,7 @@ enum class e_agent_state; class NocCostHandler; class NetPinTimingInvalidator; +class PlacerSetupSlacks; /** * These variables keep track of the number of swaps @@ -170,6 +172,7 @@ class PlacementAnnealer { public: PlacementAnnealer(const t_placer_opts& placer_opts, PlacerState& placer_state, + const PlaceMacros& place_macros, t_placer_costs& costs, NetCostHandler& net_cost_handler, std::optional& noc_cost_handler, @@ -230,7 +233,6 @@ class PlacementAnnealer { const MoveAbortionLogger& get_move_abortion_logger() const; private: - /** * @brief Pick some block and moves it to another spot. * @@ -268,6 +270,7 @@ class PlacementAnnealer { private: const t_placer_opts& placer_opts_; PlacerState& placer_state_; + const PlaceMacros& place_macros_; /// Stores different placement cost terms t_placer_costs& costs_; /// Computes bounding box for each cluster net @@ -327,8 +330,7 @@ class PlacementAnnealer { void LOG_MOVE_STATS_HEADER(); void LOG_MOVE_STATS_PROPOSED(); - void LOG_MOVE_STATS_OUTCOME(double delta_cost, double delta_bb_cost, double delta_td_cost, - const char* outcome, const char* reason); + void LOG_MOVE_STATS_OUTCOME(double delta_cost, double delta_bb_cost, double delta_td_cost, const char* outcome, const char* reason); /** * @brief Defines the RL agent's reward function factor constant. This factor controls the weight of bb cost @@ -336,4 +338,4 @@ class PlacementAnnealer { * -1*(1.5-REWARD_BB_TIMING_RELATIVE_WEIGHT)*timing_cost + (1+REWARD_BB_TIMING_RELATIVE_WEIGHT)*bb_cost) */ static constexpr float REWARD_BB_TIMING_RELATIVE_WEIGHT = 0.4; -}; \ No newline at end of file +}; diff --git a/vpr/src/place/compressed_grid.cpp b/vpr/src/place/compressed_grid.cpp index 33fa04cbfc1..ce081acb16f 100644 --- a/vpr/src/place/compressed_grid.cpp +++ b/vpr/src/place/compressed_grid.cpp @@ -3,6 +3,7 @@ #include "arch_util.h" #include "globals.h" +#include "physical_types_util.h" #include "vtr_time.h" /** @@ -17,7 +18,6 @@ static t_compressed_block_grid create_compressed_block_grid(const std::vector>>& locations, int num_layers); - std::vector create_compressed_block_grids() { /* Measure how long it takes to allocate and initialize compressed grid. * The measured execution time is printed when this object goes out of scope @@ -43,7 +43,7 @@ std::vector create_compressed_block_grids() { int width_offset = grid.get_width_offset({x, y, layer_num}); int height_offset = grid.get_height_offset(t_physical_tile_loc(x, y, layer_num)); - if (width_offset == 0 && height_offset == 0) { // the bottom left corner of a tile + if (width_offset == 0 && height_offset == 0) { // the bottom left corner of a tile const auto& type = grid.get_physical_type({x, y, layer_num}); auto equivalent_sites = get_equivalent_sites_set(type); diff --git a/vpr/src/place/compressed_grid.h b/vpr/src/place/compressed_grid.h index c9030a39376..6f9575fb670 100644 --- a/vpr/src/place/compressed_grid.h +++ b/vpr/src/place/compressed_grid.h @@ -1,8 +1,10 @@ #ifndef VPR_COMPRESSED_GRID_H #define VPR_COMPRESSED_GRID_H +#include #include "physical_types.h" +#include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_flat_map.h" @@ -60,18 +62,22 @@ struct t_compressed_block_grid { * * This function takes a physical tile location in the grid and converts it to the corresponding * compressed location. The conversion approximates by rounding up to the nearest valid compressed location. + * If all the compressed locations are less than the grid location, the function will return the last compressed location. * * @param grid_loc The physical tile location in the grid. * @return The corresponding compressed location with the same layer number. */ inline t_physical_tile_loc grid_loc_to_compressed_loc_approx_round_up(t_physical_tile_loc grid_loc) const { auto find_compressed_index = [](const std::vector& compressed, int value) -> int { - auto itr = std::upper_bound(compressed.begin(), compressed.end(), value); - if (itr == compressed.begin()) - return 0; - if (itr == compressed.end() || *(itr - 1) == value) - return (int)std::distance(compressed.begin(), itr - 1); - return (int)std::distance(compressed.begin(), itr); + // Get the first element that is not less than the value + auto itr = std::lower_bound(compressed.begin(), compressed.end(), value); + if (itr == compressed.end()) { + // If all the compressed locations are less than the grid location, return the last compressed location + return compressed.size() - 1; + } else { + // Return the index of the first element that is not less than the value + return std::distance(compressed.begin(), itr); + } }; int layer_num = grid_loc.layer_num; @@ -86,17 +92,22 @@ struct t_compressed_block_grid { * * This function takes a physical tile location in the grid and converts it to the corresponding * compressed location. The conversion approximates by rounding down to the nearest valid compressed location. + * If all the compressed locations are bigger than the grid location, the function will return the first compressed location. * * @param grid_loc The physical tile location in the grid. * @return The corresponding compressed location with the same layer number. */ inline t_physical_tile_loc grid_loc_to_compressed_loc_approx_round_down(t_physical_tile_loc grid_loc) const { auto find_compressed_index = [](const std::vector& compressed, int value) -> int { - auto itr = std::lower_bound(compressed.begin(), compressed.end(), value); - if (itr == compressed.end()) { - return (int)std::distance(compressed.begin(), itr - 1); + // Get the first element that is strictly bigger than the value + auto itr = std::upper_bound(compressed.begin(), compressed.end(), value); + if (itr == compressed.begin()) { + // If all the compressed locations are bigger than the grid location, return the first compressed location + return 0; + } else { + // Return the index of the first element that is less than or equal to the value + return std::distance(compressed.begin(), itr - 1); } - return (int)std::distance(compressed.begin(), itr); }; int layer_num = grid_loc.layer_num; @@ -111,31 +122,29 @@ struct t_compressed_block_grid { * * Useful when the point is of a different block type from coords. * - * @param point represents a coordinate in one dimension of the point - * @param coords represents vector of coordinate values of a single type only - * - * Hence, the exact point coordinate will not be found in coords if they are of different block types. In this case the function will return - * the nearest compressed location to point by rounding it down + * @param grid_loc non-compressed physical tile location in the grid + * @return Nearest x and y compressed locations in the grid (in the same layer) */ inline t_physical_tile_loc grid_loc_to_compressed_loc_approx(t_physical_tile_loc grid_loc) const { auto find_closest_compressed_point = [](int loc, const std::vector& compressed_grid_dim) -> int { + VTR_ASSERT_DEBUG(compressed_grid_dim.size() > 0); + + // Find the first element not less than loc auto itr = std::lower_bound(compressed_grid_dim.begin(), compressed_grid_dim.end(), loc); - int cx; - if (itr < compressed_grid_dim.end() - 1) { - int dist_prev = abs(loc - *itr); - int dist_next = abs(loc - *(itr+1)); - if (dist_prev < dist_next) { - cx = std::distance(compressed_grid_dim.begin(), itr); - } else { - cx = std::distance(compressed_grid_dim.begin(), itr + 1); - } + + if (itr == compressed_grid_dim.begin()) { + // If all the compressed locations are bigger that or equal to loc, return the first compressed location + return 0; } else if (itr == compressed_grid_dim.end()) { - cx = std::distance(compressed_grid_dim.begin(), itr - 1); + // If all the compressed locations are less than loc, return the last compressed location + return compressed_grid_dim.size() - 1; } else { - cx = std::distance(compressed_grid_dim.begin(), itr); + // Find the nearest compressed location. + int dist_prev = loc - *(itr - 1); + int dist_next = *itr - loc; + VTR_ASSERT_DEBUG(dist_prev >= 0 && dist_next >= 0); + return (dist_prev <= dist_next) ? (std::distance(compressed_grid_dim.begin(), itr - 1)) : (std::distance(compressed_grid_dim.begin(), itr)); } - - return cx; }; const int layer_num = grid_loc.layer_num; diff --git a/vpr/src/place/cut_spreader.cpp b/vpr/src/place/cut_spreader.cpp index c9c969b1abd..9dfe17f83c6 100644 --- a/vpr/src/place/cut_spreader.cpp +++ b/vpr/src/place/cut_spreader.cpp @@ -1,18 +1,19 @@ +#include "place_macro.h" #ifdef ENABLE_ANALYTIC_PLACE -# include "cut_spreader.h" -# include -# include -# include -# include +#include "cut_spreader.h" +#include +#include +#include +#include -# include "analytic_placer.h" -# include "vpr_types.h" -# include "vtr_time.h" -# include "globals.h" -# include "vtr_log.h" -# include "place_util.h" -# include "grid_block.h" +#include "analytic_placer.h" +#include "vpr_types.h" +#include "vtr_time.h" +#include "globals.h" +#include "vtr_log.h" +#include "place_util.h" +#include "grid_block.h" // sentinel for base case in CutSpreader (i.e. only 1 block left in region) constexpr std::pair BASE_CASE = {-2, -2}; @@ -112,7 +113,7 @@ void CutSpreader::cutSpread() { // setup CutSpreader data structures using information from AnalyticPlacer void CutSpreader::init() { const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; size_t max_x = g_vpr_ctx.device().grid.width(); size_t max_y = g_vpr_ctx.device().grid.height(); @@ -407,7 +408,7 @@ void CutSpreader::expand_regions() { std::pair CutSpreader::cut_region(SpreaderRegion& r, bool dir) { const DeviceContext& device_ctx = g_vpr_ctx.device(); const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; // TODO: CutSpreader is not compatible with 3D FPGA VTR_ASSERT(device_ctx.grid.get_num_layers() == 1); @@ -619,7 +620,7 @@ int CutSpreader::initial_source_cut(SpreaderRegion& r, bool dir, int& clearance_l, int& clearance_r) { - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; // pivot is the midpoint of cut_blks in terms of total block size (counting macro members) // this ensures the initial partitions have similar number of blocks @@ -672,7 +673,7 @@ int CutSpreader::initial_target_cut(SpreaderRegion& r, int& right_blks_n, int& left_tiles_n, int& right_tiles_n) { - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; // To achieve smallest difference in utilization, first move all tiles to right partition left_blks_n = 0, right_blks_n = 0; @@ -808,7 +809,7 @@ void CutSpreader::linear_spread_subarea(std::vector& cut_blks, void CutSpreader::strict_legalize() { auto& clb_nlist = g_vpr_ctx.clustering().clb_nlist; const auto& block_locs = ap->blk_loc_registry_ref_.block_locs(); - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; int max_x = g_vpr_ctx.device().grid.width(); int max_y = g_vpr_ctx.device().grid.height(); @@ -1035,14 +1036,14 @@ bool CutSpreader::try_place_blk(ClusterBlockId blk, std::priority_queue>& remaining) { const auto& grid_blocks = ap->blk_loc_registry_ref_.grid_blocks(); const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; // iteration at current radius has exceeded exploration limit, and a candidate sub_tile (best_subtile) is found // then blk is placed in best_subtile if (exceeds_explore_limit && best_subtile != t_pl_loc{}) { // find the logic block bound to (placed on) best_subtile ClusterBlockId bound_blk = grid_blocks.block_at_location(best_subtile); - if (bound_blk) { // if best_subtile has a logic block + if (bound_blk) { // if best_subtile has a logic block unbind_tile(best_subtile); // clear bound_block and best_subtile's placement info remaining.emplace(1, bound_blk); // put bound_blk back into remaining blocks to place } @@ -1051,7 +1052,7 @@ bool CutSpreader::try_place_blk(ClusterBlockId blk, } // if exploration limit is not met or a candidate sub_tile is not found yet - for (auto sub_t : subtiles_at_location[nx][ny]) { // for each available sub_tile at random location + for (auto sub_t : subtiles_at_location[nx][ny]) { // for each available sub_tile at random location ClusterBlockId bound_blk = grid_blocks.block_at_location(sub_t); // logic blk at [nx, ny] if (bound_blk == ClusterBlockId::INVALID() || ripup_radius_met @@ -1112,7 +1113,7 @@ bool CutSpreader::try_place_macro(ClusterBlockId blk, int nx, int ny, std::priority_queue>& remaining) { - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; const auto& grid_blocks = ap->blk_loc_registry_ref_.grid_blocks(); const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; diff --git a/vpr/src/place/cut_spreader.h b/vpr/src/place/cut_spreader.h index 472cd9cc722..5be5f0ed79d 100644 --- a/vpr/src/place/cut_spreader.h +++ b/vpr/src/place/cut_spreader.h @@ -107,8 +107,8 @@ * https://github.com/YosysHQ/nextpnr * */ -# include "vpr_context.h" -# include +#include "vpr_context.h" +#include // declaration of used types; class AnalyticPlacer; diff --git a/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp b/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp new file mode 100644 index 00000000000..e58cb4b9539 --- /dev/null +++ b/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp @@ -0,0 +1,80 @@ + + +#include "PlacementDelayModelCreator.h" + +#include "place_delay_model.h" +#include "simple_delay_model.h" +#include "delta_delay_model.h" +#include "override_delay_model.h" + +#include "vtr_time.h" +#include "physical_types.h" +#include "place_and_route.h" + +static int get_longest_segment_length(std::vector& segment_inf) { + int length = 0; + + for (const t_segment_inf& seg_info : segment_inf) { + if (seg_info.length > length) { + length = seg_info.length; + } + } + + return length; +} + +std::unique_ptr +PlacementDelayModelCreator::create_delay_model(const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + const Netlist<>& net_list, + t_det_routing_arch* det_routing_arch, + std::vector& segment_inf, + t_chan_width_dist chan_width_dist, + const std::vector& directs, + bool is_flat) { + vtr::ScopedStartFinishTimer timer("Computing placement delta delay look-up"); + + t_chan_width chan_width = setup_chan_width(router_opts, chan_width_dist); + + alloc_routing_structs(chan_width, router_opts, det_routing_arch, segment_inf, directs, is_flat); + + const RouterLookahead* router_lookahead = get_cached_router_lookahead(*det_routing_arch, + router_opts.lookahead_type, + router_opts.write_router_lookahead, + router_opts.read_router_lookahead, + segment_inf, + is_flat); + + RouterDelayProfiler route_profiler(net_list, router_lookahead, is_flat); + + int longest_length = get_longest_segment_length(segment_inf); + + // now setup and compute the actual arrays + std::unique_ptr place_delay_model; + float min_cross_layer_delay = get_min_cross_layer_delay(); + + if (placer_opts.delay_model_type == PlaceDelayModelType::SIMPLE) { + place_delay_model = std::make_unique(); + } else if (placer_opts.delay_model_type == PlaceDelayModelType::DELTA) { + place_delay_model = std::make_unique(min_cross_layer_delay, is_flat); + } else if (placer_opts.delay_model_type == PlaceDelayModelType::DELTA_OVERRIDE) { + place_delay_model = std::make_unique(min_cross_layer_delay, is_flat); + } else { + VTR_ASSERT_MSG(false, "Invalid placer delay model"); + } + + if (placer_opts.read_placement_delay_lookup.empty()) { + place_delay_model->compute(route_profiler, placer_opts, router_opts, longest_length); + } else { + place_delay_model->read(placer_opts.read_placement_delay_lookup); + } + + if (!placer_opts.write_placement_delay_lookup.empty()) { + place_delay_model->write(placer_opts.write_placement_delay_lookup); + } + + // free all data structures that are no longer needed + free_routing_structs(); + + return place_delay_model; +} diff --git a/vpr/src/place/delay_model/PlacementDelayModelCreator.h b/vpr/src/place/delay_model/PlacementDelayModelCreator.h new file mode 100644 index 00000000000..c92b67d4854 --- /dev/null +++ b/vpr/src/place/delay_model/PlacementDelayModelCreator.h @@ -0,0 +1,30 @@ + +#pragma once + +#include +#include + +#include "netlist.h" + +class PlaceDelayModel; +struct t_placer_opts; +struct t_router_opts; +struct t_det_routing_arch; +struct t_segment_inf; +struct t_chan_width_dist; +struct t_direct_inf; + +class PlacementDelayModelCreator { + public: + // nothing to do in the constructor + PlacementDelayModelCreator() = delete; + + static std::unique_ptr create_delay_model(const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + const Netlist<>& net_list, + t_det_routing_arch* det_routing_arch, + std::vector& segment_inf, + t_chan_width_dist chan_width_dist, + const std::vector& directs, + bool is_flat); +}; diff --git a/vpr/src/place/delay_model/compute_delta_delays_utils.cpp b/vpr/src/place/delay_model/compute_delta_delays_utils.cpp new file mode 100644 index 00000000000..bb1232d2778 --- /dev/null +++ b/vpr/src/place/delay_model/compute_delta_delays_utils.cpp @@ -0,0 +1,966 @@ + +#include "compute_delta_delays_utils.h" + +#include "vtr_time.h" +#include "vtr_math.h" +#include "physical_types.h" +#include "globals.h" +#include "router_delay_profiling.h" + +/// Indicates the delta delay value has not been calculated +static constexpr float UNINITIALIZED_DELTA = -1; +/// Indicates delta delay from/to an EMPTY block +static constexpr float EMPTY_DELTA = -2; +/// Indicates there is no valid delta delay +static constexpr float IMPOSSIBLE_DELTA = std::numeric_limits::infinity(); + +static vtr::NdMatrix compute_delta_delays(RouterDelayProfiler& route_profiler, + const t_placer_opts& palcer_opts, + const t_router_opts& router_opts, + bool measure_directconnect, + size_t longest_length, + bool is_flat); + +static void fix_empty_coordinates(vtr::NdMatrix& delta_delays); + +static void fill_impossible_coordinates(vtr::NdMatrix& delta_delays); + +static bool verify_delta_delays(const vtr::NdMatrix& delta_delays); + +static void generic_compute_matrix_iterative_astar(RouterDelayProfiler& route_profiler, + vtr::Matrix>& matrix, + int from_layer_num, + int to_layer_num, + int source_x, + int source_y, + int start_x, + int start_y, + int end_x, + int end_y, + const t_router_opts& router_opts, + bool measure_directconnect, + const std::set& allowed_types, + bool /*is_flat*/); + +static void generic_compute_matrix_dijkstra_expansion(RouterDelayProfiler& route_profiler, + vtr::Matrix>& matrix, + int from_layer_num, + int to_layer_num, + int source_x, + int source_y, + int start_x, + int start_y, + int end_x, + int end_y, + const t_router_opts& router_opts, + bool measure_directconnect, + const std::set& allowed_types, + bool is_flat); + +/** + * @brief Routes between a source and sink location to calculate the delay. + * + * This function computes the delay of a routed connection between a source and sink node + * specified by their coordinates and layers. It iterates over the best driver and sink pin + * classes to find a valid routing path and calculates the delay if a path exists. + * + * @param route_profiler Reference to the `RouterDelayProfiler` responsible for calculating routing delays. + * @param source_x The x-coordinate of the source location. + * @param source_y The y-coordinate of the source location. + * @param source_layer The layer index of the source node. + * @param sink_x The x-coordinate of the sink location. + * @param sink_y The y-coordinate of the sink location. + * @param sink_layer The layer index of the sink node. + * @param router_opts Routing options used for delay calculation. + * @param measure_directconnect If `true`, includes direct connect delays; otherwise, skips direct connections. + * + * @return The calculated routing delay. If routing fails, it returns `IMPOSSIBLE_DELTA`. + */ +static float route_connection_delay(RouterDelayProfiler& route_profiler, + int source_x, + int source_y, + int source_layer, + int sink_x, + int sink_y, + int sink_layer, + const t_router_opts& router_opts, + bool measure_directconnect); + +/** + * @brief Computes a reduced value from a vector of delay values using the specified reduction method. + * + * @param delays A reference to a vector of delay values. This vector may be modified + * (e.g., sorted) depending on the reducer used. + * @param reducer The reduction method to be applied. + * + * @return The reduced delay value. If the input vector is empty, the function + * returns `IMPOSSIBLE_DELTA`. + * + * @throws VPR_FATAL_ERROR if the reducer is unrecognized. + */ +static float delay_reduce(std::vector& delays, e_reducer reducer); + +/** + * @brief Adds a delay value to a 2D matrix of delay vectors. + * + * Updates the delay vector at position (`delta_x`, `delta_y`) in the matrix. + * If the element contains only `EMPTY_DELTA`, it is replaced with the new delay; + * otherwise, the delay is appended to the vector. + * + * @param matrix A 2D matrix of delay vectors. + * @param delta_x The x-index in the matrix. + * @param delta_y The y-index in the matrix. + * @param delay The delay value to add. + */ +static void add_delay_to_matrix(vtr::Matrix>& matrix, + int delta_x, + int delta_y, + float delay); + +/** + * @brief Computes the average delay for a routing span. + * + * This function calculates the average placement delay for a routing span starting from a + * given layer and spanning a region defined by delta x and delta y. It iteratively searches + * for valid delay values within an expanding neighborhood (starting from a distance of 1) + * around the specified delta offsets and layer, until valid values are found or + * the maximum search distance (`max_distance`) is reached. + * + * @param matrix A 4D matrix of delay values indexed by `[from_layer][to_layer][delta_x][delta_y]`. + * @param from_layer The starting layer index of the routing span. + * @param to_tile_loc A structure holding the delta offsets (`x` and `y`) and the target layer index (`layer_num`). + * @param max_distance The maximum neighborhood distance to search for valid delay values. + * + * @return The average of valid delay values within the search range. If no valid delays + * are found up to the maximum distance, the function returns `IMPOSSIBLE_DELTA`. + * + * @note The function performs a Manhattan-distance-based neighborhood search around the target location. + */ +static float find_neighboring_average(vtr::NdMatrix& matrix, + int from_layer, + t_physical_tile_loc to_tile_loc, + int max_distance); + +/***************************************************************************************/ + +static vtr::NdMatrix compute_delta_delays(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + bool measure_directconnect, + size_t longest_length, + bool is_flat) { + + const auto& device_ctx = g_vpr_ctx.device(); + const auto& grid = device_ctx.grid; + + const size_t num_layers = grid.get_num_layers(); + const size_t device_width = grid.width(); + const size_t device_height = grid.height(); + + /* To avoid edge effects we place the source at least 'longest_length' away + * from the device edge and route from there for all possible delta values < dimension + */ + + // +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + // + | | + + // + A | B | C + + // + | | + + // +-----------------\-----------------------.---------------+ + // + | | + + // + | | + + // + | | + + // + | | + + // + D | E | F + + // + | | + + // + | | + + // + | | + + // + | | + + // +-----------------*-----------------------/---------------+ + // + | | + + // + G | H | I + + // + | | + + // +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + // + // * = (low_x, low_y) + // . = (high_x, high_y) + // / = (high_x, low_y) + // \ = (low_x, high_y) + // + = device edge + const size_t mid_x = vtr::nint(device_width / 2); + const size_t mid_y = vtr::nint(device_height / 2); + const size_t low_x = std::min(longest_length, mid_x); + const size_t low_y = std::min(longest_length, mid_y); + const size_t high_x = (longest_length <= device_width) ? std::max(device_width - longest_length, mid_x) : mid_x; + const size_t high_y = (longest_length <= device_height) ? std::max(device_width - longest_length, mid_y) : mid_y; + + vtr::NdMatrix delta_delays({num_layers, num_layers, device_width, device_height}); + + std::set allowed_types; + if (!placer_opts.allowed_tiles_for_delay_model.empty()) { + std::vector allowed_types_vector = vtr::split(placer_opts.allowed_tiles_for_delay_model, ","); + allowed_types = std::set(allowed_types_vector.begin(), allowed_types_vector.end()); + } + + for (int from_layer_num = 0; from_layer_num < (int)num_layers; from_layer_num++) { + for (int to_layer_num = 0; to_layer_num < (int)num_layers; to_layer_num++) { + vtr::NdMatrix, 2> sampled_delta_delays({device_width, device_height}); + + // Find the lowest y location on the left edge with a non-empty block + int y = 0; + int x = 0; + t_physical_tile_type_ptr src_type = nullptr; + for (x = 0; x < (int)device_width; ++x) { + for (y = 0; y < (int)device_height; ++y) { + t_physical_tile_type_ptr type = grid.get_physical_type({x, y, from_layer_num}); + + if (type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { + // check if the tile type is among the allowed types + if (!allowed_types.empty() && allowed_types.find(type->name) == allowed_types.end()) { + continue; + } + src_type = type; + break; + } + } + if (src_type != nullptr) { + break; + } + } + VTR_ASSERT(src_type != nullptr); + + auto generic_compute_matrix = (placer_opts.place_delta_delay_matrix_calculation_method == e_place_delta_delay_algorithm::ASTAR_ROUTE) ? generic_compute_matrix_iterative_astar : generic_compute_matrix_dijkstra_expansion; + +#ifdef VERBOSE + VTR_LOG("Computing from lower left edge (%d,%d):\n", x, y); +#endif + generic_compute_matrix(route_profiler, sampled_delta_delays, + from_layer_num, to_layer_num, + x, y, + x, y, + device_width - 1, device_height - 1, + router_opts, + measure_directconnect, allowed_types, + is_flat); + + // Find the lowest x location on the bottom edge with a non-empty block + src_type = nullptr; + for (y = 0; y < (int)device_height; ++y) { + for (x = 0; x < (int)device_width; ++x) { + t_physical_tile_type_ptr type = grid.get_physical_type({x, y, from_layer_num}); + + if (type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { + // check if the tile type is among the allowed types + if (!allowed_types.empty() && allowed_types.find(type->name) == allowed_types.end()) { + continue; + } + src_type = type; + break; + } + } + if (src_type) { + break; + } + } + VTR_ASSERT(src_type != nullptr); +#ifdef VERBOSE + VTR_LOG("Computing from left bottom edge (%d,%d):\n", x, y); +#endif + generic_compute_matrix(route_profiler, sampled_delta_delays, + from_layer_num, to_layer_num, + x, y, + x, y, + device_width - 1, device_height - 1, + router_opts, + measure_directconnect, allowed_types, + is_flat); + + //Since the other delta delay values may have suffered from edge effects, + //we recalculate deltas within regions B, C, E, F +#ifdef VERBOSE + VTR_LOG("Computing from low/low:\n"); +#endif + generic_compute_matrix(route_profiler, sampled_delta_delays, + from_layer_num, to_layer_num, + low_x, low_y, + low_x, low_y, + device_width - 1, device_height - 1, + router_opts, + measure_directconnect, allowed_types, + is_flat); + + //Since the other delta delay values may have suffered from edge effects, + //we recalculate deltas within regions D, E, G, H +#ifdef VERBOSE + VTR_LOG("Computing from high/high:\n"); +#endif + generic_compute_matrix(route_profiler, sampled_delta_delays, + from_layer_num, to_layer_num, + high_x, high_y, + 0, 0, + high_x, high_y, + router_opts, + measure_directconnect, allowed_types, + is_flat); + + //Since the other delta delay values may have suffered from edge effects, + //we recalculate deltas within regions A, B, D, E +#ifdef VERBOSE + VTR_LOG("Computing from high/low:\n"); +#endif + generic_compute_matrix(route_profiler, sampled_delta_delays, + from_layer_num, to_layer_num, + high_x, low_y, + 0, low_y, + high_x, device_height - 1, + router_opts, + measure_directconnect, allowed_types, + is_flat); + + //Since the other delta delay values may have suffered from edge effects, + //we recalculate deltas within regions E, F, H, I +#ifdef VERBOSE + VTR_LOG("Computing from low/high:\n"); +#endif + generic_compute_matrix(route_profiler, sampled_delta_delays, + from_layer_num, to_layer_num, + low_x, high_y, + low_x, 0, + device_width - 1, high_y, + router_opts, + measure_directconnect, allowed_types, + is_flat); + for (size_t dx = 0; dx < sampled_delta_delays.dim_size(0); ++dx) { + for (size_t dy = 0; dy < sampled_delta_delays.dim_size(1); ++dy) { + delta_delays[from_layer_num][to_layer_num][dx][dy] = delay_reduce(sampled_delta_delays[dx][dy], placer_opts.delay_model_reducer); + } + } + } + } + + return delta_delays; +} + +static void fix_empty_coordinates(vtr::NdMatrix& delta_delays) { + // Set any empty delta's to the average of its neighbours + // + // Empty coordinates may occur if the sampling location happens to not have + // a connection at that location. However, a more thorough sampling likely + // would return a result, so we fill in the empty holes with a small + // neighbour average. + constexpr int kMaxAverageDistance = 2; + for (int from_layer = 0; from_layer < (int)delta_delays.dim_size(0); ++from_layer) { + for (int to_layer = 0; to_layer < (int)delta_delays.dim_size(1); ++to_layer) { + for (int delta_x = 0; delta_x < (int)delta_delays.dim_size(2); ++delta_x) { + for (int delta_y = 0; delta_y < (int)delta_delays.dim_size(3); ++delta_y) { + if (delta_delays[from_layer][to_layer][delta_x][delta_y] == EMPTY_DELTA) { + delta_delays[from_layer][to_layer][delta_x][delta_y] = find_neighboring_average(delta_delays, + from_layer, + {delta_x, delta_y, to_layer}, + kMaxAverageDistance); + } + } + } + } + } +} + +static void fill_impossible_coordinates(vtr::NdMatrix& delta_delays) { + // Set any impossible delta's to the average of its neighbours + // + // Impossible coordinates may occur if an IPIN cannot be reached from the + // sampling OPIN. This might occur if the IPIN or OPIN used for sampling + // is specialized, and therefore cannot be reached via the by the pins + // sampled. Leaving this value in the delay matrix will result in invalid + // slacks if the delay matrix uses this value. + // + // A max average distance of 5 is used to provide increased effort in + // filling these gaps. It is more important to have a poor predication, + // than an invalid value and causing a slack assertion. + constexpr int kMaxAverageDistance = 5; + for (int from_layer_num = 0; from_layer_num < (int)delta_delays.dim_size(0); ++from_layer_num) { + for (int to_layer_num = 0; to_layer_num < (int)delta_delays.dim_size(1); ++to_layer_num) { + for (int delta_x = 0; delta_x < (int)delta_delays.dim_size(2); ++delta_x) { + for (int delta_y = 0; delta_y < (int)delta_delays.dim_size(3); ++delta_y) { + if (delta_delays[from_layer_num][to_layer_num][delta_x][delta_y] == IMPOSSIBLE_DELTA) { + delta_delays[from_layer_num][to_layer_num][delta_x][delta_y] = find_neighboring_average( + delta_delays, from_layer_num, {delta_x, delta_y, to_layer_num}, kMaxAverageDistance); + } + } + } + } + } +} + +static bool verify_delta_delays(const vtr::NdMatrix& delta_delays) { + const auto& device_ctx = g_vpr_ctx.device(); + const auto& grid = device_ctx.grid; + + for (int from_layer_num = 0; from_layer_num < grid.get_num_layers(); ++from_layer_num) { + for (int to_layer_num = 0; to_layer_num < grid.get_num_layers(); ++to_layer_num) { + for (size_t x = 0; x < grid.width(); ++x) { + for (size_t y = 0; y < grid.height(); ++y) { + float delta_delay = delta_delays[from_layer_num][to_layer_num][x][y]; + + if (delta_delay < 0.) { + VPR_ERROR(VPR_ERROR_PLACE, + "Found invalid negative delay %g for delta [%d,%d,%d,%d]", + delta_delay, from_layer_num, to_layer_num, x, y); + } + } + } + } + } + + return true; +} + +static void generic_compute_matrix_iterative_astar(RouterDelayProfiler& route_profiler, + vtr::Matrix>& matrix, + int from_layer_num, + int to_layer_num, + int source_x, + int source_y, + int start_x, + int start_y, + int end_x, + int end_y, + const t_router_opts& router_opts, + bool measure_directconnect, + const std::set& allowed_types, + bool /*is_flat*/) { + const auto& device_ctx = g_vpr_ctx.device(); + + for (int sink_x = start_x; sink_x <= end_x; sink_x++) { + for (int sink_y = start_y; sink_y <= end_y; sink_y++) { + const int delta_x = abs(sink_x - source_x); + const int delta_y = abs(sink_y - source_y); + + t_physical_tile_type_ptr src_type = device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num}); + t_physical_tile_type_ptr sink_type = device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num}); + + bool src_or_target_empty = (src_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE + || sink_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE); + + bool is_allowed_type = allowed_types.empty() || allowed_types.find(src_type->name) != allowed_types.end(); + + if (src_or_target_empty || !is_allowed_type) { + if (matrix[delta_x][delta_y].empty()) { + // Only set empty target if we don't already have a valid delta delay + matrix[delta_x][delta_y].push_back(EMPTY_DELTA); +#ifdef VERBOSE + VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", + "EMPTY", + delta_x, delta_y, + source_x, source_y, + sink_x, sink_y); +#endif + } + } else { + // Valid start/end + float delay = route_connection_delay(route_profiler, + source_x, + source_y, + from_layer_num, + sink_x, + sink_y, + to_layer_num, + router_opts, + measure_directconnect); + +#ifdef VERBOSE + VTR_LOG("Computed delay: %12g delta: %d,%d (src: %d,%d sink: %d,%d)\n", + delay, + delta_x, delta_y, + source_x, source_y, + sink_x, sink_y); +#endif + if (matrix[delta_x][delta_y].size() == 1 && matrix[delta_x][delta_y][0] == EMPTY_DELTA) { + // Overwrite empty delta + matrix[delta_x][delta_y][0] = delay; + } else { + // Collect delta + matrix[delta_x][delta_y].push_back(delay); + } + } + } + } +} + +static void generic_compute_matrix_dijkstra_expansion(RouterDelayProfiler& /*route_profiler*/, + vtr::Matrix>& matrix, + int from_layer_num, + int to_layer_num, + int source_x, + int source_y, + int start_x, + int start_y, + int end_x, + int end_y, + const t_router_opts& router_opts, + bool measure_directconnect, + const std::set& allowed_types, + bool is_flat) { + const auto& device_ctx = g_vpr_ctx.device(); + + t_physical_tile_type_ptr src_type = device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num}); + bool is_allowed_type = allowed_types.empty() || allowed_types.find(src_type->name) != allowed_types.end(); + if (src_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE || !is_allowed_type) { + for (int sink_x = start_x; sink_x <= end_x; sink_x++) { + for (int sink_y = start_y; sink_y <= end_y; sink_y++) { + int delta_x = abs(sink_x - source_x); + int delta_y = abs(sink_y - source_y); + + if (matrix[delta_x][delta_y].empty()) { + //Only set empty target if we don't already have a valid delta delay + matrix[delta_x][delta_y].push_back(EMPTY_DELTA); +#ifdef VERBOSE + VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", + "EMPTY", + delta_x, delta_y, + source_x, source_y, + sink_x, sink_y); +#endif + } + } + } + + return; + } + + vtr::Matrix found_matrix({matrix.dim_size(0), matrix.dim_size(1)}, false); + + auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num})); + for (int driver_ptc : best_driver_ptcs) { + VTR_ASSERT(driver_ptc != OPEN); + RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(from_layer_num, source_x, source_y, SOURCE, driver_ptc); + + VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); + auto delays = calculate_all_path_delays_from_rr_node(source_rr_node, router_opts, is_flat); + + bool path_to_all_sinks = true; + for (int sink_x = start_x; sink_x <= end_x; sink_x++) { + for (int sink_y = start_y; sink_y <= end_y; sink_y++) { + int delta_x = abs(sink_x - source_x); + int delta_y = abs(sink_y - source_y); + + if (found_matrix[delta_x][delta_y]) { + continue; + } + + t_physical_tile_type_ptr sink_type = device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num}); + if (sink_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { + if (matrix[delta_x][delta_y].empty()) { + // Only set empty target if we don't already have a valid delta delay + matrix[delta_x][delta_y].push_back(EMPTY_DELTA); +#ifdef VERBOSE + VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", + "EMPTY", + delta_x, delta_y, + source_x, source_y, + sink_x, sink_y); +#endif + found_matrix[delta_x][delta_y] = true; + } + } else { + bool found_a_sink = false; + auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num})); + for (int sink_ptc : best_sink_ptcs) { + VTR_ASSERT(sink_ptc != OPEN); + RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(to_layer_num, sink_x, sink_y, SINK, sink_ptc); + + if (sink_rr_node == RRNodeId::INVALID()) + continue; + + if (!measure_directconnect && directconnect_exists(source_rr_node, sink_rr_node)) { + // Skip if we shouldn't measure direct connects and a direct connect exists + continue; + } + + if (std::isnan(delays[sink_rr_node])) { + // This sink was not found + continue; + } + +#ifdef VERBOSE + VTR_LOG("Computed delay: %12g delta: %d,%d (src: %d,%d sink: %d,%d)\n", + delays[size_t(sink_rr_node)], + delta_x, delta_y, + source_x, source_y, + sink_x, sink_y); +#endif + found_matrix[delta_x][delta_y] = true; + + add_delay_to_matrix(matrix, delta_x, delta_y, delays[sink_rr_node]); + + found_a_sink = true; + break; + } + + if (!found_a_sink) { + path_to_all_sinks = false; + } + } + } + } + + if (path_to_all_sinks) { + break; + } + } + + for (int sink_x = start_x; sink_x <= end_x; sink_x++) { + for (int sink_y = start_y; sink_y <= end_y; sink_y++) { + int delta_x = abs(sink_x - source_x); + int delta_y = abs(sink_y - source_y); + if (!found_matrix[delta_x][delta_y]) { + add_delay_to_matrix(matrix, delta_x, delta_y, IMPOSSIBLE_DELTA); + VTR_LOG_WARN("Unable to route between blocks at (%d,%d,%d) and (%d,%d,%d) to characterize delay (setting to %g)\n", + source_x, + source_y, + from_layer_num, + sink_x, + sink_y, + to_layer_num, + IMPOSSIBLE_DELTA); + } + } + } +} + +static float route_connection_delay(RouterDelayProfiler& route_profiler, + int source_x, + int source_y, + int source_layer, + int sink_x, + int sink_y, + int sink_layer, + const t_router_opts& router_opts, + bool measure_directconnect) { + //Routes between the source and sink locations and calculates the delay + + // set to known value for debug purposes + float net_delay_value = IMPOSSIBLE_DELTA; + + const auto& device_ctx = g_vpr_ctx.device(); + + bool successfully_routed = false; + + // Get the rr nodes to route between + auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, source_layer})); + auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, sink_layer})); + + for (int driver_ptc : best_driver_ptcs) { + VTR_ASSERT(driver_ptc != OPEN); + RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(source_layer, source_x, source_y, SOURCE, driver_ptc); + + VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); + + for (int sink_ptc : best_sink_ptcs) { + VTR_ASSERT(sink_ptc != OPEN); + RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(sink_layer, sink_x, sink_y, SINK, sink_ptc); + + if (sink_rr_node == RRNodeId::INVALID()) + continue; + + if (!measure_directconnect && directconnect_exists(source_rr_node, sink_rr_node)) { + // Skip if we shouldn't measure direct connects and a direct connect exists + continue; + } + + successfully_routed = route_profiler.calculate_delay(source_rr_node, + sink_rr_node, + router_opts, + &net_delay_value); + + if (successfully_routed) break; + } + if (successfully_routed) break; + } + + if (!successfully_routed) { + VTR_LOG_WARN("Unable to route between blocks at (%d,%d,%d) and (%d,%d,%d) to characterize delay (setting to %g)\n", + source_x, source_y, source_layer, sink_x, sink_y, sink_layer, net_delay_value); + } + + return net_delay_value; +} + +static float delay_reduce(std::vector& delays, e_reducer reducer) { + if (delays.empty()) { + return IMPOSSIBLE_DELTA; + } + + if (delays.size() == 1) { + return delays[0]; + } + + VTR_ASSERT(delays.size() > 1); + + float delay; + + if (reducer == e_reducer::MIN) { + auto itr = std::min_element(delays.begin(), delays.end()); + delay = *itr; + } else if (reducer == e_reducer::MAX) { + auto itr = std::max_element(delays.begin(), delays.end()); + delay = *itr; + } else if (reducer == e_reducer::MEDIAN) { + std::stable_sort(delays.begin(), delays.end()); + delay = vtr::median(delays.begin(), delays.end()); + } else if (reducer == e_reducer::ARITHMEAN) { + delay = vtr::arithmean(delays.begin(), delays.end()); + } else if (reducer == e_reducer::GEOMEAN) { + delay = vtr::geomean(delays.begin(), delays.end()); + } else { + VPR_FATAL_ERROR(VPR_ERROR_PLACE, "Unrecognized delta delay reducer"); + } + + return delay; +} + +static void add_delay_to_matrix(vtr::Matrix>& matrix, + int delta_x, + int delta_y, + float delay) { + if (matrix[delta_x][delta_y].size() == 1 && matrix[delta_x][delta_y][0] == EMPTY_DELTA) { + // Overwrite empty delta + matrix[delta_x][delta_y][0] = delay; + } else { + // Collect delta + matrix[delta_x][delta_y].push_back(delay); + } +} + +static float find_neighboring_average(vtr::NdMatrix& matrix, + int from_layer, + t_physical_tile_loc to_tile_loc, + int max_distance) { + float sum = 0.f; + int num_samples = 0; + const int endx = matrix.end_index(2); + const int endy = matrix.end_index(3); + + const int x = to_tile_loc.x; + const int y = to_tile_loc.y; + const int to_layer = to_tile_loc.layer_num; + + for (int distance = 1; distance <= max_distance; ++distance) { + for (int delx = x - distance; delx <= x + distance; delx++) { + for (int dely = y - distance; dely <= y + distance; dely++) { + // Check distance constraint + if (abs(delx - x) + abs(dely - y) > distance) { + continue; + } + + //check out of bounds + if (delx < 0 || dely < 0 || delx >= endx || dely >= endy || (delx == x && dely == y)) { + continue; + } + + if (matrix[from_layer][to_layer][delx][dely] == EMPTY_DELTA || matrix[from_layer][to_layer][delx][dely] == IMPOSSIBLE_DELTA) { + continue; + } + + sum += matrix[from_layer][to_layer][delx][dely]; + num_samples++; + } + } + + if (num_samples != 0) { + return sum / (float)num_samples; + } + } + + return IMPOSSIBLE_DELTA; +} + +/***************************************************************************************/ + +vtr::NdMatrix compute_delta_delay_model(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + bool measure_directconnect, + int longest_length, + bool is_flat) { + vtr::ScopedStartFinishTimer timer("Computing delta delays"); + vtr::NdMatrix delta_delays = compute_delta_delays(route_profiler, + placer_opts, + router_opts, + measure_directconnect, + longest_length, + is_flat); + + const size_t num_elements = delta_delays.size(); + + // set uninitialized elements to infinity + for (size_t i = 0; i < num_elements; i++) { + if (delta_delays.get(i) == UNINITIALIZED_DELTA) { + delta_delays.get(i) = IMPOSSIBLE_DELTA; + } + } + + fix_empty_coordinates(delta_delays); + + fill_impossible_coordinates(delta_delays); + + verify_delta_delays(delta_delays); + + return delta_delays; +} + +//Finds a src_rr and sink_rr appropriate for measuring the delay of the current direct specification +bool find_direct_connect_sample_locations(const t_direct_inf* direct, + t_physical_tile_type_ptr from_type, + int from_pin, + int from_pin_class, + t_physical_tile_type_ptr to_type, + int to_pin, + int to_pin_class, + RRNodeId& out_src_node, + RRNodeId& out_sink_node) { + VTR_ASSERT(from_type != nullptr); + VTR_ASSERT(to_type != nullptr); + + auto& device_ctx = g_vpr_ctx.device(); + auto& grid = device_ctx.grid; + const auto& node_lookup = device_ctx.rr_graph.node_lookup(); + + //Search the grid for an instance of from/to blocks which satisfy this direct connect offsets, + //and which has the appropriate pins + int from_x = -1; + int from_y = -1; + int from_sub_tile = -1; + int to_x = 0, to_y = 0, to_sub_tile = 0; + bool found = false; + int found_layer_num = -1; + //TODO: Function *FOR NOW* assumes that from/to blocks are at same die and have a same layer nums + for (int layer_num = 0; layer_num < grid.get_num_layers() && !found; ++layer_num) { + for (int x = 0; x < (int)grid.width() && !found; ++x) { + to_x = x + direct->x_offset; + if (to_x < 0 || to_x >= (int)grid.width()) continue; + + for (int y = 0; y < (int)grid.height() && !found; ++y) { + if (grid.get_physical_type({x, y, layer_num}) != from_type) continue; + + //Check that the from pin exists at this from location + //(with multi-width/height blocks pins may not exist at all locations) + bool from_pin_found = false; + if (direct->from_side != NUM_2D_SIDES) { + RRNodeId from_pin_rr = node_lookup.find_node(layer_num, x, y, OPIN, from_pin, direct->from_side); + from_pin_found = from_pin_rr.is_valid(); + } else { + from_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, x, y, OPIN, from_pin).empty()); + } + if (!from_pin_found) continue; + + to_y = y + direct->y_offset; + + if (to_y < 0 || to_y >= (int)grid.height()) continue; + if (grid.get_physical_type({to_x, to_y, layer_num}) != to_type) continue; + + //Check that the from pin exists at this from location + //(with multi-width/height blocks pins may not exist at all locations) + bool to_pin_found = false; + if (direct->to_side != NUM_2D_SIDES) { + RRNodeId to_pin_rr = node_lookup.find_node(layer_num, to_x, to_y, IPIN, to_pin, direct->to_side); + to_pin_found = (to_pin_rr != RRNodeId::INVALID()); + } else { + to_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, to_x, to_y, IPIN, to_pin).empty()); + } + if (!to_pin_found) continue; + + for (int sub_tile_num = 0; sub_tile_num < from_type->capacity; ++sub_tile_num) { + to_sub_tile = sub_tile_num + direct->sub_tile_offset; + + if (to_sub_tile < 0 || to_sub_tile >= to_type->capacity) continue; + + found = true; + found_layer_num = layer_num; + from_x = x; + from_y = y; + from_sub_tile = sub_tile_num; + + break; + } + } + } + } + + if (!found) { + return false; + } + + //Now have a legal instance of this direct connect + VTR_ASSERT(grid.get_physical_type({from_x, from_y, found_layer_num}) == from_type); + VTR_ASSERT(from_sub_tile < from_type->capacity); + + VTR_ASSERT(grid.get_physical_type({to_x, to_y, found_layer_num}) == to_type); + VTR_ASSERT(to_sub_tile < to_type->capacity); + + VTR_ASSERT(from_x + direct->x_offset == to_x); + VTR_ASSERT(from_y + direct->y_offset == to_y); + VTR_ASSERT(from_sub_tile + direct->sub_tile_offset == to_sub_tile); + + // Find a source/sink RR node associated with the pins of the direct + { + RRNodeId src_rr_candidate = node_lookup.find_node(found_layer_num, from_x, from_y, SOURCE, from_pin_class); + VTR_ASSERT(src_rr_candidate); + out_src_node = src_rr_candidate; + } + + { + RRNodeId sink_rr_candidate = node_lookup.find_node(found_layer_num, to_x, to_y, SINK, to_pin_class); + VTR_ASSERT(sink_rr_candidate); + out_sink_node = sink_rr_candidate; + } + + return true; +} + +std::vector get_best_classes(enum e_pin_type pintype, t_physical_tile_type_ptr type) { + std::vector best_classes; + + //Record any non-zero Fc pins + // + //Note that we track non-zero Fc pins, since certain Fc overrides + //may apply to only a subset of wire types. This ensures we record + //which pins can potentially connect to global routing. + std::unordered_set non_zero_fc_pins; + for (const t_fc_specification& fc_spec : type->fc_specs) { + if (fc_spec.fc_value == 0) continue; + + non_zero_fc_pins.insert(fc_spec.pins.begin(), fc_spec.pins.end()); + } + + // Collect all classes of matching type which connect to general routing + for (int i = 0; i < (int)type->class_inf.size(); i++) { + if (type->class_inf[i].type == pintype) { + //Check whether all pins in this class are ignored or have zero fc + bool any_pins_connect_to_general_routing = false; + for (int ipin = 0; ipin < type->class_inf[i].num_pins; ++ipin) { + int pin = type->class_inf[i].pinlist[ipin]; + //If the pin isn't ignored, and has a non-zero Fc to some general + //routing the class is suitable for delay profiling + if (!type->is_ignored_pin[pin] && non_zero_fc_pins.count(pin)) { + any_pins_connect_to_general_routing = true; + break; + } + } + + // Skip if the pin class doesn't connect to general routing + if (!any_pins_connect_to_general_routing) continue; + + // Record candidate class + best_classes.push_back(i); + } + } + + // Sort classes so the largest pin class is first + auto cmp_class = [&](int lhs, int rhs) { + return type->class_inf[lhs].num_pins > type->class_inf[rhs].num_pins; + }; + + std::stable_sort(best_classes.begin(), best_classes.end(), cmp_class); + + return best_classes; +} diff --git a/vpr/src/place/delay_model/compute_delta_delays_utils.h b/vpr/src/place/delay_model/compute_delta_delays_utils.h new file mode 100644 index 00000000000..d51c41cf18f --- /dev/null +++ b/vpr/src/place/delay_model/compute_delta_delays_utils.h @@ -0,0 +1,56 @@ + +#pragma once + +#include "vtr_ndmatrix.h" +#include "physical_types.h" +#include "rr_graph_fwd.h" + +struct t_placer_opts; +struct t_router_opts; +class RouterDelayProfiler; + +vtr::NdMatrix compute_delta_delay_model(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + bool measure_directconnect, + int longest_length, + bool is_flat); + +bool find_direct_connect_sample_locations(const t_direct_inf* direct, + t_physical_tile_type_ptr from_type, + int from_pin, + int from_pin_class, + t_physical_tile_type_ptr to_type, + int to_pin, + int to_pin_class, + RRNodeId& out_src_node, + RRNodeId& out_sink_node); + +/** + * @brief Identifies the best pin classes for delay calculation based on pin count and connectivity. + * + * This function selects pin classes of a specified type (`pintype`) from a physical tile type (`type`) + * that are suitable for delay calculations. It prioritizes pin classes with the largest number of pins + * that connect to general routing, ensuring commonly used pins are chosen for delay profiling. + * + * @param pintype The type of pins to filter. + * @param type Pointer to the physical tile type containing pin and class information. + * + * @return A vector of indices representing the selected pin classes. The classes are sorted + * in descending order based on the number of pins they contain. + * + * @details + * - A pin class is eligible if its type matches `pintype` and it contains at least one pin + * that connects to general routing (non-zero Fc). + * - Non-zero Fc pins are determined by inspecting the tile's `fc_specs`. + * - Classes are sorted so that the class with the largest number of pins appears first. + * If multiple classes have the same pin count, their order depends on their initial appearance + * in the architecture file. + * + * @note + * - Pins explicitly marked as ignored in `type->is_ignored_pin` are excluded. + * - The function ensures stability in sorting, preserving the input order for classes + * with the same number of pins. + */ + +std::vector get_best_classes(enum e_pin_type pintype, t_physical_tile_type_ptr type); diff --git a/vpr/src/place/delay_model/delta_delay_model.cpp b/vpr/src/place/delay_model/delta_delay_model.cpp new file mode 100644 index 00000000000..508787b6d69 --- /dev/null +++ b/vpr/src/place/delay_model/delta_delay_model.cpp @@ -0,0 +1,136 @@ + +#include "delta_delay_model.h" + +#include "compute_delta_delays_utils.h" + +#ifdef VTR_ENABLE_CAPNPROTO +#include "capnp/serialize.h" +#include "place_delay_model.capnp.h" +#include "ndmatrix_serdes.h" +#include "mmap_file.h" +#include "serdes_utils.h" +#endif // VTR_ENABLE_CAPNPROTO + +void DeltaDelayModel::compute(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + int longest_length) { + delays_ = compute_delta_delay_model(route_profiler, + placer_opts, + router_opts, + /*measure_directconnect=*/true, + longest_length, + is_flat_); +} + +float DeltaDelayModel::delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const { + int delta_x = std::abs(from_loc.x - to_loc.x); + int delta_y = std::abs(from_loc.y - to_loc.y); + + return delays_[from_loc.layer_num][to_loc.layer_num][delta_x][delta_y]; +} + +void DeltaDelayModel::dump_echo(std::string filepath) const { + FILE* f = vtr::fopen(filepath.c_str(), "w"); + fprintf(f, " "); + for (size_t from_layer_num = 0; from_layer_num < delays_.dim_size(0); ++from_layer_num) { + for (size_t to_layer_num = 0; to_layer_num < delays_.dim_size(1); ++to_layer_num) { + fprintf(f, " %9zu", from_layer_num); + fprintf(f, "\n"); + for (size_t dx = 0; dx < delays_.dim_size(2); ++dx) { + fprintf(f, " %9zu", dx); + } + fprintf(f, "\n"); + for (size_t dy = 0; dy < delays_.dim_size(3); ++dy) { + fprintf(f, "%9zu", dy); + for (size_t dx = 0; dx < delays_.dim_size(2); ++dx) { + fprintf(f, " %9.2e", delays_[from_layer_num][to_layer_num][dx][dy]); + } + fprintf(f, "\n"); + } + } + } + vtr::fclose(f); +} + +void DeltaDelayModel::read(const std::string& file) { +#ifndef VTR_ENABLE_CAPNPROTO + (void)file; + VPR_THROW(VPR_ERROR_PLACE, + "OverrideDelayModel::read is disabled because VTR_ENABLE_CAPNPROTO=OFF. " + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable."); +#else + + // MmapFile object creates an mmap of the specified path, and will munmap + // when the object leaves scope. + MmapFile f(file); + + /* Increase reader limit to 1G words to allow for large files. */ + ::capnp::ReaderOptions opts = default_large_capnp_opts(); + + // FlatArrayMessageReader is used to read the message from the data array + // provided by MmapFile. + ::capnp::FlatArrayMessageReader reader(f.getData(), opts); + + // When reading capnproto files the Reader object to use is named + // ::Reader. + // + // Initially this object is an empty VprDeltaDelayModel. + VprDeltaDelayModel::Reader model; + + // The reader.getRoot performs a cast from the generic capnproto to fit + // with the specified schema. + // + // Note that capnproto does not validate that the incoming data matches the + // schema. If this property is required, some form of check would be + // required. + model = reader.getRoot(); + + auto toFloat = [](float* out, const VprFloatEntry::Reader& in) -> void { + *out = in.getValue(); + }; + + // ToNdMatrix is a generic function for converting a Matrix capnproto + // to a vtr::NdMatrix. + // + // The user must supply the matrix dimension (2 in this case), the source + // capnproto type (VprFloatEntry), + // target C++ type (flat), and a function to convert from the source capnproto + // type to the target C++ type (ToFloat). + // + // The second argument should be of type Matrix::Reader where X is the + // capnproto element type. + ToNdMatrix<4, VprFloatEntry, float>(&delays_, model.getDelays(), toFloat); +#endif +} + +void DeltaDelayModel::write(const std::string& file) const { +#ifndef VTR_ENABLE_CAPNPROTO + (void)file; + VPR_THROW(VPR_ERROR_PLACE, + "DeltaDelayModel::write is disabled because VTR_ENABLE_CAPNPROTO=OFF. " + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable."); +#else + + // MallocMessageBuilder object is the generate capnproto message builder, + // using malloc for buffer allocation. + ::capnp::MallocMessageBuilder builder; + + // initRoot returns a X::Builder object that can be used to set the + // fields in the message. + auto model = builder.initRoot(); + + auto fromFloat = [](VprFloatEntry::Builder* out, const float& in) -> void { + out->setValue(in); + }; + + // FromNdMatrix is a generic function for converting a vtr::NdMatrix to a + // Matrix message. It is the mirror function of ToNdMatrix described in + // read above. + auto delay_values = model.getDelays(); + FromNdMatrix<4, VprFloatEntry, float>(&delay_values, delays_, fromFloat); + + // writeMessageToFile writes message to the specified file. + writeMessageToFile(file, &builder); +#endif +} diff --git a/vpr/src/place/delay_model/delta_delay_model.h b/vpr/src/place/delay_model/delta_delay_model.h new file mode 100644 index 00000000000..a4c548210ae --- /dev/null +++ b/vpr/src/place/delay_model/delta_delay_model.h @@ -0,0 +1,47 @@ + +#pragma once + +#include "place_delay_model.h" + +/** + * @class DeltaDelayModel + * + * @brief A simple delay model based on the distance (delta) between block locations. + */ +class DeltaDelayModel : public PlaceDelayModel { + public: + DeltaDelayModel(float min_cross_layer_delay, + bool is_flat) + : cross_layer_delay_(min_cross_layer_delay) + , is_flat_(is_flat) {} + + DeltaDelayModel(float min_cross_layer_delay, + vtr::NdMatrix delta_delays, + bool is_flat) + : delays_(std::move(delta_delays)) + , cross_layer_delay_(min_cross_layer_delay) + , is_flat_(is_flat) {} + + void compute(RouterDelayProfiler& router, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + int longest_length) override; + + float delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const override; + + void dump_echo(std::string filepath) const override; + + void read(const std::string& file) override; + void write(const std::string& file) const override; + + const vtr::NdMatrix& delays() const { + return delays_; + } + + private: + vtr::NdMatrix delays_; // [0..num_layers-1][0..max_dx][0..max_dy] + float cross_layer_delay_; + + /// Indicates whether the router is a two-stage or run-flat + bool is_flat_; +}; diff --git a/vpr/src/place/delay_model/override_delay_model.cpp b/vpr/src/place/delay_model/override_delay_model.cpp new file mode 100644 index 00000000000..a3d99c73c9d --- /dev/null +++ b/vpr/src/place/delay_model/override_delay_model.cpp @@ -0,0 +1,282 @@ + +#include "override_delay_model.h" + +#include "compute_delta_delays_utils.h" +#include "physical_types_util.h" + +#ifdef VTR_ENABLE_CAPNPROTO +#include "capnp/serialize.h" +#include "place_delay_model.capnp.h" +#include "ndmatrix_serdes.h" +#include "mmap_file.h" +#include "serdes_utils.h" +#endif // VTR_ENABLE_CAPNPROTO + +void OverrideDelayModel::compute(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + int longest_length) { + auto delays = compute_delta_delay_model(route_profiler, + placer_opts, + router_opts, + /*measure_directconnect=*/false, + longest_length, + is_flat_); + + base_delay_model_ = std::make_unique(cross_layer_delay_, delays, false); + + compute_override_delay_model_(route_profiler, router_opts); +} + +void OverrideDelayModel::compute_override_delay_model_(RouterDelayProfiler& route_profiler, + const t_router_opts& router_opts) { + const auto& device_ctx = g_vpr_ctx.device(); + t_router_opts router_opts2 = router_opts; + router_opts2.astar_fac = 0.f; + router_opts2.astar_offset = 0.f; + + // Look at all the direct connections that exist, and add overrides to delay model + for (int idirect = 0; idirect < (int)device_ctx.arch->directs.size(); ++idirect) { + const t_direct_inf* direct = &device_ctx.arch->directs[idirect]; + + InstPort from_port = parse_inst_port(direct->from_pin); + InstPort to_port = parse_inst_port(direct->to_pin); + + t_physical_tile_type_ptr from_type = find_tile_type_by_name(from_port.instance_name(), device_ctx.physical_tile_types); + t_physical_tile_type_ptr to_type = find_tile_type_by_name(to_port.instance_name(), device_ctx.physical_tile_types); + + int num_conns = from_port.port_high_index() - from_port.port_low_index() + 1; + VTR_ASSERT_MSG(num_conns == to_port.port_high_index() - to_port.port_low_index() + 1, "Directs must have the same size to/from"); + + //We now walk through all the connections associated with the current direct specification, measure + //their delay and specify that value as an override in the delay model. + // + //Note that we need to check every connection in the direct to cover the case where the pins are not + //equivalent. + // + //However, if the from/to ports are equivalent we could end up sampling the same RR SOURCE/SINK + //paths multiple times (wasting CPU time) -- we avoid this by recording the sampled paths in + //sampled_rr_pairs and skipping them if they occur multiple times. + int missing_instances = 0; + int missing_paths = 0; + std::set> sampled_rr_pairs; + for (int iconn = 0; iconn < num_conns; ++iconn) { + //Find the associated pins + int from_pin = from_type->find_pin(from_port.port_name(), from_port.port_low_index() + iconn); + int to_pin = to_type->find_pin(to_port.port_name(), to_port.port_low_index() + iconn); + + VTR_ASSERT(from_pin != OPEN); + VTR_ASSERT(to_pin != OPEN); + + int from_pin_class = from_type->find_pin_class(from_port.port_name(), from_port.port_low_index() + iconn, DRIVER); + VTR_ASSERT(from_pin_class != OPEN); + + int to_pin_class = to_type->find_pin_class(to_port.port_name(), to_port.port_low_index() + iconn, RECEIVER); + VTR_ASSERT(to_pin_class != OPEN); + + bool found_sample_points; + RRNodeId src_rr, sink_rr; + found_sample_points = find_direct_connect_sample_locations(direct, from_type, from_pin, from_pin_class, to_type, to_pin, to_pin_class, src_rr, sink_rr); + + if (!found_sample_points) { + ++missing_instances; + continue; + } + + //If some of the source/sink ports are logically equivalent we may have already + //sampled the associated source/sink pair and don't need to do so again + if (sampled_rr_pairs.count({src_rr, sink_rr})) continue; + + float direct_connect_delay = std::numeric_limits::quiet_NaN(); + bool found_routing_path = route_profiler.calculate_delay(src_rr, sink_rr, router_opts2, &direct_connect_delay); + + if (found_routing_path) { + set_delay_override(from_type->index, from_pin_class, to_type->index, to_pin_class, direct->x_offset, direct->y_offset, direct_connect_delay); + } else { + ++missing_paths; + } + + //Record that we've sampled this pair of source and sink nodes + sampled_rr_pairs.insert({src_rr, sink_rr}); + } + + VTR_LOGV_WARN(missing_instances > 0, "Found no delta delay for %d bits of inter-block direct connect '%s' (no instances of this direct found)\n", missing_instances, direct->name.c_str()); + VTR_LOGV_WARN(missing_paths > 0, "Found no delta delay for %d bits of inter-block direct connect '%s' (no routing path found)\n", missing_paths, direct->name.c_str()); + } +} + +const DeltaDelayModel* OverrideDelayModel::base_delay_model() const { + return base_delay_model_.get(); +} + +float OverrideDelayModel::delay(const t_physical_tile_loc& from_loc, int from_pin, const t_physical_tile_loc& to_loc, int to_pin) const { + // First check to if there is an override delay value + const auto& device_ctx = g_vpr_ctx.device(); + const auto& grid = device_ctx.grid; + + t_physical_tile_type_ptr from_type_ptr = grid.get_physical_type(from_loc); + t_physical_tile_type_ptr to_type_ptr = grid.get_physical_type(to_loc); + + t_override override_key; + override_key.from_type = from_type_ptr->index; + override_key.from_class = from_type_ptr->pin_class[from_pin]; + override_key.to_type = to_type_ptr->index; + override_key.to_class = to_type_ptr->pin_class[to_pin]; + + //Delay overrides may be different for +/- delta so do not use + //an absolute delta for the look-up + override_key.delta_x = to_loc.x - from_loc.x; + override_key.delta_y = to_loc.y - from_loc.y; + + float delay_val = std::numeric_limits::quiet_NaN(); + auto override_iter = delay_overrides_.find(override_key); + if (override_iter != delay_overrides_.end()) { + //Found an override + delay_val = override_iter->second; + } else { + //Fall back to the base delay model if no override was found + delay_val = base_delay_model_->delay(from_loc, from_pin, to_loc, to_pin); + } + + return delay_val; +} + +void OverrideDelayModel::set_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y, float delay_val) { + t_override override_key; + override_key.from_type = from_type; + override_key.from_class = from_class; + override_key.to_type = to_type; + override_key.to_class = to_class; + override_key.delta_x = delta_x; + override_key.delta_y = delta_y; + + auto res = delay_overrides_.insert(std::make_pair(override_key, delay_val)); + if (!res.second) { //Key already exists + res.first->second = delay_val; //Overwrite existing delay + } +} + +void OverrideDelayModel::dump_echo(std::string filepath) const { + base_delay_model_->dump_echo(filepath); + + FILE* f = vtr::fopen(filepath.c_str(), "a"); + + fprintf(f, "\n"); + fprintf(f, "# Delay Overrides\n"); + auto& device_ctx = g_vpr_ctx.device(); + for (auto kv : delay_overrides_) { + auto override_key = kv.first; + float delay_val = kv.second; + fprintf(f, "from_type: %s to_type: %s from_pin_class: %d to_pin_class: %d delta_x: %d delta_y: %d -> delay: %g\n", + device_ctx.physical_tile_types[override_key.from_type].name.c_str(), + device_ctx.physical_tile_types[override_key.to_type].name.c_str(), + override_key.from_class, + override_key.to_class, + override_key.delta_x, + override_key.delta_y, + delay_val); + } + + vtr::fclose(f); +} + +float OverrideDelayModel::get_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y) const { + t_override key; + key.from_type = from_type; + key.from_class = from_class; + key.to_type = to_type; + key.to_class = to_class; + key.delta_x = delta_x; + key.delta_y = delta_y; + + auto iter = delay_overrides_.find(key); + if (iter == delay_overrides_.end()) { + VPR_THROW(VPR_ERROR_PLACE, "Key not found."); + } + return iter->second; +} + +void OverrideDelayModel::set_base_delay_model(std::unique_ptr base_delay_model_obj) { + base_delay_model_ = std::move(base_delay_model_obj); +} + +void OverrideDelayModel::read(const std::string& file) { +#ifndef VTR_ENABLE_CAPNPROTO + (void)file; + VPR_THROW(VPR_ERROR_PLACE, + "OverrideDelayModel::read is disabled because VTR_ENABLE_CAPNPROTO=OFF. " + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable."); +#else + MmapFile f(file); + + /* Increase reader limit to 1G words to allow for large files. */ + ::capnp::ReaderOptions opts = default_large_capnp_opts(); + ::capnp::FlatArrayMessageReader reader(f.getData(), opts); + + auto toFloat = [](float* out, const VprFloatEntry::Reader& in) -> void { + *out = in.getValue(); + }; + + vtr::NdMatrix delays; + auto model = reader.getRoot(); + ToNdMatrix<4, VprFloatEntry, float>(&delays, model.getDelays(), toFloat); + + base_delay_model_ = std::make_unique(cross_layer_delay_, delays, is_flat_); + + // Reading non-scalar capnproto fields is roughly equivalent to using + // a std::vector of the field type. Actual type is capnp::List::Reader. + auto overrides = model.getDelayOverrides(); + std::vector> overrides_arr(overrides.size()); + for (size_t i = 0; i < overrides.size(); ++i) { + const auto& elem = overrides[i]; + overrides_arr[i].first.from_type = elem.getFromType(); + overrides_arr[i].first.to_type = elem.getToType(); + overrides_arr[i].first.from_class = elem.getFromClass(); + overrides_arr[i].first.to_class = elem.getToClass(); + overrides_arr[i].first.delta_x = elem.getDeltaX(); + overrides_arr[i].first.delta_y = elem.getDeltaY(); + + overrides_arr[i].second = elem.getDelay(); + } + + delay_overrides_ = vtr::make_flat_map2(std::move(overrides_arr)); +#endif +} + +void OverrideDelayModel::write(const std::string& file) const { +#ifndef VTR_ENABLE_CAPNPROTO + (void)file; + VPR_THROW(VPR_ERROR_PLACE, + "OverrideDelayModel::write is disabled because VTR_ENABLE_CAPNPROTO=OFF. " + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable."); +#else + ::capnp::MallocMessageBuilder builder; + auto model = builder.initRoot(); + + auto fromFloat = [](VprFloatEntry::Builder* out, const float& in) -> void { + out->setValue(in); + }; + + auto delays = model.getDelays(); + FromNdMatrix<4, VprFloatEntry, float>(&delays, base_delay_model_->delays(), fromFloat); + + // Non-scalar capnproto fields should be first initialized with + // init(count), and then accessed from the returned + // std::vector-like Builder object (specifically capnp::List::Builder). + auto overrides = model.initDelayOverrides(delay_overrides_.size()); + auto dst_iter = overrides.begin(); + for (const auto& src : delay_overrides_) { + auto elem = *dst_iter++; + elem.setFromType(src.first.from_type); + elem.setToType(src.first.to_type); + elem.setFromClass(src.first.from_class); + elem.setToClass(src.first.to_class); + elem.setDeltaX(src.first.delta_x); + elem.setDeltaY(src.first.delta_y); + + elem.setDelay(src.second); + } + + writeMessageToFile(file, &builder); +#endif +} diff --git a/vpr/src/place/delay_model/override_delay_model.h b/vpr/src/place/delay_model/override_delay_model.h new file mode 100644 index 00000000000..e7d71c72318 --- /dev/null +++ b/vpr/src/place/delay_model/override_delay_model.h @@ -0,0 +1,112 @@ + +#pragma once + +#include "place_delay_model.h" +#include "delta_delay_model.h" + +class OverrideDelayModel : public PlaceDelayModel { + public: + OverrideDelayModel(float min_cross_layer_delay, + bool is_flat) + : cross_layer_delay_(min_cross_layer_delay) + , is_flat_(is_flat) {} + + void compute(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + int longest_length) override; + + /** + * @brief returns delay from the specified (x,y) to the specified (x,y) with both endpoints on layer_num and the + * specified from and to pins + */ + float delay(const t_physical_tile_loc& from_loc, int from_pin, const t_physical_tile_loc& to_loc, int to_pin) const override; + + void dump_echo(std::string filepath) const override; + + void read(const std::string& file) override; + void write(const std::string& file) const override; + + public: //Mutators + void set_base_delay_model(std::unique_ptr base_delay_model); + const DeltaDelayModel* base_delay_model() const; + float get_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y) const; + void set_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y, float delay); + + private: + std::unique_ptr base_delay_model_; + /// Minimum delay of cross-layer connections + float cross_layer_delay_; + + /// Indicates whether the router is a two-stage or run-flat + bool is_flat_; + + void compute_override_delay_model_(RouterDelayProfiler& router, + const t_router_opts& router_opts); + + /** + * @brief Structure that allows delays to be queried from the delay model. + * + * Delay is calculated given the origin physical tile, the origin + * pin, the destination physical tile, and the destination pin. + * This structure encapsulates all these information. + * + * @param from_type, to_type + * Physical tile index (for easy array access) + * @param from_class, to_class + * The class that the pins belongs to. + * @param to_x, to_y + * The horizontal and vertical displacement + * between two physical tiles. + */ + struct t_override { + short from_type; + short to_type; + short from_class; + short to_class; + short delta_x; + short delta_y; + + /** + * @brief Comparison operator designed for performance. + * + * Operator< is important since t_override serves as the key into the + * map structure delay_overrides_. A default comparison operator would + * not be inlined by the compiler. + * + * A combination of ALWAYS_INLINE attribute and std::lexicographical_compare + * is required for operator< to be inlined by compiler. Proper inlining of + * the function reduces place time by around 5%. + * + * For more information: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1225 + */ + friend ALWAYS_INLINE bool operator<(const t_override& lhs, const t_override& rhs) { + const short* left = reinterpret_cast(&lhs); + const short* right = reinterpret_cast(&rhs); + constexpr size_t NUM_T_OVERRIDE_MEMBERS = sizeof(t_override) / sizeof(short); + return std::lexicographical_compare(left, left + NUM_T_OVERRIDE_MEMBERS, right, right + NUM_T_OVERRIDE_MEMBERS); + } + }; + + /** + * @brief Map data structure that returns delay values according to + * specific delay model queries. + * + * Delay model queries are provided by the t_override structure, which + * encapsulates the information regarding the origin and the destination. + */ + vtr::flat_map2 delay_overrides_; + + /** + * operator< treats memory layout of t_override as an array of short. + * This requires all members of t_override are shorts and there is no + * padding between members of t_override. + */ + static_assert(sizeof(t_override) == sizeof(t_override::from_type) + sizeof(t_override::to_type) + sizeof(t_override::from_class) + sizeof(t_override::to_class) + sizeof(t_override::delta_x) + sizeof(t_override::delta_y), "Expect t_override to have a memory layout equivalent to an array of short (no padding)"); + static_assert(sizeof(t_override::from_type) == sizeof(short), "Expect all t_override data members to be shorts"); + static_assert(sizeof(t_override::to_type) == sizeof(short), "Expect all t_override data members to be shorts"); + static_assert(sizeof(t_override::from_class) == sizeof(short), "Expect all t_override data members to be shorts"); + static_assert(sizeof(t_override::to_class) == sizeof(short), "Expect all t_override data members to be shorts"); + static_assert(sizeof(t_override::delta_x) == sizeof(short), "Expect all t_override data members to be shorts"); + static_assert(sizeof(t_override::delta_y) == sizeof(short), "Expect all t_override data members to be shorts"); +}; diff --git a/vpr/src/place/delay_model/place_delay_model.cpp b/vpr/src/place/delay_model/place_delay_model.cpp new file mode 100644 index 00000000000..6ff7ad3a0cf --- /dev/null +++ b/vpr/src/place/delay_model/place_delay_model.cpp @@ -0,0 +1,78 @@ +/** + * @file place_delay_model.cpp + * @brief This file implements all the class methods and individual + * routines related to the placer delay model. + */ + +#include "place_delay_model.h" + +#include "globals.h" +#include "physical_types_util.h" +#include "placer_state.h" +#include "vpr_error.h" + +/** + * @brief Returns the delay of one point to point connection. + * + * Only estimate delay for signals routed through the inter-block routing network. + * TODO: Do how should we compute the delay for globals. "Global signals are assumed to have zero delay." + */ +float comp_td_single_connection_delay(const PlaceDelayModel* delay_model, + const vtr::vector_map& block_locs, + ClusterNetId net_id, + int ipin) { + const auto& cluster_ctx = g_vpr_ctx.clustering(); + + float delay_source_to_sink = 0.; + + if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { + ClusterPinId source_pin = cluster_ctx.clb_nlist.net_driver(net_id); + ClusterPinId sink_pin = cluster_ctx.clb_nlist.net_pin(net_id, ipin); + + ClusterBlockId source_block = cluster_ctx.clb_nlist.pin_block(source_pin); + ClusterBlockId sink_block = cluster_ctx.clb_nlist.pin_block(sink_pin); + + int source_block_ipin = cluster_ctx.clb_nlist.pin_logical_index(source_pin); + int sink_block_ipin = cluster_ctx.clb_nlist.pin_logical_index(sink_pin); + + t_pl_loc source_block_loc = block_locs[source_block].loc; + t_pl_loc sink_block_loc = block_locs[sink_block].loc; + + /** + * This heuristic only considers delta_x and delta_y, a much better + * heuristic would be to to create a more comprehensive lookup table. + * + * In particular this approach does not accurately capture the effect + * of fast carry-chain connections. + */ + delay_source_to_sink = delay_model->delay({source_block_loc.x, source_block_loc.y, source_block_loc.layer}, source_block_ipin, + {sink_block_loc.x, sink_block_loc.y, sink_block_loc.layer}, sink_block_ipin); + if (delay_source_to_sink < 0) { + VPR_ERROR(VPR_ERROR_PLACE, + "in comp_td_single_connection_delay: Bad delay_source_to_sink value %g from %s (at %d,%d,%d) to %s (at %d,%d,%d)\n" + "in comp_td_single_connection_delay: Delay is less than 0\n", + block_type_pin_index_to_name(physical_tile_type(source_block_loc), source_block_ipin, false).c_str(), + source_block_loc.x, source_block_loc.y, source_block_loc.layer, + block_type_pin_index_to_name(physical_tile_type(sink_block_loc), sink_block_ipin, false).c_str(), + sink_block_loc.x, sink_block_loc.y, sink_block_loc.layer, + delay_source_to_sink); + } + } + + return (delay_source_to_sink); +} + +///@brief Recompute all point to point delays, updating `connection_delay` matrix. +void comp_td_connection_delays(const PlaceDelayModel* delay_model, + PlacerState& placer_state) { + const auto& cluster_ctx = g_vpr_ctx.clustering(); + auto& p_timing_ctx = placer_state.mutable_timing(); + auto& block_locs = placer_state.block_locs(); + auto& connection_delay = p_timing_ctx.connection_delay; + + for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { + for (size_t ipin = 1; ipin < cluster_ctx.clb_nlist.net_pins(net_id).size(); ++ipin) { + connection_delay[net_id][ipin] = comp_td_single_connection_delay(delay_model, block_locs, net_id, ipin); + } + } +} diff --git a/vpr/src/place/delay_model/place_delay_model.h b/vpr/src/place/delay_model/place_delay_model.h new file mode 100644 index 00000000000..ba22125d712 --- /dev/null +++ b/vpr/src/place/delay_model/place_delay_model.h @@ -0,0 +1,76 @@ +/** + * @file place_delay_model.h + * @brief This file contains all the class and function declarations related to + * the placer delay model. For implementations, see place_delay_model.cpp. + */ + +#pragma once + +#include "vtr_ndmatrix.h" +#include "vtr_flat_map.h" +#include "vpr_types.h" +#include "router_delay_profiling.h" + +#ifndef __has_attribute +#define __has_attribute(x) 0 // Compatibility with non-clang compilers. +#endif + +#if defined(COMPILER_GCC) && defined(NDEBUG) +#define ALWAYS_INLINE inline __attribute__((__always_inline__)) +#elif defined(COMPILER_MSVC) && defined(NDEBUG) +#define ALWAYS_INLINE __forceinline +#elif __has_attribute(always_inline) +#define ALWAYS_INLINE __attribute__((always_inline)) // clang +#else +#define ALWAYS_INLINE inline +#endif + +///@brief Forward declarations. +class PlaceDelayModel; +class PlacerState; + +///@brief Returns the delay of one point to point connection. +float comp_td_single_connection_delay(const PlaceDelayModel* delay_model, + const vtr::vector_map& block_locs, + ClusterNetId net_id, + int ipin); + +///@brief Recompute all point to point delays, updating `connection_delay` matrix. +void comp_td_connection_delays(const PlaceDelayModel* delay_model, + PlacerState& placer_state); + +///@brief Abstract interface to a placement delay model. +class PlaceDelayModel { + public: + virtual ~PlaceDelayModel() = default; + + ///@brief Computes place delay model. + virtual void compute(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + int longest_length) = 0; + + /** + * @brief Returns the delay estimate between the specified block pins. + * + * Either compute or read methods must be invoked before invoking delay. + */ + virtual float delay(const t_physical_tile_loc& from_loc, int from_pin, const t_physical_tile_loc& to_loc, int to_pin) const = 0; + + ///@brief Dumps the delay model to an echo file. + virtual void dump_echo(std::string filename) const = 0; + + /** + * @brief Write place delay model to specified file. + * + * May be unimplemented, in which case method should throw an exception. + */ + virtual void write(const std::string& file) const = 0; + + /** + * @brief Read place delay model from specified file. + * + * May be unimplemented, in which case method should throw an exception. + */ + virtual void read(const std::string& file) = 0; +}; diff --git a/vpr/src/place/delay_model/simple_delay_model.cpp b/vpr/src/place/delay_model/simple_delay_model.cpp new file mode 100644 index 00000000000..04d94b0fbac --- /dev/null +++ b/vpr/src/place/delay_model/simple_delay_model.cpp @@ -0,0 +1,132 @@ + +#include "simple_delay_model.h" + +#ifdef VTR_ENABLE_CAPNPROTO +#include "capnp/serialize.h" +#include "place_delay_model.capnp.h" +#include "ndmatrix_serdes.h" +#include "mmap_file.h" +#include "serdes_utils.h" +#endif // VTR_ENABLE_CAPNPROTO + +void SimpleDelayModel::compute(RouterDelayProfiler& route_profiler, + const t_placer_opts& /*placer_opts*/, + const t_router_opts& /*router_opts*/, + int /*longest_length*/) { + const auto& grid = g_vpr_ctx.device().grid; + const size_t num_physical_tile_types = g_vpr_ctx.device().physical_tile_types.size(); + const size_t num_layers = grid.get_num_layers(); + + // Initializing the delay matrix to [num_physical_types][num_layers][num_layers][width][height] + // The second index related to the layer that the source location is on and the third index is for the sink layer + delays_ = vtr::NdMatrix({num_physical_tile_types, + num_layers, + num_layers, + grid.width(), + grid.height()}); + + for (size_t physical_tile_type_idx = 0; physical_tile_type_idx < num_physical_tile_types; ++physical_tile_type_idx) { + for (size_t from_layer = 0; from_layer < num_layers; ++from_layer) { + for (size_t to_layer = 0; to_layer < num_layers; ++to_layer) { + for (size_t dx = 0; dx < grid.width(); ++dx) { + for (size_t dy = 0; dy < grid.height(); ++dy) { + float min_delay = route_profiler.get_min_delay(physical_tile_type_idx, + from_layer, + to_layer, + dx, + dy); + delays_[physical_tile_type_idx][from_layer][to_layer][dx][dy] = min_delay; + } + } + } + } + } +} + +float SimpleDelayModel::delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const { + int delta_x = std::abs(from_loc.x - to_loc.x); + int delta_y = std::abs(from_loc.y - to_loc.y); + + int from_tile_idx = g_vpr_ctx.device().grid.get_physical_type(from_loc)->index; + return delays_[from_tile_idx][from_loc.layer_num][to_loc.layer_num][delta_x][delta_y]; +} + +void SimpleDelayModel::read(const std::string& file) { +#ifndef VTR_ENABLE_CAPNPROTO + (void)file; + VPR_THROW(VPR_ERROR_PLACE, + "SimpleDelayModel::read is disabled because VTR_ENABLE_CAPNPROTO=OFF. " + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable."); +#else + // MmapFile object creates an mmap of the specified path, and will munmap + // when the object leaves scope. + MmapFile f(file); + + /* Increase reader limit to 1G words to allow for large files. */ + ::capnp::ReaderOptions opts = default_large_capnp_opts(); + + // FlatArrayMessageReader is used to read the message from the data array + // provided by MmapFile. + ::capnp::FlatArrayMessageReader reader(f.getData(), opts); + + // When reading capnproto files the Reader object to use is named + // ::Reader. + // + // Initially this object is an empty VprDeltaDelayModel. + VprDeltaDelayModel::Reader model; + + // The reader.getRoot performs a cast from the generic capnproto to fit + // with the specified schema. + // + // Note that capnproto does not validate that the incoming data matches the + // schema. If this property is required, some form of check would be + // required. + model = reader.getRoot(); + + auto toFloat = [](float* out, const VprFloatEntry::Reader& in) -> void { + *out = in.getValue(); + }; + + // ToNdMatrix is a generic function for converting a Matrix capnproto + // to a vtr::NdMatrix. + // + // The user must supply the matrix dimension (5 in this case), the source + // capnproto type (VprFloatEntry), + // target C++ type (flat), and a function to convert from the source capnproto + // type to the target C++ type (ToFloat). + // + // The second argument should be of type Matrix::Reader where X is the + // capnproto element type. + ToNdMatrix<5, VprFloatEntry, float>(&delays_, model.getDelays(), toFloat); +#endif +} + +void SimpleDelayModel::write(const std::string& file) const { +#ifndef VTR_ENABLE_CAPNPROTO + (void)file; + VPR_THROW(VPR_ERROR_PLACE, + "SimpleDelayModel::write is disabled because VTR_ENABLE_CAPNPROTO=OFF. " + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable."); +#else + // MallocMessageBuilder object generates capnproto message builder, + // using malloc for buffer allocation. + ::capnp::MallocMessageBuilder builder; + + // initRoot returns a X::Builder object that can be used to set the + // fields in the message. + auto model = builder.initRoot(); + + auto fromFloat = [](VprFloatEntry::Builder* out, const float& in) -> void { + out->setValue(in); + }; + + // FromNdMatrix is a generic function for converting a vtr::NdMatrix to a + // Matrix message. It is the mirror function of ToNdMatrix described in + // read above. + auto delay_values = model.getDelays(); + FromNdMatrix<5, VprFloatEntry, float>(&delay_values, delays_, fromFloat); + + // writeMessageToFile writes message to the specified file. + writeMessageToFile(file, &builder); +#endif +} diff --git a/vpr/src/place/delay_model/simple_delay_model.h b/vpr/src/place/delay_model/simple_delay_model.h new file mode 100644 index 00000000000..0a7ace6aece --- /dev/null +++ b/vpr/src/place/delay_model/simple_delay_model.h @@ -0,0 +1,39 @@ + +#pragma once + +#include "place_delay_model.h" + +/** + * @class SimpleDelayModel + * @brief A simple delay model based on the information stored in router lookahead + * This is in contrast to other placement delay models that get the cost of getting from one location to another by running the router + */ +class SimpleDelayModel : public PlaceDelayModel { + public: + SimpleDelayModel() {} + + /// @brief Use the information in the router lookahead to fill the delay matrix instead of running the router + void compute(RouterDelayProfiler& router, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + int longest_length) override; + + float delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const override; + + void dump_echo(std::string /*filepath*/) const override {} + + void read(const std::string& /*file*/) override; + void write(const std::string& /*file*/) const override; + + private: + /** + * @brief The matrix to store the minimum delay between different points on different layers. + * + *The matrix used to store delay information is a 5D matrix. This data structure stores the minimum delay for each tile type on each layer to other layers + *for each dx and dy. We decided to separate the delay for each physical type on each die to accommodate cases where the connectivity of a physical type differs + *on each layer. Additionally, instead of using d_layer, we distinguish between the destination layer to handle scenarios where connectivity between layers + *is not uniform. For example, if the number of inter-layer connections between layer 1 and 2 differs from the number of connections between layer 0 and 1. + *One might argue that this variability could also occur for dx and dy. However, we are operating under the assumption that the FPGA fabric architecture is regular. + */ + vtr::NdMatrix delays_; // [0..num_physical_type-1][0..num_layers-1][0..num_layers-1][0..max_dx][0..max_dy] +}; diff --git a/vpr/src/place/grid_tile_lookup.cpp b/vpr/src/place/grid_tile_lookup.cpp index d2236fdbc8a..45aad729647 100644 --- a/vpr/src/place/grid_tile_lookup.cpp +++ b/vpr/src/place/grid_tile_lookup.cpp @@ -1,12 +1,11 @@ #include "grid_tile_lookup.h" +#include "physical_types_util.h" -GridTileLookup::GridTileLookup() { +GridTileLookup::GridTileLookup() + : max_placement_locations(g_vpr_ctx.device().logical_block_types.size()) { const auto& device_ctx = g_vpr_ctx.device(); const int num_layers = device_ctx.grid.get_num_layers(); - //Will store the max number of tile locations for each logical block type - max_placement_locations.resize(device_ctx.logical_block_types.size()); - for (const auto& type : device_ctx.logical_block_types) { vtr::NdMatrix type_count({static_cast(num_layers), device_ctx.grid.width(), device_ctx.grid.height()}); fill_type_matrix(&type, type_count); @@ -85,7 +84,7 @@ int GridTileLookup::region_tile_count(const Region& reg, t_logical_block_type_pt 0, n_layers - 1); Region intersect_reg = intersection(reg, grid_reg); -// VTR_ASSERT(intersect_coord.layer_num == layer_num); + // VTR_ASSERT(intersect_coord.layer_num == layer_num); const auto [xmin, ymin, xmax, ymax] = intersect_reg.get_rect().coordinates(); const auto [layer_low, layer_high] = intersect_reg.get_layer_range(); diff --git a/vpr/src/place/grid_tile_lookup.h b/vpr/src/place/grid_tile_lookup.h index 66d9d372db3..b155bf99410 100644 --- a/vpr/src/place/grid_tile_lookup.h +++ b/vpr/src/place/grid_tile_lookup.h @@ -5,86 +5,86 @@ #include "globals.h" /** -* @class GridTileLookup -* @brief This class is used to store a grid for each logical block type that stores the cumulative number of subtiles -* for that type available at each location in the grid. -* -* The cumulative number of subtiles is the subtiles at the location plus the subtiles available at the grid locations -* above and to the right of the locations. Having these grids allows for O(1) lookups about the number of subtiles -* available for a given type of block in a rectangular region. -* This lookup class is used during initial placement when sorting blocks by the size of their floorplan constraint regions. -*/ + * @class GridTileLookup + * @brief This class is used to store a grid for each logical block type that stores the cumulative number of subtiles + * for that type available at each location in the grid. + * + * The cumulative number of subtiles is the subtiles at the location plus the subtiles available at the grid locations + * above and to the right of the locations. Having these grids allows for O(1) lookups about the number of subtiles + * available for a given type of block in a rectangular region. + * This lookup class is used during initial placement when sorting blocks by the size of their floorplan constraint regions. + */ class GridTileLookup { - public: - /** - * @brief Constructs a new GridTileLookup object. - * - * Creates a grid for each logical type and fills it with the cumulative number - * of subtiles of that type. - */ - GridTileLookup(); + public: + /** + * @brief Constructs a new GridTileLookup object. + * + * Creates a grid for each logical type and fills it with the cumulative number + * of subtiles of that type. + */ + GridTileLookup(); - /** - * @brief Returns the number of subtiles available in the specified region for the given block type. - * - * This routine uses pre-computed values from the grids for each block type to get the number of grid tiles - * covered by a region. - * For a region with no subtiles specified, the number of grid tiles can be calculated by adding - * and subtracting four values from within/at the edge of the region. - * The region with subtile case is taken care of by a helper routine, region_with_subtile_count(). - * - * @param reg The region to be queried. - * @param block_type The type of logical block. - * @return int The number of available subtiles. - */ - int region_tile_count(const Region& reg, t_logical_block_type_ptr block_type) const; + /** + * @brief Returns the number of subtiles available in the specified region for the given block type. + * + * This routine uses pre-computed values from the grids for each block type to get the number of grid tiles + * covered by a region. + * For a region with no subtiles specified, the number of grid tiles can be calculated by adding + * and subtracting four values from within/at the edge of the region. + * The region with subtile case is taken care of by a helper routine, region_with_subtile_count(). + * + * @param reg The region to be queried. + * @param block_type The type of logical block. + * @return int The number of available subtiles. + */ + int region_tile_count(const Region& reg, t_logical_block_type_ptr block_type) const; - /** - * @brief Returns the number of subtiles that can be placed in the specified region for the given block type. - * - * This routine is for the subtile specified case; an O(region_size) scan needs to be done to check whether each grid - * location in the region is compatible for the block at the subtile specified. - * - * @param reg The region to be queried. - * @param block_type The type of logical block. - * @return int The number of subtiles with placement. - */ - int region_with_subtile_count(const Region& reg, t_logical_block_type_ptr block_type) const; + /** + * @brief Returns the number of subtiles that can be placed in the specified region for the given block type. + * + * This routine is for the subtile specified case; an O(region_size) scan needs to be done to check whether each grid + * location in the region is compatible for the block at the subtile specified. + * + * @param reg The region to be queried. + * @param block_type The type of logical block. + * @return int The number of subtiles with placement. + */ + int region_with_subtile_count(const Region& reg, t_logical_block_type_ptr block_type) const; - /** - * @brief Returns the total number of tiles available for the specified block type. - * - * @param block_type The type of logical block. - * @return int The total number of available tiles. - */ - int total_type_tiles(t_logical_block_type_ptr block_type) const; + /** + * @brief Returns the total number of tiles available for the specified block type. + * + * @param block_type The type of logical block. + * @return int The total number of available tiles. + */ + int total_type_tiles(t_logical_block_type_ptr block_type) const; - private: - /** - * @brief Fills the type matrix with cumulative subtiles count for the given block type. - * - * @param block_type The type of logical block. - * @param type_count The matrix to be filled with cumulative subtiles count. - */ - void fill_type_matrix(t_logical_block_type_ptr block_type, vtr::NdMatrix& type_count); + private: + /** + * @brief Fills the type matrix with cumulative subtiles count for the given block type. + * + * @param block_type The type of logical block. + * @param type_count The matrix to be filled with cumulative subtiles count. + */ + void fill_type_matrix(t_logical_block_type_ptr block_type, vtr::NdMatrix& type_count); - /** - * @brief Stores the cumulative total of subtiles available at each (x, y) location in each layer - * for all block types. - * - * Therefore, the length of the vector will be the number of logical block types. To access the cumulative - * number of subtiles at a location in a specific layer, you would use block_type_matrices[iblock_type][layer][x][y]. - * This would give the number of placement locations that are at, or above (larger y) and to the right of the given [x,y] for - * the given block type in the given layer. - */ - std::vector> block_type_matrices; + /** + * @brief Stores the cumulative total of subtiles available at each (x, y) location in each layer + * for all block types. + * + * Therefore, the length of the vector will be the number of logical block types. To access the cumulative + * number of subtiles at a location in a specific layer, you would use block_type_matrices[iblock_type][layer][x][y]. + * This would give the number of placement locations that are at, or above (larger y) and to the right of the given [x,y] for + * the given block type in the given layer. + */ + std::vector> block_type_matrices; - /** - * @brief Stores the total number of placement locations (i.e. compatible subtiles) for each block type. - * - * To access the max_placement locations for a particular block type, use max_placement_locations[block_type->index] - */ - std::vector max_placement_locations; + /** + * @brief Stores the total number of placement locations (i.e. compatible subtiles) for each block type. + * + * To access the max_placement locations for a particular block type, use max_placement_locations[block_type->index] + */ + std::vector max_placement_locations; }; -#endif /* VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ */ \ No newline at end of file +#endif /* VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ */ diff --git a/vpr/src/place/initial_noc_placement.cpp b/vpr/src/place/initial_noc_placement.cpp index df1352c98ec..2c97ee4f788 100644 --- a/vpr/src/place/initial_noc_placement.cpp +++ b/vpr/src/place/initial_noc_placement.cpp @@ -1,6 +1,7 @@ #include "initial_noc_placment.h" +#include "place_macro.h" #include "vpr_types.h" #include "initial_placement.h" #include "noc_place_utils.h" @@ -66,6 +67,7 @@ static void place_noc_routers_randomly(std::vector& unfixed_rout */ static void noc_routers_anneal(const t_noc_opts& noc_opts, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, NocCostHandler& noc_cost_handler, vtr::RngContainer& rng); @@ -210,6 +212,7 @@ static void place_noc_routers_randomly(std::vector& unfixed_rout static void noc_routers_anneal(const t_noc_opts& noc_opts, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, NocCostHandler& noc_cost_handler, vtr::RngContainer& rng) { auto& noc_ctx = g_vpr_ctx.noc(); @@ -276,6 +279,7 @@ static void noc_routers_anneal(const t_noc_opts& noc_opts, e_create_move create_move_outcome = propose_router_swap(blocks_affected, r_lim_decayed, blk_loc_registry, + place_macros, rng); if (create_move_outcome != e_create_move::ABORT) { @@ -311,9 +315,10 @@ static void noc_routers_anneal(const t_noc_opts& noc_opts, void initial_noc_placement(const t_noc_opts& noc_opts, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, NocCostHandler& noc_cost_handler, vtr::RngContainer& rng) { - vtr::ScopedStartFinishTimer timer("Initial NoC Placement"); + vtr::ScopedStartFinishTimer timer("Initial NoC Placement"); auto& noc_ctx = g_vpr_ctx.noc(); const auto& block_locs = blk_loc_registry.block_locs(); @@ -343,7 +348,7 @@ void initial_noc_placement(const t_noc_opts& noc_opts, noc_cost_handler.initial_noc_routing({}); // Run the simulated annealing optimizer for NoC routers - noc_routers_anneal(noc_opts, blk_loc_registry, noc_cost_handler, rng); + noc_routers_anneal(noc_opts, blk_loc_registry, place_macros, noc_cost_handler, rng); // check if there is any cycles bool has_cycle = noc_cost_handler.noc_routing_has_cycle(); @@ -352,4 +357,4 @@ void initial_noc_placement(const t_noc_opts& noc_opts, "At least one cycle was found in NoC channel dependency graph. This may cause a deadlock " "when packets wait on each other in a cycle.\n"); } -} \ No newline at end of file +} diff --git a/vpr/src/place/initial_noc_placment.h b/vpr/src/place/initial_noc_placment.h index 79b062909dd..1e62164b549 100644 --- a/vpr/src/place/initial_noc_placment.h +++ b/vpr/src/place/initial_noc_placment.h @@ -5,6 +5,7 @@ struct t_noc_opts; struct t_placer_opts; class BlkLocRegistry; +class PlaceMacros; class NocCostHandler; namespace vtr { @@ -22,6 +23,7 @@ class RngContainer; */ void initial_noc_placement(const t_noc_opts& noc_opts, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, NocCostHandler& noc_cost_handler, vtr::RngContainer& rng); diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index e6c8f8e09db..aac91e0fd65 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -1,4 +1,11 @@ -#include "vtr_memory.h" +#include "clustered_netlist.h" +#include "flat_placement_types.h" +#include "atom_netlist_fwd.h" +#include "physical_types_util.h" +#include "place_macro.h" +#include "vtr_assert.h" +#include "vtr_geometry.h" +#include "vtr_ndmatrix.h" #include "vtr_random.h" #include "vtr_time.h" #include "vpr_types.h" @@ -13,10 +20,14 @@ #include "move_utils.h" #include "region.h" #include "noc_place_utils.h" +#include "vtr_vector.h" +#include #include +#include +#include #include - +#include #ifdef VERBOSE void print_clb_placement(const char* fname); @@ -31,6 +42,10 @@ static constexpr int SORT_WEIGHT_PER_FAILED_BLOCK = 10; // The amount of weight that will be added to each tile which is outside the floorplanning constraints static constexpr int SORT_WEIGHT_PER_TILES_OUTSIDE_OF_PR = 100; +// The range limit to be used when searching for a neighbor in the centroid placement. +// The neighbor location should be within the defined range to the calculated centroid location. +static constexpr int CENTROID_NEIGHBOR_SEARCH_RLIM = 15; + /** * @brief Control routine for placing a macro. * First iteration of place_marco performs the following steps to place a macro: @@ -38,10 +53,10 @@ static constexpr int SORT_WEIGHT_PER_TILES_OUTSIDE_OF_PR = 100; * 2) try_place_macro_randomly : if no smart location found in the centroid placement, the function tries * to place it randomly for the max number of tries. * 3) try_place_macro_exhaustively : if neither placement algorithms work, the function will find a location - * for the macro by exhaustively searching all available locations. + * for the macro by exhaustively searching all available locations. * If first iteration failed, next iteration calls dense placement for specific block types. - * - * @param macros_max_num_tries Max number of tries for initial placement before switching to exhaustive placement. + * + * @param macros_max_num_tries Max number of tries for initial placement before switching to exhaustive placement. * @param pl_macro The macro to be placed. * @param pad_loc_type Used to check whether an io block needs to be marked as fixed. * @param blk_types_empty_locs_in_grid First location (lowest y) and number of remaining blocks in each column for the blk_id type. @@ -49,7 +64,7 @@ static constexpr int SORT_WEIGHT_PER_TILES_OUTSIDE_OF_PR = 100; * @param blk_loc_registry Placement block location information. To be filled with the location * where pl_macro is placed. * @param rng A random number generator. - * + * * @return true if macro was placed, false if not. */ static bool place_macro(int macros_max_num_tries, @@ -58,6 +73,7 @@ static bool place_macro(int macros_max_num_tries, std::vector* blk_types_empty_locs_in_grid, vtr::vector& block_scores, BlkLocRegistry& blk_loc_registry, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng); /* @@ -85,7 +101,7 @@ static int get_y_loc_based_on_macro_direction(t_grid_empty_locs_block_type first * * @param loc The first available location that can place the macro blocks. * @param pl_macro The macro to be placed. - * @param blk_types_empty_locs_in_grid first location (lowest y) and number of remaining blocks in each column for the blk_id type + * @param blk_types_empty_locs_in_grid first location (lowest y) and number of remaining blocks in each column for the blk_id type * * @return index to a column of blk_types_empty_locs_in_grid that can accommodate pl_macro and location of first available location returned by reference */ @@ -97,8 +113,8 @@ static int get_blk_type_first_loc(t_pl_loc& loc, const t_pl_macro& pl_macro, std * @param blk_type_column_index Index to a column in blk_types_empty_locs_in_grid that placed pl_macro in itself. * @param block_type Logical block type of the macro blocks. * @param pl_macro The macro to be placed. - * @param blk_types_empty_locs_in_grid first location (lowest y) and number of remaining blocks in each column for the blk_id type - * + * @param blk_types_empty_locs_in_grid first location (lowest y) and number of remaining blocks in each column for the blk_id type + * */ static void update_blk_type_first_loc(int blk_type_column_index, t_logical_block_type_ptr block_type, @@ -106,10 +122,10 @@ static void update_blk_type_first_loc(int blk_type_column_index, std::vector* blk_types_empty_locs_in_grid); /** - * @brief Initializes empty locations of the grid with a specific block type into vector for dense initial placement + * @brief Initializes empty locations of the grid with a specific block type into vector for dense initial placement * * @param block_type_index block type index that failed in previous initial placement iterations - * + * * @return first location (lowest y) and number of remaining blocks in each column for the block_type_index */ static std::vector init_blk_types_empty_locations(int block_type_index); @@ -129,19 +145,38 @@ static inline void fix_IO_block_types(const t_pl_macro& pl_macro, vtr::vector_map& block_locs); /** - * @brief Determine whether a specific macro can be placed in a specific location. - * + * @brief Determine whether a specific macro can be placed in a specific location. + * * @param loc The location at which the macro head member is placed. * @param pr The PartitionRegion of the macro head member - represents its floorplanning constraints, is the size of * the whole chip if the macro is not constrained. * @param block_type Logical block type of the macro head member. - * + * * @return True if the location is legal for the macro head member, false otherwise. */ static bool is_loc_legal(const t_pl_loc& loc, const PartitionRegion& pr, t_logical_block_type_ptr block_type); +/** + * @brief Helper function to choose a subtile in specified location if the type is compatible and an available one exists. + * + * @param centroid The centroid location at which the subtile will be selected using its x, y, and layer. + * @param block_type Logical block type we would like to place here. + * @param block_loc_registry Information on where other blocks have been placed. + * @param pr The PartitionRegion of the block we are trying to place - represents its floorplanning constraints; + * it is the size of the whole chip if the block is not constrained. + * @param rng A random number generator to select a subtile from the available and compatible ones. + * + * @return True if the location is on the chip, legal, and at least one available subtile is found at that location; + * false otherwise. + */ +static bool find_subtile_in_location(t_pl_loc& centroid, + t_logical_block_type_ptr block_type, + const BlkLocRegistry& blk_loc_registry, + const PartitionRegion& pr, + vtr::RngContainer& rng); + /** * @brief Calculates a centroid location for a block based on its placed connections. * @@ -170,6 +205,7 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, static bool find_centroid_neighbor(t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, + int r_lim, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng); @@ -194,12 +230,13 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro, e_pad_loc_type pad_loc_type, vtr::vector& block_scores, BlkLocRegistry& blk_loc_registry, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng); /** - * @brief Looks for a valid placement location for macro in second iteration, tries to place as many macros as possible in one column - * and avoids fragmenting the available locations in one column. - * + * @brief Looks for a valid placement location for macro in second iteration, tries to place as many macros as possible in one column + * and avoids fragmenting the available locations in one column. + * * @param pl_macro The macro to be placed. * @param pr The PartitionRegion of the macro - represents its floorplanning constraints, is the size of the whole chip if the macro is not * constrained. @@ -220,7 +257,7 @@ static bool try_dense_placement(const t_pl_macro& pl_macro, /** * @brief Tries for MAX_INIT_PLACE_ATTEMPTS times to place all blocks considering their floorplanning constraints and the device size - * + * * @param pad_loc_type Used to check whether an io block needs to be marked as fixed. * @param constraints_file Used to read block locations if any constraints is available. * @param blk_loc_registry Placement block location information. To be filled with the location @@ -232,24 +269,21 @@ static void place_all_blocks(const t_placer_opts& placer_opts, e_pad_loc_type pad_loc_type, const char* constraints_file, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng); /** * @brief If any blocks remain unplaced after all initial placement iterations, this routine * throws an error indicating that initial placement can not be done with the current device size or - * floorplanning constraints. - */ -static void check_initial_placement_legality(const vtr::vector_map& block_locs); - -/** - * @brief Fills movable_blocks in global PlacementContext + * floorplanning constraints. */ -static void alloc_and_load_movable_blocks(const vtr::vector_map& block_locs); +static void check_initial_placement_legality(const BlkLocRegistry& blk_loc_registry); -static void check_initial_placement_legality(const vtr::vector_map& block_locs) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_ctx = g_vpr_ctx.placement(); - auto& device_ctx = g_vpr_ctx.device(); +static void check_initial_placement_legality(const BlkLocRegistry& blk_loc_registry) { + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& device_ctx = g_vpr_ctx.device(); + const auto& block_locs = blk_loc_registry.block_locs(); int unplaced_blocks = 0; @@ -271,14 +305,14 @@ static void check_initial_placement_legality(const vtr::vector_mapindex]; + const auto& type = device_ctx.grid.get_physical_type({centroid.x, centroid.y, centroid.layer}); + const auto& compatible_sub_tiles = compressed_block_grid.compatible_sub_tile_num(type->index); + + //filter out the occupied subtiles + const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); + std::vector available_sub_tiles; + available_sub_tiles.reserve(compatible_sub_tiles.size()); + for (int sub_tile : compatible_sub_tiles) { + t_pl_loc pos = {centroid.x, centroid.y, sub_tile, centroid.layer}; + if (!grid_blocks.block_at_location(pos)) { + available_sub_tiles.push_back(sub_tile); + } + } + + if (!available_sub_tiles.empty()) { + centroid.sub_tile = available_sub_tiles[rng.irand((int)available_sub_tiles.size() - 1)]; + return true; + } + } + + return false; +} + static bool find_centroid_neighbor(t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, + int rlim, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng) { const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; @@ -348,7 +416,7 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, //range limit (rlim) set a limit for the neighbor search in the centroid placement //the neighbor location should be within the defined range to calculated centroid location - int first_rlim = 15; + int first_rlim = rlim; auto search_range = get_compressed_grid_target_search_range(compressed_block_grid, compressed_centroid_loc[centroid_loc_layer_num], @@ -483,19 +551,299 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, return connected_blocks_to_update; } +// TODO: Should this return the unplaced_blocks_to_update_their_score? +static t_flat_pl_loc find_centroid_loc_from_flat_placement(const t_pl_macro& pl_macro, + const FlatPlacementInfo& flat_placement_info) { + // Use the flat placement to compute the centroid of the given macro. + // TODO: Instead of averaging, maybe use MODE (most frequently placed location). + float acc_weight = 0.f; + t_flat_pl_loc centroid({0.0f, 0.0f, 0.0f}); + for (const t_pl_macro_member& member : pl_macro.members) { + const auto& cluster_atoms = g_vpr_ctx.clustering().atoms_lookup[member.blk_index]; + for (AtomBlockId atom_blk_id : cluster_atoms) { + // TODO: We can get away with using less information. + VTR_ASSERT(flat_placement_info.blk_x_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS && flat_placement_info.blk_y_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS && flat_placement_info.blk_layer[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS && flat_placement_info.blk_sub_tile[atom_blk_id] != FlatPlacementInfo::UNDEFINED_SUB_TILE); + + // Accumulate the x, y, layer, and sub_tile for each atom in each + // member of the macro. Remove the offset so the centroid would be + // where the head macro should be placed to put the members in the + // correct place. + t_flat_pl_loc cluster_offset({(float)member.offset.x, + (float)member.offset.y, + (float)member.offset.layer}); + centroid += flat_placement_info.get_pos(atom_blk_id); + centroid -= cluster_offset; + acc_weight++; + } + } + if (acc_weight > 0.f) { + centroid /= acc_weight; + } + return centroid; +} + +/** + * @brief Returns the L1 distance a cluster at the given flat location would + * need to move to be within the bounds of a tile at the given tile loc. + */ +static inline float get_dist_to_tile(const t_flat_pl_loc& src_flat_loc, + const t_physical_tile_loc& tile_loc, + const DeviceGrid& device_grid) { + // Get the bounds of the tile. + // Note: The get_tile_bb function will not work in this case since it + // subtracts 1 from the width and height. + auto tile_type = device_grid.get_physical_type(tile_loc); + float tile_xmin = tile_loc.x - device_grid.get_width_offset(tile_loc); + float tile_xmax = tile_xmin + tile_type->width; + float tile_ymin = tile_loc.y - device_grid.get_height_offset(tile_loc); + float tile_ymax = tile_ymin + tile_type->height; + + // Get the closest point in the bounding box (including the edges) to + // the src_flat_loc. To do this, we project the point in L1 space. + float proj_x = std::clamp(src_flat_loc.x, tile_xmin, tile_xmax); + float proj_y = std::clamp(src_flat_loc.y, tile_ymin, tile_ymax); + + // Then compute the L1 distance from the src_flat_loc to the projected + // position. This will be the minimum distance this point needs to move. + float dx = std::abs(proj_x - src_flat_loc.x); + float dy = std::abs(proj_y - src_flat_loc.y); + return dx + dy; +} + +/** + * @brief Returns the first available sub_tile (both compatible with the given + * compressed grid and is empty according the the blk_loc_registry) in + * the tile at the given grid_loc. Returns OPEN if no such sub_tile exists. + */ +static inline int get_first_available_sub_tile_at_grid_loc(const t_physical_tile_loc& grid_loc, + const BlkLocRegistry& blk_loc_registry, + const DeviceGrid& device_grid, + const t_compressed_block_grid& compressed_block_grid) { + + // Get the compatible sub-tiles from the compressed grid for this physical + // tile type. + const t_physical_tile_type_ptr phy_type = device_grid.get_physical_type(grid_loc); + const auto& compatible_sub_tiles = compressed_block_grid.compatible_sub_tile_num(phy_type->index); + + // Return the first empty sub-tile from this list. + for (int sub_tile : compatible_sub_tiles) { + if (blk_loc_registry.grid_blocks().is_sub_tile_empty(grid_loc, sub_tile)) { + return sub_tile; + } + } + + // If one cannot be found, return OPEN. + return OPEN; +} + +/** + * @brief Find the nearest compatible location for the given macro as close to + * the src_flat_loc as possible. + * + * This method uses a BFS to find the closest legal location for the macro. + * + * @param src_flat_loc + * The start location of the BFS. This is given as a flat placement to + * allow the search to trade-off different location options. For example, + * if src_loc was (1.6, 1.5), this tells the search that the cluster + * would prefer to be at tile (1, 1), but if it cannot go there and + * it had to go to one of the neighbors, it would prefer to be on the + * right. + * @param block_type + * The logical block type of the macro. + * @param macro + * The macro to place in the location. + * @param blk_loc_registry + * + * @return Returns the closest legal location found. All of the dimensions will + * be OPEN if a locations could not be found. + */ +static inline t_pl_loc find_nearest_compatible_loc(const t_flat_pl_loc& src_flat_loc, + float max_displacement_threshold, + t_logical_block_type_ptr block_type, + const t_pl_macro& pl_macro, + const BlkLocRegistry& blk_loc_registry) { + // This method performs a BFS over the compressed grid. This avoids searching + // locations which obviously cannot implement this macro. + const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; + const DeviceGrid& device_grid = g_vpr_ctx.device().grid; + const int num_layers = device_grid.get_num_layers(); + // This method does not support 3D FPGAs yet. The search performed will only + // traverse the same layer as the src_loc. + VTR_ASSERT(num_layers == 1); + constexpr int layer = 0; + + // Get the closest (approximately) compressed location to the src location. + // This does not need to be perfect (in fact I do not think it is), but the + // closer it is, the faster the BFS will find the best solution. + t_physical_tile_loc src_grid_loc(src_flat_loc.x, src_flat_loc.y, src_flat_loc.layer); + const t_physical_tile_loc compressed_src_loc = compressed_block_grid.grid_loc_to_compressed_loc_approx(src_grid_loc); + + // Weighted-BFS search the compressed grid for an empty compatible subtile. + size_t num_rows = compressed_block_grid.get_num_rows(layer); + size_t num_cols = compressed_block_grid.get_num_columns(layer); + vtr::NdMatrix visited({num_cols, num_rows}, false); + float best_dist = std::numeric_limits::max(); + t_pl_loc best_loc(OPEN, OPEN, OPEN, OPEN); + + std::queue loc_queue; + loc_queue.push(compressed_src_loc); + while (!loc_queue.empty()) { + // Pop the top element off the queue. + t_physical_tile_loc loc = loc_queue.front(); + loc_queue.pop(); + + // If this location has already been visited, skip it. + if (visited[loc.x][loc.y]) + continue; + visited[loc.x][loc.y] = true; + + // Get the minimum distance the cluster would need to move (relative to + // its global placement solution) to be within the tile at the given + // location. + // Note: In compressed space, distances are not what they appear. We are + // using the true grid positions to get the truly closest loc. + auto grid_loc = compressed_block_grid.compressed_loc_to_grid_loc(loc); + float grid_dist = get_dist_to_tile(src_flat_loc, grid_loc, device_grid); + // If this distance is worst than the best we have seen. + // NOTE: This prune is always safe (i.e. it will never remove a better + // solution) since this is a spatial graph and our objective is + // positional distance. The un-visitied neighbors of a node should + // have a higher distance than the current node. + if (grid_dist >= best_dist) + continue; + + // If this distance is beyond the max_displacement_threshold, drop this + // location. + if (grid_dist > max_displacement_threshold) + continue; + + // In order to ensure our BFS finds the closest compatible location, we + // traverse compressed grid locations which may not actually be valid + // (i.e. no tile exists there). This is fine, we just need to check for + // them to ensure we never try to put a cluster there. + bool is_valid_compressed_loc = false; + const auto& compressed_col_blk_map = compressed_block_grid.get_column_block_map(loc.x, layer); + if (compressed_col_blk_map.count(loc.y) != 0) + is_valid_compressed_loc = true; + + // If this distance is better than the best we have seen so far, try + // to see if this is a better solution. + if (is_valid_compressed_loc) { + // Get a sub-tile at this location if it is available. + int new_sub_tile = get_first_available_sub_tile_at_grid_loc(grid_loc, + blk_loc_registry, + device_grid, + compressed_block_grid); + if (new_sub_tile != OPEN) { + // If a sub-tile is available, set this to be the first sub-tile + // available and check if this site is legal for this macro. + // Note: We are using the fully legality check here to check for + // floorplanning constraints and compatibility for all + // members of the macro. This prevents some macros being + // placed where they obviously cannot be implemented. + // Note: The check_all_legality flag is poorly named. false means + // that it WILL check all legality... + t_pl_loc new_loc = t_pl_loc(grid_loc.x, grid_loc.y, new_sub_tile, grid_loc.layer_num); + bool site_legal_for_macro = macro_can_be_placed(pl_macro, + new_loc, + false /*check_all_legality*/, + blk_loc_registry); + if (site_legal_for_macro) { + // Update the best solition. + // Note: We need to keep searching since the compressed grid + // may present a location which is closer in compressed + // space earlier than a location which is closer in + // grid space. + best_dist = grid_dist; + best_loc = new_loc; + } + } + } + + // Push the neighbors (in the compressed grid) onto the queue. + // This will push the neighbors left, right, above, and below the current + // location. Some of these locations may not exist or may have already + // been visited. The code above checks for these cases to prevent extra + // work and invalid lookups. This must be done this way to ensure that + // the closest location can be found efficiently. + if (loc.x > 0) { + t_physical_tile_loc new_comp_loc = t_physical_tile_loc(loc.x - 1, + loc.y, + loc.layer_num); + loc_queue.push(new_comp_loc); + } + if (loc.x < (int)num_cols - 1) { + t_physical_tile_loc new_comp_loc = t_physical_tile_loc(loc.x + 1, + loc.y, + loc.layer_num); + loc_queue.push(new_comp_loc); + } + if (loc.y > 0) { + t_physical_tile_loc new_comp_loc = t_physical_tile_loc(loc.x, + loc.y - 1, + loc.layer_num); + loc_queue.push(new_comp_loc); + } + if (loc.y < (int)num_rows - 1) { + t_physical_tile_loc new_comp_loc = t_physical_tile_loc(loc.x, + loc.y + 1, + loc.layer_num); + loc_queue.push(new_comp_loc); + } + } + + return best_loc; +} + static bool try_centroid_placement(const t_pl_macro& pl_macro, const PartitionRegion& pr, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, vtr::vector& block_scores, BlkLocRegistry& blk_loc_registry, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng) { auto& block_locs = blk_loc_registry.mutable_block_locs(); t_pl_loc centroid_loc(OPEN, OPEN, OPEN, OPEN); std::vector unplaced_blocks_to_update_their_score; - unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry); + bool found_legal_subtile = false; + + int rlim = CENTROID_NEIGHBOR_SEARCH_RLIM; + if (!flat_placement_info.valid) { + // If a flat placement is not provided, use the centroid of connected + // blocks which have already been placed. + unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry); + found_legal_subtile = find_subtile_in_location(centroid_loc, block_type, blk_loc_registry, pr, rng); + } else { + // If a flat placement is provided, use the flat placement to get the + // centroid location of the macro. + t_flat_pl_loc centroid_flat_loc = find_centroid_loc_from_flat_placement(pl_macro, flat_placement_info); + // Then find the nearest legal location to this centroid for this macro. + centroid_loc = find_nearest_compatible_loc(centroid_flat_loc, + static_cast(rlim), + block_type, + pl_macro, + blk_loc_registry); + // FIXME: After this point, if the find_nearest_compatible_loc function + // could not find a valid location, then nothing should be able to. + // Also the location it returns will be on the chip and in the PR + // by construction. Could save time by skipping those checks if + // needed. + if (centroid_loc.x == OPEN) { + // If we cannot find a nearest block, fall back on the original + // find_centroid_loc function. + // FIXME: We should really just skip this block and come back + // to it later. We do not want it taking space from + // someone else! + unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry); + found_legal_subtile = find_subtile_in_location(centroid_loc, block_type, blk_loc_registry, pr, rng); + } else { + found_legal_subtile = true; + } + } //no suggestion was available for this block type if (!is_loc_on_chip({centroid_loc.x, centroid_loc.y, centroid_loc.layer})) { @@ -504,9 +852,8 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro, //centroid suggestion was either occupied or does not match block type //try to find a near location that meet these requirements - bool neighbor_legal_loc = false; - if (!is_loc_legal(centroid_loc, pr, block_type)) { - neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, blk_loc_registry, rng); + if (!found_legal_subtile) { + bool neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, rlim, blk_loc_registry, rng); if (!neighbor_legal_loc) { //no neighbor candidate found return false; } @@ -518,15 +865,6 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro, } auto& device_ctx = g_vpr_ctx.device(); - //choose the location's subtile if the centroid location is legal. - //if the location is found within the "find_centroid_neighbor", it already has a subtile - //we don't need to find one again - if (!neighbor_legal_loc) { - const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; - const auto& type = device_ctx.grid.get_physical_type({centroid_loc.x, centroid_loc.y, centroid_loc.layer}); - const auto& compatible_sub_tiles = compressed_block_grid.compatible_sub_tile_num(type->index); - centroid_loc.sub_tile = compatible_sub_tiles[rng.irand((int)compatible_sub_tiles.size() - 1)]; - } int width_offset = device_ctx.grid.get_width_offset({centroid_loc.x, centroid_loc.y, centroid_loc.layer}); int height_offset = device_ctx.grid.get_height_offset({centroid_loc.x, centroid_loc.y, centroid_loc.layer}); VTR_ASSERT(width_offset == 0); @@ -562,7 +900,8 @@ static int get_y_loc_based_on_macro_direction(t_grid_empty_locs_block_type first static void update_blk_type_first_loc(int blk_type_column_index, t_logical_block_type_ptr block_type, - const t_pl_macro& pl_macro, std::vector* blk_types_empty_locs_in_grid) { + const t_pl_macro& pl_macro, + std::vector* blk_types_empty_locs_in_grid) { //check if dense placement could place macro successfully if (blk_type_column_index == -1 || blk_types_empty_locs_in_grid->size() <= (size_t)abs(blk_type_column_index)) { return; @@ -703,7 +1042,6 @@ bool try_place_macro_randomly(const t_pl_macro& pl_macro, blk_loc_registry, rng); - if (!legal) { //No valid position found return false; @@ -894,6 +1232,7 @@ static bool place_macro(int macros_max_num_tries, std::vector* blk_types_empty_locs_in_grid, vtr::vector& block_scores, BlkLocRegistry& blk_loc_registry, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng) { const auto& block_locs = blk_loc_registry.block_locs(); ClusterBlockId blk_id = pl_macro.members[0].blk_index; @@ -928,7 +1267,7 @@ static bool place_macro(int macros_max_num_tries, if (!macro_placed) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tTry centroid placement\n"); - macro_placed = try_centroid_placement(pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, rng); + macro_placed = try_centroid_placement(pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); } VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tMacro is placed: %d\n", macro_placed); // If macro is not placed yet, try to place the macro randomly for the max number of random tries @@ -953,7 +1292,8 @@ static bool place_macro(int macros_max_num_tries, static vtr::vector assign_block_scores(const PlaceMacros& place_macros) { const auto& cluster_ctx = g_vpr_ctx.clustering(); - const auto& floorplan_ctx = g_vpr_ctx.floorplanning();; + const auto& floorplan_ctx = g_vpr_ctx.floorplanning(); + ; t_block_score score; @@ -993,16 +1333,16 @@ static vtr::vector assign_block_scores(const Plac return block_scores; } - static void place_all_blocks(const t_placer_opts& placer_opts, vtr::vector& block_scores, enum e_pad_loc_type pad_loc_type, const char* constraints_file, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng) { const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& device_ctx = g_vpr_ctx.device(); - const auto& place_macros = blk_loc_registry.place_macros(); auto blocks = cluster_ctx.clb_nlist.blocks(); int number_of_unplaced_blks_in_curr_itr; @@ -1059,7 +1399,14 @@ static void place_all_blocks(const t_placer_opts& placer_opts, blocks_placed_since_heap_update++; - bool block_placed = place_one_block(blk_id, pad_loc_type, &blk_types_empty_locs_in_grid[blk_id_type->index], &block_scores, blk_loc_registry, rng); + bool block_placed = place_one_block(blk_id, + pad_loc_type, + &blk_types_empty_locs_in_grid[blk_id_type->index], + &block_scores, + blk_loc_registry, + place_macros, + flat_placement_info, + rng); //update heap based on update_heap_freq calculated above if (blocks_placed_since_heap_update % (update_heap_freq) == 0) { @@ -1095,117 +1442,386 @@ static void place_all_blocks(const t_placer_opts& placer_opts, } } +/** + * @brief Gets or creates a macro for the given blk_id. + * + * If the block belongs to a macro, this method will return that macro object. + * Note: This code should not create a copy of that macro object. + * + * If the block does not belong to a macro, it will create a "fake" macro that + * only contains the given block. + */ +static inline t_pl_macro get_or_create_macro(ClusterBlockId blk_id, + const PlaceMacros& place_macros) { + // Lookup to see if the block is part of a macro + int imacro = place_macros.get_imacro_from_iblk(blk_id); + + // If the block belongs to a macro, just return it. + if (imacro != -1) { + VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\tBelongs to a macro %d\n", imacro); + return place_macros[imacro]; + } + + // If it does not belong to a macro, create a macro with the one block and then pass to the placement routines + // This is done so that the initial placement flow can be the same whether the block belongs to a macro or not + t_pl_macro_member macro_member; + macro_member.blk_index = blk_id; + macro_member.offset = t_pl_offset(0, 0, 0, 0); + t_pl_macro pl_macro; + pl_macro.members.push_back(macro_member); + return pl_macro; +} + bool place_one_block(const ClusterBlockId blk_id, enum e_pad_loc_type pad_loc_type, std::vector* blk_types_empty_locs_in_grid, vtr::vector* block_scores, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng) { const auto& block_locs = blk_loc_registry.block_locs(); - const auto& place_macros = blk_loc_registry.place_macros(); //Check if block has already been placed if (is_block_placed(blk_id, block_locs)) { return true; } - bool placed_macro = false; + // If this cluster block is contained within a macro, return it. If not + // create a "fake" macro which only contains this block. + t_pl_macro pl_macro = get_or_create_macro(blk_id, place_macros); - //Lookup to see if the block is part of a macro - int imacro = place_macros.get_imacro_from_iblk(blk_id); + // Try to place this macro. + bool placed_macro = place_macro(MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY, pl_macro, pad_loc_type, blk_types_empty_locs_in_grid, *block_scores, blk_loc_registry, flat_placement_info, rng); - if (imacro != -1) { //If the block belongs to a macro, pass that macro to the placement routines - VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\tBelongs to a macro %d\n", imacro); - const t_pl_macro& pl_macro = place_macros[imacro]; - placed_macro = place_macro(MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY, pl_macro, pad_loc_type, blk_types_empty_locs_in_grid, *block_scores, blk_loc_registry, rng); - } else { - //If it does not belong to a macro, create a macro with the one block and then pass to the placement routines - //This is done so that the initial placement flow can be the same whether the block belongs to a macro or not - t_pl_macro_member macro_member; - macro_member.blk_index = blk_id; - macro_member.offset = t_pl_offset(0, 0, 0, 0); - t_pl_macro pl_macro; - pl_macro.members.push_back(macro_member); - placed_macro = place_macro(MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY, pl_macro, pad_loc_type, blk_types_empty_locs_in_grid, *block_scores, blk_loc_registry, rng); + // Return the status of the macro placement. + return placed_macro; +} + +static inline float get_flat_variance(const t_pl_macro& macro, + const FlatPlacementInfo& flat_placement_info) { + + // Find the flat centroid location of this macro. Then find the grid location + // that this would be. + t_flat_pl_loc centroid_flat_loc = find_centroid_loc_from_flat_placement(macro, flat_placement_info); + t_physical_tile_loc centroid_grid_loc(centroid_flat_loc.x, + centroid_flat_loc.y, + centroid_flat_loc.layer); + + // Compute the variance. + float num_atoms = 0; + float variance = 0.0f; + for (const t_pl_macro_member& member : macro.members) { + const auto& cluster_atoms = g_vpr_ctx.clustering().atoms_lookup[member.blk_index]; + for (AtomBlockId atom_blk_id : cluster_atoms) { + // Get the atom position, offset by the member offset. This translates + // all atoms to be as if they are in the head position of the macro. + t_flat_pl_loc atom_pos = flat_placement_info.get_pos(atom_blk_id); + t_flat_pl_loc cluster_offset({(float)member.offset.x, + (float)member.offset.y, + (float)member.offset.layer}); + atom_pos -= cluster_offset; + + // Get the amount this atom needs to be displaced in order to be + // within the same tile as the centroid. + float dist = get_dist_to_tile(atom_pos, centroid_grid_loc, g_vpr_ctx.device().grid); + + // Accumulate the variance. + variance += (dist * dist); + num_atoms++; + } + } + if (num_atoms > 0.f) { + variance /= num_atoms; } + return variance; +} - return placed_macro; +/** + * @brief Print the status header for the AP initial placer. + */ +static void print_ap_initial_placer_header() { + VTR_LOG("---- ---------- ---------- -------------\n"); + VTR_LOG("Pass Max Displ. Num Blocks Num Blocks \n"); + VTR_LOG(" Threshold Placed Left Unplaced\n"); + VTR_LOG("---- ---------- ---------- -------------\n"); } -static void alloc_and_load_movable_blocks(const vtr::vector_map& block_locs) { - auto& place_ctx = g_vpr_ctx.mutable_placement(); - const auto& cluster_ctx = g_vpr_ctx.clustering(); - const auto& device_ctx = g_vpr_ctx.device(); +/** + * @brief Print the status of the current iteration (pass) of the AP initial + * placer. + */ +static void print_ap_initial_placer_status(unsigned iteration, + float max_displacement_threshold, + size_t num_placed, + size_t num_unplaced) { + // Iteration + VTR_LOG("%4u", iteration); - place_ctx.movable_blocks.clear(); - place_ctx.movable_blocks_per_type.clear(); + // Max displacement threshold + VTR_LOG(" %10g", max_displacement_threshold); - size_t n_logical_blocks = device_ctx.logical_block_types.size(); - place_ctx.movable_blocks_per_type.resize(n_logical_blocks); + // Num placed + VTR_LOG(" %10zu", num_placed); - // iterate over all clustered blocks and store block ids of movable ones - for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) { - const auto& loc = block_locs[blk_id]; - if (!loc.is_fixed) { - place_ctx.movable_blocks.push_back(blk_id); + // Num unplaced + VTR_LOG(" %13zu", num_unplaced); + + VTR_LOG("\n"); + + fflush(stdout); +} + +/** + * @brief Places all blocks in the clustered netlist as close to the global + * placement produced by the AP flow. + * + * This function will place clusters in passes. In the first pass, it will try + * to place clusters exactly where their global placement is (according to the + * atoms contained in the cluster). In the second pass, all unplaced clusters + * will try to be placed within 1 tile of where they wanted to be placed. + * Subsequent passes will then try to place clusters at exponentially farther + * distances. + * + * The clusters are sorted based on how many clusters are in the macro that + * contains this cluster and the standard deviation of the placement of atoms + * within the cluster. Large macros with low standard deviation will be placed + * first. + */ +static inline void place_all_blocks_ap(enum e_pad_loc_type pad_loc_type, + BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, + const FlatPlacementInfo& flat_placement_info) { + const ClusteredNetlist& cluster_netlist = g_vpr_ctx.clustering().clb_nlist; + const DeviceGrid& device_grid = g_vpr_ctx.device().grid; + + // Create a list of clusters to place. + std::vector clusters_to_place; + clusters_to_place.reserve(cluster_netlist.blocks().size()); + for (ClusterBlockId blk_id : cluster_netlist.blocks()) { + if (!is_block_placed(blk_id, blk_loc_registry.block_locs())) { + clusters_to_place.push_back(blk_id); + } + } + + // Get the max macro size. This is used for scoring macros. + size_t max_macro_size = 1; + for (const t_pl_macro& macro : place_macros.macros()) { + max_macro_size = std::max(max_macro_size, macro.members.size()); + } + + // Sort the list of clusters to place based on some criteria. The clusters + // earlier in the list will get first dibs on where to be placed. + constexpr float macro_size_weight = 1.0f; + constexpr float std_dev_weight = 4.0f; + vtr::vector cluster_score(cluster_netlist.blocks().size(), 0.0f); + for (ClusterBlockId blk_id : cluster_netlist.blocks()) { + // Compute the standard deviation of the positions of all atoms in the + // given macro. This is a measure of how much the atoms "want" to be + // at the centroid location. + t_pl_macro pl_macro = get_or_create_macro(blk_id, place_macros); + float variance = get_flat_variance(pl_macro, flat_placement_info); + float std_dev = std::sqrt(variance); + // Normalize the standard deviation to be a number between 0 and 1. + float normalized_std_dev = std_dev / (std_dev + 1.0f); + + // Get the "size" of the macro. This is the number of members that are + // within the macro, where we consider clusters which are not part of + // macros as having 0 size. Macros tend to be harder to place. + float macro_size = pl_macro.members.size(); + if (place_macros.get_imacro_from_iblk(blk_id) == -1) + macro_size = 0.0f; + // Normalize the macro size to be a number between 0 and 1. + float normalized_macro_size = macro_size / static_cast(max_macro_size); + + // Compute the cost. Clusters wth a higher cost will be placed first. + // Cost is proportional to macro size since larger macros are more + // challenging to place and should be placed earlier if possible. + // Cost is inversly proportional to standard deviation, since clusters + // that contain atoms that all want to be within the same cluster + // should be placed first. + cluster_score[blk_id] = (macro_size_weight * normalized_macro_size) + + (std_dev_weight * (1.0f - normalized_std_dev)); + } + std::stable_sort(clusters_to_place.begin(), clusters_to_place.end(), [&](ClusterBlockId lhs, ClusterBlockId rhs) { + // Sort list such that higher score clusters are placed first. + return cluster_score[lhs] > cluster_score[rhs]; + }); + + // Compute the max L1 distance on the device. If we cannot find a location + // to place a cluster within this distance, then no legal location exists. + float max_distance_on_device = device_grid.width() + device_grid.height(); + + // Print some logging information and the status header. + VTR_LOG("Number of blocks to be placed: %zu\n", clusters_to_place.size()); + VTR_LOG("Max distance on device: %g\n", max_distance_on_device); + print_ap_initial_placer_header(); + + // Iteratively search for legal locations to place blocks. With each + // iteration, we search farther and father away from the global placement + // solution. The idea is to place blocks where they want first, then if they + // cannot be placed we let other blocks try to be placed where they want + // before trying to place the blocks elsewhere. + // + // A list to keep track of the blocks which were unplaced in this iteration. + std::vector unplaced_blocks; + unplaced_blocks.reserve(clusters_to_place.size()); + // The max displacement threshold for the search. We will not search farther + // than this distance when searching for legal location. + // Note: Distance here is the amount we would need to displace the block + // from its global placement solution to be put in the target tile. + float max_displacement_threshold = 0.0f; + float prev_max_displacement_threshold = -1.0f; + size_t iter = 0; + // We stop searching when the previous max_displacement threshold was larger + // than the maximum distance on the device. This implies that the entire device + // was searched. + while (prev_max_displacement_threshold < max_distance_on_device) { + // Early exit. If there is nothing to place in this iteration, just break. + if (clusters_to_place.size() == 0) + break; + + // Try to place each cluster in their cost order. + for (ClusterBlockId blk_to_place : clusters_to_place) { + // If this block is part of a macro, another member of that macro + // may have placed it already. Just skip in that case. + if (is_block_placed(blk_to_place, blk_loc_registry.block_locs())) { + continue; + } - const t_logical_block_type_ptr block_type = cluster_ctx.clb_nlist.block_type(blk_id); - place_ctx.movable_blocks_per_type[block_type->index].push_back(blk_id); + // Get the macro that contains this block, or create a temporary + // macro that only contains this block. + t_pl_macro pl_macro = get_or_create_macro(blk_to_place, place_macros); + + // Get the flat centroid location of the macro. + t_flat_pl_loc centroid_flat_loc = find_centroid_loc_from_flat_placement(pl_macro, flat_placement_info); + + // Find a legal, open site closest to the flat cenetroid location + // (within the displacement threshold). + auto block_type = cluster_netlist.block_type(blk_to_place); + t_pl_loc centroid_loc = find_nearest_compatible_loc(centroid_flat_loc, + max_displacement_threshold, + block_type, + pl_macro, + blk_loc_registry); + + // If a location could not be found, add to list of unplaced blocks + // and skip. + if (centroid_loc.x == OPEN) { + unplaced_blocks.push_back(blk_to_place); + continue; + } + + // The find_nearest_compatible_loc function above should only return + // a location which can legally accomodate the macro (if it found a + // location). Double check these to be safe. + VTR_ASSERT_SAFE(!blk_loc_registry.grid_blocks().block_at_location(centroid_loc)); + VTR_ASSERT_SAFE(macro_can_be_placed(pl_macro, centroid_loc, false, blk_loc_registry)); + + // Place the macro + for (const t_pl_macro_member& pl_macro_member : pl_macro.members) { + t_pl_loc member_pos = centroid_loc + pl_macro_member.offset; + ClusterBlockId iblk = pl_macro_member.blk_index; + blk_loc_registry.set_block_location(iblk, member_pos); + } + + // Finally, if the user asked for random pad locations and this is + // an IO block, lock down the macro at this location so the placer + // can't move it. + // TODO: This is not technically "random" since the AP flow is + // choosing good places to put IO blocks based on the GP stage + // of the flow. This should be investigated to see if a more + // random distribution of IO pads are necessary. + fix_IO_block_types(pl_macro, centroid_loc, pad_loc_type, blk_loc_registry.mutable_block_locs()); } + + // Print the status of this iteration for debugging. + print_ap_initial_placer_status(iter, + max_displacement_threshold, + clusters_to_place.size() - unplaced_blocks.size(), + unplaced_blocks.size()); + + // The clusters to place in the next iteration is the unplaced clusters + // from this iteration. Swap these two vectors and clear the unplaced + // blocks to be filled next iteration. + clusters_to_place.swap(unplaced_blocks); + unplaced_blocks.clear(); + + // Update the max displacement threshold. + // We exponentially increase the threshold. We first begin by trying + // to place all the clusters exactly where they want, then we increase + // the threshold from there. The idea is we spend more iterations with + // low displacement values, then rapidly increase it to get a solution + // sooner. + prev_max_displacement_threshold = max_displacement_threshold; + if (max_displacement_threshold == 0.0f) { + max_displacement_threshold = 1.0f; + } else { + max_displacement_threshold *= 2.0f; + } + + // Increase the iteration for status printing. + iter++; } + + // Check if anything has not been placed, if so just crash for now. + // TODO: Should fall back on the original initial placer. Unless there is a + // bug in the code above, it could be that it is challenging to place + // for this circuit. + VTR_ASSERT(clusters_to_place.size() == 0); } void initial_placement(const t_placer_opts& placer_opts, const char* constraints_file, const t_noc_opts& noc_opts, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, std::optional& noc_cost_handler, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng) { vtr::ScopedStartFinishTimer timer("Initial Placement"); - auto& block_locs = blk_loc_registry.mutable_block_locs(); - const auto& place_macros = blk_loc_registry.place_macros(); - /* Initialize the grid blocks to empty. - * Initialize all the blocks to unplaced. - */ - blk_loc_registry.clear_all_grid_locs(); - - /* Go through cluster blocks to calculate the tightest placement - * floorplan constraint for each constrained block - */ - propagate_place_constraints(place_macros); + // Initialize the block loc registry. + blk_loc_registry.init(); /*Mark the blocks that have already been locked to one spot via floorplan constraints * as fixed, so they do not get moved during initial placement or later during the simulated annealing stage of placement*/ mark_fixed_blocks(blk_loc_registry); - // Compute and store compressed floorplanning constraints - alloc_and_load_compressed_cluster_constraints(); - // read the constraint file and place fixed blocks if (strlen(constraints_file) != 0) { read_constraints(constraints_file, blk_loc_registry); } - if(!placer_opts.read_initial_place_file.empty()) { + if (!placer_opts.read_initial_place_file.empty()) { const auto& grid = g_vpr_ctx.device().grid; read_place(nullptr, placer_opts.read_initial_place_file.c_str(), blk_loc_registry, false, grid); } else { if (noc_opts.noc) { // NoC routers are placed before other blocks - initial_noc_placement(noc_opts, blk_loc_registry, noc_cost_handler.value(), rng); + initial_noc_placement(noc_opts, blk_loc_registry, place_macros, noc_cost_handler.value(), rng); propagate_place_constraints(place_macros); } - //Assign scores to blocks and placement macros according to how difficult they are to place - vtr::vector block_scores = assign_block_scores(place_macros); - //Place all blocks - place_all_blocks(placer_opts, block_scores, placer_opts.pad_loc_type, constraints_file, blk_loc_registry, rng); + if (flat_placement_info.valid) { + place_all_blocks_ap(placer_opts.pad_loc_type, + blk_loc_registry, + place_macros, + flat_placement_info); + } else { + //Assign scores to blocks and placement macros according to how difficult they are to place + vtr::vector block_scores = assign_block_scores(place_macros); + + place_all_blocks(placer_opts, block_scores, placer_opts.pad_loc_type, + constraints_file, blk_loc_registry, place_macros, + flat_placement_info, rng); + } } - alloc_and_load_movable_blocks(block_locs); + // Update the movable blocks vectors in the block loc registry. + blk_loc_registry.alloc_and_load_movable_blocks(); // ensure all blocks are placed and that NoC routing has no cycles - check_initial_placement_legality(block_locs); + check_initial_placement_legality(blk_loc_registry); } diff --git a/vpr/src/place/initial_placement.h b/vpr/src/place/initial_placement.h index f2078a3e720..b668ce92075 100644 --- a/vpr/src/place/initial_placement.h +++ b/vpr/src/place/initial_placement.h @@ -11,7 +11,12 @@ class NocCostHandler; #include "vpr_types.h" #include "vtr_vector_map.h" +// Forward declarations class BlkLocRegistry; +class FlatPlacementInfo; +namespace vtr { +class RngContainer; +} // namespace vtr /* The maximum number of tries when trying to place a macro at a * random location before trying exhaustive placement - find the first @@ -74,7 +79,6 @@ bool try_place_macro_randomly(const t_pl_macro& pl_macro, BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng); - /** * @brief Looks for a valid placement location for macro exhaustively once the maximum number of random locations have been tried. * @@ -143,7 +147,9 @@ void initial_placement(const t_placer_opts& placer_opts, const char* constraints_file, const t_noc_opts& noc_opts, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, std::optional& noc_cost_handler, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng); /** @@ -164,8 +170,8 @@ bool place_one_block(const ClusterBlockId blk_id, std::vector* blk_types_empty_locs_in_grid, vtr::vector* block_scores, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng); - - #endif diff --git a/vpr/src/place/move_generators/centroid_move_generator.cpp b/vpr/src/place/move_generators/centroid_move_generator.cpp index 45ba9121719..68850ac6b98 100644 --- a/vpr/src/place/move_generators/centroid_move_generator.cpp +++ b/vpr/src/place/move_generators/centroid_move_generator.cpp @@ -1,4 +1,6 @@ #include "centroid_move_generator.h" +#include "physical_types_util.h" +#include "place_macro.h" #include "vpr_types.h" #include "globals.h" #include "place_constraints.h" @@ -8,19 +10,23 @@ #include CentroidMoveGenerator::CentroidMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : MoveGenerator(placer_state, reward_function, rng) + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) , weighted_(false) , noc_attraction_weight_(0.0f) , noc_attraction_enabled_(false) {} CentroidMoveGenerator::CentroidMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng, float noc_attraction_weight, size_t high_fanout_net) - : MoveGenerator(placer_state, reward_function, rng) + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) , noc_attraction_weight_(noc_attraction_weight) , noc_attraction_enabled_(true) { VTR_ASSERT(noc_attraction_weight > 0.0 && noc_attraction_weight <= 1.0); @@ -37,13 +43,13 @@ e_create_move CentroidMoveGenerator::propose_move(t_pl_blocks_to_be_moved& block const auto& block_locs = placer_state.block_locs(); const auto& device_ctx = g_vpr_ctx.device(); const auto& cluster_ctx = g_vpr_ctx.clustering(); - const auto& place_move_ctx = placer_state.move(); const auto& blk_loc_registry = placer_state.blk_loc_registry(); // Find a movable block based on blk_type ClusterBlockId b_from = propose_block_to_move(placer_opts, proposed_action.logical_blk_type_index, /*highly_crit_block=*/false, + /*placer_criticalities=*/nullptr, /*net_from=*/nullptr, /*pin_from=*/nullptr, placer_state, @@ -66,7 +72,7 @@ e_create_move CentroidMoveGenerator::propose_move(t_pl_blocks_to_be_moved& block VTR_ASSERT(is_tile_compatible(grid_from_type, cluster_from_type)); t_range_limiters range_limiters{rlim, - place_move_ctx.first_rlim, + first_rlim, placer_opts.place_dm_rlim}; t_pl_loc to; @@ -82,7 +88,7 @@ e_create_move CentroidMoveGenerator::propose_move(t_pl_blocks_to_be_moved& block return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { @@ -308,4 +314,4 @@ t_pl_loc CentroidMoveGenerator::calculate_centroid_loc_(ClusterBlockId b_from, centroid.layer = (int)std::round(acc_layer / acc_weight); return centroid; -} \ No newline at end of file +} diff --git a/vpr/src/place/move_generators/centroid_move_generator.h b/vpr/src/place/move_generators/centroid_move_generator.h index 17d5ec82924..f818b03f8fb 100644 --- a/vpr/src/place/move_generators/centroid_move_generator.h +++ b/vpr/src/place/move_generators/centroid_move_generator.h @@ -1,8 +1,9 @@ -#ifndef VPR_CENTROID_MOVE_GEN_H -#define VPR_CENTROID_MOVE_GEN_H +#pragma once #include "move_generator.h" +class PlaceMacros; + /** * @file * @author M. Elgammal @@ -30,6 +31,8 @@ class CentroidMoveGenerator : public MoveGenerator { * of the RL agent. */ CentroidMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); @@ -49,12 +52,13 @@ class CentroidMoveGenerator : public MoveGenerator { * ignored when forming NoC groups. */ CentroidMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng, float noc_attraction_weight, size_t high_fanout_net); - /** * Returns all NoC routers that are in the NoC group with a given ID. * @param noc_grp_id The NoC group ID whose NoC routers are requested. @@ -128,5 +132,3 @@ class CentroidMoveGenerator : public MoveGenerator { */ void initialize_noc_groups(size_t high_fanout_net); }; - -#endif diff --git a/vpr/src/place/move_generators/critical_uniform_move_generator.cpp b/vpr/src/place/move_generators/critical_uniform_move_generator.cpp index 7a1d39ed308..0a641c30043 100644 --- a/vpr/src/place/move_generators/critical_uniform_move_generator.cpp +++ b/vpr/src/place/move_generators/critical_uniform_move_generator.cpp @@ -1,20 +1,26 @@ + #include "critical_uniform_move_generator.h" + #include "globals.h" +#include "physical_types_util.h" #include "place_constraints.h" +#include "place_macro.h" #include "placer_state.h" #include "move_utils.h" CriticalUniformMoveGenerator::CriticalUniformMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : MoveGenerator(placer_state, reward_function, rng) {} + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) {} e_create_move CriticalUniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, t_propose_action& proposed_action, float rlim, const t_placer_opts& placer_opts, - const PlacerCriticalities* /*criticalities*/) { - auto& cluster_ctx = g_vpr_ctx.clustering(); + const PlacerCriticalities* criticalities) { + const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& placer_state = placer_state_.get(); const auto& block_locs = placer_state.block_locs(); const auto& blk_loc_registry = placer_state.blk_loc_registry(); @@ -25,6 +31,7 @@ e_create_move CriticalUniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved ClusterBlockId b_from = propose_block_to_move(placer_opts, proposed_action.logical_blk_type_index, /*highly_crit_block=*/true, + criticalities, &net_from, &pin_from, placer_state, @@ -48,7 +55,7 @@ e_create_move CriticalUniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { @@ -57,4 +64,3 @@ e_create_move CriticalUniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved return create_move; } - diff --git a/vpr/src/place/move_generators/critical_uniform_move_generator.h b/vpr/src/place/move_generators/critical_uniform_move_generator.h index dd4e5391474..7b8e316e867 100644 --- a/vpr/src/place/move_generators/critical_uniform_move_generator.h +++ b/vpr/src/place/move_generators/critical_uniform_move_generator.h @@ -1,7 +1,8 @@ -#ifndef VPR_CRITICAL_UNIFORM_MOVE_GEN_H -#define VPR_CRITICAL_UNIFORM_MOVE_GEN_H +#pragma once + #include "move_generator.h" -#include "timing_place.h" + +class PlaceMacros; /** * @file @@ -18,6 +19,8 @@ class CriticalUniformMoveGenerator : public MoveGenerator { public: CriticalUniformMoveGenerator() = delete; CriticalUniformMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); @@ -28,5 +31,3 @@ class CriticalUniformMoveGenerator : public MoveGenerator { const t_placer_opts& /*placer_opts*/, const PlacerCriticalities* /*criticalities*/) override; }; - -#endif diff --git a/vpr/src/place/move_generators/feasible_region_move_generator.cpp b/vpr/src/place/move_generators/feasible_region_move_generator.cpp index 75210dafd43..bb8de8522e5 100644 --- a/vpr/src/place/move_generators/feasible_region_move_generator.cpp +++ b/vpr/src/place/move_generators/feasible_region_move_generator.cpp @@ -1,7 +1,9 @@ #include "feasible_region_move_generator.h" #include "globals.h" +#include "physical_types_util.h" #include "place_constraints.h" +#include "place_macro.h" #include "placer_state.h" #include "move_utils.h" @@ -9,9 +11,11 @@ #include FeasibleRegionMoveGenerator::FeasibleRegionMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : MoveGenerator(placer_state, reward_function, rng) {} + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) {} e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, t_propose_action& proposed_action, @@ -20,7 +24,6 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& const PlacerCriticalities* criticalities) { const auto& cluster_ctx = g_vpr_ctx.clustering(); auto& placer_state = placer_state_.get(); - auto& place_move_ctx = placer_state.mutable_move(); const auto& block_locs = placer_state.block_locs(); const auto& blk_loc_registry = placer_state.blk_loc_registry(); @@ -30,6 +33,7 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& ClusterBlockId b_from = propose_block_to_move(placer_opts, proposed_action.logical_blk_type_index, /*highly_crit_block=*/true, + criticalities, &net_from, &pin_from, placer_state, @@ -44,18 +48,22 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& //from block data t_pl_loc from = block_locs[b_from].loc; - auto cluster_from_type = cluster_ctx.clb_nlist.block_type(b_from); - auto grid_from_type = g_vpr_ctx.device().grid.get_physical_type({from.x, from.y, from.layer}); + t_logical_block_type_ptr cluster_from_type = cluster_ctx.clb_nlist.block_type(b_from); + t_physical_tile_type_ptr grid_from_type = g_vpr_ctx.device().grid.get_physical_type({from.x, from.y, from.layer}); VTR_ASSERT(is_tile_compatible(grid_from_type, cluster_from_type)); /* Calculate the feasible region */ t_pl_loc to; // Currently, we don't change the layer for this move to.layer = from.layer; - int max_x, min_x, max_y, min_y; - place_move_ctx.X_coord.clear(); - place_move_ctx.Y_coord.clear(); + int max_x = std::numeric_limits::min(); + int min_x = std::numeric_limits::max(); + int max_y = std::numeric_limits::min(); + int min_y = std::numeric_limits::max(); + + bool found = false; + //For critical input nodes, calculate the x & y min-max values for (ClusterPinId pin_id : cluster_ctx.clb_nlist.block_input_pins(b_from)) { ClusterNetId net_id = cluster_ctx.clb_nlist.pin_net(pin_id); @@ -65,28 +73,25 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& int ipin = cluster_ctx.clb_nlist.pin_net_index(pin_id); if (criticalities->criticality(net_id, ipin) > placer_opts.place_crit_limit) { ClusterBlockId bnum = cluster_ctx.clb_nlist.net_driver_block(net_id); - place_move_ctx.X_coord.push_back(block_locs[bnum].loc.x); - place_move_ctx.Y_coord.push_back(block_locs[bnum].loc.y); + const t_pl_loc& loc = block_locs[bnum].loc; + min_x = std::min(min_x, loc.x); + max_x = std::max(max_x, loc.x); + min_y = std::min(min_y, loc.y); + max_y = std::max(max_y, loc.y); + found = true; } } - if (!place_move_ctx.X_coord.empty()) { - max_x = *(std::max_element(place_move_ctx.X_coord.begin(), place_move_ctx.X_coord.end())); - min_x = *(std::min_element(place_move_ctx.X_coord.begin(), place_move_ctx.X_coord.end())); - max_y = *(std::max_element(place_move_ctx.Y_coord.begin(), place_move_ctx.Y_coord.end())); - min_y = *(std::min_element(place_move_ctx.Y_coord.begin(), place_move_ctx.Y_coord.end())); - } else { - max_x = from.x; - min_x = from.x; - max_y = from.y; - min_y = from.y; + + if (!found) { + min_x = max_x = from.x; + min_y = max_y = from.y; } //Get the most critical output of the node - int xt, yt; ClusterBlockId b_output = cluster_ctx.clb_nlist.net_pin_block(net_from, pin_from); t_pl_loc output_loc = block_locs[b_output].loc; - xt = output_loc.x; - yt = output_loc.y; + int xt = output_loc.x; + int yt = output_loc.y; /** * @brief determine the feasible region @@ -124,14 +129,13 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& VTR_ASSERT(FR_coords.ymin <= FR_coords.ymax); t_range_limiters range_limiters{rlim, - place_move_ctx.first_rlim, + first_rlim, placer_opts.place_dm_rlim}; // Try to find a legal location inside the feasible region if (!find_to_loc_median(cluster_from_type, from, &FR_coords, to, b_from, blk_loc_registry, rng_)) { - /** If there is no legal location in the feasible region, calculate the center of the FR and try to find a legal location - * in a range around this center. - */ + /* If there is no legal location in the feasible region, calculate the center of the FR and try to find a legal location + * in a range around this center. */ t_pl_loc center; center.x = (FR_coords.xmin + FR_coords.xmax) / 2; center.y = (FR_coords.ymin + FR_coords.ymax) / 2; @@ -141,7 +145,7 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { @@ -149,4 +153,4 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& } return create_move; -} \ No newline at end of file +} diff --git a/vpr/src/place/move_generators/feasible_region_move_generator.h b/vpr/src/place/move_generators/feasible_region_move_generator.h index 702f8bdd26c..72e58b17753 100644 --- a/vpr/src/place/move_generators/feasible_region_move_generator.h +++ b/vpr/src/place/move_generators/feasible_region_move_generator.h @@ -1,10 +1,11 @@ -#ifndef VPR_FEASIBLE_REGION_MOVE_GEN_H -#define VPR_FEASIBLE_REGION_MOVE_GEN_H +#pragma once + #include "move_generator.h" -#include "timing_place.h" + +class PlaceMacros; /** - * @brief Feasible Reion (FR) move genrator + * @brief Feasible Region (FR) move generator * * This move was originally defined by Chen et al . in "Simultaneous timing-driven placement and duplication", FPGA 2005 * @@ -22,6 +23,8 @@ class FeasibleRegionMoveGenerator : public MoveGenerator { public: FeasibleRegionMoveGenerator() = delete; FeasibleRegionMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); @@ -32,5 +35,3 @@ class FeasibleRegionMoveGenerator : public MoveGenerator { const t_placer_opts& placer_opts, const PlacerCriticalities* criticalities) override; }; - -#endif diff --git a/vpr/src/place/move_generators/manual_move_generator.cpp b/vpr/src/place/move_generators/manual_move_generator.cpp index f320d9ef1ea..cebbe8e8dd6 100644 --- a/vpr/src/place/move_generators/manual_move_generator.cpp +++ b/vpr/src/place/move_generators/manual_move_generator.cpp @@ -12,14 +12,19 @@ #include "manual_move_generator.h" #include "manual_moves.h" +#include "physical_types_util.h" +#include "place_macro.h" #include "placer_state.h" #ifndef NO_GRAPHICS -# include "draw.h" +#include "draw.h" #endif //NO_GRAPHICS -ManualMoveGenerator::ManualMoveGenerator(PlacerState& placer_state, vtr::RngContainer& rng) - : MoveGenerator(placer_state, e_reward_function::UNDEFINED_REWARD, rng) {} +ManualMoveGenerator::ManualMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, + vtr::RngContainer& rng) + : MoveGenerator(placer_state, place_macros, net_cost_handler, e_reward_function::UNDEFINED_REWARD, rng) {} //Manual Move Generator function e_create_move ManualMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, @@ -66,7 +71,6 @@ e_create_move ManualMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); return create_move; } - diff --git a/vpr/src/place/move_generators/manual_move_generator.h b/vpr/src/place/move_generators/manual_move_generator.h index 12c71dc0ce9..417ecb9d514 100644 --- a/vpr/src/place/move_generators/manual_move_generator.h +++ b/vpr/src/place/move_generators/manual_move_generator.h @@ -5,19 +5,11 @@ * @brief Contains the ManualMoveGenerator class. */ -#ifndef VPR_MANUAL_MOVE_GEN_H -#define VPR_MANUAL_MOVE_GEN_H +#pragma once #include "move_generator.h" -#include "median_move_generator.h" -#include "weighted_median_move_generator.h" -#include "weighted_centroid_move_generator.h" -#include "feasible_region_move_generator.h" -#include "uniform_move_generator.h" -#include "critical_uniform_move_generator.h" -#include "centroid_move_generator.h" -#include "simpleRL_move_generator.h" -#include + +class PlaceMacros; /** * @brief Manual Moves Generator, inherits from MoveGenerator class. @@ -27,7 +19,10 @@ class ManualMoveGenerator : public MoveGenerator { public: ManualMoveGenerator() = delete; - ManualMoveGenerator(PlacerState& placer_state, vtr::RngContainer& rng); + ManualMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, + vtr::RngContainer& rng); //Evaluates if move is successful and legal or unable to do. e_create_move propose_move(t_pl_blocks_to_be_moved& blocks_affected, @@ -36,5 +31,3 @@ class ManualMoveGenerator : public MoveGenerator { const t_placer_opts& /*placer_opts*/, const PlacerCriticalities* /*criticalities*/) override; }; - -#endif /*VPR_MANUAL_MOVE_GEN_H */ diff --git a/vpr/src/place/move_generators/median_move_generator.cpp b/vpr/src/place/move_generators/median_move_generator.cpp index 2e982ac6425..f3652d97789 100644 --- a/vpr/src/place/move_generators/median_move_generator.cpp +++ b/vpr/src/place/move_generators/median_move_generator.cpp @@ -1,16 +1,21 @@ #include "median_move_generator.h" #include "globals.h" +#include "physical_types_util.h" #include "place_constraints.h" +#include "place_macro.h" #include "placer_state.h" #include "move_utils.h" +#include "net_cost_handler.h" #include MedianMoveGenerator::MedianMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : MoveGenerator(placer_state, reward_function, rng) {} + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) {} e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, t_propose_action& proposed_action, @@ -20,7 +25,6 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& device_ctx = g_vpr_ctx.device(); auto& placer_state = placer_state_.get(); - auto& place_move_ctx = placer_state.mutable_move(); const auto& block_locs = placer_state.block_locs(); const auto& blk_loc_registry = placer_state.blk_loc_registry(); @@ -28,6 +32,7 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ ClusterBlockId b_from = propose_block_to_move(placer_opts, proposed_action.logical_blk_type_index, /*highly_crit_block=*/false, + /*placer_criticalities=*/nullptr, /*net_from=*/nullptr, /*pin_from=*/nullptr, placer_state, @@ -42,7 +47,6 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ const int num_layers = device_ctx.grid.get_num_layers(); - t_pl_loc from = block_locs[b_from].loc; int from_layer = from.layer; auto cluster_from_type = cluster_ctx.clb_nlist.block_type(b_from); @@ -57,9 +61,9 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ //clear the vectors that saves X & Y coords //reused to save allocation time - place_move_ctx.X_coord.clear(); - place_move_ctx.Y_coord.clear(); - place_move_ctx.layer_coord.clear(); + X_coord.clear(); + Y_coord.clear(); + layer_coord.clear(); std::vector layer_blk_cnt(num_layers, 0); //true if the net is a feedback from the block to itself @@ -86,10 +90,10 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ t_bb union_bb; const bool cube_bb = g_vpr_ctx.placement().cube_bb; if (!cube_bb) { - union_bb = union_2d_bb(place_move_ctx.layer_bb_coords[net_id]); + union_bb = net_cost_handler_.union_2d_bb(net_id); } - const auto& net_bb_coords = cube_bb ? place_move_ctx.bb_coords[net_id] : union_bb; + const auto& net_bb_coords = cube_bb ? net_cost_handler_.bb_coords(net_id) : union_bb; t_physical_tile_loc old_pin_loc = blk_loc_registry.get_coordinate_of_pin(pin_id); t_physical_tile_loc new_pin_loc; @@ -112,7 +116,7 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ } else { new_pin_loc.layer_num = net_bb_coords.layer_min; } - + // If the moving block is on the border of the bounding box, we cannot get // the bounding box incrementally. In that case, bounding box should be calculated // from scratch. @@ -123,36 +127,36 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ } } //push the calculated coordinates into X,Y coord vectors - place_move_ctx.X_coord.push_back(coords.xmin); - place_move_ctx.X_coord.push_back(coords.xmax); - place_move_ctx.Y_coord.push_back(coords.ymin); - place_move_ctx.Y_coord.push_back(coords.ymax); - place_move_ctx.layer_coord.push_back(coords.layer_min); - place_move_ctx.layer_coord.push_back(coords.layer_max); + X_coord.push_back(coords.xmin); + X_coord.push_back(coords.xmax); + Y_coord.push_back(coords.ymin); + Y_coord.push_back(coords.ymax); + layer_coord.push_back(coords.layer_min); + layer_coord.push_back(coords.layer_max); } - if ((place_move_ctx.X_coord.empty()) || (place_move_ctx.Y_coord.empty()) || (place_move_ctx.layer_coord.empty())) { + if ((X_coord.empty()) || (Y_coord.empty()) || (layer_coord.empty())) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\tMove aborted - X_coord or y_coord or layer_coord are empty\n"); return e_create_move::ABORT; } //calculate the median region - std::stable_sort(place_move_ctx.X_coord.begin(), place_move_ctx.X_coord.end()); - std::stable_sort(place_move_ctx.Y_coord.begin(), place_move_ctx.Y_coord.end()); - std::stable_sort(place_move_ctx.layer_coord.begin(), place_move_ctx.layer_coord.end()); + std::stable_sort(X_coord.begin(), X_coord.end()); + std::stable_sort(Y_coord.begin(), Y_coord.end()); + std::stable_sort(layer_coord.begin(), layer_coord.end()); - limit_coords.xmin = place_move_ctx.X_coord[((place_move_ctx.X_coord.size() - 1) / 2)]; - limit_coords.xmax = place_move_ctx.X_coord[((place_move_ctx.X_coord.size() - 1) / 2) + 1]; + limit_coords.xmin = X_coord[((X_coord.size() - 1) / 2)]; + limit_coords.xmax = X_coord[((X_coord.size() - 1) / 2) + 1]; - limit_coords.ymin = place_move_ctx.Y_coord[((place_move_ctx.Y_coord.size() - 1) / 2)]; - limit_coords.ymax = place_move_ctx.Y_coord[((place_move_ctx.Y_coord.size() - 1) / 2) + 1]; + limit_coords.ymin = Y_coord[((Y_coord.size() - 1) / 2)]; + limit_coords.ymax = Y_coord[((Y_coord.size() - 1) / 2) + 1]; - limit_coords.layer_min = place_move_ctx.layer_coord[((place_move_ctx.layer_coord.size() - 1) / 2)]; - limit_coords.layer_max = place_move_ctx.layer_coord[((place_move_ctx.layer_coord.size() - 1) / 2) + 1]; + limit_coords.layer_min = layer_coord[((layer_coord.size() - 1) / 2)]; + limit_coords.layer_max = layer_coord[((layer_coord.size() - 1) / 2) + 1]; //arrange the different range limiters t_range_limiters range_limiters{rlim, - place_move_ctx.first_rlim, + first_rlim, placer_opts.place_dm_rlim}; //find a location in a range around the center of median region @@ -165,7 +169,7 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { @@ -269,27 +273,24 @@ bool MedianMoveGenerator::get_bb_incrementally(ClusterNetId net_id, t_physical_tile_loc old_pin_loc, t_physical_tile_loc new_pin_loc) { //TODO: account for multiple physical pin instances per logical pin - const auto& place_move_ctx = placer_state_.get().move(); - t_bb union_bb_edge; t_bb union_bb; const bool cube_bb = g_vpr_ctx.placement().cube_bb; /* Calculating per-layer bounding box is more time-consuming compared to cube bounding box. To speed up - * this move, the bounding box used for this move is of the type cube bounding box even if the per-layer - * bounding box is used by placement SA engine. - * If per-layer bounding box is used, we take a union of bounding boxes on each layer to make a cube bounding box. - * For example, the xmax of this cube bounding box is determined by the maximum x coordinate across all blocks on all layers. - */ + * this move, the bounding box used for this move is of the type cube bounding box even if the per-layer + * bounding box is used by placement SA engine. + * If per-layer bounding box is used, we take a union of bounding boxes on each layer to make a cube bounding box. + * For example, the xmax of this cube bounding box is determined by the maximum x coordinate across all blocks on all layers. + */ if (!cube_bb) { - std::tie(union_bb_edge, union_bb) = union_2d_bb_incr(place_move_ctx.layer_bb_num_on_edges[net_id], - place_move_ctx.layer_bb_coords[net_id]); + std::tie(union_bb_edge, union_bb) = net_cost_handler_.union_2d_bb_incr(net_id); } /* In this move, we use a 3D bounding box. Thus, if per-layer BB is used by placer, we need to take a union of BBs and use that for the rest of * operations in this move */ - const t_bb& curr_bb_edge = cube_bb ? place_move_ctx.bb_num_on_edges[net_id] : union_bb_edge; - const t_bb& curr_bb_coord = cube_bb ? place_move_ctx.bb_coords[net_id] : union_bb; + const t_bb& curr_bb_edge = cube_bb ? net_cost_handler_.bb_num_on_edges(net_id) : union_bb_edge; + const t_bb& curr_bb_coord = cube_bb ? net_cost_handler_.bb_coords(net_id) : union_bb; /* Check if I can update the bounding box incrementally. */ diff --git a/vpr/src/place/move_generators/median_move_generator.h b/vpr/src/place/move_generators/median_move_generator.h index 516fcfb573d..62326cbe145 100644 --- a/vpr/src/place/move_generators/median_move_generator.h +++ b/vpr/src/place/move_generators/median_move_generator.h @@ -1,7 +1,9 @@ -#ifndef VPR_MEDIAN_MOVE_GEN_H -#define VPR_MEDIAN_MOVE_GEN_H +#pragma once + #include "move_generator.h" +class PlaceMacros; + /** * @brief Median move generator * @@ -19,6 +21,8 @@ class MedianMoveGenerator : public MoveGenerator { public: MedianMoveGenerator() = delete; MedianMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); @@ -41,11 +45,11 @@ class MedianMoveGenerator : public MoveGenerator { * can be used. Essentially, I am assuming the pins always lie on the outside of the bounding box. * The x and y coordinates are the pin's x and y coordinates. IO blocks are considered to be * one cell in for simplicity. */ - bool get_bb_incrementally(ClusterNetId net_id, t_bb& bb_coord_new, + bool get_bb_incrementally(ClusterNetId net_id, + t_bb& bb_coord_new, t_physical_tile_loc old_pin_loc, t_physical_tile_loc new_pin_loc); - /** * @brief Finds the bounding box of a net and stores its coordinates in the bb_coord_new data structure. * @@ -60,6 +64,12 @@ class MedianMoveGenerator : public MoveGenerator { t_bb& bb_coord_new, ClusterBlockId moving_block_id, bool& skip_net); -}; -#endif + private: + /// Stores x positions to find the median + std::vector X_coord; + /// Stores y positions to find the median + std::vector Y_coord; + /// Stores layer positions to find the median + std::vector layer_coord; +}; diff --git a/vpr/src/place/move_generators/move_generator.cpp b/vpr/src/place/move_generators/move_generator.cpp index fd22e8d8b34..9aa3a527a34 100644 --- a/vpr/src/place/move_generators/move_generator.cpp +++ b/vpr/src/place/move_generators/move_generator.cpp @@ -3,6 +3,8 @@ #include "vpr_error.h" +float MoveGenerator::first_rlim; + void MoveGenerator::calculate_reward_and_process_outcome(const MoveOutcomeStats& move_outcome_stats, double delta_c, float timing_bb_factor) { @@ -34,7 +36,6 @@ void MoveGenerator::calculate_reward_and_process_outcome(const MoveOutcomeStats& process_outcome(-1 * delta_c, reward_func_); break; - case e_reward_function::NON_PENALIZING_BASIC: case e_reward_function::RUNTIME_AWARE: if (delta_c < 0) { @@ -51,7 +52,7 @@ void MoveGenerator::calculate_reward_and_process_outcome(const MoveOutcomeStats& } } -void MoveTypeStat::print_placement_move_types_stats() const { +void MoveTypeStat::print_placement_move_types_stats(const std::vector>& movable_blocks_per_type) const { VTR_LOG("\n\nPlacement perturbation distribution by block and move type: \n"); VTR_LOG( @@ -71,9 +72,9 @@ void MoveTypeStat::print_placement_move_types_stats() const { int num_of_avail_moves = blk_type_moves.size() / device_ctx.logical_block_types.size(); //Print placement information for each block type - for (const auto& itype : device_ctx.logical_block_types) { + for (const t_logical_block_type& itype : device_ctx.logical_block_types) { //Skip non-existing block types in the netlist - if (itype.index == 0 || movable_blocks_per_type(itype).empty()) { + if (itype.index == 0 || movable_blocks_per_type[itype.index].empty()) { continue; } diff --git a/vpr/src/place/move_generators/move_generator.h b/vpr/src/place/move_generators/move_generator.h index e39493e16c6..4f9ed137247 100644 --- a/vpr/src/place/move_generators/move_generator.h +++ b/vpr/src/place/move_generators/move_generator.h @@ -1,13 +1,15 @@ -#ifndef VPR_MOVE_GENERATOR_H -#define VPR_MOVE_GENERATOR_H +#pragma once #include "vpr_types.h" #include "move_utils.h" -#include "timing_place.h" +#include "PlacerCriticalities.h" +#include #include +class PlaceMacros; class PlacerState; +class NetCostHandler; struct MoveOutcomeStats { float delta_cost_norm = std::numeric_limits::quiet_NaN(); @@ -35,9 +37,13 @@ struct MoveTypeStat { vtr::NdMatrix rejected_moves; /** - * @brief Prints placement perturbation distribution by block and move type. + * @brief Prints statistics on the distribution of placement perturbations, + * categorized by block type and move type. + * @param movable_blocks_per_type A vector of vectors, where each inner vector contains ClusterBlockIds of + * all movable blocks belonging to a specific logical type. The outer vector + * is indexed by the logical type index. */ - void print_placement_move_types_stats() const; + void print_placement_move_types_stats(const std::vector>& movable_blocks_per_type) const; inline void incr_blk_type_moves(const t_propose_action& proposed_action) { if (proposed_action.logical_blk_type_index != -1) { //if the agent proposed the block type, then collect the block type stat @@ -65,11 +71,11 @@ struct MoveTypeStat { * @brief enum represents the different reward functions */ enum class e_reward_function { - BASIC, ///@ directly uses the change of the annealing cost function - NON_PENALIZING_BASIC, ///@ same as basic reward function but with 0 reward if it's a hill-climbing one - RUNTIME_AWARE, ///@ same as NON_PENALIZING_BASIC but with normalizing with the runtime factor of each move type - WL_BIASED_RUNTIME_AWARE, ///@ same as RUNTIME_AWARE but more biased to WL cost (the factor of the bias is REWARD_BB_TIMING_RELATIVE_WEIGHT) - UNDEFINED_REWARD ///@ Used for manual moves + BASIC, ///@ directly uses the change of the annealing cost function + NON_PENALIZING_BASIC, ///@ same as basic reward function but with 0 reward if it's a hill-climbing one + RUNTIME_AWARE, ///@ same as NON_PENALIZING_BASIC but with normalizing with the runtime factor of each move type + WL_BIASED_RUNTIME_AWARE, ///@ same as RUNTIME_AWARE but more biased to WL cost (the factor of the bias is REWARD_BB_TIMING_RELATIVE_WEIGHT) + UNDEFINED_REWARD ///@ Used for manual moves }; e_reward_function string_to_reward(const std::string& st); @@ -81,19 +87,26 @@ e_reward_function string_to_reward(const std::string& st); */ class MoveGenerator { public: - /** * @brief Initializes some protected member variables that are used * by inheriting classes. * * @param placer_state A mutable reference to the placement state which will * be stored in this object. + * @param place_macros An immutable reference to the placement macros which + * will be stored in this object. * @param reward_function Specifies the reward function to update q-tables * of the RL agent. * @param rng A random number generator to be used for block and location selection. */ - MoveGenerator(PlacerState& placer_state, e_reward_function reward_function, vtr::RngContainer& rng) + MoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, + e_reward_function reward_function, + vtr::RngContainer& rng) : placer_state_(placer_state) + , place_macros_(place_macros) + , net_cost_handler_(net_cost_handler) , reward_func_(reward_function) , rng_(rng) {} @@ -124,7 +137,7 @@ class MoveGenerator { const PlacerCriticalities* criticalities) = 0; /** - * @brief Recieves feedback about the outcome of the previously proposed move + * @brief Receives feedback about the outcome of the previously proposed move * * This function is very useful for RL agent to get the feedback to the agent * @@ -146,10 +159,22 @@ class MoveGenerator { double delta_c, float timing_bb_factor); + public: + /** + * @brief Initial move range limit for clustered blocks. + * + * @details + * Used by multiple move generators to track annealing progress and adjust behavior. + * Several move generators compare the current range limit with its initial value to + * see if the annealing is in its early or late iterations. + * Since no specific move generators owns this variable, it's been made static. + */ + static float first_rlim; + protected: std::reference_wrapper placer_state_; + const PlaceMacros& place_macros_; + const NetCostHandler& net_cost_handler_; e_reward_function reward_func_; vtr::RngContainer& rng_; }; - -#endif diff --git a/vpr/src/place/move_generators/simpleRL_move_generator.cpp b/vpr/src/place/move_generators/simpleRL_move_generator.cpp index f0ab253c680..12e56704a81 100644 --- a/vpr/src/place/move_generators/simpleRL_move_generator.cpp +++ b/vpr/src/place/move_generators/simpleRL_move_generator.cpp @@ -9,7 +9,6 @@ #include #include - /* File-scope routines */ //a scaled and clipped exponential function static float scaled_clipped_exp(float x) { return std::exp(std::min(1000 * x, float(3.0))); } @@ -37,11 +36,14 @@ void SimpleRLMoveGenerator::process_outcome(double reward, e_reward_function rew * K-Armed bandit agent implementation * * * * */ -KArmedBanditAgent::KArmedBanditAgent(std::vector available_moves, e_agent_space agent_space, vtr::RngContainer& rng) +KArmedBanditAgent::KArmedBanditAgent(std::vector available_moves, + e_agent_space agent_space, + vtr::RngContainer& rng, + const std::vector& num_movable_blocks_per_type) : available_moves_(std::move(available_moves)) , propose_blk_type_(agent_space == e_agent_space::MOVE_BLOCK_TYPE) , rng_(rng) { - std::vector available_logical_block_types = get_available_logical_blk_types_(); + std::vector available_logical_block_types = get_available_logical_blk_types_(num_movable_blocks_per_type); num_available_types_ = available_logical_block_types.size(); size_t num_available_moves = available_moves_.size(); @@ -89,7 +91,7 @@ int KArmedBanditAgent::action_to_blk_type_(const size_t action_idx) { } } -std::vector KArmedBanditAgent::get_available_logical_blk_types_() { +std::vector KArmedBanditAgent::get_available_logical_blk_types_(const std::vector& num_movable_blocks_per_type) { const auto& device_ctx = g_vpr_ctx.device(); std::vector available_blk_types; @@ -99,9 +101,9 @@ std::vector KArmedBanditAgent::get_available_logical_blk_types_() { continue; } - const auto& blk_per_type = movable_blocks_per_type(logical_blk_type); + int num_blk_per_type = num_movable_blocks_per_type[logical_blk_type.index]; - if (!blk_per_type.empty()) { + if (num_blk_per_type > 0) { available_blk_types.push_back(logical_blk_type.index); } } @@ -192,8 +194,12 @@ int KArmedBanditAgent::agent_to_phy_blk_type(const int idx) { * E-greedy agent implementation * * * * */ -EpsilonGreedyAgent::EpsilonGreedyAgent(std::vector available_moves, e_agent_space agent_space, float epsilon, vtr::RngContainer& rng) - : KArmedBanditAgent(std::move(available_moves), agent_space, rng) { +EpsilonGreedyAgent::EpsilonGreedyAgent(std::vector available_moves, + e_agent_space agent_space, + float epsilon, + vtr::RngContainer& rng, + const std::vector& num_movable_blocks_per_type) + : KArmedBanditAgent(std::move(available_moves), agent_space, rng, num_movable_blocks_per_type) { set_epsilon(epsilon); init_q_scores_(); } @@ -267,16 +273,19 @@ void EpsilonGreedyAgent::set_epsilon_action_prob() { * Softmax agent implementation * * * * */ -SoftmaxAgent::SoftmaxAgent(std::vector available_moves, e_agent_space agent_space, vtr::RngContainer& rng) - : KArmedBanditAgent(std::move(available_moves), agent_space, rng) { - init_q_scores_(); +SoftmaxAgent::SoftmaxAgent(std::vector available_moves, + e_agent_space agent_space, + vtr::RngContainer& rng, + const std::vector& num_movable_blocks_per_type) + : KArmedBanditAgent(std::move(available_moves), agent_space, rng, num_movable_blocks_per_type) { + init_q_scores_(num_movable_blocks_per_type); } SoftmaxAgent::~SoftmaxAgent() { if (agent_info_file_) vtr::fclose(agent_info_file_); } -void SoftmaxAgent::init_q_scores_() { +void SoftmaxAgent::init_q_scores_(const std::vector& num_movable_blocks_per_type) { q_ = std::vector(num_available_actions_, 0.); exp_q_ = std::vector(num_available_actions_, 0.); num_action_chosen_ = std::vector(num_available_actions_, 0); @@ -297,7 +306,7 @@ void SoftmaxAgent::init_q_scores_() { * it will use the block ratio to calculate action probability for each q_table entry. */ if (propose_blk_type_) { - set_block_ratio_(); + set_block_ratio_(num_movable_blocks_per_type); } set_action_prob_(); } @@ -320,11 +329,8 @@ t_propose_action SoftmaxAgent::propose_action() { return proposed_action; } -void SoftmaxAgent::set_block_ratio_() { - const auto& place_ctx = g_vpr_ctx.placement(); - size_t num_movable_total_blocks = place_ctx.movable_blocks.size(); - - num_movable_total_blocks = std::max(num_movable_total_blocks, 1); +void SoftmaxAgent::set_block_ratio_(const std::vector& num_movable_blocks_per_type) { + size_t num_movable_total_blocks = std::max(1, std::accumulate(num_movable_blocks_per_type.begin(), num_movable_blocks_per_type.end(), 0)); // allocate enough space for available block types in the netlist block_type_ratio_.resize(num_available_types_); @@ -336,7 +342,7 @@ void SoftmaxAgent::set_block_ratio_() { for (size_t itype = 0; itype < num_available_types_; itype++) { t_logical_block_type blk_type; blk_type.index = agent_to_phy_blk_type(itype); - auto num_blocks = movable_blocks_per_type(blk_type).size(); + int num_blocks = num_movable_blocks_per_type[blk_type.index]; block_type_ratio_[itype] = (float)num_blocks / num_movable_total_blocks; block_type_ratio_[itype] /= available_moves_.size(); } @@ -377,4 +383,4 @@ void SoftmaxAgent::set_action_prob_() { accum += action_prob_[i]; cumm_action_prob_[i] = accum; } -} \ No newline at end of file +} diff --git a/vpr/src/place/move_generators/simpleRL_move_generator.h b/vpr/src/place/move_generators/simpleRL_move_generator.h index eacf736e79b..a3df9f01ac2 100644 --- a/vpr/src/place/move_generators/simpleRL_move_generator.h +++ b/vpr/src/place/move_generators/simpleRL_move_generator.h @@ -1,5 +1,5 @@ -#ifndef VPR_SIMPLERL_MOVE_GEN_H -#define VPR_SIMPLERL_MOVE_GEN_H +#pragma once + #include "move_generator.h" #include "median_move_generator.h" #include "weighted_median_move_generator.h" @@ -9,12 +9,17 @@ #include "critical_uniform_move_generator.h" #include "centroid_move_generator.h" +class PlaceMacros; + /** * @brief KArmedBanditAgent is the base class for RL agents that target the k-armed bandit problems */ class KArmedBanditAgent { public: - KArmedBanditAgent(std::vector available_moves, e_agent_space agent_space, vtr::RngContainer& rng); + KArmedBanditAgent(std::vector available_moves, + e_agent_space agent_space, + vtr::RngContainer& rng, + const std::vector& num_movable_blocks_per_type); virtual ~KArmedBanditAgent() = default; /** @@ -84,14 +89,14 @@ class KArmedBanditAgent { inline int agent_to_phy_blk_type(int idx); protected: - float exp_alpha_ = -1; //Step size for q_ updates (< 0 implies use incremental average) - std::vector available_moves_; //All available moves from which the agent can choose - size_t num_available_types_; //Number of block types that exist in the netlist. Agent may not choose the block type. - size_t num_available_actions_; //Total number of available actions - bool propose_blk_type_ = false; //Check if agent should propose both move and block type or only move type - std::vector num_action_chosen_; //Number of times each arm has been pulled (n) - std::vector q_; //Estimated value of each arm (Q) - size_t last_action_; //type of the last action (move type) proposed + float exp_alpha_ = -1; //Step size for q_ updates (< 0 implies use incremental average) + std::vector available_moves_; //All available moves from which the agent can choose + size_t num_available_types_; //Number of block types that exist in the netlist. Agent may not choose the block type. + size_t num_available_actions_; //Total number of available actions + bool propose_blk_type_ = false; //Check if agent should propose both move and block type or only move type + std::vector num_action_chosen_; //Number of times each arm has been pulled (n) + std::vector q_; //Estimated value of each arm (Q) + size_t last_action_; //type of the last action (move type) proposed /* Ratios of the average runtime to calculate each move type */ /* These ratios are useful for different reward functions * * The vector is calculated by averaging many runs on different circuits */ @@ -103,11 +108,13 @@ class KArmedBanditAgent { private: /** * @brief Iterates over all logical block types and check whether they exist in the - * netlist. Then, returns the logical block type indices found in the netlist. - * + * netlist. Then, returns the logical block type indices found in the netlist. + * @param movable_blocks_per_type A vector of vectors, where each inner vector contains ClusterBlockIds of + * all movable blocks belonging to a specific logical type. The outer vector + * is indexed by the logical type index. * @return A vector containing all logical block type indices that exist in the netlist. */ - static std::vector get_available_logical_blk_types_(); + static std::vector get_available_logical_blk_types_(const std::vector& num_movable_blocks_per_type); private: std::vector action_logical_blk_type_; @@ -122,7 +129,11 @@ class KArmedBanditAgent { */ class EpsilonGreedyAgent : public KArmedBanditAgent { public: - EpsilonGreedyAgent(std::vector available_moves, e_agent_space agent_space, float epsilon, vtr::RngContainer& rng); + EpsilonGreedyAgent(std::vector available_moves, + e_agent_space agent_space, + float epsilon, + vtr::RngContainer& rng, + const std::vector& num_movable_blocks_per_type); ~EpsilonGreedyAgent() override; t_propose_action propose_action() override; //Returns the type of the next action as well as the block type the agent wishes to perform @@ -161,7 +172,10 @@ class EpsilonGreedyAgent : public KArmedBanditAgent { */ class SoftmaxAgent : public KArmedBanditAgent { public: - SoftmaxAgent(std::vector available_moves, e_agent_space agent_space, vtr::RngContainer& rng); + SoftmaxAgent(std::vector available_moves, + e_agent_space agent_space, + vtr::RngContainer& rng, + const std::vector& num_movable_blocks_per_type); ~SoftmaxAgent() override; t_propose_action propose_action() override; //Returns the type of the next action as well as the block type the agent wishes to perform @@ -169,13 +183,19 @@ class SoftmaxAgent : public KArmedBanditAgent { private: /** * @brief Initialize agent's Q-table and internal variable to zero (RL-agent learns everything throughout the placement run and has no prior knowledge) + * @param movable_blocks_per_type A vector of vectors, where each inner vector contains ClusterBlockIds of + * all movable blocks belonging to a specific logical type. The outer vector + * is indexed by the logical type index. */ - void init_q_scores_(); + void init_q_scores_(const std::vector& num_movable_blocks_per_type); /** * @brief Calculate the fraction of total netlist blocks for each agent block type and will be used by the "set_action_prob" function. + * @param movable_blocks_per_type A vector of vectors, where each inner vector contains ClusterBlockIds of + * all movable blocks belonging to a specific logical type. The outer vector + * is indexed by the logical type index. */ - void set_block_ratio_(); + void set_block_ratio_(const std::vector& num_movable_blocks_per_type); /** * @brief Set action probability for all available actions. @@ -211,12 +231,12 @@ class SimpleRLMoveGenerator : public MoveGenerator { * * @param agent std::unique_ptr to the agent. Only EpsilonGreedyAgent and SoftmaxAgent types are accepted * by the constructor. If other types are passed, a compile error would be thrown. - * - * @param is_multi_layer A boolean value to indicate whether the placement is multi-layer or not */ template::value || std::is_same::value>::type> explicit SimpleRLMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng, std::unique_ptr& agent, @@ -236,30 +256,31 @@ class SimpleRLMoveGenerator : public MoveGenerator { template SimpleRLMoveGenerator::SimpleRLMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng, std::unique_ptr& agent, float noc_attraction_weight, size_t high_fanout_thresh) - : MoveGenerator(placer_state, reward_function, rng) { + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) { if (noc_attraction_weight > 0.0f) { all_moves.resize((int)e_move_type::NUMBER_OF_AUTO_MOVES); } else { all_moves.resize((int)e_move_type::NUMBER_OF_AUTO_MOVES - 1); } - all_moves[e_move_type::UNIFORM] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::MEDIAN] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::CENTROID] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::W_CENTROID] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::W_MEDIAN] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::CRIT_UNIFORM] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::FEASIBLE_REGION] = std::make_unique(placer_state, reward_function, rng); + all_moves[e_move_type::UNIFORM] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::MEDIAN] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::CENTROID] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::W_CENTROID] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::W_MEDIAN] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::CRIT_UNIFORM] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::FEASIBLE_REGION] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); if (noc_attraction_weight > 0.0f) { - all_moves[e_move_type::NOC_ATTRACTION_CENTROID] = std::make_unique(placer_state, reward_function, rng, + all_moves[e_move_type::NOC_ATTRACTION_CENTROID] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng, noc_attraction_weight, high_fanout_thresh); } karmed_bandit_agent = std::move(agent); } -#endif diff --git a/vpr/src/place/move_generators/static_move_generator.cpp b/vpr/src/place/move_generators/static_move_generator.cpp index 6a3de5b4a2a..bbe9248682c 100644 --- a/vpr/src/place/move_generators/static_move_generator.cpp +++ b/vpr/src/place/move_generators/static_move_generator.cpp @@ -2,6 +2,7 @@ #include "static_move_generator.h" #include "median_move_generator.h" +#include "place_macro.h" #include "weighted_median_move_generator.h" #include "weighted_centroid_move_generator.h" #include "feasible_region_move_generator.h" @@ -13,19 +14,21 @@ #include "vtr_assert.h" StaticMoveGenerator::StaticMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng, const vtr::vector& move_probs) - : MoveGenerator(placer_state, reward_function, rng) { + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) { all_moves.resize((int)e_move_type::NUMBER_OF_AUTO_MOVES); - all_moves[e_move_type::UNIFORM] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::MEDIAN] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::CENTROID] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::W_CENTROID] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::W_MEDIAN] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::CRIT_UNIFORM] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::FEASIBLE_REGION] = std::make_unique(placer_state, reward_function, rng); + all_moves[e_move_type::UNIFORM] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::MEDIAN] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::CENTROID] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::W_CENTROID] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::W_MEDIAN] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::CRIT_UNIFORM] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::FEASIBLE_REGION] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); initialize_move_prob(move_probs); } @@ -34,7 +37,7 @@ void StaticMoveGenerator::initialize_move_prob(const vtr::vector> all_moves; // list of pointers to the different available move type generators - vtr::vector cumm_move_probs; // accumulative probabilities for different move types - float total_prob; // sum of the input probabilities from the use + vtr::vector> all_moves; // list of pointers to the different available move type generators + vtr::vector cumm_move_probs; // accumulative probabilities for different move types + float total_prob; // sum of the input probabilities from the use void initialize_move_prob(const vtr::vector& move_probs); public: StaticMoveGenerator() = delete; StaticMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng, const vtr::vector& move_probs); @@ -29,4 +32,3 @@ class StaticMoveGenerator : public MoveGenerator { const t_placer_opts& placer_opts, const PlacerCriticalities* criticalities) override; }; -#endif diff --git a/vpr/src/place/move_generators/uniform_move_generator.cpp b/vpr/src/place/move_generators/uniform_move_generator.cpp index 6c6e283ba94..ebfebca5652 100644 --- a/vpr/src/place/move_generators/uniform_move_generator.cpp +++ b/vpr/src/place/move_generators/uniform_move_generator.cpp @@ -1,14 +1,18 @@ #include "uniform_move_generator.h" #include "globals.h" +#include "physical_types_util.h" #include "place_constraints.h" +#include "place_macro.h" #include "placer_state.h" #include "move_utils.h" UniformMoveGenerator::UniformMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : MoveGenerator(placer_state, reward_function, rng) {} + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) {} e_create_move UniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, t_propose_action& proposed_action, @@ -24,6 +28,7 @@ e_create_move UniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks ClusterBlockId b_from = propose_block_to_move(placer_opts, proposed_action.logical_blk_type_index, /*highly_crit_block=*/false, + /*placer_criticalities=*/nullptr, /*net_from=*/nullptr, /*pin_from=*/nullptr, placer_state, @@ -60,7 +65,7 @@ e_create_move UniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks VTR_LOG("\n"); #endif - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { diff --git a/vpr/src/place/move_generators/uniform_move_generator.h b/vpr/src/place/move_generators/uniform_move_generator.h index 02414c3140e..f91ff71635b 100644 --- a/vpr/src/place/move_generators/uniform_move_generator.h +++ b/vpr/src/place/move_generators/uniform_move_generator.h @@ -1,7 +1,9 @@ -#ifndef VPR_UNIFORM_MOVE_GEN_H -#define VPR_UNIFORM_MOVE_GEN_H +#pragma once + #include "move_generator.h" +class PlaceMacros; + /** * @brief The classic VPR move generator * @@ -12,6 +14,8 @@ class UniformMoveGenerator : public MoveGenerator { public: UniformMoveGenerator() = delete; UniformMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); @@ -22,5 +26,3 @@ class UniformMoveGenerator : public MoveGenerator { const t_placer_opts& /*placer_opts*/, const PlacerCriticalities* /*criticalities*/) override; }; - -#endif diff --git a/vpr/src/place/move_generators/weighted_centroid_move_generator.cpp b/vpr/src/place/move_generators/weighted_centroid_move_generator.cpp index a2b99cb1d86..489d5f0ceb4 100644 --- a/vpr/src/place/move_generators/weighted_centroid_move_generator.cpp +++ b/vpr/src/place/move_generators/weighted_centroid_move_generator.cpp @@ -1,8 +1,11 @@ #include "weighted_centroid_move_generator.h" +#include "place_macro.h" WeightedCentroidMoveGenerator::WeightedCentroidMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : CentroidMoveGenerator(placer_state, reward_function, rng) { + : CentroidMoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) { weighted_ = true; } diff --git a/vpr/src/place/move_generators/weighted_centroid_move_generator.h b/vpr/src/place/move_generators/weighted_centroid_move_generator.h index 9a13ebabf08..8d07a0e6118 100644 --- a/vpr/src/place/move_generators/weighted_centroid_move_generator.h +++ b/vpr/src/place/move_generators/weighted_centroid_move_generator.h @@ -1,8 +1,9 @@ -#ifndef VPR_WEIGHTED_CENTROID_MOVE_GEN_H -#define VPR_WEIGHTED_CENTROID_MOVE_GEN_H +#pragma once #include "centroid_move_generator.h" +class PlaceMacros; + /** * @brief Weighted Centroid move generator * @@ -18,8 +19,8 @@ class WeightedCentroidMoveGenerator : public CentroidMoveGenerator { public: WeightedCentroidMoveGenerator() = delete; WeightedCentroidMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); }; - -#endif diff --git a/vpr/src/place/move_generators/weighted_median_move_generator.cpp b/vpr/src/place/move_generators/weighted_median_move_generator.cpp index b391509f5c3..9588e899fa6 100644 --- a/vpr/src/place/move_generators/weighted_median_move_generator.cpp +++ b/vpr/src/place/move_generators/weighted_median_move_generator.cpp @@ -1,7 +1,9 @@ #include "weighted_median_move_generator.h" #include "globals.h" +#include "physical_types_util.h" #include "place_constraints.h" +#include "place_macro.h" #include "placer_state.h" #include "move_utils.h" @@ -11,9 +13,11 @@ #define CRIT_MULT_FOR_W_MEDIAN 10 WeightedMedianMoveGenerator::WeightedMedianMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : MoveGenerator(placer_state, reward_function, rng) {} + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) {} e_create_move WeightedMedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, t_propose_action& proposed_action, @@ -23,13 +27,13 @@ e_create_move WeightedMedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& const auto& cluster_ctx = g_vpr_ctx.clustering(); auto& placer_state = placer_state_.get(); const auto& block_locs = placer_state.block_locs(); - auto& place_move_ctx = placer_state.mutable_move(); const auto& blk_loc_registry = placer_state.blk_loc_registry(); //Find a movable block based on blk_type ClusterBlockId b_from = propose_block_to_move(placer_opts, proposed_action.logical_blk_type_index, /*highly_crit_block=*/false, + /*placer_criticalities=*/nullptr, /*net_from=*/nullptr, /*pin_from=*/nullptr, placer_state, @@ -57,9 +61,9 @@ e_create_move WeightedMedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& //clear the vectors that saves X & Y coords //reused to save allocation time - place_move_ctx.X_coord.clear(); - place_move_ctx.Y_coord.clear(); - place_move_ctx.layer_coord.clear(); + X_coord.clear(); + Y_coord.clear(); + layer_coord.clear(); std::vector layer_blk_cnt(num_layers, 0); //iterate over block pins @@ -87,50 +91,50 @@ e_create_move WeightedMedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& // We need to insert the calculated edges in the X,Y vectors multiple times based on the criticality of the pin that caused each of them. // As all the criticalities are [0,1], we map it to [0,CRIT_MULT_FOR_W_MEDIAN] inserts in the vectors for each edge // by multiplying each edge's criticality by CRIT_MULT_FOR_W_MEDIAN - place_move_ctx.X_coord.insert(place_move_ctx.X_coord.end(), ceil(coords.xmin.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.xmin.edge); - place_move_ctx.X_coord.insert(place_move_ctx.X_coord.end(), ceil(coords.xmax.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.xmax.edge); - place_move_ctx.Y_coord.insert(place_move_ctx.Y_coord.end(), ceil(coords.ymin.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.ymin.edge); - place_move_ctx.Y_coord.insert(place_move_ctx.Y_coord.end(), ceil(coords.ymax.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.ymax.edge); - place_move_ctx.layer_coord.insert(place_move_ctx.layer_coord.end(), ceil(coords.layer_min.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.layer_min.edge); - place_move_ctx.layer_coord.insert(place_move_ctx.layer_coord.end(), ceil(coords.layer_max.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.layer_max.edge); + X_coord.insert(X_coord.end(), ceil(coords.xmin.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.xmin.edge); + X_coord.insert(X_coord.end(), ceil(coords.xmax.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.xmax.edge); + Y_coord.insert(Y_coord.end(), ceil(coords.ymin.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.ymin.edge); + Y_coord.insert(Y_coord.end(), ceil(coords.ymax.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.ymax.edge); + layer_coord.insert(layer_coord.end(), ceil(coords.layer_min.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.layer_min.edge); + layer_coord.insert(layer_coord.end(), ceil(coords.layer_max.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.layer_max.edge); } - if ((place_move_ctx.X_coord.empty()) || (place_move_ctx.Y_coord.empty()) || (place_move_ctx.layer_coord.empty())) { + if ((X_coord.empty()) || (Y_coord.empty()) || (layer_coord.empty())) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\tMove aborted - X_coord or y_coord or layer_coord are empty\n"); return e_create_move::ABORT; } //calculate the weighted median region - std::stable_sort(place_move_ctx.X_coord.begin(), place_move_ctx.X_coord.end()); - std::stable_sort(place_move_ctx.Y_coord.begin(), place_move_ctx.Y_coord.end()); - std::stable_sort(place_move_ctx.layer_coord.begin(), place_move_ctx.layer_coord.end()); + std::stable_sort(X_coord.begin(), X_coord.end()); + std::stable_sort(Y_coord.begin(), Y_coord.end()); + std::stable_sort(layer_coord.begin(), layer_coord.end()); - if (place_move_ctx.X_coord.size() == 1) { - limit_coords.xmin = place_move_ctx.X_coord[0]; + if (X_coord.size() == 1) { + limit_coords.xmin = X_coord[0]; limit_coords.xmax = limit_coords.xmin; } else { - limit_coords.xmin = place_move_ctx.X_coord[((place_move_ctx.X_coord.size() - 1) / 2)]; - limit_coords.xmax = place_move_ctx.X_coord[((place_move_ctx.X_coord.size() - 1) / 2) + 1]; + limit_coords.xmin = X_coord[((X_coord.size() - 1) / 2)]; + limit_coords.xmax = X_coord[((X_coord.size() - 1) / 2) + 1]; } - if (place_move_ctx.Y_coord.size() == 1) { - limit_coords.ymin = place_move_ctx.Y_coord[0]; + if (Y_coord.size() == 1) { + limit_coords.ymin = Y_coord[0]; limit_coords.ymax = limit_coords.ymin; } else { - limit_coords.ymin = place_move_ctx.Y_coord[((place_move_ctx.Y_coord.size() - 1) / 2)]; - limit_coords.ymax = place_move_ctx.Y_coord[((place_move_ctx.Y_coord.size() - 1) / 2) + 1]; + limit_coords.ymin = Y_coord[((Y_coord.size() - 1) / 2)]; + limit_coords.ymax = Y_coord[((Y_coord.size() - 1) / 2) + 1]; } - if (place_move_ctx.layer_coord.size() == 1) { - limit_coords.layer_min = place_move_ctx.layer_coord[0]; + if (layer_coord.size() == 1) { + limit_coords.layer_min = layer_coord[0]; limit_coords.layer_max = limit_coords.layer_min; } else { - limit_coords.layer_min = place_move_ctx.layer_coord[((place_move_ctx.layer_coord.size() - 1) / 2)]; - limit_coords.layer_max = place_move_ctx.layer_coord[((place_move_ctx.layer_coord.size() - 1) / 2) + 1]; + limit_coords.layer_min = layer_coord[((layer_coord.size() - 1) / 2)]; + limit_coords.layer_max = layer_coord[((layer_coord.size() - 1) / 2) + 1]; } t_range_limiters range_limiters{rlim, - place_move_ctx.first_rlim, + first_rlim, placer_opts.place_dm_rlim}; t_pl_loc w_median_point; @@ -142,7 +146,7 @@ e_create_move WeightedMedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { @@ -153,9 +157,9 @@ e_create_move WeightedMedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& } bool WeightedMedianMoveGenerator::get_bb_cost_for_net_excluding_block(ClusterNetId net_id, - ClusterPinId moving_pin_id, - const PlacerCriticalities* criticalities, - t_bb_cost* coords) { + ClusterPinId moving_pin_id, + const PlacerCriticalities* criticalities, + t_bb_cost* coords) { const auto& blk_loc_registry = placer_state_.get().blk_loc_registry(); const auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -253,4 +257,3 @@ bool WeightedMedianMoveGenerator::get_bb_cost_for_net_excluding_block(ClusterNet return skip_net; } - diff --git a/vpr/src/place/move_generators/weighted_median_move_generator.h b/vpr/src/place/move_generators/weighted_median_move_generator.h index a6041f13e87..6cdaf72588f 100644 --- a/vpr/src/place/move_generators/weighted_median_move_generator.h +++ b/vpr/src/place/move_generators/weighted_median_move_generator.h @@ -1,8 +1,8 @@ -#ifndef VPR_WEIGHTED_MEDIAN_MOVE_GEN_H -#define VPR_WEIGHTED_MEDIAN_MOVE_GEN_H +#pragma once #include "move_generator.h" -#include "timing_place.h" + +class PlaceMacros; /** * @brief The weighted median move generator @@ -17,6 +17,8 @@ class WeightedMedianMoveGenerator : public MoveGenerator { public: WeightedMedianMoveGenerator() = delete; WeightedMedianMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); @@ -42,6 +44,12 @@ class WeightedMedianMoveGenerator : public MoveGenerator { ClusterPinId moving_pin_id, const PlacerCriticalities* criticalities, t_bb_cost* coords); -}; -#endif + private: + /// Stores x positions to find the median + std::vector X_coord; + /// Stores y positions to find the median + std::vector Y_coord; + /// Stores layer positions to find the median + std::vector layer_coord; +}; diff --git a/vpr/src/place/move_transactions.cpp b/vpr/src/place/move_transactions.cpp index d51e0236cbf..b64117848cb 100644 --- a/vpr/src/place/move_transactions.cpp +++ b/vpr/src/place/move_transactions.cpp @@ -5,8 +5,8 @@ #include "grid_block.h" #include "vtr_assert.h" -t_pl_blocks_to_be_moved::t_pl_blocks_to_be_moved(size_t max_blocks){ - moved_blocks.reserve(max_blocks); +t_pl_blocks_to_be_moved::t_pl_blocks_to_be_moved(size_t max_blocks) { + moved_blocks.reserve(max_blocks); } size_t t_pl_blocks_to_be_moved::get_size_and_increment() { diff --git a/vpr/src/place/move_transactions.h b/vpr/src/place/move_transactions.h index 6670a012bb0..ce1095c365d 100644 --- a/vpr/src/place/move_transactions.h +++ b/vpr/src/place/move_transactions.h @@ -62,14 +62,14 @@ struct t_pl_blocks_to_be_moved { t_pl_blocks_to_be_moved(t_pl_blocks_to_be_moved&&) = delete; /** - * @brief This function increments the size of the moved_blocks vector and return the index - * of the newly added last elements. - */ + * @brief This function increments the size of the moved_blocks vector and return the index + * of the newly added last elements. + */ size_t get_size_and_increment(); /** - * @brief This function clears all data structures of this struct. - */ + * @brief This function clears all data structures of this struct. + */ void clear_move_blocks(); /** @@ -81,11 +81,10 @@ struct t_pl_blocks_to_be_moved { */ bool driven_by_moved_block(const ClusterNetId net) const; - e_block_move_result record_block_move(ClusterBlockId blk, t_pl_loc to, const BlkLocRegistry& blk_loc_registry); - + std::set determine_locations_emptied_by_move(); std::vector moved_blocks; diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index b5efb699fc7..f3cc457d0bb 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -3,6 +3,8 @@ #include "move_transactions.h" #include "globals.h" +#include "physical_types_util.h" +#include "place_macro.h" #include "vtr_random.h" #include "draw_debug.h" @@ -10,6 +12,7 @@ #include "place_constraints.h" #include "placer_state.h" +#include "PlacerCriticalities.h" //f_placer_breakpoint_reached is used to stop the placer when a breakpoint is reached. // When this flag is true, it stops the placer after the current perturbation. Thus, when a breakpoint is reached, this flag is set to true. @@ -28,10 +31,11 @@ void set_placer_breakpoint_reached(bool flag) { e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, - const BlkLocRegistry& blk_loc_registry) { + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros) { const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); - e_block_move_result outcome = find_affected_blocks(blocks_affected, b_from, to, blk_loc_registry); + e_block_move_result outcome = find_affected_blocks(blocks_affected, b_from, to, blk_loc_registry, place_macros); if (outcome == e_block_move_result::INVERT) { //Try inverting the swap direction @@ -44,7 +48,7 @@ e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, } else { t_pl_loc from = block_locs[b_from].loc; - outcome = find_affected_blocks(blocks_affected, b_to, from, blk_loc_registry); + outcome = find_affected_blocks(blocks_affected, b_to, from, blk_loc_registry, place_macros); if (outcome == e_block_move_result::INVERT) { blocks_affected.move_abortion_logger.log_move_abort("inverted move recursion"); @@ -64,14 +68,14 @@ e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, e_block_move_result find_affected_blocks(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, - const BlkLocRegistry& blk_loc_registry) { + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros) { /* Finds and set ups the affected_blocks array. * Returns abort_swap. */ VTR_ASSERT_SAFE(b_from); const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); - const auto& place_macros = blk_loc_registry.place_macros(); e_block_move_result outcome = e_block_move_result::VALID; @@ -85,7 +89,7 @@ e_block_move_result find_affected_blocks(t_pl_blocks_to_be_moved& blocks_affecte t_pl_offset swap_offset = to - from; int imember_from = 0; - outcome = record_macro_swaps(blocks_affected, imacro_from, imember_from, swap_offset, blk_loc_registry); + outcome = record_macro_swaps(blocks_affected, imacro_from, imember_from, swap_offset, blk_loc_registry, place_macros); VTR_ASSERT_SAFE(outcome != e_block_move_result::VALID || imember_from == int(place_macros[imacro_from].members.size())); @@ -142,14 +146,13 @@ e_block_move_result record_single_block_swap(t_pl_blocks_to_be_moved& blocks_aff return e_block_move_result::ABORT; } - // Sets up the blocks moved outcome = blocks_affected.record_block_move(b_from, to, blk_loc_registry); if (outcome != e_block_move_result::VALID) { return outcome; } - + t_pl_loc from = block_locs[b_from].loc; outcome = blocks_affected.record_block_move(b_to, from, blk_loc_registry); @@ -165,8 +168,8 @@ e_block_move_result record_macro_swaps(t_pl_blocks_to_be_moved& blocks_affected, const int imacro_from, int& imember_from, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry) { - const auto& place_macros = blk_loc_registry.place_macros(); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros) { const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); @@ -199,11 +202,11 @@ e_block_move_result record_macro_swaps(t_pl_blocks_to_be_moved& blocks_affected, //To block is a macro if (imacro_from == imacro_to) { - outcome = record_macro_self_swaps(blocks_affected, imacro_from, swap_offset, blk_loc_registry); + outcome = record_macro_self_swaps(blocks_affected, imacro_from, swap_offset, blk_loc_registry, place_macros); imember_from = place_macros[imacro_from].members.size(); break; //record_macro_self_swaps() handles this case completely, so we don't need to continue the loop } else { - outcome = record_macro_macro_swaps(blocks_affected, imacro_from, imember_from, imacro_to, b_to, swap_offset, blk_loc_registry); + outcome = record_macro_macro_swaps(blocks_affected, imacro_from, imember_from, imacro_to, b_to, swap_offset, blk_loc_registry, place_macros); if (outcome == e_block_move_result::INVERT_VALID) { break; //The move was inverted and successfully proposed, don't need to continue the loop } @@ -227,7 +230,8 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff const int imacro_to, ClusterBlockId blk_to, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry) { + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& pl_macros) { //Adds the macro imacro_to to the set of affected block caused by swapping 'blk_to' to its //new position. // @@ -235,7 +239,6 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff //The position in the from macro ('imacro_from') is specified by 'imember_from', and the relevant //macro fro the to block is 'imacro_to'. - const auto& pl_macros = blk_loc_registry.place_macros().macros(); const auto& block_locs = blk_loc_registry.block_locs(); //At the moment, we only support blk_to being the first element of the 'to' macro. @@ -245,7 +248,7 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff //allows these blocks to swap) if (pl_macros[imacro_to].members[0].blk_index != blk_to) { int imember_to = 0; - auto outcome = record_macro_swaps(blocks_affected, imacro_to, imember_to, -swap_offset, blk_loc_registry); + auto outcome = record_macro_swaps(blocks_affected, imacro_to, imember_to, -swap_offset, blk_loc_registry, pl_macros); if (outcome == e_block_move_result::INVERT) { blocks_affected.move_abortion_logger.log_move_abort("invert recursion2"); outcome = e_block_move_result::ABORT; @@ -314,7 +317,7 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff // //Swap the remainder of the 'to' macro to locations after the 'from' macro. //Note that we are swapping in the opposite direction so the swap offsets are inverted. - return record_macro_swaps(blocks_affected, imacro_to, imember_to, -swap_offset, blk_loc_registry); + return record_macro_swaps(blocks_affected, imacro_to, imember_to, -swap_offset, blk_loc_registry, pl_macros); } return e_block_move_result::VALID; @@ -330,8 +333,8 @@ e_block_move_result record_macro_move(t_pl_blocks_to_be_moved& blocks_affected, std::vector& displaced_blocks, const int imacro, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry) { - const auto& place_macros = blk_loc_registry.place_macros(); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros) { const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); @@ -364,8 +367,8 @@ e_block_move_result identify_macro_self_swap_affected_macros(std::vector& m const int imacro, t_pl_offset swap_offset, const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, MoveAbortionLogger& move_abortion_logger) { - const auto& place_macros = blk_loc_registry.place_macros(); const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); @@ -390,7 +393,7 @@ e_block_move_result identify_macro_self_swap_affected_macros(std::vector& m auto itr = std::find(macros.begin(), macros.end(), imacro_to); if (itr == macros.end()) { macros.push_back(imacro_to); - outcome = identify_macro_self_swap_affected_macros(macros, imacro_to, swap_offset, blk_loc_registry, move_abortion_logger); + outcome = identify_macro_self_swap_affected_macros(macros, imacro_to, swap_offset, blk_loc_registry, place_macros, move_abortion_logger); } } } @@ -400,15 +403,14 @@ e_block_move_result identify_macro_self_swap_affected_macros(std::vector& m e_block_move_result record_macro_self_swaps(t_pl_blocks_to_be_moved& blocks_affected, const int imacro, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry) { - const auto& place_macros = blk_loc_registry.place_macros(); - + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros) { //Reset any partial move blocks_affected.clear_move_blocks(); //Collect the macros affected std::vector affected_macros; - auto outcome = identify_macro_self_swap_affected_macros(affected_macros, imacro, swap_offset, blk_loc_registry, blocks_affected.move_abortion_logger); + auto outcome = identify_macro_self_swap_affected_macros(affected_macros, imacro, swap_offset, blk_loc_registry, place_macros, blocks_affected.move_abortion_logger); if (outcome != e_block_move_result::VALID) { return outcome; @@ -421,7 +423,7 @@ e_block_move_result record_macro_self_swaps(t_pl_blocks_to_be_moved& blocks_affe //Move all the affected macros by the offset for (int imacro_affected : affected_macros) { - outcome = record_macro_move(blocks_affected, displaced_blocks, imacro_affected, swap_offset, blk_loc_registry); + outcome = record_macro_move(blocks_affected, displaced_blocks, imacro_affected, swap_offset, blk_loc_registry, place_macros); if (outcome != e_block_move_result::VALID) { return outcome; @@ -470,7 +472,6 @@ bool is_legal_swap_to_location(ClusterBlockId blk, const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); - if (to.x < 0 || to.x >= int(device_ctx.grid.width()) || to.y < 0 || to.y >= int(device_ctx.grid.height()) || to.layer < 0 @@ -547,30 +548,25 @@ void enable_placer_debug(const t_placer_opts& placer_opts, ClusterBlockId propose_block_to_move(const t_placer_opts& placer_opts, int& logical_blk_type_index, bool highly_crit_block, + const PlacerCriticalities* placer_criticalities, ClusterNetId* net_from, int* pin_from, const PlacerState& placer_state, vtr::RngContainer& rng) { + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& blk_loc_registry = placer_state.blk_loc_registry(); + ClusterBlockId b_from = ClusterBlockId::INVALID(); - auto& cluster_ctx = g_vpr_ctx.clustering(); - if (logical_blk_type_index == -1) { //If the block type is unspecified, choose any random block to be swapped with another random block - if (highly_crit_block) { - b_from = pick_from_highly_critical_block(*net_from, *pin_from, placer_state, rng); - } else { - b_from = pick_from_block(rng); - } + if (highly_crit_block) { + b_from = pick_from_highly_critical_block(*net_from, *pin_from, logical_blk_type_index, placer_state, *placer_criticalities, rng); + } else { + b_from = pick_from_block(logical_blk_type_index, rng, blk_loc_registry); + } - //if a movable block found, set the block type - if (b_from) { - logical_blk_type_index = cluster_ctx.clb_nlist.block_type(b_from)->index; - } - } else { //If the block type is specified, choose a random block with blk_type to be swapped with another random block - if (highly_crit_block) { - b_from = pick_from_highly_critical_block(*net_from, *pin_from, logical_blk_type_index, placer_state, rng); - } else { - b_from = pick_from_block(logical_blk_type_index, rng); - } + //if a movable block found, set the block type + if (b_from) { + logical_blk_type_index = cluster_ctx.clb_nlist.block_type(b_from)->index; } if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { @@ -580,110 +576,54 @@ ClusterBlockId propose_block_to_move(const t_placer_opts& placer_opts, return b_from; } -const std::vector& movable_blocks_per_type(const t_logical_block_type& blk_type) { - const auto& place_ctx = g_vpr_ctx.placement(); - - // the vector is returned as const reference to avoid unnecessary copies, - // especially that returned vectors may be very large as they contain - // all clustered blocks with a specific block type - return place_ctx.movable_blocks_per_type[blk_type.index]; -} - -ClusterBlockId pick_from_block(vtr::RngContainer& rng) { - auto& place_ctx = g_vpr_ctx.placement(); - - // get the number of movable clustered blocks - const size_t n_movable_blocks = place_ctx.movable_blocks.size(); - - if (n_movable_blocks > 0) { - //Pick a movable block at random and return it - auto b_from = ClusterBlockId(rng.irand((int)n_movable_blocks - 1)); - return b_from; - } else { - //No movable blocks found - return ClusterBlockId::INVALID(); - } -} - -ClusterBlockId pick_from_block(const int logical_blk_type_index, vtr::RngContainer& rng) { - auto& place_ctx = g_vpr_ctx.placement(); - - const auto& movable_blocks_of_type = place_ctx.movable_blocks_per_type[logical_blk_type_index]; - - if (movable_blocks_of_type.empty()) { - return ClusterBlockId::INVALID(); - } - - auto b_from = ClusterBlockId(movable_blocks_of_type[rng.irand((int)movable_blocks_of_type.size() - 1)]); - - return b_from; -} - -//Pick a random highly critical block to be swapped with another random block. -//If none is found return ClusterBlockId::INVALID() -ClusterBlockId pick_from_highly_critical_block(ClusterNetId& net_from, - int& pin_from, - const PlacerState& placer_state, - vtr::RngContainer& rng) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_move_ctx = placer_state.move(); - auto& block_locs = placer_state.block_locs(); - - //Initialize critical net and pin to be invalid - net_from = ClusterNetId::INVALID(); - pin_from = -1; +ClusterBlockId pick_from_block(const int logical_blk_type_index, + vtr::RngContainer& rng, + const BlkLocRegistry& blk_loc_registry) { + // if logical block type is specified, pick the 'from' block from blocks of that type; + // otherwise, select it randomly from all blocks + const auto& movable_blocks = (logical_blk_type_index < 0) ? blk_loc_registry.movable_blocks() : blk_loc_registry.movable_blocks_per_type()[logical_blk_type_index]; - //check if any critical block is available - if (place_move_ctx.highly_crit_pins.empty()) { + if (movable_blocks.empty()) { return ClusterBlockId::INVALID(); } - //pick a random highly critical pin and find the nets driver block - std::pair crit_pin = place_move_ctx.highly_crit_pins[rng.irand(place_move_ctx.highly_crit_pins.size() - 1)]; - ClusterBlockId b_from = cluster_ctx.clb_nlist.net_driver_block(crit_pin.first); - - if (block_locs[b_from].is_fixed) { - return ClusterBlockId::INVALID(); //Block is fixed, cannot move - } + ClusterBlockId b_from = movable_blocks[rng.irand((int)movable_blocks.size() - 1)]; - net_from = crit_pin.first; - pin_from = crit_pin.second; return b_from; - - //Unreachable statement - return ClusterBlockId::INVALID(); } -//Pick a random highly critical block with a specified block type to be swapped with another random block. -//If none is found return ClusterBlockId::INVALID() ClusterBlockId pick_from_highly_critical_block(ClusterNetId& net_from, int& pin_from, const int logical_blk_type_index, const PlacerState& placer_state, + const PlacerCriticalities& placer_criticalities, vtr::RngContainer& rng) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_move_ctx = placer_state.move(); - auto& block_locs = placer_state.block_locs(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& block_locs = placer_state.block_locs(); //Initialize critical net and pin to be invalid net_from = ClusterNetId::INVALID(); pin_from = -1; + const auto& highly_crit_pins = placer_criticalities.get_highly_critical_pins(); + //check if any critical block is available - if (place_move_ctx.highly_crit_pins.empty()) { + if (highly_crit_pins.empty()) { return ClusterBlockId::INVALID(); } //pick a random highly critical pin and find the nets driver block - std::pair crit_pin = place_move_ctx.highly_crit_pins[rng.irand(place_move_ctx.highly_crit_pins.size() - 1)]; + std::pair crit_pin = highly_crit_pins[rng.irand(highly_crit_pins.size() - 1)]; ClusterBlockId b_from = cluster_ctx.clb_nlist.net_driver_block(crit_pin.first); - //Check if picked block type matches with the blk_type specified, and it is not fixed - //blk_type from propose move doesn't account for the EMPTY type auto b_from_type = cluster_ctx.clb_nlist.block_type(b_from); - if (b_from_type->index == logical_blk_type_index) { + + // check if the type of the picked block matches with the specified block type + // when a block type is specified, i.e. when logical_blk_type_index >= 0 + if (b_from_type->index == logical_blk_type_index || logical_blk_type_index < 0) { + // ensure that the selected block is not fixed if (block_locs[b_from].is_fixed) { - return ClusterBlockId::INVALID(); //Block is fixed, cannot move + return ClusterBlockId::INVALID(); // a fixed block can't be moved } net_from = crit_pin.first; @@ -692,7 +632,6 @@ ClusterBlockId pick_from_highly_critical_block(ClusterNetId& net_from, } //No critical block with 'blk_type' found - //Unreachable statement return ClusterBlockId::INVALID(); } @@ -707,7 +646,7 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, // //Note that the range limit (rlim) is applied in a logical sense (i.e. 'compressed' grid space consisting //of the same block types, and not the physical grid space). This means, for example, that columns of 'rare' - //blocks (e.g. DSPs/RAMs) which are physically far appart but logically adjacent will be swappable even + //blocks (e.g. DSPs/RAMs) which are physically far apart but logically adjacent will be swappable even //at an rlim fo 1. // //This ensures that such blocks don't get locked down too early during placement (as would be the @@ -1252,7 +1191,7 @@ bool intersect_range_limit_with_floorplan_constraints(ClusterBlockId b_from, const auto [layer_low, layer_high] = compressed_intersect_reg.get_layer_range(); VTR_ASSERT(layer_low == layer_num && layer_high == layer_num); - delta_cx = intersect_rect.xmax() - intersect_rect.xmin(); + delta_cx = intersect_rect.xmax() - intersect_rect.xmin(); std::tie(search_range.xmin, search_range.ymin, search_range.xmax, search_range.ymax) = intersect_rect.coordinates(); search_range.layer_min = layer_low; @@ -1324,111 +1263,3 @@ int get_random_layer(t_logical_block_type_ptr logical_block, vtr::RngContainer& return layer_num; } - -t_bb union_2d_bb(const std::vector& bb_vec) { - t_bb merged_bb; - - // Not all 2d_bbs are valid. Thus, if one of the coordinates in the 2D_bb is not valid (equal to OPEN), - // we need to skip it. - for (const auto& layer_bb : bb_vec) { - if (layer_bb.xmin == OPEN) { - VTR_ASSERT_SAFE(layer_bb.xmax == OPEN); - VTR_ASSERT_SAFE(layer_bb.ymin == OPEN); - VTR_ASSERT_SAFE(layer_bb.ymax == OPEN); - VTR_ASSERT_SAFE(layer_bb.layer_num == OPEN); - continue; - } - if (merged_bb.xmin == OPEN || layer_bb.xmin < merged_bb.xmin) { - merged_bb.xmin = layer_bb.xmin; - } - if (merged_bb.xmax == OPEN || layer_bb.xmax > merged_bb.xmax) { - merged_bb.xmax = layer_bb.xmax; - } - if (merged_bb.ymin == OPEN || layer_bb.ymin < merged_bb.ymin) { - merged_bb.ymin = layer_bb.ymin; - } - if (merged_bb.ymax == OPEN || layer_bb.ymax > merged_bb.ymax) { - merged_bb.ymax = layer_bb.ymax; - } - if (merged_bb.layer_min == OPEN || layer_bb.layer_num < merged_bb.layer_min) { - merged_bb.layer_min = layer_bb.layer_num; - } - if (merged_bb.layer_max == OPEN || layer_bb.layer_num > merged_bb.layer_max) { - merged_bb.layer_max = layer_bb.layer_num; - } - } - - return merged_bb; -} - -std::pair union_2d_bb_incr(const std::vector& num_edge_vec, - const std::vector& bb_vec) { - t_bb merged_num_edge; - t_bb merged_bb; - - for (const auto& layer_bb : bb_vec) { - if (layer_bb.xmin == OPEN) { - VTR_ASSERT_SAFE(layer_bb.xmax == OPEN); - VTR_ASSERT_SAFE(layer_bb.ymin == OPEN); - VTR_ASSERT_SAFE(layer_bb.ymax == OPEN); - VTR_ASSERT_SAFE(layer_bb.layer_num == OPEN); - continue; - } - if (merged_bb.xmin == OPEN || layer_bb.xmin <= merged_bb.xmin) { - if (layer_bb.xmin == merged_bb.xmin) { - VTR_ASSERT_SAFE(merged_num_edge.xmin != OPEN); - merged_num_edge.xmin += num_edge_vec[layer_bb.layer_num].xmin; - } else { - merged_num_edge.xmin = num_edge_vec[layer_bb.layer_num].xmin; - } - merged_bb.xmin = layer_bb.xmin; - } - if (merged_bb.xmax == OPEN || layer_bb.xmax >= merged_bb.xmax) { - if (layer_bb.xmax == merged_bb.xmax) { - VTR_ASSERT_SAFE(merged_num_edge.xmax != OPEN); - merged_num_edge.xmax += num_edge_vec[layer_bb.layer_num].xmax; - } else { - merged_num_edge.xmax = num_edge_vec[layer_bb.layer_num].xmax; - } - merged_bb.xmax = layer_bb.xmax; - } - if (merged_bb.ymin == OPEN || layer_bb.ymin <= merged_bb.ymin) { - if (layer_bb.ymin == merged_bb.ymin) { - VTR_ASSERT_SAFE(merged_num_edge.ymin != OPEN); - merged_num_edge.ymin += num_edge_vec[layer_bb.layer_num].ymin; - } else { - merged_num_edge.ymin = num_edge_vec[layer_bb.layer_num].ymin; - } - merged_bb.ymin = layer_bb.ymin; - } - if (merged_bb.ymax == OPEN || layer_bb.ymax >= merged_bb.ymax) { - if (layer_bb.ymax == merged_bb.ymax) { - VTR_ASSERT_SAFE(merged_num_edge.ymax != OPEN); - merged_num_edge.ymax += num_edge_vec[layer_bb.layer_num].ymax; - } else { - merged_num_edge.ymax = num_edge_vec[layer_bb.layer_num].ymax; - } - merged_bb.ymax = layer_bb.ymax; - } - if (merged_bb.layer_min == OPEN || layer_bb.layer_num <= merged_bb.layer_min) { - if (layer_bb.layer_num == merged_bb.layer_min) { - VTR_ASSERT_SAFE(merged_num_edge.layer_min != OPEN); - merged_num_edge.layer_min += num_edge_vec[layer_bb.layer_num].layer_num; - } else { - merged_num_edge.layer_min = num_edge_vec[layer_bb.layer_num].layer_num; - } - merged_bb.layer_min = layer_bb.layer_num; - } - if (merged_bb.layer_max == OPEN || layer_bb.layer_num >= merged_bb.layer_max) { - if (layer_bb.layer_num == merged_bb.layer_max) { - VTR_ASSERT_SAFE(merged_num_edge.layer_max != OPEN); - merged_num_edge.layer_max += num_edge_vec[layer_bb.layer_num].layer_num; - } else { - merged_num_edge.layer_max = num_edge_vec[layer_bb.layer_num].layer_num; - } - merged_bb.layer_max = layer_bb.layer_num; - } - } - - return std::make_pair(merged_num_edge, merged_bb); -} diff --git a/vpr/src/place/move_utils.h b/vpr/src/place/move_utils.h index de3d771e7ae..5552c36e8e9 100644 --- a/vpr/src/place/move_utils.h +++ b/vpr/src/place/move_utils.h @@ -1,5 +1,5 @@ -#ifndef VPR_MOVE_UTILS_H -#define VPR_MOVE_UTILS_H + +#pragma once #include "vpr_types.h" #include "move_transactions.h" @@ -7,6 +7,8 @@ class PlacerState; class BlkLocRegistry; +class PlaceMacros; +class PlacerCriticalities; namespace vtr { class RngContainer; } @@ -97,7 +99,8 @@ struct t_range_limiters { e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, - const BlkLocRegistry& blk_loc_registry); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros); /** * @brief Find the blocks that will be affected by a move of b_from to to_loc @@ -110,7 +113,8 @@ e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, e_block_move_result find_affected_blocks(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, - const BlkLocRegistry& blk_loc_registry); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros); e_block_move_result record_single_block_swap(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, @@ -121,7 +125,8 @@ e_block_move_result record_macro_swaps(t_pl_blocks_to_be_moved& blocks_affected, const int imacro_from, int& imember_from, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros); e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_affected, const int imacro_from, @@ -129,24 +134,28 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff const int imacro_to, ClusterBlockId blk_to, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& pl_macros); e_block_move_result record_macro_move(t_pl_blocks_to_be_moved& blocks_affected, std::vector& displaced_blocks, const int imacro, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros); e_block_move_result identify_macro_self_swap_affected_macros(std::vector& macros, const int imacro, t_pl_offset swap_offset, const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, MoveAbortionLogger& move_abortion_logger); e_block_move_result record_macro_self_swaps(t_pl_blocks_to_be_moved& blocks_affected, const int imacro, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros); /** * @brief Check whether the "to" location is legal for the given "blk" @@ -171,55 +180,46 @@ bool is_legal_swap_to_location(ClusterBlockId blk, ClusterBlockId propose_block_to_move(const t_placer_opts& placer_opts, int& logical_blk_type_index, bool highly_crit_block, + const PlacerCriticalities* placer_criticalities, ClusterNetId* net_from, int* pin_from, const PlacerState& placer_state, vtr::RngContainer& rng); -/** - * Returns all movable clustered blocks with a specified logical block type. - * @param blk_type Specifies the logical block block type. - * @return A const reference to a vector containing all movable blocks with the specified logical block type. - */ -const std::vector& movable_blocks_per_type(const t_logical_block_type& blk_type); - -/** - * @brief Select a random block to be swapped with another block - * - * @return BlockId of the selected block, ClusterBlockId::INVALID() if no block with specified block type found - */ -ClusterBlockId pick_from_block(vtr::RngContainer& rng); - /** * @brief Find a block with a specific block type to be swapped with another block * - * @param logical_blk_type_index: the agent type of the moving block. + * @param logical_blk_type_index The logical type of the moving block. If a negative value is passed, + * the block is selected randomly from all movable blocks and not from a specific type. + * @param rng A random number generator used to select a random block. + * @param blk_loc_registry Contains movable blocks and movable blocks per type. * * @return BlockId of the selected block, ClusterBlockId::INVALID() if no block with specified block type found */ -ClusterBlockId pick_from_block(int logical_blk_type_index, vtr::RngContainer& rng); - -/** - * @brief Select a random highly critical block to be swapped with another block - * - * @return BlockId of the selected block, ClusterBlockId::INVALID() if no block with specified block type found - */ -ClusterBlockId pick_from_highly_critical_block(ClusterNetId& net_from, - int& pin_from, - const PlacerState& placer_state, - vtr::RngContainer& rng); +ClusterBlockId pick_from_block(int logical_blk_type_index, + vtr::RngContainer& rng, + const BlkLocRegistry& blk_loc_registry); /** - * @brief Find a block with a specific block type to be swapped with another block + * @brief Find a highly critical block with a specific block type to be swapped with another block. * - * @param logical_blk_type_index: the agent type of the moving block. + * @param net_from The clustered net id of the critical connection of the selected block by this function. + * To be filled by this function. + * @param pin_from The pin id of the critical connection of the selected block by this function. + * To be filled by this function. + * @param logical_blk_type_index The logical type of the moving block. If a negative value is passed, + * the block is selected randomly from all movable blocks and not from a specific type. + * @param placer_state Used to access the current placement's info, e.g. block locations and if they are fixed. + * @param placer_criticalities Holds the clustered netlist connection criticalities. + * @param rng A random number generator used to select a random highly critical block. * - * @return BlockId of the selected block, ClusterBlockId::INVALID() if no block with specified block type found + * @return BlockId of the selected block, ClusterBlockId::INVALID() if no block with specified block type found. */ ClusterBlockId pick_from_highly_critical_block(ClusterNetId& net_from, int& pin_from, int logical_blk_type_index, const PlacerState& placer_state, + const PlacerCriticalities& placer_criticalities, vtr::RngContainer& rng); bool find_to_loc_uniform(t_logical_block_type_ptr type, @@ -433,24 +433,6 @@ int find_free_layer(t_logical_block_type_ptr logical_block, int get_random_layer(t_logical_block_type_ptr logical_block, vtr::RngContainer& rng); -/** - * @brief Iterate over all layers and get the maximum x and y over that layers that have a valid value. set the layer min and max - * based on the layers that have a valid BB. - * @param tbb_vec - * @return 3D bounding box - */ -t_bb union_2d_bb(const std::vector& tbb_vec); - -/** - * @brief Iterate over all layers and get the maximum x and y over that layers that have a valid value. Create the "num_edge" in a similar way. This data structure - * stores how many blocks are on each edge of the BB. set the layer min and max based on the layers that have a valid BB. - * @param num_edge_vec - * @param bb_vec - * @return num_edge, 3D bb - */ -std::pair union_2d_bb_incr(const std::vector& num_edge_vec, - const std::vector& bb_vec); - /** * @brief If the block ID passed to the placer_debug_net parameter of the command line is equal to blk_id, or if any of the nets * connected to the block share the same ID as the net ID passed to the placer_debug_net parameter of the command line, @@ -461,5 +443,3 @@ std::pair union_2d_bb_incr(const std::vector& num_edge_vec, */ void enable_placer_debug(const t_placer_opts& placer_opts, ClusterBlockId blk_id); - -#endif diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index ac049995347..0a48466c644 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -33,7 +33,8 @@ #include "place_timing_update.h" #include "vtr_math.h" #include "vtr_ndmatrix.h" -#include "vtr_ndoffsetmatrix.h" +#include "PlacerCriticalities.h" +#include "vtr_prefix_sum.h" #include @@ -68,8 +69,6 @@ static void update_bb_pin_sink_count(const t_physical_tile_loc& pin_old_loc, vtr::NdMatrixProxy bb_pin_sink_count_new, bool is_output_pin); - - /** * @brief When BB is being updated incrementally, the pin is moving to a new layer, and the BB is of the type "per-layer, * use this function to update the BB on the new layer. @@ -85,14 +84,6 @@ static void add_block_to_bb(const t_physical_tile_loc& new_pin_loc, t_2D_bb& bb_edge_new, t_2D_bb& bb_coord_new); -/** - * @brief Given the 3D BB, calculate the wire-length estimate of the net - * @param net_id ID of the net which wirelength estimate is requested - * @param bb Bounding box of the net - * @return Wirelength estimate of the net - */ -static double get_net_wirelength_estimate(ClusterNetId net_id, const t_bb& bb); - /** * @brief To get the wirelength cost/est, BB perimeter is multiplied by a factor to approximately correct for the half-perimeter * bounding box wirelength's underestimate of wiring for nets with fanout greater than 2. @@ -102,7 +93,6 @@ static double wirelength_crossing_count(size_t fanout); /******************************* End of Function definitions ************************************/ - NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, PlacerState& placer_state, bool cube_bb) @@ -118,7 +108,9 @@ NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, if (cube_bb_) { ts_bb_edge_new_.resize(num_nets, t_bb()); ts_bb_coord_new_.resize(num_nets, t_bb()); - comp_bb_cost_functor_ = std::bind(&NetCostHandler::comp_cube_bb_cost_, this, std::placeholders::_1); + bb_coords_.resize(num_nets, t_bb()); + bb_num_on_edges_.resize(num_nets, t_bb()); + comp_bb_cost_functor_ = std::bind(&NetCostHandler::comp_cube_bb_cost_, this, std::placeholders::_1); update_bb_functor_ = std::bind(&NetCostHandler::update_bb_, this, std::placeholders::_1, std::placeholders::_2, std::placeholders::_3, std::placeholders::_4); get_net_bb_cost_functor_ = std::bind(&NetCostHandler::get_net_cube_bb_cost_, this, std::placeholders::_1, /*use_ts=*/true); @@ -126,7 +118,9 @@ NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, } else { layer_ts_bb_edge_new_.resize(num_nets, std::vector(num_layers, t_2D_bb())); layer_ts_bb_coord_new_.resize(num_nets, std::vector(num_layers, t_2D_bb())); - comp_bb_cost_functor_ = std::bind(&NetCostHandler::comp_per_layer_bb_cost_, this, std::placeholders::_1); + layer_bb_num_on_edges_.resize(num_nets, std::vector(num_layers, t_2D_bb())); + layer_bb_coords_.resize(num_nets, std::vector(num_layers, t_2D_bb())); + comp_bb_cost_functor_ = std::bind(&NetCostHandler::comp_per_layer_bb_cost_, this, std::placeholders::_1); update_bb_functor_ = std::bind(&NetCostHandler::update_layer_bb_, this, std::placeholders::_1, std::placeholders::_2, std::placeholders::_3, std::placeholders::_4); get_net_bb_cost_functor_ = std::bind(&NetCostHandler::get_net_per_layer_bb_cost_, this, std::placeholders::_1, /*use_ts=*/true); @@ -135,6 +129,7 @@ NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, /* This initializes the whole matrix to OPEN which is an invalid value*/ ts_layer_sink_pin_count_.resize({num_nets, size_t(num_layers)}, OPEN); + num_sink_pin_layer_.resize({num_nets, size_t(num_layers)}, OPEN); ts_nets_to_update_.resize(num_nets, ClusterNetId::INVALID()); @@ -153,8 +148,8 @@ NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_() { const auto& device_ctx = g_vpr_ctx.device(); - const int grid_height = (int)device_ctx.grid.height(); - const int grid_width = (int)device_ctx.grid.width(); + const size_t grid_height = device_ctx.grid.height(); + const size_t grid_width = device_ctx.grid.width(); /* These arrays contain accumulative channel width between channel zero and * the channel specified by the given index. The accumulated channel width @@ -164,38 +159,29 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_() { * acc_chan?_width_[high] - acc_chan?_width_[low - 1] * This returns the total number of tracks between channels 'low' and 'high', * including tracks in these channels. - * - * Channel -1 doesn't exist, so we can say it has zero tracks. We need to be able - * to access these arrays with index -1 to handle cases where the lower channel is 0. */ - acc_chanx_width_ = vtr::NdOffsetMatrix({{{-1, grid_height}}}); - acc_chany_width_ = vtr::NdOffsetMatrix({{{-1, grid_width}}}); - - // initialize the first element (index -1) with zero - acc_chanx_width_[-1] = 0; - for (int y = 0; y < grid_height; y++) { - acc_chanx_width_[y] = acc_chanx_width_[y - 1] + device_ctx.chan_width.x_list[y]; + acc_chanx_width_ = vtr::PrefixSum1D(grid_height, [&](size_t y) noexcept { + int chan_x_width = device_ctx.chan_width.x_list[y]; /* If the number of tracks in a channel is zero, two consecutive elements take the same * value. This can lead to a division by zero in get_chanxy_cost_fac_(). To avoid this * potential issue, we assume that the channel width is at least 1. */ - if (acc_chanx_width_[y] == acc_chanx_width_[y - 1]) { - acc_chanx_width_[y]++; - } - } + if (chan_x_width == 0) + return 1; - // initialize the first element (index -1) with zero - acc_chany_width_[-1] = 0; - for (int x = 0; x < grid_width; x++) { - acc_chany_width_[x] = acc_chany_width_[x - 1] + device_ctx.chan_width.y_list[x]; + return chan_x_width; + }); + acc_chany_width_ = vtr::PrefixSum1D(grid_width, [&](size_t x) noexcept { + int chan_y_width = device_ctx.chan_width.y_list[x]; // to avoid a division by zero - if (acc_chany_width_[x] == acc_chany_width_[x - 1]) { - acc_chany_width_[x]++; - } - } - + if (chan_y_width == 0) + return 1; + + return chan_y_width; + }); + if (is_multi_layer_) { alloc_and_load_for_fast_vertical_cost_update_(); } @@ -204,13 +190,11 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_() { void NetCostHandler::alloc_and_load_for_fast_vertical_cost_update_() { const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - + const size_t grid_height = device_ctx.grid.height(); const size_t grid_width = device_ctx.grid.width(); - acc_tile_num_inter_die_conn_ = vtr::NdMatrix({grid_width, grid_height}, 0); - - vtr::NdMatrix tile_num_inter_die_conn({grid_width, grid_height}, 0.); + vtr::NdMatrix tile_num_inter_die_conn({grid_width, grid_height}, 0.); /* * Step 1: iterate over the rr-graph, recording how many edges go between layers at each (x,y) location @@ -249,53 +233,34 @@ void NetCostHandler::alloc_and_load_for_fast_vertical_cost_update_() { int num_layers = device_ctx.grid.get_num_layers(); for (size_t x = 0; x < device_ctx.grid.width(); x++) { for (size_t y = 0; y < device_ctx.grid.height(); y++) { - tile_num_inter_die_conn[x][y] /= (num_layers-1); + tile_num_inter_die_conn[x][y] /= (num_layers - 1); } } // Step 2: Calculate prefix sum of the inter-die connectivity up to and including the channel at (x, y). - acc_tile_num_inter_die_conn_[0][0] = tile_num_inter_die_conn[0][0]; - // Initialize the first row and column - for (size_t x = 1; x < device_ctx.grid.width(); x++) { - acc_tile_num_inter_die_conn_[x][0] = acc_tile_num_inter_die_conn_[x-1][0] + - tile_num_inter_die_conn[x][0]; - } - - for (size_t y = 1; y < device_ctx.grid.height(); y++) { - acc_tile_num_inter_die_conn_[0][y] = acc_tile_num_inter_die_conn_[0][y-1] + - tile_num_inter_die_conn[0][y]; - } - - for (size_t x_high = 1; x_high < device_ctx.grid.width(); x_high++) { - for (size_t y_high = 1; y_high < device_ctx.grid.height(); y_high++) { - acc_tile_num_inter_die_conn_[x_high][y_high] = acc_tile_num_inter_die_conn_[x_high-1][y_high] + - acc_tile_num_inter_die_conn_[x_high][y_high-1] + - tile_num_inter_die_conn[x_high][y_high] - - acc_tile_num_inter_die_conn_[x_high-1][y_high-1]; - } - } + acc_tile_num_inter_die_conn_ = vtr::PrefixSum2D(grid_width, + grid_height, + [&](size_t x, size_t y) { + return (int)tile_num_inter_die_conn[x][y]; + }); } -double NetCostHandler::comp_bb_cost(e_cost_methods method) { +std::pair NetCostHandler::comp_bb_cost(e_cost_methods method) { return comp_bb_cost_functor_(method); } -double NetCostHandler::comp_cube_bb_cost_(e_cost_methods method) { +std::pair NetCostHandler::comp_cube_bb_cost_(e_cost_methods method) { const auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_move_ctx = placer_state_.mutable_move(); double cost = 0; double expected_wirelength = 0.0; - for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { /* for each net ... */ - if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ + for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { /* for each net ... */ + if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ /* Small nets don't use incremental updating on their bounding boxes, * * so they can use a fast bounding box calculator. */ if (cluster_ctx.clb_nlist.net_sinks(net_id).size() >= SMALL_NET && method == e_cost_methods::NORMAL) { - get_bb_from_scratch_(net_id, - place_move_ctx.bb_coords[net_id], - place_move_ctx.bb_num_on_edges[net_id], - place_move_ctx.num_sink_pin_layer[size_t(net_id)]); + get_bb_from_scratch_(net_id, /*use_ts=*/false); } else { get_non_updatable_cube_bb_(net_id, /*use_ts=*/false); } @@ -303,36 +268,29 @@ double NetCostHandler::comp_cube_bb_cost_(e_cost_methods method) { net_cost_[net_id] = get_net_cube_bb_cost_(net_id, /*use_ts=*/false); cost += net_cost_[net_id]; if (method == e_cost_methods::CHECK) { - expected_wirelength += get_net_wirelength_estimate(net_id, place_move_ctx.bb_coords[net_id]); + expected_wirelength += get_net_wirelength_estimate_(net_id); } } } - if (method == e_cost_methods::CHECK) { - VTR_LOG("\n"); - VTR_LOG("BB estimate of min-dist (placement) wire length: %.0f\n", - expected_wirelength); - } - - return cost; + return {cost, expected_wirelength}; } -double NetCostHandler::comp_per_layer_bb_cost_(e_cost_methods method) { +std::pair NetCostHandler::comp_per_layer_bb_cost_(e_cost_methods method) { const auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_move_ctx = placer_state_.mutable_move(); double cost = 0; double expected_wirelength = 0.0; - for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { /* for each net ... */ - if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ + for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { /* for each net ... */ + if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ /* Small nets don't use incremental updating on their bounding boxes, * * so they can use a fast bounding box calculator. */ if (cluster_ctx.clb_nlist.net_sinks(net_id).size() >= SMALL_NET && method == e_cost_methods::NORMAL) { get_layer_bb_from_scratch_(net_id, - place_move_ctx.layer_bb_num_on_edges[net_id], - place_move_ctx.layer_bb_coords[net_id], - place_move_ctx.num_sink_pin_layer[size_t(net_id)]); + layer_bb_num_on_edges_[net_id], + layer_bb_coords_[net_id], + num_sink_pin_layer_[size_t(net_id)]); } else { get_non_updatable_per_layer_bb_(net_id, /*use_ts=*/false); } @@ -345,13 +303,7 @@ double NetCostHandler::comp_per_layer_bb_cost_(e_cost_methods method) { } } - if (method == e_cost_methods::CHECK) { - VTR_LOG("\n"); - VTR_LOG("BB estimate of min-dist (placement) wire length: %.0f\n", - expected_wirelength); - } - - return cost; + return {cost, expected_wirelength}; } void NetCostHandler::update_net_bb_(const ClusterNetId net, @@ -532,12 +484,11 @@ void NetCostHandler::get_non_updatable_cube_bb_(ClusterNetId net_id, bool use_ts const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& device_ctx = g_vpr_ctx.device(); const auto& blk_loc_registry = placer_state_.blk_loc_registry(); - auto& move_ctx = placer_state_.mutable_move(); // the bounding box coordinates that is going to be updated by this function - t_bb& bb_coord_new = use_ts ? ts_bb_coord_new_[net_id] : move_ctx.bb_coords[net_id]; + t_bb& bb_coord_new = use_ts ? ts_bb_coord_new_[net_id] : bb_coords_[net_id]; // the number of sink pins of "net_id" on each layer - vtr::NdMatrixProxy num_sink_pin_layer = use_ts ? ts_layer_sink_pin_count_[size_t(net_id)] : move_ctx.num_sink_pin_layer[size_t(net_id)]; + vtr::NdMatrixProxy num_sink_pin_layer = use_ts ? ts_layer_sink_pin_count_[size_t(net_id)] : num_sink_pin_layer_[size_t(net_id)]; // get the source pin's location ClusterPinId source_pin_id = cluster_ctx.clb_nlist.net_pin(net_id, 0); @@ -585,10 +536,9 @@ void NetCostHandler::get_non_updatable_per_layer_bb_(ClusterNetId net_id, bool u const auto& device_ctx = g_vpr_ctx.device(); const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& blk_loc_registry = placer_state_.blk_loc_registry(); - auto& move_ctx = placer_state_.mutable_move(); - std::vector& bb_coord_new = use_ts ? layer_ts_bb_coord_new_[net_id] : move_ctx.layer_bb_coords[net_id]; - vtr::NdMatrixProxy num_sink_layer = use_ts ? ts_layer_sink_pin_count_[size_t(net_id)] : move_ctx.num_sink_pin_layer[size_t(net_id)]; + std::vector& bb_coord_new = use_ts ? layer_ts_bb_coord_new_[net_id] : layer_bb_coords_[net_id]; + vtr::NdMatrixProxy num_sink_layer = use_ts ? ts_layer_sink_pin_count_[size_t(net_id)] : num_sink_pin_layer_[size_t(net_id)]; const int num_layers = device_ctx.grid.get_num_layers(); VTR_ASSERT_DEBUG(bb_coord_new.size() == (size_t)num_layers); @@ -627,8 +577,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, //TODO: account for multiple physical pin instances per logical pin const t_bb *curr_bb_edge, *curr_bb_coord; - auto& device_ctx = g_vpr_ctx.device(); - auto& place_move_ctx = placer_state_.move(); + const auto& device_ctx = g_vpr_ctx.device(); const int num_layers = device_ctx.grid.get_num_layers(); @@ -645,12 +594,12 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, return; } - vtr::NdMatrixProxy curr_num_sink_pin_layer = (bb_update_status_[net_id] == NetUpdateState::NOT_UPDATED_YET) ? place_move_ctx.num_sink_pin_layer[size_t(net_id)] : num_sink_pin_layer_new; + vtr::NdMatrixProxy curr_num_sink_pin_layer = (bb_update_status_[net_id] == NetUpdateState::NOT_UPDATED_YET) ? num_sink_pin_layer_[size_t(net_id)] : num_sink_pin_layer_new; if (bb_update_status_[net_id] == NetUpdateState::NOT_UPDATED_YET) { /* The net had NOT been updated before, could use the old values */ - curr_bb_edge = &place_move_ctx.bb_num_on_edges[net_id]; - curr_bb_coord = &place_move_ctx.bb_coords[net_id]; + curr_bb_edge = &bb_num_on_edges_[net_id]; + curr_bb_coord = &bb_coords_[net_id]; bb_update_status_[net_id] = NetUpdateState::UPDATED_ONCE; } else { /* The net had been updated before, must use the new values */ @@ -666,7 +615,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, if (pin_old_loc.x == curr_bb_coord->xmax) { /* Old position at xmax. */ if (curr_bb_edge->xmax == 1) { - get_bb_from_scratch_(net_id, bb_coord_new, bb_edge_new, num_sink_pin_layer_new); + get_bb_from_scratch_(net_id, /*use_ts=*/true); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -698,7 +647,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, if (pin_old_loc.x == curr_bb_coord->xmin) { /* Old position at xmin. */ if (curr_bb_edge->xmin == 1) { - get_bb_from_scratch_(net_id, bb_coord_new, bb_edge_new, num_sink_pin_layer_new); + get_bb_from_scratch_(net_id, /*use_ts=*/true); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -739,7 +688,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, if (pin_old_loc.y == curr_bb_coord->ymax) { /* Old position at ymax. */ if (curr_bb_edge->ymax == 1) { - get_bb_from_scratch_(net_id, bb_coord_new, bb_edge_new, num_sink_pin_layer_new); + get_bb_from_scratch_(net_id, /*use_ts=*/true); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -771,7 +720,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, if (pin_old_loc.y == curr_bb_coord->ymin) { /* Old position at ymin. */ if (curr_bb_edge->ymin == 1) { - get_bb_from_scratch_(net_id, bb_coord_new, bb_edge_new, num_sink_pin_layer_new); + get_bb_from_scratch_(net_id, /*use_ts=*/true); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -821,7 +770,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, if (pin_new_loc.layer_num < pin_old_loc.layer_num) { if (pin_old_loc.layer_num == curr_bb_coord->layer_max) { if (curr_bb_edge->layer_max == 1) { - get_bb_from_scratch_(net_id, bb_coord_new, bb_edge_new, num_sink_pin_layer_new); + get_bb_from_scratch_(net_id, /*use_ts=*/true); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -847,7 +796,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, } else if (pin_new_loc.layer_num > pin_old_loc.layer_num) { if (pin_old_loc.layer_num == curr_bb_coord->layer_min) { if (curr_bb_edge->layer_min == 1) { - get_bb_from_scratch_(net_id, bb_coord_new, bb_edge_new, num_sink_pin_layer_new); + get_bb_from_scratch_(net_id, /*use_ts=*/true); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -893,8 +842,6 @@ void NetCostHandler::update_layer_bb_(ClusterNetId net_id, t_physical_tile_loc pin_old_loc, t_physical_tile_loc pin_new_loc, bool is_output_pin) { - auto& place_move_ctx = placer_state_.move(); - std::vector& bb_edge_new = layer_ts_bb_edge_new_[net_id]; std::vector& bb_coord_new = layer_ts_bb_coord_new_[net_id]; vtr::NdMatrixProxy bb_pin_sink_count_new = ts_layer_sink_pin_count_[size_t(net_id)]; @@ -905,13 +852,13 @@ void NetCostHandler::update_layer_bb_(ClusterNetId net_id, return; } - const vtr::NdMatrixProxy curr_layer_pin_sink_count = (bb_update_status_[net_id] == NetUpdateState::NOT_UPDATED_YET) ? place_move_ctx.num_sink_pin_layer[size_t(net_id)] : bb_pin_sink_count_new; + const vtr::NdMatrixProxy curr_layer_pin_sink_count = (bb_update_status_[net_id] == NetUpdateState::NOT_UPDATED_YET) ? num_sink_pin_layer_[size_t(net_id)] : bb_pin_sink_count_new; const std::vector*curr_bb_edge, *curr_bb_coord; if (bb_update_status_[net_id] == NetUpdateState::NOT_UPDATED_YET) { /* The net had NOT been updated before, could use the old values */ - curr_bb_edge = &place_move_ctx.layer_bb_num_on_edges[net_id]; - curr_bb_coord = &place_move_ctx.layer_bb_coords[net_id]; + curr_bb_edge = &layer_bb_num_on_edges_[net_id]; + curr_bb_coord = &layer_bb_coords_[net_id]; bb_update_status_[net_id] = NetUpdateState::UPDATED_ONCE; } else { /* The net had been updated before, must use the new values */ @@ -960,13 +907,13 @@ void NetCostHandler::update_layer_bb_(ClusterNetId net_id, } inline void NetCostHandler::update_bb_same_layer_(ClusterNetId net_id, - const t_physical_tile_loc& pin_old_loc, - const t_physical_tile_loc& pin_new_loc, - const std::vector& curr_bb_edge, - const std::vector& curr_bb_coord, - vtr::NdMatrixProxy bb_pin_sink_count_new, - std::vector& bb_edge_new, - std::vector& bb_coord_new) { + const t_physical_tile_loc& pin_old_loc, + const t_physical_tile_loc& pin_new_loc, + const std::vector& curr_bb_edge, + const std::vector& curr_bb_coord, + vtr::NdMatrixProxy bb_pin_sink_count_new, + std::vector& bb_edge_new, + std::vector& bb_coord_new) { int x_old = pin_old_loc.x; int x_new = pin_new_loc.x; @@ -979,13 +926,13 @@ inline void NetCostHandler::update_bb_same_layer_(ClusterNetId net_id, if (x_new < x_old) { if (x_old == curr_bb_coord[layer_num].xmax) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[layer_num].xmax, - curr_bb_coord[layer_num].xmax, - bb_edge_new[layer_num].xmax, - bb_coord_new[layer_num].xmax); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[layer_num].xmax, + curr_bb_coord[layer_num].xmax, + bb_edge_new[layer_num].xmax, + bb_coord_new[layer_num].xmax); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } @@ -1002,13 +949,13 @@ inline void NetCostHandler::update_bb_same_layer_(ClusterNetId net_id, } else if (x_new > x_old) { if (x_old == curr_bb_coord[layer_num].xmin) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[layer_num].xmin, - curr_bb_coord[layer_num].xmin, - bb_edge_new[layer_num].xmin, - bb_coord_new[layer_num].xmin); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[layer_num].xmin, + curr_bb_coord[layer_num].xmin, + bb_edge_new[layer_num].xmin, + bb_coord_new[layer_num].xmin); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } @@ -1026,13 +973,13 @@ inline void NetCostHandler::update_bb_same_layer_(ClusterNetId net_id, if (y_new < y_old) { if (y_old == curr_bb_coord[layer_num].ymax) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[layer_num].ymax, - curr_bb_coord[layer_num].ymax, - bb_edge_new[layer_num].ymax, - bb_coord_new[layer_num].ymax); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[layer_num].ymax, + curr_bb_coord[layer_num].ymax, + bb_edge_new[layer_num].ymax, + bb_coord_new[layer_num].ymax); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } @@ -1049,13 +996,13 @@ inline void NetCostHandler::update_bb_same_layer_(ClusterNetId net_id, } else if (y_new > y_old) { if (y_old == curr_bb_coord[layer_num].ymin) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[layer_num].ymin, - curr_bb_coord[layer_num].ymin, - bb_edge_new[layer_num].ymin, - bb_coord_new[layer_num].ymin); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[layer_num].ymin, + curr_bb_coord[layer_num].ymin, + bb_edge_new[layer_num].ymin, + bb_coord_new[layer_num].ymin); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } @@ -1072,13 +1019,13 @@ inline void NetCostHandler::update_bb_same_layer_(ClusterNetId net_id, } inline void NetCostHandler::update_bb_layer_changed_(ClusterNetId net_id, - const t_physical_tile_loc& pin_old_loc, - const t_physical_tile_loc& pin_new_loc, - const std::vector& curr_bb_edge, - const std::vector& curr_bb_coord, - vtr::NdMatrixProxy bb_pin_sink_count_new, - std::vector& bb_edge_new, - std::vector& bb_coord_new) { + const t_physical_tile_loc& pin_old_loc, + const t_physical_tile_loc& pin_new_loc, + const std::vector& curr_bb_edge, + const std::vector& curr_bb_coord, + vtr::NdMatrixProxy bb_pin_sink_count_new, + std::vector& bb_edge_new, + std::vector& bb_coord_new) { int x_old = pin_old_loc.x; int y_old = pin_old_loc.y; @@ -1088,31 +1035,31 @@ inline void NetCostHandler::update_bb_layer_changed_(ClusterNetId net_id, VTR_ASSERT_SAFE(old_layer_num != new_layer_num); /* - This funcitn is called when BB per layer is used and when the moving block is moving from one layer to another. - Thus, we need to update bounding box on both "from" and "to" layer. Here, we update the bounding box on "from" or - "old_layer". Then, "add_block_to_bb" is called to update the bounding box on the new layer. - */ + * This funcitn is called when BB per layer is used and when the moving block is moving from one layer to another. + * Thus, we need to update bounding box on both "from" and "to" layer. Here, we update the bounding box on "from" or + * "old_layer". Then, "add_block_to_bb" is called to update the bounding box on the new layer. + */ if (x_old == curr_bb_coord[old_layer_num].xmax) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[old_layer_num].xmax, - curr_bb_coord[old_layer_num].xmax, - bb_edge_new[old_layer_num].xmax, - bb_coord_new[old_layer_num].xmax); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[old_layer_num].xmax, + curr_bb_coord[old_layer_num].xmax, + bb_edge_new[old_layer_num].xmax, + bb_coord_new[old_layer_num].xmax); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } } else if (x_old == curr_bb_coord[old_layer_num].xmin) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[old_layer_num].xmin, - curr_bb_coord[old_layer_num].xmin, - bb_edge_new[old_layer_num].xmin, - bb_coord_new[old_layer_num].xmin); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[old_layer_num].xmin, + curr_bb_coord[old_layer_num].xmin, + bb_edge_new[old_layer_num].xmin, + bb_coord_new[old_layer_num].xmin); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } @@ -1120,25 +1067,25 @@ inline void NetCostHandler::update_bb_layer_changed_(ClusterNetId net_id, if (y_old == curr_bb_coord[old_layer_num].ymax) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[old_layer_num].ymax, - curr_bb_coord[old_layer_num].ymax, - bb_edge_new[old_layer_num].ymax, - bb_coord_new[old_layer_num].ymax); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[old_layer_num].ymax, + curr_bb_coord[old_layer_num].ymax, + bb_edge_new[old_layer_num].ymax, + bb_coord_new[old_layer_num].ymax); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } } else if (y_old == curr_bb_coord[old_layer_num].ymin) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[old_layer_num].ymin, - curr_bb_coord[old_layer_num].ymin, - bb_edge_new[old_layer_num].ymin, - bb_coord_new[old_layer_num].ymin); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[old_layer_num].ymin, + curr_bb_coord[old_layer_num].ymin, + bb_edge_new[old_layer_num].ymin, + bb_coord_new[old_layer_num].ymin); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } @@ -1167,18 +1114,18 @@ static void update_bb_pin_sink_count(const t_physical_tile_loc& pin_old_loc, } inline void NetCostHandler::update_bb_edge_(ClusterNetId net_id, - std::vector& bb_edge_new, - std::vector& bb_coord_new, - vtr::NdMatrixProxy bb_layer_pin_sink_count, - const int& old_num_block_on_edge, - const int& old_edge_coord, - int& new_num_block_on_edge, - int& new_edge_coord) { + std::vector& bb_edge_new, + std::vector& bb_coord_new, + vtr::NdMatrixProxy bb_layer_pin_sink_count, + const int& old_num_block_on_edge, + const int& old_edge_coord, + int& new_num_block_on_edge, + int& new_edge_coord) { if (old_num_block_on_edge == 1) { get_layer_bb_from_scratch_(net_id, - bb_edge_new, - bb_coord_new, - bb_layer_pin_sink_count); + bb_edge_new, + bb_coord_new, + bb_layer_pin_sink_count); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -1196,10 +1143,10 @@ static void add_block_to_bb(const t_physical_tile_loc& new_pin_loc, int y_new = new_pin_loc.y; /* - This function is called to only update the bounding box on the new layer from a block - moving to this layer from another layer. Thus, we only need to assess the effect of this - new block on the edges. - */ + * This function is called to only update the bounding box on the new layer from a block + * moving to this layer from another layer. Thus, we only need to assess the effect of this + * new block on the edges. + */ if (x_new > bb_coord_old.xmax) { bb_edge_new.xmax = 1; @@ -1230,15 +1177,16 @@ static void add_block_to_bb(const t_physical_tile_loc& new_pin_loc, } } -void NetCostHandler::get_bb_from_scratch_(ClusterNetId net_id, - t_bb& coords, - t_bb& num_on_edges, - vtr::NdMatrixProxy num_sink_pin_layer) { +void NetCostHandler::get_bb_from_scratch_(ClusterNetId net_id, bool use_ts) { const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& device_ctx = g_vpr_ctx.device(); const auto& grid = device_ctx.grid; const auto& blk_loc_registry = placer_state_.blk_loc_registry(); + t_bb& coords = use_ts ? ts_bb_coord_new_[net_id] : bb_coords_[net_id]; + t_bb& num_on_edges = use_ts ? ts_bb_edge_new_[net_id] : bb_num_on_edges_[net_id]; + vtr::NdMatrixProxy num_sink_pin_layer = use_ts ? ts_layer_sink_pin_count_[(size_t)net_id] : num_sink_pin_layer_[(size_t)net_id]; + // get the source pin's location ClusterPinId source_pin_id = cluster_ctx.clb_nlist.net_pin(net_id, 0); t_physical_tile_loc source_pin_loc = blk_loc_registry.get_coordinate_of_pin(source_pin_id); @@ -1382,12 +1330,11 @@ void NetCostHandler::get_layer_bb_from_scratch_(ClusterNetId net_id, } } - double NetCostHandler::get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts) { // Finds the cost due to one net by looking at its coordinate bounding box. auto& cluster_ctx = g_vpr_ctx.clustering(); - const t_bb& bb = use_ts ? ts_bb_coord_new_[net_id] : placer_state_.move().bb_coords[net_id]; + const t_bb& bb = use_ts ? ts_bb_coord_new_[net_id] : bb_coords_[net_id]; const double crossing = wirelength_crossing_count(cluster_ctx.clb_nlist.net_pins(net_id).size()); @@ -1417,20 +1364,15 @@ double NetCostHandler::get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts) { return ncost; } - -double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id , bool use_ts) { - const auto& move_ctx = placer_state_.move(); - +double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id, bool use_ts) { // Per-layer bounding box of the net - const std::vector& bb = use_ts ? layer_ts_bb_coord_new_[net_id] : move_ctx.layer_bb_coords[net_id]; - const vtr::NdMatrixProxy layer_pin_sink_count = use_ts ? ts_layer_sink_pin_count_[size_t(net_id)] : move_ctx.num_sink_pin_layer[size_t(net_id)]; + const std::vector& bb = use_ts ? layer_ts_bb_coord_new_[net_id] : layer_bb_coords_[net_id]; + const vtr::NdMatrixProxy layer_pin_sink_count = use_ts ? ts_layer_sink_pin_count_[size_t(net_id)] : num_sink_pin_layer_[size_t(net_id)]; // Finds the cost due to one net by looking at its coordinate bounding box double ncost = 0.; int num_layers = g_vpr_ctx.device().grid.get_num_layers(); - - for (int layer_num = 0; layer_num < num_layers; layer_num++) { VTR_ASSERT(layer_pin_sink_count[layer_num] != OPEN); if (layer_pin_sink_count[layer_num] == 0) { @@ -1454,7 +1396,7 @@ double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id , bool use * chan?_place_cost_fac_ objects can handle -1 indices internally. */ - const auto[chanx_cost_fac, chany_cost_fac] = get_chanxy_cost_fac_(bb[layer_num]); + const auto [chanx_cost_fac, chany_cost_fac] = get_chanxy_cost_fac_(bb[layer_num]); ncost += (bb[layer_num].xmax - bb[layer_num].xmin + 1) * chanx_cost_fac; ncost += (bb[layer_num].ymax - bb[layer_num].ymin + 1) * chany_cost_fac; ncost *= crossing; @@ -1463,7 +1405,8 @@ double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id , bool use return ncost; } -static double get_net_wirelength_estimate(ClusterNetId net_id, const t_bb& bb) { +double NetCostHandler::get_net_wirelength_estimate_(ClusterNetId net_id) const { + const t_bb& bb = bb_coords_[net_id]; auto& cluster_ctx = g_vpr_ctx.clustering(); double crossing = wirelength_crossing_count(cluster_ctx.clb_nlist.net_pins(net_id).size()); @@ -1482,23 +1425,26 @@ static double get_net_wirelength_estimate(ClusterNetId net_id, const t_bb& bb) { return ncost; } -double NetCostHandler::get_net_wirelength_from_layer_bb_(ClusterNetId net_id) { +double NetCostHandler::get_net_wirelength_from_layer_bb_(ClusterNetId net_id) const { /* WMF: Finds the estimate of wirelength due to one net by looking at * * its coordinate bounding box. */ - const auto& move_ctx = placer_state_.move(); - const std::vector& bb = move_ctx.layer_bb_coords[net_id]; - const auto& layer_pin_sink_count = move_ctx.num_sink_pin_layer[size_t(net_id)]; + const std::vector& bb = layer_bb_coords_[net_id]; + const vtr::NdMatrixProxy net_layer_pin_sink_count = num_sink_pin_layer_[size_t(net_id)]; double ncost = 0.; - const int num_layers = g_vpr_ctx.device().grid.get_num_layers(); + VTR_ASSERT_SAFE(static_cast(bb.size()) == g_vpr_ctx.device().grid.get_num_layers()); - for (int layer_num = 0; layer_num < num_layers; layer_num++) { - VTR_ASSERT_SAFE(layer_pin_sink_count[layer_num] != OPEN); - if (layer_pin_sink_count[layer_num] == 0) { + for (size_t layer_num = 0; layer_num < bb.size(); layer_num++) { + VTR_ASSERT_SAFE(net_layer_pin_sink_count[layer_num] != OPEN); + if (net_layer_pin_sink_count[layer_num] == 0) { continue; } - double crossing = wirelength_crossing_count(layer_pin_sink_count[layer_num] + 1); + + // The reason we add 1 to the number of sink pins is because when per-layer bounding box is used, + // we want to get the estimated wirelength of the given layer assuming that the source pin is + // also on that layer + double crossing = wirelength_crossing_count(net_layer_pin_sink_count[layer_num] + 1); /* Could insert a check for xmin == xmax. In that case, assume * * connection will be made with no bends and hence no x-cost. * @@ -1515,23 +1461,11 @@ double NetCostHandler::get_net_wirelength_from_layer_bb_(ClusterNetId net_id) { } float NetCostHandler::get_chanz_cost_factor_(const t_bb& bb) { - int num_inter_dir_conn; - - if (bb.xmin == 0 && bb.ymin == 0) { - num_inter_dir_conn = acc_tile_num_inter_die_conn_[bb.xmax][bb.ymax]; - } else if (bb.xmin == 0) { - num_inter_dir_conn = acc_tile_num_inter_die_conn_[bb.xmax][bb.ymax] - - acc_tile_num_inter_die_conn_[bb.xmax][bb.ymin-1]; - } else if (bb.ymin == 0) { - num_inter_dir_conn = acc_tile_num_inter_die_conn_[bb.xmax][bb.ymax] - - acc_tile_num_inter_die_conn_[bb.xmin-1][bb.ymax]; - } else { - num_inter_dir_conn = acc_tile_num_inter_die_conn_[bb.xmax][bb.ymax] - - acc_tile_num_inter_die_conn_[bb.xmin-1][bb.ymax] - - acc_tile_num_inter_die_conn_[bb.xmax][bb.ymin-1] + - acc_tile_num_inter_die_conn_[bb.xmin-1][bb.ymin-1]; - } - + int num_inter_dir_conn = acc_tile_num_inter_die_conn_.get_sum(bb.xmin, + bb.ymin, + bb.xmax, + bb.ymax); + float z_cost_factor; if (num_inter_dir_conn == 0) { return 1.0f; @@ -1541,7 +1475,6 @@ float NetCostHandler::get_chanz_cost_factor_(const t_bb& bb) { } return z_cost_factor; - } double NetCostHandler::recompute_bb_cost_() { @@ -1549,8 +1482,8 @@ double NetCostHandler::recompute_bb_cost_() { auto& cluster_ctx = g_vpr_ctx.clustering(); - for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { /* for each net ... */ - if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ + for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { /* for each net ... */ + if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ /* Bounding boxes don't have to be recomputed; they're correct. */ cost += net_cost_[net_id]; } @@ -1571,7 +1504,7 @@ static double wirelength_crossing_count(size_t fanout) { } void NetCostHandler::set_bb_delta_cost_(double& bb_delta_c) { - for (const ClusterNetId ts_net: ts_nets_to_update_) { + for (const ClusterNetId ts_net : ts_nets_to_update_) { ClusterNetId net_id = ts_net; proposed_net_cost_[net_id] = get_net_bb_cost_functor_(net_id); @@ -1621,7 +1554,6 @@ void NetCostHandler::find_affected_nets_and_update_costs(const PlaceDelayModel* void NetCostHandler::update_move_nets() { /* update net cost functions and reset flags. */ auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_move_ctx = placer_state_.mutable_move(); for (const ClusterNetId ts_net : ts_nets_to_update_) { ClusterNetId net_id = ts_net; @@ -1629,7 +1561,7 @@ void NetCostHandler::update_move_nets() { set_ts_bb_coord_(net_id); for (int layer_num = 0; layer_num < g_vpr_ctx.device().grid.get_num_layers(); layer_num++) { - place_move_ctx.num_sink_pin_layer[size_t(net_id)][layer_num] = ts_layer_sink_pin_count_[size_t(net_id)][layer_num]; + num_sink_pin_layer_[size_t(net_id)][layer_num] = ts_layer_sink_pin_count_[size_t(net_id)][layer_num]; } if (cluster_ctx.clb_nlist.net_sinks(net_id).size() >= SMALL_NET) { @@ -1682,20 +1614,146 @@ void NetCostHandler::recompute_costs_from_scratch(const PlaceDelayModel* delay_m } } +double NetCostHandler::get_total_wirelength_estimate() const { + const auto& clb_nlist = g_vpr_ctx.clustering().clb_nlist; + + double estimated_wirelength = 0.0; + for (ClusterNetId net_id : clb_nlist.nets()) { /* for each net ... */ + if (!clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ + if (cube_bb_) { + estimated_wirelength += get_net_wirelength_estimate_(net_id); + } else { + estimated_wirelength += get_net_wirelength_from_layer_bb_(net_id); + } + } + } + + return estimated_wirelength; +} + void NetCostHandler::set_ts_bb_coord_(const ClusterNetId net_id) { - auto& place_move_ctx = placer_state_.mutable_move(); if (cube_bb_) { - place_move_ctx.bb_coords[net_id] = ts_bb_coord_new_[net_id]; + bb_coords_[net_id] = ts_bb_coord_new_[net_id]; } else { - place_move_ctx.layer_bb_coords[net_id] = layer_ts_bb_coord_new_[net_id]; + layer_bb_coords_[net_id] = layer_ts_bb_coord_new_[net_id]; } } void NetCostHandler::set_ts_edge_(const ClusterNetId net_id) { - auto& place_move_ctx = placer_state_.mutable_move(); if (cube_bb_) { - place_move_ctx.bb_num_on_edges[net_id] = ts_bb_edge_new_[net_id]; + bb_num_on_edges_[net_id] = ts_bb_edge_new_[net_id]; } else { - place_move_ctx.layer_bb_num_on_edges[net_id] = layer_ts_bb_edge_new_[net_id]; + layer_bb_num_on_edges_[net_id] = layer_ts_bb_edge_new_[net_id]; + } +} + +t_bb NetCostHandler::union_2d_bb(ClusterNetId net_id) const { + t_bb merged_bb; + const std::vector& bb_vec = layer_bb_coords_[net_id]; + + // Not all 2d_bbs are valid. Thus, if one of the coordinates in the 2D_bb is not valid (equal to OPEN), + // we need to skip it. + for (const t_2D_bb& layer_bb : bb_vec) { + if (layer_bb.xmin == OPEN) { + VTR_ASSERT_DEBUG(layer_bb.xmax == OPEN); + VTR_ASSERT_DEBUG(layer_bb.ymin == OPEN); + VTR_ASSERT_DEBUG(layer_bb.ymax == OPEN); + VTR_ASSERT_DEBUG(layer_bb.layer_num == OPEN); + continue; + } + if (merged_bb.xmin == OPEN || layer_bb.xmin < merged_bb.xmin) { + merged_bb.xmin = layer_bb.xmin; + } + if (merged_bb.xmax == OPEN || layer_bb.xmax > merged_bb.xmax) { + merged_bb.xmax = layer_bb.xmax; + } + if (merged_bb.ymin == OPEN || layer_bb.ymin < merged_bb.ymin) { + merged_bb.ymin = layer_bb.ymin; + } + if (merged_bb.ymax == OPEN || layer_bb.ymax > merged_bb.ymax) { + merged_bb.ymax = layer_bb.ymax; + } + if (merged_bb.layer_min == OPEN || layer_bb.layer_num < merged_bb.layer_min) { + merged_bb.layer_min = layer_bb.layer_num; + } + if (merged_bb.layer_max == OPEN || layer_bb.layer_num > merged_bb.layer_max) { + merged_bb.layer_max = layer_bb.layer_num; + } } + + return merged_bb; +} + +std::pair NetCostHandler::union_2d_bb_incr(ClusterNetId net_id) const { + t_bb merged_num_edge; + t_bb merged_bb; + + const std::vector& num_edge_vec = layer_bb_num_on_edges_[net_id]; + const std::vector& bb_vec = layer_bb_coords_[net_id]; + + for (const t_2D_bb& layer_bb : bb_vec) { + if (layer_bb.xmin == OPEN) { + VTR_ASSERT_SAFE(layer_bb.xmax == OPEN); + VTR_ASSERT_SAFE(layer_bb.ymin == OPEN); + VTR_ASSERT_SAFE(layer_bb.ymax == OPEN); + VTR_ASSERT_SAFE(layer_bb.layer_num == OPEN); + continue; + } + if (merged_bb.xmin == OPEN || layer_bb.xmin <= merged_bb.xmin) { + if (layer_bb.xmin == merged_bb.xmin) { + VTR_ASSERT_SAFE(merged_num_edge.xmin != OPEN); + merged_num_edge.xmin += num_edge_vec[layer_bb.layer_num].xmin; + } else { + merged_num_edge.xmin = num_edge_vec[layer_bb.layer_num].xmin; + } + merged_bb.xmin = layer_bb.xmin; + } + if (merged_bb.xmax == OPEN || layer_bb.xmax >= merged_bb.xmax) { + if (layer_bb.xmax == merged_bb.xmax) { + VTR_ASSERT_SAFE(merged_num_edge.xmax != OPEN); + merged_num_edge.xmax += num_edge_vec[layer_bb.layer_num].xmax; + } else { + merged_num_edge.xmax = num_edge_vec[layer_bb.layer_num].xmax; + } + merged_bb.xmax = layer_bb.xmax; + } + if (merged_bb.ymin == OPEN || layer_bb.ymin <= merged_bb.ymin) { + if (layer_bb.ymin == merged_bb.ymin) { + VTR_ASSERT_SAFE(merged_num_edge.ymin != OPEN); + merged_num_edge.ymin += num_edge_vec[layer_bb.layer_num].ymin; + } else { + merged_num_edge.ymin = num_edge_vec[layer_bb.layer_num].ymin; + } + merged_bb.ymin = layer_bb.ymin; + } + if (merged_bb.ymax == OPEN || layer_bb.ymax >= merged_bb.ymax) { + if (layer_bb.ymax == merged_bb.ymax) { + VTR_ASSERT_SAFE(merged_num_edge.ymax != OPEN); + merged_num_edge.ymax += num_edge_vec[layer_bb.layer_num].ymax; + } else { + merged_num_edge.ymax = num_edge_vec[layer_bb.layer_num].ymax; + } + merged_bb.ymax = layer_bb.ymax; + } + if (merged_bb.layer_min == OPEN || layer_bb.layer_num <= merged_bb.layer_min) { + if (layer_bb.layer_num == merged_bb.layer_min) { + VTR_ASSERT_SAFE(merged_num_edge.layer_min != OPEN); + merged_num_edge.layer_min += num_edge_vec[layer_bb.layer_num].layer_num; + } else { + merged_num_edge.layer_min = num_edge_vec[layer_bb.layer_num].layer_num; + } + merged_bb.layer_min = layer_bb.layer_num; + } + if (merged_bb.layer_max == OPEN || layer_bb.layer_num >= merged_bb.layer_max) { + if (layer_bb.layer_num == merged_bb.layer_max) { + VTR_ASSERT_SAFE(merged_num_edge.layer_max != OPEN); + merged_num_edge.layer_max += num_edge_vec[layer_bb.layer_num].layer_num; + } else { + merged_num_edge.layer_max = num_edge_vec[layer_bb.layer_num].layer_num; + } + merged_bb.layer_max = layer_bb.layer_num; + } + } + + return std::make_pair(merged_num_edge, merged_bb); } diff --git a/vpr/src/place/net_cost_handler.h b/vpr/src/place/net_cost_handler.h index 2b8e59af88f..ee60d5ed348 100644 --- a/vpr/src/place/net_cost_handler.h +++ b/vpr/src/place/net_cost_handler.h @@ -7,14 +7,14 @@ #pragma once #include "place_delay_model.h" -#include "timing_place.h" #include "move_transactions.h" #include "place_util.h" -#include "vtr_ndoffsetmatrix.h" +#include "vtr_prefix_sum.h" #include class PlacerState; +class PlacerCriticalities; /** * @brief The method used to calculate placement cost @@ -29,7 +29,6 @@ enum class e_cost_methods { CHECK }; - class NetCostHandler { public: NetCostHandler() = delete; @@ -59,33 +58,35 @@ class NetCostHandler { * non_updateable_bb routine, to provide a cost which can be * used to check the correctness of the other routine. * @param method The method used to calculate placement cost. - * @return The bounding box cost of the placement. - */ - double comp_bb_cost(e_cost_methods method); - - /** - * @brief Find all the nets and pins affected by this swap and update costs. - * - * Find all the nets affected by this swap and update the bounding box (wiring) - * costs. This cost function doesn't depend on the timing info. - * - * Find all the connections affected by this swap and update the timing cost. - * For a connection to be affected, it not only needs to be on or driven by - * a block, but it also needs to have its delay changed. Otherwise, it will - * not be added to the affected_pins structure. - * - * For more, see update_td_delta_costs(). - * - * The timing costs are calculated by getting the new connection delays, - * multiplied by the connection criticalities returned by the timing - * analyzer. These timing costs are stored in the proposed_* data structures. - * - * The change in the bounding box cost is stored in `bb_delta_c`. - * The change in the timing cost is stored in `timing_delta_c`. - * ts_nets_to_update is also extended with the latest net. - * - * @return The number of affected nets. - */ + * @return (bounding box cost of the placement, estimated wirelength) + * + * @note The returned estimated wirelength is valid only when method == CHECK + */ + std::pair comp_bb_cost(e_cost_methods method); + + /** + * @brief Find all the nets and pins affected by this swap and update costs. + * + * Find all the nets affected by this swap and update the bounding box (wiring) + * costs. This cost function doesn't depend on the timing info. + * + * Find all the connections affected by this swap and update the timing cost. + * For a connection to be affected, it not only needs to be on or driven by + * a block, but it also needs to have its delay changed. Otherwise, it will + * not be added to the affected_pins structure. + * + * For more, see update_td_delta_costs(). + * + * The timing costs are calculated by getting the new connection delays, + * multiplied by the connection criticalities returned by the timing + * analyzer. These timing costs are stored in the proposed_* data structures. + * + * The change in the bounding box cost is stored in `bb_delta_c`. + * The change in the timing cost is stored in `timing_delta_c`. + * ts_nets_to_update is also extended with the latest net. + * + * @return The number of affected nets. + */ void find_affected_nets_and_update_costs(const PlaceDelayModel* delay_model, const PlacerCriticalities* criticalities, t_pl_blocks_to_be_moved& blocks_affected, @@ -120,6 +121,11 @@ class NetCostHandler { const PlacerCriticalities* criticalities, t_placer_costs& costs); + /** + * @brief Get the total wirelength estimate of all nets. + */ + double get_total_wirelength_estimate() const; + private: ///@brief Specifies whether the bounding box is computed using cube method or per-layer method. bool cube_bb_; @@ -130,7 +136,7 @@ class NetCostHandler { ///@brief Contains some parameter that determine how the placement cost is computed. const t_placer_opts& placer_opts_; ///@brief Points to the proper method for computing the bounding box cost from scratch. - std::function comp_bb_cost_functor_; + std::function(e_cost_methods method)> comp_bb_cost_functor_; ///@brief Points to the proper method for updating the bounding box of a net. std::function update_bb_functor_; ///@brief Points to the proper method for getting the bounding box cost of a net @@ -148,12 +154,20 @@ class NetCostHandler { }; /** - * @brief The wire length estimation is based on the bounding box of the net. In the case of the 2D architecture, - * we use a 3D BB with the z-dimension (layer) set to 1. In the case of 3D architecture, there 2 types of bounding box: - * 3D and per-layer. The type is determined at the beginning of the placement and stored in the placement context. - * If the bonding box is of the type 3D, ts_bb_coord_new and ts_bb_edge_new are used. Otherwise, layer_ts_bb_edge_new and - * layer_ts_bb_coord_new are used. + * @brief The wire length estimation is based on the bounding box of the net. + * + * For 2D architectures, we use a 3D bounding box with the layer (z) set to 1. + * For 3D architectures, we support two types: full 3D and per-layer bounding boxes. + * The type is set at the start of placement and stored in the placement context. + * + * If using full 3D, `ts_bb_coord_new_` and `ts_bb_edge_new_` are used. + * If using per-layer, `layer_ts_bb_coord_new_` and `layer_ts_bb_edge_new_` are used. + * + * Temporary `ts_*` data members store the bounding box updates for nets affected by a move. + * If the move is accepted, these updates are copied to the permanent data members that store + * bounding box information for all nets. */ + /* [0...cluster_ctx.clb_nlist.nets().size()-1] -> 3D bounding box*/ vtr::vector ts_bb_coord_new_, ts_bb_edge_new_; /* [0...cluster_ctx.clb_nlist.nets().size()-1][0...num_layers-1] -> 2D bonding box on a layer*/ @@ -163,6 +177,20 @@ class NetCostHandler { /* [0...num_affected_nets] -> net_id of the affected nets */ std::vector ts_nets_to_update_; + // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the number of blocks on each of a net's bounding box (to allow efficient updates) + vtr::vector bb_num_on_edges_; + + // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the bounding box coordinates of a net's bounding box + vtr::vector bb_coords_; + + // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the number of blocks on each of a net's bounding box (to allow efficient updates) + vtr::vector> layer_bb_num_on_edges_; + + // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the bounding box coordinates of a net's bounding box + vtr::vector> layer_bb_coords_; + + // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the number of blocks on each layer () + vtr::Matrix num_sink_pin_layer_; /** * @brief In each of these vectors, there is one entry per cluster level net: @@ -195,8 +223,8 @@ class NetCostHandler { * number of tracks in that direction; for other cost functions they * will never be used. */ - vtr::NdOffsetMatrix acc_chanx_width_; // [-1...device_ctx.grid.width()-1] - vtr::NdOffsetMatrix acc_chany_width_; // [-1...device_ctx.grid.height()-1] + vtr::PrefixSum1D acc_chanx_width_; // [0..device_ctx.grid.width()-1] + vtr::PrefixSum1D acc_chany_width_; // [0..device_ctx.grid.height()-1] /** * @brief The matrix below is used to calculate a chanz_place_cost_fac based on the average channel width in @@ -206,31 +234,30 @@ class NetCostHandler { * (x=0,y=0) to (x,y). Given this, we can compute the average number of inter-die connections over a (xlow,ylow) to (xhigh,yhigh) * region in O(1) (by adding and subtracting 4 entries) */ - vtr::NdMatrix acc_tile_num_inter_die_conn_; // [0..grid_width-1][0..grid_height-1] - + vtr::PrefixSum2D acc_tile_num_inter_die_conn_; // [0..grid_width-1][0..grid_height-1] private: /** - * @brief Update the bounding box (3D) of the net connected to blk_pin. The old and new locations of the pin are - * stored in pl_moved_block. The updated bounding box will be stored in ts data structures. Do not update the net - * cost here since it should only be updated once per net, not once per pin. - */ + * @brief Update the bounding box (3D) of the net connected to blk_pin. The old and new locations of the pin are + * stored in pl_moved_block. The updated bounding box will be stored in ts data structures. Do not update the net + * cost here since it should only be updated once per net, not once per pin. + */ void update_net_bb_(const ClusterNetId net, const ClusterBlockId blk, const ClusterPinId blk_pin, const t_pl_moved_block& pl_moved_block); /** - * @brief Call suitable function based on the bounding box type to update the bounding box of the net connected to pin_id. Also, - * call the function to update timing information if the placement algorithm is timing-driven. - * @param delay_model Timing delay model used by placer - * @param criticalities Connections timing criticalities - * @param pin_id Pin ID of the moving pin - * @param moving_blk_inf Data structure that holds information, e.g., old location and new location, about all moving blocks - * @param affected_pins Netlist pins which are affected, in terms placement cost, by the proposed move. - * @param timing_delta_c Timing cost change based on the proposed move - * @param is_src_moving Is the moving pin the source of a net. - */ + * @brief Call suitable function based on the bounding box type to update the bounding box of the net connected to pin_id. Also, + * call the function to update timing information if the placement algorithm is timing-driven. + * @param delay_model Timing delay model used by placer + * @param criticalities Connections timing criticalities + * @param pin_id Pin ID of the moving pin + * @param moving_blk_inf Data structure that holds information, e.g., old location and new location, about all moving blocks + * @param affected_pins Netlist pins which are affected, in terms placement cost, by the proposed move. + * @param timing_delta_c Timing cost change based on the proposed move + * @param is_src_moving Is the moving pin the source of a net. + */ void update_net_info_on_pin_move_(const PlaceDelayModel* delay_model, const PlacerCriticalities* criticalities, const ClusterPinId pin_id, @@ -240,10 +267,10 @@ class NetCostHandler { bool is_src_moving); /** - * @brief Calculates and returns the total bb (wirelength) cost change that would result from moving the blocks - * indicated in the blocks_affected data structure. - * @param bb_delta_c Cost difference after and before moving the block - */ + * @brief Calculates and returns the total bb (wirelength) cost change that would result from moving the blocks + * indicated in the blocks_affected data structure. + * @param bb_delta_c Cost difference after and before moving the block + */ void set_bb_delta_cost_(double& bb_delta_c); /** @@ -253,18 +280,16 @@ class NetCostHandler { * @details This is only useful for the cost function that takes the length of the net bounding box in each * dimension divided by the average number of tracks in that direction. For other cost functions, you don't * have to bother calling this routine; when using the cost function described above, however, you must always - * call this routine before you do any placement cost determination. The place_cost_exp factor specifies to - * what power the width of the channel should be taken -- larger numbers make narrower channels more expensive. + * call this routine before you do any placement cost determination. */ void alloc_and_load_chan_w_factors_for_place_cost_(); /** - * @brief Allocates and loads acc_tile_num_inter_die_conn_ which contains the accumulative number of inter-die - * conntections. - * - * @details This is only useful for multi-die FPGAs. The place_cost_exp factor specifies to - * what power the average number of inter-die connections should be take -- larger numbers make narrower channels more expensive. - */ + * @brief Allocates and loads acc_tile_num_inter_die_conn_ which contains the accumulative number of inter-die + * conntections. + * + * @details This is only useful for multi-die FPGAs. + */ void alloc_and_load_for_fast_vertical_cost_update_(); /** @@ -325,14 +350,9 @@ class NetCostHandler { * It updates both the coordinate and number of pins on each edge information. It should only be called when the bounding box * information is not valid. * @param net_id ID of the net which the moving pin belongs to - * @param coords Bounding box coordinates of the net. It is calculated in this function - * @param num_on_edges Net's number of blocks on the edges of the bounding box. It is calculated in this function. - * @param num_sink_pin_layer Net's number of sinks on each layer, calculated in this function. + * @param use_ts Specifies whether the `ts` bounding box is updated or the actual one. */ - void get_bb_from_scratch_(ClusterNetId net_id, - t_bb& coords, - t_bb& num_on_edges, - vtr::NdMatrixProxy num_sink_pin_layer); + void get_bb_from_scratch_(ClusterNetId net_id, bool use_ts); /** * @brief Calculate the per-layer BB of a large net from scratch and update coord, edge, and num_sink_pin_layer data structures. @@ -413,8 +433,8 @@ class NetCostHandler { int& new_edge_coord); /** - * @brief This function is called in update_layer_bb to update the net's bounding box incrementally if - * the pin under consideration change layer. + * @brief This function is called in update_layer_bb to update the net's bounding box incrementally if + * the pin under consideration change layer. * @param net_id ID of the net which the moving pin belongs to * @param pin_old_loc Old location of the moving pin * @param pin_new_loc New location of the moving pin @@ -445,70 +465,66 @@ class NetCostHandler { * @param bb_edge_new The new bb edge calculated by this function * @param bb_coord_new The new bb calculated by this function */ - inline void update_bb_same_layer_(ClusterNetId net_id, - const t_physical_tile_loc& pin_old_loc, - const t_physical_tile_loc& pin_new_loc, - const std::vector& curr_bb_edge, - const std::vector& curr_bb_coord, - vtr::NdMatrixProxy bb_pin_sink_count_new, - std::vector& bb_edge_new, - std::vector& bb_coord_new); - - /** - * @brief Computes the bounding box from scratch using 2D bounding boxes (per-layer mode) - * @param method The method used to calculate placement cost. Specifies whether the cost is - * computed from scratch or incrementally. - * @return Computed bounding box cost. - */ - double comp_per_layer_bb_cost_(e_cost_methods method); - - /** - * @brief Computes the bounding box from scratch using 3D bounding boxes (cube mode) - * @param method The method used to calculate placement cost. Specifies whether the cost is - * computed from scratch or incrementally. - * @return Computed bounding box cost. - */ - double comp_cube_bb_cost_(e_cost_methods method); - - /** - * @brief if "net" is not already stored as an affected net, add it in ts_nets_to_update. - * @param net ID of a net affected by a move - */ - void record_affected_net_(const ClusterNetId net); - - /** - * @brief To mitigate round-off errors, every once in a while, the costs of nets are summed up from scratch. - * This functions is called to do that for bb cost. It doesn't calculate the BBs from scratch, it would only add the costs again. - * @return Total bb (wirelength) cost for the placement - */ - double recompute_bb_cost_(); - - /** - * @brief Given the 3D BB, calculate the wire-length cost of the net - * @param net_id ID of the net which cost is requested. - * @param use_ts Specifies if the bounding box is retrieved from ts data structures - * or move context. - * @return Wirelength cost of the net - */ - double get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts); - - /** - * @brief Given the per-layer BB, calculate the wire-length cost of the net on each layer - * and return the sum of the costs - * @param net_id ID of the net which cost is requested. Currently unused - * @param use_ts Specifies whether the 'ts` bounding box is used to compute the - * cost or the one stored in placer_state_ - * @return Wirelength cost of the net - */ - double get_net_per_layer_bb_cost_(ClusterNetId net_id, bool use_ts); + inline void update_bb_same_layer_(ClusterNetId net_id, + const t_physical_tile_loc& pin_old_loc, + const t_physical_tile_loc& pin_new_loc, + const std::vector& curr_bb_edge, + const std::vector& curr_bb_coord, + vtr::NdMatrixProxy bb_pin_sink_count_new, + std::vector& bb_edge_new, + std::vector& bb_coord_new); /** - * @brief Given the per-layer BB, calculate the wire-length estimate of the net on each layer - * and return the sum of the lengths - * @param net_id ID of the net which wirelength estimate is requested - * @return Wirelength estimate of the net + * @brief Computes the bounding box from scratch using 2D bounding boxes (per-layer mode) + * @param method The method used to calculate placement cost. Specifies whether the cost is + * computed from scratch or incrementally. + * @return (bounding box cost of the placement, estimated wirelength) + * + * @note The returned estimated wirelength is valid only when method == CHECK + */ + std::pair comp_per_layer_bb_cost_(e_cost_methods method); + + /** + * @brief Computes the bounding box from scratch using 3D bounding boxes (cube mode) + * @param method The method used to calculate placement cost. Specifies whether the cost is + * computed from scratch or incrementally. + * @return (bounding box cost of the placement, estimated wirelength) + * + * @note The returned estimated wirelength is valid only when method == CHECK + */ + std::pair comp_cube_bb_cost_(e_cost_methods method); + + /** + * @brief if "net" is not already stored as an affected net, add it in ts_nets_to_update. + * @param net ID of a net affected by a move + */ + void record_affected_net_(const ClusterNetId net); + + /** + * @brief To mitigate round-off errors, every once in a while, the costs of nets are summed up from scratch. + * This functions is called to do that for bb cost. It doesn't calculate the BBs from scratch, it would only add the costs again. + * @return Total bb (wirelength) cost for the placement + */ + double recompute_bb_cost_(); + + /** + * @brief Given the 3D BB, calculate the wire-length cost of the net + * @param net_id ID of the net which cost is requested. + * @param use_ts Specifies if the bounding box is retrieved from ts data structures + * or move context. + * @return Wirelength cost of the net */ - double get_net_wirelength_from_layer_bb_(ClusterNetId net_id); + double get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts); + + /** + * @brief Given the per-layer BB, calculate the wire-length cost of the net on each layer + * and return the sum of the costs + * @param net_id ID of the net which cost is requested. Currently unused + * @param use_ts Specifies whether the 'ts` bounding box is used to compute the + * cost or the one stored in placer_state_ + * @return Wirelength cost of the net + */ + double get_net_per_layer_bb_cost_(ClusterNetId net_id, bool use_ts); /** * @brief Computes the inverse of average channel width for horizontal and @@ -522,10 +538,10 @@ class NetCostHandler { */ template std::pair get_chanxy_cost_fac_(const BBT& bb) { - const int total_chanx_width = acc_chanx_width_[bb.ymax] - acc_chanx_width_[bb.ymin - 1]; + const int total_chanx_width = acc_chanx_width_.get_sum(bb.ymin, bb.ymax); const double inverse_average_chanx_width = (bb.ymax - bb.ymin + 1.0) / total_chanx_width; - const int total_chany_width = acc_chany_width_[bb.xmax] - acc_chany_width_[bb.xmin - 1]; + const int total_chany_width = acc_chany_width_.get_sum(bb.xmin, bb.xmax); const double inverse_average_chany_width = (bb.xmax - bb.xmin + 1.0) / total_chany_width; return {inverse_average_chanx_width, inverse_average_chany_width}; @@ -541,6 +557,42 @@ class NetCostHandler { * @param bb Bounding box of the net which chanz cost factor is to be calculated * @return ChanZ cost factor */ - float get_chanz_cost_factor_(const t_bb& bb); + float get_chanz_cost_factor_(const t_bb& bb); + + /** + * @brief Given the 3D BB, calculate the wire-length estimate of the net + * @param net_id ID of the net which wirelength estimate is requested + * @param bb Bounding box of the net + * @return Wirelength estimate of the net + */ + double get_net_wirelength_estimate_(ClusterNetId net_id) const; + + /** + * @brief Given the per-layer BB, calculate the wire-length estimate of the net on each layer + * and return the sum of the lengths + * @param bb Per-layer BB of the net + * @param net_layer_pin_sink_count Number of sink pins on each layer for the net + * @return Wirelength estimate of the net + */ + double get_net_wirelength_from_layer_bb_(ClusterNetId net_id) const; + + // Bounding-box getters + public: + inline const t_bb& bb_num_on_edges(ClusterNetId net_id) const { return bb_num_on_edges_[net_id]; } + inline const t_bb& bb_coords(ClusterNetId net_id) const { return bb_coords_[net_id]; } + + /** + * @brief Iterate over all layers and get the maximum x and y over that layers that have a valid value. set the layer min and max + * based on the layers that have a valid BB. + * @return 3D bounding box + */ + t_bb union_2d_bb(ClusterNetId net_id) const; + + /** + * @brief Iterate over all layers and get the maximum x and y over that layers that have a valid value. Create the "num_edge" in a similar way. This data structure + * stores how many blocks are on each edge of the BB. set the layer min and max based on the layers that have a valid BB. + * @return num_edge, 3D bb + */ + std::pair union_2d_bb_incr(ClusterNetId net_id) const; }; diff --git a/vpr/src/place/noc_place_utils.cpp b/vpr/src/place/noc_place_utils.cpp index 9f5fbb6045d..569408bb354 100644 --- a/vpr/src/place/noc_place_utils.cpp +++ b/vpr/src/place/noc_place_utils.cpp @@ -2,6 +2,8 @@ #include "noc_place_utils.h" #include "globals.h" +#include "physical_types_util.h" +#include "place_macro.h" #include "vtr_log.h" #include "vtr_assert.h" #include "vtr_random.h" @@ -20,7 +22,6 @@ #include #include - /** * @brief Randomly select a movable NoC router cluster blocks * @@ -79,8 +80,8 @@ void NocCostHandler::initial_noc_routing(const vtr::vector calculate_traffic_flow_latency_cost(const std::vector< noc_router_latency_component = noc_router_latency * num_of_routers_in_traffic_flow; } - // calculate the total traffic flow latency double latency = noc_router_latency_component + noc_link_latency_component; @@ -686,10 +686,10 @@ double NocCostHandler::get_link_congestion_cost(const NocLink& link) const { void normalize_noc_cost_weighting_factor(t_noc_opts& noc_opts) { // calculate the sum of all weighting factors - double weighting_factor_sum = noc_opts.noc_latency_weighting + - noc_opts.noc_latency_constraints_weighting + - noc_opts.noc_congestion_weighting + - noc_opts.noc_aggregate_bandwidth_weighting; + double weighting_factor_sum = noc_opts.noc_latency_weighting + + noc_opts.noc_latency_constraints_weighting + + noc_opts.noc_congestion_weighting + + noc_opts.noc_aggregate_bandwidth_weighting; // Normalize weighting factor so they add up to 1 noc_opts.noc_aggregate_bandwidth_weighting /= weighting_factor_sum; @@ -871,6 +871,7 @@ static bool select_random_router_cluster(ClusterBlockId& b_from, e_create_move propose_router_swap(t_pl_blocks_to_be_moved& blocks_affected, float rlim, const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, vtr::RngContainer& rng) { // block ID for the randomly selected router cluster ClusterBlockId b_from; @@ -898,7 +899,7 @@ e_create_move propose_router_swap(t_pl_blocks_to_be_moved& blocks_affected, return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { @@ -1000,26 +1001,25 @@ void NocCostHandler::print_noc_costs(std::string_view header, const t_placer_costs& costs, const t_noc_opts& noc_opts) const { VTR_LOG("%s. " - "cost: %g, " - "aggregate_bandwidth_cost: %g, " - "latency_cost: %g, " - "n_met_latency_constraints: %d, " - "latency_overrun_cost: %g, " - "congestion_cost: %g, " - "accum_congested_ratio: %g, " - "n_congested_links: %d \n", - header.data(), - calculate_noc_cost(costs.noc_cost_terms, costs.noc_cost_norm_factors, noc_opts), - costs.noc_cost_terms.aggregate_bandwidth, - costs.noc_cost_terms.latency, - get_number_of_traffic_flows_with_latency_cons_met(), - costs.noc_cost_terms.latency_overrun, - costs.noc_cost_terms.congestion, - get_total_congestion_bandwidth_ratio(), - get_number_of_congested_noc_links()); + "cost: %g, " + "aggregate_bandwidth_cost: %g, " + "latency_cost: %g, " + "n_met_latency_constraints: %d, " + "latency_overrun_cost: %g, " + "congestion_cost: %g, " + "accum_congested_ratio: %g, " + "n_congested_links: %d \n", + header.data(), + calculate_noc_cost(costs.noc_cost_terms, costs.noc_cost_norm_factors, noc_opts), + costs.noc_cost_terms.aggregate_bandwidth, + costs.noc_cost_terms.latency, + get_number_of_traffic_flows_with_latency_cons_met(), + costs.noc_cost_terms.latency_overrun, + costs.noc_cost_terms.congestion, + get_total_congestion_bandwidth_ratio(), + get_number_of_congested_noc_links()); } - static std::vector find_affected_links_by_flow_reroute(std::vector& prev_links, std::vector& curr_links) { // Sort both link containers diff --git a/vpr/src/place/noc_place_utils.h b/vpr/src/place/noc_place_utils.h index 0224ef78af8..a71963b8f10 100644 --- a/vpr/src/place/noc_place_utils.h +++ b/vpr/src/place/noc_place_utils.h @@ -5,6 +5,8 @@ #include "move_utils.h" #include "place_util.h" +class PlaceMacros; + /** * @class NocCostHandler is responsible for computing NoC-related costs terms. * @@ -192,7 +194,7 @@ class NocCostHandler { * * @param costs Contains the normalization factors which need to be updated */ - static void update_noc_normalization_factors(t_placer_costs& costs) ; + static void update_noc_normalization_factors(t_placer_costs& costs); /** * @brief Calculates the aggregate bandwidth of each traffic flow in the NoC @@ -443,7 +445,6 @@ class NocCostHandler { NocRouting& noc_flows_router, std::unordered_set& updated_traffic_flows); - /** * @brief Removes the route of a traffic flow and updates the links to indicate * that the traffic flow does not use them. And then finds @@ -486,7 +487,6 @@ class NocCostHandler { */ static constexpr double MAX_INV_NOC_LATENCY_COST = 1.e12; - /** * @brief Represents the minimum link bandwidth over-utilization for that link to be considered congested. * @details If a link is overloaded by less than 0.1% of the link bandwidth capacity, @@ -626,8 +626,6 @@ double calculate_noc_cost(const NocCostTerms& cost_terms, const NocCostTerms& norm_factors, const t_noc_opts& noc_opts); - - /* Below are functions related to the feature that forces to the placer to swap router blocks for a certain percentage of the total number of swaps */ /** @@ -662,6 +660,7 @@ bool check_for_router_swap(int user_supplied_noc_router_swap_percentage, e_create_move propose_router_swap(t_pl_blocks_to_be_moved& blocks_affected, float rlim, const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, vtr::RngContainer& rng); /** @@ -683,8 +682,6 @@ e_create_move propose_router_swap(t_pl_blocks_to_be_moved& blocks_affected, void write_noc_placement_file(const std::string& file_name, const vtr::vector_map& block_locs); - - /** * @brief Check if the channel dependency graph created from the given traffic flow routes * has any cycles. @@ -708,5 +705,4 @@ bool noc_routing_has_cycle(const vtr::vector - +#include + +#include "flat_placement_types.h" +#include "initial_placement.h" +#include "load_flat_place.h" +#include "noc_place_utils.h" +#include "pack.h" +#include "vpr_context.h" #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_time.h" @@ -10,17 +17,9 @@ #include "globals.h" #include "place.h" #include "annealer.h" -#include "read_xml_arch_file.h" #include "echo_files.h" -#include "histogram.h" -#include "place_delay_model.h" -#include "move_utils.h" -#include "buttons.h" - -#include "VprTimingGraphResolver.h" -#include "tatum/TimingReporter.hpp" +#include "PlacementDelayModelCreator.h" -#include "RL_agent_util.h" #include "placer.h" /********************* Static subroutines local to place.c *******************/ @@ -28,15 +27,6 @@ void print_clb_placement(const char* fname); #endif -/** - * @brief determine the type of the bounding box used by the placer to predict the wirelength - * - * @param place_bb_mode The bounding box mode passed by the CLI - * @param rr_graph The routing resource graph - */ -static bool is_cube_bb(const e_place_bounding_box_mode place_bb_mode, - const RRGraphView& rr_graph); - /*****************************************************************************/ void try_place(const Netlist<>& net_list, const t_placer_opts& placer_opts, @@ -47,6 +37,7 @@ void try_place(const Netlist<>& net_list, t_det_routing_arch* det_routing_arch, std::vector& segment_inf, const std::vector& directs, + const FlatPlacementInfo& flat_placement_info, bool is_flat) { /* Currently, the functions that require is_flat as their parameter and are called during placement should @@ -58,6 +49,33 @@ void try_place(const Netlist<>& net_list, const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& atom_ctx = g_vpr_ctx.atom(); + // Initialize the variables in the placement context. + g_vpr_ctx.mutable_placement().init_placement_context(placer_opts, directs); + + // Update the floorplanning constraints with the macro information from the + // placement context. + g_vpr_ctx.mutable_floorplanning().update_floorplanning_context_pre_place(*g_vpr_ctx.placement().place_macros); + + const bool cube_bb = g_vpr_ctx.placement().cube_bb; + + VTR_LOG("\n"); + VTR_LOG("Bounding box mode is %s\n", (cube_bb ? "Cube" : "Per-layer")); + VTR_LOG("\n"); + + /* To make sure the importance of NoC-related cost terms compared to + * BB and timing cost is determine only through NoC placement weighting factor, + * we normalize NoC-related cost weighting factors so that they add up to 1. + * With this normalization, NoC-related cost weighting factors only determine + * the relative importance of NoC cost terms with respect to each other, while + * the importance of total NoC cost to conventional placement cost is determined + * by NoC placement weighting factor. + * FIXME: This should not be modifying the NoC Opts here, this normalization + * should occur when these Opts are loaded in. + */ + if (noc_opts.noc) { + normalize_noc_cost_weighting_factor(const_cast(noc_opts)); + } + /* Placement delay model is independent of the placement and can be shared across * multiple placers if we are performing parallel annealing. * So, it is created and initialized once. */ @@ -65,35 +83,25 @@ void try_place(const Netlist<>& net_list, if (placer_opts.place_algorithm.is_timing_driven()) { /*do this before the initial placement to avoid messing up the initial placement */ - place_delay_model = alloc_lookups_and_delay_model(net_list, - chan_width_dist, - placer_opts, - router_opts, - det_routing_arch, - segment_inf, - directs, - is_flat); + place_delay_model = PlacementDelayModelCreator::create_delay_model(placer_opts, + router_opts, + net_list, + det_routing_arch, + segment_inf, + chan_width_dist, + directs, + is_flat); if (isEchoFileEnabled(E_ECHO_PLACEMENT_DELTA_DELAY_MODEL)) { place_delay_model->dump_echo(getEchoFileName(E_ECHO_PLACEMENT_DELTA_DELAY_MODEL)); } } - g_vpr_ctx.mutable_placement().cube_bb = is_cube_bb(placer_opts.place_bounding_box_mode, device_ctx.rr_graph); - const bool cube_bb = g_vpr_ctx.placement().cube_bb; - - VTR_LOG("\n"); - VTR_LOG("Bounding box mode is %s\n", (cube_bb ? "Cube" : "Per-layer")); - VTR_LOG("\n"); - - auto& place_ctx = g_vpr_ctx.mutable_placement(); - /* Make the global instance of BlkLocRegistry inaccessible through the getter methods of the * placement context. This is done to make sure that the placement stage only accesses its * own local instances of BlkLocRegistry. */ - place_ctx.lock_loc_vars(); - place_ctx.compressed_block_grids = create_compressed_block_grids(); + g_vpr_ctx.mutable_placement().lock_loc_vars(); /* Start measuring placement time. The measured execution time will be printed * when this object goes out of scope at the end of this function. @@ -103,45 +111,24 @@ void try_place(const Netlist<>& net_list, // Enables fast look-up pb graph pins from block pin indices IntraLbPbPinLookup pb_gpin_lookup(device_ctx.logical_block_types); // Enables fast look-up of atom pins connect to CLB pins - ClusteredPinAtomPinsLookup netlist_pin_lookup(cluster_ctx.clb_nlist, atom_ctx.nlist, pb_gpin_lookup); + ClusteredPinAtomPinsLookup netlist_pin_lookup(cluster_ctx.clb_nlist, atom_ctx.netlist(), pb_gpin_lookup); - Placer placer(net_list, placer_opts, analysis_opts, noc_opts, pb_gpin_lookup, netlist_pin_lookup, - directs, place_delay_model, cube_bb, is_flat, /*quiet=*/false); + Placer placer(net_list, {}, placer_opts, analysis_opts, noc_opts, pb_gpin_lookup, netlist_pin_lookup, + flat_placement_info, place_delay_model, cube_bb, is_flat, /*quiet=*/false); placer.place(); - vtr::release_memory(place_ctx.compressed_block_grids); - /* The placer object has its own copy of block locations and doesn't update * the global context directly. We need to copy its internal data structures * to the global placement context before it goes out of scope. */ - placer.copy_locs_to_global_state(place_ctx); -} - -static bool is_cube_bb(const e_place_bounding_box_mode place_bb_mode, - const RRGraphView& rr_graph) { - bool cube_bb; - const int number_layers = g_vpr_ctx.device().grid.get_num_layers(); - - if (place_bb_mode == e_place_bounding_box_mode::AUTO_BB) { - // If the auto_bb is used, we analyze the RR graph to see whether is there any inter-layer connection that is not - // originated from OPIN. If there is any, cube BB is chosen, otherwise, per-layer bb is chosen. - if (number_layers > 1 && inter_layer_connections_limited_to_opin(rr_graph)) { - cube_bb = false; - } else { - cube_bb = true; - } - } else if (place_bb_mode == e_place_bounding_box_mode::CUBE_BB) { - // The user has specifically asked for CUBE_BB - cube_bb = true; - } else { - // The user has specifically asked for PER_LAYER_BB - VTR_ASSERT_SAFE(place_bb_mode == e_place_bounding_box_mode::PER_LAYER_BB); - cube_bb = false; - } + placer.copy_locs_to_global_state(g_vpr_ctx.mutable_placement()); - return cube_bb; + // Clean the variables in the placement context. This will deallocate memory + // used by variables which were allocated in the placement context and are + // never used outside of placement. + g_vpr_ctx.mutable_placement().clean_placement_context_post_place(); + g_vpr_ctx.mutable_floorplanning().clean_floorplanning_context_post_place(); } #ifdef VERBOSE @@ -173,4 +160,3 @@ static void update_screen_debug() { update_screen(ScreenUpdatePriority::MAJOR, "DEBUG", PLACEMENT, nullptr); } #endif - diff --git a/vpr/src/place/place.h b/vpr/src/place/place.h index e4a0172ba4e..c7c3d9f8758 100644 --- a/vpr/src/place/place.h +++ b/vpr/src/place/place.h @@ -3,6 +3,8 @@ #include "vpr_types.h" +class FlatPlacementInfo; + void try_place(const Netlist<>& net_list, const t_placer_opts& placer_opts, const t_router_opts& router_opts, @@ -12,4 +14,5 @@ void try_place(const Netlist<>& net_list, t_det_routing_arch* det_routing_arch, std::vector& segment_inf, const std::vector& directs, + const FlatPlacementInfo& flat_placement_info, bool is_flat); diff --git a/vpr/src/place/place_checkpoint.cpp b/vpr/src/place/place_checkpoint.cpp index 60b009d85ae..a6e2858e577 100644 --- a/vpr/src/place/place_checkpoint.cpp +++ b/vpr/src/place/place_checkpoint.cpp @@ -1,7 +1,11 @@ + #include "place_checkpoint.h" + #include "noc_place_utils.h" #include "placer_state.h" #include "grid_block.h" +#include "PlacerCriticalities.h" +#include "PlacerSetupSlacks.h" float t_placement_checkpoint::get_cp_cpd() const { return cpd_; } diff --git a/vpr/src/place/place_constraints.cpp b/vpr/src/place/place_constraints.cpp index 2fee09e9d7b..ef867ce5b1a 100644 --- a/vpr/src/place/place_constraints.cpp +++ b/vpr/src/place/place_constraints.cpp @@ -10,6 +10,7 @@ #include "globals.h" #include "place_constraints.h" +#include "physical_types_util.h" #include "place_util.h" #include "vpr_context.h" @@ -117,7 +118,6 @@ PartitionRegion update_macro_member_pr(const PartitionRegion& head_pr, macro_pr.add_to_part_region(modified_reg); } - //intersect to ensure the macro pr does not go outside of grid dimensions macro_pr = intersection(macro_pr, grid_pr); @@ -282,8 +282,6 @@ void alloc_and_load_compressed_cluster_constraints() { // Get the compressed grid for NoC const auto& compressed_grid = place_ctx.compressed_block_grids[block_type->index]; - - for (const Region& region : pr.get_regions()) { const auto [layer_low, layer_high] = region.get_layer_range(); const vtr::Rect& rect = region.get_rect(); @@ -310,14 +308,12 @@ void alloc_and_load_compressed_cluster_constraints() { } } - for (int l = 0 ; l < n_layers; l++) { + for (int l = 0; l < n_layers; l++) { if (floorplanning_ctx.compressed_cluster_constraints[l][blk_id].empty()) { floorplanning_ctx.compressed_cluster_constraints[l][blk_id].add_to_part_region(Region{}); } } - } - } /* diff --git a/vpr/src/place/place_constraints.h b/vpr/src/place/place_constraints.h index 9e045178e77..77952144795 100644 --- a/vpr/src/place/place_constraints.h +++ b/vpr/src/place/place_constraints.h @@ -34,7 +34,6 @@ bool is_cluster_constrained(ClusterBlockId blk_id); */ bool cluster_floorplanning_legal(ClusterBlockId blk_id, const t_pl_loc& loc); - /** * @brief Check whether any member of the macro has floorplan constraints. * @@ -107,7 +106,6 @@ inline bool floorplan_legal(const t_pl_blocks_to_be_moved& blocks_affected) { return true; } - /** * @brief Load cluster_constraints if the pack stage of VPR is skipped. * @@ -185,7 +183,6 @@ int get_part_reg_size(const PartitionRegion& pr, t_logical_block_type_ptr block_type, const GridTileLookup& grid_tiles); - /** * @brief Return the floorplan score that will be used for sorting blocks during initial placement. * @@ -205,5 +202,4 @@ double get_floorplan_score(ClusterBlockId blk_id, t_logical_block_type_ptr block_type, const GridTileLookup& grid_tiles); - #endif /* VPR_SRC_PLACE_PLACE_CONSTRAINTS_H_ */ diff --git a/vpr/src/place/place_delay_model.cpp b/vpr/src/place/place_delay_model.cpp deleted file mode 100644 index 4cbf5be1b6a..00000000000 --- a/vpr/src/place/place_delay_model.cpp +++ /dev/null @@ -1,469 +0,0 @@ -/** - * @file place_delay_model.cpp - * @brief This file implements all the class methods and individual - * routines related to the placer delay model. - */ - -#include -#include "place_delay_model.h" -#include "globals.h" -#include "router_lookahead_map.h" -#include "rr_graph2.h" - -#include "timing_place_lookup.h" -#include "placer_state.h" - -#include "vtr_log.h" -#include "vtr_math.h" -#include "vpr_error.h" - -#ifdef VTR_ENABLE_CAPNPROTO -# include "capnp/serialize.h" -# include "place_delay_model.capnp.h" -# include "ndmatrix_serdes.h" -# include "mmap_file.h" -# include "serdes_utils.h" -#endif /* VTR_ENABLE_CAPNPROTO */ - -///@brief DeltaDelayModel methods. -float DeltaDelayModel::delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const { - int delta_x = std::abs(from_loc.x - to_loc.x); - int delta_y = std::abs(from_loc.y - to_loc.y); - - return delays_[from_loc.layer_num][to_loc.layer_num][delta_x][delta_y]; -} - -void DeltaDelayModel::dump_echo(std::string filepath) const { - FILE* f = vtr::fopen(filepath.c_str(), "w"); - fprintf(f, " "); - for (size_t from_layer_num = 0; from_layer_num < delays_.dim_size(0); ++from_layer_num) { - for (size_t to_layer_num = 0; to_layer_num < delays_.dim_size(1); ++to_layer_num) { - fprintf(f, " %9zu", from_layer_num); - fprintf(f, "\n"); - for (size_t dx = 0; dx < delays_.dim_size(2); ++dx) { - fprintf(f, " %9zu", dx); - } - fprintf(f, "\n"); - for (size_t dy = 0; dy < delays_.dim_size(3); ++dy) { - fprintf(f, "%9zu", dy); - for (size_t dx = 0; dx < delays_.dim_size(2); ++dx) { - fprintf(f, " %9.2e", delays_[from_layer_num][to_layer_num][dx][dy]); - } - fprintf(f, "\n"); - } - } - } - vtr::fclose(f); -} - -const DeltaDelayModel* OverrideDelayModel::base_delay_model() const { - return base_delay_model_.get(); -} - -///@brief OverrideDelayModel methods. -float OverrideDelayModel::delay(const t_physical_tile_loc& from_loc, int from_pin, const t_physical_tile_loc& to_loc, int to_pin) const { - //First check to if there is an override delay value - auto& device_ctx = g_vpr_ctx.device(); - auto& grid = device_ctx.grid; - - t_physical_tile_type_ptr from_type_ptr = grid.get_physical_type(from_loc); - t_physical_tile_type_ptr to_type_ptr = grid.get_physical_type(to_loc); - - t_override override_key; - override_key.from_type = from_type_ptr->index; - override_key.from_class = from_type_ptr->pin_class[from_pin]; - override_key.to_type = to_type_ptr->index; - override_key.to_class = to_type_ptr->pin_class[to_pin]; - - //Delay overrides may be different for +/- delta so do not use - //an absolute delta for the look-up - override_key.delta_x = to_loc.x - from_loc.x; - override_key.delta_y = to_loc.y - from_loc.y; - - float delay_val = std::numeric_limits::quiet_NaN(); - auto override_iter = delay_overrides_.find(override_key); - if (override_iter != delay_overrides_.end()) { - //Found an override - delay_val = override_iter->second; - } else { - //Fall back to the base delay model if no override was found - delay_val = base_delay_model_->delay(from_loc, from_pin, to_loc, to_pin); - } - - return delay_val; -} - -void OverrideDelayModel::set_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y, float delay_val) { - t_override override_key; - override_key.from_type = from_type; - override_key.from_class = from_class; - override_key.to_type = to_type; - override_key.to_class = to_class; - override_key.delta_x = delta_x; - override_key.delta_y = delta_y; - - auto res = delay_overrides_.insert(std::make_pair(override_key, delay_val)); - if (!res.second) { //Key already exists - res.first->second = delay_val; //Overwrite existing delay - } -} - -void OverrideDelayModel::dump_echo(std::string filepath) const { - base_delay_model_->dump_echo(filepath); - - FILE* f = vtr::fopen(filepath.c_str(), "a"); - - fprintf(f, "\n"); - fprintf(f, "# Delay Overrides\n"); - auto& device_ctx = g_vpr_ctx.device(); - for (auto kv : delay_overrides_) { - auto override_key = kv.first; - float delay_val = kv.second; - fprintf(f, "from_type: %s to_type: %s from_pin_class: %d to_pin_class: %d delta_x: %d delta_y: %d -> delay: %g\n", - device_ctx.physical_tile_types[override_key.from_type].name.c_str(), - device_ctx.physical_tile_types[override_key.to_type].name.c_str(), - override_key.from_class, - override_key.to_class, - override_key.delta_x, - override_key.delta_y, - delay_val); - } - - vtr::fclose(f); -} - -float OverrideDelayModel::get_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y) const { - t_override key; - key.from_type = from_type; - key.from_class = from_class; - key.to_type = to_type; - key.to_class = to_class; - key.delta_x = delta_x; - key.delta_y = delta_y; - - auto iter = delay_overrides_.find(key); - if (iter == delay_overrides_.end()) { - VPR_THROW(VPR_ERROR_PLACE, "Key not found."); - } - return iter->second; -} - -void OverrideDelayModel::set_base_delay_model(std::unique_ptr base_delay_model_obj) { - base_delay_model_ = std::move(base_delay_model_obj); -} - -float SimpleDelayModel::delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const { - int delta_x = std::abs(from_loc.x - to_loc.x); - int delta_y = std::abs(from_loc.y - to_loc.y); - - int from_tile_idx = g_vpr_ctx.device().grid.get_physical_type(from_loc)->index; - return delays_[from_tile_idx][from_loc.layer_num][to_loc.layer_num][delta_x][delta_y]; -} - -/** - * When writing capnp targetted serialization, always allow compilation when - * VTR_ENABLE_CAPNPROTO=OFF. Generally this means throwing an exception instead. - */ -#ifndef VTR_ENABLE_CAPNPROTO - -# define DISABLE_ERROR \ - "is disable because VTR_ENABLE_CAPNPROTO=OFF." \ - "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable." - -void SimpleDelayModel::read(const std::string& /*file*/) { - VPR_THROW(VPR_ERROR_PLACE, "SimpleDelayModel::read " DISABLE_ERROR); -} - -void SimpleDelayModel::write(const std::string& /*file*/) const { - VPR_THROW(VPR_ERROR_PLACE, "SimpleDelayModel::write " DISABLE_ERROR); -} - -void DeltaDelayModel::read(const std::string& /*file*/) { - VPR_THROW(VPR_ERROR_PLACE, "DeltaDelayModel::read " DISABLE_ERROR); -} - -void DeltaDelayModel::write(const std::string& /*file*/) const { - VPR_THROW(VPR_ERROR_PLACE, "DeltaDelayModel::write " DISABLE_ERROR); -} - -void OverrideDelayModel::read(const std::string& /*file*/) { - VPR_THROW(VPR_ERROR_PLACE, "OverrideDelayModel::read " DISABLE_ERROR); -} - -void OverrideDelayModel::write(const std::string& /*file*/) const { - VPR_THROW(VPR_ERROR_PLACE, "OverrideDelayModel::write " DISABLE_ERROR); -} - -#else /* VTR_ENABLE_CAPNPROTO */ - -static void ToFloat(float* out, const VprFloatEntry::Reader& in) { - // Getting a scalar field is always "get()". - *out = in.getValue(); -} - -static void FromFloat(VprFloatEntry::Builder* out, const float& in) { - // Setting a scalar field is always "set(value)". - out->setValue(in); -} - -void SimpleDelayModel::read(const std::string& file) { - // MmapFile object creates an mmap of the specified path, and will munmap - // when the object leaves scope. - MmapFile f(file); - - /* Increase reader limit to 1G words to allow for large files. */ - ::capnp::ReaderOptions opts = default_large_capnp_opts(); - - // FlatArrayMessageReader is used to read the message from the data array - // provided by MmapFile. - ::capnp::FlatArrayMessageReader reader(f.getData(), opts); - - // When reading capnproto files the Reader object to use is named - // ::Reader. - // - // Initially this object is an empty VprDeltaDelayModel. - VprDeltaDelayModel::Reader model; - - // The reader.getRoot performs a cast from the generic capnproto to fit - // with the specified schema. - // - // Note that capnproto does not validate that the incoming data matches the - // schema. If this property is required, some form of check would be - // required. - model = reader.getRoot(); - - // ToNdMatrix is a generic function for converting a Matrix capnproto - // to a vtr::NdMatrix. - // - // The user must supply the matrix dimension (5 in this case), the source - // capnproto type (VprFloatEntry), - // target C++ type (flat), and a function to convert from the source capnproto - // type to the target C++ type (ToFloat). - // - // The second argument should be of type Matrix::Reader where X is the - // capnproto element type. - ToNdMatrix<5, VprFloatEntry, float>(&delays_, model.getDelays(), ToFloat); -} - -void SimpleDelayModel::write(const std::string& file) const { - // MallocMessageBuilder object generates capnproto message builder, - // using malloc for buffer allocation. - ::capnp::MallocMessageBuilder builder; - - // initRoot returns a X::Builder object that can be used to set the - // fields in the message. - auto model = builder.initRoot(); - - // FromNdMatrix is a generic function for converting a vtr::NdMatrix to a - // Matrix message. It is the mirror function of ToNdMatrix described in - // read above. - auto delay_values = model.getDelays(); - FromNdMatrix<5, VprFloatEntry, float>(&delay_values, delays_, FromFloat); - - // writeMessageToFile writes message to the specified file. - writeMessageToFile(file, &builder); -} - -void DeltaDelayModel::read(const std::string& file) { - // MmapFile object creates an mmap of the specified path, and will munmap - // when the object leaves scope. - MmapFile f(file); - - /* Increase reader limit to 1G words to allow for large files. */ - ::capnp::ReaderOptions opts = default_large_capnp_opts(); - - // FlatArrayMessageReader is used to read the message from the data array - // provided by MmapFile. - ::capnp::FlatArrayMessageReader reader(f.getData(), opts); - - // When reading capnproto files the Reader object to use is named - // ::Reader. - // - // Initially this object is an empty VprDeltaDelayModel. - VprDeltaDelayModel::Reader model; - - // The reader.getRoot performs a cast from the generic capnproto to fit - // with the specified schema. - // - // Note that capnproto does not validate that the incoming data matches the - // schema. If this property is required, some form of check would be - // required. - model = reader.getRoot(); - - // ToNdMatrix is a generic function for converting a Matrix capnproto - // to a vtr::NdMatrix. - // - // The use must supply the matrix dimension (2 in this case), the source - // capnproto type (VprFloatEntry), - // target C++ type (flat), and a function to convert from the source capnproto - // type to the target C++ type (ToFloat). - // - // The second argument should be of type Matrix::Reader where X is the - // capnproto element type. - ToNdMatrix<4, VprFloatEntry, float>(&delays_, model.getDelays(), ToFloat); -} - -void DeltaDelayModel::write(const std::string& file) const { - // MallocMessageBuilder object is the generate capnproto message builder, - // using malloc for buffer allocation. - ::capnp::MallocMessageBuilder builder; - - // initRoot returns a X::Builder object that can be used to set the - // fields in the message. - auto model = builder.initRoot(); - - // FromNdMatrix is a generic function for converting a vtr::NdMatrix to a - // Matrix message. It is the mirror function of ToNdMatrix described in - // read above. - auto delay_values = model.getDelays(); - FromNdMatrix<4, VprFloatEntry, float>(&delay_values, delays_, FromFloat); - - // writeMessageToFile writes message to the specified file. - writeMessageToFile(file, &builder); -} - -void OverrideDelayModel::read(const std::string& file) { - MmapFile f(file); - - /* Increase reader limit to 1G words to allow for large files. */ - ::capnp::ReaderOptions opts = default_large_capnp_opts(); - ::capnp::FlatArrayMessageReader reader(f.getData(), opts); - - vtr::NdMatrix delays; - auto model = reader.getRoot(); - ToNdMatrix<4, VprFloatEntry, float>(&delays, model.getDelays(), ToFloat); - - base_delay_model_ = std::make_unique(cross_layer_delay_, delays, is_flat_); - - // Reading non-scalar capnproto fields is roughly equivilant to using - // a std::vector of the field type. Actual type is capnp::List::Reader. - auto overrides = model.getDelayOverrides(); - std::vector > overrides_arr(overrides.size()); - for (size_t i = 0; i < overrides.size(); ++i) { - const auto& elem = overrides[i]; - overrides_arr[i].first.from_type = elem.getFromType(); - overrides_arr[i].first.to_type = elem.getToType(); - overrides_arr[i].first.from_class = elem.getFromClass(); - overrides_arr[i].first.to_class = elem.getToClass(); - overrides_arr[i].first.delta_x = elem.getDeltaX(); - overrides_arr[i].first.delta_y = elem.getDeltaY(); - - overrides_arr[i].second = elem.getDelay(); - } - - delay_overrides_ = vtr::make_flat_map2(std::move(overrides_arr)); -} - -void OverrideDelayModel::write(const std::string& file) const { - ::capnp::MallocMessageBuilder builder; - auto model = builder.initRoot(); - - auto delays = model.getDelays(); - FromNdMatrix<4, VprFloatEntry, float>(&delays, base_delay_model_->delays(), FromFloat); - - // Non-scalar capnproto fields should be first initialized with - // init(count), and then accessed from the returned - // std::vector-like Builder object (specifically capnp::List::Builder). - auto overrides = model.initDelayOverrides(delay_overrides_.size()); - auto dst_iter = overrides.begin(); - for (const auto& src : delay_overrides_) { - auto elem = *dst_iter++; - elem.setFromType(src.first.from_type); - elem.setToType(src.first.to_type); - elem.setFromClass(src.first.from_class); - elem.setToClass(src.first.to_class); - elem.setDeltaX(src.first.delta_x); - elem.setDeltaY(src.first.delta_y); - - elem.setDelay(src.second); - } - - writeMessageToFile(file, &builder); -} - -#endif - -///@brief Initialize the placer delay model. -std::unique_ptr alloc_lookups_and_delay_model(const Netlist<>& net_list, - t_chan_width_dist chan_width_dist, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - t_det_routing_arch* det_routing_arch, - std::vector& segment_inf, - const std::vector& directs, - bool is_flat) { - return compute_place_delay_model(placer_opts, - router_opts, - net_list, - det_routing_arch, - segment_inf, - chan_width_dist, - directs, - is_flat); -} - -/** - * @brief Returns the delay of one point to point connection. - * - * Only estimate delay for signals routed through the inter-block routing network. - * TODO: Do how should we compute the delay for globals. "Global signals are assumed to have zero delay." - */ -float comp_td_single_connection_delay(const PlaceDelayModel* delay_model, - const vtr::vector_map& block_locs, - ClusterNetId net_id, - int ipin) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - - float delay_source_to_sink = 0.; - - if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { - ClusterPinId source_pin = cluster_ctx.clb_nlist.net_driver(net_id); - ClusterPinId sink_pin = cluster_ctx.clb_nlist.net_pin(net_id, ipin); - - ClusterBlockId source_block = cluster_ctx.clb_nlist.pin_block(source_pin); - ClusterBlockId sink_block = cluster_ctx.clb_nlist.pin_block(sink_pin); - - int source_block_ipin = cluster_ctx.clb_nlist.pin_logical_index(source_pin); - int sink_block_ipin = cluster_ctx.clb_nlist.pin_logical_index(sink_pin); - - t_pl_loc source_block_loc = block_locs[source_block].loc; - t_pl_loc sink_block_loc = block_locs[sink_block].loc; - - /** - * This heuristic only considers delta_x and delta_y, a much better - * heuristic would be to to create a more comprehensive lookup table. - * - * In particular this approach does not accurately capture the effect - * of fast carry-chain connections. - */ - delay_source_to_sink = delay_model->delay({source_block_loc.x, source_block_loc.y, source_block_loc.layer}, source_block_ipin, - {sink_block_loc.x, sink_block_loc.y, sink_block_loc.layer}, sink_block_ipin); - if (delay_source_to_sink < 0) { - VPR_ERROR(VPR_ERROR_PLACE, - "in comp_td_single_connection_delay: Bad delay_source_to_sink value %g from %s (at %d,%d,%d) to %s (at %d,%d,%d)\n" - "in comp_td_single_connection_delay: Delay is less than 0\n", - block_type_pin_index_to_name(physical_tile_type(source_block_loc), source_block_ipin, false).c_str(), - source_block_loc.x, source_block_loc.y, source_block_loc.layer, - block_type_pin_index_to_name(physical_tile_type(sink_block_loc), sink_block_ipin, false).c_str(), - sink_block_loc.x, sink_block_loc.y, sink_block_loc.layer, - delay_source_to_sink); - } - } - - return (delay_source_to_sink); -} - -///@brief Recompute all point to point delays, updating `connection_delay` matrix. -void comp_td_connection_delays(const PlaceDelayModel* delay_model, - PlacerState& placer_state) { - const auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& p_timing_ctx = placer_state.mutable_timing(); - auto& block_locs = placer_state.block_locs(); - auto& connection_delay = p_timing_ctx.connection_delay; - - for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { - for (size_t ipin = 1; ipin < cluster_ctx.clb_nlist.net_pins(net_id).size(); ++ipin) { - connection_delay[net_id][ipin] = comp_td_single_connection_delay(delay_model, block_locs, net_id, ipin); - } - } -} diff --git a/vpr/src/place/place_delay_model.h b/vpr/src/place/place_delay_model.h deleted file mode 100644 index d9df7a18e90..00000000000 --- a/vpr/src/place/place_delay_model.h +++ /dev/null @@ -1,275 +0,0 @@ -/** - * @file place_delay_model.h - * @brief This file contains all the class and function declarations related to - * the placer delay model. For implementations, see place_delay_model.cpp. - */ - -#pragma once -#include "vtr_ndmatrix.h" -#include "vtr_flat_map.h" -#include "vpr_types.h" -#include "router_delay_profiling.h" - -#ifndef __has_attribute -# define __has_attribute(x) 0 // Compatibility with non-clang compilers. -#endif - -#if defined(COMPILER_GCC) && defined(NDEBUG) -# define ALWAYS_INLINE inline __attribute__((__always_inline__)) -#elif defined(COMPILER_MSVC) && defined(NDEBUG) -# define ALWAYS_INLINE __forceinline -#elif __has_attribute(always_inline) -# define ALWAYS_INLINE __attribute__((always_inline)) // clang -#else -# define ALWAYS_INLINE inline -#endif - -///@brief Forward declarations. -class PlaceDelayModel; -class PlacerState; - -///@brief Initialize the placer delay model. -std::unique_ptr alloc_lookups_and_delay_model(const Netlist<>& net_list, - t_chan_width_dist chan_width_dist, - const t_placer_opts& place_opts, - const t_router_opts& router_opts, - t_det_routing_arch* det_routing_arch, - std::vector& segment_inf, - const std::vector& directs, - bool is_flat); - -///@brief Returns the delay of one point to point connection. -float comp_td_single_connection_delay(const PlaceDelayModel* delay_model, - const vtr::vector_map& block_locs, - ClusterNetId net_id, - int ipin); - -///@brief Recompute all point to point delays, updating `connection_delay` matrix. -void comp_td_connection_delays(const PlaceDelayModel* delay_model, - PlacerState& placer_state); - -///@brief Abstract interface to a placement delay model. -class PlaceDelayModel { - public: - virtual ~PlaceDelayModel() = default; - - ///@brief Computes place delay model. - virtual void compute( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - int longest_length) - = 0; - - /** - * @brief Returns the delay estimate between the specified block pins. - * - * Either compute or read methods must be invoked before invoking delay. - */ - virtual float delay(const t_physical_tile_loc& from_loc, int from_pin, const t_physical_tile_loc& to_loc, int to_pin) const = 0; - - ///@brief Dumps the delay model to an echo file. - virtual void dump_echo(std::string filename) const = 0; - - /** - * @brief Write place delay model to specified file. - * - * May be unimplemented, in which case method should throw an exception. - */ - virtual void write(const std::string& file) const = 0; - - /** - * @brief Read place delay model from specified file. - * - * May be unimplemented, in which case method should throw an exception. - */ - virtual void read(const std::string& file) = 0; -}; - -///@brief A simple delay model based on the distance (delta) between block locations. -class DeltaDelayModel : public PlaceDelayModel { - public: - DeltaDelayModel(float min_cross_layer_delay, - bool is_flat) - : cross_layer_delay_(min_cross_layer_delay) - , is_flat_(is_flat) {} - DeltaDelayModel(float min_cross_layer_delay, - vtr::NdMatrix delta_delays, - bool is_flat) - : delays_(std::move(delta_delays)) - , cross_layer_delay_(min_cross_layer_delay) - , is_flat_(is_flat) {} - - void compute( - RouterDelayProfiler& router, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - int longest_length) override; - float delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const override; - void dump_echo(std::string filepath) const override; - - void read(const std::string& file) override; - void write(const std::string& file) const override; - const vtr::NdMatrix& delays() const { - return delays_; - } - - private: - vtr::NdMatrix delays_; // [0..num_layers-1][0..max_dx][0..max_dy] - float cross_layer_delay_; - /** - * @brief Indicates whether the router is a two-stage or run-flat - */ - bool is_flat_; -}; - -class OverrideDelayModel : public PlaceDelayModel { - public: - OverrideDelayModel(float min_cross_layer_delay, - bool is_flat) - : cross_layer_delay_(min_cross_layer_delay) - , is_flat_(is_flat) {} - void compute( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - int longest_length) override; - // returns delay from the specified (x,y) to the specified (x,y) with both endpoints on layer_num and the - // specified from and to pins - float delay(const t_physical_tile_loc& from_loc, int from_pin, const t_physical_tile_loc& to_loc, int to_pin) const override; - void dump_echo(std::string filepath) const override; - - void read(const std::string& file) override; - void write(const std::string& file) const override; - - public: //Mutators - void set_base_delay_model(std::unique_ptr base_delay_model); - const DeltaDelayModel* base_delay_model() const; - float get_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y) const; - void set_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y, float delay); - - private: - std::unique_ptr base_delay_model_; - /** - * @brief Minimum delay of cross-layer connections - */ - float cross_layer_delay_; - /** - * @brief Indicates whether the router is a two-stage or run-flat - */ - bool is_flat_; - - void compute_override_delay_model(RouterDelayProfiler& router, - const t_router_opts& router_opts); - - /** - * @brief Structure that allows delays to be queried from the delay model. - * - * Delay is calculated given the origin physical tile, the origin - * pin, the destination physical tile, and the destination pin. - * This structure encapsulates all these information. - * - * @param from_type, to_type - * Physical tile index (for easy array access) - * @param from_class, to_class - * The class that the pins belongs to. - * @param to_x, to_y - * The horizontal and vertical displacement - * between two physical tiles. - */ - struct t_override { - short from_type; - short to_type; - short from_class; - short to_class; - short delta_x; - short delta_y; - - /** - * @brief Comparison operator designed for performance. - * - * Operator< is important since t_override serves as the key into the - * map structure delay_overrides_. A default comparison operator would - * not be inlined by the compiler. - * - * A combination of ALWAYS_INLINE attribute and std::lexicographical_compare - * is required for operator< to be inlined by compiler. Proper inlining of - * the function reduces place time by around 5%. - * - * For more information: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1225 - */ - friend ALWAYS_INLINE bool operator<(const t_override& lhs, const t_override& rhs) { - const short* left = reinterpret_cast(&lhs); - const short* right = reinterpret_cast(&rhs); - constexpr size_t NUM_T_OVERRIDE_MEMBERS = sizeof(t_override) / sizeof(short); - return std::lexicographical_compare(left, left + NUM_T_OVERRIDE_MEMBERS, right, right + NUM_T_OVERRIDE_MEMBERS); - } - }; - - /** - * @brief Map data structure that returns delay values according to - * specific delay model queries. - * - * Delay model queries are provided by the t_override structure, which - * encapsulates the information regarding the origin and the destination. - */ - vtr::flat_map2 delay_overrides_; - - /** - * operator< treats memory layout of t_override as an array of short. - * This requires all members of t_override are shorts and there is no - * padding between members of t_override. - */ - static_assert(sizeof(t_override) == sizeof(t_override::from_type) + sizeof(t_override::to_type) + sizeof(t_override::from_class) + sizeof(t_override::to_class) + sizeof(t_override::delta_x) + sizeof(t_override::delta_y), "Expect t_override to have a memory layout equivalent to an array of short (no padding)"); - static_assert(sizeof(t_override::from_type) == sizeof(short), "Expect all t_override data members to be shorts"); - static_assert(sizeof(t_override::to_type) == sizeof(short), "Expect all t_override data members to be shorts"); - static_assert(sizeof(t_override::from_class) == sizeof(short), "Expect all t_override data members to be shorts"); - static_assert(sizeof(t_override::to_class) == sizeof(short), "Expect all t_override data members to be shorts"); - static_assert(sizeof(t_override::delta_x) == sizeof(short), "Expect all t_override data members to be shorts"); - static_assert(sizeof(t_override::delta_y) == sizeof(short), "Expect all t_override data members to be shorts"); -}; - -///@brief A simple delay model based on the information stored in router lookahead -/// This is in contrast to other placement delay models that get the cost of getting from one location to another by running the router -class SimpleDelayModel : public PlaceDelayModel { - public: - SimpleDelayModel() {} - - /** - * @brief Initializes the `delays_` data structure. This involves retrieving the corresponding delays for each entry from - * the router lookahead and storing the minimum among them. - * - * @param router The router used to retrieve information from the router lookahead. - * @param placer_opts Placment parameters. - * @param router_opts Routing parameters. - * @param longest_length The length of the longest routing track. - */ - void compute( - RouterDelayProfiler& router, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - int longest_length) override; - float delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const override; - void dump_echo(std::string /*filepath*/) const override {} - - void read(const std::string& /*file*/) override; - void write(const std::string& /*file*/) const override; - /** - @brief Returns a reference to the array containing the placement delay matrix. - */ - const vtr::NdMatrix& delays() const { - return delays_; - } - - private: - /** - * @brief The matrix to store the minimum delay between different points on different layers. - * - *The matrix used to store delay information is a 5D matrix. This data structure stores the minimum delay for each tile type on each layer to other layers - *for each dx and dy. We decided to separate the delay for each physical type on each die to accommodate cases where the connectivity of a physical type differs - *on each layer. Additionally, instead of using d_layer, we distinguish between the destination layer to handle scenarios where connectivity between layers - *is not uniform. For example, if the number of inter-layer connections between layer 1 and 2 differs from the number of connections between layer 0 and 1. - *One might argue that this variability could also occur for dx and dy. However, we are operating under the assumption that the FPGA fabric architecture is regular. - */ - vtr::NdMatrix delays_; // [0..num_physical_type-1][0..num_layers-1][0..num_layers-1][0..max_dx][0..max_dy] -}; diff --git a/vpr/src/place/place_macro.cpp b/vpr/src/place/place_macro.cpp index 3568405290c..4a8ccb62666 100644 --- a/vpr/src/place/place_macro.cpp +++ b/vpr/src/place/place_macro.cpp @@ -7,13 +7,16 @@ #include #include +#include "atom_lookup.h" +#include "atom_netlist.h" +#include "clustered_netlist.h" +#include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_util.h" #include "vpr_utils.h" #include "vpr_types.h" #include "vpr_error.h" #include "physical_types.h" -#include "globals.h" #include "echo_files.h" /** @@ -21,14 +24,17 @@ * @param clb_net The unique id of a cluster net. * @return True if the net is constant; otherwise false. */ -static bool is_constant_clb_net(ClusterNetId clb_net); +static bool is_constant_clb_net(ClusterNetId clb_net, + const AtomLookup& atom_lookup, + const AtomNetlist& atom_nlist); /** * @brief Performs a sanity check on macros by making sure that * each block appears in at most one macro. * @param macros All placement macros in the netlist. */ -static void validate_macros(const std::vector& macros); +static void validate_macros(const std::vector& macros, + const ClusteredNetlist& clb_nlist); /** * @brief Tries to combine two placement macros. @@ -62,6 +68,7 @@ static void mark_direct_of_ports(int idirect, int line, std::vector>& idirect_from_blk_pin, std::vector>& direct_type_from_blk_pin, + const std::vector& physical_tile_types, const PortPinToBlockPinConverter& port_pin_to_block_pin); /** @@ -79,13 +86,18 @@ static void mark_direct_of_pins(int start_pin_index, int direct_type, int line, std::string_view src_string, + const std::vector& physical_tile_types, const PortPinToBlockPinConverter& port_pin_to_block_pin); const std::vector& PlaceMacros::macros() const { return pl_macros_; } -void PlaceMacros::alloc_and_load_placement_macros(const std::vector& directs) { +PlaceMacros::PlaceMacros(const std::vector& directs, + const std::vector& physical_tile_types, + const ClusteredNetlist& clb_nlist, + const AtomNetlist& atom_nlist, + const AtomLookup& atom_lookup) { /* Allocates allocates and loads placement macros and returns * the total number of macros in 2 steps. * 1) Allocate temporary data structure for maximum possible @@ -96,16 +108,17 @@ void PlaceMacros::alloc_and_load_placement_macros(const std::vector pl_macro_idirect(cluster_ctx.clb_nlist.blocks().size()); - std::vector pl_macro_num_members(cluster_ctx.clb_nlist.blocks().size()); + std::vector pl_macro_idirect(num_clusters); + std::vector pl_macro_num_members(num_clusters); /* For pl_macro_member_blk_num, Allocate for the first dimension only at first. Allocate for the second dimension * when I know the size. Otherwise, the array is going to be of size cluster_ctx.clb_nlist.blocks().size()^2 */ - std::vector> pl_macro_member_blk_num(cluster_ctx.clb_nlist.blocks().size()); + std::vector> pl_macro_member_blk_num(num_clusters); - alloc_and_load_idirect_from_blk_pin_(directs); + alloc_and_load_idirect_from_blk_pin_(directs, physical_tile_types); /* Compute required size: * Go through all the pins with possible direct connections in @@ -114,7 +127,9 @@ void PlaceMacros::alloc_and_load_placement_macros(const std::vector& pl_macro_idirect, +int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, + const AtomNetlist& atom_nlist, + const AtomLookup& atom_lookup, + std::vector& pl_macro_idirect, std::vector& pl_macro_num_members, std::vector>& pl_macro_member_blk_num) { /* Compute required size: * @@ -161,8 +182,7 @@ int PlaceMacros::find_all_the_macro_(std::vector& pl_macro_idirect, * as the number macros) and also the length of each macro * * Head - blocks with to_pin OPEN and from_pin connected * * Tail - blocks with to_pin connected and from_pin OPEN */ - const auto& cluster_ctx = g_vpr_ctx.clustering(); - std::vector pl_macro_member_blk_num_of_this_blk(cluster_ctx.clb_nlist.blocks().size()); + std::vector pl_macro_member_blk_num_of_this_blk(clb_nlist.blocks().size()); // Hash table holding the unique cluster ids and the macro id it belongs to std::unordered_map clusters_macro; @@ -170,15 +190,15 @@ int PlaceMacros::find_all_the_macro_(std::vector& pl_macro_idirect, // counts the total number of macros int num_macro = 0; - for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) { - t_logical_block_type_ptr logical_block = cluster_ctx.clb_nlist.block_type(blk_id); + for (ClusterBlockId blk_id : clb_nlist.blocks()) { + t_logical_block_type_ptr logical_block = clb_nlist.block_type(blk_id); t_physical_tile_type_ptr physical_tile = pick_physical_type(logical_block); - int num_blk_pins = cluster_ctx.clb_nlist.block_type(blk_id)->pb_type->num_pins; + int num_blk_pins = clb_nlist.block_type(blk_id)->pb_type->num_pins; for (int to_iblk_pin = 0; to_iblk_pin < num_blk_pins; to_iblk_pin++) { int to_physical_pin = get_physical_pin(physical_tile, logical_block, to_iblk_pin); - ClusterNetId to_net_id = cluster_ctx.clb_nlist.block_net(blk_id, to_iblk_pin); + ClusterNetId to_net_id = clb_nlist.block_net(blk_id, to_iblk_pin); int to_idirect = idirect_from_blk_pin_[physical_tile->index][to_physical_pin]; int to_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][to_physical_pin]; @@ -191,12 +211,12 @@ int PlaceMacros::find_all_the_macro_(std::vector& pl_macro_idirect, // Note that the restriction that constant nets are not driven from another direct ensures that // blocks in the middle of a chain with internal constant signals are not detected as potential // head blocks. - if (to_src_or_sink == SINK && to_idirect != OPEN && - (to_net_id == ClusterNetId::INVALID() || (is_constant_clb_net(to_net_id) && !net_is_driven_by_direct_(to_net_id)))) { + if (to_src_or_sink == SINK && to_idirect != OPEN + && (to_net_id == ClusterNetId::INVALID() || (is_constant_clb_net(to_net_id, atom_lookup, atom_nlist) && !net_is_driven_by_direct_(to_net_id, clb_nlist)))) { for (int from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) { int from_physical_pin = get_physical_pin(physical_tile, logical_block, from_iblk_pin); - ClusterNetId from_net_id = cluster_ctx.clb_nlist.block_net(blk_id, from_iblk_pin); + ClusterNetId from_net_id = clb_nlist.block_net(blk_id, from_iblk_pin); int from_idirect = idirect_from_blk_pin_[physical_tile->index][from_physical_pin]; int from_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][from_physical_pin]; @@ -224,13 +244,13 @@ int PlaceMacros::find_all_the_macro_(std::vector& pl_macro_idirect, ClusterNetId curr_net_id = next_net_id; // Assume that carry chains only has 1 sink - direct connection - VTR_ASSERT(cluster_ctx.clb_nlist.net_sinks(curr_net_id).size() == 1); - next_blk_id = cluster_ctx.clb_nlist.net_pin_block(curr_net_id, 1); + VTR_ASSERT(clb_nlist.net_sinks(curr_net_id).size() == 1); + next_blk_id = clb_nlist.net_pin_block(curr_net_id, 1); // Assume that the from_iblk_pin index is the same for the next block VTR_ASSERT(idirect_from_blk_pin_[physical_tile->index][from_physical_pin] == from_idirect && direct_type_from_blk_pin_[physical_tile->index][from_physical_pin] == SOURCE); - next_net_id = cluster_ctx.clb_nlist.block_net(next_blk_id, from_iblk_pin); + next_net_id = clb_nlist.block_net(next_blk_id, from_iblk_pin); // Mark down this block as a member of the macro int imember = pl_macro_num_members[num_macro]; @@ -274,10 +294,10 @@ int PlaceMacros::find_all_the_macro_(std::vector& pl_macro_idirect, num_macro++; } // Do nothing if the from_pins does not have same possible direct connection. - } // Finish going through all the pins for from_pins. - } // Do nothing if the to_pins does not have same possible direct connection. - } // Finish going through all the pins for to_pins. - } // Finish going through all blocks. + } // Finish going through all the pins for from_pins. + } // Do nothing if the to_pins does not have same possible direct connection. + } // Finish going through all the pins for to_pins. + } // Finish going through all blocks. // Now, all the data is readily stored in the temporary data structures. return num_macro; @@ -395,13 +415,12 @@ int PlaceMacros::get_imacro_from_iblk(ClusterBlockId iblk) const { return imacro; } -void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vector& directs) { - const auto& device_ctx = g_vpr_ctx.device(); - +void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vector& directs, + const std::vector& physical_tile_types) { // Allocate and initialize the values to OPEN (-1). - idirect_from_blk_pin_.resize(device_ctx.physical_tile_types.size()); - direct_type_from_blk_pin_.resize(device_ctx.physical_tile_types.size()); - for (const t_physical_tile_type& type : device_ctx.physical_tile_types) { + idirect_from_blk_pin_.resize(physical_tile_types.size()); + direct_type_from_blk_pin_.resize(physical_tile_types.size()); + for (const t_physical_tile_type& type : physical_tile_types) { if (is_empty_type(&type)) { continue; } @@ -433,6 +452,7 @@ void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vector>& idirect_from_blk_pin, std::vector>& direct_type_from_blk_pin, + const std::vector& physical_tile_types, const PortPinToBlockPinConverter& port_pin_to_block_pin) { /* Go through all the ports in all the blocks to find the port that has the same * * name as port_name and belongs to the block type that has the name pb_type_name. * @@ -462,11 +484,9 @@ static void mark_direct_of_ports(int idirect, * they are, mark down the pins from start_pin_index to end_pin_index, inclusive. * * Otherwise, mark down all the pins in that port. */ - auto& device_ctx = g_vpr_ctx.device(); - // Go through all the block types - for (int itype = 1; itype < (int)device_ctx.physical_tile_types.size(); itype++) { - auto& physical_tile = device_ctx.physical_tile_types[itype]; + for (int itype = 1; itype < (int)physical_tile_types.size(); itype++) { + auto& physical_tile = physical_tile_types[itype]; // Find blocks with the same pb_type_name if (pb_type_name == physical_tile.name) { int num_sub_tiles = physical_tile.sub_tiles.size(); @@ -493,18 +513,20 @@ static void mark_direct_of_ports(int idirect, mark_direct_of_pins(start_pin_index, end_pin_index, itype, isub_tile, iport, idirect_from_blk_pin, idirect, direct_type_from_blk_pin, direct_type, line, src_string, + physical_tile_types, port_pin_to_block_pin); } else { mark_direct_of_pins(0, num_port_pins - 1, itype, isub_tile, iport, idirect_from_blk_pin, idirect, direct_type_from_blk_pin, direct_type, line, src_string, + physical_tile_types, port_pin_to_block_pin); } } // Do nothing if port_name does not match - } // Finish going through all the ports - } // Finish going through all the subtiles - } // Do nothing if pb_type_name does not match - } // Finish going through all the blocks + } // Finish going through all the ports + } // Finish going through all the subtiles + } // Do nothing if pb_type_name does not match + } // Finish going through all the blocks } static void mark_direct_of_pins(int start_pin_index, @@ -518,16 +540,15 @@ static void mark_direct_of_pins(int start_pin_index, int direct_type, int line, std::string_view src_string, + const std::vector& physical_tile_types, const PortPinToBlockPinConverter& port_pin_to_block_pin) { - const auto& device_ctx = g_vpr_ctx.device(); - // Mark pins with indices from start_pin_index to end_pin_index, inclusive for (int iport_pin = start_pin_index; iport_pin <= end_pin_index; iport_pin++) { int iblk_pin = port_pin_to_block_pin.get_blk_pin_from_port_pin(itype, isub_tile, iport, iport_pin); // iterate through all segment connections and check if all Fc's are 0 bool all_fcs_0 = true; - for (const auto& fc_spec : device_ctx.physical_tile_types[itype].fc_specs) { + for (const auto& fc_spec : physical_tile_types[itype].fc_specs) { for (int ipin : fc_spec.pins) { if (iblk_pin == ipin && fc_spec.fc_value > 0) { all_fcs_0 = false; @@ -554,13 +575,12 @@ static void mark_direct_of_pins(int start_pin_index, } /* Allocates and loads imacro_from_iblk array. */ -void PlaceMacros::alloc_and_load_imacro_from_iblk_(const std::vector& macros) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - - imacro_from_iblk_.resize(cluster_ctx.clb_nlist.blocks().size()); +void PlaceMacros::alloc_and_load_imacro_from_iblk_(const std::vector& macros, + const ClusteredNetlist& clb_nlist) { + imacro_from_iblk_.resize(clb_nlist.blocks().size()); /* Allocate and initialize the values to OPEN (-1). */ - for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { + for (auto blk_id : clb_nlist.blocks()) { imacro_from_iblk_.insert(blk_id, OPEN); } @@ -573,11 +593,12 @@ void PlaceMacros::alloc_and_load_imacro_from_iblk_(const std::vector } } -void PlaceMacros::write_place_macros_(std::string filename, const std::vector& macros) { +void PlaceMacros::write_place_macros_(std::string filename, + const std::vector& macros, + const std::vector& physical_tile_types, + const ClusteredNetlist& clb_nlist) { FILE* f = vtr::fopen(filename.c_str(), "w"); - auto& cluster_ctx = g_vpr_ctx.clustering(); - fprintf(f, "#Identified Placement macros\n"); fprintf(f, "Num_Macros: %zu\n", macros.size()); for (size_t imacro = 0; imacro < macros.size(); ++imacro) { @@ -588,7 +609,7 @@ void PlaceMacros::write_place_macros_(std::string filename, const std::vectormembers[imember]; fprintf(f, "Block_Id: %zu (%s), x_offset: %d, y_offset: %d, z_offset: %d\n", size_t(macro_memb->blk_index), - cluster_ctx.clb_nlist.block_name(macro_memb->blk_index).c_str(), + clb_nlist.block_name(macro_memb->blk_index).c_str(), macro_memb->offset.x, macro_memb->offset.y, macro_memb->offset.sub_tile); @@ -601,8 +622,7 @@ void PlaceMacros::write_place_macros_(std::string filename, const std::vector& macros) { +static void validate_macros(const std::vector& macros, + const ClusteredNetlist& clb_nlist) { //Perform sanity checks on macros - const auto& cluster_ctx = g_vpr_ctx.clustering(); //Verify that blocks only appear in a single macro std::multimap block_to_macro; @@ -667,13 +685,13 @@ static void validate_macros(const std::vector& macros) { } } - for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) { + for (ClusterBlockId blk_id : clb_nlist.blocks()) { auto range = block_to_macro.equal_range(blk_id); int blk_macro_cnt = std::distance(range.first, range.second); if (blk_macro_cnt > 1) { std::stringstream msg; - msg << "Block #" << size_t(blk_id) << " '" << cluster_ctx.clb_nlist.block_name(blk_id) << "'" + msg << "Block #" << size_t(blk_id) << " '" << clb_nlist.block_name(blk_id) << "'" << " appears in " << blk_macro_cnt << " placement macros (should appear in at most one). Related Macros:\n"; for (auto iter = range.first; iter != range.second; ++iter) { @@ -685,4 +703,3 @@ static void validate_macros(const std::vector& macros) { } } } - diff --git a/vpr/src/place/place_macro.h b/vpr/src/place/place_macro.h index ed6a2fc82c5..0b5988c7c61 100644 --- a/vpr/src/place/place_macro.h +++ b/vpr/src/place/place_macro.h @@ -125,6 +125,9 @@ #include "physical_types.h" #include "vpr_types.h" +class AtomLookup; +class AtomNetlist; + /** * @struct t_pl_macro_member * @brief The placement macro structure. @@ -143,8 +146,6 @@ struct t_pl_macro { class PlaceMacros { public: - PlaceMacros() = default; - /** * @brief Allocates and loads the placement macros. * @details The following steps are taken in this methodL @@ -162,7 +163,11 @@ class PlaceMacros { * carry_in's is connected to the netlist which has only 1 SINK. * @param directs */ - void alloc_and_load_placement_macros(const std::vector& directs); + PlaceMacros(const std::vector& directs, + const std::vector& physical_tile_types, + const ClusteredNetlist& clb_nlist, + const AtomNetlist& atom_nlist, + const AtomLookup& atom_lookup); /** * @brief Returns the placement macro index to which the given block belongs. @@ -194,7 +199,6 @@ class PlaceMacros { const t_pl_macro& operator[](int idx) const; private: - /** * @brief This array allow us to quickly find pins that could be in a direct connection. * @details Values stored is the index of the possible direct connection as specified in the arch file, @@ -222,15 +226,23 @@ class PlaceMacros { std::vector pl_macros_; private: - int find_all_the_macro_(std::vector& pl_macro_idirect, + int find_all_the_macro_(const ClusteredNetlist& clb_nlist, + const AtomNetlist& atom_nlist, + const AtomLookup& atom_lookup, + std::vector& pl_macro_idirect, std::vector& pl_macro_num_members, std::vector>& pl_macro_member_blk_num); - void alloc_and_load_imacro_from_iblk_(const std::vector& macros); + void alloc_and_load_imacro_from_iblk_(const std::vector& macros, + const ClusteredNetlist& clb_nlist); - void write_place_macros_(std::string filename, const std::vector& macros); + void write_place_macros_(std::string filename, + const std::vector& macros, + const std::vector& physical_tile_types, + const ClusteredNetlist& clb_nlist); - bool net_is_driven_by_direct_(ClusterNetId clb_net); + bool net_is_driven_by_direct_(ClusterNetId clb_net, + const ClusteredNetlist& clb_nlist); /** * @brief Allocates and loads idirect_from_blk_pin and direct_type_from_blk_pin arrays. @@ -246,8 +258,10 @@ class PlaceMacros { * the arch file, OPEN (-1) is stored for pins that could not be part of a direct * chain connection. * @param directs Contains information about all direct connections in the architecture. + * @param physical_tile_types A list of the physical tile types on the device. */ - void alloc_and_load_idirect_from_blk_pin_(const std::vector& directs); + void alloc_and_load_idirect_from_blk_pin_(const std::vector& directs, + const std::vector& physical_tile_types); }; #endif diff --git a/vpr/src/place/place_util.cpp b/vpr/src/place/place_util.cpp index e3f3d9da567..1ac0899fbdf 100644 --- a/vpr/src/place/place_util.cpp +++ b/vpr/src/place/place_util.cpp @@ -6,55 +6,10 @@ #include "place_util.h" #include "globals.h" -#include "draw_global.h" +#include "physical_types_util.h" #include "place_constraints.h" #include "noc_place_utils.h" -/** - * @brief Initialize `grid_blocks`, the inverse structure of `block_locs`. - * - * The container at each grid block location should have a length equal to the - * subtile capacity of that block. Unused subtile would be marked ClusterBlockId::INVALID(). - */ -static GridBlock init_grid_blocks(); - -void init_placement_context(BlkLocRegistry& blk_loc_registry, - const std::vector& directs) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - - auto& block_locs = blk_loc_registry.mutable_block_locs(); - auto& grid_blocks = blk_loc_registry.mutable_grid_blocks(); - auto& place_macros = blk_loc_registry.mutable_place_macros(); - - /* Initialize the lookup of CLB block positions */ - block_locs.clear(); - block_locs.resize(cluster_ctx.clb_nlist.blocks().size()); - - /* Initialize the reverse lookup of CLB block positions */ - grid_blocks = init_grid_blocks(); - - place_macros.alloc_and_load_placement_macros(directs); -} - -static GridBlock init_grid_blocks() { - auto& device_ctx = g_vpr_ctx.device(); - int num_layers = device_ctx.grid.get_num_layers(); - - /* Structure should have the same dimensions as the grid. */ - auto grid_blocks = GridBlock(device_ctx.grid.width(), device_ctx.grid.height(), num_layers); - - for (int layer_num = 0; layer_num < num_layers; ++layer_num) { - for (int x = 0; x < (int)device_ctx.grid.width(); ++x) { - for (int y = 0; y < (int)device_ctx.grid.height(); ++y) { - auto type = device_ctx.grid.get_physical_type({x, y, layer_num}); - grid_blocks.initialized_grid_block_at_location({x, y, layer_num}, type->capacity); - } - } - } - - return grid_blocks; -} - void t_placer_costs::update_norm_factors() { if (place_algorithm.is_timing_driven()) { bb_cost_norm = 1 / bb_cost; @@ -95,7 +50,7 @@ t_placer_costs& t_placer_costs::operator+=(const NocCostTerms& noc_delta_cost) { return *this; } -int get_initial_move_lim(const t_placer_opts& placer_opts, const t_annealing_sched& annealing_sched) { +int get_place_inner_loop_num_move(const t_placer_opts& placer_opts, const t_annealing_sched& annealing_sched) { const auto& device_ctx = g_vpr_ctx.device(); const auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -113,8 +68,6 @@ int get_initial_move_lim(const t_placer_opts& placer_opts, const t_annealing_sch /* Avoid having a non-positive move_lim */ move_lim = std::max(move_lim, 1); - VTR_LOG("Moves per temperature: %d\n", move_lim); - return move_lim; } @@ -165,7 +118,6 @@ double get_std_dev(int n, double sum_x_squared, double av_x) { return (std_dev > 0.) ? sqrt(std_dev) : 0.; } - void alloc_and_load_legal_placement_locations(std::vector>>& legal_pos) { auto& device_ctx = g_vpr_ctx.device(); diff --git a/vpr/src/place/place_util.h b/vpr/src/place/place_util.h index 2a816e01350..14cf44455c6 100644 --- a/vpr/src/place/place_util.h +++ b/vpr/src/place/place_util.h @@ -25,6 +25,8 @@ constexpr double PL_INCREMENTAL_COST_TOLERANCE = .01; class t_placer_costs; class BlkLocRegistry; +struct t_pl_macro; + /** * @brief Data structure that stores different cost terms for NoC placement. * This data structure can also be used to store normalization and weighting @@ -195,19 +197,8 @@ class t_placer_statistics { }; /** - * @brief Initialize the placer's block-grid dual direction mapping. - * - * Forward direction - block to grid: place_ctx.block_locs. - * Reverse direction - grid to block: place_ctx.grid_blocks. - * Allocates and load placement macros. - * - * Initialize both of them to empty states. - */ -void init_placement_context(BlkLocRegistry& blk_loc_registry, - const std::vector& directs); - -/** - * @brief Get the initial limit for inner loop block move attempt limit. + * @brief Get the number of moves attempted by the annealer's inner + * loop in each outer loop iteration. * * There are two ways to scale the move limit. * e_place_effort_scaling::CIRCUIT @@ -220,7 +211,7 @@ void init_placement_context(BlkLocRegistry& blk_loc_registry, * (device_size >> num_blocks), the search space is larger, so the second method * performs more moves to ensure better optimization. */ -int get_initial_move_lim(const t_placer_opts& placer_opts, const t_annealing_sched& annealing_sched); +int get_place_inner_loop_num_move(const t_placer_opts& placer_opts, const t_annealing_sched& annealing_sched); /** * @brief Returns the standard deviation of data set x. diff --git a/vpr/src/place/placement_log_printer.cpp b/vpr/src/place/placement_log_printer.cpp index a4eafb3b30f..1ce8c239dc7 100644 --- a/vpr/src/place/placement_log_printer.cpp +++ b/vpr/src/place/placement_log_printer.cpp @@ -1,6 +1,7 @@ #include "placement_log_printer.h" +#include "place_macro.h" #include "vtr_log.h" #include "annealer.h" #include "place_util.h" @@ -92,10 +93,10 @@ void PlacementLogPrinter::print_place_status(float elapsed_sec) const { VTR_LOG("\n"); fflush(stdout); - sprintf(msg_.data(), "Cost: %g BB Cost %g TD Cost %g Temperature: %g", - costs.cost, costs.bb_cost, costs.timing_cost, annealing_state.t); + sprintf(msg_.data(), "Cost: %g BB Cost %g TD Cost %g Temperature: %g", + costs.cost, costs.bb_cost, costs.timing_cost, annealing_state.t); - update_screen(ScreenUpdatePriority::MINOR, msg_.data(), PLACEMENT, timing_info); + update_screen(ScreenUpdatePriority::MINOR, msg_.data(), PLACEMENT, timing_info); } void PlacementLogPrinter::print_resources_utilization() const { @@ -176,7 +177,10 @@ void PlacementLogPrinter::print_initial_placement_stats() const { std::shared_ptr timing_info = placer_.timing_info_; VTR_LOG("Initial placement cost: %g bb_cost: %g td_cost: %g\n", - costs.cost, costs.bb_cost, costs.timing_cost); + costs.cost, costs.bb_cost, costs.timing_cost); + + double wirelength = placer_.net_cost_handler_.get_total_wirelength_estimate(); + VTR_LOG("Initial placement BB estimate of wirelength: %g\n", wirelength); if (placer_.noc_opts_.noc) { VTR_ASSERT(placer_.noc_cost_handler_.has_value()); @@ -196,13 +200,14 @@ void PlacementLogPrinter::print_initial_placement_stats() const { } const BlkLocRegistry& blk_loc_registry = placer_.placer_state_.blk_loc_registry(); + const PlaceMacros& place_macros = *g_vpr_ctx.placement().place_macros; size_t num_macro_members = 0; - for (const t_pl_macro& macro : blk_loc_registry.place_macros().macros()) { + for (const t_pl_macro& macro : place_macros.macros()) { num_macro_members += macro.members.size(); } VTR_LOG("Placement contains %zu placement macros involving %zu blocks (average macro size %f)\n", - blk_loc_registry.place_macros().macros().size(), num_macro_members, - float(num_macro_members) / blk_loc_registry.place_macros().macros().size()); + place_macros.macros().size(), num_macro_members, + float(num_macro_members) / place_macros.macros().size()); VTR_LOG("\n"); sprintf(msg_.data(), @@ -231,6 +236,10 @@ void PlacementLogPrinter::print_post_placement_stats() const { VTR_LOG("Swaps called: %d\n", swap_stats.num_ts_called); placer_.annealer_->get_move_abortion_logger().report_aborted_moves(); + VTR_LOG("\n"); + double estimated_wirelength = placer_.net_cost_handler_.get_total_wirelength_estimate(); + VTR_LOG("BB estimate of min-dist (placement) wire length: %.0f\n", estimated_wirelength); + if (placer_.placer_opts_.place_algorithm.is_timing_driven()) { //Final timing estimate VTR_ASSERT(placer_.timing_info_); @@ -279,7 +288,7 @@ void PlacementLogPrinter::print_post_placement_stats() const { print_resources_utilization(); print_placement_swaps_stats(); - move_type_stats.print_placement_move_types_stats(); + move_type_stats.print_placement_move_types_stats(placer_.placer_state_.blk_loc_registry().movable_blocks_per_type()); if (placer_.noc_opts_.noc) { write_noc_placement_file(placer_.noc_opts_.noc_placement_file_name, @@ -306,7 +315,7 @@ void generate_post_place_timing_reports(const t_placer_opts& placer_opts, const auto& timing_ctx = g_vpr_ctx.timing(); const auto& atom_ctx = g_vpr_ctx.atom(); - VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); @@ -317,4 +326,3 @@ void generate_post_place_timing_reports(const t_placer_opts& placer_opts, placer_opts.post_place_timing_report_file, *timing_info.setup_analyzer(), analysis_opts.timing_report_npaths); } - diff --git a/vpr/src/place/placement_log_printer.h b/vpr/src/place/placement_log_printer.h index d538c20d895..e349fbe051f 100644 --- a/vpr/src/place/placement_log_printer.h +++ b/vpr/src/place/placement_log_printer.h @@ -2,7 +2,7 @@ * @file placement_log_printer.h * @brief Declares the PlacementLogPrinter class and associated utilities for logging * and reporting placement-related statistics and timing analysis results. - + * * ### Integration: * The PlacementLogPrinter class integrates with the Placer class to provide information about * the placement process for debugging, optimization, and analysis purposes. @@ -61,6 +61,8 @@ class PlacementLogPrinter { void print_initial_placement_stats() const; /// Prints final placement metrics and generates timing reports. void print_post_placement_stats() const; + /// Returns a bool to indicate whether the instance is in quiet mode. + bool quiet() const { return quiet_; } private: /** diff --git a/vpr/src/place/placer.cpp b/vpr/src/place/placer.cpp index 37b48f11d0d..d850fb0144b 100644 --- a/vpr/src/place/placer.cpp +++ b/vpr/src/place/placer.cpp @@ -1,13 +1,19 @@ #include "placer.h" +#include +#include #include +#include "flat_placement_types.h" +#include "blk_loc_registry.h" +#include "place_macro.h" #include "vtr_time.h" #include "draw.h" #include "read_place.h" #include "analytic_placer.h" #include "initial_placement.h" +#include "load_flat_place.h" #include "concrete_timing_info.h" #include "verify_placement.h" #include "place_timing_update.h" @@ -17,12 +23,13 @@ #include "tatum/echo_writer.hpp" Placer::Placer(const Netlist<>& net_list, + std::optional> init_place, const t_placer_opts& placer_opts, const t_analysis_opts& analysis_opts, const t_noc_opts& noc_opts, const IntraLbPbPinLookup& pb_gpin_lookup, const ClusteredPinAtomPinsLookup& netlist_pin_lookup, - const std::vector& directs, + const FlatPlacementInfo& flat_placement_info, std::shared_ptr place_delay_model, bool cube_bb, bool is_flat, @@ -33,42 +40,55 @@ Placer::Placer(const Netlist<>& net_list, , pb_gpin_lookup_(pb_gpin_lookup) , netlist_pin_lookup_(netlist_pin_lookup) , costs_(placer_opts.place_algorithm, noc_opts.noc) - , placer_state_(placer_opts.place_algorithm.is_timing_driven(), cube_bb) + , placer_state_(placer_opts.place_algorithm.is_timing_driven()) , rng_(placer_opts.seed) , net_cost_handler_(placer_opts, placer_state_, cube_bb) , place_delay_model_(std::move(place_delay_model)) , log_printer_(*this, quiet) + , quench_only_(placer_opts.place_quench_only) , is_flat_(is_flat) { const auto& cluster_ctx = g_vpr_ctx.clustering(); pre_place_timing_stats_ = g_vpr_ctx.timing().stats; - init_placement_context(placer_state_.mutable_blk_loc_registry(), directs); + const PlaceMacros& place_macros = *g_vpr_ctx.placement().place_macros; // create a NoC cost handler if NoC optimization is enabled if (noc_opts.noc) { noc_cost_handler_.emplace(placer_state_.block_locs()); } - /* To make sure the importance of NoC-related cost terms compared to - * BB and timing cost is determine only through NoC placement weighting factor, - * we normalize NoC-related cost weighting factors so that they add up to 1. - * With this normalization, NoC-related cost weighting factors only determine - * the relative importance of NoC cost terms with respect to each other, while - * the importance of total NoC cost to conventional placement cost is determined - * by NoC placement weighting factor. - */ - if (noc_opts.noc) { - normalize_noc_cost_weighting_factor(const_cast(noc_opts)); - } - + // Initialize the placement for the Simulated Annealer. BlkLocRegistry& blk_loc_registry = placer_state_.mutable_blk_loc_registry(); - initial_placement(placer_opts, placer_opts.constraints_file.c_str(), - noc_opts, blk_loc_registry, noc_cost_handler_, rng_); + if (init_place.has_value()) { + // If an initial placement has been provided, use that. + blk_loc_registry = *init_place; + } else { + // If an initial placement has not been provided, run the initial placer. + initial_placement(placer_opts, placer_opts.constraints_file.c_str(), + noc_opts, blk_loc_registry, place_macros, noc_cost_handler_, + flat_placement_info, rng_); + + // After initial placement, if a flat placement is being reconstructed, + // print flat placement reconstruction info. + if (flat_placement_info.valid) { + log_flat_placement_reconstruction_info(flat_placement_info, + blk_loc_registry.block_locs(), + g_vpr_ctx.clustering().atoms_lookup, + g_vpr_ctx.atom().lookup(), + g_vpr_ctx.atom().netlist(), + g_vpr_ctx.clustering().clb_nlist); + } + } const int move_lim = (int)(placer_opts.anneal_sched.inner_num * pow(net_list.blocks().size(), 1.3333)); //create the move generator based on the chosen placement strategy - auto [move_generator, move_generator2] = create_move_generators(placer_state_, placer_opts, move_lim, noc_opts.noc_centroid_weight, rng_); + auto [move_generator, move_generator2] = create_move_generators(placer_state_, + place_macros, + net_cost_handler_, + placer_opts, move_lim, + noc_opts.noc_centroid_weight, + rng_); if (!placer_opts.write_initial_place_file.empty()) { print_place(nullptr, nullptr, placer_opts.write_initial_place_file.c_str(), placer_state_.block_locs()); @@ -82,251 +102,250 @@ Placer::Placer(const Netlist<>& net_list, * Most of anneal is disabled later by setting initial temperature to 0 and only further optimizes in quench */ if (placer_opts.enable_analytic_placer) { - AnalyticPlacer{blk_loc_registry}.ap_place(); + AnalyticPlacer{blk_loc_registry, place_macros}.ap_place(); } #endif /* ENABLE_ANALYTIC_PLACE */ // Update physical pin values - for (const ClusterBlockId block_id : cluster_ctx.clb_nlist.blocks()) { - blk_loc_registry.place_sync_external_block_connections(block_id); - } + for (const ClusterBlockId block_id : cluster_ctx.clb_nlist.blocks()) { + blk_loc_registry.place_sync_external_block_connections(block_id); + } - if (!quiet) { + if (!quiet) { #ifndef NO_GRAPHICS - if (noc_cost_handler_.has_value()) { - get_draw_state_vars()->set_noc_link_bandwidth_usages_ref(noc_cost_handler_->get_link_bandwidth_usages()); - } + if (noc_cost_handler_.has_value()) { + get_draw_state_vars()->set_noc_link_bandwidth_usages_ref(noc_cost_handler_->get_link_bandwidth_usages()); + } #endif - // width_fac gives the width of the widest channel - const int width_fac = placer_opts.place_chan_width; - init_draw_coords((float)width_fac, placer_state_.blk_loc_registry()); - } - - // Gets initial cost and loads bounding boxes. - costs_.bb_cost = net_cost_handler_.comp_bb_cost(e_cost_methods::NORMAL); - costs_.bb_cost_norm = 1 / costs_.bb_cost; - - if (placer_opts.place_algorithm.is_timing_driven()) { - alloc_and_init_timing_objects_(net_list, analysis_opts); - } else { - VTR_ASSERT(placer_opts.place_algorithm == e_place_algorithm::BOUNDING_BOX_PLACE); - // Timing cost and normalization factors are not used - constexpr double INVALID_COST = std::numeric_limits::quiet_NaN(); - costs_.timing_cost = INVALID_COST; - costs_.timing_cost_norm = INVALID_COST; - } - - if (noc_opts.noc) { - VTR_ASSERT(noc_cost_handler_.has_value()); - - // get the costs associated with the NoC - costs_.noc_cost_terms.aggregate_bandwidth = noc_cost_handler_->comp_noc_aggregate_bandwidth_cost(); - std::tie(costs_.noc_cost_terms.latency, costs_.noc_cost_terms.latency_overrun) = noc_cost_handler_->comp_noc_latency_cost(); - costs_.noc_cost_terms.congestion = noc_cost_handler_->comp_noc_congestion_cost(); - - // initialize all the noc normalization factors - noc_cost_handler_->update_noc_normalization_factors(costs_); - } - - // set the starting total placement cost - costs_.cost = costs_.get_total_cost(placer_opts, noc_opts); - - // Sanity check that initial placement is legal - check_place_(); - - log_printer_.print_initial_placement_stats(); - - annealer_ = std::make_unique(placer_opts_, placer_state_, costs_, net_cost_handler_, noc_cost_handler_, - noc_opts_, rng_, std::move(move_generator), std::move(move_generator2), place_delay_model_.get(), - placer_criticalities_.get(), placer_setup_slacks_.get(), timing_info_.get(), pin_timing_invalidator_.get(), - move_lim); + // width_fac gives the width of the widest channel + const int width_fac = placer_opts.place_chan_width; + init_draw_coords((float)width_fac, placer_state_.blk_loc_registry()); + } + + // Gets initial cost and loads bounding boxes. + costs_.bb_cost = net_cost_handler_.comp_bb_cost(e_cost_methods::NORMAL).first; + costs_.bb_cost_norm = 1 / costs_.bb_cost; + + if (placer_opts.place_algorithm.is_timing_driven()) { + alloc_and_init_timing_objects_(net_list, analysis_opts); + } else { + VTR_ASSERT(placer_opts.place_algorithm == e_place_algorithm::BOUNDING_BOX_PLACE); + // Timing cost and normalization factors are not used + constexpr double INVALID_COST = std::numeric_limits::quiet_NaN(); + costs_.timing_cost = INVALID_COST; + costs_.timing_cost_norm = INVALID_COST; + } + + if (noc_opts.noc) { + VTR_ASSERT(noc_cost_handler_.has_value()); + + // get the costs associated with the NoC + costs_.noc_cost_terms.aggregate_bandwidth = noc_cost_handler_->comp_noc_aggregate_bandwidth_cost(); + std::tie(costs_.noc_cost_terms.latency, costs_.noc_cost_terms.latency_overrun) = noc_cost_handler_->comp_noc_latency_cost(); + costs_.noc_cost_terms.congestion = noc_cost_handler_->comp_noc_congestion_cost(); + + // initialize all the noc normalization factors + noc_cost_handler_->update_noc_normalization_factors(costs_); + } + + // set the starting total placement cost + costs_.cost = costs_.get_total_cost(placer_opts, noc_opts); + + // Sanity check that initial placement is legal + check_place_(); + + log_printer_.print_initial_placement_stats(); + + annealer_ = std::make_unique(placer_opts_, placer_state_, place_macros, costs_, net_cost_handler_, noc_cost_handler_, + noc_opts_, rng_, std::move(move_generator), std::move(move_generator2), place_delay_model_.get(), + placer_criticalities_.get(), placer_setup_slacks_.get(), timing_info_.get(), pin_timing_invalidator_.get(), + move_lim); } void Placer::alloc_and_init_timing_objects_(const Netlist<>& net_list, const t_analysis_opts& analysis_opts) { - const auto& atom_ctx = g_vpr_ctx.atom(); - const auto& cluster_ctx = g_vpr_ctx.clustering(); - const auto& timing_ctx = g_vpr_ctx.timing(); - const auto& p_timing_ctx = placer_state_.timing(); + const auto& atom_ctx = g_vpr_ctx.atom(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& timing_ctx = g_vpr_ctx.timing(); + const auto& p_timing_ctx = placer_state_.timing(); - // Update the point-to-point delays from the initial placement - comp_td_connection_delays(place_delay_model_.get(), placer_state_); + // Update the point-to-point delays from the initial placement + comp_td_connection_delays(place_delay_model_.get(), placer_state_); - // Initialize timing analysis - placement_delay_calc_ = std::make_shared(atom_ctx.nlist, - atom_ctx.lookup, - p_timing_ctx.connection_delay, - is_flat_); - placement_delay_calc_->set_tsu_margin_relative(placer_opts_.tsu_rel_margin); - placement_delay_calc_->set_tsu_margin_absolute(placer_opts_.tsu_abs_margin); + // Initialize timing analysis + placement_delay_calc_ = std::make_shared(atom_ctx.netlist(), + atom_ctx.lookup(), + p_timing_ctx.connection_delay, + is_flat_); + placement_delay_calc_->set_tsu_margin_relative(placer_opts_.tsu_rel_margin); + placement_delay_calc_->set_tsu_margin_absolute(placer_opts_.tsu_abs_margin); - timing_info_ = make_setup_timing_info(placement_delay_calc_, placer_opts_.timing_update_type); + timing_info_ = make_setup_timing_info(placement_delay_calc_, placer_opts_.timing_update_type); - placer_setup_slacks_ = std::make_unique(cluster_ctx.clb_nlist, - netlist_pin_lookup_, - timing_info_); + placer_setup_slacks_ = std::make_unique(cluster_ctx.clb_nlist, + netlist_pin_lookup_, + timing_info_); - placer_criticalities_ = std::make_unique(cluster_ctx.clb_nlist, - netlist_pin_lookup_, - timing_info_); + placer_criticalities_ = std::make_unique(cluster_ctx.clb_nlist, + netlist_pin_lookup_, + timing_info_); - pin_timing_invalidator_ = make_net_pin_timing_invalidator(placer_opts_.timing_update_type, - net_list, - netlist_pin_lookup_, - atom_ctx.nlist, - atom_ctx.lookup, - timing_info_, - is_flat_); + pin_timing_invalidator_ = make_net_pin_timing_invalidator(placer_opts_.timing_update_type, + net_list, + netlist_pin_lookup_, + atom_ctx.netlist(), + atom_ctx.lookup(), + timing_info_, + is_flat_); - // First time compute timing and costs, compute from scratch - PlaceCritParams crit_params; - crit_params.crit_exponent = placer_opts_.td_place_exp_first; - crit_params.crit_limit = placer_opts_.place_crit_limit; + // First time compute timing and costs, compute from scratch + PlaceCritParams crit_params; + crit_params.crit_exponent = placer_opts_.td_place_exp_first; + crit_params.crit_limit = placer_opts_.place_crit_limit; - initialize_timing_info(crit_params, place_delay_model_.get(), placer_criticalities_.get(), - placer_setup_slacks_.get(), pin_timing_invalidator_.get(), - timing_info_.get(), &costs_, placer_state_); + initialize_timing_info(crit_params, place_delay_model_.get(), placer_criticalities_.get(), + placer_setup_slacks_.get(), pin_timing_invalidator_.get(), + timing_info_.get(), &costs_, placer_state_); - critical_path_ = timing_info_->least_slack_critical_path(); + critical_path_ = timing_info_->least_slack_critical_path(); - // Write out the initial timing echo file - if (isEchoFileEnabled(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH)) { - tatum::write_echo(getEchoFileName(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH), - *timing_ctx.graph, *timing_ctx.constraints, - *placement_delay_calc_, timing_info_->analyzer()); + // Write out the initial timing echo file + if (isEchoFileEnabled(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH)) { + tatum::write_echo(getEchoFileName(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH), + *timing_ctx.graph, *timing_ctx.constraints, + *placement_delay_calc_, timing_info_->analyzer()); - tatum::NodeId debug_tnode = id_or_pin_name_to_tnode(analysis_opts.echo_dot_timing_graph_node); + tatum::NodeId debug_tnode = id_or_pin_name_to_tnode(analysis_opts.echo_dot_timing_graph_node); - write_setup_timing_graph_dot(getEchoFileName(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH) + std::string(".dot"), - *timing_info_, debug_tnode); - } + write_setup_timing_graph_dot(getEchoFileName(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH) + std::string(".dot"), + *timing_info_, debug_tnode); + } - costs_.timing_cost_norm = 1 / costs_.timing_cost; + costs_.timing_cost_norm = 1 / costs_.timing_cost; } void Placer::check_place_() { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const DeviceGrid& device_grid = g_vpr_ctx.device().grid; - const auto& cluster_constraints = g_vpr_ctx.floorplanning().cluster_constraints; - - int error = 0; - - // Verify the placement invariants independent to the placement flow. - error += verify_placement(placer_state_.blk_loc_registry(), - clb_nlist, - device_grid, - cluster_constraints); - - error += check_placement_costs_(); - - if (noc_opts_.noc) { - // check the NoC costs during placement if the user is using the NoC supported flow - error += noc_cost_handler_->check_noc_placement_costs(costs_, PL_INCREMENTAL_COST_TOLERANCE, noc_opts_); - // make sure NoC routing configuration does not create any cycles in CDG - error += (int)noc_cost_handler_->noc_routing_has_cycle(); - } - - if (error == 0) { - VTR_LOG("\n"); - VTR_LOG("Completed placement consistency check successfully.\n"); - - } else { - VPR_ERROR(VPR_ERROR_PLACE, - "\nCompleted placement consistency check, %d errors found.\n" - "Aborting program.\n", - error); - } + const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; + const DeviceGrid& device_grid = g_vpr_ctx.device().grid; + const auto& cluster_constraints = g_vpr_ctx.floorplanning().cluster_constraints; + const PlaceMacros& place_macros = *g_vpr_ctx.placement().place_macros; + + int error = 0; + + // Verify the placement invariants independent to the placement flow. + error += verify_placement(placer_state_.blk_loc_registry(), + place_macros, + clb_nlist, + device_grid, + cluster_constraints); + + error += check_placement_costs_(); + + if (noc_opts_.noc) { + // check the NoC costs during placement if the user is using the NoC supported flow + error += noc_cost_handler_->check_noc_placement_costs(costs_, PL_INCREMENTAL_COST_TOLERANCE, noc_opts_); + // make sure NoC routing configuration does not create any cycles in CDG + error += (int)noc_cost_handler_->noc_routing_has_cycle(); + } + + if (error == 0) { + VTR_LOGV(!log_printer_.quiet(), + "\nCompleted placement consistency check successfully.\n"); + + } else { + VPR_ERROR(VPR_ERROR_PLACE, + "\nCompleted placement consistency check, %d errors found.\n" + "Aborting program.\n", + error); + } } int Placer::check_placement_costs_() { - int error = 0; - double timing_cost_check; - - double bb_cost_check = net_cost_handler_.comp_bb_cost(e_cost_methods::CHECK); - - if (fabs(bb_cost_check - costs_.bb_cost) > costs_.bb_cost * PL_INCREMENTAL_COST_TOLERANCE) { - VTR_LOG_ERROR( - "bb_cost_check: %g and bb_cost: %g differ in check_place.\n", - bb_cost_check, costs_.bb_cost); - error++; - } - - if (placer_opts_.place_algorithm.is_timing_driven()) { - comp_td_costs(place_delay_model_.get(), *placer_criticalities_, placer_state_, &timing_cost_check); - //VTR_LOG("timing_cost recomputed from scratch: %g\n", timing_cost_check); - if (fabs(timing_cost_check - costs_.timing_cost) > costs_.timing_cost * PL_INCREMENTAL_COST_TOLERANCE) { - VTR_LOG_ERROR( - "timing_cost_check: %g and timing_cost: %g differ in check_place.\n", - timing_cost_check, costs_.timing_cost); - error++; - } - } - return error; -} + int error = 0; + double timing_cost_check; -void Placer::place() { - const auto& timing_ctx = g_vpr_ctx.timing(); - const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto [bb_cost_check, expected_wirelength] = net_cost_handler_.comp_bb_cost(e_cost_methods::CHECK); + if (fabs(bb_cost_check - costs_.bb_cost) > costs_.bb_cost * PL_INCREMENTAL_COST_TOLERANCE) { + VTR_LOG_ERROR( + "bb_cost_check: %g and bb_cost: %g differ in check_place.\n", + bb_cost_check, costs_.bb_cost); + error++; + } + + if (placer_opts_.place_algorithm.is_timing_driven()) { + comp_td_costs(place_delay_model_.get(), *placer_criticalities_, placer_state_, &timing_cost_check); + if (fabs(timing_cost_check - costs_.timing_cost) > costs_.timing_cost * PL_INCREMENTAL_COST_TOLERANCE) { + VTR_LOG_ERROR( + "timing_cost_check: %g and timing_cost: %g differ in check_place.\n", + timing_cost_check, costs_.timing_cost); + error++; + } + } + return error; +} - bool skip_anneal = false; +void Placer::place() { + const auto& timing_ctx = g_vpr_ctx.timing(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + bool analytic_place_enabled = false; #ifdef ENABLE_ANALYTIC_PLACE - // Cluster-level analytic placer: when enabled, skip most of the annealing and go straight to quench - if (placer_opts_.enable_analytic_placer) { - skip_anneal = true; - } + // Cluster-level analytic placer: when enabled, skip most of the annealing and go straight to quench + if (placer_opts_.enable_analytic_placer) { + analytic_place_enabled = true; + } #endif - if (!skip_anneal) { - // Table header - log_printer_.print_place_status_header(); + if (!analytic_place_enabled && !quench_only_) { + // Table header + log_printer_.print_place_status_header(); - // Outer loop of the simulated annealing begins - do { - vtr::Timer temperature_timer; + // Outer loop of the simulated annealing begins + do { + vtr::Timer temperature_timer; - annealer_->outer_loop_update_timing_info(); + annealer_->outer_loop_update_timing_info(); - if (placer_opts_.place_algorithm.is_timing_driven()) { - critical_path_ = timing_info_->least_slack_critical_path(); + if (placer_opts_.place_algorithm.is_timing_driven()) { + critical_path_ = timing_info_->least_slack_critical_path(); - // see if we should save the current placement solution as a checkpoint - if (placer_opts_.place_checkpointing && annealer_->get_agent_state() == e_agent_state::LATE_IN_THE_ANNEAL) { - save_placement_checkpoint_if_needed(placer_state_.mutable_block_locs(), - placement_checkpoint_, - timing_info_, costs_, critical_path_.delay()); - } - } + // see if we should save the current placement solution as a checkpoint + if (placer_opts_.place_checkpointing && annealer_->get_agent_state() == e_agent_state::LATE_IN_THE_ANNEAL) { + save_placement_checkpoint_if_needed(placer_state_.mutable_block_locs(), + placement_checkpoint_, + timing_info_, costs_, critical_path_.delay()); + } + } - // do a complete inner loop iteration - annealer_->placement_inner_loop(); + // do a complete inner loop iteration + annealer_->placement_inner_loop(); - log_printer_.print_place_status(temperature_timer.elapsed_sec()); + log_printer_.print_place_status(temperature_timer.elapsed_sec()); - // Outer loop of the simulated annealing ends - } while (annealer_->outer_loop_update_state()); - } //skip_anneal ends + // Outer loop of the simulated annealing ends + } while (annealer_->outer_loop_update_state()); + } //skip_anneal ends // Start Quench annealer_->start_quench(); pre_quench_timing_stats_ = timing_ctx.stats; { // Quench - vtr::ScopedFinishTimer temperature_timer("Placement Quench"); + vtr::ScopedFinishTimer temperature_timer("Placement Quench"); - annealer_->outer_loop_update_timing_info(); + annealer_->outer_loop_update_timing_info(); - /* Run inner loop again with temperature = 0 so as to accept only swaps - * which reduce the cost of the placement */ - annealer_->placement_inner_loop(); + /* Run inner loop again with temperature = 0 so as to accept only swaps + * which reduce the cost of the placement */ + annealer_->placement_inner_loop(); - if (placer_opts_.place_quench_algorithm.is_timing_driven()) { - critical_path_ = timing_info_->least_slack_critical_path(); - } + if (placer_opts_.place_quench_algorithm.is_timing_driven()) { + critical_path_ = timing_info_->least_slack_critical_path(); + } - log_printer_.print_place_status(temperature_timer.elapsed_sec()); + log_printer_.print_place_status(temperature_timer.elapsed_sec()); } post_quench_timing_stats_ = timing_ctx.stats; @@ -337,34 +356,34 @@ void Placer::place() { crit_params.crit_limit = placer_opts_.place_crit_limit; if (placer_opts_.place_algorithm.is_timing_driven()) { - perform_full_timing_update(crit_params, place_delay_model_.get(), placer_criticalities_.get(), - placer_setup_slacks_.get(), pin_timing_invalidator_.get(), - timing_info_.get(), &costs_, placer_state_); + perform_full_timing_update(crit_params, place_delay_model_.get(), placer_criticalities_.get(), + placer_setup_slacks_.get(), pin_timing_invalidator_.get(), + timing_info_.get(), &costs_, placer_state_); - critical_path_ = timing_info_->least_slack_critical_path(); + critical_path_ = timing_info_->least_slack_critical_path(); - VTR_LOG("post-quench CPD = %g (ns) \n", - 1e9 * critical_path_.delay()); + VTR_LOGV(!log_printer_.quiet(), + "post-quench CPD = %g (ns) \n", 1e9 * critical_path_.delay()); } // See if our latest checkpoint is better than the current placement solution if (placer_opts_.place_checkpointing) { - restore_best_placement(placer_state_, - placement_checkpoint_, timing_info_, costs_, - placer_criticalities_, placer_setup_slacks_, place_delay_model_, - pin_timing_invalidator_, crit_params, noc_cost_handler_); + restore_best_placement(placer_state_, + placement_checkpoint_, timing_info_, costs_, + placer_criticalities_, placer_setup_slacks_, place_delay_model_, + pin_timing_invalidator_, crit_params, noc_cost_handler_); } if (placer_opts_.placement_saves_per_temperature >= 1) { - std::string filename = vtr::string_fmt("placement_%03d_%03d.place", - annealing_state.num_temps + 1, 0); - VTR_LOG("Saving final placement to file: %s\n", filename.c_str()); - print_place(nullptr, nullptr, filename.c_str(), placer_state_.mutable_block_locs()); + std::string filename = vtr::string_fmt("placement_%03d_%03d.place", + annealing_state.num_temps + 1, 0); + VTR_LOGV(!log_printer_.quiet(), "Saving final placement to file: %s\n", filename.c_str()); + print_place(nullptr, nullptr, filename.c_str(), placer_state_.mutable_block_locs()); } // Update physical pin values for (const ClusterBlockId block_id : cluster_ctx.clb_nlist.blocks()) { - placer_state_.mutable_blk_loc_registry().place_sync_external_block_connections(block_id); + placer_state_.mutable_blk_loc_registry().place_sync_external_block_connections(block_id); } check_place_(); diff --git a/vpr/src/place/placer.h b/vpr/src/place/placer.h index 99c00d7e8e5..61a8301818c 100644 --- a/vpr/src/place/placer.h +++ b/vpr/src/place/placer.h @@ -17,31 +17,37 @@ #pragma once +#include #include #include -#include "timing_place.h" +#include "annealer.h" #include "place_checkpoint.h" #include "PlacementDelayCalculator.h" #include "placer_state.h" #include "noc_place_utils.h" #include "net_cost_handler.h" #include "placement_log_printer.h" +#include "PlacerSetupSlacks.h" +#include "PlacerCriticalities.h" +#include "NetPinTimingInvalidator.h" -class PlacementAnnealer; -namespace vtr{ +class BlkLocRegistry; +class FlatPlacementInfo; +namespace vtr { class ScopedStartFinishTimer; } class Placer { public: Placer(const Netlist<>& net_list, + std::optional> init_place, const t_placer_opts& placer_opts, const t_analysis_opts& analysis_opts, const t_noc_opts& noc_opts, const IntraLbPbPinLookup& pb_gpin_lookup, const ClusteredPinAtomPinsLookup& netlist_pin_lookup, - const std::vector& directs, + const FlatPlacementInfo& flat_placement_info, std::shared_ptr place_delay_model, bool cube_bb, bool is_flat, @@ -91,6 +97,8 @@ class Placer { std::shared_ptr place_delay_model_; /// Prints logs during placement const PlacementLogPrinter log_printer_; + /// Indicates if the placement quench phase should be skipped. + const bool quench_only_; /// Indicates if flat routing resource graph and delay model is used. It should be false. const bool is_flat_; diff --git a/vpr/src/place/placer_breakpoint.cpp b/vpr/src/place/placer_breakpoint.cpp index a31a0add053..d71430f2090 100644 --- a/vpr/src/place/placer_breakpoint.cpp +++ b/vpr/src/place/placer_breakpoint.cpp @@ -1,6 +1,5 @@ #include "placer_breakpoint.h" - //map of the available move types and their corresponding type number std::map available_move_types = { {0, "Uniform"}}; @@ -17,8 +16,11 @@ void transform_blocks_affected(const t_pl_blocks_to_be_moved& blocksAffected) { } } -void stop_placement_and_check_breakpoints(t_pl_blocks_to_be_moved& blocks_affected, e_move_result move_outcome, - double delta_c, double bb_delta_c, double timing_delta_c) { +void stop_placement_and_check_breakpoints(t_pl_blocks_to_be_moved& blocks_affected, + e_move_result move_outcome, + double delta_c, + double bb_delta_c, + double timing_delta_c) { t_draw_state* draw_state = get_draw_state_vars(); BreakpointState* bp_state = get_bp_state_globals()->get_glob_breakpoint_state(); diff --git a/vpr/src/place/placer_breakpoint.h b/vpr/src/place/placer_breakpoint.h index 510b7071e0d..159e9c40b38 100644 --- a/vpr/src/place/placer_breakpoint.h +++ b/vpr/src/place/placer_breakpoint.h @@ -1,5 +1,5 @@ -#ifndef PLACER_BREAKPOINT_H -#define PLACER_BREAKPOINT_H + +#pragma once #include "globals.h" #include "vpr_types.h" @@ -7,13 +7,12 @@ #include "breakpoint.h" #include "draw.h" - //transforms the vector moved_blocks to a vector of ints and adds it in glob_breakpoint_state void transform_blocks_affected(const t_pl_blocks_to_be_moved& blocksAffected); //checks the breakpoint and see whether one of them was reached and pause place,emt accordingly -void stop_placement_and_check_breakpoints(t_pl_blocks_to_be_moved& blocks_affected, e_move_result move_outcome, - double delta_c, double bb_delta_c, double timing_delta_c); - - -#endif +void stop_placement_and_check_breakpoints(t_pl_blocks_to_be_moved& blocks_affected, + e_move_result move_outcome, + double delta_c, + double bb_delta_c, + double timing_delta_c); diff --git a/vpr/src/place/placer_state.cpp b/vpr/src/place/placer_state.cpp index 998c097b4ca..c0bba0052be 100644 --- a/vpr/src/place/placer_state.cpp +++ b/vpr/src/place/placer_state.cpp @@ -4,29 +4,6 @@ #include "globals.h" #include "move_transactions.h" -PlacerMoveContext::PlacerMoveContext(bool cube_bb) { - const auto& device_ctx = g_vpr_ctx.device(); - const auto& cluster_ctx = g_vpr_ctx.clustering(); - - const size_t num_nets = cluster_ctx.clb_nlist.nets().size(); - - const int num_layers = device_ctx.grid.get_num_layers(); - - if (cube_bb) { - bb_coords.resize(num_nets, t_bb()); - bb_num_on_edges.resize(num_nets, t_bb()); - } else { - layer_bb_num_on_edges.resize(num_nets, std::vector(num_layers, t_2D_bb())); - layer_bb_coords.resize(num_nets, std::vector(num_layers, t_2D_bb())); - } - - num_sink_pin_layer.resize({num_nets, size_t(num_layers)}); - for (size_t flat_idx = 0; flat_idx < num_sink_pin_layer.size(); flat_idx++) { - int& elem = num_sink_pin_layer.get(flat_idx); - elem = OPEN; - } -} - PlacerTimingContext::PlacerTimingContext(bool placement_is_timing_driven) { const auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -85,7 +62,6 @@ void PlacerTimingContext::revert_td_cost(const t_pl_blocks_to_be_moved& blocks_a auto& cluster_ctx = g_vpr_ctx.clustering(); auto& clb_nlist = cluster_ctx.clb_nlist; - for (ClusterPinId pin : blocks_affected.affected_pins) { ClusterNetId net = clb_nlist.pin_net(pin); int ipin = clb_nlist.pin_net_index(pin); @@ -95,7 +71,5 @@ void PlacerTimingContext::revert_td_cost(const t_pl_blocks_to_be_moved& blocks_a #endif } -PlacerState::PlacerState(bool placement_is_timing_driven, bool cube_bb) - : timing_(placement_is_timing_driven) - , move_(cube_bb) {} - +PlacerState::PlacerState(bool placement_is_timing_driven) + : timing_(placement_is_timing_driven) {} diff --git a/vpr/src/place/placer_state.h b/vpr/src/place/placer_state.h index 8f3b966a56d..10592ebcfca 100644 --- a/vpr/src/place/placer_state.h +++ b/vpr/src/place/placer_state.h @@ -12,7 +12,7 @@ #include "vpr_context.h" #include "vpr_net_pins_matrix.h" #include "vpr_types.h" -#include "timing_place.h" +#include "PlacerTimingCosts.h" /** * @brief State relating to the timing driven data. @@ -111,47 +111,6 @@ struct PlacerRuntimeContext : public Context { float f_update_td_costs_total_elapsed_sec; }; -/** - * @brief Placement Move generators data - */ -struct PlacerMoveContext : public Context { - public: - PlacerMoveContext() = delete; - explicit PlacerMoveContext(bool cube_bb); - - public: - // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the number of blocks on each of a net's bounding box (to allow efficient updates) - vtr::vector bb_num_on_edges; - - // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the bounding box coordinates of a net's bounding box - vtr::vector bb_coords; - - // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the number of blocks on each of a net's bounding box (to allow efficient updates) - vtr::vector> layer_bb_num_on_edges; - - // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the bounding box coordinates of a net's bounding box - vtr::vector> layer_bb_coords; - - // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the number of blocks on each layer () - vtr::Matrix num_sink_pin_layer; - - // The first range limit calculated by the annealer - float first_rlim; - - // Scratch vectors that are used by different directed moves for temporary calculations - // These vectors will grow up with the net size as it is mostly used to save coords of the net pins or net bb edges - // Given that placement moves involve operations on each coordinate independently, we chose to - // utilize a Struct of Arrays (SoA) rather than an Array of Struct (AoS). - std::vector X_coord; - std::vector Y_coord; - std::vector layer_coord; - - // Container to save the highly critical pins (higher than a timing criticality limit set by commandline option) - std::vector> highly_crit_pins; -}; - - - /** * @brief This object encapsulates VPR placer's state. * @@ -167,7 +126,7 @@ struct PlacerMoveContext : public Context { */ class PlacerState : public Context { public: - PlacerState(bool placement_is_timing_driven, bool cube_bb); + PlacerState(bool placement_is_timing_driven); public: inline const PlacerTimingContext& timing() const { return timing_; } @@ -176,9 +135,6 @@ class PlacerState : public Context { inline const PlacerRuntimeContext& runtime() const { return runtime_; } inline PlacerRuntimeContext& mutable_runtime() { return runtime_; } - inline const PlacerMoveContext& move() const { return move_; } - inline PlacerMoveContext& mutable_move() { return move_; } - inline const vtr::vector_map& block_locs() const { return blk_loc_registry_.block_locs(); } inline vtr::vector_map& mutable_block_locs() { return blk_loc_registry_.mutable_block_locs(); } @@ -194,7 +150,6 @@ class PlacerState : public Context { private: PlacerTimingContext timing_; PlacerRuntimeContext runtime_; - PlacerMoveContext move_; /** * @brief Contains: 1) The location where each clustered block is placed at. diff --git a/vpr/src/place/timing/PlacerCriticalities.cpp b/vpr/src/place/timing/PlacerCriticalities.cpp new file mode 100644 index 00000000000..4cbf1ec66ec --- /dev/null +++ b/vpr/src/place/timing/PlacerCriticalities.cpp @@ -0,0 +1,117 @@ + +#include "PlacerCriticalities.h" + +#include "timing_info.h" +#include "timing_util.h" + +PlacerCriticalities::PlacerCriticalities(const ClusteredNetlist& clb_nlist, + const ClusteredPinAtomPinsLookup& netlist_pin_lookup, + std::shared_ptr timing_info) + : clb_nlist_(clb_nlist) + , pin_lookup_(netlist_pin_lookup) + , timing_info_(std::move(timing_info)) + , timing_place_crit_(make_net_pins_matrix(clb_nlist_, std::numeric_limits::quiet_NaN())) { +} + +void PlacerCriticalities::update_criticalities(const PlaceCritParams& crit_params) { + // If update is not enabled, exit the routine. + if (!update_enabled) { + // re-computation is required on the next iteration + recompute_required = true; + return; + } + + // Determine what pins need updating + if (!recompute_required && crit_params.crit_exponent == last_crit_exponent_) { + incr_update_criticalities(); + } else { + recompute_criticalities(); + + // Record new criticality exponent + last_crit_exponent_ = crit_params.crit_exponent; + } + + /* Performs a 1-to-1 mapping from criticality to timing_place_crit_. + * For every pin on every net (or, equivalently, for every tedge ending + * in that pin), timing_place_crit_ = criticality^(criticality exponent) */ + + // Update the affected pins + for (ClusterPinId clb_pin : cluster_pins_with_modified_criticality_) { + ClusterNetId clb_net = clb_nlist_.pin_net(clb_pin); + int pin_index_in_net = clb_nlist_.pin_net_index(clb_pin); + + float clb_pin_crit = calculate_clb_net_pin_criticality(*timing_info_, pin_lookup_, ParentPinId(size_t(clb_pin)), /*is_flat=*/false); + float new_crit = pow(clb_pin_crit, crit_params.crit_exponent); + + /* Update the highly critical pins container + * + * If the old criticality < limit and the new criticality > limit --> add this pin to the highly critical pins + * If the old criticality > limit and the new criticality < limit --> remove this pin from the highly critical pins + */ + if (!first_time_update_criticality) { + if (new_crit > crit_params.crit_limit && timing_place_crit_[clb_net][pin_index_in_net] < crit_params.crit_limit) { + highly_crit_pins.emplace_back(clb_net, pin_index_in_net); + } else if (new_crit < crit_params.crit_limit && timing_place_crit_[clb_net][pin_index_in_net] > crit_params.crit_limit) { + highly_crit_pins.erase(std::remove(highly_crit_pins.begin(), highly_crit_pins.end(), std::make_pair(clb_net, pin_index_in_net)), + highly_crit_pins.end()); + } + } else { + if (new_crit > crit_params.crit_limit) { + highly_crit_pins.emplace_back(clb_net, pin_index_in_net); + } + } + + /* The placer likes a great deal of contrast between criticalities. + * Since path criticality varies much more than timing, we "sharpen" timing + * criticality by taking it to some power, crit_exponent (between 1 and 8 by default). */ + timing_place_crit_[clb_net][pin_index_in_net] = new_crit; + } + + /* Criticalities updated. In sync with timing info. + * Can be incrementally updated on the next iteration */ + recompute_required = false; + + first_time_update_criticality = false; +} + +void PlacerCriticalities::set_recompute_required() { + recompute_required = true; +} + +void PlacerCriticalities::incr_update_criticalities() { + cluster_pins_with_modified_criticality_.clear(); + + for (AtomPinId atom_pin : timing_info_->pins_with_modified_setup_criticality()) { + ClusterPinId clb_pin = pin_lookup_.connected_clb_pin(atom_pin); + + /* Some atom pins correspond to connections which are completely + * contained within a cluster, and hence have no corresponding + * clustered pin. */ + if (!clb_pin) continue; + + cluster_pins_with_modified_criticality_.insert(clb_pin); + } +} + +void PlacerCriticalities::recompute_criticalities() { + cluster_pins_with_modified_criticality_.clear(); + + // Non-incremental: all sink pins need updating + for (ClusterNetId net_id : clb_nlist_.nets()) { + for (ClusterPinId pin_id : clb_nlist_.net_sinks(net_id)) { + cluster_pins_with_modified_criticality_.insert(pin_id); + } + } +} + +///@brief Override the criticality of a particular connection. +void PlacerCriticalities::set_criticality(ClusterNetId net_id, int ipin, float crit_val) { + VTR_ASSERT_SAFE_MSG(ipin > 0, "The pin should not be a driver pin (ipin != 0)"); + VTR_ASSERT_SAFE_MSG(ipin < int(clb_nlist_.net_pins(net_id).size()), "The pin index in net should be smaller than fanout"); + + timing_place_crit_[net_id][ipin] = crit_val; +} + +PlacerCriticalities::pin_range PlacerCriticalities::pins_with_modified_criticality() const { + return vtr::make_range(cluster_pins_with_modified_criticality_); +} diff --git a/vpr/src/place/timing/PlacerCriticalities.h b/vpr/src/place/timing/PlacerCriticalities.h new file mode 100644 index 00000000000..5ad0ef80735 --- /dev/null +++ b/vpr/src/place/timing/PlacerCriticalities.h @@ -0,0 +1,214 @@ + +#pragma once + +#include "vtr_vec_id_set.h" +#include "timing_info_fwd.h" +#include "clustered_netlist_utils.h" +#include "place_delay_model.h" +#include "vpr_net_pins_matrix.h" + +/** + * @brief Saves the placement criticality parameters + * + * crit_exponent: The criticality exponent used to sharpen the criticalities + * crit_limit: The limit to consider a pin as timing critical + */ +struct PlaceCritParams { + float crit_exponent; + float crit_limit; +}; + +/** + * @brief PlacerCriticalities returns the clustered netlist connection criticalities + * used by the placer ('sharpened' by a criticality exponent). + * + * Usage + * ===== + * This class also serves to map atom netlist level criticalites (i.e. on AtomPinIds) + * to the clustered netlist (i.e. ClusterPinIds) used during placement. + * + * Criticalities are updated by update_criticalities(), given that `update_enabled` is + * set to true. It will update criticalities based on the atom netlist connection + * criticalities provided by the passed in SetupTimingInfo. + * + * This process can be done incrementally, based on the modified connections/AtomPinIds + * returned by SetupTimingInfo. However, the set returned only reflects the connections + * changed by the last call to the timing info update (update_setup() method of SetupTimingInfo). + * + * Therefore, if SetupTimingInfo is updated twice in a row without criticalities + * getting updated after the first update of SetupTimingInfo (PlacerCriticalities::update_enabled = false), + * the returned set of modified connections/AtomPinIds by SetupTimingInfo after its second update does not + * account for all the connections that have been modified. + * To address this issue, whenever update_criticalities() is called with flag update_enabled = false, + * we don't update criticalities and set flag recompute_required to true to remember that criticalities + * need to be recomputed from scratch in the first call to update_criticalities() with update_enabled = true. + * + * This class also maps/transforms the modified atom connections/pins returned by the + * timing info into modified clustered netlist connections/pins after calling + * update_criticalities(). The interface then enables users to iterate over this range + * via pins_with_modified_criticalities(). This is useful for incrementally re-calculating + * the timing costs. + * + * The criticalities of individual connections can then be queried by calling the + * criticality() member function. + * + * Implementation + * ============== + * To support incremental re-calculation, the class saves the last criticality exponent + * passed to PlacerCriticalities::update_criticalites(). If the next update uses the same + * exponent, criticalities can be incrementally updated. Otherwise, they must be re-calculated + * from scratch, since a change in exponent changes *all* criticalities. + * + * Calculating criticalities: + * All the raw setup slack values across a single clock domain are gathered + * and rated from the best to the worst in terms of criticalities. In order + * to calculate criticalities, all the slack values need to be non-negative. + * Hence, if the worst slack is negative, all the slack values are shifted + * by the value of the worst slack so that the value is at least 0. If the + * worst slack is positive, then no shift happens. + * + * The best (shifted) slack (the most positive one) will have a criticality of 0. + * The worst (shifted) slack value will have a criticality of 1. + * + * Criticalities are used to calculated timing costs for each connection. + * The formula is cost = delay * criticality. + * + * For a more detailed description on how criticalities are calculated, see + * calc_relaxed_criticality() in `timing_util.cpp`. + */ +class PlacerCriticalities { + public: //Types + typedef vtr::vec_id_set::iterator pin_iterator; + typedef vtr::vec_id_set::iterator net_iterator; + + typedef vtr::Range pin_range; + typedef vtr::Range net_range; + + public: //Lifetime + /** + * @brief Allocates space for the timing_place_crit_ data structure. + * @param clb_nlist Used to lookup and iterate clustered netlist connections. + * @param netlist_pin_lookup Used to lookup Atom/Clustered pins connected to a Clustered/Atom pin. + * @param timing_info Holds setup timing info. + * + * @note timing_info may be shared by multiple objects with different lifetimes. + * To ensure timing_info is destroyed only after all its user object are destructed, + * each user object should hold a shared_ptr to it. + */ + PlacerCriticalities(const ClusteredNetlist& clb_nlist, + const ClusteredPinAtomPinsLookup& netlist_pin_lookup, + std::shared_ptr timing_info); + + PlacerCriticalities(const PlacerCriticalities&) = delete; + PlacerCriticalities& operator=(const PlacerCriticalities&) = delete; + + public: //Accessors + ///@brief Returns the criticality of the specified connection. + float criticality(ClusterNetId net, int ipin) const { return timing_place_crit_[net][ipin]; } + + /** + * @brief Returns the range of clustered netlist pins (i.e. ClusterPinIds) which + * were modified by the last call to PlacerCriticalities::update_criticalities(). + */ + pin_range pins_with_modified_criticality() const; + + /// @brief Returns a constant reference to highly critical pins + const std::vector>& get_highly_critical_pins() const { return highly_crit_pins; } + + public: //Modifiers + /** + * @brief Updates criticalities based on the atom netlist criticalities + * provided by timing_info and the provided criticality_exponent. + * + * Should consistently call this method after the most recent timing analysis to + * keep the criticalities stored in this class in sync with the timing analyzer. + * If out of sync, then the criticalities cannot be incrementally updated on + * during the next timing analysis iteration. + * + * If the criticalities are not updated immediately after each time we call + * timing_info->update(), then timing_info->pins_with_modified_setup_criticality() + * cannot accurately account for all the pins that need to be updated. In this case, + * `recompute_required` would be true, and we update all criticalities from scratch. + * If the criticality exponent has changed, we also need to update from scratch. + */ + void update_criticalities(const PlaceCritParams& crit_params); + + ///@bried Enable the recompute_required flag to enforce from scratch update. + void set_recompute_required(); + + /** + * @brief Collect all the sink pins in the netlist and prepare them update. + * + * For the incremental version, see PlacerCriticalities::incr_update_criticalities(). + */ + void recompute_criticalities(); + + ///@brief Override the criticality of a particular connection. + void set_criticality(ClusterNetId net, int ipin, float crit_val); + + ///@brief Set `update_enabled` to true. + void enable_update() { update_enabled = true; } + + ///@brief Set `update_enabled` to true. + void disable_update() { update_enabled = false; } + + private: //Data + ///@brief The clb netlist in the placement context. + const ClusteredNetlist& clb_nlist_; + + ///@brief The lookup table that maps atom pins to clb pins. + const ClusteredPinAtomPinsLookup& pin_lookup_; + + ///@brief A pointer to the setup timing analyzer + std::shared_ptr timing_info_; + + /** + * @brief The matrix that stores criticality value for each connection. + * + * Index range: [0..cluster_ctx.clb_nlist.nets().size()-1][1..num_pins-1] + */ + ClbNetPinsMatrix timing_place_crit_; + + /** + * The criticality exponent when update_criticalites() was last called + * (used to detect if incremental update can be used). + */ + float last_crit_exponent_ = std::numeric_limits::quiet_NaN(); + + ///@brief Set of pins with criticalities modified by last call to update_criticalities(). + vtr::vec_id_set cluster_pins_with_modified_criticality_; + + /** + * @brief Collect the cluster pins which need to be updated based on the latest timing + * analysis so that incremental updates to criticalities can be performed. + * + * Note we use the set of pins reported by the *timing_info* as having modified + * criticality, rather than those marked as modified by the timing analyzer. + * + * Since timing_info uses shifted/relaxed criticality (which depends on max required + * time and worst case slacks), additional nodes may be modified when updating the + * atom pin criticalities. + */ + void incr_update_criticalities(); + + ///@brief Flag that turns on/off the update_criticalities() routine. + bool update_enabled = true; + + /** + * @brief Flag that checks if criticalities need to be recomputed for all connections. + * + * Used by the method update_criticalities(). They incremental update is not possible + * if this method wasn't called updated after the previous timing info update. + */ + bool recompute_required = true; + + /** + * @brief if this is first time to call update_criticality + * + * This can be used for incremental criticality update and also incrementally update the highly critical pins + */ + bool first_time_update_criticality = true; + + /// @brief Saves the highly critical pins (higher than a timing criticality limit set by commandline option) + std::vector> highly_crit_pins; +}; diff --git a/vpr/src/place/timing/PlacerSetupSlacks.cpp b/vpr/src/place/timing/PlacerSetupSlacks.cpp new file mode 100644 index 00000000000..ac8f74d2d7e --- /dev/null +++ b/vpr/src/place/timing/PlacerSetupSlacks.cpp @@ -0,0 +1,81 @@ + +#include "PlacerSetupSlacks.h" + +#include "timing_util.h" +#include "timing_info.h" + +PlacerSetupSlacks::PlacerSetupSlacks(const ClusteredNetlist& clb_nlist, + const ClusteredPinAtomPinsLookup& netlist_pin_lookup, + std::shared_ptr timing_info) + : clb_nlist_(clb_nlist) + , pin_lookup_(netlist_pin_lookup) + , timing_info_(std::move(timing_info)) + , timing_place_setup_slacks_(make_net_pins_matrix(clb_nlist_, std::numeric_limits::quiet_NaN())) { +} + +void PlacerSetupSlacks::update_setup_slacks() { + // If update is not enabled, exit the routine. + if (!update_enabled) { + // re-computation is required on the next iteration + recompute_required = true; + return; + } + + // Determine what pins need updating + if (!recompute_required) { + incr_update_setup_slacks(); + } else { + recompute_setup_slacks(); + } + + // Update the affected pins + for (ClusterPinId clb_pin : cluster_pins_with_modified_setup_slack_) { + ClusterNetId clb_net = clb_nlist_.pin_net(clb_pin); + int pin_index_in_net = clb_nlist_.pin_net_index(clb_pin); + + float clb_pin_setup_slack = calculate_clb_net_pin_setup_slack(*timing_info_, pin_lookup_, clb_pin); + + timing_place_setup_slacks_[clb_net][pin_index_in_net] = clb_pin_setup_slack; + } + + /* Setup slacks updated. In sync with timing info. + * Can be incrementally updated on the next iteration. */ + recompute_required = false; +} + +void PlacerSetupSlacks::incr_update_setup_slacks() { + cluster_pins_with_modified_setup_slack_.clear(); + + for (AtomPinId atom_pin : timing_info_->pins_with_modified_setup_slack()) { + ClusterPinId clb_pin = pin_lookup_.connected_clb_pin(atom_pin); + + //Some atom pins correspond to connections which are completely + //contained within a cluster, and hence have no corresponding + //clustered pin. + if (!clb_pin) continue; + + cluster_pins_with_modified_setup_slack_.insert(clb_pin); + } +} + +void PlacerSetupSlacks::recompute_setup_slacks() { + cluster_pins_with_modified_setup_slack_.clear(); + + // Non-incremental: all sink pins need updating + for (ClusterNetId net_id : clb_nlist_.nets()) { + for (ClusterPinId pin_id : clb_nlist_.net_sinks(net_id)) { + cluster_pins_with_modified_setup_slack_.insert(pin_id); + } + } +} + +void PlacerSetupSlacks::set_setup_slack(ClusterNetId net_id, int ipin, float slack_val) { + VTR_ASSERT_SAFE_MSG(ipin > 0, "The pin should not be a driver pin (ipin != 0)"); + VTR_ASSERT_SAFE_MSG(ipin < int(clb_nlist_.net_pins(net_id).size()), "The pin index in net should be smaller than fanout"); + + timing_place_setup_slacks_[net_id][ipin] = slack_val; +} + +PlacerSetupSlacks::pin_range PlacerSetupSlacks::pins_with_modified_setup_slack() const { + return vtr::make_range(cluster_pins_with_modified_setup_slack_); +} diff --git a/vpr/src/place/timing/PlacerSetupSlacks.h b/vpr/src/place/timing/PlacerSetupSlacks.h new file mode 100644 index 00000000000..521d83809ca --- /dev/null +++ b/vpr/src/place/timing/PlacerSetupSlacks.h @@ -0,0 +1,128 @@ + +#pragma once + +#include "vtr_vec_id_set.h" +#include "timing_info_fwd.h" +#include "clustered_netlist_utils.h" +#include "place_delay_model.h" +#include "vpr_net_pins_matrix.h" + +/** + * @brief PlacerSetupSlacks returns the RAW setup slacks of clustered netlist connection. + * + * Usage + * ===== + * This class mirrors PlacerCriticalities by both its methods and its members. The only + * difference is that this class deals with RAW setup slacks returned by SetupTimingInfo + * rather than criticalities. See the documentation on PlacerCriticalities for more. + * + * RAW setup slacks are unlike criticalities. Their values are not confined between + * 0 and 1. Their values can be either positive or negative. + * + * This class also provides iterating over the clustered netlist connections/pins that + * have modified setup slacks by the last call to update_setup_slacks(). However, this + * utility is mainly used for incrementally committing the setup slack values into the + * structure `connection_setup_slack` used by many placer routines. + */ +class PlacerSetupSlacks { + public: //Types + typedef vtr::vec_id_set::iterator pin_iterator; + typedef vtr::vec_id_set::iterator net_iterator; + + typedef vtr::Range pin_range; + typedef vtr::Range net_range; + + public: //Lifetime + ///@brief Allocates space for the timing_place_setup_slacks_ data structure. + PlacerSetupSlacks(const ClusteredNetlist& clb_nlist, + const ClusteredPinAtomPinsLookup& netlist_pin_lookup, + std::shared_ptr timing_info); + + PlacerSetupSlacks(const PlacerSetupSlacks& clb_nlist) = delete; + PlacerSetupSlacks& operator=(const PlacerSetupSlacks& clb_nlist) = delete; + + public: //Accessors + ///@brief Returns the setup slack of the specified connection. + float setup_slack(ClusterNetId net, int ipin) const { return timing_place_setup_slacks_[net][ipin]; } + + /** + * @brief Returns the range of clustered netlist pins (i.e. ClusterPinIds) + * which were modified by the last call to PlacerSetupSlacks::update_setup_slacks(). + */ + pin_range pins_with_modified_setup_slack() const; + + public: //Modifiers + /** + * @brief Updates setup slacks based on the atom netlist setup slacks provided + * by timing_info_. + * + * @note This function updates the setup slacks in the timing_place_setup_slacks_ + * data structure. + * + * Should consistently call this method after the most recent timing analysis to + * keep the setup slacks stored in this class in sync with the timing analyzer. + * If out of sync, then the setup slacks cannot be incrementally updated during + * the next timing analysis iteration. + * + * If the setup slacks are not updated immediately after each time we cal + * timing_info->update(), then timing_info->pins_with_modified_setup_slack() + * cannot accurately account for all the pins that need to be updated. + * In this case, `recompute_required` would be true, and we update all setup slacks + * from scratch. + */ + void update_setup_slacks(); + + ///@bried Enable the recompute_required flag to enforce from scratch update. + void set_recompute_required() { recompute_required = true; } + + ///@brief Override the setup slack of a particular connection. + void set_setup_slack(ClusterNetId net, int ipin, float slack_val); + + ///@brief Set `update_enabled` to true. + void enable_update() { update_enabled = true; } + + ///@brief Set `update_enabled` to true. + void disable_update() { update_enabled = false; } + + private: //Data + const ClusteredNetlist& clb_nlist_; + const ClusteredPinAtomPinsLookup& pin_lookup_; + std::shared_ptr timing_info_; + + /** + * @brief The matrix that stores raw setup slack values for each connection. + * + * Index range: [0..cluster_ctx.clb_nlist.nets().size()-1][1..num_pins-1] + */ + ClbNetPinsMatrix timing_place_setup_slacks_; + + ///@brief Set of pins with raw setup slacks modified by last call to update_setup_slacks() + vtr::vec_id_set cluster_pins_with_modified_setup_slack_; + + /** + * @brief Collect the cluster pins which need to be updated based on the latest timing + * analysis so that incremental updates to setup slacks can be performed. + * + * Note we use the set of pins reported by the *timing_info* as having modified + * setup slacks, rather than those marked as modified by the timing analyzer. + */ + void incr_update_setup_slacks(); + + /** + * @brief Collect all the sink pins in the netlist and prepare them update. + * + * For the incremental version, see PlacerSetupSlacks::incr_update_setup_slacks(). + */ + void recompute_setup_slacks(); + + ///@brief Flag that turns on/off the update_setup_slacks() routine. + bool update_enabled = true; + + /** + * @brief Flag that checks if setup slacks need to be recomputed for all connections. + * + * Used by the method update_setup_slacks(). They incremental update is not possible + * if this method wasn't called updated after the previous timing info update. + */ + bool recompute_required = true; +}; diff --git a/vpr/src/place/timing/PlacerTimingCosts.cpp b/vpr/src/place/timing/PlacerTimingCosts.cpp new file mode 100644 index 00000000000..483111a14e6 --- /dev/null +++ b/vpr/src/place/timing/PlacerTimingCosts.cpp @@ -0,0 +1,126 @@ + +#include "PlacerTimingCosts.h" + +PlacerTimingCosts::PlacerTimingCosts(const ClusteredNetlist& nlist) { + auto nets = nlist.nets(); + + net_start_indices_.resize(nets.size()); + + // Walk through the netlist to determine how many connections there are. + size_t iconn = 0; + for (ClusterNetId net : nets) { + // The placer always skips 'ignored' nets, so they don't affect timing + // costs, so we also skip them here + if (nlist.net_is_ignored(net)) { + net_start_indices_[net] = OPEN; + continue; + } + + // Save the starting index of the current net's connections. + // We use a -1 offset, since sinks indexed from [1..num_net_pins-1] + // (there is no timing cost associated with net drivers) + net_start_indices_[net] = iconn - 1; + + // Reserve space for all this net's connections + iconn += nlist.net_sinks(net).size(); + } + + const size_t num_connections = iconn; + + // Determine how many binary tree levels we need to have a leaf for each connection cost + size_t ilevel = 0; + while (num_nodes_in_level(ilevel) < num_connections) { + ++ilevel; + } + num_levels_ = ilevel + 1; + + size_t num_leaves = num_nodes_in_level(ilevel); + size_t num_nodes_in_previous_level = num_nodes_in_level(ilevel - 1); + + VTR_ASSERT_MSG(num_leaves >= num_connections, "Need at least as many leaves as connections"); + VTR_ASSERT_MSG(num_connections == 0 || num_nodes_in_previous_level < num_connections, + "Level before should have fewer nodes than connections (to ensure using the smallest binary tree)"); + + // We don't need to store all possible leaves if we have fewer connections (i.e. bottom-right of tree is empty) + size_t last_level_unused_nodes = num_nodes_in_level(ilevel) - num_connections; + size_t num_nodes = num_nodes_up_to_level(ilevel) - last_level_unused_nodes; + + // Reserve space for connection costs and intermediate node values + connection_costs_ = std::vector(num_nodes, std::numeric_limits::quiet_NaN()); + + // The net start indices we calculated earlier didn't account for intermediate binary tree nodes + // Shift the start indices after the intermediate nodes + size_t num_intermediate_nodes = num_nodes_up_to_level(ilevel - 1); + for (ClusterNetId net : nets) { + if (nlist.net_is_ignored(net)) continue; + + net_start_indices_[net] = net_start_indices_[net] + num_intermediate_nodes; + } +} + +double PlacerTimingCosts::total_cost_recurr(size_t inode) { + // Prune out-of-tree + if (inode > connection_costs_.size() - 1) { + return 0.; + } + + //Valid pre-calculated intermediate result or valid leaf + if (!std::isnan(connection_costs_[inode])) { + return connection_costs_[inode]; + } + + //Recompute recursively + double node_cost = total_cost_recurr(left_child(inode)) + + total_cost_recurr(right_child(inode)); + + //Save intermediate cost at this node + connection_costs_[inode] = node_cost; + + return node_cost; +} + +double PlacerTimingCosts::total_cost_from_scratch(size_t inode) const { + // Prune out-of-tree + if (inode > connection_costs_.size() - 1) { + return 0.; + } + + //Recompute recursively + double node_cost = total_cost_from_scratch(left_child(inode)) + + total_cost_from_scratch(right_child(inode)); + + return node_cost; +} + +void PlacerTimingCosts::invalidate(const double* invalidated_cost) { + //Check pointer within range of internal storage + VTR_ASSERT_SAFE_MSG( + invalidated_cost >= &connection_costs_[0], + "Connection cost pointer should be after start of internal storage"); + + VTR_ASSERT_SAFE_MSG( + invalidated_cost <= &connection_costs_[connection_costs_.size() - 1], + "Connection cost pointer should be before end of internal storage"); + + size_t icost = invalidated_cost - &connection_costs_[0]; + + VTR_ASSERT_SAFE(icost >= num_nodes_up_to_level(num_levels_ - 2)); + + //Invalidate parent intermediate costs up to root or first + //already-invalidated parent + size_t iparent = parent(icost); + + while (!std::isnan(connection_costs_[iparent])) { + //Invalidate + connection_costs_[iparent] = std::numeric_limits::quiet_NaN(); + + if (iparent == 0) { + break; //At root + } else { + //Next parent + iparent = parent(iparent); + } + } + + VTR_ASSERT_SAFE_MSG(std::isnan(connection_costs_[0]), "Invalidating any connection should have invalidated the root"); +} diff --git a/vpr/src/place/timing/PlacerTimingCosts.h b/vpr/src/place/timing/PlacerTimingCosts.h new file mode 100644 index 00000000000..5e1415581c3 --- /dev/null +++ b/vpr/src/place/timing/PlacerTimingCosts.h @@ -0,0 +1,242 @@ + +#pragma once +#include "vtr_vec_id_set.h" +#include "timing_info_fwd.h" +#include "clustered_netlist_utils.h" +#include "place_delay_model.h" +#include "vpr_net_pins_matrix.h" + +/** + * @brief PlacerTimingCosts mimics a 2D array of connection timing costs running from: + * [0..cluster_ctx.clb_nlist.nets().size()-1][1..num_pins-1]. + * + * It can be used similar to: + * + * PlacerTimingCosts connection_timing_costs(cluster_ctx.clb_nlist); //Construct + * + * //... + * + * //Modify a connection cost + * connection_timing_costs[net_id][ipin] = new_cost; + * + * //Potentially other modifications... + * + * //Calculate the updated timing cost, of all connections, + * //incrementally based on modifications + * float total_timing_cost = connection_timing_costs.total_cost(); + * + * However behind the scenes PlacerTimingCosts tracks when connection costs are modified, + * and efficiently re-calculates the total timing cost incrementally based on the connections + * which have had their cost modified. + * + * Implementation + * ============== + * Internally, PlacerTimingCosts stores all connection costs in a flat array in the last part + * of connection_costs_. To mimic 2d-array like access PlacerTimingCosts also uses two proxy + * classes which allow indexing in the net and pin dimensions (NetProxy and ConnectionProxy + * respectively). + * + * The first part of connection_costs_ stores intermediate sums of the connection costs for + * efficient incremental re-calculation. More concretely, connection_costs_ stores a binary + * tree, where leaves correspond to individual connection costs and intermediate nodes the + * partial sums of the connection costs. (The binary tree is stored implicitly in the + * connection_costs_ vector, using Eytzinger's/BFS layout.) By summing the entire binary + * tree we calculate the total timing cost over all connections. + * + * Using a binary tree allows us to efficiently re-calculate the timing costs when only a subset + * of connections are changed. This is done by 'invalidating' intermediate nodes (from leaves up + * to the root) which have ancestors (leaves) with modified connection costs. When the + * total_cost() method is called, it recursively walks the binary tree to re-calculate the cost. + * Only invalidated nodes are traversed, with valid nodes just returning their previously + * calculated (and unchanged) value. + * + * For a circuit with 'K' connections, of which 'k' have changed (typically k << K), this can + * be done in O(k log K) time. + * + * It is important to note that due to limited floating point precision, floating point + * arithmetic has an order dependence (due to round-off). Using a binary tree to total + * the timing connection costs allows us to incrementally update the total timing cost while + * maintaining the *same order of operations* as if it was re-computed from scratch. This + * ensures we *always* get consistent results regardless of what/when connections are changed. + * + * Proxy Classes + * ============= + * NetProxy is returned by PlacerTimingCost's operator[], and stores a pointer to the start of + * internal storage of that net's connection costs. + * + * ConnectionProxy is returned by NetProxy's operator[], and holds a reference to a particular + * element of the internal storage pertaining to a specific connection's cost. ConnectionProxy + * supports assignment, allowing clients to modify the connection cost. It also detects if the + * assigned value differs from the previous value and if so, calls PlacerTimingCosts's + * invalidate() method on that connection cost. + * + * PlacerTimingCosts's invalidate() method marks the cost element's ancestors as invalid (NaN) + * so they will be re-calculated by PlacerTimingCosts' total_cost() method. + */ +class PlacerTimingCosts { + public: + PlacerTimingCosts() = default; + + PlacerTimingCosts(const ClusteredNetlist& nlist); + + /** + * @brief Proxy class representing a connection cost. + * + * Supports modification of connection cost while detecting + * changes and reporting them up to PlacerTimingCosts. + */ + class ConnectionProxy { + public: + ConnectionProxy(PlacerTimingCosts* timing_costs, double& connection_cost) + : timing_costs_(timing_costs) + , connection_cost_(connection_cost) {} + + ///@brief Allow clients to modify the connection cost via assignment. + ConnectionProxy& operator=(double new_cost) { + if (new_cost != connection_cost_) { + //If connection cost changed, update it, and mark it + //as invalidated + connection_cost_ = new_cost; + timing_costs_->invalidate(&connection_cost_); + } + return *this; + } + + /** + * @brief Support getting the current connection cost as a double. + * + * Useful for client code operating on the cost values (e.g. difference between costs). + */ + operator double() const { + return connection_cost_; + } + + private: + PlacerTimingCosts* timing_costs_; + double& connection_cost_; + }; + + /** + * @brief Proxy class representing the connection costs of a net. + * + * Supports indexing by pin index to retrieve the ConnectionProxy for that pin/connection. + */ + class NetProxy { + public: + NetProxy(PlacerTimingCosts* timing_costs, double* net_sink_costs) + : timing_costs_(timing_costs) + , net_sink_costs_(net_sink_costs) {} + + ///@brief Indexes into the specific net pin/connection. + ConnectionProxy operator[](size_t ipin) { + return ConnectionProxy(timing_costs_, net_sink_costs_[ipin]); + } + + const ConnectionProxy operator[](size_t ipin) const { + return ConnectionProxy(timing_costs_, net_sink_costs_[ipin]); + } + + private: + PlacerTimingCosts* timing_costs_; + double* net_sink_costs_; + }; + + ///@brief Indexes into the specific net. + NetProxy operator[](ClusterNetId net_id) { + VTR_ASSERT_SAFE(net_start_indices_[net_id] >= 0); + + double* net_connection_costs = &connection_costs_[net_start_indices_[net_id]]; + return NetProxy(this, net_connection_costs); + } + + NetProxy operator[](ClusterNetId net_id) const { + VTR_ASSERT_SAFE(net_start_indices_[net_id] >= 0); + + const double* net_connection_costs = &connection_costs_[net_start_indices_[net_id]]; + return NetProxy(const_cast(this), const_cast(net_connection_costs)); + } + + void clear() { + connection_costs_.clear(); + net_start_indices_.clear(); + } + + void swap(PlacerTimingCosts& other) { + std::swap(connection_costs_, other.connection_costs_); + std::swap(net_start_indices_, other.net_start_indices_); + std::swap(num_levels_, other.num_levels_); + } + + /** + * @brief Calculates the total cost of all connections efficiently + * in the face of modified connection costs. + */ + double total_cost() { + float cost = total_cost_recurr(0); //Root + + VTR_ASSERT_DEBUG_MSG(cost == total_cost_from_scratch(0), + "Expected incremental and from-scratch costs to be consistent"); + + return cost; + } + + private: + ///@brief Recursively calculate and update the timing cost rooted at inode. + double total_cost_recurr(size_t inode); + + double total_cost_from_scratch(size_t inode) const; + + ///@brief Friend-ed so it can call invalidate(). + friend ConnectionProxy; + + void invalidate(const double* invalidated_cost); + + static size_t left_child(size_t i) { + return 2 * i + 1; + } + + static size_t right_child(size_t i) { + return 2 * i + 2; + } + + static size_t parent(size_t i) { + return (i - 1) / 2; + } + + /** + * @brief Returns the number of nodes in ilevel'th level. + * + * If ilevel is negative, return 0, since the root shouldn't + * be counted as a leaf node candidate. + */ + static size_t num_nodes_in_level(int ilevel) { + return ilevel < 0 ? 0 : (2 << (ilevel)); + } + + ///@brief Returns the total number of nodes in levels [0..ilevel] (inclusive). + static size_t num_nodes_up_to_level(int ilevel) { + return (2 << (ilevel + 1)) - 1; + } + + private: + /** + * @brief Vector storing the implicit binary tree of connection costs. + * + * The actual connections are stored at the end of the vector + * (last level of the binary tree). The earlier portions of + * the tree are the intermediate nodes. + * + * The methods left_child()/right_child()/parent() can be used + * to traverse the tree by indices into this vector. + */ + std::vector connection_costs_; + + /** + * @brief Vector storing the indices of the first connection + * for each net in the netlist, used for indexing by net. + */ + vtr::vector net_start_indices_; + + ///@brief Number of levels in the binary tree. + size_t num_levels_ = 0; +}; diff --git a/vpr/src/place/place_timing_update.cpp b/vpr/src/place/timing/place_timing_update.cpp similarity index 98% rename from vpr/src/place/place_timing_update.cpp rename to vpr/src/place/timing/place_timing_update.cpp index c9c53b88f90..e038af00860 100644 --- a/vpr/src/place/place_timing_update.cpp +++ b/vpr/src/place/timing/place_timing_update.cpp @@ -3,10 +3,14 @@ * @brief Defines the routines declared in place_timing_update.h. */ -#include "vtr_time.h" - #include "place_timing_update.h" + +#include "NetPinTimingInvalidator.h" +#include "PlacerCriticalities.h" +#include "PlacerSetupSlacks.h" #include "placer_state.h" +#include "place_util.h" +#include "vtr_time.h" /* Routines local to place_timing_update.cpp */ static double comp_td_connection_cost(const PlaceDelayModel* delay_model, @@ -94,8 +98,7 @@ void perform_full_timing_update(const PlaceCritParams& crit_params, timing_info, criticalities, setup_slacks, - pin_timing_invalidator, - placer_state); + pin_timing_invalidator); /* Update the timing cost with new connection criticalities. */ update_timing_cost(delay_model, @@ -136,13 +139,12 @@ void update_timing_classes(const PlaceCritParams& crit_params, SetupTimingInfo* timing_info, PlacerCriticalities* criticalities, PlacerSetupSlacks* setup_slacks, - NetPinTimingInvalidator* pin_timing_invalidator, - PlacerState& placer_state) { + NetPinTimingInvalidator* pin_timing_invalidator) { /* Run STA to update slacks and adjusted/relaxed criticalities. */ timing_info->update(); /* Update the placer's criticalities (e.g. sharpen with crit_exponent). */ - criticalities->update_criticalities(crit_params, placer_state); + criticalities->update_criticalities(crit_params); /* Update the placer's raw setup slacks. */ setup_slacks->update_setup_slacks(); diff --git a/vpr/src/place/place_timing_update.h b/vpr/src/place/timing/place_timing_update.h similarity index 93% rename from vpr/src/place/place_timing_update.h rename to vpr/src/place/timing/place_timing_update.h index 7944c4a7552..8e7a0dc1f46 100644 --- a/vpr/src/place/place_timing_update.h +++ b/vpr/src/place/timing/place_timing_update.h @@ -4,10 +4,15 @@ */ #pragma once -#include "timing_place.h" -#include "place_util.h" -#include "NetPinTimingInvalidator.h" +class PlacerState; +class PlaceCritParams; +class PlacerCriticalities; +class PlacerSetupSlacks; +class NetPinTimingInvalidator; +class PlaceDelayModel; +class SetupTimingInfo; +struct t_placer_costs; ///@brief Initialize the timing information and structures in the placer. void initialize_timing_info(const PlaceCritParams& crit_params, @@ -34,8 +39,7 @@ void update_timing_classes(const PlaceCritParams& crit_params, SetupTimingInfo* timing_info, PlacerCriticalities* criticalities, PlacerSetupSlacks* setup_slacks, - NetPinTimingInvalidator* pin_timing_invalidator, - PlacerState& placer_state); + NetPinTimingInvalidator* pin_timing_invalidator); ///@brief Updates the timing driven (td) costs. void update_timing_cost(const PlaceDelayModel* delay_model, diff --git a/vpr/src/place/timing_place.cpp b/vpr/src/place/timing_place.cpp deleted file mode 100644 index badd9d1fb61..00000000000 --- a/vpr/src/place/timing_place.cpp +++ /dev/null @@ -1,270 +0,0 @@ -/** - * @file timing_place.cpp - * @brief Stores the method definitions of classes defined in timing_place.h. - */ - -#include - -#include "vtr_util.h" - -#include "vpr_types.h" -#include "vpr_utils.h" -#include "net_delay.h" -#include "timing_place.h" -#include "placer_state.h" - -#include "timing_info.h" - -///@brief Allocates space for the timing_place_crit_ data structure. -PlacerCriticalities::PlacerCriticalities(const ClusteredNetlist& clb_nlist, - const ClusteredPinAtomPinsLookup& netlist_pin_lookup, - std::shared_ptr timing_info) - : clb_nlist_(clb_nlist) - , pin_lookup_(netlist_pin_lookup) - , timing_info_(std::move(timing_info)) - , timing_place_crit_(make_net_pins_matrix(clb_nlist_, std::numeric_limits::quiet_NaN())) { -} - -/** - * @brief Updated the criticalities in the timing_place_crit_ data structure. - * - * If the criticalities are not updated immediately after each time we call - * timing_info->update(), then timing_info->pins_with_modified_setup_criticality() - * cannot accurately account for all the pins that need to be updated. In this case, - * `recompute_required` would be true, and we update all criticalities from scratch. - * - * If the criticality exponent has changed, we also need to update from scratch. - */ -void PlacerCriticalities::update_criticalities(const PlaceCritParams& crit_params, - PlacerState& placer_state) { - /* If update is not enabled, exit the routine. */ - if (!update_enabled) { - /* re-computation is required on the next iteration */ - recompute_required = true; - return; - } - - /* Determine what pins need updating */ - if (!recompute_required && crit_params.crit_exponent == last_crit_exponent_) { - incr_update_criticalities(); - } else { - recompute_criticalities(); - - /* Record new criticality exponent */ - last_crit_exponent_ = crit_params.crit_exponent; - } - - auto& place_move_ctx = placer_state.mutable_move(); - - /* Performs a 1-to-1 mapping from criticality to timing_place_crit_. - * For every pin on every net (or, equivalently, for every tedge ending - * in that pin), timing_place_crit_ = criticality^(criticality exponent) */ - - /* Update the affected pins */ - for (ClusterPinId clb_pin : cluster_pins_with_modified_criticality_) { - ClusterNetId clb_net = clb_nlist_.pin_net(clb_pin); - int pin_index_in_net = clb_nlist_.pin_net_index(clb_pin); - // Routing for placement is not flat (at least for the time being) - float clb_pin_crit = calculate_clb_net_pin_criticality(*timing_info_, pin_lookup_, ParentPinId(size_t(clb_pin)), /*is_flat=*/false); - - float new_crit = pow(clb_pin_crit, crit_params.crit_exponent); - /* - * Update the highly critical pins container - * - * If the old criticality < limit and the new criticality > limit --> add this pin to the highly critical pins - * If the old criticality > limit and the new criticality < limit --> remove this pin from the highly critical pins - */ - if (!first_time_update_criticality) { - if (new_crit > crit_params.crit_limit && timing_place_crit_[clb_net][pin_index_in_net] < crit_params.crit_limit) { - place_move_ctx.highly_crit_pins.emplace_back(clb_net, pin_index_in_net); - } else if (new_crit < crit_params.crit_limit && timing_place_crit_[clb_net][pin_index_in_net] > crit_params.crit_limit) { - place_move_ctx.highly_crit_pins.erase(std::remove(place_move_ctx.highly_crit_pins.begin(), place_move_ctx.highly_crit_pins.end(), std::make_pair(clb_net, pin_index_in_net)), - place_move_ctx.highly_crit_pins.end()); - } - } else { - if (new_crit > crit_params.crit_limit) { - place_move_ctx.highly_crit_pins.emplace_back(clb_net, pin_index_in_net); - } - } - - /* The placer likes a great deal of contrast between criticalities. - * Since path criticality varies much more than timing, we "sharpen" timing - * criticality by taking it to some power, crit_exponent (between 1 and 8 by default). */ - timing_place_crit_[clb_net][pin_index_in_net] = new_crit; - } - - /* Criticalities updated. In sync with timing info. */ - /* Can be incrementally updated on the next iteration */ - recompute_required = false; - - first_time_update_criticality = false; -} - -void PlacerCriticalities::set_recompute_required() { - recompute_required = true; -} - -/** - * @brief Collect the cluster pins which need to be updated based on the latest timing - * analysis so that incremental updates to criticalities can be performed. - * - * Note we use the set of pins reported by the *timing_info* as having modified - * criticality, rather than those marked as modified by the timing analyzer. - * - * Since timing_info uses shifted/relaxed criticality (which depends on max required - * time and worst case slacks), additional nodes may be modified when updating the - * atom pin criticalities. - */ - -void PlacerCriticalities::incr_update_criticalities() { - cluster_pins_with_modified_criticality_.clear(); - - for (AtomPinId atom_pin : timing_info_->pins_with_modified_setup_criticality()) { - ClusterPinId clb_pin = pin_lookup_.connected_clb_pin(atom_pin); - - //Some atom pins correspond to connections which are completely - //contained within a cluster, and hence have no corresponding - //clustered pin. - if (!clb_pin) continue; - - cluster_pins_with_modified_criticality_.insert(clb_pin); - } -} - -/** - * @brief Collect all the sink pins in the netlist and prepare them update. - * - * For the incremental version, see PlacerCriticalities::incr_update_criticalities(). - */ -void PlacerCriticalities::recompute_criticalities() { - cluster_pins_with_modified_criticality_.clear(); - - /* Non-incremental: all sink pins need updating */ - for (ClusterNetId net_id : clb_nlist_.nets()) { - for (ClusterPinId pin_id : clb_nlist_.net_sinks(net_id)) { - cluster_pins_with_modified_criticality_.insert(pin_id); - } - } -} - -///@brief Override the criticality of a particular connection. -void PlacerCriticalities::set_criticality(ClusterNetId net_id, int ipin, float crit_val) { - VTR_ASSERT_SAFE_MSG(ipin > 0, "The pin should not be a driver pin (ipin != 0)"); - VTR_ASSERT_SAFE_MSG(ipin < int(clb_nlist_.net_pins(net_id).size()), "The pin index in net should be smaller than fanout"); - - timing_place_crit_[net_id][ipin] = crit_val; -} - -/** - * @brief Returns the range of clustered netlist pins (i.e. ClusterPinIds) which - * were modified by the last call to PlacerCriticalities::update_criticalities(). - */ -PlacerCriticalities::pin_range PlacerCriticalities::pins_with_modified_criticality() const { - return vtr::make_range(cluster_pins_with_modified_criticality_); -} - -/**************************************/ - -///@brief Allocates space for the timing_place_setup_slacks_ data structure. -PlacerSetupSlacks::PlacerSetupSlacks(const ClusteredNetlist& clb_nlist, - const ClusteredPinAtomPinsLookup& netlist_pin_lookup, - std::shared_ptr timing_info) - : clb_nlist_(clb_nlist) - , pin_lookup_(netlist_pin_lookup) - , timing_info_(std::move(timing_info)) - , timing_place_setup_slacks_(make_net_pins_matrix(clb_nlist_, std::numeric_limits::quiet_NaN())) { -} - -/** - * @brief Updated the setup slacks in the timing_place_setup_slacks_ data structure. - * - * If the setup slacks are not updated immediately after each time we call - * timing_info->update(), then timing_info->pins_with_modified_setup_slack() - * cannot accurately account for all the pins that need to be updated. - * - * In this case, `recompute_required` would be true, and we update all setup slacks - * from scratch. - */ -void PlacerSetupSlacks::update_setup_slacks() { - /* If update is not enabled, exit the routine. */ - if (!update_enabled) { - /* re-computation is required on the next iteration */ - recompute_required = true; - return; - } - - /* Determine what pins need updating */ - if (!recompute_required) { - incr_update_setup_slacks(); - } else { - recompute_setup_slacks(); - } - - /* Update the affected pins */ - for (ClusterPinId clb_pin : cluster_pins_with_modified_setup_slack_) { - ClusterNetId clb_net = clb_nlist_.pin_net(clb_pin); - int pin_index_in_net = clb_nlist_.pin_net_index(clb_pin); - - float clb_pin_setup_slack = calculate_clb_net_pin_setup_slack(*timing_info_, pin_lookup_, clb_pin); - - timing_place_setup_slacks_[clb_net][pin_index_in_net] = clb_pin_setup_slack; - } - - /* Setup slacks updated. In sync with timing info. */ - /* Can be incrementally updated on the next iteration. */ - recompute_required = false; -} - -/** - * @brief Collect the cluster pins which need to be updated based on the latest timing - * analysis so that incremental updates to setup slacks can be performed. - * - * Note we use the set of pins reported by the *timing_info* as having modified - * setup slacks, rather than those marked as modified by the timing analyzer. - */ -void PlacerSetupSlacks::incr_update_setup_slacks() { - cluster_pins_with_modified_setup_slack_.clear(); - - for (AtomPinId atom_pin : timing_info_->pins_with_modified_setup_slack()) { - ClusterPinId clb_pin = pin_lookup_.connected_clb_pin(atom_pin); - - //Some atom pins correspond to connections which are completely - //contained within a cluster, and hence have no corresponding - //clustered pin. - if (!clb_pin) continue; - - cluster_pins_with_modified_setup_slack_.insert(clb_pin); - } -} - -/** - * @brief Collect all the sink pins in the netlist and prepare them update. - * - * For the incremental version, see PlacerSetupSlacks::incr_update_setup_slacks(). - */ -void PlacerSetupSlacks::recompute_setup_slacks() { - cluster_pins_with_modified_setup_slack_.clear(); - - /* Non-incremental: all sink pins need updating */ - for (ClusterNetId net_id : clb_nlist_.nets()) { - for (ClusterPinId pin_id : clb_nlist_.net_sinks(net_id)) { - cluster_pins_with_modified_setup_slack_.insert(pin_id); - } - } -} - -///@brief Override the setup slack of a particular connection. -void PlacerSetupSlacks::set_setup_slack(ClusterNetId net_id, int ipin, float slack_val) { - VTR_ASSERT_SAFE_MSG(ipin > 0, "The pin should not be a driver pin (ipin != 0)"); - VTR_ASSERT_SAFE_MSG(ipin < int(clb_nlist_.net_pins(net_id).size()), "The pin index in net should be smaller than fanout"); - - timing_place_setup_slacks_[net_id][ipin] = slack_val; -} - -/** - * @brief Returns the range of clustered netlist pins (i.e. ClusterPinIds) - * which were modified by the last call to PlacerSetupSlacks::update_setup_slacks(). - */ -PlacerSetupSlacks::pin_range PlacerSetupSlacks::pins_with_modified_setup_slack() const { - return vtr::make_range(cluster_pins_with_modified_setup_slack_); -} diff --git a/vpr/src/place/timing_place.h b/vpr/src/place/timing_place.h deleted file mode 100644 index 71e144334ad..00000000000 --- a/vpr/src/place/timing_place.h +++ /dev/null @@ -1,647 +0,0 @@ -/** - * @file timing_place.h - * @brief Interface used by the VPR placer to query information - * from the Tatum timing analyzer. - * - * @class PlacerSetupSlacks - * Queries connection **RAW** setup slacks, which can - * range from negative to positive values. Also maps - * atom pin setup slacks to clb pin setup slacks. - * @class PlacerCriticalities - * Query connection criticalities, which are calculuated - * based on the raw setup slacks and ranges from 0 to 1. - * Also maps atom pin crit. to clb pin crit. - * @class PlacerTimingCosts - * Hierarchical structure used by update_td_costs() to - * maintain the order of addition operation of float values - * (to avoid round-offs) while doing incremental updates. - * - * Calculating criticalities: - * All the raw setup slack values across a single clock domain are gathered - * and rated from the best to the worst in terms of criticalities. In order - * to calculate criticalities, all the slack values need to be non-negative. - * Hence, if the worst slack is negative, all the slack values are shifted - * by the value of the worst slack so that the value is at least 0. If the - * worst slack is positive, then no shift happens. - * - * The best (shifted) slack (the most positive one) will have a criticality of 0. - * The worst (shifted) slack value will have a criticality of 1. - * - * Criticalities are used to calculated timing costs for each connection. - * The formula is cost = delay * criticality. - * - * For a more detailed description on how criticalities are calculated, see - * calc_relaxed_criticality() in `timing_util.cpp`. - */ - -#pragma once -#include "vtr_vec_id_set.h" -#include "timing_info_fwd.h" -#include "clustered_netlist_utils.h" -#include "place_delay_model.h" -#include "vpr_net_pins_matrix.h" - -/** - * @brief Saves the placement criticality parameters - * - * crit_exponent: The criticality exponent used to sharpen the criticalities - * crit_limit: The limit to consider a pin as timing critical - */ -struct PlaceCritParams { - float crit_exponent; - float crit_limit; -}; - -/** - * @brief PlacerCriticalities returns the clustered netlist connection criticalities - * used by the placer ('sharpened' by a criticality exponent). - * - * Usage - * ===== - * This class also serves to map atom netlist level criticalites (i.e. on AtomPinIds) - * to the clustered netlist (i.e. ClusterPinIds) used during placement. - * - * Criticalities are updated by update_criticalities(), given that `update_enabled` is - * set to true. It will update criticalities based on the atom netlist connection - * criticalities provided by the passed in SetupTimingInfo. - * - * This process can be done incrementally, based on the modified connections/AtomPinIds - * returned by SetupTimingInfo. However, the set returned only reflects the connections - * changed by the last call to the timing info update. - * - * Therefore, if SetupTimingInfo is updated twice in succession without criticalities - * getting updated (update_enabled = false), the returned set cannot account for all - * the connections that have been modified. In this case, we flag `recompute_required` - * as false, and we recompute the criticalities for every connection to ensure that - * they are all up to date. Hence, each time update_setup_slacks_and_criticalities() - * is called, we assign `recompute_required` the opposite value of `update_enabled`. - * - * This class also maps/transforms the modified atom connections/pins returned by the - * timing info into modified clustered netlist connections/pins after calling - * update_criticalities(). The interface then enables users to iterate over this range - * via pins_with_modified_criticalities(). This is useful for incrementally re-calculating - * the timing costs. - * - * The criticalities of individual connections can then be queried by calling the - * criticality() member function. - * - * Implementation - * ============== - * To support incremental re-calculation, the class saves the last criticality exponent - * passed to PlacerCriticalities::update_criticalites(). If the next update uses the same - * exponent, criticalities can be incrementally updated. Otherwise, they must be re-calculated - * from scratch, since a change in exponent changes *all* criticalities. - */ -class PlacerCriticalities { - public: //Types - typedef vtr::vec_id_set::iterator pin_iterator; - typedef vtr::vec_id_set::iterator net_iterator; - - typedef vtr::Range pin_range; - typedef vtr::Range net_range; - - public: //Lifetime - PlacerCriticalities(const ClusteredNetlist& clb_nlist, - const ClusteredPinAtomPinsLookup& netlist_pin_lookup, - std::shared_ptr timing_info); - PlacerCriticalities(const PlacerCriticalities&) = delete; - PlacerCriticalities& operator=(const PlacerCriticalities&) = delete; - - public: //Accessors - ///@brief Returns the criticality of the specified connection. - float criticality(ClusterNetId net, int ipin) const { return timing_place_crit_[net][ipin]; } - - /** - * @brief Returns the range of clustered netlist pins (i.e. ClusterPinIds) which - * were modified by the last call to PlacerCriticalities::update_criticalities(). - */ - pin_range pins_with_modified_criticality() const; - - public: //Modifiers - /** - * @brief Updates criticalities based on the atom netlist criticalitites - * provided by timing_info and the provided criticality_exponent. - * - * Should consistently call this method after the most recent timing analysis to - * keep the criticalities stored in this class in sync with the timing analyzer. - * If out of sync, then the criticalities cannot be incrementally updated on - * during the next timing analysis iteration. - */ - void update_criticalities(const PlaceCritParams& crit_params, - PlacerState& placer_state); - - ///@bried Enable the recompute_required flag to enforce from scratch update. - void set_recompute_required(); - - ///@brief From scratch update. See timing_place.cpp for more. - void recompute_criticalities(); - - ///@brief Override the criticality of a particular connection. - void set_criticality(ClusterNetId net, int ipin, float crit_val); - - ///@brief Set `update_enabled` to true. - void enable_update() { update_enabled = true; } - - ///@brief Set `update_enabled` to true. - void disable_update() { update_enabled = false; } - - private: //Data - ///@brief The clb netlist in the placement context. - const ClusteredNetlist& clb_nlist_; - - ///@brief The lookup table that maps atom pins to clb pins. - const ClusteredPinAtomPinsLookup& pin_lookup_; - - ///@brief A pointer to the setup timing analyzer - std::shared_ptr timing_info_; - - /** - * @brief The matrix that stores criticality value for each connection. - * - * Index range: [0..cluster_ctx.clb_nlist.nets().size()-1][1..num_pins-1] - */ - ClbNetPinsMatrix timing_place_crit_; - - /** - * The criticality exponent when update_criticalites() was last called - * (used to detect if incremental update can be used). - */ - float last_crit_exponent_ = std::numeric_limits::quiet_NaN(); - - ///@brief Set of pins with criticaltites modified by last call to update_criticalities(). - vtr::vec_id_set cluster_pins_with_modified_criticality_; - - ///@brief Incremental update. See timing_place.cpp for more. - void incr_update_criticalities(); - - ///@brief Flag that turns on/off the update_criticalities() routine. - bool update_enabled = true; - - /** - * @brief Flag that checks if criticalities need to be recomputed for all connections. - * - * Used by the method update_criticalities(). They incremental update is not possible - * if this method wasn't called updated after the previous timing info update. - */ - bool recompute_required = true; - - /** - * @brief if this is first time to call update_criticality - * - * This can be used for incremental criticality update and also incrementally update the highly critical pins - */ - bool first_time_update_criticality = true; -}; - -/** - * @brief PlacerSetupSlacks returns the RAW setup slacks of clustered netlist connection. - * - * Usage - * ===== - * This class mirrors PlacerCriticalities by both its methods and its members. The only - * difference is that this class deals with RAW setup slacks returned by SetupTimingInfo - * rather than criticalities. See the documentation on PlacerCriticalities for more. - * - * RAW setup slacks are unlike criticalities. Their values are not confined between - * 0 and 1. Their values can be either positive or negative. - * - * This class also provides iterating over the clustered netlist connections/pins that - * have modified setup slacks by the last call to update_setup_slacks(). However, this - * utility is mainly used for incrementally committing the setup slack values into the - * structure `connection_setup_slack` used by many placer routines. - */ -class PlacerSetupSlacks { - public: //Types - typedef vtr::vec_id_set::iterator pin_iterator; - typedef vtr::vec_id_set::iterator net_iterator; - - typedef vtr::Range pin_range; - typedef vtr::Range net_range; - - public: //Lifetime - PlacerSetupSlacks(const ClusteredNetlist& clb_nlist, - const ClusteredPinAtomPinsLookup& netlist_pin_lookup, - std::shared_ptr timing_info); - PlacerSetupSlacks(const PlacerSetupSlacks& clb_nlist) = delete; - PlacerSetupSlacks& operator=(const PlacerSetupSlacks& clb_nlist) = delete; - - public: //Accessors - ///@brief Returns the setup slack of the specified connection. - float setup_slack(ClusterNetId net, int ipin) const { return timing_place_setup_slacks_[net][ipin]; } - - /** - * @brief Returns the range of clustered netlist pins (i.e. ClusterPinIds) - * which were modified by the last call to PlacerSetupSlacks::update_setup_slacks(). - */ - pin_range pins_with_modified_setup_slack() const; - - public: //Modifiers - /** - * @brief Updates setup slacks based on the atom netlist setup slacks provided - * by timing_info_. - * - * Should consistently call this method after the most recent timing analysis to - * keep the setup slacks stored in this class in sync with the timing analyzer. - * If out of sync, then the setup slacks cannot be incrementally updated on - * during the next timing analysis iteration. - */ - void update_setup_slacks(); - - ///@bried Enable the recompute_required flag to enforce from scratch update. - void set_recompute_required() { recompute_required = true; } - - ///@brief Override the setup slack of a particular connection. - void set_setup_slack(ClusterNetId net, int ipin, float slack_val); - - ///@brief Set `update_enabled` to true. - void enable_update() { update_enabled = true; } - - ///@brief Set `update_enabled` to true. - void disable_update() { update_enabled = false; } - - private: //Data - const ClusteredNetlist& clb_nlist_; - const ClusteredPinAtomPinsLookup& pin_lookup_; - std::shared_ptr timing_info_; - - /** - * @brief The matrix that stores raw setup slack values for each connection. - * - * Index range: [0..cluster_ctx.clb_nlist.nets().size()-1][1..num_pins-1] - */ - ClbNetPinsMatrix timing_place_setup_slacks_; - - ///@brief Set of pins with raw setup slacks modified by last call to update_setup_slacks() - vtr::vec_id_set cluster_pins_with_modified_setup_slack_; - - ///@brief Incremental update. See timing_place.cpp for more. - void incr_update_setup_slacks(); - - ///@brief Incremental update. See timing_place.cpp for more. - void recompute_setup_slacks(); - - ///@brief Flag that turns on/off the update_setup_slacks() routine. - bool update_enabled = true; - - /** - * @brief Flag that checks if setup slacks need to be recomputed for all connections. - * - * Used by the method update_setup_slacks(). They incremental update is not possible - * if this method wasn't called updated after the previous timing info update. - */ - bool recompute_required = true; -}; - -/** - * @brief PlacerTimingCosts mimics a 2D array of connection timing costs running from: - * [0..cluster_ctx.clb_nlist.nets().size()-1][1..num_pins-1]. - * - * It can be used similar to: - * - * PlacerTimingCosts connection_timing_costs(cluster_ctx.clb_nlist); //Construct - * - * //... - * - * //Modify a connection cost - * connection_timing_costs[net_id][ipin] = new_cost; - * - * //Potentially other modifications... - * - * //Calculate the updated timing cost, of all connections, - * //incrementally based on modifications - * float total_timing_cost = connection_timing_costs.total_cost(); - * - * However behind the scenes PlacerTimingCosts tracks when connection costs are modified, - * and efficiently re-calculates the total timing cost incrementally based on the connections - * which have had their cost modified. - * - * Implementation - * ============== - * Internally, PlacerTimingCosts stores all connection costs in a flat array in the last part - * of connection_costs_. To mimic 2d-array like access PlacerTimingCosts also uses two proxy - * classes which allow indexing in the net and pin dimensions (NetProxy and ConnectionProxy - * respectively). - * - * The first part of connection_costs_ stores intermediate sums of the connection costs for - * efficient incremental re-calculation. More concretely, connection_costs_ stores a binary - * tree, where leaves correspond to individual connection costs and intermediate nodes the - * partial sums of the connection costs. (The binary tree is stored implicitly in the - * connection_costs_ vector, using Eytzinger's/BFS layout.) By summing the entire binary - * tree we calculate the total timing cost over all connections. - * - * Using a binary tree allows us to efficiently re-calculate the timing costs when only a subset - * of connections are changed. This is done by 'invalidating' intermediate nodes (from leaves up - * to the root) which have ancestors (leaves) with modified connection costs. When the - * total_cost() method is called, it recursively walks the binary tree to re-calculate the cost. - * Only invalidated nodes are traversed, with valid nodes just returning their previously - * calculated (and unchanged) value. - * - * For a circuit with 'K' connections, of which 'k' have changed (typically k << K), this can - * be done in O(k log K) time. - * - * It is important to note that due to limited floating point precision, floating point - * arithmetic has an order dependence (due to round-off). Using a binary tree to total - * the timing connection costs allows us to incrementally update the total timing cost while - * maintianing the *same order of operations* as if it was re-computed from scratch. This - * ensures we *always* get consistent results regardless of what/when connections are changed. - * - * Proxy Classes - * ============= - * NetProxy is returned by PlacerTimingCost's operator[], and stores a pointer to the start of - * internal storage of that net's connection costs. - * - * ConnectionProxy is returned by NetProxy's operator[], and holds a reference to a particular - * element of the internal storage pertaining to a specific connection's cost. ConnectionProxy - * supports assignment, allowing clients to modify the connection cost. It also detects if the - * assigned value differs from the previous value and if so, calls PlacerTimingCosts's - * invalidate() method on that connection cost. - * - * PlacerTimingCosts's invalidate() method marks the cost element's ancestors as invalid (NaN) - * so they will be re-calculated by PlacerTimingCosts' total_cost() method. - */ -class PlacerTimingCosts { - public: - PlacerTimingCosts() = default; - - PlacerTimingCosts(const ClusteredNetlist& nlist) { - auto nets = nlist.nets(); - - net_start_indicies_.resize(nets.size()); - - //Walk through the netlist to determine how many connections there are. - size_t iconn = 0; - for (ClusterNetId net : nets) { - //The placer always skips 'ignored' nets, so they don't affect timing - //costs, so we also skip them here - if (nlist.net_is_ignored(net)) { - net_start_indicies_[net] = OPEN; - continue; - } - - //Save the startind index of the current net's connections. - // We use a -1 offset, since sinks indexed from [1..num_net_pins-1] - // (there is no timing cost associated with net drivers) - net_start_indicies_[net] = iconn - 1; - - //Reserve space for all this net's connections - iconn += nlist.net_sinks(net).size(); - } - - size_t num_connections = iconn; - - //Determine how many binary tree levels we need to have a leaf - //for each connection cost - size_t ilevel = 0; - while (num_nodes_in_level(ilevel) < num_connections) { - ++ilevel; - } - num_levels_ = ilevel + 1; - - size_t num_leaves = num_nodes_in_level(ilevel); - size_t num_level_before_leaves = num_nodes_in_level(ilevel - 1); - - VTR_ASSERT_MSG(num_leaves >= num_connections, "Need at least as many leaves as connections"); - VTR_ASSERT_MSG( - num_connections == 0 || num_level_before_leaves < num_connections, - "Level before should have fewer nodes than connections (to ensure using the smallest binary tree)"); - - //We don't need to store all possible leaves if we have fewer connections - //(i.e. bottom-right of tree is empty) - size_t last_level_unused_nodes = num_nodes_in_level(ilevel) - num_connections; - size_t num_nodes = num_nodes_up_to_level(ilevel) - last_level_unused_nodes; - - //Reserve space for connection costs and intermediate node values - connection_costs_ = std::vector(num_nodes, std::numeric_limits::quiet_NaN()); - - //The net start indicies we calculated earlier didn't account for intermediate binary tree nodes - //Shift the start indicies after the intermediate nodes - size_t num_intermediate_nodes = num_nodes_up_to_level(ilevel - 1); - for (ClusterNetId net : nets) { - if (nlist.net_is_ignored(net)) continue; - - net_start_indicies_[net] = net_start_indicies_[net] + num_intermediate_nodes; - } - } - - /** - * @brief Proxy class representing a connection cost. - * - * Supports modification of connection cost while detecting - * changes and reporting them up to PlacerTimingCosts. - */ - class ConnectionProxy { - public: - ConnectionProxy(PlacerTimingCosts* timing_costs, double& connection_cost) - : timing_costs_(timing_costs) - , connection_cost_(connection_cost) {} - - ///@brief Allow clients to modify the connection cost via assignment. - ConnectionProxy& operator=(double new_cost) { - if (new_cost != connection_cost_) { - //If connection cost changed, update it, and mark it - //as invalidated - connection_cost_ = new_cost; - timing_costs_->invalidate(&connection_cost_); - } - return *this; - } - - /** - * @brief Support getting the current connection cost as a double. - * - * Useful for client code operating on the cost values (e.g. difference between costs). - */ - operator double() const { - return connection_cost_; - } - - private: - PlacerTimingCosts* timing_costs_; - double& connection_cost_; - }; - - /** - * @brief Proxy class representing the connection costs of a net. - * - * Supports indexing by pin index to retrieve the ConnectionProxy for that pin/connection. - */ - class NetProxy { - public: - NetProxy(PlacerTimingCosts* timing_costs, double* net_sink_costs) - : timing_costs_(timing_costs) - , net_sink_costs_(net_sink_costs) {} - - ///@brief Indexes into the specific net pin/connection. - ConnectionProxy operator[](size_t ipin) { - return ConnectionProxy(timing_costs_, net_sink_costs_[ipin]); - } - - const ConnectionProxy operator[](size_t ipin) const { - return ConnectionProxy(timing_costs_, net_sink_costs_[ipin]); - } - - private: - PlacerTimingCosts* timing_costs_; - double* net_sink_costs_; - }; - - ///@brief Indexes into the specific net. - NetProxy operator[](ClusterNetId net_id) { - VTR_ASSERT_SAFE(net_start_indicies_[net_id] >= 0); - - double* net_connection_costs = &connection_costs_[net_start_indicies_[net_id]]; - return NetProxy(this, net_connection_costs); - } - - NetProxy operator[](ClusterNetId net_id) const { - VTR_ASSERT_SAFE(net_start_indicies_[net_id] >= 0); - - const double* net_connection_costs = &connection_costs_[net_start_indicies_[net_id]]; - return NetProxy(const_cast(this), const_cast(net_connection_costs)); - } - - void clear() { - connection_costs_.clear(); - net_start_indicies_.clear(); - } - - void swap(PlacerTimingCosts& other) { - std::swap(connection_costs_, other.connection_costs_); - std::swap(net_start_indicies_, other.net_start_indicies_); - std::swap(num_levels_, other.num_levels_); - } - - /** - * @brief Calculates the total cost of all connections efficiently - * in the face of modified connection costs. - */ - double total_cost() { - float cost = total_cost_recurr(0); //Root - - VTR_ASSERT_DEBUG_MSG(cost == total_cost_from_scratch(0), - "Expected incremental and from-scratch costs to be consistent"); - - return cost; - } - - private: - ///@brief Recursively calculate and update the timing cost rooted at inode. - double total_cost_recurr(size_t inode) { - //Prune out-of-tree - if (inode > connection_costs_.size() - 1) { - return 0.; - } - - //Valid pre-calculated intermediate result or valid leaf - if (!std::isnan(connection_costs_[inode])) { - return connection_costs_[inode]; - } - - //Recompute recursively - double node_cost = total_cost_recurr(left_child(inode)) - + total_cost_recurr(right_child(inode)); - - //Save intermedate cost at this node - connection_costs_[inode] = node_cost; - - return node_cost; - } - - double total_cost_from_scratch(size_t inode) const { - //Prune out-of-tree - if (inode > connection_costs_.size() - 1) { - return 0.; - } - - //Recompute recursively - double node_cost = total_cost_from_scratch(left_child(inode)) - + total_cost_from_scratch(right_child(inode)); - - return node_cost; - } - - ///@brief Friend-ed so it can call invalidate(). - friend ConnectionProxy; - - void invalidate(double* invalidated_cost) { - //Check pointer within range of internal storage - VTR_ASSERT_SAFE_MSG( - invalidated_cost >= &connection_costs_[0], - "Connection cost pointer should be after start of internal storage"); - - VTR_ASSERT_SAFE_MSG( - invalidated_cost <= &connection_costs_[connection_costs_.size() - 1], - "Connection cost pointer should be before end of internal storage"); - - size_t icost = invalidated_cost - &connection_costs_[0]; - - VTR_ASSERT_SAFE(icost >= num_nodes_up_to_level(num_levels_ - 2)); - - //Invalidate parent intermediate costs up to root or first - //already-invalidated parent - size_t iparent = parent(icost); - - while (!std::isnan(connection_costs_[iparent])) { - //Invalidate - connection_costs_[iparent] = std::numeric_limits::quiet_NaN(); - - if (iparent == 0) { - break; //At root - } else { - //Next parent - iparent = parent(iparent); - } - } - - VTR_ASSERT_SAFE_MSG(std::isnan(connection_costs_[0]), "Invalidating any connection should have invalidated the root"); - } - - size_t left_child(size_t i) const { - return 2 * i + 1; - } - - size_t right_child(size_t i) const { - return 2 * i + 2; - } - - size_t parent(size_t i) const { - return (i - 1) / 2; - } - - /** - * @brief Returns the number of nodes in ilevel'th level. - * - * If ilevel is negative, return 0, since the root shouldn't - * be counted as a leaf node candidate. - */ - size_t num_nodes_in_level(int ilevel) const { - return ilevel < 0 ? 0 : (2 << (ilevel)); - } - - ///@brief Returns the total number of nodes in levels [0..ilevel] (inclusive). - size_t num_nodes_up_to_level(int ilevel) const { - return (2 << (ilevel + 1)) - 1; - } - - private: - /** - * @brief Vector storing the implicit binary tree of connection costs. - * - * The actual connections are stored at the end of the vector - * (last level of the binary tree). The earlier portions of - * the tree are the intermediate nodes. - * - * The methods left_child()/right_child()/parent() can be used - * to traverse the tree by indicies into this vector. - */ - std::vector connection_costs_; - - /** - * @brief Vector storing the indicies of the first connection - * for each net in the netlist, used for indexing by net. - */ - vtr::vector net_start_indicies_; - - ///@brief Number of levels in the binary tree. - size_t num_levels_ = 0; -}; diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp deleted file mode 100644 index 86dc396e2b8..00000000000 --- a/vpr/src/place/timing_place_lookup.cpp +++ /dev/null @@ -1,1319 +0,0 @@ - -#include -#include - -#include "rr_graph_fwd.h" -#include "vtr_assert.h" -#include "vtr_ndmatrix.h" -#include "vtr_log.h" -#include "vtr_util.h" -#include "vtr_math.h" -#include "vtr_memory.h" -#include "vtr_time.h" -#include "vtr_geometry.h" - -#include "arch_util.h" -#include "vpr_types.h" -#include "globals.h" -#include "place_and_route.h" -#include "route_net.h" -#include "timing_place_lookup.h" -#include "read_xml_arch_file.h" -#include "atom_netlist.h" - -// all functions in profiling:: namespace, which are only activated if PROFILE is defined -#include "route_profiling.h" -#include "router_delay_profiling.h" -#include "place_delay_model.h" - -/*To compute delay between blocks we calculate the delay between */ -/*different nodes in the FPGA. From this procedure we generate - * a lookup table which tells us the delay between different locations in*/ -/*the FPGA */ - -/*the delta arrays are used to contain the best case routing delay */ -/*between different locations on the FPGA. */ - -//#define VERBOSE - -constexpr float UNINITIALIZED_DELTA = -1; //Indicates the delta delay value has not been calculated -constexpr float EMPTY_DELTA = -2; //Indicates delta delay from/to an EMPTY block -constexpr float IMPOSSIBLE_DELTA = std::numeric_limits::infinity(); //Indicates there is no valid delta delay - -struct t_profile_loc { - t_profile_loc(int x, int y, std::vector> delta_values) - : root(x, y) - , deltas(delta_values) {} - - vtr::Point root; - std::vector> deltas; -}; - -struct t_profile_info { - std::vector locations; - - int max_delta_x; - int max_delta_y; -}; - -/*** Function Prototypes *****/ -static t_chan_width setup_chan_width(const t_router_opts& router_opts, - t_chan_width_dist chan_width_dist); - -static float route_connection_delay( - RouterDelayProfiler& route_profiler, - int from_layer_num, - int to_layer_num, - int source_x_loc, - int source_y_loc, - int sink_x_loc, - int sink_y_loc, - const t_router_opts& router_opts, - bool measure_directconnect); - -// Prototype for computing delta delay matrix. -typedef std::function>&, - int, - int, - int, - int, - int, - int, - int, - int, - const t_router_opts&, - bool, - const std::set&, - bool)> - t_compute_delta_delay_matrix; - -static void generic_compute_matrix_iterative_astar( - RouterDelayProfiler& route_profiler, - vtr::Matrix>& matrix, - int from_layer_num, - int to_layer_num, - int source_x, - int source_y, - int start_x, - int start_y, - int end_x, - int end_y, - const t_router_opts& router_opts, - bool measure_directconnect, - const std::set& allowed_types, - bool /***/); - -static void generic_compute_matrix_dijkstra_expansion( - RouterDelayProfiler& route_profiler, - vtr::Matrix>& matrix, - int from_layer_num, - int to_layer_num, - int source_x, - int source_y, - int start_x, - int start_y, - int end_x, - int end_y, - const t_router_opts& router_opts, - bool measure_directconnect, - const std::set& allowed_types, - bool is_flat); - -static vtr::NdMatrix compute_delta_delays( - RouterDelayProfiler& route_profiler, - const t_placer_opts& palcer_opts, - const t_router_opts& router_opts, - bool measure_directconnect, - size_t longest_length, - bool is_flat); - -float delay_reduce(std::vector& delays, e_reducer reducer); - -static vtr::NdMatrix compute_delta_delay_model( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - bool measure_directconnect, - int longest_length, - bool is_flat); - -/** - * @brief Use the information in the router lookahead to fill the delay matrix instead of running the router - * @param route_profiler - * @return The delay matrix that contain the minimum cost between two locations - */ -static vtr::NdMatrix compute_simple_delay_model(RouterDelayProfiler& route_profiler); - -static bool find_direct_connect_sample_locations(const t_direct_inf* direct, - t_physical_tile_type_ptr from_type, - int from_pin, - int from_pin_class, - t_physical_tile_type_ptr to_type, - int to_pin, - int to_pin_class, - RRNodeId& out_src_node, - RRNodeId& out_sink_node); - -static bool verify_delta_delays(const vtr::NdMatrix& delta_delays); - -static int get_longest_segment_length(std::vector& segment_inf); - -static void fix_empty_coordinates(vtr::NdMatrix& delta_delays); -static void fix_uninitialized_coordinates(vtr::NdMatrix& delta_delays); - -static float find_neighboring_average(vtr::NdMatrix& matrix, - int from_layer, - t_physical_tile_loc to_tile_loc, - int max_distance); - -/******* Globally Accessible Functions **********/ - -std::unique_ptr compute_place_delay_model(const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - const Netlist<>& net_list, - t_det_routing_arch* det_routing_arch, - std::vector& segment_inf, - t_chan_width_dist chan_width_dist, - const std::vector& directs, - bool is_flat) { - vtr::ScopedStartFinishTimer timer("Computing placement delta delay look-up"); - - t_chan_width chan_width = setup_chan_width(router_opts, chan_width_dist); - - alloc_routing_structs(chan_width, router_opts, det_routing_arch, segment_inf, directs, is_flat); - - const RouterLookahead* router_lookahead = get_cached_router_lookahead(*det_routing_arch, - router_opts.lookahead_type, - router_opts.write_router_lookahead, - router_opts.read_router_lookahead, - segment_inf, - is_flat); - - RouterDelayProfiler route_profiler(net_list, router_lookahead, is_flat); - - int longest_length = get_longest_segment_length(segment_inf); - - /*now setup and compute the actual arrays */ - std::unique_ptr place_delay_model; - float min_cross_layer_delay = get_min_cross_layer_delay(); - - if (placer_opts.delay_model_type == PlaceDelayModelType::SIMPLE) { - place_delay_model = std::make_unique(); - } else if (placer_opts.delay_model_type == PlaceDelayModelType::DELTA) { - place_delay_model = std::make_unique(min_cross_layer_delay, is_flat); - } else if (placer_opts.delay_model_type == PlaceDelayModelType::DELTA_OVERRIDE) { - place_delay_model = std::make_unique(min_cross_layer_delay, is_flat); - } else { - VTR_ASSERT_MSG(false, "Invalid placer delay model"); - } - - if (placer_opts.read_placement_delay_lookup.empty()) { - place_delay_model->compute(route_profiler, placer_opts, router_opts, longest_length); - } else { - place_delay_model->read(placer_opts.read_placement_delay_lookup); - } - - if (!placer_opts.write_placement_delay_lookup.empty()) { - place_delay_model->write(placer_opts.write_placement_delay_lookup); - } - - /*free all data structures that are no longer needed */ - free_routing_structs(); - - return place_delay_model; -} - -void DeltaDelayModel::compute( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - int longest_length) { - delays_ = compute_delta_delay_model( - route_profiler, - placer_opts, router_opts, /*measure_directconnect=*/true, - longest_length, - is_flat_); -} - -void OverrideDelayModel::compute( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - int longest_length) { - auto delays = compute_delta_delay_model( - route_profiler, - placer_opts, router_opts, /*measure_directconnect=*/false, - longest_length, - is_flat_); - - base_delay_model_ = std::make_unique(cross_layer_delay_, delays, false); - - compute_override_delay_model(route_profiler, router_opts); -} - -void SimpleDelayModel::compute( - RouterDelayProfiler& router, - const t_placer_opts& /*placer_opts*/, - const t_router_opts& /*router_opts*/, - int /*longest_length*/) { - delays_ = compute_simple_delay_model(router); -} - -/******* File Accessible Functions **********/ - -std::vector get_best_classes(enum e_pin_type pintype, t_physical_tile_type_ptr type) { - /* - * This function tries to identify the best pin classes to hook up - * for delay calculation. The assumption is that we should pick - * the pin class with the largest number of pins. This makes - * sense, since it ensures we pick commonly used pins, and - * removes order dependence on how the pins are specified - * in the architecture (except in the case were the two largest pin classes - * of a particular pintype have the same number of pins, in which case the - * first pin class is used). - */ - - std::vector best_classes; - - //Record any non-zero Fc pins - // - //Note that we track non-zero Fc pins, since certain Fc overides - //may apply to only a subset of wire types. This ensures we record - //which pins can potentially connect to global routing. - std::unordered_set non_zero_fc_pins; - for (const t_fc_specification& fc_spec : type->fc_specs) { - if (fc_spec.fc_value == 0) continue; - - non_zero_fc_pins.insert(fc_spec.pins.begin(), fc_spec.pins.end()); - } - - //Collect all classes of matching type which connect to general routing - for (int i = 0; i < (int)type->class_inf.size(); i++) { - if (type->class_inf[i].type == pintype) { - //Check whether all pins in this class are ignored or have zero fc - bool any_pins_connect_to_general_routing = false; - for (int ipin = 0; ipin < type->class_inf[i].num_pins; ++ipin) { - int pin = type->class_inf[i].pinlist[ipin]; - //If the pin isn't ignored, and has a non-zero Fc to some general - //routing the class is suitable for delay profiling - if (!type->is_ignored_pin[pin] && non_zero_fc_pins.count(pin)) { - any_pins_connect_to_general_routing = true; - break; - } - } - - if (!any_pins_connect_to_general_routing) continue; //Skip if doesn't connect to general routing - - //Record candidate class - best_classes.push_back(i); - } - } - - //Sort classe so largest pin class is first - auto cmp_class = [&](int lhs, int rhs) { - return type->class_inf[lhs].num_pins > type->class_inf[rhs].num_pins; - }; - - std::stable_sort(best_classes.begin(), best_classes.end(), cmp_class); - - return best_classes; -} - -static int get_longest_segment_length(std::vector& segment_inf) { - int length = 0; - - for (const t_segment_inf &seg_info : segment_inf) { - if (seg_info.length > length) { - length = seg_info.length; - } - } - - return length; -} - -static t_chan_width setup_chan_width(const t_router_opts& router_opts, - t_chan_width_dist chan_width_dist) { - /*we give plenty of tracks, this increases routability for the */ - /*lookup table generation */ - - t_graph_type graph_directionality; - int width_fac; - - if (router_opts.fixed_channel_width == NO_FIXED_CHANNEL_WIDTH) { - auto& device_ctx = g_vpr_ctx.device(); - - auto type = find_most_common_tile_type(device_ctx.grid); - - width_fac = 4 * type->num_pins; - /*this is 2x the value that binary search starts */ - /*this should be enough to allow most pins to */ - /*connect to tracks in the architecture */ - } else { - width_fac = router_opts.fixed_channel_width; - } - - if (router_opts.route_type == GLOBAL) { - graph_directionality = GRAPH_BIDIR; - } else { - graph_directionality = GRAPH_UNIDIR; - } - - return init_chan(width_fac, chan_width_dist, graph_directionality); -} - -static float route_connection_delay( - RouterDelayProfiler& route_profiler, - int from_layer_num, - int to_layer_num, - int source_x, - int source_y, - int sink_x, - int sink_y, - const t_router_opts& router_opts, - bool measure_directconnect) { - //Routes between the source and sink locations and calculates the delay - - float net_delay_value = IMPOSSIBLE_DELTA; /*set to known value for debug purposes */ - - auto& device_ctx = g_vpr_ctx.device(); - - bool successfully_routed = false; - - //Get the rr nodes to route between - auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num})); - auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num})); - - for (int driver_ptc : best_driver_ptcs) { - VTR_ASSERT(driver_ptc != OPEN); - RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(from_layer_num, source_x, source_y, SOURCE, driver_ptc); - - VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); - - for (int sink_ptc : best_sink_ptcs) { - VTR_ASSERT(sink_ptc != OPEN); - RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(to_layer_num, sink_x, sink_y, SINK, sink_ptc); - - if (sink_rr_node == RRNodeId::INVALID()) - continue; - - if (!measure_directconnect && directconnect_exists(source_rr_node, sink_rr_node)) { - //Skip if we shouldn't measure direct connects and a direct connect exists - continue; - } - - { - successfully_routed = route_profiler.calculate_delay( - source_rr_node, sink_rr_node, - router_opts, - &net_delay_value); - } - - if (successfully_routed) break; - } - if (successfully_routed) break; - } - - if (!successfully_routed) { - VTR_LOG_WARN("Unable to route between blocks at (%d,%d,%d) and (%d,%d,%d) to characterize delay (setting to %g)\n", - source_x, source_y, from_layer_num, sink_x, sink_y, to_layer_num, net_delay_value); - } - - return (net_delay_value); -} - -static void add_delay_to_matrix( - vtr::Matrix>* matrix, - int delta_x, - int delta_y, - float delay) { - if ((*matrix)[delta_x][delta_y].size() == 1 && (*matrix)[delta_x][delta_y][0] == EMPTY_DELTA) { - //Overwrite empty delta - (*matrix)[delta_x][delta_y][0] = delay; - } else { - //Collect delta - (*matrix)[delta_x][delta_y].push_back(delay); - } -} - -static void generic_compute_matrix_dijkstra_expansion( - RouterDelayProfiler& /*route_profiler*/, - vtr::Matrix>& matrix, - int from_layer_num, - int to_layer_num, - int source_x, - int source_y, - int start_x, - int start_y, - int end_x, - int end_y, - const t_router_opts& router_opts, - bool measure_directconnect, - const std::set& allowed_types, - bool is_flat) { - auto& device_ctx = g_vpr_ctx.device(); - - t_physical_tile_type_ptr src_type = device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num}); - bool is_allowed_type = allowed_types.empty() || allowed_types.find(src_type->name) != allowed_types.end(); - if (src_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE || !is_allowed_type) { - for (int sink_x = start_x; sink_x <= end_x; sink_x++) { - for (int sink_y = start_y; sink_y <= end_y; sink_y++) { - int delta_x = abs(sink_x - source_x); - int delta_y = abs(sink_y - source_y); - - if (matrix[delta_x][delta_y].empty()) { - //Only set empty target if we don't already have a valid delta delay - matrix[delta_x][delta_y].push_back(EMPTY_DELTA); -#ifdef VERBOSE - VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", - "EMPTY", - delta_x, delta_y, - source_x, source_y, - sink_x, sink_y); -#endif - } - } - } - - return; - } - - vtr::Matrix found_matrix({matrix.dim_size(0), matrix.dim_size(1)}, false); - - auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num})); - for (int driver_ptc : best_driver_ptcs) { - VTR_ASSERT(driver_ptc != OPEN); - RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(from_layer_num, source_x, source_y, SOURCE, driver_ptc); - - VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); - auto delays = calculate_all_path_delays_from_rr_node(source_rr_node, router_opts, is_flat); - - bool path_to_all_sinks = true; - for (int sink_x = start_x; sink_x <= end_x; sink_x++) { - for (int sink_y = start_y; sink_y <= end_y; sink_y++) { - int delta_x = abs(sink_x - source_x); - int delta_y = abs(sink_y - source_y); - - if (found_matrix[delta_x][delta_y]) { - continue; - } - - t_physical_tile_type_ptr sink_type = device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num}); - if (sink_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { - if (matrix[delta_x][delta_y].empty()) { - //Only set empty target if we don't already have a valid delta delay - matrix[delta_x][delta_y].push_back(EMPTY_DELTA); -#ifdef VERBOSE - VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", - "EMPTY", - delta_x, delta_y, - source_x, source_y, - sink_x, sink_y); -#endif - found_matrix[delta_x][delta_y] = true; - } - } else { - bool found_a_sink = false; - auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num})); - for (int sink_ptc : best_sink_ptcs) { - VTR_ASSERT(sink_ptc != OPEN); - RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(to_layer_num, sink_x, sink_y, SINK, sink_ptc); - - if (sink_rr_node == RRNodeId::INVALID()) - continue; - - if (!measure_directconnect && directconnect_exists(source_rr_node, sink_rr_node)) { - //Skip if we shouldn't measure direct connects and a direct connect exists - continue; - } - - if (std::isnan(delays[sink_rr_node])) { - // This sink was not found - continue; - } - -#ifdef VERBOSE - VTR_LOG("Computed delay: %12g delta: %d,%d (src: %d,%d sink: %d,%d)\n", - delays[size_t(sink_rr_node)], - delta_x, delta_y, - source_x, source_y, - sink_x, sink_y); -#endif - found_matrix[delta_x][delta_y] = true; - - add_delay_to_matrix(&matrix, delta_x, delta_y, delays[sink_rr_node]); - - found_a_sink = true; - break; - } - - if (!found_a_sink) { - path_to_all_sinks = false; - } - } - } - } - - if (path_to_all_sinks) { - break; - } - } - - for (int sink_x = start_x; sink_x <= end_x; sink_x++) { - for (int sink_y = start_y; sink_y <= end_y; sink_y++) { - int delta_x = abs(sink_x - source_x); - int delta_y = abs(sink_y - source_y); - if (!found_matrix[delta_x][delta_y]) { - add_delay_to_matrix(&matrix, delta_x, delta_y, IMPOSSIBLE_DELTA); - VTR_LOG_WARN("Unable to route between blocks at (%d,%d,%d) and (%d,%d,%d) to characterize delay (setting to %g)\n", - source_x, - source_y, - from_layer_num, - sink_x, - sink_y, - to_layer_num, - IMPOSSIBLE_DELTA); - } - } - } -} - -static void generic_compute_matrix_iterative_astar( - RouterDelayProfiler& route_profiler, - vtr::Matrix>& matrix, - int from_layer_num, - int to_layer_num, - int source_x, - int source_y, - int start_x, - int start_y, - int end_x, - int end_y, - const t_router_opts& router_opts, - bool measure_directconnect, - const std::set& allowed_types, - bool /***/) { - //vtr::ScopedStartFinishTimer t(vtr::string_fmt("Profiling from (%d,%d)", source_x, source_y)); - - int delta_x, delta_y; - int sink_x, sink_y; - - auto& device_ctx = g_vpr_ctx.device(); - - for (sink_x = start_x; sink_x <= end_x; sink_x++) { - for (sink_y = start_y; sink_y <= end_y; sink_y++) { - delta_x = abs(sink_x - source_x); - delta_y = abs(sink_y - source_y); - - t_physical_tile_type_ptr src_type = device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num}); - t_physical_tile_type_ptr sink_type = device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num}); - - bool src_or_target_empty = (src_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE - || sink_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE); - - bool is_allowed_type = allowed_types.empty() || allowed_types.find(src_type->name) != allowed_types.end(); - - if (src_or_target_empty || !is_allowed_type) { - if (matrix[delta_x][delta_y].empty()) { - //Only set empty target if we don't already have a valid delta delay - matrix[delta_x][delta_y].push_back(EMPTY_DELTA); -#ifdef VERBOSE - VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", - "EMPTY", - delta_x, delta_y, - source_x, source_y, - sink_x, sink_y); -#endif - } - } else { - //Valid start/end - - float delay = route_connection_delay(route_profiler, - from_layer_num, - to_layer_num, - source_x, - source_y, - sink_x, - sink_y, - router_opts, - measure_directconnect); - -#ifdef VERBOSE - VTR_LOG("Computed delay: %12g delta: %d,%d (src: %d,%d sink: %d,%d)\n", - delay, - delta_x, delta_y, - source_x, source_y, - sink_x, sink_y); -#endif - if (matrix[delta_x][delta_y].size() == 1 && matrix[delta_x][delta_y][0] == EMPTY_DELTA) { - //Overwrite empty delta - matrix[delta_x][delta_y][0] = delay; - } else { - //Collect delta - matrix[delta_x][delta_y].push_back(delay); - } - } - } - } -} - -static vtr::NdMatrix compute_delta_delays( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - bool measure_directconnect, - size_t longest_length, - bool is_flat) { - //To avoid edge effects we place the source at least 'longest_length' away - //from the device edge - //and route from there for all possible delta values < dimension - - auto& device_ctx = g_vpr_ctx.device(); - auto& grid = device_ctx.grid; - - vtr::NdMatrix delta_delays({static_cast(grid.get_num_layers()), static_cast(grid.get_num_layers()), grid.width(), grid.height()}); - - for (int from_layer_num = 0; from_layer_num < grid.get_num_layers(); from_layer_num++) { - for (int to_layer_num = 0; to_layer_num < grid.get_num_layers(); to_layer_num++) { - vtr::NdMatrix, 2> sampled_delta_delays({grid.width(), grid.height()}); - - size_t mid_x = vtr::nint(grid.width() / 2); - size_t mid_y = vtr::nint(grid.height() / 2); - - size_t low_x = std::min(longest_length, mid_x); - size_t low_y = std::min(longest_length, mid_y); - size_t high_x = mid_x; - size_t high_y = mid_y; - if (longest_length <= grid.width()) { - high_x = std::max(grid.width() - longest_length, mid_x); - } - if (longest_length <= grid.height()) { - high_y = std::max(grid.height() - longest_length, mid_y); - } - - std::set allowed_types; - if (!placer_opts.allowed_tiles_for_delay_model.empty()) { - auto allowed_types_vector = vtr::split(placer_opts.allowed_tiles_for_delay_model, ","); - for (const auto& type : allowed_types_vector) { - allowed_types.insert(type); - } - } - - // +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - // + | | + - // + A | B | C + - // + | | + - // +-----------------\-----------------------.---------------+ - // + | | + - // + | | + - // + | | + - // + | | + - // + D | E | F + - // + | | + - // + | | + - // + | | + - // + | | + - // +-----------------*-----------------------/---------------+ - // + | | + - // + G | H | I + - // + | | + - // +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - // - // * = (low_x, low_y) - // . = (high_x, high_y) - // / = (high_x, low_y) - // \ = (low_x, high_y) - // + = device edge - - //Find the lowest y location on the left edge with a non-empty block - int y = 0; - int x = 0; - t_physical_tile_type_ptr src_type = nullptr; - for (x = 0; x < (int)grid.width(); ++x) { - for (y = 0; y < (int)grid.height(); ++y) { - auto type = grid.get_physical_type({x, y, from_layer_num}); - - if (type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { - if (!allowed_types.empty() && allowed_types.find(type->name) == allowed_types.end()) { - continue; - } - src_type = type; - break; - } - } - if (src_type) { - break; - } - } - VTR_ASSERT(src_type != nullptr); - - t_compute_delta_delay_matrix generic_compute_matrix; - switch (placer_opts.place_delta_delay_matrix_calculation_method) { - case e_place_delta_delay_algorithm::ASTAR_ROUTE: - generic_compute_matrix = generic_compute_matrix_iterative_astar; - break; - case e_place_delta_delay_algorithm::DIJKSTRA_EXPANSION: - generic_compute_matrix = generic_compute_matrix_dijkstra_expansion; - break; - default: - VPR_FATAL_ERROR(VPR_ERROR_PLACE, "Unknown place_delta_delay_matrix_calculation_method %d", placer_opts.place_delta_delay_matrix_calculation_method); - } - -#ifdef VERBOSE - VTR_LOG("Computing from lower left edge (%d,%d):\n", x, y); -#endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - from_layer_num, to_layer_num, - x, y, - x, y, - grid.width() - 1, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types, - is_flat); - - //Find the lowest x location on the bottom edge with a non-empty block - src_type = nullptr; - for (y = 0; y < (int)grid.height(); ++y) { - for (x = 0; x < (int)grid.width(); ++x) { - auto type = grid.get_physical_type({x, y, from_layer_num}); - - if (type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { - if (!allowed_types.empty() && allowed_types.find(type->name) == allowed_types.end()) { - continue; - } - src_type = type; - break; - } - } - if (src_type) { - break; - } - } - VTR_ASSERT(src_type != nullptr); -#ifdef VERBOSE - VTR_LOG("Computing from left bottom edge (%d,%d):\n", x, y); -#endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - from_layer_num, to_layer_num, - x, y, - x, y, - grid.width() - 1, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types, - is_flat); - - //Since the other delta delay values may have suffered from edge effects, - //we recalculate deltas within regions B, C, E, F -#ifdef VERBOSE - VTR_LOG("Computing from low/low:\n"); -#endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - from_layer_num, to_layer_num, - low_x, low_y, - low_x, low_y, - grid.width() - 1, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types, - is_flat); - - //Since the other delta delay values may have suffered from edge effects, - //we recalculate deltas within regions D, E, G, H -#ifdef VERBOSE - VTR_LOG("Computing from high/high:\n"); -#endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - from_layer_num, to_layer_num, - high_x, high_y, - 0, 0, - high_x, high_y, - router_opts, - measure_directconnect, allowed_types, - is_flat); - - //Since the other delta delay values may have suffered from edge effects, - //we recalculate deltas within regions A, B, D, E -#ifdef VERBOSE - VTR_LOG("Computing from high/low:\n"); -#endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - from_layer_num, to_layer_num, - high_x, low_y, - 0, low_y, - high_x, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types, - is_flat); - - //Since the other delta delay values may have suffered from edge effects, - //we recalculate deltas within regions E, F, H, I -#ifdef VERBOSE - VTR_LOG("Computing from low/high:\n"); -#endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - from_layer_num, to_layer_num, - low_x, high_y, - low_x, 0, - grid.width() - 1, high_y, - router_opts, - measure_directconnect, allowed_types, - is_flat); - for (size_t dx = 0; dx < sampled_delta_delays.dim_size(0); ++dx) { - for (size_t dy = 0; dy < sampled_delta_delays.dim_size(1); ++dy) { - delta_delays[from_layer_num][to_layer_num][dx][dy] = delay_reduce(sampled_delta_delays[dx][dy], placer_opts.delay_model_reducer); - } - } - } - } - - return delta_delays; -} - -float delay_reduce(std::vector& delays, e_reducer reducer) { - if (delays.empty()) { - return IMPOSSIBLE_DELTA; - } else if (delays.size() == 1) { - return delays[0]; - } - - VTR_ASSERT(delays.size() > 1); - - float delay; - - if (reducer == e_reducer::MIN) { - auto itr = std::min_element(delays.begin(), delays.end()); - delay = *itr; - } else if (reducer == e_reducer::MAX) { - auto itr = std::max_element(delays.begin(), delays.end()); - delay = *itr; - } else if (reducer == e_reducer::MEDIAN) { - std::stable_sort(delays.begin(), delays.end()); - delay = vtr::median(delays.begin(), delays.end()); - } else if (reducer == e_reducer::ARITHMEAN) { - delay = vtr::arithmean(delays.begin(), delays.end()); - } else if (reducer == e_reducer::GEOMEAN) { - delay = vtr::geomean(delays.begin(), delays.end()); - } else { - VPR_FATAL_ERROR(VPR_ERROR_PLACE, "Unrecognized delta delay reducer"); - } - - return delay; -} - -/* We return the average placement estimated delay for a routing spanning (x,y). - * We start with an averaging distance of 1 (i.e. from (x-1,y-1) to (x+1,y+1)) - * and look for legal delay values to average; if some are found we return the - * average and if none are found we increase the distance to average over. - * - * If no legal values are found to average over with a range of max_distance, - * we return IMPOSSIBLE_DELTA. - */ -static float find_neighboring_average( - vtr::NdMatrix& matrix, - int from_layer, - t_physical_tile_loc to_tile_loc, - int max_distance) { - float sum = 0; - int counter = 0; - int endx = matrix.end_index(2); - int endy = matrix.end_index(3); - - int x = to_tile_loc.x; - int y = to_tile_loc.y; - int to_layer = to_tile_loc.layer_num; - - for (int distance = 1; distance <= max_distance; ++distance) { - for (int delx = x - distance; delx <= x + distance; delx++) { - for (int dely = y - distance; dely <= y + distance; dely++) { - // Check distance constraint - if (abs(delx - x) + abs(dely - y) > distance) { - continue; - } - - //check out of bounds - if (delx < 0 || dely < 0 || delx >= endx || dely >= endy || (delx == x && dely == y)) { - continue; - } - - if (matrix[from_layer][to_layer][delx][dely] == EMPTY_DELTA || matrix[from_layer][to_layer][delx][dely] == IMPOSSIBLE_DELTA) { - continue; - } - counter++; - sum += matrix[from_layer][to_layer][delx][dely]; - } - } - if (counter != 0) { - return sum / (float)counter; - } - } - - return IMPOSSIBLE_DELTA; -} - -static void fix_empty_coordinates(vtr::NdMatrix& delta_delays) { - // Set any empty delta's to the average of it's neighbours - // - // Empty coordinates may occur if the sampling location happens to not have - // a connection at that location. However a more through sampling likely - // would return a result, so we fill in the empty holes with a small - // neighbour average. - constexpr int kMaxAverageDistance = 2; - for (int from_layer = 0; from_layer < (int)delta_delays.dim_size(0); ++from_layer) { - for (int to_layer = 0; to_layer < (int)delta_delays.dim_size(1); ++to_layer) { - for (int delta_x = 0; delta_x < (int)delta_delays.dim_size(2); ++delta_x) { - for (int delta_y = 0; delta_y < (int)delta_delays.dim_size(3); ++delta_y) { - if (delta_delays[from_layer][to_layer][delta_x][delta_y] == EMPTY_DELTA) { - delta_delays[from_layer][to_layer][delta_x][delta_y] = - find_neighboring_average(delta_delays, - from_layer, - {delta_x, delta_y, to_layer}, - kMaxAverageDistance); - } - } - } - } - } -} - -static void fix_uninitialized_coordinates(vtr::NdMatrix& delta_delays) { - // Set any empty delta's to the average of it's neighbours - - for (size_t from_layer_num = 0; from_layer_num < delta_delays.dim_size(0); ++from_layer_num) { - for (size_t to_layer_num = 0; to_layer_num < delta_delays.dim_size(1); ++to_layer_num) { - for (size_t delta_x = 0; delta_x < delta_delays.dim_size(2); ++delta_x) { - for (size_t delta_y = 0; delta_y < delta_delays.dim_size(3); ++delta_y) { - if (delta_delays[from_layer_num][to_layer_num][delta_x][delta_y] == UNINITIALIZED_DELTA) { - delta_delays[from_layer_num][to_layer_num][delta_x][delta_y] = IMPOSSIBLE_DELTA; - } - } - } - } - } -} - -static void fill_impossible_coordinates(vtr::NdMatrix& delta_delays) { - // Set any impossible delta's to the average of its neighbours - // - // Impossible coordinates may occur if an IPIN cannot be reached from the - // sampling OPIN. This might occur if the IPIN or OPIN used for sampling - // is specialized, and therefore cannot be reached via the by the pins - // sampled. Leaving this value in the delay matrix will result in invalid - // slacks if the delay matrix uses this value. - // - // A max average distance of 5 is used to provide increased effort in - // filling these gaps. It is more important to have a poor predication, - // than an invalid value and causing a slack assertion. - constexpr int kMaxAverageDistance = 5; - for (int from_layer_num = 0; from_layer_num < (int)delta_delays.dim_size(0); ++from_layer_num) { - for (int to_layer_num = 0; to_layer_num < (int)delta_delays.dim_size(1); ++to_layer_num) { - for (int delta_x = 0; delta_x < (int)delta_delays.dim_size(2); ++delta_x) { - for (int delta_y = 0; delta_y < (int)delta_delays.dim_size(3); ++delta_y) { - if (delta_delays[from_layer_num][to_layer_num][delta_x][delta_y] == IMPOSSIBLE_DELTA) { - delta_delays[from_layer_num][to_layer_num][delta_x][delta_y] = find_neighboring_average( - delta_delays, from_layer_num, {delta_x, delta_y, to_layer_num}, kMaxAverageDistance); - } - } - } - } - } -} - -static vtr::NdMatrix compute_delta_delay_model( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - bool measure_directconnect, - int longest_length, - bool is_flat) { - vtr::ScopedStartFinishTimer timer("Computing delta delays"); - vtr::NdMatrix delta_delays = compute_delta_delays(route_profiler, - placer_opts, - router_opts, - measure_directconnect, - longest_length, - is_flat); - - fix_uninitialized_coordinates(delta_delays); - - fix_empty_coordinates(delta_delays); - - fill_impossible_coordinates(delta_delays); - - verify_delta_delays(delta_delays); - - return delta_delays; -} - -static vtr::NdMatrix compute_simple_delay_model(RouterDelayProfiler& route_profiler) { - const auto& grid = g_vpr_ctx.device().grid; - int num_physical_tile_types = static_cast(g_vpr_ctx.device().physical_tile_types.size()); - // Initializing the delay matrix to [num_physical_types][num_layers][num_layers][width][height] - // The second index related to the layer that the source location is on and the third index is for the sink layer - vtr::NdMatrix delta_delays({static_cast(num_physical_tile_types), - static_cast(grid.get_num_layers()), - static_cast(grid.get_num_layers()), - grid.width(), - grid.height()}); - - for (int physical_tile_type_idx = 0; physical_tile_type_idx < num_physical_tile_types; ++physical_tile_type_idx) { - for (int from_layer = 0; from_layer < grid.get_num_layers(); ++from_layer) { - for (int to_layer = 0; to_layer < grid.get_num_layers(); ++to_layer) { - for (int dx = 0; dx < static_cast(grid.width()); ++dx) { - for (int dy = 0; dy < static_cast(grid.height()); ++dy) { - float min_delay = route_profiler.get_min_delay(physical_tile_type_idx, - from_layer, - to_layer, - dx, - dy); - delta_delays[physical_tile_type_idx][from_layer][to_layer][dx][dy] = min_delay; - } - } - } - } - } - - return delta_delays; -} - -//Finds a src_rr and sink_rr appropriate for measuring the delay of the current direct specification -static bool find_direct_connect_sample_locations(const t_direct_inf* direct, - t_physical_tile_type_ptr from_type, - int from_pin, - int from_pin_class, - t_physical_tile_type_ptr to_type, - int to_pin, - int to_pin_class, - RRNodeId& out_src_node, - RRNodeId& out_sink_node) { - VTR_ASSERT(from_type != nullptr); - VTR_ASSERT(to_type != nullptr); - - auto& device_ctx = g_vpr_ctx.device(); - auto& grid = device_ctx.grid; - const auto& node_lookup = device_ctx.rr_graph.node_lookup(); - - //Search the grid for an instance of from/to blocks which satisfy this direct connect offsets, - //and which has the appropriate pins - int from_x = -1; - int from_y = -1; - int from_sub_tile = -1; - int to_x = 0, to_y = 0, to_sub_tile = 0; - bool found = false; - int found_layer_num = -1; - //TODO: Function *FOR NOW* assumes that from/to blocks are at same die and have a same layer nums - for (int layer_num = 0; layer_num < grid.get_num_layers() && !found; ++layer_num) { - for (int x = 0; x < (int)grid.width() && !found; ++x) { - to_x = x + direct->x_offset; - if (to_x < 0 || to_x >= (int)grid.width()) continue; - - for (int y = 0; y < (int)grid.height() && !found; ++y) { - if (grid.get_physical_type({x, y, layer_num}) != from_type) continue; - - //Check that the from pin exists at this from location - //(with multi-width/height blocks pins may not exist at all locations) - bool from_pin_found = false; - if (direct->from_side != NUM_2D_SIDES) { - RRNodeId from_pin_rr = node_lookup.find_node(layer_num, x, y, OPIN, from_pin, direct->from_side); - from_pin_found = from_pin_rr.is_valid(); - } else { - from_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, x, y, OPIN, from_pin).empty()); - } - if (!from_pin_found) continue; - - to_y = y + direct->y_offset; - - if (to_y < 0 || to_y >= (int)grid.height()) continue; - if (grid.get_physical_type({to_x, to_y, layer_num}) != to_type) continue; - - //Check that the from pin exists at this from location - //(with multi-width/height blocks pins may not exist at all locations) - bool to_pin_found = false; - if (direct->to_side != NUM_2D_SIDES) { - RRNodeId to_pin_rr = node_lookup.find_node(layer_num, to_x, to_y, IPIN, to_pin, direct->to_side); - to_pin_found = (to_pin_rr != RRNodeId::INVALID()); - } else { - to_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, to_x, to_y, IPIN, to_pin).empty()); - } - if (!to_pin_found) continue; - - for (int sub_tile_num = 0; sub_tile_num < from_type->capacity; ++sub_tile_num) { - to_sub_tile = sub_tile_num + direct->sub_tile_offset; - - if (to_sub_tile < 0 || to_sub_tile >= to_type->capacity) continue; - - found = true; - found_layer_num = layer_num; - from_x = x; - from_y = y; - from_sub_tile = sub_tile_num; - - break; - } - } - } - } - - if (!found) { - return false; - } - - //Now have a legal instance of this direct connect - VTR_ASSERT(grid.get_physical_type({from_x, from_y, found_layer_num}) == from_type); - VTR_ASSERT(from_sub_tile < from_type->capacity); - - VTR_ASSERT(grid.get_physical_type({to_x, to_y, found_layer_num}) == to_type); - VTR_ASSERT(to_sub_tile < to_type->capacity); - - VTR_ASSERT(from_x + direct->x_offset == to_x); - VTR_ASSERT(from_y + direct->y_offset == to_y); - VTR_ASSERT(from_sub_tile + direct->sub_tile_offset == to_sub_tile); - - // - //Find a source/sink RR node associated with the pins of the direct - // - - { - RRNodeId src_rr_candidate = node_lookup.find_node(found_layer_num, from_x, from_y, SOURCE, from_pin_class); - VTR_ASSERT(src_rr_candidate); - out_src_node = src_rr_candidate; - } - - { - RRNodeId sink_rr_candidate = node_lookup.find_node(found_layer_num, to_x, to_y, SINK, to_pin_class); - VTR_ASSERT(sink_rr_candidate); - out_sink_node = sink_rr_candidate; - } - - return true; -} - -static bool verify_delta_delays(const vtr::NdMatrix& delta_delays) { - auto& device_ctx = g_vpr_ctx.device(); - auto& grid = device_ctx.grid; - - for (int from_layer_num = 0; from_layer_num < grid.get_num_layers(); ++from_layer_num) { - for (int to_layer_num = 0; to_layer_num < grid.get_num_layers(); ++to_layer_num) { - for (size_t x = 0; x < grid.width(); ++x) { - for (size_t y = 0; y < grid.height(); ++y) { - float delta_delay = delta_delays[from_layer_num][to_layer_num][x][y]; - - if (delta_delay < 0.) { - VPR_ERROR(VPR_ERROR_PLACE, - "Found invaild negative delay %g for delta [%d,%d,%d,%d]", - delta_delay, from_layer_num, to_layer_num, x, y); - } - } - } - } - } - - return true; -} - -void OverrideDelayModel::compute_override_delay_model( - RouterDelayProfiler& route_profiler, - const t_router_opts& router_opts) { - t_router_opts router_opts2 = router_opts; - router_opts2.astar_fac = 0.f; - router_opts2.astar_offset = 0.f; - - //Look at all the direct connections that exist, and add overrides to delay model - auto& device_ctx = g_vpr_ctx.device(); - for (int idirect = 0; idirect < (int)device_ctx.arch->directs.size(); ++idirect) { - const t_direct_inf* direct = &device_ctx.arch->directs[idirect]; - - InstPort from_port = parse_inst_port(direct->from_pin); - InstPort to_port = parse_inst_port(direct->to_pin); - - t_physical_tile_type_ptr from_type = find_tile_type_by_name(from_port.instance_name(), device_ctx.physical_tile_types); - t_physical_tile_type_ptr to_type = find_tile_type_by_name(to_port.instance_name(), device_ctx.physical_tile_types); - - int num_conns = from_port.port_high_index() - from_port.port_low_index() + 1; - VTR_ASSERT_MSG(num_conns == to_port.port_high_index() - to_port.port_low_index() + 1, "Directs must have the same size to/from"); - - //We now walk through all the connections associated with the current direct specification, measure - //their delay and specify that value as an override in the delay model. - // - //Note that we need to check every connection in the direct to cover the case where the pins are not - //equivalent. - // - //However, if the from/to ports are equivalent we could end up sampling the same RR SOURCE/SINK - //paths multiple times (wasting CPU time) -- we avoid this by recording the sampled paths in - //sampled_rr_pairs and skipping them if they occur multiple times. - int missing_instances = 0; - int missing_paths = 0; - std::set> sampled_rr_pairs; - for (int iconn = 0; iconn < num_conns; ++iconn) { - //Find the associated pins - int from_pin = find_pin(from_type, from_port.port_name(), from_port.port_low_index() + iconn); - int to_pin = find_pin(to_type, to_port.port_name(), to_port.port_low_index() + iconn); - - VTR_ASSERT(from_pin != OPEN); - VTR_ASSERT(to_pin != OPEN); - - int from_pin_class = find_pin_class(from_type, from_port.port_name(), from_port.port_low_index() + iconn, DRIVER); - VTR_ASSERT(from_pin_class != OPEN); - - int to_pin_class = find_pin_class(to_type, to_port.port_name(), to_port.port_low_index() + iconn, RECEIVER); - VTR_ASSERT(to_pin_class != OPEN); - - bool found_sample_points; - RRNodeId src_rr, sink_rr; - found_sample_points = find_direct_connect_sample_locations(direct, from_type, from_pin, from_pin_class, to_type, to_pin, to_pin_class, src_rr, sink_rr); - - if (!found_sample_points) { - ++missing_instances; - continue; - } - - //If some of the source/sink ports are logically equivalent we may have already - //sampled the associated source/sink pair and don't need to do so again - if (sampled_rr_pairs.count({src_rr, sink_rr})) continue; - - float direct_connect_delay = std::numeric_limits::quiet_NaN(); - bool found_routing_path = route_profiler.calculate_delay(src_rr, sink_rr, router_opts2, &direct_connect_delay); - - if (found_routing_path) { - set_delay_override(from_type->index, from_pin_class, to_type->index, to_pin_class, direct->x_offset, direct->y_offset, direct_connect_delay); - } else { - ++missing_paths; - } - - //Record that we've sampled this pair of source and sink nodes - sampled_rr_pairs.insert({src_rr, sink_rr}); - } - - VTR_LOGV_WARN(missing_instances > 0, "Found no delta delay for %d bits of inter-block direct connect '%s' (no instances of this direct found)\n", missing_instances, direct->name.c_str()); - VTR_LOGV_WARN(missing_paths > 0, "Found no delta delay for %d bits of inter-block direct connect '%s' (no routing path found)\n", missing_paths, direct->name.c_str()); - } -} - -bool directconnect_exists(RRNodeId src_rr_node, RRNodeId sink_rr_node) { - //Returns true if there is a directconnect between the two RR nodes - // - //This is checked by looking for a SOURCE -> OPIN -> IPIN -> SINK path - //which starts at src_rr_node and ends at sink_rr_node - auto& device_ctx = g_vpr_ctx.device(); - const auto& rr_graph = device_ctx.rr_graph; - - VTR_ASSERT(rr_graph.node_type(src_rr_node) == SOURCE && rr_graph.node_type(sink_rr_node) == SINK); - - //TODO: This is a constant depth search, but still may be too slow - for (t_edge_size i_src_edge = 0; i_src_edge < rr_graph.num_edges(src_rr_node); ++i_src_edge) { - RRNodeId opin_rr_node = rr_graph.edge_sink_node(src_rr_node, i_src_edge); - - if (rr_graph.node_type(opin_rr_node) != OPIN) continue; - - for (t_edge_size i_opin_edge = 0; i_opin_edge < rr_graph.num_edges(opin_rr_node); ++i_opin_edge) { - RRNodeId ipin_rr_node = rr_graph.edge_sink_node(opin_rr_node, i_opin_edge); - if (rr_graph.node_type(ipin_rr_node) != IPIN) continue; - - for (t_edge_size i_ipin_edge = 0; i_ipin_edge < rr_graph.num_edges(ipin_rr_node); ++i_ipin_edge) { - if (sink_rr_node == rr_graph.edge_sink_node(ipin_rr_node, i_ipin_edge)) { - return true; - } - } - } - } - return false; -} diff --git a/vpr/src/place/timing_place_lookup.h b/vpr/src/place/timing_place_lookup.h deleted file mode 100644 index fba3f470483..00000000000 --- a/vpr/src/place/timing_place_lookup.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef TIMING_PLACE_LOOKUP_H -#define TIMING_PLACE_LOOKUP_H -#include "place_delay_model.h" - -std::unique_ptr compute_place_delay_model(const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - const Netlist<>& net_list, - t_det_routing_arch* det_routing_arch, - std::vector& segment_inf, - t_chan_width_dist chan_width_dist, - const std::vector& directs, - bool is_flat); - -std::vector get_best_classes(enum e_pin_type pintype, t_physical_tile_type_ptr type); - -bool directconnect_exists(RRNodeId src_rr_node, RRNodeId sink_rr_node); - -#endif diff --git a/vpr/src/place/verify_placement.cpp b/vpr/src/place/verify_placement.cpp index 9e9dd6fbcd8..b40b55e1d6c 100644 --- a/vpr/src/place/verify_placement.cpp +++ b/vpr/src/place/verify_placement.cpp @@ -18,6 +18,7 @@ #include "device_grid.h" #include "partition_region.h" #include "physical_types.h" +#include "physical_types_util.h" #include "place_macro.h" #include "vpr_context.h" #include "vpr_types.h" @@ -63,8 +64,7 @@ static unsigned check_block_placement_consistency(const BlkLocRegistry& blk_loc_ // and that it has no valid clusters placed at this location. // TODO: Eventually it should be made impossible to place blocks // at these locations. - if (device_grid.get_width_offset(tile_loc) != 0 || - device_grid.get_height_offset(tile_loc) != 0) { + if (device_grid.get_width_offset(tile_loc) != 0 || device_grid.get_height_offset(tile_loc) != 0) { // Usage must be 0 if (grid_blocks.get_usage(tile_loc) != 0) { VTR_LOG_ERROR( @@ -171,8 +171,8 @@ static unsigned check_block_placement_consistency(const BlkLocRegistry& blk_loc_ * * @return The number of errors in the macro placement. */ -static unsigned check_macro_placement_consistency(const BlkLocRegistry& blk_loc_registry) { - const PlaceMacros& pl_macros = blk_loc_registry.place_macros(); +static unsigned check_macro_placement_consistency(const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& pl_macros) { const auto& block_locs = blk_loc_registry.block_locs(); const auto& grid_blocks = blk_loc_registry.grid_blocks(); @@ -247,6 +247,7 @@ static unsigned check_placement_floorplanning(const BlkLocRegistry& blk_loc_regi } unsigned verify_placement(const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, const ClusteredNetlist& clb_nlist, const DeviceGrid& device_grid, const vtr::vector& cluster_constraints) { @@ -264,7 +265,7 @@ unsigned verify_placement(const BlkLocRegistry& blk_loc_registry, // FIXME: Should we be checking the macro consistency at all? Does the // router use the pl_macros? If not this should be removed from this // method and only used when the macro placement is actually used. - num_errors += check_macro_placement_consistency(blk_loc_registry); + num_errors += check_macro_placement_consistency(blk_loc_registry, place_macros); // Check that the floorplanning is observed. num_errors += check_placement_floorplanning(blk_loc_registry, @@ -277,8 +278,8 @@ unsigned verify_placement(const BlkLocRegistry& blk_loc_registry, unsigned verify_placement(const VprContext& ctx) { // Verify the placement within the given context. return verify_placement(ctx.placement().blk_loc_registry(), + *ctx.placement().place_macros, ctx.clustering().clb_nlist, ctx.device().grid, ctx.floorplanning().cluster_constraints); } - diff --git a/vpr/src/place/verify_placement.h b/vpr/src/place/verify_placement.h index 1bee823ea5e..2a3236d3b4c 100644 --- a/vpr/src/place/verify_placement.h +++ b/vpr/src/place/verify_placement.h @@ -22,6 +22,7 @@ class ClusterBlockId; class ClusteredNetlist; class DeviceGrid; class PartitionRegion; +class PlaceMacros; class VprContext; /** @@ -52,6 +53,7 @@ class VprContext; * * @param blk_loc_registry A registry containing the current placement of * the clusters. + * @param place_macros The place macros for the clustered netlist. * @param clb_nlist The clustered netlist being verified. * @param device_grid The device grid being verified over. * @param cluster_constraints The constrained regions that each cluster is @@ -61,6 +63,7 @@ class VprContext; * log messages for each error found. */ unsigned verify_placement(const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, const ClusteredNetlist& clb_nlist, const DeviceGrid& device_grid, const vtr::vector& cluster_constraints); @@ -78,4 +81,3 @@ unsigned verify_placement(const BlkLocRegistry& blk_loc_registry, * @param ctx The global VPR context variable found in g_vpr_ctx. */ unsigned verify_placement(const VprContext& ctx); - diff --git a/vpr/src/power/power.cpp b/vpr/src/power/power.cpp index e899935864a..669133f5a01 100644 --- a/vpr/src/power/power.cpp +++ b/vpr/src/power/power.cpp @@ -26,13 +26,12 @@ #include #include #include -#include +#include "physical_types_util.h" #include "vtr_util.h" #include "vtr_path.h" #include "vtr_log.h" #include "vtr_assert.h" -#include "vtr_memory.h" #include "power.h" #include "power_components.h" @@ -44,7 +43,6 @@ #include "physical_types.h" #include "globals.h" -#include "rr_graph.h" #include "vpr_utils.h" /************************* DEFINES **********************************/ @@ -164,9 +162,9 @@ static void power_usage_primitive(t_power_usage* power_usage, t_pb* pb, t_pb_gra } if (pb) { - AtomBlockId blk_id = atom_ctx.lookup.pb_atom(pb); + AtomBlockId blk_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(pb); SRAM_values = alloc_SRAM_values_from_truth_table(LUT_size, - atom_ctx.nlist.block_truth_table(blk_id)); + atom_ctx.netlist().block_truth_table(blk_id)); } else { SRAM_values = alloc_SRAM_values_from_truth_table(LUT_size, AtomNetlist::TruthTable()); } @@ -810,7 +808,7 @@ static void power_usage_routing(t_power_usage* power_usage, /* Populate net indices into rr graph */ for (auto net_id : cluster_ctx.clb_nlist.nets()) { - ParentNetId parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup, net_id, is_flat); + ParentNetId parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup(), net_id, is_flat); if (!route_ctx.route_trees[parent_id]) continue; for (auto& rt_node : route_ctx.route_trees[parent_id].value().all_nodes()) { @@ -821,7 +819,7 @@ static void power_usage_routing(t_power_usage* power_usage, /* Populate net indices into rr graph */ for (auto net_id : cluster_ctx.clb_nlist.nets()) { - ParentNetId parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup, net_id, is_flat); + ParentNetId parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup(), net_id, is_flat); if (!route_ctx.route_trees[parent_id]) continue; for (auto& rt_node : route_ctx.route_trees[parent_id].value().all_nodes()) { @@ -923,7 +921,7 @@ static void power_usage_routing(t_power_usage* power_usage, C_wire = wire_length * rr_graph.rr_segments(RRSegmentId(seg_index)).Cmetal; //(double)power_ctx.commonly_used->tile_length); if (node_fan_in == 0) { - continue; // Bypass some nodes with 0 fan-in + continue; // Bypass some nodes with 0 fan-in } VTR_ASSERT(node_power->selected_input < node_fan_in); @@ -1201,8 +1199,8 @@ void power_routing_init(const t_det_routing_arch* routing_arch) { power_ctx.clb_net_power.resize(cluster_ctx.clb_nlist.nets().size()); } for (auto net_id : cluster_ctx.clb_nlist.nets()) { - power_ctx.clb_net_power[net_id].probability = power_ctx.atom_net_power[atom_ctx.lookup.atom_net(net_id)].probability; - power_ctx.clb_net_power[net_id].density = power_ctx.atom_net_power[atom_ctx.lookup.atom_net(net_id)].density; + power_ctx.clb_net_power[net_id].probability = power_ctx.atom_net_power[atom_ctx.lookup().atom_net(net_id)].probability; + power_ctx.clb_net_power[net_id].density = power_ctx.atom_net_power[atom_ctx.lookup().atom_net(net_id)].density; } /* Initialize RR Graph Structures */ diff --git a/vpr/src/power/power_components.h b/vpr/src/power/power_components.h index dd235450603..3faa7b7b641 100644 --- a/vpr/src/power/power_components.h +++ b/vpr/src/power/power_components.h @@ -38,7 +38,7 @@ */ #define POWER_LUT_SLOW #if (!(defined(POWER_LUT_SLOW) || defined(POWER_LUT_FAST))) -# define POWER_LUT_SLOW +#define POWER_LUT_SLOW #endif /************************* ENUMS ************************************/ diff --git a/vpr/src/route/DecompNetlistRouter.tpp b/vpr/src/route/DecompNetlistRouter.tpp index 47de291a14c..228cf428ef6 100644 --- a/vpr/src/route/DecompNetlistRouter.tpp +++ b/vpr/src/route/DecompNetlistRouter.tpp @@ -26,7 +26,7 @@ inline RouteIterResults DecompNetlistRouter::route_netlist(int itry, f /* Organize netlist into a PartitionTree. * Nets in a given level of nodes are guaranteed to not have any overlapping bounding boxes, so they can be routed in parallel. */ - if(!_tree){ + if (!_tree) { _tree = PartitionTree(_net_list); PartitionTreeDebug::log("Iteration " + std::to_string(itry) + ": built partition tree in " + std::to_string(timer.elapsed_sec()) + " s"); } @@ -449,8 +449,8 @@ inline bool is_close_to_cutline(RRNodeId inode, Axis cutline_axis, int cutline_p const auto& rr_graph = device_ctx.rr_graph; vtr::Rect tile_bb = device_ctx.grid.get_tile_bb({rr_graph.node_xlow(inode), - rr_graph.node_ylow(inode), - rr_graph.node_layer(inode)}); + rr_graph.node_ylow(inode), + rr_graph.node_layer(inode)}); /* Cutlines are considered to be at x + 0.5, set a thickness of +1 here by checking for equality */ if (cutline_axis == Axis::X) { @@ -466,8 +466,8 @@ inline bool is_close_to_bb(RRNodeId inode, const t_bb& bb, int thickness) { const auto& rr_graph = device_ctx.rr_graph; vtr::Rect tile_bb = device_ctx.grid.get_tile_bb({rr_graph.node_xlow(inode), - rr_graph.node_ylow(inode), - rr_graph.node_layer(inode)}); + rr_graph.node_ylow(inode), + rr_graph.node_layer(inode)}); int xlow = tile_bb.xmin() - thickness; int ylow = tile_bb.ymin() - thickness; @@ -686,9 +686,9 @@ vtr::dynamic_bitset<> DecompNetlistRouter::get_decomposition_mask_vnet if (inside_bb(tree.root().inode, vnet.clipped_bb)) { /* We have source, no need to sample after reduction in most cases */ bool is_reduced = get_reduction_mask_vnet_with_source(vnet, node.cutline_axis, node.cutline_pos, out); bool source_on_cutline = is_close_to_cutline(tree.root().inode, node.cutline_axis, node.cutline_pos, 1); - if (!is_reduced || source_on_cutline){ + if (!is_reduced || source_on_cutline) { convex_hull_downsample(vnet.net_id, vnet.clipped_bb, out); - } + } } else { int reduced_sides = get_reduction_mask_vnet_no_source(vnet, node.cutline_axis, node.cutline_pos, out); if (reduced_sides < 2) { diff --git a/vpr/src/route/NestedNetlistRouter.h b/vpr/src/route/NestedNetlistRouter.h new file mode 100644 index 00000000000..6870842af8f --- /dev/null +++ b/vpr/src/route/NestedNetlistRouter.h @@ -0,0 +1,134 @@ +#pragma once + +/** @file Nested parallel case for NetlistRouter */ +#include "netlist_routers.h" +#include "vtr_optional.h" +#include "vtr_thread_pool.h" +#include + +/* Add cmd line option for this later */ +constexpr int MAX_THREADS = 4; + +/** Nested parallel impl for NetlistRouter. + * + * Calls a parallel ConnectionRouter for route_net to extract even more parallelism. + * The main reason why this is a different router instead of templating NetlistRouter + * on ConnectionRouter is this router does not use TBB. The scheduling performance is + * worse, but it can wait in individual tasks now (which is not possible with TBB). + * + * Holds enough context members to glue together ConnectionRouter and net routing functions, + * such as \ref route_net. Keeps the members in thread-local storage where needed, + * i.e. ConnectionRouters and RouteIterResults-es. + * See \ref route_net. */ +template +class NestedNetlistRouter : public NetlistRouter { + public: + NestedNetlistRouter( + const Netlist<>& net_list, + const RouterLookahead* router_lookahead, + const t_router_opts& router_opts, + CBRR& connections_inf, + NetPinsMatrix& net_delay, + const ClusteredPinAtomPinsLookup& netlist_pin_lookup, + std::shared_ptr timing_info, + NetPinTimingInvalidator* pin_timing_invalidator, + route_budgets& budgeting_inf, + const RoutingPredictor& routing_predictor, + const vtr::vector>>& choking_spots, + bool is_flat) + : _net_list(net_list) + , _router_lookahead(router_lookahead) + , _router_opts(router_opts) + , _connections_inf(connections_inf) + , _net_delay(net_delay) + , _netlist_pin_lookup(netlist_pin_lookup) + , _timing_info(timing_info) + , _pin_timing_invalidator(pin_timing_invalidator) + , _budgeting_inf(budgeting_inf) + , _routing_predictor(routing_predictor) + , _choking_spots(choking_spots) + , _is_flat(is_flat) + , _thread_pool(MAX_THREADS) {} + ~NestedNetlistRouter() {} + + /** Run a single iteration of netlist routing for this->_net_list. This usually means calling + * \ref route_net for each net, which will handle other global updates. + * \return RouteIterResults for this iteration. */ + RouteIterResults route_netlist(int itry, float pres_fac, float worst_neg_slack); + /** Inform the PartitionTree of the nets with updated bounding boxes */ + void handle_bb_updated_nets(const std::vector& nets); + + /** Set rcv_enabled for each ConnectionRouter this is managing */ + void set_rcv_enabled(bool x); + /** Set timing_info for each ConnectionRouter this is managing */ + void set_timing_info(std::shared_ptr timing_info); + + private: + /** Route all nets in a PartitionTree node and add its children to the task queue. */ + void route_partition_tree_node(PartitionTreeNode& node); + + ConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { + auto& device_ctx = g_vpr_ctx.device(); + auto& route_ctx = g_vpr_ctx.mutable_routing(); + + return ConnectionRouter( + device_ctx.grid, + *router_lookahead, + device_ctx.rr_graph.rr_nodes(), + &device_ctx.rr_graph, + device_ctx.rr_rc_data, + device_ctx.rr_graph.rr_switch(), + route_ctx.rr_node_route_inf, + is_flat); + } + + /* Context fields. Most of them will be forwarded to route_net (see route_net.tpp) */ + const Netlist<>& _net_list; + const RouterLookahead* _router_lookahead; + const t_router_opts& _router_opts; + CBRR& _connections_inf; + NetPinsMatrix& _net_delay; + const ClusteredPinAtomPinsLookup& _netlist_pin_lookup; + std::shared_ptr _timing_info; + NetPinTimingInvalidator* _pin_timing_invalidator; + route_budgets& _budgeting_inf; + const RoutingPredictor& _routing_predictor; + const vtr::vector>>& _choking_spots; + bool _is_flat; + + /** Cached routing parameters for current iteration (inputs to \see route_netlist()) */ + int _itry; + float _pres_fac; + float _worst_neg_slack; + + /** The partition tree. Holds the groups of nets for each partition */ + vtr::optional _tree; + + /** Thread pool for parallel routing. See vtr_thread_pool.h for implementation */ + vtr::thread_pool _thread_pool; + + /* Thread-local storage. + * These are maps because thread::id is a random integer instead of 1, 2, ... */ + std::unordered_map> _routers_th; + std::unordered_map _results_th; + std::mutex _storage_mutex; + + /** Get a thread-local ConnectionRouter. We lock the id->router lookup, but this is + * accessed once per partition so the overhead should be small */ + ConnectionRouter& get_thread_router() { + auto id = std::this_thread::get_id(); + std::lock_guard lock(_storage_mutex); + if (!_routers_th.count(id)) { + _routers_th.emplace(id, _make_router(_router_lookahead, _is_flat)); + } + return _routers_th.at(id); + } + + RouteIterResults& get_thread_results() { + auto id = std::this_thread::get_id(); + std::lock_guard lock(_storage_mutex); + return _results_th[id]; + } +}; + +#include "NestedNetlistRouter.tpp" diff --git a/vpr/src/route/NestedNetlistRouter.tpp b/vpr/src/route/NestedNetlistRouter.tpp new file mode 100644 index 00000000000..333be28ea3b --- /dev/null +++ b/vpr/src/route/NestedNetlistRouter.tpp @@ -0,0 +1,141 @@ +#pragma once + +/** @file Impls for ParallelNetlistRouter */ + +#include +#include "netlist_routers.h" +#include "route_net.h" +#include "vtr_time.h" + +template +inline RouteIterResults NestedNetlistRouter::route_netlist(int itry, float pres_fac, float worst_neg_slack) { + /* Reset results for each thread */ + for (auto& [_, results] : _results_th) { + results = RouteIterResults(); + } + + /* Set the routing parameters: they won't change until the next call and that saves us the trouble of passing them around */ + _itry = itry; + _pres_fac = pres_fac; + _worst_neg_slack = worst_neg_slack; + + /* Organize netlist into a PartitionTree. + * Nets in a given level of nodes are guaranteed to not have any overlapping bounding boxes, so they can be routed in parallel. */ + vtr::Timer timer; + if (!_tree) { + _tree = PartitionTree(_net_list); + PartitionTreeDebug::log("Iteration " + std::to_string(itry) + ": built partition tree in " + std::to_string(timer.elapsed_sec()) + " s"); + } + + /* Push a single route_partition_tree_node task to the thread pool, + * which will recursively schedule the rest of the tree */ + _thread_pool.schedule_work([this]() { + route_partition_tree_node(_tree->root()); + }); + + /* Wait for all tasks in the thread pool to complete */ + _thread_pool.wait_for_all(); + + PartitionTreeDebug::log("Routing all nets took " + std::to_string(timer.elapsed_sec()) + " s"); + + /* Combine results from threads */ + RouteIterResults out; + for (auto& [_, results] : _results_th) { + out.stats.combine(results.stats); + out.rerouted_nets.insert(out.rerouted_nets.end(), results.rerouted_nets.begin(), results.rerouted_nets.end()); + out.bb_updated_nets.insert(out.bb_updated_nets.end(), results.bb_updated_nets.begin(), results.bb_updated_nets.end()); + out.is_routable &= results.is_routable; + } + return out; +} + +template +void NestedNetlistRouter::route_partition_tree_node(PartitionTreeNode& node) { + auto& route_ctx = g_vpr_ctx.mutable_routing(); + + /* node.nets is an unordered set, copy into vector to sort */ + std::vector nets(node.nets.begin(), node.nets.end()); + + /* Sort so net with most sinks is routed first. */ + std::stable_sort(nets.begin(), nets.end(), [&](ParentNetId id1, ParentNetId id2) -> bool { + return _net_list.net_sinks(id1).size() > _net_list.net_sinks(id2).size(); + }); + + vtr::Timer timer; + + /* Route all nets in this node serially */ + for (auto net_id : nets) { + auto& results = get_thread_results(); + auto& router = get_thread_router(); + + auto flags = route_net( + router, + _net_list, + net_id, + _itry, + _pres_fac, + _router_opts, + _connections_inf, + results.stats, + _net_delay, + _netlist_pin_lookup, + _timing_info.get(), + _pin_timing_invalidator, + _budgeting_inf, + _worst_neg_slack, + _routing_predictor, + _choking_spots[net_id], + _is_flat, + route_ctx.route_bb[net_id]); + + if (!flags.success && !flags.retry_with_full_bb) { + /* Disconnected RRG and ConnectionRouter doesn't think growing the BB will work */ + results.is_routable = false; + return; + } + if (flags.retry_with_full_bb) { + /* ConnectionRouter thinks we should grow the BB. Do that and leave this net unrouted for now */ + route_ctx.route_bb[net_id] = full_device_bb(); + results.bb_updated_nets.push_back(net_id); + continue; + } + if (flags.was_rerouted) { + results.rerouted_nets.push_back(net_id); + } + } + + PartitionTreeDebug::log("Node with " + std::to_string(node.nets.size()) + + " nets and " + std::to_string(node.vnets.size()) + + " virtual nets routed in " + std::to_string(timer.elapsed_sec()) + + " s"); + + /* Schedule child nodes as new tasks */ + if (node.left && node.right) { + _thread_pool.schedule_work([this, left = node.left.get()]() { + route_partition_tree_node(*left); + }); + _thread_pool.schedule_work([this, right = node.right.get()]() { + route_partition_tree_node(*right); + }); + } else { + VTR_ASSERT(!node.left && !node.right); // there shouldn't be a node with a single branch + } +} + +template +void NestedNetlistRouter::handle_bb_updated_nets(const std::vector& nets) { + VTR_ASSERT(_tree); + _tree->update_nets(nets); +} + +template +void NestedNetlistRouter::set_rcv_enabled(bool x) { + for (auto& [_, router] : _routers_th) { + router.set_rcv_enabled(x); + } +} + +template +void NestedNetlistRouter::set_timing_info(std::shared_ptr timing_info) { + _timing_info = timing_info; +} diff --git a/vpr/src/route/ParallelNetlistRouter.tpp b/vpr/src/route/ParallelNetlistRouter.tpp index 1268ed6030e..c845be8518d 100644 --- a/vpr/src/route/ParallelNetlistRouter.tpp +++ b/vpr/src/route/ParallelNetlistRouter.tpp @@ -22,7 +22,7 @@ inline RouteIterResults ParallelNetlistRouter::route_netlist(int itry, /* Organize netlist into a PartitionTree. * Nets in a given level of nodes are guaranteed to not have any overlapping bounding boxes, so they can be routed in parallel. */ vtr::Timer timer; - if(!_tree){ + if (!_tree) { _tree = PartitionTree(_net_list); PartitionTreeDebug::log("Iteration " + std::to_string(itry) + ": built partition tree in " + std::to_string(timer.elapsed_sec()) + " s"); } diff --git a/vpr/src/route/annotate_routing.cpp b/vpr/src/route/annotate_routing.cpp index 42b798d4d02..6f20d2e873d 100644 --- a/vpr/src/route/annotate_routing.cpp +++ b/vpr/src/route/annotate_routing.cpp @@ -14,8 +14,8 @@ #include "annotate_routing.h" vtr::vector annotate_rr_node_nets(const ClusteringContext& cluster_ctx, - const DeviceContext& device_ctx, - const bool& verbose) { + const DeviceContext& device_ctx, + const bool& verbose) { size_t counter = 0; vtr::ScopedStartFinishTimer timer("Annotating rr_node with routed nets"); @@ -35,7 +35,7 @@ vtr::vector annotate_rr_node_nets(const ClusteringContex } auto& tree = get_route_tree_from_cluster_net_id(net_id); - if(!tree) + if (!tree) continue; for (auto& rt_node : tree->all_nodes()) { diff --git a/vpr/src/route/annotate_routing.h b/vpr/src/route/annotate_routing.h index cf548e1e0fe..d12bf313a74 100644 --- a/vpr/src/route/annotate_routing.h +++ b/vpr/src/route/annotate_routing.h @@ -11,7 +11,7 @@ * - Unmapped rr_node will use invalid ids *******************************************************************/ vtr::vector annotate_rr_node_nets(const ClusteringContext& cluster_ctx, - const DeviceContext& device_ctx, - const bool& verbose); + const DeviceContext& device_ctx, + const bool& verbose); #endif diff --git a/vpr/src/route/build_switchblocks.cpp b/vpr/src/route/build_switchblocks.cpp index c203aa001f7..a0dbe35bb1c 100644 --- a/vpr/src/route/build_switchblocks.cpp +++ b/vpr/src/route/build_switchblocks.cpp @@ -141,6 +141,7 @@ #include "physical_types.h" #include "parse_switchblocks.h" #include "vtr_expr_eval.h" +#include "rr_types.h" using vtr::FormulaParser; using vtr::t_formula_data; @@ -431,8 +432,8 @@ t_sb_connection_map* alloc_and_load_switchblock_permutations(const t_chan_detail /******** slow switch block computation method; computes switchblocks at each coordinate ********/ /* iterate over all the switchblocks specified in the architecture */ - for (auto sb: switchblocks) { - + for (auto sb : switchblocks) { + /* verify that switchblock type matches specified directionality -- currently we have to stay consistent */ if (directionality != sb.directionality) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "alloc_and_load_switchblock_connections: Switchblock %s does not match directionality of architecture\n", sb.name.c_str()); @@ -505,10 +506,10 @@ static bool sb_not_here(const DeviceGrid& grid, const std::vector& inter_c } break; case e_sb_location::E_XY_SPECIFIED: - if(match_sb_xy(grid, inter_cluster_rr, x, y, layer, sb)) { + if (match_sb_xy(grid, inter_cluster_rr, x, y, layer, sb)) { sb_not_here = false; } - + break; default: VPR_FATAL_ERROR(VPR_ERROR_ARCH, "sb_not_here: unrecognized location enum: %d\n", sb.location); @@ -564,18 +565,18 @@ static bool match_sb_xy(const DeviceGrid& grid, const std::vector& inter_c if (!is_prog_routing_avail(grid, inter_cluster_rr, layer)) { return false; } - //if one of sb_x and sb_y is defined, we either know the exact location (x,y) or the exact x location (will apply it to all rows) - //or the exact y location (will apply it to all columns) - if(sb.x != -1 || sb.y != -1){ - if(x == sb.x && y == sb.y){ + //if one of sb_x and sb_y is defined, we either know the exact location (x,y) or the exact x location (will apply it to all rows) + //or the exact y location (will apply it to all columns) + if (sb.x != -1 || sb.y != -1) { + if (x == sb.x && y == sb.y) { return true; - } + } - if(x == sb.x && sb.y == -1){ + if (x == sb.x && sb.y == -1) { return true; } - - if(sb.x == -1 && y == sb.y){ + + if (sb.x == -1 && y == sb.y) { return true; } } @@ -585,12 +586,12 @@ static bool match_sb_xy(const DeviceGrid& grid, const std::vector& inter_c //calculate the appropriate region based on the repeatx/repeaty and current location. //This is to determine whether the given location is part of the current SB specified region with regular expression or not //After region calculation, the current SB will apply to this location if: - // 1) the given (x,y) location falls into the calculated region + // 1) the given (x,y) location falls into the calculated region // *AND* // 2) incrx/incry are respected within the region, this means all locations within the calculated region do - // not necessarily crosspond to the current SB. If incrx/incry is equal to 1, then all locations within the - // calculated region are valid. - + // not necessarily crosspond to the current SB. If incrx/incry is equal to 1, then all locations within the + // calculated region are valid. + //calculate the region int x_reg_step = (sb.reg_x.repeat != 0) ? (x - sb.reg_x.start) / sb.reg_x.repeat : sb.reg_x.start; int y_reg_step = (sb.reg_y.repeat != 0) ? (y - sb.reg_y.start) / sb.reg_y.repeat : sb.reg_y.start; @@ -608,23 +609,23 @@ static bool match_sb_xy(const DeviceGrid& grid, const std::vector& inter_c reg_endy = std::min(reg_endy, int(grid.height() - 1)); //check x coordinate - if (x >= reg_startx && x <= reg_endx){ //should fall into the region + if (x >= reg_startx && x <= reg_endx) { //should fall into the region //we also should respect the incrx //if incrx is not equal to 1, all locations within this region are *NOT* valid - if((x + reg_startx) % sb.reg_x.incr == 0){ + if ((x + reg_startx) % sb.reg_x.incr == 0) { //valid x coordinate, check for y value - if(y >= reg_starty && y <= reg_endy){ + if (y >= reg_starty && y <= reg_endy) { //check for incry, similar as incrx - if((y + reg_starty) % sb.reg_y.incr == 0){ + if ((y + reg_starty) % sb.reg_y.incr == 0) { //both x and y are valid return true; } } - } + } } //if reach here, we don't have sb in this location - return false; + return false; } /* Counts the number of wires in each wire type in the specified channel */ @@ -991,7 +992,7 @@ static void compute_wireconn_connections( } else { VTR_ASSERT(from_layer != to_layer); sb_edge.switch_ind = to_chan_details[to_x][to_y][to_wire].arch_wire_switch(); - sb_edge.switch_ind_between_layers = to_chan_details[to_x][to_y][to_wire].arch_opin_between_dice_switch(); + sb_edge.switch_ind_between_layers = to_chan_details[to_x][to_y][to_wire].arch_inter_die_switch(); } VTR_LOGV(verbose, " make_conn: %d -> %d switch=%d\n", sb_edge.from_wire, sb_edge.to_wire, sb_edge.switch_ind); diff --git a/vpr/src/route/build_switchblocks.h b/vpr/src/route/build_switchblocks.h index d9f283dfd4f..917bd16620b 100644 --- a/vpr/src/route/build_switchblocks.h +++ b/vpr/src/route/build_switchblocks.h @@ -7,8 +7,8 @@ #include "physical_types.h" #include "vpr_types.h" #include "device_grid.h" - #include "vtr_random.h" +#include "rr_types.h" /************ Classes, structs, typedefs ************/ @@ -92,9 +92,9 @@ struct t_switchblock_edge { short to_wire_layer; }; -/* Switchblock connections are made as [x][y][from_side][to_side][from_wire_ind]. +/* Switchblock connections are made as [x][y][from_layer][from_side][to_side][from_wire_idx]. * The Switchblock_Lookup class specifies these dimensions. - * Furthermore, a source_wire at a given 5-d coordinate may connect to multiple destination wires so the value + * Furthermore, a source_wire at a given 6-d coordinate may connect to multiple destination wires so the value * of the map is a vector of destination wires. * A matrix specifying connections for all switchblocks in an FPGA would be sparse and possibly very large * so we use an unordered map to take advantage of the sparsity. */ diff --git a/vpr/src/route/cb_metrics.cpp b/vpr/src/route/cb_metrics.cpp index a1fa4294179..6664bd91d41 100644 --- a/vpr/src/route/cb_metrics.cpp +++ b/vpr/src/route/cb_metrics.cpp @@ -19,28 +19,22 @@ #include #include -#include #include #include #include -#include -#include -#include -#include #include #include #include +#include "physical_types_util.h" #include "vtr_random.h" -#include "vtr_assert.h" #include "vtr_log.h" #include "vtr_math.h" #include "vpr_types.h" #include "vpr_error.h" -#include "vpr_utils.h" #include "cb_metrics.h" @@ -170,7 +164,6 @@ void adjust_cb_metric(const e_metric metric, const float target, const float tar get_conn_block_metrics(block_type, pin_to_track_connections, num_segments, segment_inf, pin_type, Fc_array, chan_width_inf, &cb_metrics); - vtr::RngContainer rng(0); /* now run the annealer to adjust the desired metric towards the target value */ bool success = annealer(metric, nodes_per_chan, block_type, pin_type, Fc, num_pin_type_pins, target, @@ -626,7 +619,7 @@ static void get_pin_locations(const t_physical_tile_type_ptr block_type, const e } } /* sort the vector at the current side in increasing order, for good measure */ - std::stable_sort(pin_locations->at(iside).begin(), pin_locations->at(iside).end()); + std::stable_sort(pin_locations->at(iside).begin(), pin_locations->at(iside).end()); } } /* now we have a vector of vectors [0..3][0..num_pins_on_this_side] specifying which pins are on which side */ diff --git a/vpr/src/route/channel_stats.cpp b/vpr/src/route/channel_stats.cpp index 065a6e5b7a0..f95275db9f4 100644 --- a/vpr/src/route/channel_stats.cpp +++ b/vpr/src/route/channel_stats.cpp @@ -36,7 +36,7 @@ void print_channel_stats(bool is_flat) { for (size_t x = 0; x < device_ctx.grid.width() - 1; ++x) { for (size_t y = 0; y < device_ctx.grid.height() - 1; ++y) { float chanx_util = routing_util(chanx_usage[x][y], chanx_avail[x][y]); - float chany_util = routing_util(chanx_usage[x][y], chanx_avail[x][y]); + float chany_util = routing_util(chany_usage[x][y], chany_avail[x][y]); for (float util : {chanx_util, chany_util}) { //Record peak utilization diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index e436018fe52..ab2aad9a281 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -1,20 +1,19 @@ -#include +#include "check_route.h" + +#include "physical_types_util.h" #include "route_common.h" #include "vtr_assert.h" #include "vtr_log.h" -#include "vtr_memory.h" #include "vtr_time.h" #include "vpr_types.h" #include "vpr_error.h" #include "globals.h" -#include "route_export.h" -#include "check_route.h" + #include "rr_graph.h" #include "check_rr_graph.h" -#include "read_xml_arch_file.h" #include "route_tree.h" /******************** Subroutines local to this module **********************/ @@ -39,11 +38,32 @@ static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_ enum e_route_type route_type, bool is_flat); +/** + * Checks that all non-configurable edges are in a legal configuration. + * @param net_list The netlist whose routing is to be checked. + * @param is_flat True if flat routing is enabled; otherwise false. + */ static void check_all_non_configurable_edges(const Netlist<>& net_list, bool is_flat); + +/** + * @brief Checks that the specified routing is legal with respect to non-configurable edges. + * For routing to be valid, if any non-configurable edge is used, all nodes in the same set + * and the required connecting edges in the set must also be used. + * + * @param net_list A reference to the netlist. + * @param net The net id for which the check is done. + * @param non_configurable_rr_sets Node and edge sets that constitute non-configurable RR sets. + * @param rrnode_set_id Specifies which RR sets each RR node is part of. These indices can be used to + * access elements of node_sets and edge_sets in non_configurable_rr_sets. + * @param is_flat Indicates whether flat routing is enabled. + * @return True if check is done successfully; otherwise false. + */ static bool check_non_configurable_edges(const Netlist<>& net_list, ParentNetId net, const t_non_configurable_rr_sets& non_configurable_rr_sets, + const vtr::vector& rrnode_set_id, bool is_flat); + static void check_net_for_stubs(const Netlist<>& net_list, ParentNetId net, bool is_flat); @@ -65,13 +85,9 @@ void check_route(const Netlist<>& net_list, return; } - int max_pins; - unsigned int ipin; - bool valid, connects; - - auto& device_ctx = g_vpr_ctx.device(); + const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - auto& route_ctx = g_vpr_ctx.routing(); + const auto& route_ctx = g_vpr_ctx.routing(); const size_t num_switches = rr_graph.num_rr_switches(); @@ -83,7 +99,7 @@ void check_route(const Netlist<>& net_list, * is a successful routing, but I want to double check it here. */ recompute_occupancy_from_scratch(net_list, is_flat); - valid = feasible_routing(); + const bool valid = feasible_routing(); if (valid == false) { VPR_ERROR(VPR_ERROR_ROUTE, "Error in check_route -- routing resources are overused.\n"); @@ -95,7 +111,7 @@ void check_route(const Netlist<>& net_list, is_flat); } - max_pins = 0; + int max_pins = 0; for (auto net_id : net_list.nets()) max_pins = std::max(max_pins, (int)net_list.net_pins(net_id).size()); @@ -129,7 +145,7 @@ void check_route(const Netlist<>& net_list, check_switch(rt_node, num_switches); if (rt_node.parent()) { - connects = check_adjacent(rt_node.parent()->inode, rt_node.inode, is_flat); + bool connects = check_adjacent(rt_node.parent()->inode, rt_node.inode, is_flat); if (!connects) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_route: found non-adjacent segments in traceback while checking net %d:\n" @@ -154,7 +170,7 @@ void check_route(const Netlist<>& net_list, num_sinks, net_list.net_sinks(net_id).size()); } - for (ipin = 0; ipin < net_list.net_pins(net_id).size(); ipin++) { + for (size_t ipin = 0; ipin < net_list.net_pins(net_id).size(); ipin++) { if (pin_done[ipin] == false) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_route: net %zu does not connect to pin %d.\n", size_t(net_id), ipin); @@ -194,7 +210,7 @@ static void check_sink(const Netlist<>& net_list, inode, net_list.net_name(net_id).c_str(), size_t(net_id)); } - VTR_ASSERT(!pin_done[net_pin_index]); /* Should not have found a routed cnnection to it before */ + VTR_ASSERT(!pin_done[net_pin_index]); /* Should not have found a routed connection to it before */ pin_done[net_pin_index] = true; } @@ -464,8 +480,8 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { VTR_ASSERT(to_type == OPIN || to_type == IPIN); // If pin is located inside a cluster return true; } else { - VTR_ASSERT(to_type == IPIN); - num_adj += 1; + VTR_ASSERT(to_type == IPIN); + num_adj += 1; } break; @@ -614,43 +630,71 @@ static void check_node_and_range(RRNodeId inode, is_flat); } -//Checks that all non-configurable edges are in a legal configuration -//This check is slow, so it has been moved out of check_route() static void check_all_non_configurable_edges(const Netlist<>& net_list, bool is_flat) { + const auto& rr_graph = g_vpr_ctx.device().rr_graph; + vtr::ScopedStartFinishTimer timer("Checking to ensure non-configurable edges are legal"); - auto non_configurable_rr_sets = identify_non_configurable_rr_sets(); + const t_non_configurable_rr_sets non_configurable_rr_sets = identify_non_configurable_rr_sets(); + + // Specifies which RR set each node is part of. + vtr::vector rrnode_set_ids(rr_graph.num_nodes(), -1); + + const size_t num_non_cfg_rr_sets = non_configurable_rr_sets.node_sets.size(); + + // Populate rrnode_set_ids + for (size_t non_cfg_rr_set_id = 0; non_cfg_rr_set_id < num_non_cfg_rr_sets; non_cfg_rr_set_id++) { + const std::set& node_set = non_configurable_rr_sets.node_sets[non_cfg_rr_set_id]; + for (const RRNodeId node_id : node_set) { + VTR_ASSERT_SAFE(rrnode_set_ids[node_id] == -1); + rrnode_set_ids[node_id] = (int)non_cfg_rr_set_id; + } + } for (auto net_id : net_list.nets()) { check_non_configurable_edges(net_list, net_id, non_configurable_rr_sets, + rrnode_set_ids, is_flat); } } -// Checks that the specified routing is legal with respect to non-configurable edges -// -//For routing to be legal if *any* non-configurable edge is used, so must *all* -//other non-configurable edges in the same set static bool check_non_configurable_edges(const Netlist<>& net_list, ParentNetId net, const t_non_configurable_rr_sets& non_configurable_rr_sets, + const vtr::vector& rrnode_set_id, bool is_flat) { const auto& device_ctx = g_vpr_ctx.device(); - auto& route_ctx = g_vpr_ctx.mutable_routing(); + const auto& route_ctx = g_vpr_ctx.routing(); if (!route_ctx.route_trees[net]) // no routing return true; - // Collect all the edges used by this net's routing + // Collect all the nodes, edges, and non-configurable RR set ids used by this net's routing std::set routing_edges; std::set routing_nodes; - for (auto& rt_node : route_ctx.route_trees[net].value().all_nodes()) { + std::set routing_non_configurable_rr_set_ids; + for (const RouteTreeNode& rt_node : route_ctx.route_trees[net].value().all_nodes()) { routing_nodes.insert(rt_node.inode); if (!rt_node.parent()) continue; t_node_edge edge = {rt_node.parent()->inode, rt_node.inode}; routing_edges.insert(edge); + + if (rrnode_set_id[rt_node.inode] >= 0) { // The node belongs to a non-configurable RR set + routing_non_configurable_rr_set_ids.insert(rrnode_set_id[rt_node.inode]); + } + } + + // Copy used non-configurable RR sets + // This is done to check legality only for used non-configurable RR sets. If a non-configurable RR set + // is not used by a net's routing, it cannot violate the requirements of using that non-configurable RR set. + t_non_configurable_rr_sets used_non_configurable_rr_sets; + used_non_configurable_rr_sets.node_sets.reserve(routing_non_configurable_rr_set_ids.size()); + used_non_configurable_rr_sets.edge_sets.reserve(routing_non_configurable_rr_set_ids.size()); + for (const int set_idx : routing_non_configurable_rr_set_ids) { + used_non_configurable_rr_sets.node_sets.emplace_back(non_configurable_rr_sets.node_sets[set_idx]); + used_non_configurable_rr_sets.edge_sets.emplace_back(non_configurable_rr_sets.edge_sets[set_idx]); } //We need to perform two types of checks: @@ -659,13 +703,13 @@ static bool check_non_configurable_edges(const Netlist<>& net_list, // 2) That all (required) non-configurable edges are used // //We need to check (2) in addition to (1) to ensure that (1) did not pass - //because the nodes 'happend' to be connected together by configurable + //because the nodes 'happened' to be connected together by configurable //routing (to be legal, by definition, they must be connected by //non-configurable routing). - //Check that all nodes in each non-configurable set are full included if any element + //Check that all nodes in each non-configurable set are fully included if any element //within a set is used by the routing - for (const auto& rr_nodes : non_configurable_rr_sets.node_sets) { + for (const auto& rr_nodes : used_non_configurable_rr_sets.node_sets) { //Compute the intersection of the routing and current non-configurable nodes set std::vector intersection; std::set_intersection(routing_nodes.begin(), routing_nodes.end(), @@ -687,7 +731,7 @@ static bool check_non_configurable_edges(const Netlist<>& net_list, routing_nodes.begin(), routing_nodes.end(), std::back_inserter(difference)); - VTR_ASSERT(difference.size() > 0); + VTR_ASSERT(!difference.empty()); std::string msg = vtr::string_fmt( "Illegal routing for net '%s' (#%zu) some " "required non-configurably connected nodes are missing:\n", @@ -704,7 +748,7 @@ static bool check_non_configurable_edges(const Netlist<>& net_list, //Check that any sets of non-configurable RR graph edges are fully included //in the routing, if any of a set's edges are used - for (const auto& rr_edges : non_configurable_rr_sets.edge_sets) { + for (const auto& rr_edges : used_non_configurable_rr_sets.edge_sets) { //Compute the intersection of the routing and current non-configurable edge set std::vector intersection; std::set_intersection(routing_edges.begin(), routing_edges.end(), @@ -717,7 +761,7 @@ static bool check_non_configurable_edges(const Netlist<>& net_list, //Since at least one non-configurable edge is used, to be legal //the full set of non-configurably connected edges must be used. // - //This is somewhat complicted by the fact that non-configurable edges + //This is somewhat complicated by the fact that non-configurable edges //are sometimes bi-directional (e.g. electrical shorts) and so appear //in rr_edges twice (once forward, once backward). Only one of the //paired edges need appear to be correct. @@ -810,9 +854,9 @@ class StubFinder { std::set stub_nodes_; }; -//Cheks for stubs in a net's routing. +//Checks for stubs in a net's routing. // -//Stubs (routing branches which don't connect to SINKs) serve no purpose, and only chew up wiring unecessarily. +//Stubs (routing branches which don't connect to SINKs) serve no purpose, and only chew up wiring unnecessarily. //The only exception are stubs required by non-configurable switches (e.g. shorts). // //We treat any configurable stubs as an error. diff --git a/vpr/src/route/clock_connection_builders.cpp b/vpr/src/route/clock_connection_builders.cpp index d7b0f831e44..5a193a159ad 100644 --- a/vpr/src/route/clock_connection_builders.cpp +++ b/vpr/src/route/clock_connection_builders.cpp @@ -2,11 +2,7 @@ #include "globals.h" #include "arch_util.h" -#include "rr_graph2.h" - -#include "vtr_assert.h" -#include "vtr_log.h" -#include "vtr_error.h" +#include "rr_rc_data.h" #include #include diff --git a/vpr/src/route/clock_network_builders.cpp b/vpr/src/route/clock_network_builders.cpp index 40e581a02de..34dccc4ff29 100644 --- a/vpr/src/route/clock_network_builders.cpp +++ b/vpr/src/route/clock_network_builders.cpp @@ -2,9 +2,9 @@ #include "globals.h" +#include "rr_rc_data.h" #include "vtr_assert.h" #include "vtr_log.h" -#include "vtr_error.h" void static populate_segment_values(int seg_index, std::string name, diff --git a/vpr/src/route/clock_network_builders.h b/vpr/src/route/clock_network_builders.h index f9983cd85e9..2e73fe211c0 100644 --- a/vpr/src/route/clock_network_builders.h +++ b/vpr/src/route/clock_network_builders.h @@ -113,8 +113,7 @@ class ClockNetwork { t_rr_graph_storage* rr_nodes, RRGraphBuilder& rr_graph_builder, t_rr_edge_info_set* rr_edges_to_create, - int num_segments_x) - = 0; + int num_segments_x) = 0; virtual size_t estimate_additional_nodes(const DeviceGrid& grid) = 0; virtual void map_relative_seg_indices(const t_unified_to_parallel_seg_index& index_map) = 0; }; diff --git a/vpr/src/route/connection_router.cpp b/vpr/src/route/connection_router.cpp index 8ec7ecc8e2a..664553995a4 100644 --- a/vpr/src/route/connection_router.cpp +++ b/vpr/src/route/connection_router.cpp @@ -221,7 +221,7 @@ void ConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId s HeapNode cheapest; while (heap_.try_pop(cheapest)) { // inode with the cheapest total cost in current route tree to be expanded on - const auto& [ new_total_cost, inode ] = cheapest; + const auto& [new_total_cost, inode] = cheapest; update_router_stats(router_stats_, /*is_push=*/false, inode, @@ -303,7 +303,7 @@ vtr::vector ConnectionRouter::timing_driven_find HeapNode cheapest; while (heap_.try_pop(cheapest)) { // inode with the cheapest total cost in current route tree to be expanded on - const auto& [ new_total_cost, inode ] = cheapest; + const auto& [new_total_cost, inode] = cheapest; update_router_stats(router_stats_, /*is_push=*/false, inode, @@ -573,8 +573,7 @@ void ConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_params& // When RCV is enabled, prune based on the RCV-specific total path cost (see // in `compute_node_cost_using_rcv` in `evaluate_timing_driven_node_costs`) // to allow detours to get better QoR. - if ((!rcv_path_manager.is_enabled() && best_back_cost > new_back_cost) || - (rcv_path_manager.is_enabled() && best_total_cost > new_total_cost)) { + if ((!rcv_path_manager.is_enabled() && best_back_cost > new_back_cost) || (rcv_path_manager.is_enabled() && best_total_cost > new_total_cost)) { VTR_LOGV_DEBUG(router_debug_, " Expanding to node %d (%s)\n", to_node, describe_rr_node(device_ctx.rr_graph, device_ctx.grid, @@ -790,12 +789,12 @@ void ConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* t //Update total cost float expected_cost = router_lookahead_.get_expected_cost(to->index, target_node, cost_params, to->R_upstream); VTR_LOGV_DEBUG(router_debug_ && !std::isfinite(expected_cost), - " Lookahead from %s (%s) to %s (%s) is non-finite, expected_cost = %f, to->R_upstream = %f\n", - rr_node_arch_name(to->index, is_flat_).c_str(), - describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to->index, is_flat_).c_str(), - rr_node_arch_name(target_node, is_flat_).c_str(), - describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, target_node, is_flat_).c_str(), - expected_cost, to->R_upstream); + " Lookahead from %s (%s) to %s (%s) is non-finite, expected_cost = %f, to->R_upstream = %f\n", + rr_node_arch_name(to->index, is_flat_).c_str(), + describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to->index, is_flat_).c_str(), + rr_node_arch_name(target_node, is_flat_).c_str(), + describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, target_node, is_flat_).c_str(), + expected_cost, to->R_upstream); total_cost += to->backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); } to->total_cost = total_cost; @@ -876,7 +875,7 @@ void ConnectionRouter::add_route_tree_node_to_heap( describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, is_flat_).c_str()); if (tot_cost > rr_node_route_inf_[inode].path_cost) { - return ; + return; } add_to_mod_list(inode); rr_node_route_inf_[inode].path_cost = tot_cost; @@ -1068,8 +1067,7 @@ static inline void update_router_stats(RouterStats* router_stats, const VibInf* vib; if (!g_vpr_ctx.device().arch->vib_infs.empty()) { vib = g_vpr_ctx.device().vib_grid.get_vib(rr_graph->node_layer(rr_node_id), rr_graph->node_xlow(rr_node_id), rr_graph->node_ylow(rr_node_id)); - } - else { + } else { vib = nullptr; } if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { diff --git a/vpr/src/route/connection_router.h b/vpr/src/route/connection_router.h index cee93384974..0de6d508991 100644 --- a/vpr/src/route/connection_router.h +++ b/vpr/src/route/connection_router.h @@ -51,7 +51,7 @@ class ConnectionRouter : public ConnectionRouterInterface { ~ConnectionRouter() { VTR_LOG("Serial Connection Router is being destroyed. Time spent on path search: %.3f seconds.\n", - std::chrono::duration(path_search_cumulative_time).count()); + std::chrono::duration(path_search_cumulative_time).count()); } // Clear's the modified list. Should be called after reset_path_costs diff --git a/vpr/src/route/connection_router_interface.h b/vpr/src/route/connection_router_interface.h index 62111edc285..96ef278833a 100644 --- a/vpr/src/route/connection_router_interface.h +++ b/vpr/src/route/connection_router_interface.h @@ -59,8 +59,7 @@ class ConnectionRouterInterface { const t_conn_cost_params& cost_params, const t_bb& bounding_box, RouterStats& router_stats, - const ConnectionParameters& conn_params) - = 0; + const ConnectionParameters& conn_params) = 0; /** Finds a path from the route tree rooted at rt_root to sink_node for a * high fanout net. @@ -79,8 +78,7 @@ class ConnectionRouterInterface { const t_bb& bounding_box, const SpatialRouteTreeLookup& spatial_rt_lookup, RouterStats& router_stats, - const ConnectionParameters& conn_params) - = 0; + const ConnectionParameters& conn_params) = 0; // Finds a path from the route tree rooted at rt_root to all sinks // available. @@ -99,8 +97,7 @@ class ConnectionRouterInterface { const t_conn_cost_params& cost_params, const t_bb& bounding_box, RouterStats& router_stats, - const ConnectionParameters& conn_params) - = 0; + const ConnectionParameters& conn_params) = 0; // Sets whether router debug information should be on. virtual void set_router_debug(bool router_debug) = 0; diff --git a/vpr/src/route/d_ary_heap.h b/vpr/src/route/d_ary_heap.h index 5ac59f1eef2..c52cd702d13 100644 --- a/vpr/src/route/d_ary_heap.h +++ b/vpr/src/route/d_ary_heap.h @@ -17,7 +17,7 @@ * to BinaryHeap. This is likely because FourAryHeap has lower tree height, and as we can fit 8 * heap node (each is 8 bytes) on a cache line (commonly 64 bytes on modern architectures), each * heap operation (the comparison among sibling nodes) tends to benefit from the caches. -*/ + */ template class DAryHeap : public HeapInterface { public: diff --git a/vpr/src/route/d_ary_heap.tpp b/vpr/src/route/d_ary_heap.tpp index 565b8bac72b..b1fb0529c86 100644 --- a/vpr/src/route/d_ary_heap.tpp +++ b/vpr/src/route/d_ary_heap.tpp @@ -58,7 +58,7 @@ class customized_d_ary_priority_queue { inline size_t largest_child_index_partial(const size_t first_child, const size_t num_children /*must < `D`*/) { if constexpr (D == 2) { - (void) num_children; + (void)num_children; return first_child; } else { switch (num_children) { @@ -125,7 +125,7 @@ class customized_d_ary_priority_queue { public: explicit customized_d_ary_priority_queue(const Compare& compare = Compare(), - const Container& cont = Container()) + const Container& cont = Container()) : comp_(compare) , heap_(cont) { heap_.resize(1); // FIXME: currently do not support `make_heap` from cont (heap_) diff --git a/vpr/src/route/edge_groups.cpp b/vpr/src/route/edge_groups.cpp index 6b63f7d8823..6ca1e36692a 100644 --- a/vpr/src/route/edge_groups.cpp +++ b/vpr/src/route/edge_groups.cpp @@ -52,14 +52,14 @@ t_non_configurable_rr_sets EdgeGroups::output_sets() { std::set edge_set; std::set node_set(nodes.begin(), nodes.end()); - for (const auto& src : node_set) { - for (const auto& dest : graph_[src].edges) { - edge_set.emplace(t_node_edge(src, dest)); + for (const RRNodeId src : node_set) { + for (const RRNodeId dest : graph_[src].edges) { + edge_set.emplace(src, dest); } } - sets.node_sets.emplace(std::move(node_set)); - sets.edge_sets.emplace(std::move(edge_set)); + sets.node_sets.emplace_back(std::move(node_set)); + sets.edge_sets.emplace_back(std::move(edge_set)); } return sets; diff --git a/vpr/src/route/netlist_routers.h b/vpr/src/route/netlist_routers.h index 1524c2ddb38..d64477f03ad 100644 --- a/vpr/src/route/netlist_routers.h +++ b/vpr/src/route/netlist_routers.h @@ -71,9 +71,10 @@ class NetlistRouter { /* Include the derived classes here to get the HeapType-templated impls */ #include "SerialNetlistRouter.h" +#include "NestedNetlistRouter.h" #ifdef VPR_USE_TBB -# include "ParallelNetlistRouter.h" -# include "DecompNetlistRouter.h" +#include "ParallelNetlistRouter.h" +#include "DecompNetlistRouter.h" #endif template @@ -104,6 +105,20 @@ inline std::unique_ptr make_netlist_router_with_heap( routing_predictor, choking_spots, is_flat); + } else if (router_opts.router_algorithm == e_router_algorithm::NESTED) { + return std::make_unique>( + net_list, + router_lookahead, + router_opts, + connections_inf, + net_delay, + netlist_pin_lookup, + timing_info, + pin_timing_invalidator, + budgeting_inf, + routing_predictor, + choking_spots, + is_flat); } else if (router_opts.router_algorithm == e_router_algorithm::PARALLEL) { #ifdef VPR_USE_TBB return std::make_unique>( diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index cdaa5c00805..618f4edc67b 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -1,6 +1,7 @@ #include "overuse_report.h" #include +#include "physical_types_util.h" #include "vtr_log.h" /** @@ -29,13 +30,28 @@ static void report_congested_nets(const Netlist<>& net_list, static void log_overused_nodes_header(); static void log_single_overused_node_status(int overuse_index, RRNodeId inode); -void print_block_pins_nets(std::ostream& os, - t_physical_tile_type_ptr physical_type, - int layer, - int root_x, - int root_y, - int pin_physical_num, - const std::map>& rr_node_to_net_map); + +/** + * @brief When reporting overused IPIN/OPIN nodes, we also print the nets + * connected to other pins of the same block. This information may help + * the user understand why the node is overused or why other pins are not + * being utilized for routing the net. + * + * @param os The output stream to write the information to. + * @param physical_type The physical type of the block. + * @param layer The layer number of the block. + * @param root_x The x coordinate of the root of the block. + * @param root_y The y coordinate of the root of the block. + * @param pin_physical_num The physical number of the pin. + * @param rr_node_to_net_map A map of RR nodes to the nets that pass through them. + */ +static void print_block_pins_nets(std::ostream& os, + t_physical_tile_type_ptr physical_type, + int layer, + int root_x, + int root_y, + int pin_physical_num, + const std::map>& rr_node_to_net_map); /** * @brief Print out RR node overuse info in the VPR logfile. * @@ -141,7 +157,7 @@ void report_overused_nodes(const Netlist<>& net_list, * info on the nets passing through this overused node */ os << "-----------------------------\n"; //Separation line report_congested_nets(net_list, - g_vpr_ctx.atom().lookup, + g_vpr_ctx.atom().lookup(), os, congested_nets, is_flat, @@ -223,8 +239,7 @@ static void report_overused_ipin_opin(std::ostream& os, const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid.get_vib(grid_layer, grid_x, grid_y); - } - else { + } else { vib = nullptr; } //const t_vib_inf* vib = device_ctx.vib_grid[grid_layer][grid_x][grid_y]; @@ -329,7 +344,7 @@ static void report_congested_nets(const Netlist<>& net_list, os << "Net name = " << net_list.net_name(net_id) << ", "; if (is_flat) { AtomBlockId atom_blk_id = convert_to_atom_block_id(block_id); - os << "Driving block name = " << atom_lookup.atom_pb(atom_blk_id)->name << ", "; + os << "Driving block name = " << atom_lookup.atom_pb_bimap().atom_pb(atom_blk_id)->name << ", "; os << "Driving block type = " << g_vpr_ctx.clustering().clb_nlist.block_type(atom_lookup.atom_clb(atom_blk_id))->name << '\n'; } else { ClusterBlockId clb_blk_id = convert_to_cluster_block_id(block_id); @@ -357,7 +372,7 @@ static void report_congested_nets(const Netlist<>& net_list, << "\n"; if (is_flat) { auto pb_pin = atom_lookup.atom_pin_pb_graph_pin(convert_to_atom_pin_id(sink_id)); - auto pb_net_list = atom_lookup.atom_pb(convert_to_atom_block_id(net_list.pin_block(sink_id))); + auto pb_net_list = atom_lookup.atom_pb_bimap().atom_pb(convert_to_atom_block_id(net_list.pin_block(sink_id))); os << " " << "Pin Logical Num: " << pb_pin->pin_count_in_cluster << " PB Type: " << pb_pin->parent_node->pb_type->name << " Netlist PB: " << pb_net_list->name << " Parent PB Type: " << pb_net_list->parent_pb->pb_graph_node->pb_type->name << "Parent Netlist PB : " << pb_net_list->parent_pb->name << "\n"; os << " " @@ -447,17 +462,18 @@ static void log_single_overused_node_status(int overuse_index, RRNodeId node_id) fflush(stdout); } -void print_block_pins_nets(std::ostream& os, - t_physical_tile_type_ptr physical_type, - int layer, - int root_x, - int root_y, - int pin_physical_num, - const std::map>& rr_node_to_net_map) { +static void print_block_pins_nets(std::ostream& os, + t_physical_tile_type_ptr physical_type, + int layer, + int root_x, + int root_y, + int pin_physical_num, + const std::map>& rr_node_to_net_map) { const auto& rr_graph = g_vpr_ctx.device().rr_graph; t_pin_range pin_num_range; - if (is_pin_on_tile(physical_type, pin_physical_num)) { + bool pin_on_tile = is_pin_on_tile(physical_type, pin_physical_num); + if (pin_on_tile) { pin_num_range.low = 0; pin_num_range.high = physical_type->num_pins - 1; } else { @@ -479,7 +495,13 @@ void print_block_pins_nets(std::ostream& os, for (int pin = pin_num_range.low; pin <= pin_num_range.high; pin++) { t_rr_type rr_type = (get_pin_type_from_pin_physical_num(physical_type, pin) == DRIVER) ? t_rr_type::OPIN : t_rr_type::IPIN; RRNodeId node_id = get_pin_rr_node_id(rr_graph.node_lookup(), physical_type, layer, root_x, root_y, pin); - VTR_ASSERT(node_id != RRNodeId::INVALID()); + // When flat router is enabled, RR Node chains collapse into a single node. Thus, when + // looking up the RR Node ID, it may return an invalid node ID. In this case, we skip + // this pin. + if (!pin_on_tile && node_id == RRNodeId::INVALID()) { + continue; + } + VTR_ASSERT(node_id.is_valid()); auto search_result = rr_node_to_net_map.find(node_id); if (rr_type == t_rr_type::OPIN) { os << " OPIN - "; diff --git a/vpr/src/route/overuse_report.h b/vpr/src/route/overuse_report.h index ff48e170cfe..bae9da1d135 100644 --- a/vpr/src/route/overuse_report.h +++ b/vpr/src/route/overuse_report.h @@ -20,7 +20,11 @@ * All the nets passing through an overused RR node are flagged as congested nets. */ -///@brief Print out RR node overuse info in the VPR logfile. +/** + * @brief Print out RR node overuse info in the VPR logfile. + * + * @param max_logged_overused_rr_nodes The maximum number of overused RR nodes to log. + */ void log_overused_nodes_status(int max_logged_overused_rr_nodes); ///@brief Print out RR node overuse info in a post-VPR report file. diff --git a/vpr/src/route/partition_tree.cpp b/vpr/src/route/partition_tree.cpp index ac95a9a5285..38ee7abc2dd 100644 --- a/vpr/src/route/partition_tree.cpp +++ b/vpr/src/route/partition_tree.cpp @@ -34,7 +34,7 @@ std::unique_ptr PartitionTree::build_helper(const Netlist<>& out->bb = {x1, x2, y1, y2, 0, layer_max}; out->nets = nets; /* Build net to ptree node lookup */ - for(auto net_id: nets){ + for (auto net_id : nets) { _net_to_ptree_node[net_id] = out.get(); } return out; @@ -130,7 +130,7 @@ std::unique_ptr PartitionTree::build_helper(const Netlist<>& out->bb = {x1, x2, y1, y2, 0, layer_max}; out->nets = nets; /* Build net to ptree node lookup */ - for(auto net_id: nets){ + for (auto net_id : nets) { _net_to_ptree_node[net_id] = out.get(); } } @@ -169,9 +169,9 @@ std::unique_ptr PartitionTree::build_helper(const Netlist<>& out->right = build_helper(netlist, right_nets, x1, std::floor(best_pos + 1), x2, y2); } - if(out->left) + if (out->left) out->left->parent = out.get(); - if(out->right) + if (out->right) out->right->parent = out.get(); out->bb = {x1, x2, y1, y2, 0, 0}; @@ -180,23 +180,23 @@ std::unique_ptr PartitionTree::build_helper(const Netlist<>& out->cutline_pos = best_pos; /* Build net to ptree node lookup */ - for(auto net_id: my_nets){ + for (auto net_id : my_nets) { _net_to_ptree_node[net_id] = out.get(); } return out; } -inline bool net_in_ptree_node(ParentNetId net_id, const PartitionTreeNode* node){ +inline bool net_in_ptree_node(ParentNetId net_id, const PartitionTreeNode* node) { auto& route_ctx = g_vpr_ctx.routing(); const t_bb& bb = route_ctx.route_bb[net_id]; return bb.xmin >= node->bb.xmin && bb.xmax <= node->bb.xmax && bb.ymin >= node->bb.ymin && bb.ymax <= node->bb.ymax; } void PartitionTree::update_nets(const std::vector& nets) { - for(auto net_id: nets){ + for (auto net_id : nets) { PartitionTreeNode* old_ptree_node = _net_to_ptree_node[net_id]; PartitionTreeNode* new_ptree_node = old_ptree_node; - while(!net_in_ptree_node(net_id, new_ptree_node)) + while (!net_in_ptree_node(net_id, new_ptree_node)) new_ptree_node = new_ptree_node->parent; old_ptree_node->nets.erase(net_id); new_ptree_node->nets.insert(net_id); @@ -208,13 +208,13 @@ void PartitionTree::update_nets(const std::vector& nets) { void PartitionTree::clear_vnets(void) { std::stack stack; stack.push(_root.get()); - while(!stack.empty()){ + while (!stack.empty()) { PartitionTreeNode* node = stack.top(); stack.pop(); node->vnets.clear(); - if(node->left) + if (node->left) stack.push(node->left.get()); - if(node->right) + if (node->right) stack.push(node->right.get()); } } diff --git a/vpr/src/route/partition_tree.h b/vpr/src/route/partition_tree.h index 82b75976b83..6bf68be04b8 100644 --- a/vpr/src/route/partition_tree.h +++ b/vpr/src/route/partition_tree.h @@ -10,7 +10,7 @@ #include #ifdef VPR_USE_TBB -# include +#include #endif /** Self-descriptive */ @@ -87,10 +87,10 @@ class PartitionTree { inline PartitionTreeNode& root(void) { return *_root; } /** Handle nets which had a bounding box update. - * Bounding boxes can only grow, so we should find a new partition tree node for - * these nets by moving them up until they fit in a node's bounds */ + * Bounding boxes can only grow, so we should find a new partition tree node for + * these nets by moving them up until they fit in a node's bounds */ void update_nets(const std::vector& nets); - + /** Delete all virtual nets in the tree. Used for the net decomposing router. * Virtual nets are invalidated between iterations due to changing bounding * boxes. */ diff --git a/vpr/src/route/route.cpp b/vpr/src/route/route.cpp index 6010e0626ef..098ae85ba5e 100644 --- a/vpr/src/route/route.cpp +++ b/vpr/src/route/route.cpp @@ -34,18 +34,18 @@ bool route(const Netlist<>& net_list, VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "No nets to route\n"); } - t_graph_type graph_type; - t_graph_type graph_directionality; + e_graph_type graph_type; + e_graph_type graph_directionality; if (router_opts.route_type == GLOBAL) { - graph_type = GRAPH_GLOBAL; - graph_directionality = GRAPH_BIDIR; + graph_type = e_graph_type::GLOBAL; + graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); /* Branch on tileable routing */ if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { - graph_type = GRAPH_UNIDIR_TILEABLE; + graph_type = e_graph_type::UNIDIR_TILEABLE; } - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } /* Set the channel widths */ @@ -77,7 +77,7 @@ bool route(const Netlist<>& net_list, is_flat); IntraLbPbPinLookup intra_lb_pb_pin_lookup(device_ctx.logical_block_types); - ClusteredPinAtomPinsLookup netlist_pin_lookup(cluster_ctx.clb_nlist, atom_ctx.nlist, intra_lb_pb_pin_lookup); + ClusteredPinAtomPinsLookup netlist_pin_lookup(cluster_ctx.clb_nlist, atom_ctx.netlist(), intra_lb_pb_pin_lookup); auto choking_spots = set_nets_choking_spots(net_list, route_ctx.net_terminal_groups, @@ -204,8 +204,8 @@ bool route(const Netlist<>& net_list, router_opts.timing_update_type, net_list, netlist_pin_lookup, - atom_ctx.nlist, - atom_ctx.lookup, + atom_ctx.netlist(), + atom_ctx.lookup(), timing_info, is_flat); @@ -312,7 +312,7 @@ bool route(const Netlist<>& net_list, float iter_cumm_time = iteration_timer.elapsed_sec(); float iter_elapsed_time = iter_cumm_time - prev_iter_cumm_time; - PartitionTreeDebug::log("Iteration " + std::to_string(itry) + " took " + std::to_string(iter_elapsed_time) + " s"); + PartitionTreeDebug::log("Iteration " + std::to_string(itry) + " took " + std::to_string(iter_elapsed_time) + " s"); //Output progress print_route_status(itry, iter_elapsed_time, pres_fac, num_net_bounding_boxes_updated, iter_results.stats, overuse_info, wirelength_info, timing_info, est_success_iteration); @@ -605,7 +605,6 @@ bool route(const Netlist<>& net_list, print_invalid_routing_info(net_list, is_flat); } } - } if (router_opts.with_timing_analysis) { diff --git a/vpr/src/route/route_budgets.cpp b/vpr/src/route/route_budgets.cpp index 00dd14ae2bc..677450ee034 100644 --- a/vpr/src/route/route_budgets.cpp +++ b/vpr/src/route/route_budgets.cpp @@ -507,7 +507,7 @@ float route_budgets::get_total_path_delay(std::shared_ptrsetup_tags(timing_node, tatum::TagType::DATA_ARRIVAL); auto required_tags = timing_analyzer->setup_tags(timing_node, tatum::TagType::DATA_REQUIRED); @@ -660,7 +660,7 @@ void route_budgets::check_if_budgets_in_bounds() { std::shared_ptr route_budgets::perform_sta(NetPinsMatrix& temp_budgets) { auto& atom_ctx = g_vpr_ctx.atom(); /*Perform static timing analysis to get the delay and path weights for slack allocation*/ - std::shared_ptr routing_delay_calc = std::make_shared(atom_ctx.nlist, atom_ctx.lookup, temp_budgets, is_flat_); + std::shared_ptr routing_delay_calc = std::make_shared(atom_ctx.netlist(), atom_ctx.lookup(), temp_budgets, is_flat_); //TODO: now that we support incremental timing updates, we should avoid re-building the timing analyzer from scratch and try // to calculate this incrementally @@ -950,4 +950,4 @@ void route_budgets::set_should_reroute(ParentNetId net_id, bool value) { if (set) { should_reroute_for_hold[net_id] = value; } -} \ No newline at end of file +} diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 7fd9720e450..3b720c5d76f 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -2,11 +2,16 @@ #include "atom_netlist_utils.h" #include "connection_router_interface.h" +#include "describe_rr_node.h" #include "draw_global.h" -#include "place_and_route.h" #include "route_common.h" +#include "physical_types_util.h" #include "route_export.h" -#include "rr_graph.h" + +#if defined(VPR_USE_TBB) +#include +#include +#endif /* The numbering relation between the channels and clbs is: * * * @@ -533,8 +538,8 @@ load_net_terminal_groups(const RRGraphView& rr_graph, } if (group_num == -1) { - /* TODO: net_terminal_groups cannot be fully RRNodeId - ified, because this code calls libarchfpga which - * I think should not be aware of RRNodeIds. Fixing this requires some refactoring to lift the offending functions + /* TODO: net_terminal_groups cannot be fully RRNodeId - ified, because this code calls libarchfpga which + * I think should not be aware of RRNodeIds. Fixing this requires some refactoring to lift the offending functions * into VPR. */ std::vector new_group = {int(rr_node_num)}; int new_group_num = net_terminal_groups[net_id].size(); @@ -601,12 +606,11 @@ static vtr::vector> load_rr_clb_sources(con static vtr::vector load_is_clock_net(const Netlist<>& net_list, bool is_flat) { - vtr::vector is_clock_net; + vtr::vector is_clock_net(net_list.nets().size()); auto& atom_ctx = g_vpr_ctx.atom(); - std::set clock_nets = find_netlist_physical_clock_nets(atom_ctx.nlist); + std::set clock_nets = find_netlist_physical_clock_nets(atom_ctx.netlist()); - is_clock_net.resize(net_list.nets().size()); for (auto net_id : net_list.nets()) { std::size_t net_id_num = std::size_t(net_id); if (is_flat) { @@ -614,7 +618,7 @@ static vtr::vector load_is_clock_net(const Netlist<>& net_ is_clock_net[net_id] = clock_nets.find(atom_net_id) != clock_nets.end(); } else { ClusterNetId cluster_net_id = ClusterNetId(net_id_num); - is_clock_net[net_id] = clock_nets.find(atom_ctx.lookup.atom_net(cluster_net_id)) != clock_nets.end(); + is_clock_net[net_id] = clock_nets.find(atom_ctx.lookup().atom_net(cluster_net_id)) != clock_nets.end(); } } diff --git a/vpr/src/route/route_profiling.cpp b/vpr/src/route/route_profiling.cpp index b7c88749335..7ae6f7c813e 100644 --- a/vpr/src/route/route_profiling.cpp +++ b/vpr/src/route/route_profiling.cpp @@ -146,7 +146,7 @@ struct Congested_node_types { }; void congestion_analysis() { -# if 0 +#if 0 // each type indexes into array which holds the congestion for that type std::vector congestion_per_type((size_t)NUM_RR_TYPES, 0); // print out specific node information if congestion for type is low enough @@ -183,7 +183,7 @@ void congestion_analysis() { } } return; -# endif +#endif } static clock_t conn_start_time; diff --git a/vpr/src/route/route_utilization.cpp b/vpr/src/route/route_utilization.cpp index 05fc2eda054..66b03751451 100644 --- a/vpr/src/route/route_utilization.cpp +++ b/vpr/src/route/route_utilization.cpp @@ -16,7 +16,7 @@ vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool //Collect all the in-use RR nodes std::set rr_nodes; for (auto net : cluster_ctx.clb_nlist.nets()) { - auto parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup, net, is_flat); + auto parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup(), net, is_flat); if (!route_ctx.route_trees[parent_id]) continue; diff --git a/vpr/src/route/route_utils.cpp b/vpr/src/route/route_utils.cpp index b398066769f..aab9e952315 100644 --- a/vpr/src/route/route_utils.cpp +++ b/vpr/src/route/route_utils.cpp @@ -10,6 +10,7 @@ #include "net_delay.h" #include "netlist_fwd.h" #include "overuse_report.h" +#include "physical_types_util.h" #include "place_and_route.h" #include "route_debug.h" @@ -219,7 +220,7 @@ void generate_route_timing_reports(const t_router_opts& router_opts, auto& atom_ctx = g_vpr_ctx.atom(); const auto& blk_loc_registry = g_vpr_ctx.placement().blk_loc_registry(); - VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); @@ -471,14 +472,14 @@ void try_graph(int width_fac, bool is_flat) { auto& device_ctx = g_vpr_ctx.mutable_device(); - t_graph_type graph_type; - t_graph_type graph_directionality; + e_graph_type graph_type; + e_graph_type graph_directionality; if (router_opts.route_type == GLOBAL) { - graph_type = GRAPH_GLOBAL; - graph_directionality = GRAPH_BIDIR; + graph_type = e_graph_type::GLOBAL; + graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } /* Set the channel widths */ @@ -516,7 +517,7 @@ void update_draw_pres_fac(const float /*new_pres_fac*/) { #ifndef NO_GRAPHICS void update_router_info_and_check_bp(bp_router_type type, int net_id) { t_draw_state* draw_state = get_draw_state_vars(); - if (draw_state->list_of_breakpoints.size() != 0) { + if (!draw_state->list_of_breakpoints.empty()) { if (type == BP_ROUTE_ITER) get_bp_state_globals()->get_glob_breakpoint_state()->router_iter++; else if (type == BP_NET_ID) diff --git a/vpr/src/route/route_utils.h b/vpr/src/route/route_utils.h index d129193ee1e..19f14e7cdb2 100644 --- a/vpr/src/route/route_utils.h +++ b/vpr/src/route/route_utils.h @@ -73,12 +73,12 @@ int get_max_pins_per_net(const Netlist<>& net_list); /** Get the RouteTree associated with the ClusterNetId. * Flat routing maps AtomNetIds to RouteTrees instead, so we need to first look up the associated AtomNetId. */ -inline const vtr::optional& get_route_tree_from_cluster_net_id(ClusterNetId net_id){ +inline const vtr::optional& get_route_tree_from_cluster_net_id(ClusterNetId net_id) { auto& route_ctx = g_vpr_ctx.routing(); - if(!route_ctx.is_flat){ + if (!route_ctx.is_flat) { return route_ctx.route_trees[ParentNetId(net_id)]; - }else{ - auto& atom_lookup = g_vpr_ctx.atom().lookup; + } else { + auto& atom_lookup = g_vpr_ctx.atom().lookup(); AtomNetId atom_id = atom_lookup.atom_net(net_id); return route_ctx.route_trees[ParentNetId(atom_id)]; } diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index 1b8c4ab771d..d88b0024517 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -6,7 +6,6 @@ #include "route_tree.h" #include "rr_graph.h" #include "vtr_time.h" -#include "draw.h" RouterDelayProfiler::RouterDelayProfiler(const Netlist<>& net_list, const RouterLookahead* lookahead, @@ -187,10 +186,10 @@ vtr::vector calculate_all_path_delays_from_rr_node(RRNodeId src RouterStats router_stats; ConnectionParameters conn_params(ParentNetId::INVALID(), OPEN, false, std::unordered_map()); vtr::vector shortest_paths = router.timing_driven_find_all_shortest_paths_from_route_tree(tree.root(), - cost_params, - bounding_box, - router_stats, - conn_params); + cost_params, + bounding_box, + router_stats, + conn_params); VTR_ASSERT(shortest_paths.size() == device_ctx.rr_graph.num_nodes()); for (int isink = 0; isink < (int)device_ctx.rr_graph.num_nodes(); ++isink) { @@ -250,16 +249,17 @@ void alloc_routing_structs(const t_chan_width& chan_width, const std::vector& directs, bool is_flat) { int warnings; - t_graph_type graph_type; + e_graph_type graph_type; auto& device_ctx = g_vpr_ctx.mutable_device(); if (router_opts.route_type == GLOBAL) { - graph_type = GRAPH_GLOBAL; + graph_type = e_graph_type::GLOBAL; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); - if ((UNI_DIRECTIONAL == det_routing_arch->directionality) && (true == det_routing_arch->tileable)) { - graph_type = GRAPH_UNIDIR_TILEABLE; + graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + /* Branch on tileable routing */ + if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + graph_type = e_graph_type::UNIDIR_TILEABLE; } } diff --git a/vpr/src/route/router_lookahead_cost_map.cpp b/vpr/src/route/router_lookahead_cost_map.cpp index ec27878b3a1..2f7a8911084 100644 --- a/vpr/src/route/router_lookahead_cost_map.cpp +++ b/vpr/src/route/router_lookahead_cost_map.cpp @@ -6,11 +6,11 @@ #include "vtr_geometry.h" #ifdef VTR_ENABLE_CAPNPROTO -# include "capnp/serialize.h" -# include "extended_map_lookahead.capnp.h" -# include "ndmatrix_serdes.h" -# include "mmap_file.h" -# include "serdes_utils.h" +#include "capnp/serialize.h" +#include "extended_map_lookahead.capnp.h" +#include "ndmatrix_serdes.h" +#include "mmap_file.h" +#include "serdes_utils.h" #endif // Lookahead penalties constants diff --git a/vpr/src/route/router_lookahead_extended_map.cpp b/vpr/src/route/router_lookahead_extended_map.cpp index d72f5471130..2f3964b47b5 100644 --- a/vpr/src/route/router_lookahead_extended_map.cpp +++ b/vpr/src/route/router_lookahead_extended_map.cpp @@ -19,15 +19,15 @@ #include "route_debug.h" #ifdef VTR_ENABLE_CAPNPROTO -# include "capnp/serialize.h" -# include "extended_map_lookahead.capnp.h" -# include "ndmatrix_serdes.h" -# include "mmap_file.h" -# include "serdes_utils.h" +#include "capnp/serialize.h" +#include "extended_map_lookahead.capnp.h" +#include "ndmatrix_serdes.h" +#include "mmap_file.h" +#include "serdes_utils.h" #endif #if defined(VPR_USE_TBB) -# include +#include #endif /* we're profiling routing cost over many tracks for each wire type, so we'll diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 648b182c9eb..d11f216c8ee 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -24,28 +24,24 @@ #include #include #include "connection_router_interface.h" +#include "physical_types_util.h" #include "vpr_types.h" -#include "vpr_error.h" #include "vpr_utils.h" #include "globals.h" #include "vtr_math.h" -#include "vtr_log.h" #include "vtr_assert.h" #include "vtr_time.h" -#include "vtr_geometry.h" #include "router_lookahead_map.h" #include "router_lookahead_map_utils.h" -#include "rr_graph2.h" #include "rr_graph.h" -#include "route_common.h" #ifdef VTR_ENABLE_CAPNPROTO -# include "capnp/serialize.h" -# include "map_lookahead.capnp.h" -# include "ndmatrix_serdes.h" -# include "intra_cluster_serdes.h" -# include "mmap_file.h" -# include "serdes_utils.h" +#include "capnp/serialize.h" +#include "map_lookahead.capnp.h" +#include "ndmatrix_serdes.h" +#include "intra_cluster_serdes.h" +#include "mmap_file.h" +#include "serdes_utils.h" #endif /* VTR_ENABLE_CAPNPROTO */ static constexpr int VALID_NEIGHBOR_NUMBER = 3; @@ -207,8 +203,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(current_node), rr_graph.node_xlow(current_node), rr_graph.node_ylow(current_node)); - } - else { + } else { vib = nullptr; } //const t_vib_inf* vib = device_ctx.vib_grid[rr_graph.node_layer(current_node)][rr_graph.node_xlow(current_node)][rr_graph.node_ylow(current_node)]; @@ -334,7 +329,6 @@ std::pair MapLookahead::get_expected_delay_and_cong(RRNodeId from_ //cost to reach them) in src_opin_delays. Once we know what wire types are //reachable, we query the f_wire_cost_map (i.e. the wire lookahead) to get the final //delay to reach the sink. - t_physical_tile_type_ptr from_tile_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(from_node), rr_graph.node_ylow(from_node), from_layer_num}); @@ -348,15 +342,15 @@ std::pair MapLookahead::get_expected_delay_and_cong(RRNodeId from_ * the minimum cost among them. In the following for loop, we iterate over each layer and pass it the * routing segments on that layer reachable from the OPIN/SOURCE to segments on that layer. This for loop then calculates and returns * the minimum cost from the given OPIN/SOURCE to the specified SINK considering routing options across all layers. - */ + */ for (int layer_num = 0; layer_num < device_ctx.grid.get_num_layers(); layer_num++) { float this_delay_cost; float this_cong_cost; std::tie(this_delay_cost, this_cong_cost) = util::get_cost_from_src_opin(src_opin_delays[from_layer_num][from_tile_index][from_ptc][layer_num], - delta_x, - delta_y, - to_layer_num, - get_wire_cost_entry); + delta_x, + delta_y, + to_layer_num, + get_wire_cost_entry); expected_delay_cost = std::min(expected_delay_cost, this_delay_cost); expected_cong_cost = std::min(expected_cong_cost, this_cong_cost); } @@ -904,9 +898,9 @@ static void min_opin_distance_cost_map(const util::t_src_opin_delays& src_opin_d // #ifndef VTR_ENABLE_CAPNPROTO -# define DISABLE_ERROR \ - "is disabled because VTR_ENABLE_CAPNPROTO=OFF." \ - "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable." +#define DISABLE_ERROR \ + "is disabled because VTR_ENABLE_CAPNPROTO=OFF." \ + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable." void read_router_lookahead(const std::string& /*file*/) { VPR_THROW(VPR_ERROR_PLACE, "MapLookahead::read_router_lookahead " DISABLE_ERROR); diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index a433ad365a3..c64e97f85c3 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -12,6 +12,7 @@ #include #include "globals.h" +#include "physical_types_util.h" #include "vpr_context.h" #include "vtr_math.h" #include "vtr_time.h" @@ -58,7 +59,6 @@ static void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, vtr::vector& node_expanded, std::priority_queue& pq); - /** * @brief Computes the adjusted position of an RR graph node. * This function does not modify the position of the given node. @@ -423,8 +423,7 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat) { const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid.get_vib(sample_loc.layer_num, sample_loc.x, sample_loc.y); - } - else { + } else { vib = nullptr; } //const t_vib_inf* vib = device_ctx.vib_grid[sample_loc.layer_num][sample_loc.x][sample_loc.y]; @@ -674,7 +673,18 @@ std::pair get_xy_deltas(RRNodeId from_node, RRNodeId to_node) { Direction from_dir = rr_graph.node_direction(from_node); if (is_chan(from_type) && ((to_seg < from_seg_low && from_dir == Direction::INC) || (to_seg > from_seg_high && from_dir == Direction::DEC))) { - delta_seg++; + // If the routing channel starts from the perimeter of the grid, + // and it is heading towards the outside of the grid, we should + // not increment the delta_seg by 1. + int max_seg_index = -1; + if (from_type == CHANX) { + max_seg_index = static_cast(device_ctx.grid.width()) - 1; + } else { + max_seg_index = static_cast(device_ctx.grid.height()) - 1; + } + if (!((from_seg_low == 0 && from_dir == Direction::DEC) || (from_seg_low == max_seg_index && from_dir == Direction::INC))) { + delta_seg++; + } } if (from_type == CHANY) { @@ -792,7 +802,6 @@ t_routing_cost_map get_routing_cost_map(int longest_seg_length, //Finally, now that we have a list of sample locations, run a Dijkstra flood from //each sample location to profile the routing network from this type - t_routing_cost_map routing_cost_map({static_cast(device_ctx.grid.get_num_layers()), device_ctx.grid.width(), device_ctx.grid.height()}); if (sample_nodes.empty()) { @@ -1043,8 +1052,7 @@ static void dijkstra_flood_to_wires(int itile, const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(next_node), rr_graph.node_xlow(next_node), rr_graph.node_ylow(next_node)); - } - else { + } else { vib = nullptr; } //const t_vib_inf* vib = device_ctx.vib_grid[rr_graph.node_layer(next_node)][rr_graph.node_xlow(next_node)][rr_graph.node_ylow(next_node)]; @@ -1247,9 +1255,7 @@ static void run_intra_tile_dijkstra(const RRGraphView& rr_graph, node_expanded.resize(rr_graph.num_nodes()); std::fill(node_expanded.begin(), node_expanded.end(), false); - vtr::vector node_seen_cost; - node_seen_cost.resize(rr_graph.num_nodes()); - std::fill(node_seen_cost.begin(), node_seen_cost.end(), -1.); + vtr::vector node_seen_cost(rr_graph.num_nodes(), -1.f); struct t_pq_entry { float delay; @@ -1415,11 +1421,10 @@ static void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(child_node), rr_graph.node_xlow(child_node), rr_graph.node_ylow(child_node)); - } - else { + } else { vib = nullptr; } - + if (!is_inter_cluster_node(physical_type, vib, rr_graph.node_type(child_node), diff --git a/vpr/src/route/router_lookahead_sampling.cpp b/vpr/src/route/router_lookahead_sampling.cpp index c7f2221ff9c..a8ad7dc2f15 100644 --- a/vpr/src/route/router_lookahead_sampling.cpp +++ b/vpr/src/route/router_lookahead_sampling.cpp @@ -60,9 +60,9 @@ static std::vector choose_points(const vtr::Matrix& counts, // sort by distance from center std::stable_sort(points.begin(), points.end(), - [&](const SamplePoint& a, const SamplePoint& b) { - return manhattan_distance(a.location, center) < manhattan_distance(b.location, center); - }); + [&](const SamplePoint& a, const SamplePoint& b) { + return manhattan_distance(a.location, center) < manhattan_distance(b.location, center); + }); return points; } @@ -233,9 +233,9 @@ std::vector find_sample_regions(int num_segments) { // sort regions std::stable_sort(sample_regions.begin(), sample_regions.end(), - [](const SampleRegion& a, const SampleRegion& b) { - return a.order < b.order; - }); + [](const SampleRegion& a, const SampleRegion& b) { + return a.order < b.order; + }); // build an index of sample points on segment type and location std::map, SamplePoint*> sample_point_index; diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 0660c652881..0b38fc692ce 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1,14 +1,14 @@ #include -#include #include -#include #include #include #include +#include "alloc_and_load_rr_indexed_data.h" +#include "physical_types_util.h" +#include "rr_rc_data.h" #include "vtr_assert.h" #include "vtr_util.h" -#include "vtr_memory.h" #include "vtr_math.h" #include "vtr_log.h" #include "vtr_time.h" @@ -21,42 +21,24 @@ #include "rr_graph_utils.h" #include "rr_graph.h" #include "rr_graph_area.h" -#include "rr_graph_utils.h" #include "rr_graph2.h" #include "rr_graph_sbox.h" #include "rr_graph_timing_params.h" -#include "rr_graph_indexed_data.h" #include "check_rr_graph.h" -#include "read_xml_arch_file.h" #include "echo_files.h" -#include "cb_metrics.h" #include "build_switchblocks.h" #include "rr_graph_writer.h" #include "rr_graph_reader.h" -#include "router_lookahead_map.h" #include "rr_graph_clock.h" #include "edge_groups.h" #include "rr_graph_builder.h" #include "tileable_rr_graph_builder.h" #include "rr_types.h" -#include "echo_files.h" //#define VERBOSE //used for getting the exact count of each edge type and printing it to std out. -struct t_mux { - int size; - t_mux* next; -}; - -struct t_mux_size_distribution { - int mux_count; - int max_index; - int* distr; - t_mux_size_distribution* next; -}; - struct t_pin_loc { int pin_index; int width_offset; @@ -65,12 +47,6 @@ struct t_pin_loc { e_side side; }; -struct t_pin_spec { - t_rr_type pin_type; - int pin_ptc; - RRNodeId pin_rr_node_id; -}; - /******************* Variables local to this module. ***********************/ /********************* Subroutines local to this module. *******************/ @@ -108,11 +84,11 @@ bool channel_widths_unchanged(const t_chan_width& current, const t_chan_width& p static vtr::NdMatrix, 5> alloc_and_load_pin_to_track_map(const e_pin_type pin_type, const vtr::Matrix& Fc, const t_physical_tile_type_ptr tile_type, - const std::set type_layer, + const std::set& type_layer, const std::vector& perturb_switch_pattern, const e_directionality directionality, const std::vector& seg_inf, - const int* sets_per_seg_type); + const std::vector& sets_per_seg_type); /** * @brief This routine calculates pin connections to tracks for a specific type and a specific segment based on the Fc value * defined for each pin in the architecture file. This routine is called twice for each combination of block type and segment @@ -146,7 +122,7 @@ static void advance_to_next_block_side(t_physical_tile_type_ptr tile_type, int& static vtr::NdMatrix, 5> alloc_and_load_track_to_pin_lookup(vtr::NdMatrix, 5> pin_to_track_map, const vtr::Matrix& Fc, const t_physical_tile_type_ptr tile_type, - const std::set type_layer, + const std::set& type_layer, const int width, const int height, const int num_pins, @@ -166,7 +142,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder, const t_chan_details& chan_details_y, const DeviceGrid& grid, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs, + const std::vector& clb_to_clb_directs, const int num_seg_types); static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, @@ -186,7 +162,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, bool* Fc_clipped, const t_unified_to_parallel_seg_index& seg_index_map, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs, + const std::vector& clb_to_clb_directs, const int num_seg_types, int& edge_count); @@ -200,7 +176,7 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder, RRNodeId from_rr_node, t_rr_edge_info_set& rr_edges_to_create, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs); + const std::vector& clb_to_clb_directs); static std::function alloc_and_load_rr_graph(RRGraphBuilder& rr_graph_builder, t_rr_graph_storage& L_rr_node, @@ -229,7 +205,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder const enum e_directionality directionality, bool* Fc_clipped, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs, + const std::vector& clb_to_clb_directs, bool is_global_graph, const enum e_clock_modeling clock_modeling, bool is_flat, @@ -322,7 +298,6 @@ static void alloc_and_load_tile_rr_graph(RRGraphBuilder& rr_graph_builder, static float pattern_fmod(float a, float b); - /** * @brief Loads the tracks_connected_to_pin array with an even distribution of switches across the tracks for each pin. * @@ -375,7 +350,7 @@ static void check_all_tracks_reach_pins(t_logical_block_type_ptr type, static std::vector> alloc_and_load_perturb_ipins(const int L_num_types, const int num_seg_types, - const int* sets_per_seg_type, + const std::vector& sets_per_seg_type, const std::vector>& Fc_in, const std::vector>& Fc_out, const enum e_directionality directionality); @@ -529,7 +504,7 @@ static float get_min_delay_to_chain(t_physical_tile_type_ptr physical_type, int pin_physical_num, int chain_sink_pin); -static std::unordered_set get_chain_pins(std::vector chain); +static std::unordered_set get_chain_pins(const std::vector& chain); static void build_rr_chan(RRGraphBuilder& rr_graph_builder, const int layer, @@ -593,8 +568,7 @@ static void alloc_rr_switch_inf(RRGraphBuilder& rr_graph_builder, t_arch_switch_fanin& arch_switch_fanins, const std::map& arch_sw_map); -static t_seg_details* alloc_and_load_global_route_seg_details(const int global_route_switch, - int* num_seg_details = nullptr); +static std::vector alloc_and_load_global_route_seg_details(const int global_route_switch); static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraphView& rr_graph, RRNodeId from_rr, @@ -688,7 +662,7 @@ static float get_delay_directly_connected_pins(t_physical_tile_type_ptr physical static void process_non_config_sets(); -static void build_rr_graph(const t_graph_type graph_type, +static void build_rr_graph(e_graph_type graph_type, const std::vector& types, const DeviceGrid& grid, t_chan_width nodes_per_chan, @@ -711,7 +685,7 @@ static void build_rr_graph(const t_graph_type graph_type, int* Warnings, const int route_verbosity); -static void build_intra_cluster_rr_graph(const t_graph_type graph_type, +static void build_intra_cluster_rr_graph(e_graph_type graph_type, const DeviceGrid& grid, const std::vector& types, const RRGraphView& rr_graph, @@ -728,12 +702,12 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, * @param det_routing_arch Contain the information from architecture file * @param load_rr_graph Indicate whether the RR graph is loaded from a file */ -static int get_delayless_switch_id(t_det_routing_arch* det_routing_arch, - bool load_rr_graph); +static int get_delayless_switch_id(t_det_routing_arch* det_routing_arch, + bool load_rr_graph); /******************* Subroutine definitions *******************************/ -void create_rr_graph(const t_graph_type graph_type, +void create_rr_graph(e_graph_type graph_type, const std::vector& block_types, const DeviceGrid& grid, const t_chan_width& nodes_per_chan, @@ -759,7 +733,7 @@ void create_rr_graph(const t_graph_type graph_type, } } else { if (load_rr_graph) { - if (device_ctx.read_rr_graph_filename != det_routing_arch->read_rr_graph_filename) { + if (device_ctx.loaded_rr_graph_filename != det_routing_arch->read_rr_graph_filename) { free_rr_graph(); load_rr_file(&mutable_device_ctx.rr_graph_builder, @@ -777,7 +751,7 @@ void create_rr_graph(const t_graph_type graph_type, &det_routing_arch->wire_to_rr_ipin_switch, &det_routing_arch->wire_to_arch_ipin_switch_between_dice, det_routing_arch->read_rr_graph_filename.c_str(), - &det_routing_arch->read_rr_graph_filename, + &mutable_device_ctx.loaded_rr_graph_filename, router_opts.read_rr_edge_metadata, router_opts.do_check_rr_graph, echo_enabled, @@ -791,7 +765,7 @@ void create_rr_graph(const t_graph_type graph_type, } } else { free_rr_graph(); - if (GRAPH_UNIDIR_TILEABLE != graph_type) { + if (e_graph_type::UNIDIR_TILEABLE != graph_type) { build_rr_graph(graph_type, block_types, grid, @@ -833,7 +807,7 @@ void create_rr_graph(const t_graph_type graph_type, directs, &det_routing_arch->wire_to_rr_ipin_switch, det_routing_arch->shrink_boundary, /* Shrink to the smallest boundary, no routing wires for empty zone */ - det_routing_arch->perimeter_cb, /* Now I/O or any programmable blocks on perimeter can have full cb access (both cbx and cby) */ + det_routing_arch->perimeter_cb, /* Now I/O or any programmable blocks on perimeter can have full cb access (both cbx and cby) */ router_opts.trim_obs_channels || det_routing_arch->through_channel, /* Allow/Prohibit through tracks across multi-height and multi-width grids */ det_routing_arch->opin2all_sides, /* Allow opin of grid to directly drive routing tracks at all sides of a switch block */ det_routing_arch->concat_wire, /* Allow end-point tracks to be wired to a starting point track on the opposite in a switch block. It means a wire can be continued in the same direction to another wire */ @@ -841,6 +815,18 @@ void create_rr_graph(const t_graph_type graph_type, Warnings); } } + + // Check if there is an edge override file to read and that it is not already loaded. + if (!det_routing_arch->read_rr_edge_override_filename.empty() + && det_routing_arch->read_rr_edge_override_filename != device_ctx.loaded_rr_edge_override_filename) { + + load_rr_edge_delay_overrides(det_routing_arch->read_rr_edge_override_filename, + mutable_device_ctx.rr_graph_builder, + device_ctx.rr_graph); + + // Remember the loaded filename to avoid reloading it before the RR graph is cleared. + mutable_device_ctx.loaded_rr_edge_override_filename = det_routing_arch->read_rr_edge_override_filename; + } } if (is_flat) { @@ -1045,7 +1031,7 @@ bool channel_widths_unchanged(const t_chan_width& current, const t_chan_width& p return true; //Identical } -static void build_rr_graph(const t_graph_type graph_type, +static void build_rr_graph(e_graph_type graph_type, const std::vector& types, const DeviceGrid& grid, t_chan_width nodes_per_chan, @@ -1073,9 +1059,9 @@ static void build_rr_graph(const t_graph_type graph_type, *Warnings = RR_GRAPH_NO_WARN; /* Decode the graph_type */ - bool is_global_graph = ((GRAPH_GLOBAL == graph_type) ? true : false); - bool use_full_seg_groups = ((GRAPH_UNIDIR_TILEABLE == graph_type) ? true : false); - enum e_directionality directionality = ((GRAPH_BIDIR == graph_type) ? BI_DIRECTIONAL : UNI_DIRECTIONAL); + bool is_global_graph = (e_graph_type::GLOBAL == graph_type); + bool use_full_seg_groups = (e_graph_type::UNIDIR_TILEABLE == graph_type); + enum e_directionality directionality = (e_graph_type::BIDIR == graph_type) ? BI_DIRECTIONAL : UNI_DIRECTIONAL; if (is_global_graph) { directionality = BI_DIRECTIONAL; } @@ -1091,32 +1077,26 @@ static void build_rr_graph(const t_graph_type graph_type, auto& device_ctx = g_vpr_ctx.mutable_device(); const auto& rr_graph = device_ctx.rr_graph; - t_clb_to_clb_directs* clb_to_clb_directs = nullptr; - if (!directs.empty()) { - clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, delayless_switch); - } + std::vector clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, delayless_switch); /* START SEG_DETAILS */ - size_t num_segments = segment_inf.size(); + const size_t num_segments = segment_inf.size(); device_ctx.rr_graph_builder.reserve_segments(num_segments); for (size_t iseg = 0; iseg < num_segments; ++iseg) { device_ctx.rr_graph_builder.add_rr_segment(segment_inf[iseg]); } - int num_seg_details_x = 0; - int num_seg_details_y = 0; - - t_seg_details* seg_details_x = nullptr; - t_seg_details* seg_details_y = nullptr; - t_unified_to_parallel_seg_index segment_index_map; std::vector segment_inf_x = get_parallel_segs(segment_inf, segment_index_map, X_AXIS); std::vector segment_inf_y = get_parallel_segs(segment_inf, segment_index_map, Y_AXIS); + std::vector seg_details_x; + std::vector seg_details_y; + if (is_global_graph) { /* Sets up a single unit length segment type for global routing. */ - seg_details_x = alloc_and_load_global_route_seg_details(global_route_switch, &num_seg_details_x); - seg_details_y = alloc_and_load_global_route_seg_details(global_route_switch, &num_seg_details_y); + seg_details_x = alloc_and_load_global_route_seg_details(global_route_switch); + seg_details_y = alloc_and_load_global_route_seg_details(global_route_switch); } else { /* Setup segments including distributing tracks and staggering. @@ -1131,13 +1111,11 @@ static void build_rr_graph(const t_graph_type graph_type, /*Get x & y segments separately*/ seg_details_x = alloc_and_load_seg_details(&max_chan_width_x, max_dim, segment_inf_x, - use_full_seg_groups, directionality, - &num_seg_details_x); + use_full_seg_groups, directionality); seg_details_y = alloc_and_load_seg_details(&max_chan_width_y, max_dim, segment_inf_y, - use_full_seg_groups, directionality, - &num_seg_details_y); + use_full_seg_groups, directionality); if (nodes_per_chan.x_max != max_chan_width_x || nodes_per_chan.y_max != max_chan_width_y) { nodes_per_chan.x_max = max_chan_width_x; @@ -1166,8 +1144,7 @@ static void build_rr_graph(const t_graph_type graph_type, t_chan_details chan_details_x; t_chan_details chan_details_y; - alloc_and_load_chan_details(grid, &nodes_per_chan, - num_seg_details_x, num_seg_details_y, + alloc_and_load_chan_details(grid, nodes_per_chan, seg_details_x, seg_details_y, chan_details_x, chan_details_y); @@ -1205,14 +1182,9 @@ static void build_rr_graph(const t_graph_type graph_type, total_sets_x /= 2; total_sets_y /= 2; } - auto sets_per_seg_type_x = get_seg_track_counts(total_sets_x, segment_inf_x, use_full_seg_groups); - auto sets_per_seg_type_y = get_seg_track_counts(total_sets_y, segment_inf_y, use_full_seg_groups); - auto sets_per_seg_type = get_seg_track_counts(total_sets, segment_inf, use_full_seg_groups); - - auto sets_test = get_ordered_seg_track_counts(segment_inf_x, segment_inf_y, segment_inf, sets_per_seg_type_x, sets_per_seg_type_y); - - //VTR_ASSERT_MSG(sets_test==sets_per_seg_type, - // "Not equal combined output after combining segs " ); + std::vector sets_per_seg_type_x = get_seg_track_counts(total_sets_x, segment_inf_x, use_full_seg_groups); + std::vector sets_per_seg_type_y = get_seg_track_counts(total_sets_y, segment_inf_y, use_full_seg_groups); + std::vector sets_per_seg_type = get_seg_track_counts(total_sets, segment_inf, use_full_seg_groups); if (is_global_graph) { //All pins can connect during global routing @@ -1221,19 +1193,19 @@ static void build_rr_graph(const t_graph_type graph_type, Fc_out = std::vector>(types.size(), ones); } else { bool Fc_clipped = false; - Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type.get(), &nodes_per_chan, + Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, &nodes_per_chan, e_fc_type::IN, directionality, &Fc_clipped, is_flat); if (Fc_clipped) { *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; } Fc_clipped = false; - Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type.get(), &nodes_per_chan, + Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, &nodes_per_chan, e_fc_type::OUT, directionality, &Fc_clipped, is_flat); if (Fc_clipped) { *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; } - for (const auto& type : types) { + for (const t_physical_tile_type& type : types) { int i = type.index; /* Skip "EMPTY" */ @@ -1263,7 +1235,7 @@ static void build_rr_graph(const t_graph_type graph_type, } auto perturb_ipins = alloc_and_load_perturb_ipins(types.size(), segment_inf.size(), - sets_per_seg_type.get(), Fc_in, Fc_out, directionality); + sets_per_seg_type, Fc_in, Fc_out, directionality); /* END FC */ /* Alloc node lookups, count nodes, alloc rr nodes */ @@ -1335,10 +1307,10 @@ static void build_rr_graph(const t_graph_type graph_type, /* it looks like we get unbalanced muxing from this switch block code with Fs > 3 */ VTR_ASSERT(Fs == 3); - unidir_sb_pattern = alloc_sblock_pattern_lookup(grid, &nodes_per_chan); + unidir_sb_pattern = alloc_sblock_pattern_lookup(grid, nodes_per_chan); for (size_t i = 0; i < grid.width() - 1; i++) { for (size_t j = 0; j < grid.height() - 1; j++) { - load_sblock_pattern_lookup(i, j, grid, &nodes_per_chan, + load_sblock_pattern_lookup(i, j, grid, nodes_per_chan, chan_details_x, chan_details_y, Fs, sb_type, unidir_sb_pattern); } @@ -1358,7 +1330,7 @@ static void build_rr_graph(const t_graph_type graph_type, */ if (grid.get_num_layers() > 1 && sb_type == CUSTOM) { //keep how many nodes each switchblock requires for each x,y location - auto extra_nodes_per_switchblock = get_number_track_to_track_inter_die_conn(sb_conn_map,custom_3d_sb_fanin_fanout, device_ctx.rr_graph_builder); + auto extra_nodes_per_switchblock = get_number_track_to_track_inter_die_conn(sb_conn_map, custom_3d_sb_fanin_fanout, device_ctx.rr_graph_builder); //allocate new nodes in each switchblocks alloc_and_load_inter_die_rr_node_indices(device_ctx.rr_graph_builder, &nodes_per_chan, grid, extra_nodes_per_switchblock, &num_rr_nodes); device_ctx.rr_graph_builder.resize_nodes(num_rr_nodes); @@ -1380,12 +1352,12 @@ static void build_rr_graph(const t_graph_type graph_type, ipin_to_track_map_x[itype] = alloc_and_load_pin_to_track_map(RECEIVER, Fc_in[itype], &types[itype], type_layer, perturb_ipins[itype], directionality, - segment_inf_x, sets_per_seg_type_x.get()); + segment_inf_x, sets_per_seg_type_x); ipin_to_track_map_y[itype] = alloc_and_load_pin_to_track_map(RECEIVER, Fc_in[itype], &types[itype], type_layer, perturb_ipins[itype], directionality, - segment_inf_y, sets_per_seg_type_y.get()); + segment_inf_y, sets_per_seg_type_y); track_to_pin_lookup_x[itype] = alloc_and_load_track_to_pin_lookup(ipin_to_track_map_x[itype], Fc_in[itype], &types[itype], @@ -1422,7 +1394,7 @@ static void build_rr_graph(const t_graph_type graph_type, max_chan_width, segment_inf); opin_to_track_map[itype] = alloc_and_load_pin_to_track_map(DRIVER, Fc_out[itype], &types[itype], type_layer, perturb_opins, directionality, - segment_inf, sets_per_seg_type.get()); + segment_inf, sets_per_seg_type); } } /* END OPIN MAP */ @@ -1469,16 +1441,16 @@ static void build_rr_graph(const t_graph_type graph_type, route_verbosity); // Verify no incremental node allocation. - // AA: Note that in the case of dedicated networks, we are currently underestimating the additional node count due to the clock networks. + // AA: Note that in the case of dedicated networks, we are currently underestimating the additional node count due to the clock networks. /* For now, the node count comparison is being skipped in the presence of clock networks. - * TODO: The node estimation needs to be fixed for dedicated clock networks. */ + * TODO: The node estimation needs to be fixed for dedicated clock networks. */ if (rr_graph.num_nodes() > expected_node_count && clock_modeling != DEDICATED_NETWORK) { VTR_LOG_ERROR("Expected no more than %zu nodes, have %zu nodes\n", expected_node_count, rr_graph.num_nodes()); } /* Update rr_nodes capacities if global routing */ - if (graph_type == GRAPH_GLOBAL) { + if (graph_type == e_graph_type::GLOBAL) { // Using num_rr_nodes here over device_ctx.rr_nodes.size() because // clock_modeling::DEDICATED_NETWORK will append some rr nodes after // the regular graph. @@ -1495,7 +1467,7 @@ static void build_rr_graph(const t_graph_type graph_type, } /*Update rr_nodes ptc_twist_incr number if we are creating tileable graph*/ - if (graph_type == GRAPH_UNIDIR_TILEABLE) { + if (graph_type == e_graph_type::UNIDIR_TILEABLE) { device_ctx.rr_graph_builder.resize_ptc_twist_incr(num_rr_nodes); for (int rr_node_id = 0; rr_node_id < num_rr_nodes; rr_node_id++) { auto node_type = rr_graph.node_type(RRNodeId(rr_node_id)); @@ -1534,7 +1506,7 @@ static void build_rr_graph(const t_graph_type graph_type, device_ctx.chan_width = nodes_per_chan; rr_graph_externals(segment_inf, segment_inf_x, segment_inf_y, *wire_to_rr_ipin_switch, base_cost_type); - + const VibDeviceGrid vib_grid; check_rr_graph(device_ctx.rr_graph, types, @@ -1545,34 +1517,17 @@ static void build_rr_graph(const t_graph_type graph_type, graph_type, is_flat); - /* Free all temp structs */ - delete[] seg_details_x; - delete[] seg_details_y; - - seg_details_x = nullptr; - seg_details_y = nullptr; - if (!chan_details_x.empty() || !chan_details_y.empty()) { - free_chan_details(chan_details_x, chan_details_y); - } - if (sb_conn_map) { free_switchblock_permutations(sb_conn_map); sb_conn_map = nullptr; } - track_to_pin_lookup_x.clear(); - track_to_pin_lookup_y.clear(); - - if (clb_to_clb_directs != nullptr) { - delete[] clb_to_clb_directs; - } - // We are done with building the RR Graph. Thus, we can clear the storages only used // to build the RR Graph device_ctx.rr_graph_builder.clear_temp_storage(); } -static void build_intra_cluster_rr_graph(const t_graph_type graph_type, +static void build_intra_cluster_rr_graph(e_graph_type graph_type, const DeviceGrid& grid, const std::vector& types, const RRGraphView& rr_graph, @@ -1643,12 +1598,12 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, } static int get_delayless_switch_id(t_det_routing_arch* det_routing_arch, - bool load_rr_graph) { + bool load_rr_graph) { const auto& device_ctx = g_vpr_ctx.device(); int delayless_switch = OPEN; if (load_rr_graph) { const auto& rr_switches = device_ctx.rr_graph.rr_switch(); - for (size_t switch_id = 0; switch_id < rr_switches.size(); switch_id++){ + for (size_t switch_id = 0; switch_id < rr_switches.size(); switch_id++) { const auto& rr_switch = rr_switches[RRSwitchId(switch_id)]; if (rr_switch.name.find("delayless") != std::string::npos) { delayless_switch = static_cast(switch_id); @@ -1925,7 +1880,7 @@ void rr_graph_externals(const std::vector& segment_inf, static std::vector> alloc_and_load_perturb_ipins(const int L_num_types, const int num_seg_types, - const int* sets_per_seg_type, + const std::vector& sets_per_seg_type, const std::vector>& Fc_in, const std::vector>& Fc_out, const enum e_directionality directionality) { @@ -1976,33 +1931,27 @@ static std::vector> alloc_and_load_perturb_ipins(const int L_n return result; } -static t_seg_details* alloc_and_load_global_route_seg_details(const int global_route_switch, - int* num_seg_details) { - t_seg_details* seg_details = new t_seg_details[1]; - - seg_details->index = 0; - seg_details->abs_index = 0; - seg_details->length = 1; - seg_details->arch_wire_switch = global_route_switch; - seg_details->arch_opin_switch = global_route_switch; - seg_details->longline = false; - seg_details->direction = Direction::BIDIR; - seg_details->Cmetal = 0.0; - seg_details->Rmetal = 0.0; - seg_details->start = 1; - seg_details->cb = std::make_unique(1); - seg_details->cb[0] = true; - seg_details->sb = std::make_unique(2); - seg_details->sb[0] = true; - seg_details->sb[1] = true; - seg_details->group_size = 1; - seg_details->group_start = 0; - seg_details->seg_start = -1; - seg_details->seg_end = -1; - - if (num_seg_details) { - *num_seg_details = 1; - } +static std::vector alloc_and_load_global_route_seg_details(const int global_route_switch) { + std::vector seg_details(1); + + seg_details[0].index = 0; + seg_details[0].abs_index = 0; + seg_details[0].length = 1; + seg_details[0].arch_wire_switch = global_route_switch; + seg_details[0].arch_opin_switch = global_route_switch; + seg_details[0].longline = false; + seg_details[0].direction = Direction::BIDIR; + seg_details[0].Cmetal = 0.0; + seg_details[0].Rmetal = 0.0; + seg_details[0].start = 1; + seg_details[0].cb = std::make_unique(1); + seg_details[0].cb[0] = true; + seg_details[0].sb = std::make_unique(2); + seg_details[0].sb[0] = true; + seg_details[0].sb[1] = true; + seg_details[0].group_size = 1; + seg_details[0].group_start = 0; + return seg_details; } @@ -2010,7 +1959,7 @@ static t_seg_details* alloc_and_load_global_route_seg_details(const int global_r std::vector> alloc_and_load_actual_fc(const std::vector& types, const int max_pins, const std::vector& segment_inf, - const int* sets_per_seg_type, + const std::vector& sets_per_seg_type, const t_chan_width* nodes_per_chan, const e_fc_type fc_type, const enum e_directionality directionality, @@ -2030,7 +1979,7 @@ std::vector> alloc_and_load_actual_fc(const std::vectorx_max % fac) == 0 && (nodes_per_chan->y_max % fac) == 0); - for (const auto& type : types) { //Skip EMPTY + for (const t_physical_tile_type& type : types) { //Skip EMPTY int itype = type.index; for (const t_fc_specification& fc_spec : type.fc_specs) { @@ -2048,7 +1997,7 @@ std::vector> alloc_and_load_actual_fc(const std::vector alloc_and_load_rr_graph(RRGraphBuilder const enum e_directionality directionality, bool* Fc_clipped, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs, + const std::vector& clb_to_clb_directs, bool is_global_graph, const enum e_clock_modeling clock_modeling, bool /*is_flat*/, @@ -2173,7 +2122,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder *Fc_clipped = false; /* This function is called to build the general routing graph resoruces. Thus, - the edges are not remapped yet.*/ + * the edges are not remapped yet.*/ bool switches_remapped = false; int num_edges = 0; @@ -2221,7 +2170,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder } } - VTR_LOGV(route_verbosity > 1,"SOURCE->OPIN and IPIN->SINK edge count:%d\n", num_edges); + VTR_LOGV(route_verbosity > 1, "SOURCE->OPIN and IPIN->SINK edge count:%d\n", num_edges); num_edges = 0; /* Build opins */ int rr_edges_before_directs = 0; @@ -2258,8 +2207,8 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder } } - VTR_LOGV(route_verbosity > 1,"OPIN->CHANX/CHANY edge count before creating direct connections: %d\n", rr_edges_before_directs); - VTR_LOGV(route_verbosity > 1,"OPIN->CHANX/CHANY edge count after creating direct connections: %d\n", num_edges); + VTR_LOGV(route_verbosity > 1, "OPIN->CHANX/CHANY edge count before creating direct connections: %d\n", rr_edges_before_directs); + VTR_LOGV(route_verbosity > 1, "OPIN->CHANX/CHANY edge count after creating direct connections: %d\n", num_edges); num_edges = 0; /* Build channels */ @@ -2269,14 +2218,14 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder vtr::NdMatrix num_of_3d_conns_custom_SB; t_rr_edge_info_set des_3d_rr_edges_to_create; - if(grid.get_num_layers() > 1 && sb_conn_map != nullptr){ - num_of_3d_conns_custom_SB.resize(std::array{grid.width(), grid.height()}, 0); + if (grid.get_num_layers() > 1 && sb_conn_map != nullptr) { + num_of_3d_conns_custom_SB.resize(std::array{grid.width(), grid.height()}, 0); } for (size_t i = 0; i < grid.width() - 1; ++i) { for (size_t j = 0; j < grid.height() - 1; ++j) { for (int layer = 0; layer < grid.get_num_layers(); ++layer) { - auto &device_ctx = g_vpr_ctx.device(); + auto& device_ctx = g_vpr_ctx.device(); /* Skip the current die if architecture file specifies that it doesn't require inter-cluster programmable resource routing */ if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { continue; @@ -2338,15 +2287,14 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder } } - if(grid.get_num_layers() > 1 && sb_conn_map != nullptr){ + if (grid.get_num_layers() > 1 && sb_conn_map != nullptr) { uniquify_edges(des_3d_rr_edges_to_create); alloc_and_load_edges(rr_graph_builder, des_3d_rr_edges_to_create); num_edges += des_3d_rr_edges_to_create.size(); des_3d_rr_edges_to_create.clear(); } - - VTR_LOGV(route_verbosity > 1,"CHAN->CHAN type edge count:%d\n", num_edges); + VTR_LOGV(route_verbosity > 1, "CHAN->CHAN type edge count:%d\n", num_edges); num_edges = 0; std::function update_chan_width = [](t_chan_width*) noexcept {}; @@ -2733,7 +2681,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder, const t_chan_details& chan_details_y, const DeviceGrid& grid, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs, + const std::vector& clb_to_clb_directs, const int num_seg_types) { //Don't connect pins which are not adjacent to channels around the perimeter if ((i == 0 && side != RIGHT) @@ -2796,7 +2744,8 @@ void free_rr_graph() { * allocated, as ALL the chunk allocated data is already free! */ auto& device_ctx = g_vpr_ctx.mutable_device(); - device_ctx.read_rr_graph_filename.clear(); + device_ctx.loaded_rr_graph_filename.clear(); + device_ctx.loaded_rr_edge_override_filename.clear(); device_ctx.rr_graph_builder.clear(); @@ -2959,11 +2908,11 @@ static void add_pb_edges(RRGraphBuilder& rr_graph_builder, float delay = g_vpr_ctx.device().all_sw_inf.at(sw_idx).Tdel(); bool is_new_sw; std::tie(is_new_sw, sw_idx) = find_create_intra_cluster_sw(rr_graph_builder, - all_sw_inf, - R_minW_nmos, - R_minW_pmos, - switches_remapped, - delay); + all_sw_inf, + R_minW_nmos, + R_minW_pmos, + switches_remapped, + delay); } rr_edges_to_create.emplace_back(parent_pin_node_id, conn_pin_node_id, sw_idx, switches_remapped); } @@ -3170,7 +3119,7 @@ static float get_min_delay_to_chain(t_physical_tile_type_ptr physical_type, return min_delay; } -static std::unordered_set get_chain_pins(std::vector chain) { +static std::unordered_set get_chain_pins(const std::vector& chain) { std::unordered_set chain_pins; for (auto node : chain) { chain_pins.insert(node.pin_physical_num); @@ -3282,10 +3231,10 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, } if (to_seg_details->length() > 0) { get_track_to_tracks(rr_graph_builder, layer, chan_coord, start, track, chan_type, chan_coord, - opposite_chan_type, seg_dimension, max_opposite_chan_width, grid, + opposite_chan_type, seg_dimension, max_opposite_chan_width, grid, Fs_per_side, sblock_pattern, num_of_3d_conns_custom_SB, node, rr_edges_to_create, des_3d_rr_edges_to_create, from_seg_details, to_seg_details, opposite_chan_details, - directionality,custom_3d_sb_fanin_fanout,delayless_switch, + directionality, custom_3d_sb_fanin_fanout, delayless_switch, switch_block_conn, sb_conn_map); } } @@ -3302,10 +3251,10 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, } if (to_seg_details->length() > 0) { get_track_to_tracks(rr_graph_builder, layer, chan_coord, start, track, chan_type, chan_coord + 1, - opposite_chan_type, seg_dimension, max_opposite_chan_width, grid, + opposite_chan_type, seg_dimension, max_opposite_chan_width, grid, Fs_per_side, sblock_pattern, num_of_3d_conns_custom_SB, node, rr_edges_to_create, des_3d_rr_edges_to_create, from_seg_details, to_seg_details, opposite_chan_details, - directionality,custom_3d_sb_fanin_fanout, delayless_switch, switch_block_conn, sb_conn_map); + directionality, custom_3d_sb_fanin_fanout, delayless_switch, switch_block_conn, sb_conn_map); } } @@ -3334,10 +3283,10 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, } if (to_seg_details->length() > 0) { get_track_to_tracks(rr_graph_builder, layer, chan_coord, start, track, chan_type, target_seg, - chan_type, seg_dimension, max_chan_width, grid, + chan_type, seg_dimension, max_chan_width, grid, Fs_per_side, sblock_pattern, num_of_3d_conns_custom_SB, node, rr_edges_to_create, des_3d_rr_edges_to_create, from_seg_details, to_seg_details, from_chan_details, - directionality,custom_3d_sb_fanin_fanout, delayless_switch, + directionality, custom_3d_sb_fanin_fanout, delayless_switch, switch_block_conn, sb_conn_map); } } @@ -3435,18 +3384,18 @@ void alloc_and_load_edges(RRGraphBuilder& rr_graph_builder, const t_rr_edge_info static vtr::NdMatrix, 5> alloc_and_load_pin_to_track_map(const e_pin_type pin_type, const vtr::Matrix& Fc, const t_physical_tile_type_ptr tile_type, - const std::set type_layer, + const std::set& type_layer, const std::vector& perturb_switch_pattern, const e_directionality directionality, const std::vector& seg_inf, - const int* sets_per_seg_type) { + const std::vector& sets_per_seg_type) { /* allocate 'result' matrix and initialize entries to OPEN. also allocate and intialize matrix which will be * used to index into the correct entries when loading up 'result' */ auto& grid = g_vpr_ctx.device().grid; auto result = vtr::NdMatrix, 5>({ - size_t(tile_type->num_pins), //[0..num_pins-1] - size_t(tile_type->width), //[0..width-1] - size_t(tile_type->height), //[0..height-1] + size_t(tile_type->num_pins), //[0..num_pins-1] + size_t(tile_type->width), //[0..width-1] + size_t(tile_type->height), //[0..height-1] size_t(grid.get_num_layers()), //[0..layer-1] 4, //[0..sides-1] }); @@ -3536,12 +3485,12 @@ static vtr::NdMatrix alloc_and_load_pin_to_seg_type(const e_pin_type pin } auto tracks_connected_to_pin = vtr::NdMatrix({ - size_t(tile_type->num_pins), //[0..num_pins-1] - size_t(tile_type->width), //[0..width-1] - size_t(tile_type->height), //[0..height-1] + size_t(tile_type->num_pins), //[0..num_pins-1] + size_t(tile_type->width), //[0..width-1] + size_t(tile_type->height), //[0..height-1] size_t(grid.get_num_layers()), //[0..layer-1] NUM_2D_SIDES, //[0..NUM_2D_SIDES-1] - size_t(max_Fc) //[0..Fc-1] + size_t(max_Fc) //[0..Fc-1] }, OPEN); //Unconnected @@ -3550,8 +3499,8 @@ static vtr::NdMatrix alloc_and_load_pin_to_seg_type(const e_pin_type pin //Type->num_pins) if a logical pin has multiple specified physical //pinlocations (i.e. appears on multiple sides of the block) auto num_dir = vtr::NdMatrix({ - size_t(tile_type->width), //[0..width-1] - size_t(tile_type->height), //[0..height-1] + size_t(tile_type->width), //[0..width-1] + size_t(tile_type->height), //[0..height-1] size_t(grid.get_num_layers()), //[0..layer-1] NUM_2D_SIDES //[0..NUM_2D_SIDES-1] }, @@ -3565,16 +3514,16 @@ static vtr::NdMatrix alloc_and_load_pin_to_seg_type(const e_pin_type pin auto dir_list = vtr::NdMatrix({ size_t(tile_type->width), //[0..width-1] size_t(tile_type->height), //[0..height-1] - size_t(grid.get_num_layers()), //[0..layer-1] - NUM_2D_SIDES, //[0..NUM_2D_SIDES-1] + size_t(grid.get_num_layers()), //[0..layer-1] + NUM_2D_SIDES, //[0..NUM_2D_SIDES-1] size_t(tile_type->num_pins) * size_t(grid.get_num_layers()) //[0..num_pins * num_layers-1] }, -1); //Defensive coding: Initialize to invalid //Number of currently assigned physical pins auto num_done_per_dir = vtr::NdMatrix({ - size_t(tile_type->width), //[0..width-1] - size_t(tile_type->height), //[0..height-1] + size_t(tile_type->width), //[0..width-1] + size_t(tile_type->height), //[0..height-1] size_t(grid.get_num_layers()), //[0..layer-1] NUM_2D_SIDES //[0..NUM_2D_SIDES-1] }, @@ -4068,7 +4017,7 @@ static void load_perturbed_connection_block_pattern(vtr::NdMatrix& track int layer = pin_locations[i].layer_offset; int pin_Fc = Fc[pin][seg_index]; - int Fc_dense = ( pin_Fc / 2) + 1; + int Fc_dense = (pin_Fc / 2) + 1; int Fc_sparse = pin_Fc - Fc_dense; int Fc_half[2]; @@ -4146,7 +4095,7 @@ static void check_all_tracks_reach_pins(t_logical_block_type_ptr type, static vtr::NdMatrix, 5> alloc_and_load_track_to_pin_lookup(vtr::NdMatrix, 5> pin_to_track_map, const vtr::Matrix& Fc, const t_physical_tile_type_ptr tile_type, - const std::set type_layer, + const std::set& type_layer, const int type_width, const int type_height, const int num_pins, @@ -4235,7 +4184,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, bool* Fc_clipped, const t_unified_to_parallel_seg_index& seg_index_map, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs, + const std::vector& clb_to_clb_directs, const int num_seg_types, int& rr_edge_count) { /* @@ -4344,21 +4293,18 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, * This data structure supplements the the info in the "directs" data structure * TODO: The function that does this parsing in placement is poorly done because it lacks generality on heterogeniety, should replace with this one */ -t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, int delayless_switch) { - t_clb_to_clb_directs* clb_to_clb_directs; - t_physical_tile_type_ptr physical_tile = nullptr; - t_physical_tile_port tile_port; +std::vector alloc_and_load_clb_to_clb_directs(const std::vector& directs, int delayless_switch) { auto& device_ctx = g_vpr_ctx.device(); const int num_directs = directs.size(); - clb_to_clb_directs = new t_clb_to_clb_directs[num_directs]; + std::vector clb_to_clb_directs(num_directs); for (int i = 0; i < num_directs; i++) { //clb_to_clb_directs[i].from_clb_type; clb_to_clb_directs[i].from_clb_pin_start_index = 0; clb_to_clb_directs[i].from_clb_pin_end_index = 0; - //clb_to_clb_directs[i]. t_physical_tile_type_ptr to_clb_type; + //clb_to_clb_directs[i].to_clb_type; clb_to_clb_directs[i].to_clb_pin_start_index = 0; clb_to_clb_directs[i].to_clb_pin_end_index = 0; clb_to_clb_directs[i].switch_index = 0; @@ -4367,20 +4313,15 @@ t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs) { + const std::vector& clb_to_clb_directs) { auto& device_ctx = g_vpr_ctx.device(); t_physical_tile_type_ptr curr_type = device_ctx.grid.get_physical_type({x, y, layer}); @@ -5135,15 +5069,15 @@ static std::pair find_create_intra_cluster_sw(RRGraphBuilder& rr_grap // If this assumption proven to not be accurate, the implementation needs to be changed. VTR_ASSERT(arch_sw.fixed_Tdel()); - t_rr_switch_inf new_rr_switch_inf = create_rr_switch_from_arch_switch(create_internal_arch_sw(delay), - R_minW_nmos, - R_minW_pmos); + t_rr_switch_inf new_rr_switch_inf = create_rr_switch_from_arch_switch(create_internal_arch_sw(delay), + R_minW_nmos, + R_minW_pmos); RRSwitchId rr_switch_id = rr_graph.add_rr_switch(new_rr_switch_inf); /*If the switch found inside the cluster has not seen before and RR graph is not read from a file, - we need to add this switch to switch_fanin_remap data strcutre which is used later to remap switch IDs - from architecture ID to RR graph switch ID. The reason why we don't this when RR graph is read from a file - is that in that case, the switch IDs of edges are alreay RR graph switch IDs. */ + * we need to add this switch to switch_fanin_remap data strcutre which is used later to remap switch IDs + * from architecture ID to RR graph switch ID. The reason why we don't this when RR graph is read from a file + * is that in that case, the switch IDs of edges are alreay RR graph switch IDs. */ auto& switch_fanin_remap = g_vpr_ctx.mutable_device().switch_fanin_remap; switch_fanin_remap.push_back({{UNDEFINED, size_t(rr_switch_id)}}); diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index 0d074f95bb8..b92db8005ea 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -21,7 +21,7 @@ enum { RR_GRAPH_WARN_CHAN_Y_WIDTH_CHANGED = 0x03 }; -void create_rr_graph(const t_graph_type graph_type, +void create_rr_graph(e_graph_type graph_type, const std::vector& block_types, const DeviceGrid& grid, const t_chan_width& nodes_per_chan, @@ -62,12 +62,12 @@ void rr_graph_externals(const std::vector& segment_inf, int wire_to_rr_ipin_switch, enum e_base_cost_type base_cost_type); -t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, const int delayless_switch); +std::vector alloc_and_load_clb_to_clb_directs(const std::vector& directs, const int delayless_switch); std::vector> alloc_and_load_actual_fc(const std::vector& types, const int max_pins, const std::vector& segment_inf, - const int* sets_per_seg_type, + const std::vector& sets_per_seg_type, const t_chan_width* nodes_per_chan, const e_fc_type fc_type, const enum e_directionality directionality, diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index cb8b729b05f..81763f8cdb6 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1,9 +1,9 @@ #include +#include "describe_rr_node.h" +#include "physical_types_util.h" #include "vtr_util.h" #include "vtr_assert.h" -#include "vtr_log.h" -#include "vtr_memory.h" #include "vpr_types.h" #include "vpr_error.h" @@ -11,9 +11,7 @@ #include "globals.h" #include "rr_graph_utils.h" #include "rr_graph2.h" -#include "rr_graph.h" #include "rr_graph_sbox.h" -#include "read_xml_arch_file.h" #include "rr_types.h" constexpr short UN_SET = -1; @@ -257,56 +255,35 @@ static bool should_apply_switch_override(int switch_override); /******************** Subroutine definitions *******************************/ -/* This assigns tracks (individually or pairs) to segment types. - * It tries to match requested ratio. If use_full_seg_groups is - * true, then segments are assigned only in multiples of their - * length. This is primarily used for making a tileable unidir - * layout. The effect of using this is that the number of tracks - * requested will not always be met and the result will sometimes - * be over and sometimes under. - * The pattern when using use_full_seg_groups is to keep adding - * one group of the track type that wants the largest number of - * groups of tracks. Each time a group is assigned, the types - * demand is reduced by 1 unit. The process stops when we are - * no longer less than the requested number of tracks. As a final - * step, if we were closer to target before last more, undo it - * and end up with a result that uses fewer tracks than given. */ -std::unique_ptr get_seg_track_counts(const int num_sets, - const std::vector& segment_inf, - const bool use_full_seg_groups) { - std::unique_ptr result; - int imax, freq_sum, assigned, size; - double scale, max, reduce; - - result = std::make_unique(segment_inf.size()); - std::vector demand(segment_inf.size()); - - /* Scale factor so we can divide by any length - * and still use integers */ - scale = 1; - freq_sum = 0; +std::vector get_seg_track_counts(int num_sets, + const std::vector& segment_inf, + bool use_full_seg_groups) { + // Scale factor so we can divide by any length and still use integers + double scale = 1; + int freq_sum = 0; for (size_t i = 0; i < segment_inf.size(); ++i) { scale *= segment_inf[i].length; freq_sum += segment_inf[i].frequency; } - reduce = scale * freq_sum; + const double reduce = scale * freq_sum; - /* Init assignments to 0 and set the demand values */ + // Init assignments to 0 and set the demand values + std::vector result(segment_inf.size(), 0); + std::vector demand(segment_inf.size()); for (size_t i = 0; i < segment_inf.size(); ++i) { - result[i] = 0; demand[i] = scale * num_sets * segment_inf[i].frequency; if (use_full_seg_groups) { demand[i] /= segment_inf[i].length; } } - /* Keep assigning tracks until we use them up */ - assigned = 0; - size = 0; - imax = 0; + // Keep assigning tracks until we use them up + int assigned = 0; + int imax = 0; + int size = 0; while (assigned < num_sets) { - /* Find current maximum demand */ - max = 0; + // Find current maximum demand + double max = 0; for (size_t i = 0; i < segment_inf.size(); ++i) { if (demand[i] > max) { imax = i; @@ -314,19 +291,18 @@ std::unique_ptr get_seg_track_counts(const int num_sets, } } - /* Assign tracks to the type and reduce the types demand */ - size = (use_full_seg_groups ? segment_inf[imax].length : 1); + // Assign tracks to the type and reduce the types demand + size = use_full_seg_groups ? segment_inf[imax].length : 1; demand[imax] -= reduce; result[imax] += size; assigned += size; } - /* Undo last assignment if we were closer to goal without it */ + // Undo last assignment if we were closer to goal without it if ((assigned - num_sets) > (size / 2)) { result[imax] -= size; } - /* This must be freed by caller */ return result; } @@ -345,53 +321,11 @@ int get_parallel_seg_index(const int abs_index, return index; } -/* Returns an array of tracks per segment, with matching indices to segment_inf by combining * - * sets per segment for each direction. This is a helper function to avoid having to refactor * - * alot of the functions inside rr_graph.cpp & rr_graph2.cpp to model different horizontal and vertical * - * channel widths. */ -std::unique_ptr get_ordered_seg_track_counts(const std::vector& segment_inf_x, - const std::vector& segment_inf_y, - const std::vector& segment_inf, - const std::unique_ptr& segment_sets_x, - const std::unique_ptr& segment_sets_y) { - std::unordered_map all_segs_index; - std::unique_ptr ordered_seg_track_counts; - ordered_seg_track_counts = std::make_unique(segment_inf.size()); - - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - all_segs_index.insert(std::make_pair(segment_inf[iseg], iseg)); - } - for (size_t iseg_x = 0; iseg_x < segment_inf_x.size(); ++iseg_x) { - auto seg_in_x_dir = all_segs_index.find(segment_inf_x[iseg_x]); - if (seg_in_x_dir != all_segs_index.end()) { - ordered_seg_track_counts[seg_in_x_dir->second] = segment_sets_x[iseg_x]; - } else { - VTR_ASSERT_MSG(seg_in_x_dir != all_segs_index.end(), - "Segment in the x-direction must be a part of all segments."); - } - } - for (size_t iseg_y = 0; iseg_y < segment_inf_y.size(); ++iseg_y) { - if (segment_inf_y[iseg_y].parallel_axis == BOTH_AXIS) { /*Avoid counting segments in both horizontal and vertical direction twice*/ - continue; - } - auto seg_in_y_dir = all_segs_index.find(segment_inf_y[iseg_y]); - if (seg_in_y_dir != all_segs_index.end()) { - ordered_seg_track_counts[seg_in_y_dir->second] = segment_sets_y[iseg_y]; - } else { - VTR_ASSERT_MSG(seg_in_y_dir != all_segs_index.end(), - "Segment in the x-direction must be a part of all segments."); - } - } - - return ordered_seg_track_counts; -} - -t_seg_details* alloc_and_load_seg_details(int* max_chan_width, - const int max_len, - const std::vector& segment_inf, - const bool use_full_seg_groups, - const enum e_directionality directionality, - int* num_seg_details) { +std::vector alloc_and_load_seg_details(int* max_chan_width, + const int max_len, + const std::vector& segment_inf, + const bool use_full_seg_groups, + const enum e_directionality directionality) { /* Allocates and loads the seg_details data structure. Max_len gives the * * maximum length of a segment (dimension of array). The code below tries * * to: * @@ -401,16 +335,8 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, * (3) stagger the connection and switch boxes on different long lines, * * as they will not be staggered by different segment start points. */ - int cur_track, ntracks, itrack, length, j, index; - int fac, num_sets, tmp; - int arch_wire_switch, arch_opin_switch, arch_wire_switch_dec, arch_opin_switch_dec; - int arch_opin_between_dice_switch; - int group_start, first_track; - std::unique_ptr sets_per_seg_type; - t_seg_details* seg_details = nullptr; - bool longline; - - /* Unidir tracks are assigned in pairs, and bidir tracks individually */ + // Unidir tracks are assigned in pairs, and bidir tracks individually + int fac; if (directionality == BI_DIRECTIONAL) { fac = 1; } else { @@ -422,51 +348,45 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Routing channel width must be divisible by %d (channel width was %d)", fac, *max_chan_width); } - /* Map segment type fractions and groupings to counts of tracks */ - sets_per_seg_type = get_seg_track_counts((*max_chan_width / fac), - segment_inf, use_full_seg_groups); + // Map segment type fractions and groupings to counts of tracks + const std::vector sets_per_seg_type = get_seg_track_counts((*max_chan_width / fac), + segment_inf, use_full_seg_groups); - /* Count the number tracks actually assigned. */ - tmp = 0; - for (size_t i = 0; i < segment_inf.size(); ++i) { - tmp += sets_per_seg_type[i] * fac; - } + // Count the number tracks actually assigned. + int tmp = std::accumulate(sets_per_seg_type.begin(), sets_per_seg_type.end(), 0) * fac; VTR_ASSERT(use_full_seg_groups || (tmp == *max_chan_width)); *max_chan_width = tmp; - seg_details = new t_seg_details[*max_chan_width]; + std::vector seg_details(*max_chan_width); - /* Setup the seg_details data */ - cur_track = 0; + // Setup the seg_details data + int cur_track = 0; for (size_t i = 0; i < segment_inf.size(); ++i) { - first_track = cur_track; + int first_track = cur_track; - num_sets = sets_per_seg_type[i]; - ntracks = fac * num_sets; + const int num_sets = sets_per_seg_type[i]; + const int ntracks = fac * num_sets; if (ntracks < 1) { continue; } /* Avoid divide by 0 if ntracks */ - longline = segment_inf[i].longline; - length = segment_inf[i].length; - if (longline) { - length = max_len; - } - - arch_wire_switch = segment_inf[i].arch_wire_switch; - arch_opin_switch = segment_inf[i].arch_opin_switch; - arch_wire_switch_dec = segment_inf[i].arch_wire_switch_dec; - arch_opin_switch_dec = segment_inf[i].arch_opin_switch_dec; - arch_opin_between_dice_switch = segment_inf[i].arch_opin_between_dice_switch; + const bool longline = segment_inf[i].longline; + const int length = (longline) ? max_len : segment_inf[i].length; + + const int arch_wire_switch = segment_inf[i].arch_wire_switch; + const int arch_opin_switch = segment_inf[i].arch_opin_switch; + const int arch_wire_switch_dec = segment_inf[i].arch_wire_switch_dec; + const int arch_opin_switch_dec = segment_inf[i].arch_opin_switch_dec; + const int arch_inter_die_switch = segment_inf[i].arch_inter_die_switch; VTR_ASSERT((arch_wire_switch == arch_opin_switch && arch_wire_switch_dec == arch_opin_switch_dec) || (directionality != UNI_DIRECTIONAL)); - /* Set up the tracks of same type */ - group_start = 0; - for (itrack = 0; itrack < ntracks; itrack++) { - /* set the name of the segment type this track belongs to */ + // Set up the tracks of same type + int group_start = 0; + for (int itrack = 0; itrack < ntracks; itrack++) { + // set the name of the segment type this track belongs to seg_details[cur_track].type_name = segment_inf[i].name; - /* Remember the start track of the current wire group */ + // Remember the start track of the current wire group if ((itrack / fac) % length == 0 && (itrack % fac) == 0) { group_start = cur_track; } @@ -478,12 +398,10 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, * pin mappings should be aware of this when choosing an * intelligent way of connecting pins and tracks. * cur_track is used as an offset so that extra tracks - * from different segment types are hopefully better - * balanced. */ + * from different segment types are hopefully better balanced. */ seg_details[cur_track].start = (cur_track / fac) % length + 1; - /* These properties are used for vpr_to_phy_track to determine - * * twisting of wires. */ + // These properties are used for vpr_to_phy_track to determine twisting of wires. seg_details[cur_track].group_start = group_start; seg_details[cur_track].group_size = std::min(ntracks + first_track - group_start, length * fac); VTR_ASSERT(0 == seg_details[cur_track].group_size % fac); @@ -491,28 +409,25 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, seg_details[cur_track].group_size = length * fac; } - seg_details[cur_track].seg_start = -1; - seg_details[cur_track].seg_end = -1; - /* Setup the cb and sb patterns. Global route graphs can't depopulate cb and sb * since this is a property of a detailed route. */ seg_details[cur_track].cb = std::make_unique(length); seg_details[cur_track].sb = std::make_unique(length + 1); - for (j = 0; j < length; ++j) { + for (int j = 0; j < length; ++j) { if (seg_details[cur_track].longline) { seg_details[cur_track].cb[j] = true; } else { - /* Use the segment's pattern. */ - index = j % segment_inf[i].cb.size(); + // Use the segment's pattern. + int index = j % segment_inf[i].cb.size(); seg_details[cur_track].cb[j] = segment_inf[i].cb[index]; } } - for (j = 0; j < (length + 1); ++j) { + for (int j = 0; j < (length + 1); ++j) { if (seg_details[cur_track].longline) { seg_details[cur_track].sb[j] = true; } else { /* Use the segment's pattern. */ - index = j % segment_inf[i].sb.size(); + int index = j % segment_inf[i].sb.size(); seg_details[cur_track].sb[j] = segment_inf[i].sb[index]; } } @@ -521,7 +436,7 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, seg_details[cur_track].Cmetal = segment_inf[i].Cmetal; //seg_details[cur_track].Cmetal_per_m = segment_inf[i].Cmetal_per_m; - seg_details[cur_track].arch_opin_between_dice_switch = arch_opin_between_dice_switch; + seg_details[cur_track].arch_inter_die_switch = arch_inter_die_switch; if (BI_DIRECTIONAL == directionality) { seg_details[cur_track].direction = Direction::BIDIR; @@ -530,13 +445,12 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, seg_details[cur_track].direction = (itrack % 2) ? Direction::DEC : Direction::INC; } - //check for directionality to set the wire_switch and opin_switch - //if not specified in the architecture file, we will use a same mux for both directions - if (seg_details[cur_track].direction == Direction::INC || seg_details[cur_track].direction == Direction::BIDIR || arch_wire_switch_dec == -1){ + // check for directionality to set the wire_switch and opin_switch + // if not specified in the architecture file, we will use a same mux for both directions + if (seg_details[cur_track].direction == Direction::INC || seg_details[cur_track].direction == Direction::BIDIR || arch_wire_switch_dec == -1) { seg_details[cur_track].arch_opin_switch = arch_opin_switch; seg_details[cur_track].arch_wire_switch = arch_wire_switch; - } - else { + } else { VTR_ASSERT(seg_details[cur_track].direction == Direction::DEC); seg_details[cur_track].arch_opin_switch = arch_opin_switch_dec; seg_details[cur_track].arch_wire_switch = arch_wire_switch_dec; @@ -549,43 +463,35 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, } } /* End for each segment type. */ - if (num_seg_details) { - *num_seg_details = cur_track; - } + seg_details.resize(cur_track); return seg_details; } /* Allocates and loads the chan_details data structure, a 2D array of * seg_details structures. This array is used to handle unique seg_details * (ie. channel segments) for each horizontal and vertical channel. */ - void alloc_and_load_chan_details(const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, - const int num_seg_details_x, - const int num_seg_details_y, - const t_seg_details* seg_details_x, - const t_seg_details* seg_details_y, + const t_chan_width& nodes_per_chan, + const std::vector& seg_details_x, + const std::vector& seg_details_y, t_chan_details& chan_details_x, t_chan_details& chan_details_y) { - chan_details_x = init_chan_details(grid, nodes_per_chan, - num_seg_details_x, seg_details_x, X_AXIS); - chan_details_y = init_chan_details(grid, nodes_per_chan, - num_seg_details_y, seg_details_y, Y_AXIS); + chan_details_x = init_chan_details(grid, nodes_per_chan, seg_details_x, X_AXIS); + chan_details_y = init_chan_details(grid, nodes_per_chan, seg_details_y, Y_AXIS); /* Adjust segment start/end based on obstructed channels, if any */ - adjust_chan_details(grid, nodes_per_chan, - chan_details_x, chan_details_y); + adjust_chan_details(grid, nodes_per_chan, chan_details_x, chan_details_y); } t_chan_details init_chan_details(const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, - const int num_seg_details, - const t_seg_details* seg_details, + const t_chan_width& nodes_per_chan, + const std::vector& seg_details, const enum e_parallel_axis seg_parallel_axis) { + const int num_seg_details = (int)seg_details.size(); if (seg_parallel_axis == X_AXIS) { - VTR_ASSERT(num_seg_details <= nodes_per_chan->x_max); + VTR_ASSERT(num_seg_details <= nodes_per_chan.x_max); } else if (seg_parallel_axis == Y_AXIS) { - VTR_ASSERT(num_seg_details <= nodes_per_chan->y_max); + VTR_ASSERT(num_seg_details <= nodes_per_chan.y_max); } t_chan_details chan_details({grid.width(), grid.height(), size_t(num_seg_details)}); @@ -611,11 +517,11 @@ t_chan_details init_chan_details(const DeviceGrid& grid, p_seg_details[i].set_seg_end(seg_end); if (seg_parallel_axis == X_AXIS) { - if (i >= nodes_per_chan->x_list[y]) { + if (i >= nodes_per_chan.x_list[y]) { p_seg_details[i].set_length(0); } } else if (seg_parallel_axis == Y_AXIS) { - if (i >= nodes_per_chan->y_list[x]) { + if (i >= nodes_per_chan.y_list[x]) { p_seg_details[i].set_length(0); } } @@ -626,7 +532,7 @@ t_chan_details init_chan_details(const DeviceGrid& grid, } void adjust_chan_details(const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, t_chan_details& chan_details_x, t_chan_details& chan_details_y) { for (size_t y = 0; y <= grid.height() - 2; ++y) { //-2 for no perim channels @@ -657,18 +563,18 @@ void adjust_chan_details(const DeviceGrid& grid, void adjust_seg_details(const int x, const int y, const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, t_chan_details& chan_details, const enum e_parallel_axis seg_parallel_axis) { int seg_index = (seg_parallel_axis == X_AXIS ? x : y); int max_chan_width = 0; if (seg_parallel_axis == X_AXIS) { - max_chan_width = nodes_per_chan->x_max; + max_chan_width = nodes_per_chan.x_max; } else if (seg_parallel_axis == Y_AXIS) { - max_chan_width = nodes_per_chan->y_max; + max_chan_width = nodes_per_chan.y_max; } else { VTR_ASSERT(seg_parallel_axis == BOTH_AXIS); - max_chan_width = nodes_per_chan->max; + max_chan_width = nodes_per_chan.max; } for (int track = 0; track < max_chan_width; ++track) { @@ -702,14 +608,8 @@ void adjust_seg_details(const int x, } } -void free_chan_details(t_chan_details& chan_details_x, - t_chan_details& chan_details_y) { - chan_details_x.clear(); - chan_details_y.clear(); -} - -/* Returns the segment number at which the segment this track lies on * - * started. */ +/* Returns the segment number at which the segment this track lies on + * started. */ int get_seg_start(const t_chan_seg_details* seg_details, const int itrack, const int chan_num, @@ -717,16 +617,14 @@ int get_seg_start(const t_chan_seg_details* seg_details, int seg_start = 0; if (seg_details[itrack].seg_start() >= 0) { seg_start = seg_details[itrack].seg_start(); - } else { seg_start = 1; - if (false == seg_details[itrack].longline()) { + if (!seg_details[itrack].longline()) { int length = seg_details[itrack].length(); int start = seg_details[itrack].start(); - /* Start is guaranteed to be between 1 and length. Hence adding length to * - * the quantity in brackets below guarantees it will be nonnegative. */ - + /* Start is guaranteed to be between 1 and length. Hence, adding length to + * the quantity in brackets below guarantees it will be non-negative. */ VTR_ASSERT(start > 0); VTR_ASSERT(start <= length); @@ -740,6 +638,7 @@ int get_seg_start(const t_chan_seg_details* seg_details, } } } + return seg_start; } @@ -856,7 +755,7 @@ int get_bidir_opin_connections(RRGraphBuilder& rr_graph_builder, continue; } - to_switch = (track_layer == opin_layer) ? seg_details[to_track].arch_wire_switch() : seg_details[to_track].arch_opin_between_dice_switch(); + to_switch = (track_layer == opin_layer) ? seg_details[to_track].arch_wire_switch() : seg_details[to_track].arch_inter_die_switch(); rr_edges_to_create.emplace_back(from_rr_node, to_node, to_switch, false); ++num_conn; @@ -947,11 +846,11 @@ int get_unidir_opin_connections(RRGraphBuilder& rr_graph_builder, } /* Add to the list. */ - auto to_switch = (opin_layer == track_layer) ? seg_details[inc_track].arch_opin_switch() : seg_details[inc_track].arch_opin_between_dice_switch(); + auto to_switch = (opin_layer == track_layer) ? seg_details[inc_track].arch_opin_switch() : seg_details[inc_track].arch_inter_die_switch(); rr_edges_to_create.emplace_back(from_rr_node, inc_inode_index, to_switch, false); ++num_edges; - to_switch = (opin_layer == track_layer) ? seg_details[dec_track].arch_opin_switch() : seg_details[dec_track].arch_opin_between_dice_switch(); + to_switch = (opin_layer == track_layer) ? seg_details[dec_track].arch_opin_switch() : seg_details[dec_track].arch_inter_die_switch(); rr_edges_to_create.emplace_back(from_rr_node, dec_inode_index, to_switch, false); ++num_edges; } @@ -1188,7 +1087,7 @@ static void load_chan_rr_indices(const int max_chan_width, const t_chan_details& chan_details, RRGraphBuilder& rr_graph_builder, int* index) { - auto& device_ctx = g_vpr_ctx.device(); + const auto& device_ctx = g_vpr_ctx.device(); for (int layer = 0; layer < grid.get_num_layers(); layer++) { /* Skip the current die if architecture file specifies that it doesn't require global resource routing */ @@ -1281,17 +1180,17 @@ vtr::NdMatrix get_number_track_to_track_inter_die_conn(t_sb_connection_m for (int iconn = 0; iconn < (int)conn_vector.size(); ++iconn) { //check if both from_node and to_node exists in the rr-graph //CHANY -> CHANX connection - if(check_3d_SB_RRnodes(rr_graph_builder, x, y, conn_vector[iconn].from_wire, - conn_vector[iconn].from_wire_layer, CHANY, - conn_vector[iconn].to_wire, conn_vector[iconn].to_wire_layer, - CHANX)){ + if (check_3d_SB_RRnodes(rr_graph_builder, x, y, conn_vector[iconn].from_wire, + conn_vector[iconn].from_wire_layer, CHANY, + conn_vector[iconn].to_wire, conn_vector[iconn].to_wire_layer, + CHANX)) { num_of_3d_conn++; } //CHANX -> CHANY connection - if(check_3d_SB_RRnodes(rr_graph_builder, x, y, conn_vector[iconn].from_wire, - conn_vector[iconn].from_wire_layer, CHANX, - conn_vector[iconn].to_wire, conn_vector[iconn].to_wire_layer, - CHANY)){ + if (check_3d_SB_RRnodes(rr_graph_builder, x, y, conn_vector[iconn].from_wire, + conn_vector[iconn].from_wire_layer, CHANX, + conn_vector[iconn].to_wire, conn_vector[iconn].to_wire_layer, + CHANY)) { num_of_3d_conn++; } } @@ -1299,7 +1198,7 @@ vtr::NdMatrix get_number_track_to_track_inter_die_conn(t_sb_connection_m } } } - extra_nodes_per_switchblocks[x][y] += ((num_of_3d_conn + custom_3d_sb_fanin_fanout - 1)/ custom_3d_sb_fanin_fanout); + extra_nodes_per_switchblocks[x][y] += ((num_of_3d_conn + custom_3d_sb_fanin_fanout - 1) / custom_3d_sb_fanin_fanout); } } } @@ -1364,17 +1263,14 @@ static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, for (int x = 0; x < (int)grid.width(); x++) { for (int y = 0; y < (int)grid.height(); y++) { //Process each block from its root location - if (grid.get_width_offset({x, y, layer}) == 0 && grid.get_height_offset({x, y, layer}) == 0) { - t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, - y, - layer}); + if (grid.is_root_location({x, y, layer})) { + t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); + //Assign indices for SINKs and SOURCEs // Note that SINKS/SOURCES have no side, so we always use side 0 - std::vector class_num_vec; - std::vector pin_num_vec; + std::vector class_num_vec = get_tile_root_classes(physical_type); + std::vector pin_num_vec = get_tile_root_pins(physical_type); - class_num_vec = get_tile_root_classes(physical_type); - pin_num_vec = get_tile_root_pins(physical_type); add_classes_spatial_lookup(rr_graph_builder, physical_type, class_num_vec, @@ -1471,17 +1367,14 @@ static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, } } - for (auto pin_num : pin_num_vec) { + for (const int pin_num : pin_num_vec) { bool assigned_to_rr_node = false; - std::vector x_offset; - std::vector y_offset; - std::vector pin_sides; - std::tie(x_offset, y_offset, pin_sides) = get_pin_coordinates(physical_type_ptr, pin_num, wanted_sides); - auto pin_type = get_pin_type_from_pin_physical_num(physical_type_ptr, pin_num); + const auto [x_offset, y_offset, pin_sides] = get_pin_coordinates(physical_type_ptr, pin_num, wanted_sides); + e_pin_type pin_type = get_pin_type_from_pin_physical_num(physical_type_ptr, pin_num); for (int pin_coord_idx = 0; pin_coord_idx < (int)pin_sides.size(); pin_coord_idx++) { int x_tile = root_x + x_offset[pin_coord_idx]; int y_tile = root_y + y_offset[pin_coord_idx]; - auto side = pin_sides[pin_coord_idx]; + e_side side = pin_sides[pin_coord_idx]; if (pin_type == DRIVER) { rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, OPIN, pin_num, side); assigned_to_rr_node = true; @@ -1524,8 +1417,8 @@ static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, } } - for (auto class_num : class_num_vec) { - auto class_type = get_class_type_from_class_physical_num(physical_type_ptr, class_num); + for (const int class_num : class_num_vec) { + e_pin_type class_type = get_class_type_from_class_physical_num(physical_type_ptr, class_num); e_rr_type node_type = SINK; if (class_type == DRIVER) { node_type = SOURCE; @@ -1546,16 +1439,7 @@ static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, } } -/* As the rr_indices builders modify a local copy of indices, use the local copy in the builder - * TODO: these building functions should only talk to a RRGraphBuilder object - * The biggest and fatal issue is - * - the rr_graph2.h is included in the rr_graph_storage.h, - * which is included in the rr_graph_builder.h - * If we include rr_graph_builder.h in rr_graph2.h, this creates a loop - * for C++ compiler to identify data structures, which cannot be solved!!! - * This will block us when putting the RRGraphBuilder object as an input arguement - * of this function - */ +/* As the rr_indices builders modify a local copy of indices, use the local copy in the builder */ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, const t_chan_width* nodes_per_chan, const DeviceGrid& grid, @@ -1594,8 +1478,8 @@ void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_build for (int layer = 0; layer < grid.get_num_layers(); layer++) { for (int x = 0; x < (int)grid.width(); x++) { for (int y = 0; y < (int)grid.height(); y++) { - //Process each block from it's root location - if (grid.get_width_offset({x, y, layer}) == 0 && grid.get_height_offset({x, y, layer}) == 0) { + //Process each block from its root location + if (grid.is_root_location({x, y, layer})) { t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); //Assign indices for SINKs and SOURCEs // Note that SINKS/SOURCES have no side, so we always use side 0 @@ -1875,7 +1759,6 @@ int get_track_to_pins(RRGraphBuilder& rr_graph_builder, } /* Check there is a connection and Fc map isn't wrong */ - /*int to_node = get_rr_node_index(L_rr_node_indices, x + width_offset, y + height_offset, IPIN, ipin, side);*/ RRNodeId to_node = rr_graph_builder.node_lookup().find_node(layer_index, x, y, IPIN, ipin, side); int switch_type = (layer_index == layer) ? wire_to_ipin_switch : wire_to_pin_between_dice_switch; if (to_node) { @@ -2100,7 +1983,7 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, if (Direction::INC == from_seg_details[from_track].direction() || BI_DIRECTIONAL == directionality) { num_conn += get_track_to_chan_seg(rr_graph_builder, layer, max_chan_width, from_track, to_chan, to_seg, to_type, from_side_b, to_side, - switch_override,custom_3d_sb_fanin_fanout, delayless_switch, + switch_override, custom_3d_sb_fanin_fanout, delayless_switch, sb_conn_map, num_of_3d_conns_custom_SB, from_rr_node, rr_edges_to_create, des_3d_rr_edges_to_create); } } else { @@ -2671,7 +2554,7 @@ static int vpr_to_phy_track(const int itrack, } t_sblock_pattern alloc_sblock_pattern_lookup(const DeviceGrid& grid, - t_chan_width* nodes_per_chan) { + const t_chan_width& nodes_per_chan) { /* loading up the sblock connection pattern matrix. It's a huge matrix because * for nonquantized W, it's impossible to make simple permutations to figure out * where muxes are and how to connect to them such that their sizes are balanced */ @@ -2686,14 +2569,14 @@ t_sblock_pattern alloc_sblock_pattern_lookup(const DeviceGrid& grid, VTR_ASSERT(grid.width() > 0); VTR_ASSERT(grid.height() > 0); //CHANGE THIS - VTR_ASSERT(nodes_per_chan->max >= 0); + VTR_ASSERT(nodes_per_chan.max >= 0); t_sblock_pattern sblock_pattern({{ grid.width() - 1, grid.height() - 1, 4, //From side 4, //To side - size_t(nodes_per_chan->max), + size_t(nodes_per_chan.max), 4 //to_mux, to_trac, alt_mux, alt_track }}, UN_SET); @@ -2705,7 +2588,7 @@ t_sblock_pattern alloc_sblock_pattern_lookup(const DeviceGrid& grid, void load_sblock_pattern_lookup(const int i, const int j, const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, const int /*Fs*/, @@ -2864,9 +2747,9 @@ void load_sblock_pattern_lookup(const int i, for (int ichan = 0; ichan < get_chan_width((e_side)side_cw, nodes_per_chan); ichan++) { int itrack = ichan; if (side_cw == TOP || side_cw == BOTTOM) { - itrack = ichan % nodes_per_chan->y_list[i]; + itrack = ichan % nodes_per_chan.y_list[i]; } else if (side_cw == RIGHT || side_cw == LEFT) { - itrack = ichan % nodes_per_chan->x_list[j]; + itrack = ichan % nodes_per_chan.x_list[j]; } if (incoming_wire_label[side_cw][itrack] != UN_SET) { @@ -2890,9 +2773,9 @@ void load_sblock_pattern_lookup(const int i, for (int ichan = 0; ichan < get_chan_width((e_side)side_ccw, nodes_per_chan); ichan++) { int itrack = ichan; if (side_ccw == TOP || side_ccw == BOTTOM) { - itrack = ichan % nodes_per_chan->y_list[i]; + itrack = ichan % nodes_per_chan.y_list[i]; } else if (side_ccw == RIGHT || side_ccw == LEFT) { - itrack = ichan % nodes_per_chan->x_list[j]; + itrack = ichan % nodes_per_chan.x_list[j]; } if (incoming_wire_label[side_ccw][itrack] != UN_SET) { @@ -3161,6 +3044,6 @@ static bool should_apply_switch_override(int switch_override) { return false; } -inline int get_chan_width(enum e_side side, const t_chan_width* nodes_per_chan) { - return (side == TOP || side == BOTTOM ? nodes_per_chan->y_max : nodes_per_chan->x_max); +inline int get_chan_width(enum e_side side, const t_chan_width& nodes_per_chan) { + return (side == TOP || side == BOTTOM ? nodes_per_chan.y_max : nodes_per_chan.x_max); } diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h index 348e5633708..71b7004197f 100644 --- a/vpr/src/route/rr_graph2.h +++ b/vpr/src/route/rr_graph2.h @@ -12,13 +12,6 @@ #include "device_grid.h" #include "get_parallel_segs.h" -/******************* Types shared by rr_graph2 functions *********************/ - -/* [0..grid.width()-1][0..grid.width()][0..3 (From side)] \ - * [0..3 (To side)][0...max_chan_width][0..3 (to_mux,to_trac,alt_mux,alt_track)] - * originally initialized to UN_SET until alloc_and_load_sb is called */ -typedef vtr::NdMatrix t_sblock_pattern; - /******************* Subroutines exported by rr_graph2.c *********************/ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, @@ -63,21 +56,6 @@ bool verify_rr_node_indices(const DeviceGrid& grid, const vtr::vector& rr_indexed_data, const t_rr_graph_storage& rr_nodes, bool is_flat); - -//Returns all x-channel or y-channel wires at the specified location -std::vector get_rr_node_chan_wires_at_location(const t_rr_node_indices& L_rr_node_indices, - t_rr_type rr_type, - int x, - int y); - -//Return the first rr node of the specified type and coordinates -// For non-IPIN/OPIN types 'side' is ignored -int get_rr_node_index(const t_rr_node_indices& L_rr_node_indices, - int x, - int y, - t_rr_type rr_type, - int ptc, - e_side side = NUM_2D_SIDES); /** * @brief goes through 3D custom switch blocks and counts how many connections are crossing dice for each switch block. * @@ -90,46 +68,36 @@ vtr::NdMatrix get_number_track_to_track_inter_die_conn(t_sb_connection_m const int custom_3d_sb_fanin_fanout, RRGraphBuilder& rr_graph_builder); -int find_average_rr_node_index(int device_width, - int device_height, - t_rr_type rr_type, - int ptc, - const t_rr_node_indices& L_rr_node_indices); - -t_seg_details* alloc_and_load_seg_details(int* max_chan_width, - const int max_len, - const std::vector& segment_inf, - const bool use_full_seg_groups, - const enum e_directionality directionality, - int* num_seg_details = nullptr); +std::vector alloc_and_load_seg_details(int* max_chan_width, + const int max_len, + const std::vector& segment_inf, + const bool use_full_seg_groups, + const enum e_directionality directionality); void alloc_and_load_chan_details(const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, - const int num_seg_details_x, - const int num_seg_details_y, - const t_seg_details* seg_details_x, - const t_seg_details* seg_details_y, + const t_chan_width& nodes_per_chan, + const std::vector& seg_details_x, + const std::vector& seg_details_y, t_chan_details& chan_details_x, t_chan_details& chan_details_y); + t_chan_details init_chan_details(const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, - const int num_seg_details, - const t_seg_details* seg_details, + const t_chan_width& nodes_per_chan, + const std::vector& seg_details, const enum e_parallel_axis seg_details_type); + void adjust_chan_details(const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, t_chan_details& chan_details_x, t_chan_details& chan_details_y); + void adjust_seg_details(const int x, const int y, const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, t_chan_details& chan_details, const enum e_parallel_axis seg_details_type); -void free_chan_details(t_chan_details& chan_details_x, - t_chan_details& chan_details_y); - int get_seg_start(const t_chan_seg_details* seg_details, const int itrack, const int chan_num, @@ -223,12 +191,12 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, t_sb_connection_map* sb_conn_map); t_sblock_pattern alloc_sblock_pattern_lookup(const DeviceGrid& grid, - t_chan_width* nodes_per_chan); + const t_chan_width& nodes_per_chan); void load_sblock_pattern_lookup(const int i, const int j, const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, const int Fs, @@ -239,15 +207,28 @@ int get_parallel_seg_index(const int abs, const t_unified_to_parallel_seg_index& index_map, const e_parallel_axis parallel_axis); -std::unique_ptr get_ordered_seg_track_counts(const std::vector& segment_inf_x, - const std::vector& segment_inf_y, - const std::vector& segment_inf, - const std::unique_ptr& segment_sets_x, - const std::unique_ptr& segment_sets_y); - -std::unique_ptr get_seg_track_counts(const int num_sets, - const std::vector& segment_inf, - const bool use_full_seg_groups); +/** + * @brief Assigns routing tracks to each segment type based on their frequencies and lengths. + * + * This function determines how many routing tracks (or sets of tracks) to assign to each + * segment type in order to match the desired frequency distribution specified in + * the segment information. + * + * When @p use_full_seg_groups is true, the function assigns tracks in multiples of the + * segment length, which may result in a total track count that slightly overshoots or + * undershoots the target @p num_sets. The algorithm proceeds by: + * - Calculating the demand for each segment type. + * - Iteratively assigning tracks to the segment type with the highest remaining demand. + * - Optionally undoing the last assignment if it overshoots the target by more than half a group. + * + * @param num_sets Total number of track sets to assign. + * @param segment_inf Vector containing segment type information (frequency, length, etc.). + * @param use_full_seg_groups If true, assign tracks in full segment-length groups. + * @return A vector where each element indicates the number of tracks assigned to the corresponding segment type. + */ +std::vector get_seg_track_counts(int num_sets, + const std::vector& segment_inf, + bool use_full_seg_groups); void dump_seg_details(const t_chan_seg_details* seg_details, int max_chan_width, @@ -270,9 +251,5 @@ void dump_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map, int max_chan_width, FILE* fp); -void add_to_rr_node_indices(t_rr_node_indices& rr_node_indices, const t_rr_graph_storage& rr_nodes, int inode); - -void insert_at_ptc_index(std::vector& rr_indices, int ptc, int inode); - -inline int get_chan_width(enum e_side side, const t_chan_width* nodes_per_channel); +inline int get_chan_width(enum e_side side, const t_chan_width& nodes_per_channel); #endif diff --git a/vpr/src/route/rr_graph_area.cpp b/vpr/src/route/rr_graph_area.cpp index 75d99f2fde2..06b1c5e512d 100644 --- a/vpr/src/route/rr_graph_area.cpp +++ b/vpr/src/route/rr_graph_area.cpp @@ -282,7 +282,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl break; } /* End switch on from_rr_type */ - } /* End for all nodes */ + } /* End for all nodes */ delete[] cblock_counted; delete[] shared_buffer_trans; @@ -480,7 +480,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* break; } /* End switch on from_rr_type */ - } /* End for all nodes */ + } /* End for all nodes */ /* Now add in the input connection block transistors. */ diff --git a/vpr/src/route/rr_graph_indexed_data.cpp b/vpr/src/route/rr_graph_indexed_data.cpp index 115f29b0445..09bad36ad28 100644 --- a/vpr/src/route/rr_graph_indexed_data.cpp +++ b/vpr/src/route/rr_graph_indexed_data.cpp @@ -19,4 +19,4 @@ void load_rr_index_segments(const int num_segment) { index = CHANX_COST_INDEX_START + num_segment + iseg; device_ctx.rr_indexed_data[RRIndexedDataId(index)].seg_index = iseg; } -} \ No newline at end of file +} diff --git a/vpr/src/route/rr_graph_timing_params.cpp b/vpr/src/route/rr_graph_timing_params.cpp index ae316cef2c7..d2c478dffe6 100644 --- a/vpr/src/route/rr_graph_timing_params.cpp +++ b/vpr/src/route/rr_graph_timing_params.cpp @@ -1,14 +1,9 @@ #include -#include "vtr_memory.h" - -#include "vpr_types.h" -#include "vpr_error.h" - #include "globals.h" #include "rr_graph.h" #include "rr_graph_utils.h" -#include "rr_graph2.h" +#include "rr_rc_data.h" #include "rr_graph_timing_params.h" /****************** Subroutine definitions *********************************/ diff --git a/vpr/src/route/rr_types.h b/vpr/src/route/rr_types.h index d75f107d082..8e093faca75 100644 --- a/vpr/src/route/rr_types.h +++ b/vpr/src/route/rr_types.h @@ -22,4 +22,164 @@ typedef std::vector, 5>> t_pin_to_track_lookup; typedef std::vector, 5>> t_track_to_pin_lookup; +/** + * @brief Lists detailed information about wire segments. [0 .. W-1]. + */ +struct t_seg_details { + /** @brief Length (in clbs) of the segment. */ + int length = 0; + + /** @brief Index at which a segment starts in channel 0. */ + int start = 0; + + /** @brief True if this segment spans the entire channel. */ + bool longline = false; + + /** @brief [0..length]: true for every channel intersection, relative to the + * segment start, at which there is a switch box. + */ + std::unique_ptr sb; + + /** @brief [0..length-1]: true for every logic block along the segment at + * which there is a connection box. + */ + std::unique_ptr cb; + + /** @brief Index of the switch type that connects other wires to this segment. + * Note that this index is in relation to the switches from the architecture + * file, not the expanded list of switches that is built at the end of build_rr_graph. + */ + short arch_wire_switch = 0; + + /** @brief Index of the switch type that connects output pins (OPINs) *to* this segment. + * Note that this index is in relation to the switches from the architecture + * file, not the expanded list of switches that is built at the end of build_rr_graph. + */ + short arch_opin_switch = 0; + + /** @brief Index of the switch type that connects output pins (OPINs) *to* this segment + * from *another dice*. Note that this index is in relation to the switches from the + * architecture file, not the expanded list of switches that is built at the end of + * build_rr_graph. + */ + short arch_inter_die_switch = 0; + + /** @brief Resistance of a routing track, per unit logic block length. */ + float Rmetal = 0; + + /** @brief Capacitance of a routing track, per unit logic block length. */ + float Cmetal = 0; + + /** @brief Whether the segment is twisted. */ + bool twisted = false; + + /** @brief Direction of the segment. */ + enum Direction direction = Direction::NONE; + + /** @brief Index of the first logic block in the group. */ + int group_start = 0; + + /** @brief Size of the group. */ + int group_size = 0; + + /** @brief index of the segment type used for this track. + * Note that this index will store the index of the segment + * relative to its **parallel** segment types, not all segments + * as stored in device_ctx. Look in rr_graph.cpp: build_rr_graph + * for details but here is an example: say our segment_inf_vec in + * device_ctx is as follows: [seg_a_x, seg_b_x, seg_a_y, seg_b_y] + * when building the rr_graph, static segment_inf_vectors will be + * created for each direction, thus you will have the following + * 2 vectors: X_vec =[seg_a_x,seg_b_x] and Y_vec = [seg_a_y,seg_b_y]. + * As a result, e.g. seg_b_y::index == 1 (index in Y_vec) + * and != 3 (index in device_ctx segment_inf_vec). + */ + int index = 0; + + /** @brief index is relative to the segment_inf vec as stored in device_ctx. + * Note that the above vector is **unifies** both x-parallel and + * y-parallel segments and is loaded up originally in read_xml_arch_file.cpp + */ + int abs_index = 0; + + /** @brief Used for power */ + float Cmetal_per_m = 0; + + /** @brief Name of the segment type. */ + std::string type_name; +}; + +class t_chan_seg_details { + public: + t_chan_seg_details() = default; + t_chan_seg_details(const t_seg_details* init_seg_details) + : length_(init_seg_details->length) + , seg_detail_(init_seg_details) {} + + public: + int length() const { return length_; } + int seg_start() const { return seg_start_; } + int seg_end() const { return seg_end_; } + + int start() const { return seg_detail_->start; } + bool longline() const { return seg_detail_->longline; } + + int group_start() const { return seg_detail_->group_start; } + int group_size() const { return seg_detail_->group_size; } + + bool cb(int pos) const { return seg_detail_->cb[pos]; } + bool sb(int pos) const { return seg_detail_->sb[pos]; } + + float Rmetal() const { return seg_detail_->Rmetal; } + float Cmetal() const { return seg_detail_->Cmetal; } + float Cmetal_per_m() const { return seg_detail_->Cmetal_per_m; } + + short arch_wire_switch() const { return seg_detail_->arch_wire_switch; } + short arch_opin_switch() const { return seg_detail_->arch_opin_switch; } + short arch_inter_die_switch() const { return seg_detail_->arch_inter_die_switch; } + + Direction direction() const { return seg_detail_->direction; } + + int index() const { return seg_detail_->index; } + int abs_index() const { return seg_detail_->abs_index; } + + const vtr::string_view type_name() const { + return vtr::string_view( + seg_detail_->type_name.data(), + seg_detail_->type_name.size()); + } + + public: //Modifiers + void set_length(int new_len) { length_ = new_len; } + void set_seg_start(int new_start) { seg_start_ = new_start; } + void set_seg_end(int new_end) { seg_end_ = new_end; } + + private: + //The only unique information about a channel segment is it's start/end + //and length. All other information is shared across segment types, + //so we use a flyweight to the t_seg_details which defines that info. + // + //To preserve the illusion of uniqueness we wrap all t_seg_details members + //so it appears transparent -- client code of this class doesn't need to + //know about t_seg_details. + int length_ = -1; + int seg_start_ = -1; + int seg_end_ = -1; + const t_seg_details* seg_detail_ = nullptr; +}; + +/** + * @typedef t_chan_details + * @brief Defines a 3-D array of t_chan_seg_details structures (one for each horizontal and vertical channel). + * + * Once allocated in rr_graph2.cpp, it can be accessed as: + * [0..grid.width()][0..grid.height()][0..num_tracks-1] + */ +typedef vtr::NdMatrix t_chan_details; + +/* [0..grid.width()-1][0..grid.width()][0..3 (From side)] \ + * [0..3 (To side)][0...max_chan_width][0..3 (to_mux,to_trac,alt_mux,alt_track)] + * originally initialized to UN_SET until alloc_and_load_sb is called */ +typedef vtr::NdMatrix t_sblock_pattern; + #endif diff --git a/vpr/src/route/sink_sampling.h b/vpr/src/route/sink_sampling.h index 485bff9b3e5..341a292db7f 100644 --- a/vpr/src/route/sink_sampling.h +++ b/vpr/src/route/sink_sampling.h @@ -159,7 +159,7 @@ inline void convex_hull_downsample(ParentNetId net_id, const t_bb& net_bb, vtr:: for (auto& point : hull) { if (point.isink == 0) /* source */ continue; - if(is_isink_reached.get(point.isink)) + if (is_isink_reached.get(point.isink)) continue; out.set(point.isink, true); } diff --git a/vpr/src/server/bytearray.h b/vpr/src/server/bytearray.h index 2a94927f0cc..566cc83f02d 100644 --- a/vpr/src/server/bytearray.h +++ b/vpr/src/server/bytearray.h @@ -12,9 +12,9 @@ namespace comm { /** * @brief ByteArray is a simple wrapper over std::vector that provides a user-friendly interface for manipulating array data.. -*/ + */ class ByteArray : public std::vector { -public: + public: static const std::size_t DEFAULT_SIZE_HINT = 1024; /** @@ -27,8 +27,7 @@ class ByteArray : public std::vector { * @param data A pointer to the null-terminated C string from which to construct the ByteArray. */ explicit ByteArray(const char* data) - : std::vector(data, data + std::strlen(data)) - {} + : std::vector(data, data + std::strlen(data)) {} /** * @brief Constructs a ByteArray from a raw character array. @@ -41,8 +40,7 @@ class ByteArray : public std::vector { * @param size The size of the raw character array, in bytes. */ ByteArray(const char* data, std::size_t size) - : std::vector(data, data + size) - {} + : std::vector(data, data + size) {} /** * @brief Constructs a byte array with the specified size hint. @@ -66,7 +64,8 @@ class ByteArray : public std::vector { * @param last An iterator to the last element in the range. */ template - ByteArray(Iterator first, Iterator last): std::vector(first, last) {} + ByteArray(Iterator first, Iterator last) + : std::vector(first, last) {} /** * @brief Appends the content of another byte array to the end of this byte array. diff --git a/vpr/src/server/commcmd.h b/vpr/src/server/commcmd.h index 28f3f69f452..54301bad63e 100644 --- a/vpr/src/server/commcmd.h +++ b/vpr/src/server/commcmd.h @@ -6,9 +6,9 @@ namespace comm { enum class CMD : int { - NONE=-1, - GET_PATH_LIST_ID=0, - DRAW_PATH_ID=1 + NONE = -1, + GET_PATH_LIST_ID = 0, + DRAW_PATH_ID = 1 }; } // namespace comm diff --git a/vpr/src/server/convertutils.cpp b/vpr/src/server/convertutils.cpp index f176e7ffee9..6832b23767b 100644 --- a/vpr/src/server/convertutils.cpp +++ b/vpr/src/server/convertutils.cpp @@ -18,7 +18,7 @@ std::optional try_convert_to_int(const std::string& str) { static std::string get_pretty_str_from_double(double value) { std::ostringstream ss; - ss << std::fixed << std::setprecision(2) << value; // Set precision to 2 digit after the decimal point + ss << std::fixed << std::setprecision(2) << value; // Set precision to 2 digit after the decimal point return ss.str(); } @@ -35,10 +35,10 @@ std::string get_pretty_duration_str_from_ms(int64_t duration_ms) { std::string get_pretty_size_str_from_bytes_num(int64_t bytes_num) { std::string result; - if (bytes_num >= 1024*1024*1024) { - result = get_pretty_str_from_double(bytes_num / double(1024*1024*1024)) + "Gb"; - } else if (bytes_num >= 1024*1024) { - result = get_pretty_str_from_double(bytes_num / double(1024*1024)) + "Mb"; + if (bytes_num >= 1024 * 1024 * 1024) { + result = get_pretty_str_from_double(bytes_num / double(1024 * 1024 * 1024)) + "Gb"; + } else if (bytes_num >= 1024 * 1024) { + result = get_pretty_str_from_double(bytes_num / double(1024 * 1024)) + "Mb"; } else if (bytes_num >= 1024) { result = get_pretty_str_from_double(bytes_num / double(1024)) + "Kb"; } else { diff --git a/vpr/src/server/gateio.cpp b/vpr/src/server/gateio.cpp index d40431e7da9..4094fd3e061 100644 --- a/vpr/src/server/gateio.cpp +++ b/vpr/src/server/gateio.cpp @@ -36,7 +36,7 @@ void GateIO::stop() { void GateIO::take_received_tasks(std::vector& tasks) { std::unique_lock lock(m_tasks_mutex); - for (TaskPtr& task: m_received_tasks) { + for (TaskPtr& task : m_received_tasks) { m_logger.queue(LogLevel::Debug, "move task id=", task->job_id(), "for processing"); tasks.push_back(std::move(task)); } @@ -45,7 +45,7 @@ void GateIO::take_received_tasks(std::vector& tasks) { void GateIO::move_tasks_to_send_queue(std::vector& tasks) { std::unique_lock lock(m_tasks_mutex); - for (TaskPtr& task: tasks) { + for (TaskPtr& task : tasks) { m_logger.queue(LogLevel::Debug, "move task id=", task->job_id(), "finished", (task->has_error() ? "with error" : "successfully"), task->error(), "to send queue"); m_send_tasks.push_back(std::move(task)); } @@ -58,7 +58,7 @@ GateIO::ActivityStatus GateIO::check_client_connection(sockpp::tcp6_acceptor& tc sockpp::inet6_address peer; sockpp::tcp6_socket client = tcp_server.accept(&peer); if (client) { - m_logger.queue(LogLevel::Info, "client", client.address().to_string() , "connection accepted"); + m_logger.queue(LogLevel::Info, "client", client.address().to_string(), "connection accepted"); client.set_non_blocking(true); client_opt = std::move(client); @@ -80,12 +80,12 @@ GateIO::ActivityStatus GateIO::handle_sending_data(sockpp::tcp6_socket& client) if (bytes_sent <= task->orig_reponse_bytes_num()) { task->chop_num_sent_bytes_from_response_buffer(bytes_sent); m_logger.queue(LogLevel::Detail, - "sent chunk:", get_pretty_size_str_from_bytes_num(bytes_sent), - "from", get_pretty_size_str_from_bytes_num(task->orig_reponse_bytes_num()), - "left:", get_pretty_size_str_from_bytes_num(task->response_buffer().size())); + "sent chunk:", get_pretty_size_str_from_bytes_num(bytes_sent), + "from", get_pretty_size_str_from_bytes_num(task->orig_reponse_bytes_num()), + "left:", get_pretty_size_str_from_bytes_num(task->response_buffer().size())); status = ActivityStatus::CLIENT_ACTIVITY; } - } catch(...) { + } catch (...) { m_logger.queue(LogLevel::Detail, "error while writing chunk"); status = ActivityStatus::COMMUNICATION_PROBLEM; } @@ -99,7 +99,7 @@ GateIO::ActivityStatus GateIO::handle_sending_data(sockpp::tcp6_socket& client) std::size_t tasks_num_before_removing = m_send_tasks.size(); auto partition_iter = std::partition(m_send_tasks.begin(), m_send_tasks.end(), - [](const TaskPtr& task) { return !task->is_response_fully_sent(); }); + [](const TaskPtr& task) { return !task->is_response_fully_sent(); }); m_send_tasks.erase(partition_iter, m_send_tasks.end()); bool is_removing_took_place = tasks_num_before_removing != m_send_tasks.size(); if (!m_send_tasks.empty() && is_removing_took_place) { @@ -114,7 +114,7 @@ GateIO::ActivityStatus GateIO::handle_receiving_data(sockpp::tcp6_socket& client std::size_t bytes_actually_received{0}; try { bytes_actually_received = client.read_n(&received_message[0], CHUNK_MAX_BYTES_NUM); - } catch(...) { + } catch (...) { m_logger.queue(LogLevel::Error, "fail to receiving"); status = ActivityStatus::COMMUNICATION_PROBLEM; } @@ -132,7 +132,7 @@ GateIO::ActivityStatus GateIO::handle_telegrams(std::vectorbody}; bool is_echo_telegram = false; @@ -150,7 +150,7 @@ GateIO::ActivityStatus GateIO::handle_telegrams(std::vector(job_id_opt.value(), static_cast(cmd_opt.value()), options_opt.value()); const comm::TelegramHeader& header = telegram_frame->header; - m_logger.queue(LogLevel::Info, "received:", header.info(), task->info(/*skipDuration*/true)); + m_logger.queue(LogLevel::Info, "received:", header.info(), task->info(/*skipDuration*/ true)); std::unique_lock lock(m_tasks_mutex); m_received_tasks.push_back(std::move(task)); } else { @@ -176,7 +176,7 @@ GateIO::ActivityStatus GateIO::handle_client_alive_tracker(sockpp::tcp6_socket& m_logger.queue(LogLevel::Detail, "sent", comm::ECHO_TELEGRAM_BODY); client_alive_tracker_ptr->on_echo_sent(); } - } catch(...) { + } catch (...) { m_logger.queue(LogLevel::Debug, "fail to sent", comm::ECHO_TELEGRAM_BODY); status = ActivityStatus::COMMUNICATION_PROBLEM; } @@ -204,8 +204,7 @@ void GateIO::handle_activity_status(ActivityStatus status, std::unique_ptr client_alive_tracker_ptr = - std::make_unique(std::chrono::milliseconds{5000}, std::chrono::milliseconds{20000}); + std::unique_ptr client_alive_tracker_ptr = std::make_unique(std::chrono::milliseconds{5000}, std::chrono::milliseconds{20000}); #else std::unique_ptr client_alive_tracker_ptr; #endif @@ -229,7 +228,7 @@ void GateIO::start_listening() { received_message.resize(CHUNK_MAX_BYTES_NUM); /// comm event loop - while(m_is_running.load()) { + while (m_is_running.load()) { bool is_communication_problem_detected = false; if (!client_opt) { @@ -259,7 +258,7 @@ void GateIO::start_listening() { // forward telegramBuffer errors std::vector telegram_buffer_errors; telegram_buff.take_errors(telegram_buffer_errors); - for (const std::string& error: telegram_buffer_errors) { + for (const std::string& error : telegram_buffer_errors) { m_logger.queue(LogLevel::Info, error); } diff --git a/vpr/src/server/gateio.h b/vpr/src/server/gateio.h index aa9036459c5..ee72d155cb7 100644 --- a/vpr/src/server/gateio.h +++ b/vpr/src/server/gateio.h @@ -37,16 +37,15 @@ namespace server { * and responsiveness of the application. * - GateIO is not started automatically upon creation, you have to use the 'start' method with the port number. * - The socket is initialized in a non-blocking mode to function properly in a multithreaded environment. -*/ -class GateIO -{ + */ +class GateIO { enum class ActivityStatus : int { WAITING_ACTIVITY, CLIENT_ACTIVITY, COMMUNICATION_PROBLEM }; - const std::size_t CHUNK_MAX_BYTES_NUM = 2*1024*1024; // 2Mb + const std::size_t CHUNK_MAX_BYTES_NUM = 2 * 1024 * 1024; // 2Mb /** * @brief Helper class aimed to help detecting a client offline. @@ -58,12 +57,13 @@ class GateIO * and it's time to start accepting new client connections in GateIO. */ class ClientAliveTracker { - public: + public: ClientAliveTracker(const std::chrono::milliseconds& echoIntervalMs, const std::chrono::milliseconds& clientTimeoutMs) - : m_echo_interval_ms(echoIntervalMs), m_client_timeout_ms(clientTimeoutMs) { + : m_echo_interval_ms(echoIntervalMs) + , m_client_timeout_ms(clientTimeoutMs) { reset(); } - ClientAliveTracker()=default; + ClientAliveTracker() = default; void on_client_activity() { m_last_client_activity_time = std::chrono::high_resolution_clock::now(); @@ -76,13 +76,13 @@ class GateIO bool is_time_to_sent_echo() const { return (duration_since_last_client_activity_ms() > m_echo_interval_ms) && (durationSinceLastEchoSentMs() > m_echo_interval_ms); } - bool is_client_timeout() const { return duration_since_last_client_activity_ms() > m_client_timeout_ms; } + bool is_client_timeout() const { return duration_since_last_client_activity_ms() > m_client_timeout_ms; } void reset() { on_client_activity(); } - private: + private: std::chrono::high_resolution_clock::time_point m_last_client_activity_time; std::chrono::high_resolution_clock::time_point m_last_echo_sent_time; std::chrono::milliseconds m_echo_interval_ms; @@ -98,7 +98,7 @@ class GateIO } }; - enum class LogLevel: int { + enum class LogLevel : int { Error, Info, Detail, @@ -106,7 +106,7 @@ class GateIO }; class TLogger { - public: + public: TLogger() { m_log_level = static_cast(LogLevel::Info); } @@ -132,7 +132,7 @@ class GateIO } } - private: + private: std::stringstream m_log_stream; std::mutex m_log_stream_mutex; std::atomic m_log_level; @@ -140,7 +140,7 @@ class GateIO const int LOOP_INTERVAL_MS = 100; -public: + public: /** * @brief Default constructor for GateIO. */ @@ -154,10 +154,10 @@ class GateIO GateIO& operator=(GateIO&&) = delete; /** - * @brief Returns a bool indicating whether or not the port listening process is currently running. - * - * @return True if the port listening process is running, false otherwise. - */ + * @brief Returns a bool indicating whether or not the port listening process is currently running. + * + * @return True if the port listening process is running, false otherwise. + */ bool is_running() const { return m_is_running.load(); } /** @@ -178,7 +178,7 @@ class GateIO * remains empty after the operation. * * @param tasks A reference to a vector containing the tasks to be moved to the send queue. - */ + */ void move_tasks_to_send_queue(std::vector& tasks); /** @@ -187,7 +187,7 @@ class GateIO * @note Must be called from the main thread since it's invoke std::cout. * Calling this method from other threads may result in unexpected behavior. */ - void print_logs(); + void print_logs(); /** * @brief Starts the server on the specified port number. @@ -210,16 +210,16 @@ class GateIO */ void stop(); -private: + private: int m_port_num = -1; std::atomic m_is_running; // is true when started std::thread m_thread; // thread to execute socket IO work - std::mutex m_tasks_mutex; // we used single mutex to guard both vectors m_received_tasks and m_sendTasks + std::mutex m_tasks_mutex; // we used single mutex to guard both vectors m_received_tasks and m_sendTasks std::vector m_received_tasks; // tasks from client (requests) - std::vector m_send_tasks; // tasks to client (responses) + std::vector m_send_tasks; // tasks to client (responses) TLogger m_logger; @@ -240,4 +240,3 @@ class GateIO #endif /* NO_SERVER */ #endif /* GATEIO_H */ - diff --git a/vpr/src/server/pathhelper.cpp b/vpr/src/server/pathhelper.cpp index 9e9d8a7b576..b1f581aa620 100644 --- a/vpr/src/server/pathhelper.cpp +++ b/vpr/src/server/pathhelper.cpp @@ -13,7 +13,7 @@ namespace server { -/** +/** * @brief helper function to collect crit parser metadata. * This data is used on parser side to properly extract arrival path elements from the timing report. */ @@ -29,7 +29,7 @@ static void collect_crit_path_metadata(std::stringstream& ss, const std::vector< } } -/** +/** * @brief Helper function to calculate critical path timing report with specified parameters. */ CritPathsResultPtr calc_critical_path(const std::string& report_type, int crit_path_num, e_timing_report_detail details_level, bool is_flat_routing) { @@ -45,7 +45,7 @@ CritPathsResultPtr calc_critical_path(const std::string& report_type, int crit_p analysis_opts.timing_report_detail = details_level; analysis_opts.timing_report_npaths = crit_path_num; - VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, *routing_delay_calc, is_flat_routing, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, *routing_delay_calc, is_flat_routing, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); diff --git a/vpr/src/server/pathhelper.h b/vpr/src/server/pathhelper.h index 8d2244a885a..3de4ba9f4f4 100644 --- a/vpr/src/server/pathhelper.h +++ b/vpr/src/server/pathhelper.h @@ -16,36 +16,36 @@ namespace server { * @brief Structure to retain the calculation result of the critical path. * * It contains the critical path list and the generated report as a string. -*/ + */ struct CritPathsResult { /** - * @brief Checks if the CritPathsResult contains report. - * @return True if contains report, false otherwise. - */ + * @brief Checks if the CritPathsResult contains report. + * @return True if contains report, false otherwise. + */ bool is_valid() const { return !report.empty(); } /** - * @brief Vector containing timing paths. - */ + * @brief Vector containing timing paths. + */ std::vector paths; /** - * @brief String containing the generated report. - */ + * @brief String containing the generated report. + */ std::string report; }; using CritPathsResultPtr = std::shared_ptr; /** -* @brief Calculates the critical path. - -* This function calculates the critical path based on the provided parameters. -* @param type The type of the critical path. Must be either "setup" or "hold". -* @param crit_path_num The max number of critical paths to record. -* @param details_level The level of detail for the timing report. See @ref e_timing_report_detail. -* @param is_flat_routing Indicates whether flat routing should be used. -* @return A `CritPathsResultPtr` which is a pointer to the result of the critical path calculation (see @ref CritPathsResult). -*/ + * @brief Calculates the critical path. + * + * This function calculates the critical path based on the provided parameters. + * @param type The type of the critical path. Must be either "setup" or "hold". + * @param crit_path_num The max number of critical paths to record. + * @param details_level The level of detail for the timing report. See @ref e_timing_report_detail. + * @param is_flat_routing Indicates whether flat routing should be used. + * @return A `CritPathsResultPtr` which is a pointer to the result of the critical path calculation (see @ref CritPathsResult). + */ CritPathsResultPtr calc_critical_path(const std::string& type, int crit_path_num, e_timing_report_detail details_level, bool is_flat_routing); } // namespace server diff --git a/vpr/src/server/serverupdate.cpp b/vpr/src/server/serverupdate.cpp index de45c45936d..075077389ec 100644 --- a/vpr/src/server/serverupdate.cpp +++ b/vpr/src/server/serverupdate.cpp @@ -19,7 +19,7 @@ gboolean update(gpointer data) { std::vector tasks_buff; gate_io.take_received_tasks(tasks_buff); - for (TaskPtr& task: tasks_buff) { + for (TaskPtr& task : tasks_buff) { task_resolver.own_task(std::move(task)); } tasks_buff.clear(); @@ -39,7 +39,7 @@ gboolean update(gpointer data) { } gate_io.print_logs(); } - + // Return TRUE to keep the timer running, or FALSE to stop it return is_running; } diff --git a/vpr/src/server/serverupdate.h b/vpr/src/server/serverupdate.h index f3add9ed269..2235c6910a3 100644 --- a/vpr/src/server/serverupdate.h +++ b/vpr/src/server/serverupdate.h @@ -21,4 +21,3 @@ gboolean update(gpointer); #endif /* NO_SERVER */ #endif /* SERVERUPDATE_H */ - diff --git a/vpr/src/server/task.cpp b/vpr/src/server/task.cpp index f05ada6d835..185c8b81ca5 100644 --- a/vpr/src/server/task.cpp +++ b/vpr/src/server/task.cpp @@ -11,7 +11,9 @@ namespace server { Task::Task(int jobId, comm::CMD cmd, const std::string& options) -: m_job_id(jobId), m_cmd(cmd), m_options(options) { + : m_job_id(jobId) + , m_cmd(cmd) + , m_options(options) { m_creation_time = std::chrono::high_resolution_clock::now(); } @@ -54,7 +56,7 @@ void Task::set_success(std::string&& result) { std::string Task::info(bool skip_duration) const { std::stringstream ss; ss << "task[" - << "id=" << std::to_string(m_job_id) + << "id=" << std::to_string(m_job_id) << ",cmd=" << std::to_string(static_cast(m_cmd)); if (!skip_duration) { ss << ",exists=" << get_pretty_duration_str_from_ms(time_ms_elapsed()); diff --git a/vpr/src/server/task.h b/vpr/src/server/task.h index 3d29e49373f..696e2fb012d 100644 --- a/vpr/src/server/task.h +++ b/vpr/src/server/task.h @@ -19,7 +19,7 @@ namespace server { * It generates a JSON data structure to be sent back to the client as a response. */ class Task { -public: + public: /** * @brief Constructs a new Task object. * @@ -178,7 +178,7 @@ class Task { */ const std::string& options() const { return m_options; } -private: + private: int m_job_id = -1; comm::CMD m_cmd = comm::CMD::NONE; std::string m_options; diff --git a/vpr/src/server/taskresolver.cpp b/vpr/src/server/taskresolver.cpp index 5298521ece0..c9e505c727a 100644 --- a/vpr/src/server/taskresolver.cpp +++ b/vpr/src/server/taskresolver.cpp @@ -14,7 +14,7 @@ namespace server { void TaskResolver::own_task(TaskPtr&& new_task) { // pre-process task before adding, where we could quickly detect failure scenarios - for (const auto& task: m_tasks) { + for (const auto& task : m_tasks) { if (task->cmd() == new_task->cmd()) { if (task->options_match(new_task)) { std::string msg = "similar task is already in execution, reject new " + new_task->info() + " and waiting for old " + task->info() + " execution"; @@ -34,7 +34,7 @@ void TaskResolver::own_task(TaskPtr&& new_task) { } void TaskResolver::take_finished_tasks(std::vector& result) { - for (auto it=m_tasks.begin(); it != m_tasks.end();) { + for (auto it = m_tasks.begin(); it != m_tasks.end();) { TaskPtr& task = *it; if (task->is_finished()) { result.push_back(std::move(task)); @@ -61,21 +61,22 @@ std::optional TaskResolver::try_get_details_level_enum(c bool TaskResolver::update(ezgl::application* app) { bool has_processed_task = false; - for (auto& task: m_tasks) { + for (auto& task : m_tasks) { if (!task->is_finished()) { - switch(task->cmd()) { + switch (task->cmd()) { case comm::CMD::GET_PATH_LIST_ID: { process_get_path_list_task(app, task); has_processed_task = true; break; - } + } case comm::CMD::DRAW_PATH_ID: { process_draw_critical_path_task(app, task); has_processed_task = true; break; } - default: break; - } + default: + break; + } } } diff --git a/vpr/src/server/taskresolver.h b/vpr/src/server/taskresolver.h index eca06bc1b74..ce38348a6b5 100644 --- a/vpr/src/server/taskresolver.h +++ b/vpr/src/server/taskresolver.h @@ -10,7 +10,7 @@ #include namespace ezgl { - class application; +class application; } namespace server { @@ -19,51 +19,51 @@ namespace server { * @brief Resolve server task. * * Process and resolve server task, store result and status for processed task. -*/ + */ class TaskResolver { -public: + public: /** * @brief Default constructor for TaskResolver. */ - TaskResolver()=default; + TaskResolver() = default; - ~TaskResolver()=default; + ~TaskResolver() = default; int tasks_num() const { return m_tasks.size(); } /** - * @brief Takes ownership of a task. - * - * This method takes ownership of a task by moving it into the TaskResolver's internal task queue. - * After calling this method, the task will be owned and managed by the TaskResolver. - * - * @param task The task to take ownership of. After calling this method, the task object will be in a valid but unspecified state. - * - * @note After calling this method, the caller should avoid accessing or modifying the task object. - */ + * @brief Takes ownership of a task. + * + * This method takes ownership of a task by moving it into the TaskResolver's internal task queue. + * After calling this method, the task will be owned and managed by the TaskResolver. + * + * @param task The task to take ownership of. After calling this method, the task object will be in a valid but unspecified state. + * + * @note After calling this method, the caller should avoid accessing or modifying the task object. + */ void own_task(TaskPtr&& task); /** - * @brief Resolve queued tasks. - * - * @param app A pointer to the ezgl::application object representing the application instance. - */ + * @brief Resolve queued tasks. + * + * @param app A pointer to the ezgl::application object representing the application instance. + */ bool update(ezgl::application* app); /** - * @brief Extracts finished tasks from the internal task queue. - * - * This function removes finished tasks from the internal task queue and appends them to the provided vector. - * After this operation, the internal task queue will no longer hold the extracted tasks. - * - * @param tasks A reference to a vector where the finished tasks will be appended. - */ + * @brief Extracts finished tasks from the internal task queue. + * + * This function removes finished tasks from the internal task queue and appends them to the provided vector. + * After this operation, the internal task queue will no longer hold the extracted tasks. + * + * @param tasks A reference to a vector where the finished tasks will be appended. + */ void take_finished_tasks(std::vector& tasks); // helper method used in tests const std::vector& tasks() const { return m_tasks; } -private: + private: std::vector m_tasks; void process_get_path_list_task(ezgl::application*, const TaskPtr&); @@ -77,4 +77,3 @@ class TaskResolver { #endif /* NO_SERVER */ #endif /* TASKRESOLVER_H */ - diff --git a/vpr/src/server/telegrambuffer.cpp b/vpr/src/server/telegrambuffer.cpp index 0aab6af8be1..5e8a79a9a69 100644 --- a/vpr/src/server/telegrambuffer.cpp +++ b/vpr/src/server/telegrambuffer.cpp @@ -55,7 +55,7 @@ void TelegramBuffer::take_telegram_frames(std::vector& r result.push_back(telegram_frame_ptr); } else { - m_errors.push_back("wrong checkSums " + std::to_string(actual_check_sum) +" for " + header.info() + " , drop this chunk"); + m_errors.push_back("wrong checkSums " + std::to_string(actual_check_sum) + " for " + header.info() + " , drop this chunk"); } m_raw_buffer.erase(m_raw_buffer.begin(), m_raw_buffer.begin() + expected_telegram_size); m_header_opt.reset(); diff --git a/vpr/src/server/telegrambuffer.h b/vpr/src/server/telegrambuffer.h index b5822e9a5c6..f7e2abba229 100644 --- a/vpr/src/server/telegrambuffer.h +++ b/vpr/src/server/telegrambuffer.h @@ -17,20 +17,20 @@ namespace comm { * @brief Implements Telegram Buffer as a wrapper over BytesArray * * It aggregates received bytes and assists in extracting telegram frames ( @ref TelegramFrame ) from the raw byte buffer. -*/ -class TelegramBuffer -{ + */ +class TelegramBuffer { inline static const std::size_t DEFAULT_SIZE_HINT = 1024; -public: + public: /** * @brief Constructs a TelegramBuffer object with a specified size hint. * * This constructor initializes a TelegramBuffer object with a specified size hint for the raw buffer. */ - explicit TelegramBuffer(std::size_t size_hint = DEFAULT_SIZE_HINT): m_raw_buffer(size_hint) {} + explicit TelegramBuffer(std::size_t size_hint = DEFAULT_SIZE_HINT) + : m_raw_buffer(size_hint) {} - ~TelegramBuffer()=default; + ~TelegramBuffer() = default; /** * @brief Check if internal byte buffer is empty. @@ -77,7 +77,7 @@ class TelegramBuffer */ const ByteArray& data() const { return m_raw_buffer; } -private: + private: ByteArray m_raw_buffer; std::vector m_errors; std::optional m_header_opt; diff --git a/vpr/src/server/telegramframe.h b/vpr/src/server/telegramframe.h index e2237de3e36..2fc0c312a73 100644 --- a/vpr/src/server/telegramframe.h +++ b/vpr/src/server/telegramframe.h @@ -11,19 +11,19 @@ namespace comm { /** -* @brief Structure representing a TelegramFrame. -* -* A TelegramFrame consists of a TelegramHeader followed by data. -*/ + * @brief Structure representing a TelegramFrame. + * + * A TelegramFrame consists of a TelegramHeader followed by data. + */ struct TelegramFrame { /** - * @brief header The TelegramHeader containing metadata about the telegram message. - */ + * @brief header The TelegramHeader containing metadata about the telegram message. + */ TelegramHeader header; /** - * @brief body The actual data of the telegram message. - */ + * @brief body The actual data of the telegram message. + */ ByteArray body; }; using TelegramFramePtr = std::shared_ptr; diff --git a/vpr/src/server/telegramheader.h b/vpr/src/server/telegramheader.h index ffe95b04ba2..84f1adcac1d 100644 --- a/vpr/src/server/telegramheader.h +++ b/vpr/src/server/telegramheader.h @@ -25,7 +25,7 @@ namespace comm { * @note: The DATA_CHECKSUM field can be used to check the integrity of the telegram body on the client app side. */ class TelegramHeader { -public: + public: static constexpr const char SIGNATURE[] = "IPA"; static constexpr size_t SIGNATURE_SIZE = sizeof(SIGNATURE); static constexpr size_t LENGTH_SIZE = sizeof(uint32_t); @@ -36,7 +36,7 @@ class TelegramHeader { static constexpr size_t CHECKSUM_OFFSET = LENGTH_OFFSET + LENGTH_SIZE; static constexpr size_t COMPRESSORID_OFFSET = CHECKSUM_OFFSET + CHECKSUM_SIZE; - TelegramHeader()=default; + TelegramHeader() = default; /** * @brief Constructs a TelegramHeader object with the specified length, checksum, and optional compressor ID. @@ -56,7 +56,7 @@ class TelegramHeader { */ explicit TelegramHeader(const ByteArray& buffer); - ~TelegramHeader()=default; + ~TelegramHeader() = default; /** * @brief Constructs a TelegramHeader based on the provided body data. @@ -129,7 +129,7 @@ class TelegramHeader { */ std::string info() const; -private: + private: bool m_is_valid = false; ByteArray m_buffer; diff --git a/vpr/src/server/telegramoptions.cpp b/vpr/src/server/telegramoptions.cpp index fef982d1437..86c4803c0d9 100644 --- a/vpr/src/server/telegramoptions.cpp +++ b/vpr/src/server/telegramoptions.cpp @@ -8,11 +8,11 @@ #include namespace server { - + TelegramOptions::TelegramOptions(const std::string& data, const std::vector& expected_keys) { // parse data string std::vector options = vtr::split(data, ";"); - for (const std::string& option_str: options) { + for (const std::string& option_str : options) { std::vector fragments = vtr::split(option_str, ":"); if (fragments.size() == TOTAL_INDEXES_NUM) { std::string name{std::move(fragments[INDEX_NAME])}; @@ -36,14 +36,14 @@ std::map> TelegramOptions::get_map_of_sets(co std::string data_str = get_string(name); if (!data_str.empty()) { std::vector paths = vtr::split(data_str, "|"); - for (const std::string& path: paths) { + for (const std::string& path : paths) { std::vector path_struct = vtr::split(path, "#"); if (path_struct.size() == 2) { std::string path_index_str = path_struct[0]; std::string path_element_indexes_str = path_struct[1]; std::vector path_element_indexes = vtr::split(path_element_indexes_str, ","); std::set elements; - for (const std::string& path_element_index_Str: path_element_indexes) { + for (const std::string& path_element_index_Str : path_element_indexes) { if (std::optional opt_value = try_convert_to_int(path_element_index_Str)) { elements.insert(opt_value.value()); } else { @@ -91,10 +91,10 @@ bool TelegramOptions::get_bool(const std::string& name, bool fail_value) { std::string TelegramOptions::errors_str() const { std::string result; - for (const std::string& error: m_errors) { + for (const std::string& error : m_errors) { result += error + ';'; } - return result; + return result; } bool TelegramOptions::is_data_type_supported(const std::string& type) const { @@ -104,7 +104,7 @@ bool TelegramOptions::is_data_type_supported(const std::string& type) const { bool TelegramOptions::check_keys_presence(const std::vector& keys) { bool result = true; - for (const std::string& key: keys) { + for (const std::string& key : keys) { if (m_options.find(key) == m_options.end()) { m_errors.emplace_back("cannot find required option " + std::string(key)); result = false; diff --git a/vpr/src/server/telegramoptions.h b/vpr/src/server/telegramoptions.h index 41237cdde2e..576973c441f 100644 --- a/vpr/src/server/telegramoptions.h +++ b/vpr/src/server/telegramoptions.h @@ -10,19 +10,19 @@ #include namespace server { - + /** * @brief Option class Parser * * Parse the string of options in the format "TYPE:KEY1:VALUE1;TYPE:KEY2:VALUE2", * for example "int:path_num:11;string:path_type:debug;int:details_level:3;bool:is_flat_routing:0". * It provides a simple interface to check value presence and access them. -*/ + */ class TelegramOptions { -private: + private: enum { - INDEX_TYPE=0, + INDEX_TYPE = 0, INDEX_NAME, INDEX_VALUE, TOTAL_INDEXES_NUM @@ -33,7 +33,7 @@ class TelegramOptions { std::string value; }; -public: + public: /** * @brief Constructs a TelegramOptions object with the provided data and expected keys. * @@ -45,7 +45,7 @@ class TelegramOptions { * @param expected_keys A vector of strings representing the expected keys in the options. */ TelegramOptions(const std::string& data, const std::vector& expected_keys); - ~TelegramOptions()=default; + ~TelegramOptions() = default; /** * @brief Checks if there are any errors present. @@ -115,7 +115,7 @@ class TelegramOptions { */ std::string errors_str() const; -private: + private: std::unordered_map m_options; std::vector m_errors; diff --git a/vpr/src/server/telegramparser.h b/vpr/src/server/telegramparser.h index 23e942f1d9d..633c83484ce 100644 --- a/vpr/src/server/telegramparser.h +++ b/vpr/src/server/telegramparser.h @@ -15,7 +15,7 @@ namespace comm { * from a JSON schema structured as follows: {JOB_ID:num, CMD:enum, OPTIONS:string, DATA:string, STATUS:num}. */ class TelegramParser { -public: + public: /** * @brief Attempts to extract the JOB_ID field from a given message. * @@ -76,7 +76,7 @@ class TelegramParser { */ static std::optional try_extract_field_status(const std::string& message); -private: + private: static std::optional try_extract_json_value_str(const std::string& json_string, const std::string& key); }; diff --git a/vpr/src/server/zlibutils.h b/vpr/src/server/zlibutils.h index a531fe2bcc9..c9ca7cded52 100644 --- a/vpr/src/server/zlibutils.h +++ b/vpr/src/server/zlibutils.h @@ -9,31 +9,31 @@ constexpr const int BYTES_NUM_IN_32KB = 32768; /** -* @brief Compresses the input sequence using zlib. -* -* This function takes a string representing the decompressed data as input -* and compresses it using zlib. If compression is successful, the compressed -* data is returned as an optional string. If compression fails, an empty optional -* is returned. -* -* @param decompressed The input string representing the decompressed data. -* @return An optional string containing the compressed data if compression is successful, -* or an empty optional if compression fails. -*/ + * @brief Compresses the input sequence using zlib. + * + * This function takes a string representing the decompressed data as input + * and compresses it using zlib. If compression is successful, the compressed + * data is returned as an optional string. If compression fails, an empty optional + * is returned. + * + * @param decompressed The input string representing the decompressed data. + * @return An optional string containing the compressed data if compression is successful, + * or an empty optional if compression fails. + */ std::optional try_compress(const std::string& decompressed); /** -* @brief Decompresses the compressed sequence using zlib. -* -* This function takes a string representing the compressed data as input -* and decompresses it using zlib. If decompression is successful, the decompressed -* data is returned as an optional string. If decompression fails, an empty optional -* is returned. -* -* @param compressed The input string representing the compressed data. -* @return An optional string containing the decompressed data if decompression is successful, -* or an empty optional if decompression fails. -*/ + * @brief Decompresses the compressed sequence using zlib. + * + * This function takes a string representing the compressed data as input + * and decompresses it using zlib. If decompression is successful, the decompressed + * data is returned as an optional string. If decompression fails, an empty optional + * is returned. + * + * @param compressed The input string representing the compressed data. + * @return An optional string containing the decompressed data if decompression is successful, + * or an empty optional if decompression fails. + */ std::optional try_decompress(const std::string& compressed); #endif /* NO_SERVER */ diff --git a/vpr/src/tileable_rr_graph/chan_node_details.h b/vpr/src/tileable_rr_graph/chan_node_details.h index 6768f84ebf0..d0a2793416b 100644 --- a/vpr/src/tileable_rr_graph/chan_node_details.h +++ b/vpr/src/tileable_rr_graph/chan_node_details.h @@ -70,7 +70,7 @@ class ChanNodeDetails { std::vector seg_length_; /* Length of each segment */ std::vector track_start_; /* flag to identify if this is the starting point of the track */ std::vector track_end_; /* flag to identify if this is the ending point of the track */ - std::vector track_bend_start_; /* flag to identify if this is the starting point of the track after bend. 0 means it is not a bend start. Int number means the corresponding bend group */ + std::vector track_bend_start_; /* flag to identify if this is the starting point of the track after bend. 0 means it is not a bend start. Int number means the corresponding bend group */ std::vector track_bend_end_; }; diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp index 66ab365b42a..7b631e799ca 100644 --- a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp @@ -18,8 +18,8 @@ void DeviceGridAnnotation::init(const DeviceGrid& grid, const bool& perimeter_cb size_t start_x = 1; size_t end_x = grid.width() - 1; if (perimeter_cb) { - start_x = 0; - end_x = grid.width(); + start_x = 0; + end_x = grid.width(); } for (size_t iy = 0; iy < grid.height() - 1; ++iy) { for (size_t ix = start_x; ix < end_x; ++ix) { @@ -29,8 +29,8 @@ void DeviceGridAnnotation::init(const DeviceGrid& grid, const bool& perimeter_cb size_t start_y = 1; size_t end_y = grid.height() - 1; if (perimeter_cb) { - start_y = 0; - end_y = grid.height(); + start_y = 0; + end_y = grid.height(); } for (size_t ix = 0; ix < grid.width() - 1; ++ix) { for (size_t iy = start_y; iy < end_y; ++iy) { diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp index a73ff2f15d5..986339d96a9 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -74,8 +74,8 @@ std::vector get_rr_graph_driver_switches(const RRGraphView& rr_graph std::vector driver_switches; for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { - if (driver_switches.end() == std::find(driver_switches.begin(), driver_switches.end(), rr_graph.edge_switch(edge))) { - driver_switches.push_back(rr_graph.edge_switch(edge)); + if (driver_switches.end() == std::find(driver_switches.begin(), driver_switches.end(), RRSwitchId(rr_graph.edge_switch(edge)))) { + driver_switches.push_back(RRSwitchId(rr_graph.edge_switch(edge))); } } diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 3b9e21bab9b..9bd38254b69 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -44,9 +44,9 @@ int get_grid_pin_class_index(const DeviceGrid& grids, /* Deteremine the side of a io grid */ std::vector determine_io_grid_pin_side(const vtr::Point& device_size, - const vtr::Point& grid_coordinate, - const bool& perimeter_cb) { - std::vector pin_sides; + const vtr::Point& grid_coordinate, + const bool& perimeter_cb) { + std::vector pin_sides; /* TOP side IO of FPGA */ if (device_size.y() == grid_coordinate.y()) { /* Such I/O has only bottom side pins */ @@ -64,7 +64,7 @@ std::vector determine_io_grid_pin_side(const vtr::Point& device_ pin_sides.push_back(TOP); pin_sides.push_back(BOTTOM); } - } else if (0 == grid_coordinate.y()) { /* BOTTOM side IO of FPGA */ + } else if (0 == grid_coordinate.y()) { /* BOTTOM side IO of FPGA */ /* Such I/O has only Top side pins */ pin_sides.push_back(TOP); /* If cbs are allowed around boundary I/Os, add two more sides */ @@ -72,7 +72,7 @@ std::vector determine_io_grid_pin_side(const vtr::Point& device_ pin_sides.push_back(LEFT); pin_sides.push_back(RIGHT); } - } else if (0 == grid_coordinate.x()) { /* LEFT side IO of FPGA */ + } else if (0 == grid_coordinate.x()) { /* LEFT side IO of FPGA */ /* Such I/O has only Right side pins */ pin_sides.push_back(RIGHT); /* If cbs are allowed around boundary I/Os, add two more sides */ @@ -89,8 +89,8 @@ std::vector determine_io_grid_pin_side(const vtr::Point& device_ grid_coordinate.x(), grid_coordinate.y(), device_size.x(), device_size.y()); exit(1); - } - return pin_sides; + } + return pin_sides; } /* Deteremine the side of a pin of a grid */ @@ -227,8 +227,8 @@ bool is_chanx_exist(const DeviceGrid& grids, size_t chanx_start = 1; size_t chanx_end = grids.width() - 2; if (perimeter_cb) { - chanx_start = 0; - chanx_end = grids.width() - 1; + chanx_start = 0; + chanx_end = grids.width() - 1; } if ((chanx_start > chanx_coord.x()) || (chanx_coord.x() > chanx_end)) { return false; @@ -273,8 +273,8 @@ bool is_chany_exist(const DeviceGrid& grids, size_t chany_start = 1; size_t chany_end = grids.height() - 2; if (perimeter_cb) { - chany_start = 0; - chany_end = grids.height() - 1; + chany_start = 0; + chany_end = grids.height() - 1; } if (chany_coord.x() > grids.width() - 2) { return false; @@ -311,9 +311,9 @@ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, const bool& through_channel) { size_t start_x = 1; if (perimeter_cb) { - start_x = 0; + start_x = 0; } else { - VTR_ASSERT(0 < chanx_coord.x()); + VTR_ASSERT(0 < chanx_coord.x()); } if (start_x == chanx_coord.x()) { /* This is already the LEFT side of FPGA fabric, @@ -354,7 +354,7 @@ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, VTR_ASSERT(chanx_coord.x() <= grids.width() - 1); size_t end_x = grids.width() - 2; if (perimeter_cb) { - end_x = grids.width() - 1; + end_x = grids.width() - 1; } if (end_x == chanx_coord.x()) { @@ -400,9 +400,9 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, const bool& through_channel) { size_t start_y = 1; if (perimeter_cb) { - start_y = 0; + start_y = 0; } else { - VTR_ASSERT(0 < chany_coord.y()); + VTR_ASSERT(0 < chany_coord.y()); } if (start_y == chany_coord.y()) { /* This is already the BOTTOM side of FPGA fabric, @@ -448,7 +448,7 @@ bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, VTR_ASSERT(chany_coord.y() <= grids.height() - 1); size_t end_y = grids.height() - 2; if (perimeter_cb) { - end_y = grids.height() - 1; + end_y = grids.height() - 1; } if (end_y == chany_coord.y()) { diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index c73ebb8206f..e1869ed4d4a 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -28,8 +28,8 @@ std::vector find_grid_pin_sides(const DeviceGrid& grids, const size_t& pin_id); std::vector determine_io_grid_pin_side(const vtr::Point& device_size, - const vtr::Point& grid_coordinate, - const bool& perimeter_cb); + const vtr::Point& grid_coordinate, + const bool& perimeter_cb); std::vector get_grid_side_pins(const DeviceGrid& grids, const size_t& layer, diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index 9698ac03b45..7816e46134c 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -23,7 +23,7 @@ std::vector find_rr_graph_switches(const RRGraphView& rr_graph, * and update the switch list */ for (auto edge : edges) { - switches.push_back(rr_graph.edge_switch(edge)); + switches.push_back(RRSwitchId(rr_graph.edge_switch(edge))); } return switches; @@ -102,7 +102,7 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, /* Ensure that (x, y) is a valid location in grids */ if (size_t(x) > device_grid.width() - 1 || size_t(y) > device_grid.height() - 1) { - return indices; + return indices; } /* Ensure we have a valid side */ @@ -112,7 +112,7 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, t_physical_tile_loc tile_loc(x, y, layer); int width_offset = device_grid.get_width_offset(tile_loc); int height_offset = device_grid.get_height_offset(tile_loc); - + for (int pin = 0; pin < device_grid.get_physical_type(tile_loc)->num_pins; ++pin) { /* Skip those pins have been ignored during rr_graph build-up */ if (true == device_grid.get_physical_type(tile_loc)->is_ignored_pin[pin]) { diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 36663b21e2a..58c721a06b1 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -30,7 +30,7 @@ RRGSB::RRGSB() { medium_node_.clear(); for (size_t icb_type = 0; icb_type < 2; icb_type++) { - for (size_t iside = 0; iside < NUM_2D_SIDES; iside++) { + for (size_t iside = 0; iside < NUM_2D_SIDES; iside++) { cb_opin_node_[icb_type][iside].clear(); } } @@ -475,7 +475,7 @@ bool RRGSB::is_medium_node(const RRNodeId& node) const { } return false; } - + bool RRGSB::is_chan_node(const RRNodeId& node) const { std::vector sides = {TOP, RIGHT, BOTTOM, LEFT}; for (e_side side : sides) { @@ -965,7 +965,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, const RRNodeId& src_node = rr_graph.edge_src_node(edge); /* In this part, we only sort routing track nodes. IPIN nodes will be handled later */ if (CHANX != rr_graph.node_type(src_node) && CHANY != rr_graph.node_type(src_node)) { - continue; + continue; } /* The driver routing channel node can be either an input or an output to the GSB. * Just try to find a qualified one. */ @@ -1008,7 +1008,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, const RRNodeId& src_node = rr_graph.edge_src_node(edge); /* In this part, we only sort routing track nodes. IPIN nodes will be handled later */ if (OPIN != rr_graph.node_type(src_node)) { - continue; + continue; } enum e_side cb_opin_side = NUM_2D_SIDES; int cb_opin_index = -1; @@ -1073,45 +1073,44 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph) { } void RRGSB::build_cb_opin_nodes(const RRGraphView& rr_graph) { - for (t_rr_type cb_type : {CHANX, CHANY}) { - size_t icb_type = cb_type == CHANX ? 0 : 1; - std::vector cb_ipin_sides = get_cb_ipin_sides(cb_type); - for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { - enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < get_num_ipin_nodes(cb_ipin_side); - ++inode) { - std::vector driver_rr_edges = - get_ipin_node_in_edges(rr_graph, cb_ipin_side, inode); - for (const RREdgeId curr_edge : driver_rr_edges) { - RRNodeId cand_node = rr_graph.edge_src_node(curr_edge); - if (OPIN != rr_graph.node_type(cand_node)) { - continue; - } - enum e_side cb_opin_side = NUM_2D_SIDES; - int cb_opin_index = -1; - get_node_side_and_index(rr_graph, cand_node, IN_PORT, cb_opin_side, - cb_opin_index); - if ((-1 == cb_opin_index) || (NUM_2D_SIDES == cb_opin_side)) { - VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); - VTR_LOG("----------------------------------\n"); - VTR_LOG("SRC node:\n"); - VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(cand_node).c_str()); - VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(cand_node)); - VTR_LOG("Fan-out nodes:\n"); - for (const auto& temp_edge : rr_graph.edge_range(cand_node)) { - VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); - } - } - VTR_ASSERT((-1 != cb_opin_index) && (NUM_2D_SIDES != cb_opin_side)); - - if (cb_opin_node_[icb_type][size_t(cb_opin_side)].end() == - std::find(cb_opin_node_[icb_type][size_t(cb_opin_side)].begin(), cb_opin_node_[icb_type][size_t(cb_opin_side)].end(), cand_node)) { - cb_opin_node_[icb_type][size_t(cb_opin_side)].push_back(cand_node); - } + for (t_rr_type cb_type : {CHANX, CHANY}) { + size_t icb_type = cb_type == CHANX ? 0 : 1; + std::vector cb_ipin_sides = get_cb_ipin_sides(cb_type); + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < get_num_ipin_nodes(cb_ipin_side); + ++inode) { + std::vector driver_rr_edges = + get_ipin_node_in_edges(rr_graph, cb_ipin_side, inode); + for (const RREdgeId curr_edge : driver_rr_edges) { + RRNodeId cand_node = rr_graph.edge_src_node(curr_edge); + if (OPIN != rr_graph.node_type(cand_node)) { + continue; + } + enum e_side cb_opin_side = NUM_2D_SIDES; + int cb_opin_index = -1; + get_node_side_and_index(rr_graph, cand_node, IN_PORT, cb_opin_side, + cb_opin_index); + if ((-1 == cb_opin_index) || (NUM_2D_SIDES == cb_opin_side)) { + VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); + VTR_LOG("----------------------------------\n"); + VTR_LOG("SRC node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(cand_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(cand_node)); + VTR_LOG("Fan-out nodes:\n"); + for (const auto& temp_edge : rr_graph.edge_range(cand_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); + } + } + VTR_ASSERT((-1 != cb_opin_index) && (NUM_2D_SIDES != cb_opin_side)); + + if (cb_opin_node_[icb_type][size_t(cb_opin_side)].end() == std::find(cb_opin_node_[icb_type][size_t(cb_opin_side)].begin(), cb_opin_node_[icb_type][size_t(cb_opin_side)].end(), cand_node)) { + cb_opin_node_[icb_type][size_t(cb_opin_side)].push_back(cand_node); + } + } + } } - } } - } } /************************************************************************ diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 37b2dcc6f9d..30d8e80372b 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -232,6 +232,7 @@ class RRGSB { void sort_ipin_node_in_edges(const RRGraphView& rr_graph, const e_side& chan_side, const size_t& ipin_id); + private: /* internal functions */ size_t get_track_id_first_short_connection(const RRGraphView& rr_graph, const e_side& node_side) const; diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp index c1334d81d96..084dd9d67d2 100644 --- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp @@ -26,18 +26,21 @@ std::vector get_num_tracks_per_seg_type(const size_t& chan_width, const std::vector& segment_inf, const bool& use_full_seg_groups) { - std::vector result; - std::vector demand; - /* Make sure a clean start */ - result.resize(segment_inf.size()); - demand.resize(segment_inf.size()); + + const size_t num_segments = segment_inf.size(); + std::vector result(num_segments); + std::vector demand(num_segments); + + if (segment_inf.empty()) { + return result; + } /* Scale factor so we can divide by any length * and still use integers */ /* Get the sum of frequency */ size_t scale = 1; size_t freq_sum = 0; - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + for (size_t iseg = 0; iseg < num_segments; ++iseg) { scale *= segment_inf[iseg].length; freq_sum += segment_inf[iseg].frequency; } @@ -47,7 +50,7 @@ std::vector get_num_tracks_per_seg_type(const size_t& chan_width, /* Get the fraction of each segment type considering the frequency: * num_track_per_seg = chan_width * (freq_of_seg / sum_freq) */ - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + for (size_t iseg = 0; iseg < num_segments; ++iseg) { result[iseg] = 0; demand[iseg] = scale * chan_width * segment_inf[iseg].frequency; if (true == use_full_seg_groups) { @@ -63,7 +66,7 @@ std::vector get_num_tracks_per_seg_type(const size_t& chan_width, while (assigned < chan_width) { /* Find current maximum demand */ double max = 0; - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + for (size_t iseg = 0; iseg < num_segments; ++iseg) { if (demand[iseg] > max) { imax = iseg; } @@ -179,9 +182,9 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, /* Add node to ChanNodeDetails */ size_t cur_track = 0; - size_t bend_num = 0; // The index for bend segments + size_t bend_num = 0; // The index for bend segments for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - if (!segment_inf[iseg].isbend){ + if (!segment_inf[iseg].isbend) { /* segment length will be set to maxium segment length if this is a longwire */ size_t seg_len = segment_inf[iseg].length; if (true == segment_inf[iseg].longline) { @@ -208,34 +211,33 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len, seg_start, seg_end); cur_track++; } - } - else{ // bend segment + } else { // bend segment bend_num++; VTR_ASSERT(segment_inf[iseg].isbend); std::vector seg_len = segment_inf[iseg].part_len; std::vector bend = segment_inf[iseg].bend; - VTR_ASSERT(seg_len.size() == 2); // Only support one bend position for a segment. - + VTR_ASSERT(seg_len.size() == 2); // Only support one bend position for a segment. + std::vector num_tracks_bend; /* Each bend part tracks number * - * For example, a length-5 segment with bend pattern: <- - U -> has 20 tracks. * - * Its num_tracks_bend is [20 * 3/5, 20 * 2/5] = [12, 8] */ - for(size_t i = 0; i < seg_len.size(); i++) - num_tracks_bend.push_back(num_tracks[iseg] * seg_len[i] / segment_inf[iseg].length); - + * For example, a length-5 segment with bend pattern: <- - U -> has 20 tracks. * + * Its num_tracks_bend is [20 * 3/5, 20 * 2/5] = [12, 8] */ + for (size_t i = 0; i < seg_len.size(); i++) + num_tracks_bend.push_back(num_tracks[iseg] * seg_len[i] / segment_inf[iseg].length); + VTR_ASSERT(num_tracks_bend[0] + num_tracks_bend[1] == num_tracks[iseg]); for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) { bool seg_start = false; bool seg_end = false; - size_t seg_bend_start = 0; // seg_bend_start = 0 means not a bend start. + size_t seg_bend_start = 0; // seg_bend_start = 0 means not a bend start. // seg_bend_start = i (i > 0) means a bend start for bend segment i. size_t seg_bend_end = 0; // The same as seg_bend_start. - // Tracks has same seg_bend_start and seg_bend_end values will be + // Tracks has same seg_bend_start and seg_bend_end values will be // connected by a delayless switch. /* Every first track of a group of Length-N wires, we set a starting point */ if (0 == itrack % segment_inf[iseg].length) { - seg_start = true; + seg_start = true; } /* Number seg_len[0] track of a group of Length-N wires, we set a bend start point */ if (seg_len[0] == int(itrack) % segment_inf[iseg].length) { @@ -260,56 +262,56 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); cur_track++; } - + /*for (size_t itrack = 0; itrack < num_tracks_bend[0]; ++itrack) { - - bool seg_start = false; - bool seg_end = false; - size_t seg_bend_start = 0; - size_t seg_bend_end = 0; - - if (0 == itrack % seg_len[0]) { - seg_start = true; - } - - if ((seg_len[0] - 1 == itrack % seg_len[0]) - || (itrack == num_tracks_bend[0] - 1)) { - seg_end = true; - seg_bend_end = bend_num; - } - int seg_index = segment_inf[iseg].seg_index; - - chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); - cur_track++; - chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); - cur_track++; - - } - for (size_t itrack = 0; itrack < num_tracks_bend[1]; ++itrack) { - - bool seg_start = false; - bool seg_end = false; - size_t seg_bend_start = 0; - size_t seg_bend_end = 0; - - if (0 == itrack % seg_len[1]) { - seg_start = true; - seg_bend_start = bend_num; - } - - if ((seg_len[1] - 1 == itrack % seg_len[1]) - || (itrack == num_tracks_bend[1] - 1)) { - seg_end = true; - } - int seg_index = segment_inf[iseg].seg_index; - - chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[1], seg_start, seg_end, seg_bend_start, seg_bend_end); - cur_track++; - - chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[1], seg_start, seg_end, seg_bend_start, seg_bend_end); - cur_track++; - - }*/ + * + * bool seg_start = false; + * bool seg_end = false; + * size_t seg_bend_start = 0; + * size_t seg_bend_end = 0; + * + * if (0 == itrack % seg_len[0]) { + * seg_start = true; + * } + * + * if ((seg_len[0] - 1 == itrack % seg_len[0]) + * || (itrack == num_tracks_bend[0] - 1)) { + * seg_end = true; + * seg_bend_end = bend_num; + * } + * int seg_index = segment_inf[iseg].seg_index; + * + * chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); + * cur_track++; + * chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); + * cur_track++; + * + * } + * for (size_t itrack = 0; itrack < num_tracks_bend[1]; ++itrack) { + * + * bool seg_start = false; + * bool seg_end = false; + * size_t seg_bend_start = 0; + * size_t seg_bend_end = 0; + * + * if (0 == itrack % seg_len[1]) { + * seg_start = true; + * seg_bend_start = bend_num; + * } + * + * if ((seg_len[1] - 1 == itrack % seg_len[1]) + * || (itrack == num_tracks_bend[1] - 1)) { + * seg_end = true; + * } + * int seg_index = segment_inf[iseg].seg_index; + * + * chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[1], seg_start, seg_end, seg_bend_start, seg_bend_end); + * cur_track++; + * + * chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[1], seg_start, seg_end, seg_bend_start, seg_bend_end); + * cur_track++; + * + * }*/ } } /* Check if all the tracks have been satisified */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index d8ead463d9e..f911c8861d7 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -220,7 +220,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ * Should use tileable version so that we have can have full control */ std::vector num_tracks = get_num_tracks_per_seg_type(max_chan_width / 2, segment_inf, false); - int* sets_per_seg_type = (int*)vtr::malloc(sizeof(int) * segment_inf.size()); + std::vector sets_per_seg_type(segment_inf.size()); VTR_ASSERT(num_tracks.size() == segment_inf.size()); for (size_t iseg = 0; iseg < num_tracks.size(); ++iseg) { sets_per_seg_type[iseg] = num_tracks[iseg]; @@ -272,10 +272,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ * TODO: use tile direct builder ***********************************************************************/ /* Create data structure of direct-connections */ - t_clb_to_clb_directs* clb_to_clb_directs = NULL; - if (!directs.empty()) { - clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, delayless_switch); - } + auto clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, delayless_switch); std::vector clb2clb_directs; for (size_t idirect = 0; idirect < directs.size(); ++idirect) { /* Sanity checks on rr switch id */ @@ -323,15 +320,5 @@ void build_tileable_unidir_rr_graph(const std::vector& typ /* No clock network support yet; Does not support flatten rr_graph yet */ - check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, vib_grid, device_ctx.chan_width, GRAPH_UNIDIR, false); - - - /************************************************************************ - * Free all temp stucts - ***********************************************************************/ - free(sets_per_seg_type); - - if (nullptr != clb_to_clb_directs) { - free(clb_to_clb_directs); - } + check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, vib_grid, device_ctx.chan_width, e_graph_type::UNIDIR_TILEABLE, false); } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index d242a0b9bf1..4b32fcab7cf 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -136,8 +136,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, segment_inf_y, perimeter_cb, delayless_switch); - } - else { + } else { build_rr_graph_regular_edges(rr_graph, rr_graph_builder, rr_node_driver_switches, @@ -171,7 +170,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // for (size_t iy = 0; iy < vib_grid.height(); iy++) { // std::map mux_name_map; - + // for (size_t i_mux = 0; i_mux < vib_grid.num_medium_nodes(i_layer, ix, iy); i_mux++) { // mux_name_map.emplace(vib_grid.medium_node_name(i_layer, ix, iy, i_mux), i_mux); // } @@ -179,10 +178,9 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // } // } // } - + // } - - + // size_t num_edges_to_create = 0; // /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ // build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); @@ -212,7 +210,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // t_vib_map vib_map; // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, gsb_coord, medium_mux_name2medium_index); // build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); - + // rr_graph_builder.build_edges(true); // } // else { @@ -254,7 +252,6 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // device_chan_width, segment_inf_x, segment_inf_y, // layer, gsb_coord, perimeter_cb); - // t_vib_map vib_map; // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); @@ -267,7 +264,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // } // num_edges_to_create += edge_count; // //rr_graph_builder.build_edges(true); - + // } // // process right boundary @@ -281,7 +278,6 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // device_chan_width, segment_inf_x, segment_inf_y, // layer, gsb_coord, perimeter_cb); - // t_vib_map vib_map; // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); @@ -294,7 +290,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // } // num_edges_to_create += edge_count; // //rr_graph_builder.build_edges(true); - + // } // // process right-top corner @@ -309,7 +305,6 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // device_chan_width, segment_inf_x, segment_inf_y, // layer, gsb_coord, perimeter_cb); - // t_vib_map vib_map; // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); @@ -379,7 +374,7 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, // for (size_t iy = 0; iy < vib_grid.height(); iy++) { // std::map mux_name_map; - + // for (size_t i_mux = 0; i_mux < vib_grid.num_medium_nodes(i_layer, ix, iy); i_mux++) { // mux_name_map.emplace(vib_grid.medium_node_name(i_layer, ix, iy, i_mux), i_mux); // } @@ -413,13 +408,12 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, device_chan_width, segment_inf_x, segment_inf_y, layer, gsb_coord, perimeter_cb); - t_vib_map vib_map; vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, gsb_coord); build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); - + rr_graph_builder.build_edges(true); - + // else { // /* adapt the track_to_ipin_lookup for the GSB nodes */ // t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ @@ -446,10 +440,10 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, } /* Process boundary */ - + size_t ix, iy; // process top boundary - iy = gsb_range.y() + 1; // == grids.height() - 1 + iy = gsb_range.y() + 1; // == grids.height() - 1 for (ix = 0; ix < gsb_range.x() + 1; ++ix) { vtr::Point actual_coord(ix, iy); vtr::Point gsb_coord(ix, iy - 1); @@ -459,7 +453,6 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, device_chan_width, segment_inf_x, segment_inf_y, layer, gsb_coord, perimeter_cb); - t_vib_map vib_map; vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord); //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); @@ -472,7 +465,6 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, } num_edges_to_create += edge_count; //rr_graph_builder.build_edges(true); - } // process right boundary @@ -486,7 +478,6 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, device_chan_width, segment_inf_x, segment_inf_y, layer, gsb_coord, perimeter_cb); - t_vib_map vib_map; vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord); //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); @@ -499,7 +490,6 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, } num_edges_to_create += edge_count; //rr_graph_builder.build_edges(true); - } // process right-top corner @@ -514,7 +504,6 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, // device_chan_width, segment_inf_x, segment_inf_y, // layer, gsb_coord, perimeter_cb); - // t_vib_map vib_map; // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); @@ -527,7 +516,6 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, // } // num_edges_to_create += edge_count; rr_graph_builder.build_edges(true); - } void build_rr_graph_regular_edges(const RRGraphView& rr_graph, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index a0e8494718a..c76320b29c3 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -535,19 +535,19 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, } t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, - RRGraphBuilder& rr_graph_builder, + RRGraphBuilder& rr_graph_builder, const RRGraphView& rr_graph, const std::vector& segment_inf, const size_t& layer, const vtr::Point& gsb_coordinate, const RRSwitchId& delayless_switch, vtr::vector& rr_node_driver_switches) { - + std::vector>>> chan_rr_nodes_all_sides; //[side][bend_num][start/end][node] chan_rr_nodes_all_sides.resize(4); int bend_seg_num = 0; - std::vector bend_seg_type; //bend type: 1: U; 2: D + std::vector bend_seg_type; //bend type: 1: U; 2: D for (size_t iseg = 0; iseg < segment_inf.size(); iseg++) { if (segment_inf[iseg].isbend) { bend_seg_num++; @@ -562,24 +562,24 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, } VTR_ASSERT(bend_seg_num == int(bend_seg_type.size())); for (size_t side = 0; side < 4; ++side) { - std::vector rr_nodes; + std::vector rr_nodes; switch (side) { case TOP: /* TOP = 0 */ /* For the bording, we should take special care */ if (gsb_coordinate.y() == grids.height() - 2) { - + break; } chan_rr_nodes_all_sides[0].resize(bend_seg_num); - for (int i = 0; i < bend_seg_num; i++){ + for (int i = 0; i < bend_seg_num; i++) { chan_rr_nodes_all_sides[0][i].resize(2); //start/end track for bend } - + rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, CHANY); - + for (auto inode : rr_nodes) { VTR_ASSERT(rr_graph.node_type(inode) == CHANY); Direction direction = rr_graph.node_direction(inode); @@ -597,26 +597,25 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, VTR_ASSERT(bend_start == 0); chan_rr_nodes_all_sides[0][bend_end - 1][1].push_back(inode); } - } - + break; case RIGHT: /* RIGHT = 1 */ /* For the bording, we should take special care */ if (gsb_coordinate.x() == grids.width() - 2) { - + break; } - + chan_rr_nodes_all_sides[1].resize(bend_seg_num); - for (int i = 0; i < bend_seg_num; i++){ + for (int i = 0; i < bend_seg_num; i++) { chan_rr_nodes_all_sides[1][i].resize(2); //start/end track for bend } - + rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), CHANX); - + for (auto inode : rr_nodes) { VTR_ASSERT(rr_graph.node_type(inode) == CHANX); Direction direction = rr_graph.node_direction(inode); @@ -634,25 +633,24 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, VTR_ASSERT(bend_start == 0); chan_rr_nodes_all_sides[1][bend_end - 1][1].push_back(inode); } - } break; case BOTTOM: /* BOTTOM = 2 */ /* For the bording, we should take special care */ if (gsb_coordinate.y() == 0) { - + break; } - + chan_rr_nodes_all_sides[2].resize(bend_seg_num); - for (int i = 0; i < bend_seg_num; i++){ + for (int i = 0; i < bend_seg_num; i++) { chan_rr_nodes_all_sides[2][i].resize(2); //start/end track for bend } - + rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x(), gsb_coordinate.y(), CHANY); - + for (auto inode : rr_nodes) { VTR_ASSERT(rr_graph.node_type(inode) == CHANY); Direction direction = rr_graph.node_direction(inode); @@ -670,25 +668,24 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, VTR_ASSERT(bend_end == 0); chan_rr_nodes_all_sides[2][bend_start - 1][0].push_back(inode); } - } break; case LEFT: /* BOTTOM = 2 */ /* For the bording, we should take special care */ if (gsb_coordinate.x() == 0) { - + break; } - + chan_rr_nodes_all_sides[3].resize(bend_seg_num); - for (int i = 0; i < bend_seg_num; i++){ + for (int i = 0; i < bend_seg_num; i++) { chan_rr_nodes_all_sides[3][i].resize(2); //start/end track for bend } - + rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x(), gsb_coordinate.y(), CHANX); - + for (auto inode : rr_nodes) { VTR_ASSERT(rr_graph.node_type(inode) == CHANX); Direction direction = rr_graph.node_direction(inode); @@ -706,71 +703,65 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, VTR_ASSERT(bend_end == 0); chan_rr_nodes_all_sides[3][bend_start - 1][0].push_back(inode); } - } break; default: VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid side index!\n"); exit(1); - } } std::map bend_seg_head2bend_seg_end_map; for (size_t ibend_seg = 0; ibend_seg < (size_t)bend_seg_num; ibend_seg++) { - int bend_type = bend_seg_type[ibend_seg]; //bend_type 1:U 2:D + int bend_type = bend_seg_type[ibend_seg]; //bend_type 1:U 2:D VTR_ASSERT(bend_type == 1 || bend_type == 2); - if (bend_type == 1) { //bend type U - for (size_t side = 0; side < 4; side++){ + if (bend_type == 1) { //bend type U + for (size_t side = 0; side < 4; side++) { size_t to_side = (side + 1) % 4; if (chan_rr_nodes_all_sides[side].size() > 0) for (size_t inode = 0; inode < chan_rr_nodes_all_sides[side][ibend_seg][1].size(); inode++) { - + if (chan_rr_nodes_all_sides[to_side].size() > 0) { VTR_ASSERT(chan_rr_nodes_all_sides[side][ibend_seg][1].size() == chan_rr_nodes_all_sides[to_side][ibend_seg][0].size()); bend_seg_head2bend_seg_end_map.emplace(std::make_pair(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode])); rr_node_driver_switches[chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode]] = delayless_switch; - } - else { + } else { rr_graph_builder.set_node_bend_end(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], 0); - } + } } else { if (chan_rr_nodes_all_sides[to_side].size() > 0) { for (size_t inode = 0; inode < chan_rr_nodes_all_sides[to_side][ibend_seg][0].size(); inode++) { - rr_graph_builder.set_node_bend_start(chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode], 0); + rr_graph_builder.set_node_bend_start(chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode], 0); } } } } - - } - else if (bend_type == 2) { //bend type D - for (size_t side = 0; side < 4; side++){ + + } else if (bend_type == 2) { //bend type D + for (size_t side = 0; side < 4; side++) { size_t to_side = (side + 3) % 4; if (chan_rr_nodes_all_sides[side].size() > 0) for (size_t inode = 0; inode < chan_rr_nodes_all_sides[side][ibend_seg][1].size(); inode++) { - + if (chan_rr_nodes_all_sides[to_side].size() > 0) { VTR_ASSERT(chan_rr_nodes_all_sides[side][ibend_seg][1].size() == chan_rr_nodes_all_sides[to_side][ibend_seg][0].size()); bend_seg_head2bend_seg_end_map.emplace(std::make_pair(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode])); rr_node_driver_switches[chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode]] = delayless_switch; - } - else { + } else { rr_graph_builder.set_node_bend_end(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], 0); - } + } } else { if (chan_rr_nodes_all_sides[to_side].size() > 0) { for (size_t inode = 0; inode < chan_rr_nodes_all_sides[to_side][ibend_seg][0].size(); inode++) { - rr_graph_builder.set_node_bend_start(chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode], 0); + rr_graph_builder.set_node_bend_start(chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode], 0); } } } } } - } return bend_seg_head2bend_seg_end_map; @@ -961,7 +952,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - if (!perimeter_cb && gsb_coordinate.y() == 0) { + if (!perimeter_cb && gsb_coordinate.y() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -990,7 +981,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - if (!perimeter_cb && gsb_coordinate.x() == 0) { + if (!perimeter_cb && gsb_coordinate.x() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -1806,7 +1797,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, const vtr::Point& gsb_coordinate, const vtr::Point& actual_coordinate) { VTR_ASSERT(rr_gsb.get_x() == gsb_coordinate.x() && rr_gsb.get_y() == gsb_coordinate.y()); - + t_vib_map vib_map; const VibInf* vib = vib_grid.get_vib(layer, actual_coordinate.x(), actual_coordinate.y()); @@ -1821,17 +1812,17 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, for (auto from : froms) { RRNodeId from_node; if (from.from_type == PB) { - + if (from.type_name != vib->get_pbtype_name()) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong from type name!\n"); exit(1); } - + for (e_side side : TOTAL_2D_SIDES) { from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); if (from_node.is_valid()) - break; + break; } if (!from_node.is_valid()) { VTR_LOGF_WARN(__FILE__, __LINE__, @@ -1840,11 +1831,10 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } if (!rr_gsb.is_opin_node(from_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, - "Opin node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + "Opin node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } - } - else if (from.from_type == SEGMENT) { + } else if (from.from_type == SEGMENT) { char from_dir = from.seg_dir; //int from_index = from.seg_index; t_segment_inf segment = segment_inf[from.type_index]; @@ -1858,10 +1848,14 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } VTR_ASSERT(from.seg_index < seg_group.track_num * segment.length); e_side side; - if (from_dir == 'W') side = RIGHT; - else if (from_dir == 'E') side = LEFT; - else if (from_dir == 'N') side = BOTTOM; - else if (from_dir == 'S') side = TOP; + if (from_dir == 'W') + side = RIGHT; + else if (from_dir == 'E') + side = LEFT; + else if (from_dir == 'N') + side = BOTTOM; + else if (from_dir == 'S') + side = TOP; else { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong segment from direction!\n"); @@ -1869,14 +1863,14 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(side, RRSegmentId(segment.seg_index)); - if (track_list.size() == 0) continue; + if (track_list.size() == 0) + continue; else { VTR_ASSERT((int)track_list.size() >= (from.seg_index + 1) * 2); size_t seg_id; - if (side == LEFT || side == BOTTOM) { //INC + if (side == LEFT || side == BOTTOM) { //INC seg_id = from.seg_index * 2; - } - else { //DEC + } else { //DEC VTR_ASSERT(side == RIGHT || side == TOP); seg_id = from.seg_index * 2 + 1; } @@ -1887,21 +1881,17 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, "Wire node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } - } - - } - else if (from.from_type == MUX) { + } else if (from.from_type == MUX) { size_t from_mux_index = vib->medium_mux_index_by_name(from.type_name); from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); if (!rr_gsb.is_medium_node(from_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, - "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } - } - else { + } else { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong from type!\n"); exit(1); @@ -1918,8 +1908,6 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, to_nodes.push_back(to_node); vib_map.emplace(std::make_pair(from_node, to_nodes)); } - - } } /* Second stages*/ @@ -1927,22 +1915,22 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, for (size_t i_second_stage = 0; i_second_stage < second_stages.size(); i_second_stage++) { std::vector froms = second_stages[i_second_stage].froms; std::vector tos = second_stages[i_second_stage].to; - + std::vector to_nodes; for (auto to : tos) { RRNodeId to_node; if (to.from_type == PB) { - + if (to.type_name != vib->get_pbtype_name()) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong to type name!\n"); exit(1); } - + for (e_side side : TOTAL_2D_SIDES) { to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), IPIN, to.phy_pin_index, side); if (to_node.is_valid()) - break; + break; } if (!to_node.is_valid()) { VTR_LOGF_WARN(__FILE__, __LINE__, @@ -1951,11 +1939,10 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } if (!rr_gsb.is_ipin_node(to_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, - "Medium node %d is not in the GSB (%d, %d)\n", to_node, rr_gsb.get_x(), rr_gsb.get_y()); + "Medium node %d is not in the GSB (%d, %d)\n", to_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } - } - else if (to.from_type == SEGMENT) { + } else if (to.from_type == SEGMENT) { char to_dir = to.seg_dir; //int from_index = from.seg_index; t_segment_inf segment = segment_inf[to.type_index]; @@ -1969,10 +1956,14 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } VTR_ASSERT(to.seg_index < seg_group.track_num * segment.length); e_side side; - if (to_dir == 'W') side = LEFT; - else if (to_dir == 'E') side = RIGHT; - else if (to_dir == 'N') side = TOP; - else if (to_dir == 'S') side = BOTTOM; + if (to_dir == 'W') + side = LEFT; + else if (to_dir == 'E') + side = RIGHT; + else if (to_dir == 'N') + side = TOP; + else if (to_dir == 'S') + side = BOTTOM; else { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong segment from direction!\n"); @@ -1980,15 +1971,15 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(side, RRSegmentId(segment.seg_index)); - if (track_list.size() == 0) continue; + if (track_list.size() == 0) + continue; else { //enum e_track_status track_status = determine_track_status_of_gsb VTR_ASSERT((int)track_list.size() >= (to.seg_index + 1) * 2); size_t seg_id; - if (side == LEFT || side == BOTTOM) { //DEC + if (side == LEFT || side == BOTTOM) { //DEC seg_id = to.seg_index * 2 + 1; - } - else { //INC + } else { //INC VTR_ASSERT(side == RIGHT || side == TOP); seg_id = to.seg_index * 2; } @@ -1998,39 +1989,35 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, VTR_ASSERT(OUT_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); if (!rr_gsb.is_chan_node(to_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, - "Medium node %d is not in the GSB (%d, %d)\n", to_node, rr_gsb.get_x(), rr_gsb.get_y()); + "Medium node %d is not in the GSB (%d, %d)\n", to_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } } - - } - else { + } else { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong from type!\n"); exit(1); } VTR_ASSERT(to_node.is_valid()); - to_nodes.push_back(to_node); + to_nodes.push_back(to_node); } - - std::vector from_nodes; for (auto from : froms) { RRNodeId from_node; if (from.from_type == PB) { - + if (from.type_name != vib->get_pbtype_name()) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong from type name!\n"); exit(1); } - + for (e_side side : TOTAL_2D_SIDES) { from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); if (from_node.is_valid()) - break; + break; } if (!from_node.is_valid()) { VTR_LOGF_WARN(__FILE__, __LINE__, @@ -2039,11 +2026,10 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } if (!rr_gsb.is_opin_node(from_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, - "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } - } - else if (from.from_type == SEGMENT) { + } else if (from.from_type == SEGMENT) { char from_dir = from.seg_dir; //int from_index = from.seg_index; t_segment_inf segment = segment_inf[from.type_index]; @@ -2057,10 +2043,14 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } VTR_ASSERT(from.seg_index < seg_group.track_num * segment.length); e_side side; - if (from_dir == 'W') side = RIGHT; - else if (from_dir == 'E') side = LEFT; - else if (from_dir == 'N') side = BOTTOM; - else if (from_dir == 'S') side = TOP; + if (from_dir == 'W') + side = RIGHT; + else if (from_dir == 'E') + side = LEFT; + else if (from_dir == 'N') + side = BOTTOM; + else if (from_dir == 'S') + side = TOP; else { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong segment from direction!\n"); @@ -2068,14 +2058,14 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(side, RRSegmentId(segment.seg_index)); - if (track_list.size() == 0) continue; + if (track_list.size() == 0) + continue; else { VTR_ASSERT((int)track_list.size() >= (from.seg_index + 1) * 2); size_t seg_id; - if (side == LEFT || side == BOTTOM) { //INC + if (side == LEFT || side == BOTTOM) { //INC seg_id = from.seg_index * 2; - } - else { //DEC + } else { //DEC VTR_ASSERT(side == RIGHT || side == TOP); seg_id = from.seg_index * 2 + 1; } @@ -2087,27 +2077,24 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, exit(1); } } - - } - else if (from.from_type == MUX) { + } else if (from.from_type == MUX) { size_t from_mux_index = vib->medium_mux_index_by_name(from.type_name); from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); if (!rr_gsb.is_medium_node(from_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, - "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } - } - else { + } else { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong from type!\n"); exit(1); } VTR_ASSERT(from_node.is_valid()); - from_nodes.push_back(from_node); + from_nodes.push_back(from_node); } - + if (to_nodes.size() > 0 && from_nodes.size() > 0) { for (auto from_node : from_nodes) { auto iter = vib_map.begin(); @@ -2116,7 +2103,6 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, for (auto to_node : to_nodes) { vib_map[from_node].push_back(to_node); } - } } if (iter == vib_map.end()) { diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 5e7ca853700..672af21bc0a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -42,9 +42,9 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, const bool& concat_wire, const bool& wire_opposite_side, const std::vector& segment_inf); - + t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, - RRGraphBuilder& rr_graph_builder, + RRGraphBuilder& rr_graph_builder, const RRGraphView& rr_graph, const std::vector& segment_inf, const size_t& layer, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 08d80b5936d..5b48ec0f2e6 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -20,6 +20,7 @@ #include "tileable_chan_details_builder.h" #include "tileable_rr_graph_node_builder.h" #include "rr_rc_data.h" +#include "physical_types_util.h" /************************************************************************ * Find the number output pins by considering all the grid @@ -89,7 +90,7 @@ static size_t estimate_num_medium_rr_nodes(const DeviceGrid& grids, VTR_ASSERT(grids.width() == vib_grid.width() && grids.height() == vib_grid.height()); for (size_t ix = 0; ix < grids.width(); ++ix) { for (size_t iy = 0; iy < grids.height(); ++iy) { - + const VibInf* vib = vib_grid.get_vib(layer, ix, iy); if (!vib) { VTR_LOGF_ERROR(__FILE__, __LINE__, @@ -223,12 +224,12 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, size_t start_x = 1; size_t end_x = grids.width() - 1; if (perimeter_cb) { - start_x = 0; - end_x = grids.width(); + start_x = 0; + end_x = grids.width(); } size_t max_seg_length = grids.width() - 2; if (perimeter_cb) { - max_seg_length = grids.width(); + max_seg_length = grids.width(); } for (size_t iy = 0; iy < grids.height() - 1; ++iy) { @@ -300,12 +301,12 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, size_t start_y = 1; size_t end_y = grids.height() - 1; if (perimeter_cb) { - start_y = 0; - end_y = grids.height(); + start_y = 0; + end_y = grids.height(); } size_t max_seg_length = grids.height() - 2; if (perimeter_cb) { - max_seg_length = grids.height(); + max_seg_length = grids.height(); } for (size_t ix = 0; ix < grids.width() - 1; ++ix) { @@ -389,7 +390,6 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, layer, SOURCE, perimeter_cb); num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, layer, SINK, perimeter_cb); - /** * 2. Assign the segments for each routing channel, * To be specific, for each routing track, we assign a routing segment. @@ -519,9 +519,9 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); } /* End of loading OPIN rr_nodes */ - } /* End of side enumeration */ - } /* End of height enumeration */ - } /* End of width enumeration */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ } /************************************************************************ @@ -576,9 +576,9 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); } /* End of loading IPIN rr_nodes */ - } /* End of side enumeration */ - } /* End of height enumeration */ - } /* End of width enumeration */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ } /************************************************************************ @@ -713,7 +713,6 @@ static void load_one_grid_medium_nodes_basic_info(RRGraphBuilder& rr_graph_build /* RC data */ rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); } - } /************************************************************************ @@ -803,7 +802,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, VTR_ASSERT(grids.width() == vib_grid.width() && grids.height() == vib_grid.height()); for (size_t iy = 0; iy < grids.height(); ++iy) { for (size_t ix = 0; ix < grids.width(); ++ix) { - + t_physical_tile_loc tile_loc(ix, iy, layer); VTR_ASSERT(vib_grid.vib_pbtype_name(layer, ix, iy) == grids.get_physical_type(tile_loc)->name); vtr::Point grid_coordinate(ix, iy); @@ -815,11 +814,9 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, rr_rc_data, layer, grid_coordinate, vib_grid); - + } } } - } - //Copy the SOURCE/SINK nodes to all offset positions for blocks with width > 1 and/or height > 1 // This ensures that look-ups on non-root locations will still find the correct SOURCE/SINK @@ -1007,12 +1004,12 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, size_t start_x = 1; size_t end_x = grids.width() - 1; if (perimeter_cb) { - start_x = 0; - end_x = grids.width(); + start_x = 0; + end_x = grids.width(); } size_t max_seg_length = grids.width() - 2; if (perimeter_cb) { - max_seg_length = grids.width(); + max_seg_length = grids.width(); } /* For X-direction Channel: CHANX */ @@ -1145,12 +1142,12 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, size_t start_y = 1; size_t end_y = grids.height() - 1; if (perimeter_cb) { - start_y = 0; - end_y = grids.height(); + start_y = 0; + end_y = grids.height(); } size_t max_seg_length = grids.height() - 2; if (perimeter_cb) { - max_seg_length = grids.height(); + max_seg_length = grids.height(); } /* For Y-direction Channel: CHANY */ diff --git a/vpr/src/timing/NetPinTimingInvalidator.h b/vpr/src/timing/NetPinTimingInvalidator.h index c76a075cb74..09badeecc53 100644 --- a/vpr/src/timing/NetPinTimingInvalidator.h +++ b/vpr/src/timing/NetPinTimingInvalidator.h @@ -9,7 +9,7 @@ #include "vtr_vec_id_set.h" #ifdef VPR_USE_TBB -# include +#include #endif /** Make NetPinTimingInvalidator a virtual class since it does nothing for the general case of non-incremental @@ -191,4 +191,4 @@ inline std::unique_ptr make_net_pin_timing_invalidator( return std::make_unique(net_list, clb_atom_pin_lookup, atom_nlist, atom_lookup, timing_info, is_flat); } -} \ No newline at end of file +} diff --git a/vpr/src/timing/PostClusterDelayCalculator.tpp b/vpr/src/timing/PostClusterDelayCalculator.tpp index 9c989cec03f..e112aae06e5 100644 --- a/vpr/src/timing/PostClusterDelayCalculator.tpp +++ b/vpr/src/timing/PostClusterDelayCalculator.tpp @@ -336,9 +336,9 @@ inline tatum::Time PostClusterDelayCalculator::atom_net_delay(const tatum::Timin VTR_ASSERT(src_pin != ParentPinId::INVALID()); VTR_ASSERT(sink_pin != ParentPinId::INVALID()); if (is_flat_) { - AtomNetId atom_src_net = g_vpr_ctx.atom().nlist.pin_net((AtomPinId&)src_pin); - VTR_ASSERT(atom_src_net == g_vpr_ctx.atom().nlist.pin_net((AtomPinId&)sink_pin)); - sink_net_pin_index = g_vpr_ctx.atom().nlist.pin_net_index((AtomPinId&)sink_pin); + AtomNetId atom_src_net = g_vpr_ctx.atom().netlist().pin_net((AtomPinId&)src_pin); + VTR_ASSERT(atom_src_net == g_vpr_ctx.atom().netlist().pin_net((AtomPinId&)sink_pin)); + sink_net_pin_index = g_vpr_ctx.atom().netlist().pin_net_index((AtomPinId&)sink_pin); tatum::Time net_delay = tatum::Time(inter_cluster_delay((ParentNetId&)atom_src_net, 0, sink_net_pin_index)); diff --git a/vpr/src/timing/PreClusterDelayCalculator.h b/vpr/src/timing/PreClusterDelayCalculator.h index a4177fd6126..069aaa13530 100644 --- a/vpr/src/timing/PreClusterDelayCalculator.h +++ b/vpr/src/timing/PreClusterDelayCalculator.h @@ -19,7 +19,7 @@ class PreClusterDelayCalculator : public tatum::DelayCalculator { PreClusterDelayCalculator(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, float intercluster_net_delay, - const Prepacker& prepacker) + const Prepacker& prepacker) noexcept : netlist_(netlist) , netlist_lookup_(netlist_lookup) , inter_cluster_net_delay_(intercluster_net_delay) diff --git a/vpr/src/timing/PreClusterTimingGraphResolver.cpp b/vpr/src/timing/PreClusterTimingGraphResolver.cpp index c94d961c84f..d1d8c2d8754 100644 --- a/vpr/src/timing/PreClusterTimingGraphResolver.cpp +++ b/vpr/src/timing/PreClusterTimingGraphResolver.cpp @@ -28,7 +28,7 @@ std::string PreClusterTimingGraphResolver::node_type_name(tatum::NodeId node) co //Annotate primitive grid location, if known auto& atom_ctx = g_vpr_ctx.atom(); auto& block_locs = g_vpr_ctx.placement().block_locs(); - ClusterBlockId cb = atom_ctx.lookup.atom_clb(blk); + ClusterBlockId cb = atom_ctx.lookup().atom_clb(blk); if (cb && block_locs.count(cb)) { int x = block_locs[cb].loc.x; int y = block_locs[cb].loc.y; diff --git a/vpr/src/timing/PreClusterTimingManager.cpp b/vpr/src/timing/PreClusterTimingManager.cpp new file mode 100644 index 00000000000..44407d61522 --- /dev/null +++ b/vpr/src/timing/PreClusterTimingManager.cpp @@ -0,0 +1,296 @@ +/** + * @file + * @author Alex Singer + * @date April 2025 + * @brief Implementation of the pre-cluster timing manager class. + */ + +#include "PreClusterTimingManager.h" +#include +#include +#include "PreClusterDelayCalculator.h" +#include "PreClusterTimingGraphResolver.h" +#include "SetupGrid.h" +#include "atom_lookup.h" +#include "atom_netlist.h" +#include "atom_netlist_fwd.h" +#include "concrete_timing_info.h" +#include "physical_types_util.h" +#include "prepack.h" +#include "tatum/TimingReporter.hpp" +#include "tatum/echo_writer.hpp" +#include "vpr_types.h" +#include "vtr_assert.h" +#include "vtr_time.h" + +/** + * Since the parameters of a switch may change as a function of its fanin, + * to get an estimation of inter-cluster delays we need a reasonable estimation + * of the fan-ins of switches that connect clusters together. These switches are + * 1) opin to wire switch + * 2) wire to wire switch + * 3) wire to ipin switch + * We can estimate the fan-in of these switches based on the Fc_in/Fc_out of + * a logic block, and the switch block Fs value + */ +static void get_intercluster_switch_fanin_estimates(const t_arch& arch, + const t_det_routing_arch& routing_arch, + const std::string& device_layout, + const int wire_segment_length, + int* opin_switch_fanin, + int* wire_switch_fanin, + int* ipin_switch_fanin); + +static float get_arch_switch_info(short switch_index, int switch_fanin, float& Tdel_switch, float& R_switch, float& Cout_switch); + +static float approximate_inter_cluster_delay(const t_arch& arch, + const t_det_routing_arch& routing_arch, + const std::string& device_layout); + +PreClusterTimingManager::PreClusterTimingManager(bool timing_driven, + const AtomNetlist& atom_netlist, + const AtomLookup& atom_lookup, + const Prepacker& prepacker, + e_timing_update_type timing_update_type, + const t_arch& arch, + const t_det_routing_arch& routing_arch, + const std::string& device_layout, + const t_analysis_opts& analysis_opts) { + + // If the flow is not timing driven, do not initialize any of the timing + // objects and set the valid flag to false. This allows this object to be + // passed through the VPR flow when timing is turned off. + if (!timing_driven) { + is_valid_ = false; + return; + } + is_valid_ = true; + + // Start an overall timer for building the pre-cluster timing info. + vtr::ScopedStartFinishTimer timer("Initializing Pre-Cluster Timing"); + + // Approximate the inter-cluster delay + // FIXME: This can probably be simplified. It can also be improved using + // AP information. + float inter_cluster_net_delay = approximate_inter_cluster_delay(arch, routing_arch, device_layout); + VTR_LOG("Using inter-cluster delay: %g\n", inter_cluster_net_delay); + + // Initialize the timing analyzer + clustering_delay_calc_ = std::make_shared(atom_netlist, + atom_lookup, + inter_cluster_net_delay, + prepacker); + timing_info_ = make_setup_timing_info(clustering_delay_calc_, timing_update_type); + + // Calculate the initial timing + timing_info_->update(); + + // Create the echo file if requested. + if (isEchoFileEnabled(E_ECHO_PRE_PACKING_TIMING_GRAPH)) { + auto& timing_ctx = g_vpr_ctx.timing(); + tatum::write_echo(getEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH), + *timing_ctx.graph, *timing_ctx.constraints, *clustering_delay_calc_, timing_info_->analyzer()); + + tatum::NodeId debug_tnode = id_or_pin_name_to_tnode(analysis_opts.echo_dot_timing_graph_node); + write_setup_timing_graph_dot(getEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH) + std::string(".dot"), + *timing_info_, debug_tnode); + } + + // Write a timing report. + { + auto& timing_ctx = g_vpr_ctx.timing(); + PreClusterTimingGraphResolver resolver(atom_netlist, + atom_lookup, + *timing_ctx.graph, + *clustering_delay_calc_); + resolver.set_detail_level(analysis_opts.timing_report_detail); + + tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, + *timing_ctx.constraints); + + timing_reporter.report_timing_setup( + "pre_pack.report_timing.setup.rpt", + *timing_info_->setup_analyzer(), + analysis_opts.timing_report_npaths); + } +} + +static float approximate_inter_cluster_delay(const t_arch& arch, + const t_det_routing_arch& routing_arch, + const std::string& device_layout) { + + /* If needed, estimate inter-cluster delay. Assume the average routing hop goes out of + * a block through an opin switch to a length-4 wire, then through a wire switch to another + * length-4 wire, then through a wire-to-ipin-switch into another block. */ + constexpr int wire_segment_length = 4; + + /* We want to determine a reasonable fan-in to the opin, wire, and ipin switches, based + * on which the intercluster delays can be estimated. The fan-in of a switch influences its + * delay. + * + * The fan-in of the switch depends on the architecture (unidirectional/bidirectional), as + * well as Fc_in/out and Fs */ + int opin_switch_fanin, wire_switch_fanin, ipin_switch_fanin; + get_intercluster_switch_fanin_estimates(arch, routing_arch, device_layout, wire_segment_length, &opin_switch_fanin, + &wire_switch_fanin, &ipin_switch_fanin); + + float Tdel_opin_switch, R_opin_switch, Cout_opin_switch; + float opin_switch_del = get_arch_switch_info(arch.Segments[0].arch_opin_switch, opin_switch_fanin, + Tdel_opin_switch, R_opin_switch, Cout_opin_switch); + + float Tdel_wire_switch, R_wire_switch, Cout_wire_switch; + float wire_switch_del = get_arch_switch_info(arch.Segments[0].arch_wire_switch, wire_switch_fanin, + Tdel_wire_switch, R_wire_switch, Cout_wire_switch); + + float Tdel_wtoi_switch, R_wtoi_switch, Cout_wtoi_switch; + float wtoi_switch_del = get_arch_switch_info(routing_arch.wire_to_arch_ipin_switch, ipin_switch_fanin, + Tdel_wtoi_switch, R_wtoi_switch, Cout_wtoi_switch); + + float Rmetal = arch.Segments[0].Rmetal; + float Cmetal = arch.Segments[0].Cmetal; + + /* The delay of a wire with its driving switch is the switch delay plus the + * product of the equivalent resistance and capacitance experienced by the wire. */ + + float first_wire_seg_delay = opin_switch_del + + (R_opin_switch + Rmetal * (float)wire_segment_length / 2) + * (Cout_opin_switch + Cmetal * (float)wire_segment_length); + float second_wire_seg_delay = wire_switch_del + + (R_wire_switch + Rmetal * (float)wire_segment_length / 2) + * (Cout_wire_switch + Cmetal * (float)wire_segment_length); + + /* multiply by 4 to get a more conservative estimate */ + return 4 * (first_wire_seg_delay + second_wire_seg_delay + wtoi_switch_del); +} + +static float get_arch_switch_info(short switch_index, int switch_fanin, float& Tdel_switch, float& R_switch, float& Cout_switch) { + /* Fetches delay, resistance and output capacitance of the architecture switch at switch_index. + * Returns the total delay through the switch. Used to calculate inter-cluster net delay. */ + + /* The intrinsic delay may depend on fanin to the switch. If the delay map of a + * switch from the architecture file has multiple (#inputs, delay) entries, we + * interpolate/extrapolate to get the delay at 'switch_fanin'. */ + auto& device_ctx = g_vpr_ctx.device(); + + Tdel_switch = device_ctx.arch_switch_inf[switch_index].Tdel(switch_fanin); + R_switch = device_ctx.arch_switch_inf[switch_index].R; + Cout_switch = device_ctx.arch_switch_inf[switch_index].Cout; + + /* The delay through a loaded switch is its intrinsic (unloaded) + * delay plus the product of its resistance and output capacitance. */ + return Tdel_switch + R_switch * Cout_switch; +} + +static void get_intercluster_switch_fanin_estimates(const t_arch& arch, + const t_det_routing_arch& routing_arch, + const std::string& device_layout, + const int wire_segment_length, + int* opin_switch_fanin, + int* wire_switch_fanin, + int* ipin_switch_fanin) { + // W is unknown pre-packing, so *if* we need W here, we will assume a value of 100 + constexpr int W = 100; + + //Build a dummy 10x10 device to determine the 'best' block type to use + auto grid = create_device_grid(device_layout, arch.grid_layouts, 10, 10); + + auto type = find_most_common_tile_type(grid); + /* get Fc_in/out for most common block (e.g. logic blocks) */ + VTR_ASSERT(!type->fc_specs.empty()); + + //Estimate the maximum Fc_in/Fc_out + float Fc_in = 0.f; + float Fc_out = 0.f; + for (const t_fc_specification& fc_spec : type->fc_specs) { + float Fc = fc_spec.fc_value; + + if (fc_spec.fc_value_type == e_fc_value_type::ABSOLUTE) { + //Convert to estimated fractional + Fc /= W; + } + VTR_ASSERT_MSG(Fc >= 0 && Fc <= 1., "Fc should be fractional"); + + for (int ipin : fc_spec.pins) { + e_pin_type pin_type = get_pin_type_from_pin_physical_num(type, ipin); + + if (pin_type == DRIVER) { + Fc_out = std::max(Fc, Fc_out); + } else { + VTR_ASSERT(pin_type == RECEIVER); + Fc_in = std::max(Fc, Fc_in); + } + } + } + + /* Estimates of switch fan-in are done as follows: + * 1) opin to wire switch: + * 2 CLBs connect to a channel, each with #opins/4 pins. Each pin has Fc_out*W + * switches, and then we assume the switches are distributed evenly over the W wires. + * In the unidirectional case, all these switches are then crammed down to W/wire_segment_length wires. + * + * Unidirectional: 2 * #opins_per_side * Fc_out * wire_segment_length + * Bidirectional: 2 * #opins_per_side * Fc_out + * + * 2) wire to wire switch + * A wire segment in a switchblock connects to Fs other wires. Assuming these connections are evenly + * distributed, each target wire receives Fs connections as well. In the unidirectional case, + * source wires can only connect to W/wire_segment_length wires. + * + * Unidirectional: Fs * wire_segment_length + * Bidirectional: Fs + * + * 3) wire to ipin switch + * An input pin of a CLB simply receives Fc_in connections. + * + * Unidirectional: Fc_in + * Bidirectional: Fc_in + */ + + /* Fan-in to opin/ipin/wire switches depends on whether the architecture is unidirectional/bidirectional */ + (*opin_switch_fanin) = 2.f * type->num_drivers / 4.f * Fc_out; + (*wire_switch_fanin) = routing_arch.Fs; + (*ipin_switch_fanin) = Fc_in; + if (routing_arch.directionality == UNI_DIRECTIONAL) { + /* adjustments to opin-to-wire and wire-to-wire switch fan-ins */ + (*opin_switch_fanin) *= wire_segment_length; + (*wire_switch_fanin) *= wire_segment_length; + } else if (routing_arch.directionality == BI_DIRECTIONAL) { + /* no adjustments need to be made here */ + } else { + VPR_FATAL_ERROR(VPR_ERROR_PACK, "Unrecognized directionality: %d\n", + (int)routing_arch.directionality); + } +} + +float PreClusterTimingManager::calc_atom_setup_criticality(AtomBlockId blk_id, + const AtomNetlist& atom_netlist) const { + VTR_ASSERT_SAFE_MSG(is_valid_, + "PreClusterTimingManager has not been initialized"); + VTR_ASSERT_SAFE_MSG(blk_id.is_valid(), + "Invalid block ID"); + + float crit = 0.0f; + for (AtomPinId in_pin : atom_netlist.block_input_pins(blk_id)) { + // Max criticality over incoming nets + float pin_crit = timing_info_->setup_pin_criticality(in_pin); + crit = std::max(crit, pin_crit); + } + + return crit; +} + +float PreClusterTimingManager::calc_net_setup_criticality(AtomNetId net_id, + const AtomNetlist& atom_netlist) const { + VTR_ASSERT_SAFE_MSG(is_valid_, + "PreClusterTimingManager has not been initialized"); + VTR_ASSERT_SAFE_MSG(net_id.is_valid(), + "Invalid net ID"); + + // We let the criticality of an entire net to be the max criticality of all + // timing edges within the net. Since all timing paths start at the driver, + // this is equivalent to the criticality of the driver pin. + AtomPinId net_driver_pin_id = atom_netlist.net_driver(net_id); + VTR_ASSERT_SAFE_MSG(net_driver_pin_id.is_valid(), + "Net has no driver"); + return timing_info_->setup_pin_criticality(net_driver_pin_id); +} diff --git a/vpr/src/timing/PreClusterTimingManager.h b/vpr/src/timing/PreClusterTimingManager.h new file mode 100644 index 00000000000..0aaed6edea1 --- /dev/null +++ b/vpr/src/timing/PreClusterTimingManager.h @@ -0,0 +1,119 @@ +/** + * @file + * @author Alex Singer + * @date April 2025 + * @brief Manager class for pre-cluster (primitive-level) timing analysis. + */ + +#pragma once + +#include +#include +#include "vpr_types.h" +#include "vtr_assert.h" + +// Forward declarations. +class AtomLookup; +class AtomNetlist; +class PreClusterDelayCalculator; +class Prepacker; +class SetupTimingInfo; + +/** + * @brief Pre-cluster timing manager class. + * + * This class encapsulates the timing computations used prior to clustering. + * This maintains all of the state necessary to perform these timing computations. + */ +class PreClusterTimingManager { + public: + /** + * @brief Constructor for the manager class. + * + * If timing_driven is set to true, this constructor will perform a setup + * timing analysis with a pre-clustered delay model. The delay model uses + * the primitive delays specified in the architecture file and a simple + * estimate of routing (a typical routing delay based on the wire delays + * found in the architecture, and more specific delays for direct connections + * like carry chains whose use we already know from the pre-packing). + * + * @param timing_driven + * Whether this class should compute timing information or not. This + * may seem counter-intuitive, but this class still needs to exist + * even if timing is turned off. This will not initialize anything + * and set the valid flag to false if we are not timing driven. + * @param atom_netlist + * The primitive netlist to perform timing analysis over. + * @param atom_lookup + * A lookup between the primitives and their timing nodes. + * @param prepacker + * The prepacker object used to prepack primitives into molecules. + * @param timing_update_type + * The type of timing update this class should perform. + * @param arch + * The architecture. + * @param routing_arch + * The routing architecture. + * @param analysis opts + * Options for the timing analysis in VPR. + */ + PreClusterTimingManager(bool timing_driven, + const AtomNetlist& atom_netlist, + const AtomLookup& atom_lookup, + const Prepacker& prepacker, + e_timing_update_type timing_update_type, + const t_arch& arch, + const t_det_routing_arch& routing_arch, + const std::string& device_layout, + const t_analysis_opts& analysis_opts); + + /** + * @brief Calculates the setup criticality of the given primitive block. + * + * Currently defined as the maximum criticality over the block inputs. + */ + float calc_atom_setup_criticality(AtomBlockId blk_id, + const AtomNetlist& atom_netlist) const; + + /** + * @brief Calculates the setup criticality of the given net in the primitive + * netlist. + * + * Currently defined as the maximum criticality over all edges in the net + * from the driver pin to the sink pins. This is equivalent to the criticality + * of the driver pin. + */ + float calc_net_setup_criticality(AtomNetId net_id, + const AtomNetlist& atom_netlist) const; + + /** + * @brief Returns whether or not the pre-cluster timing manager was + * initialized (i.e. timing information can be computed). + */ + bool is_valid() const { + return is_valid_; + } + + /** + * @brief Get a reference to the setup timing info. + */ + const SetupTimingInfo& get_timing_info() const { + VTR_ASSERT_SAFE_MSG(is_valid_, + "Timing manager has not been initialized"); + return *timing_info_; + } + + private: + /// @brief A valid flag used to signify if the pre-cluster timing manager + /// class has been initialized or not. For example, if the flow is + /// not timing-driven, then this class will just be a shell which + /// should not have any timing information (but the object exists). + bool is_valid_; + + /// @brief The delay calculator used for computing timing. + std::shared_ptr clustering_delay_calc_; + + /// @brief The setup timing info used for getting the timing of edges + /// in the timing graph. + std::shared_ptr timing_info_; +}; diff --git a/vpr/src/timing/VprTimingGraphResolver.cpp b/vpr/src/timing/VprTimingGraphResolver.cpp index fa5dc1ae960..791615e5585 100644 --- a/vpr/src/timing/VprTimingGraphResolver.cpp +++ b/vpr/src/timing/VprTimingGraphResolver.cpp @@ -34,7 +34,7 @@ std::string VprTimingGraphResolver::node_type_name(tatum::NodeId node) const { //Annotate primitive grid location, if known auto& atom_ctx = g_vpr_ctx.atom(); auto& block_locs = blk_loc_registry_.block_locs(); - ClusterBlockId cb = atom_ctx.lookup.atom_clb(blk); + ClusterBlockId cb = atom_ctx.lookup().atom_clb(blk); if (cb && block_locs.count(cb)) { int x = block_locs[cb].loc.x; int y = block_locs[cb].loc.y; @@ -174,11 +174,11 @@ std::vector VprTimingGraphResolver::interconnect_delay_br tatum::Time sink_clb_delay; if (is_flat_) { - AtomNetId tmp_atom_net = atom_ctx.nlist.pin_net((AtomPinId&)src_pin); - VTR_ASSERT(tmp_atom_net == atom_ctx.nlist.pin_net((AtomPinId&)sink_pin)); + AtomNetId tmp_atom_net = atom_ctx.netlist().pin_net((AtomPinId&)src_pin); + VTR_ASSERT(tmp_atom_net == atom_ctx.netlist().pin_net((AtomPinId&)sink_pin)); - AtomBlockId tmp_atom_src_block = atom_ctx.nlist.pin_block((AtomPinId&)src_pin); - AtomBlockId tmp_atom_sink_block = atom_ctx.nlist.pin_block((AtomPinId&)sink_pin); + AtomBlockId tmp_atom_src_block = atom_ctx.netlist().pin_block((AtomPinId&)src_pin); + AtomBlockId tmp_atom_sink_block = atom_ctx.netlist().pin_block((AtomPinId&)sink_pin); src_blk = (ParentBlockId&)tmp_atom_src_block; sink_blk = (ParentBlockId&)tmp_atom_sink_block; @@ -188,7 +188,7 @@ std::vector VprTimingGraphResolver::interconnect_delay_br driver_clb_delay = tatum::Time(0); sink_clb_delay = tatum::Time(0); - sink_net_pin_index = g_vpr_ctx.atom().nlist.pin_net_index((AtomPinId&)sink_pin); + sink_net_pin_index = g_vpr_ctx.atom().netlist().pin_net_index((AtomPinId&)sink_pin); } else { ClusterNetId tmp_cluster_net = cluster_ctx.clb_nlist.pin_net((ClusterPinId&)src_pin); @@ -218,7 +218,7 @@ std::vector VprTimingGraphResolver::interconnect_delay_br //driver_component.inst_name = cluster_ctx.clb_nlist.block_name(src_blk); driver_component.type_name = "intra '"; if (is_flat_) { - const t_pb* atom_pb = atom_ctx.lookup.atom_pb((AtomBlockId&)src_blk); + const t_pb* atom_pb = atom_ctx.lookup().atom_pb_bimap().atom_pb((AtomBlockId&)src_blk); driver_component.type_name += (std::string(atom_pb->name) + "(" + atom_pb->hierarchical_type_name() + ")"); } else { driver_component.type_name += cluster_ctx.clb_nlist.block_type((ClusterBlockId&)src_blk)->name; @@ -263,7 +263,7 @@ std::vector VprTimingGraphResolver::interconnect_delay_br //sink_component.inst_name = cluster_ctx.clb_nlist.block_name(sink_blk); sink_component.type_name = "intra '"; if (is_flat_) { - sink_component.type_name += atom_ctx.lookup.atom_pb((AtomBlockId&)sink_blk)->name; + sink_component.type_name += atom_ctx.lookup().atom_pb_bimap().atom_pb((AtomBlockId&)sink_blk)->name; } else { sink_component.type_name += cluster_ctx.clb_nlist.block_type((ClusterBlockId&)sink_blk)->name; } @@ -283,8 +283,8 @@ void VprTimingGraphResolver::set_detail_level(e_timing_report_detail report_deta } void VprTimingGraphResolver::get_detailed_interconnect_components(std::vector& components, ParentNetId net_id, ParentPinId sink_pin) const { - /* This routine obtains the interconnect components such as: OPIN, CHANX, CHANY, IPIN which join - * two intra-block clusters in two parts. In part one, we construct the route tree + /* This routine obtains the interconnect components such as: OPIN, CHANX, CHANY, IPIN which join + * two intra-block clusters in two parts. In part one, we construct the route tree * from the traceback and computes its value for R, C, and Tdel. Next, we find the pointer to * the route tree sink which corresponds to the sink_pin. In part two, we call the helper function, * which walks the route tree from the sink to the source. Along the way, we process each node @@ -295,7 +295,7 @@ void VprTimingGraphResolver::get_detailed_interconnect_components(std::vector&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + auto& netlist = is_flat_ ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; int ipin = netlist.pin_net_index(sink_pin); RRNodeId sink_rr_inode = RRNodeId(route_ctx.net_rr_terminals[net_id][ipin]); //obtain the value of the routing resource sink diff --git a/vpr/src/timing/concrete_timing_info.h b/vpr/src/timing/concrete_timing_info.h index ce02e2abe90..d534e597c70 100644 --- a/vpr/src/timing/concrete_timing_info.h +++ b/vpr/src/timing/concrete_timing_info.h @@ -28,7 +28,7 @@ class ConcreteSetupTimingInfo : public SetupTimingInfo { , timing_constraints_(timing_constraints_v) , delay_calc_(delay_calc) , setup_analyzer_(analyzer_v) - , slack_crit_(g_vpr_ctx.atom().nlist, g_vpr_ctx.atom().lookup) { + , slack_crit_(g_vpr_ctx.atom().netlist(), g_vpr_ctx.atom().lookup()) { //pass } @@ -184,7 +184,7 @@ class ConcreteHoldTimingInfo : public HoldTimingInfo { , timing_constraints_(timing_constraints_v) , delay_calc_(delay_calc) , hold_analyzer_(analyzer_v) - , slack_crit_(g_vpr_ctx.atom().nlist, g_vpr_ctx.atom().lookup) { + , slack_crit_(g_vpr_ctx.atom().netlist(), g_vpr_ctx.atom().lookup()) { //pass } diff --git a/vpr/src/timing/read_sdc.cpp b/vpr/src/timing/read_sdc.cpp index 202a3cfe6e0..e8db27b9a28 100644 --- a/vpr/src/timing/read_sdc.cpp +++ b/vpr/src/timing/read_sdc.cpp @@ -1,5 +1,6 @@ #include "read_sdc.h" +#include #include #include "vtr_log.h" @@ -741,13 +742,14 @@ class SdcParseCallback : public sdcparse::Callback { VTR_ASSERT_MSG(capture_clock.period >= 0., "Clock period must be positive"); float constraint = std::numeric_limits::quiet_NaN(); - - if (std::fabs(launch_clock.period - capture_clock.period) < EPSILON && std::fabs(launch_clock.rise_edge - capture_clock.rise_edge) < EPSILON && std::fabs(launch_clock.fall_edge - capture_clock.fall_edge) < EPSILON) { + if (vtr::isclose(launch_clock.period, capture_clock.period) + && vtr::isclose(launch_clock.rise_edge, capture_clock.rise_edge) + && vtr::isclose(launch_clock.fall_edge, capture_clock.fall_edge)) { //The source and sink domains have the same period and edges, the constraint is the common clock period. constraint = launch_clock.period; - } else if (launch_clock.period < EPSILON || capture_clock.period < EPSILON) { + } else if (vtr::isclose(launch_clock.period, 0.0) || vtr::isclose(capture_clock.period, 0.0)) { //If either period is 0, the constraint is 0 constraint = 0.; diff --git a/vpr/src/timing/slack_evaluation.cpp b/vpr/src/timing/slack_evaluation.cpp index 464bc4bc031..7d14d50c201 100644 --- a/vpr/src/timing/slack_evaluation.cpp +++ b/vpr/src/timing/slack_evaluation.cpp @@ -8,9 +8,9 @@ #include "vtr_time.h" #if defined(VPR_USE_TBB) -# include -# include -# include +#include +#include +#include #endif template diff --git a/vpr/src/timing/timing_graph_builder.cpp b/vpr/src/timing/timing_graph_builder.cpp index 49534b9d380..78bbbe63ba2 100644 --- a/vpr/src/timing/timing_graph_builder.cpp +++ b/vpr/src/timing/timing_graph_builder.cpp @@ -7,23 +7,23 @@ * The Timing Graph is a directed acyclic graph (DAG) consisting of nodes and edges: * - Nodes: represent netlist pins (tatum::IPIN, tatum::OPIN) and logical sources/ * sinks like primary inputs/outpus, flip-flops and clock generators (tatum::SOURCE, - * tatum::SINK). + * tatum::SINK). * * Note that tatum::SOURCE/tatum::SINK represent the start/end of * a timing path. As a result tatum::SOURCE's hould never have input edges (except - * perhaps from a tatum::CPIN if it is a sequential source), and tatum::SINKS's + * perhaps from a tatum::CPIN if it is a sequential source), and tatum::SINKS's * should never have output edges. * - * - Edges: represent the timing dependences between nodes in the timing graph. - * These correspond to net connections, combinational paths inside primitives, + * - Edges: represent the timing dependences between nodes in the timing graph. + * These correspond to net connections, combinational paths inside primitives, * clock-to-q, and setup/hold constraints for sequential elements. * - * The timing graph is constructed by first creating timing sub-graphs corresponding to - * each primitive block in the AtomNetlist. Each sub-graph contains the timing graph + * The timing graph is constructed by first creating timing sub-graphs corresponding to + * each primitive block in the AtomNetlist. Each sub-graph contains the timing graph * nodes required to represent the primitive, and all internal timing graph edges (i.e. * those completely contained within the primitive). * - * Next timing graph edges corresponding to nets in the netlist (i.e. connections between + * Next timing graph edges corresponding to nets in the netlist (i.e. connections between * netlist primitives) are created to "stitch" the sub-graph together. This results in a * timing graph corresponding to the netlist. * @@ -31,18 +31,18 @@ * Modelling Primitive Combinational and Sequential Logic as a Timing Graph * ----------------------------------------------------------------------- * - * Consider the architectural primitive block below, which contains two - * sequential elements 'A' and 'B' (controlled by the primitive input + * Consider the architectural primitive block below, which contains two + * sequential elements 'A' and 'B' (controlled by the primitive input * pin 'clk'), and two clouds of combinational logic 'C' and 'D'. * - * The combinational logic 'D' is driven by primtive input 'e' and + * The combinational logic 'D' is driven by primtive input 'e' and * drives primitive output pin 'g'. * * The combinational logic 'C' is driven by the sequential element 'A' and - * primitive input pin 'e'; it then drives the input of the sequential + * primitive input pin 'e'; it then drives the input of the sequential * element 'B'. * - * Sequential element 'A' is driven by primitive input 'f', and sequential + * Sequential element 'A' is driven by primitive input 'f', and sequential * element 'B' drives primitive output pin 'h'. * * +---------------------------------------+ @@ -50,7 +50,7 @@ * | --- | * | / \ | * e --->-----------------+----->| D |-------->|--> g - * | | \ / | + * | | \ / | * | | --- | * | v ^ | * | --- | | @@ -82,9 +82,9 @@ * * which all must be modelled by the timing graph: * - * Modelling combinational logic is simple, and only requires that there is - * a timing graph edge (tedge) between the corresponding timing graph nodes - * (STA only considers the topological structure of the netlist, not it's + * Modelling combinational logic is simple, and only requires that there is + * a timing graph edge (tedge) between the corresponding timing graph nodes + * (STA only considers the topological structure of the netlist, not it's * logic functionality). * * For instance, to model the combinational logic 'D', we use two tnodes as @@ -94,12 +94,12 @@ * --->| IPIN e |------->| OPIN g |---> * +--------+ +--------+ * - * where 'IPIN e' and 'OPIN g' respectively corresponds to the primitive + * where 'IPIN e' and 'OPIN g' respectively corresponds to the primitive * input 'e' and output 'g' and the edge between them the timing dependency * through the combinational logic 'D'. * * - * To model a sequential element like 'B', we use three timing graph + * To model a sequential element like 'B', we use three timing graph * nodes as follows: * * +--------+ +--------+ @@ -113,13 +113,13 @@ * --->| CPIN | * +--------+ * - * Where 'SINK B' represents the data input of sequential element 'B' (e.g. - * Flip-Flop D pin), 'SRC B' the data output (SOURCE) of sequential element - * 'B' (e.g. Flip-Flop Q pin), and 'CPIN' the clock input pin of sequential + * Where 'SINK B' represents the data input of sequential element 'B' (e.g. + * Flip-Flop D pin), 'SRC B' the data output (SOURCE) of sequential element + * 'B' (e.g. Flip-Flop Q pin), and 'CPIN' the clock input pin of sequential * element 'B'. * * - * Following the above transformations, we arrive at the following timing graph + * Following the above transformations, we arrive at the following timing graph * structure, which corresponds to the architectural primitive described above: * * +--------+ +--------+ @@ -145,9 +145,9 @@ * | |------------------------------+ | * --->| CPIN clk | | * | |-----------------------------------------------+ - * +----------+ + * +----------+ * - * Note that we have also used only a single CPIN for both 'A' and 'B' (since + * Note that we have also used only a single CPIN for both 'A' and 'B' (since * they are controlled by the same clock). * * @@ -156,29 +156,29 @@ * ---------------------------------------------------- * * VPR does not directly model the intenals of netlist primitives (e.g. internal - * sequential elements like 'A' or 'B' above). Instead, various attributes are + * sequential elements like 'A' or 'B' above). Instead, various attributes are * tagged on the pins of the primitive which indicate: * - whether a pin is sequential, combinational or a clock - * - whether the pin is combinationally connected to another pin + * - whether the pin is combinationally connected to another pin * within the primitive. - * + * * Mostly there is a one-to-one correspondance between netlist pins and tnodes, * the only exception is for sequential-sequential connections within a primtive * (e.g. the fully internal 'A' to 'B' timing path above). * * As a result we make a distinction between tnodes which are strictly "internal" * to a primitive, and those which are "external" (i.e. connect to tnodes outside - * the primitive). Note that this distinction is just a labelling which is only - * relevant to how VPR tracks the relation between tnodes and netlist pins. It - * has no effect on the timing analysis result (which only depends on the - * structure of the timing graph). Most of VPR doesn't care about the internal + * the primitive). Note that this distinction is just a labelling which is only + * relevant to how VPR tracks the relation between tnodes and netlist pins. It + * has no effect on the timing analysis result (which only depends on the + * structure of the timing graph). Most of VPR doesn't care about the internal * timing paths, as they are typically uneffected by any of VPR's optimization - * choices. Therefore most of VPR only considers "external" tnodes when mapping + * choices. Therefore most of VPR only considers "external" tnodes when mapping * between netlist pins and tnodes. Of course we record both so the parts of VPR * which *do* care about them (e.g. the code here, and in the delay calculator) * can figure out the correct mapping. * - * As a result the timing graph we build (for the primitive example above) is + * As a result the timing graph we build (for the primitive example above) is * described within VPR as: * * +------------+ +------------+ @@ -207,12 +207,12 @@ * | CPIN clk |--------------------------------+ | * --->| | | * | (external) |--------------------------------------------------+ - * +------------+ + * +------------+ * - * Where each pin in the netlist corresponds to an "external" tnode, but the - * sequential netlist pins 'f' and 'h' have additional "internal" tnodes + * Where each pin in the netlist corresponds to an "external" tnode, but the + * sequential netlist pins 'f' and 'h' have additional "internal" tnodes * corresponding to their respective data outputs/inputs within the primitive. - * Also note that combinational pins are makred as both internal and external + * Also note that combinational pins are makred as both internal and external * for convenience (i.e. both map to the same tnode). * */ @@ -371,9 +371,9 @@ void TimingGraphBuilder::add_block_to_timing_graph(const AtomBlockId blk) { * Once all nodes have been created the edges are added between them according * to what was specified in the architecture file models. * - * Note that to minimize the size of the timing graph we only create tnodes and - * edges where they actually exist within the netlist. This means we do not create - * tnodes or tedges to/from pins which are disconnected in the netlist (even if + * Note that to minimize the size of the timing graph we only create tnodes and + * edges where they actually exist within the netlist. This means we do not create + * tnodes or tedges to/from pins which are disconnected in the netlist (even if * they exist in the architecture). * * diff --git a/vpr/src/timing/timing_graph_builder.h b/vpr/src/timing/timing_graph_builder.h index 92de6afdf3d..1f1624eed81 100644 --- a/vpr/src/timing/timing_graph_builder.h +++ b/vpr/src/timing/timing_graph_builder.h @@ -6,14 +6,14 @@ #include "atom_lookup.h" /* - * Class for constructing a Timing Graph (a tatum::TimingGraph, for use with the Tatum - * STA engine) from the provided AtomNetlist. It also updates the provided AtomLookup + * Class for constructing a Timing Graph (a tatum::TimingGraph, for use with the Tatum + * STA engine) from the provided AtomNetlist. It also updates the provided AtomLookup * with the mapping from netlist elements to timing graph nodes. * - * To construct a timing graph initialize this class with the netlist and lookup + * To construct a timing graph initialize this class with the netlist and lookup * (via constructor), and call the timing_graph() method. * - * For details on how the timing graph is constructed from the netlist, see the comments + * For details on how the timing graph is constructed from the netlist, see the comments * in the associated .cpp implementation file. */ class TimingGraphBuilder { diff --git a/vpr/src/timing/timing_util.cpp b/vpr/src/timing/timing_util.cpp index e51fadf5d42..94191667499 100644 --- a/vpr/src/timing/timing_util.cpp +++ b/vpr/src/timing/timing_util.cpp @@ -485,20 +485,20 @@ float find_total_negative_slack_within_clb_blocks(const tatum::HoldTimingAnalyze VTR_ASSERT(origin_node); /*Retrieve the source and sink clb blocks corresponding to these timing nodes*/ - AtomPinId origin_pin = atom_ctx.lookup.tnode_atom_pin(origin_node); - AtomPinId pin = atom_ctx.lookup.tnode_atom_pin(node); + AtomPinId origin_pin = atom_ctx.lookup().tnode_atom_pin(origin_node); + AtomPinId pin = atom_ctx.lookup().tnode_atom_pin(node); VTR_ASSERT(origin_pin); VTR_ASSERT(pin); - AtomBlockId atom_src_block = atom_ctx.nlist.pin_block(origin_pin); - AtomBlockId atom_sink_block = atom_ctx.nlist.pin_block(pin); + AtomBlockId atom_src_block = atom_ctx.netlist().pin_block(origin_pin); + AtomBlockId atom_sink_block = atom_ctx.netlist().pin_block(pin); - ClusterBlockId clb_src_block = atom_ctx.lookup.atom_clb(atom_src_block); + ClusterBlockId clb_src_block = atom_ctx.lookup().atom_clb(atom_src_block); VTR_ASSERT(clb_src_block); - ClusterBlockId clb_sink_block = atom_ctx.lookup.atom_clb(atom_sink_block); + ClusterBlockId clb_sink_block = atom_ctx.lookup().atom_clb(atom_sink_block); VTR_ASSERT(clb_sink_block); - const t_pb_graph_pin* sink_gpin = atom_ctx.lookup.atom_pin_pb_graph_pin(pin); + const t_pb_graph_pin* sink_gpin = atom_ctx.lookup().atom_pin_pb_graph_pin(pin); VTR_ASSERT(sink_gpin); int sink_pb_route_id = sink_gpin->pin_count_in_cluster; @@ -843,13 +843,13 @@ tatum::NodeId id_or_pin_name_to_tnode(const std::string& pin_name_or_tnode) { tatum::NodeId pin_name_to_tnode(const std::string& pin_name) { auto& atom_ctx = g_vpr_ctx.atom(); - AtomPinId pin = atom_ctx.nlist.find_pin(pin_name); + AtomPinId pin = atom_ctx.netlist().find_pin(pin_name); if (!pin) { VPR_THROW(VPR_ERROR_ATOM_NETLIST, "Failed to find pin named '%s'\n", pin_name.c_str()); } - tatum::NodeId tnode = atom_ctx.lookup.atom_pin_tnode(pin); + tatum::NodeId tnode = atom_ctx.lookup().atom_pin_tnode(pin); if (!tnode) { VPR_THROW(VPR_ERROR_TIMING, "Failed to find tnode for pin '%s' (pin: %zu)\n", pin_name.c_str(), size_t(pin)); diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 447404067b3..f960f5c8668 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -4,11 +4,10 @@ #include #include "pack_types.h" -#include "prepack.h" +#include "physical_types_util.h" #include "vpr_context.h" #include "vtr_assert.h" #include "vtr_log.h" -#include "vtr_memory.h" #include "vpr_types.h" #include "vpr_error.h" @@ -19,7 +18,6 @@ #include "cluster_placement.h" #include "device_grid.h" #include "user_route_constraints.h" -#include "placer_state.h" #include "grid_block.h" /* This module contains subroutines that are used in several unrelated parts * @@ -214,7 +212,7 @@ AtomPinId find_clb_pin_driver_atom_pin(ClusterBlockId clb, int logical_pin, cons AtomPinId atom_pin = find_atom_pin_for_pb_route_id(clb, pb_pin_id, pb_gpin_lookup); VTR_ASSERT(atom_pin); - VTR_ASSERT_MSG(atom_ctx.nlist.pin_net(atom_pin) == atom_net, "Driver atom pin should drive the same net"); + VTR_ASSERT_MSG(atom_ctx.netlist().pin_net(atom_pin) == atom_net, "Driver atom pin should drive the same net"); return atom_pin; } @@ -244,7 +242,7 @@ std::vector find_clb_pin_sink_atom_pins(ClusterBlockId clb, int logic AtomPinId atom_pin = find_atom_pin_for_pb_route_id(clb, sink_pb_pin, pb_gpin_lookup); VTR_ASSERT(atom_pin); - VTR_ASSERT_MSG(atom_ctx.nlist.pin_net(atom_pin) == atom_net, "Sink atom pins should be driven by the same net"); + VTR_ASSERT_MSG(atom_ctx.netlist().pin_net(atom_pin) == atom_net, "Sink atom pins should be driven by the same net"); sink_atom_pins.push_back(atom_pin); } @@ -300,12 +298,12 @@ static AtomPinId find_atom_pin_for_pb_route_id(ClusterBlockId clb, int pb_route_ //It is a leaf, and hence should map to an atom //Find the associated atom - AtomBlockId atom_block = atom_ctx.lookup.pb_atom(child_pb); + AtomBlockId atom_block = atom_ctx.lookup().atom_pb_bimap().pb_atom(child_pb); VTR_ASSERT(atom_block); //Now find the matching pin by seeing which pin maps to the gpin - for (AtomPinId atom_pin : atom_ctx.nlist.block_pins(atom_block)) { - const t_pb_graph_pin* atom_pin_gpin = atom_ctx.lookup.atom_pin_pb_graph_pin(atom_pin); + for (AtomPinId atom_pin : atom_ctx.netlist().block_pins(atom_block)) { + const t_pb_graph_pin* atom_pin_gpin = atom_ctx.lookup().atom_pin_pb_graph_pin(atom_pin); if (atom_pin_gpin == gpin) { //Match return atom_pin; @@ -413,7 +411,7 @@ t_physical_tile_type_ptr physical_tile_type(t_pl_loc loc) { } t_physical_tile_type_ptr physical_tile_type(AtomBlockId atom_blk) { - auto& atom_look_up = g_vpr_ctx.atom().lookup; + auto& atom_look_up = g_vpr_ctx.atom().lookup(); auto& block_locs = g_vpr_ctx.placement().block_locs(); ClusterBlockId cluster_blk = atom_look_up.atom_clb(atom_blk); @@ -512,12 +510,12 @@ t_class_range get_class_range_for_block(const ClusterBlockId blk_id) { } t_class_range get_class_range_for_block(const AtomBlockId atom_blk) { - auto& atom_look_up = g_vpr_ctx.atom().lookup; + auto& atom_look_up = g_vpr_ctx.atom().lookup(); ClusterBlockId cluster_blk = atom_look_up.atom_clb(atom_blk); auto [physical_tile, sub_tile, sub_tile_cap, logical_block] = get_cluster_blk_physical_spec(cluster_blk); - const t_pb_graph_node* pb_graph_node = atom_look_up.atom_pb_graph_node(atom_blk); + const t_pb_graph_node* pb_graph_node = atom_look_up.atom_pb_bimap().atom_pb_graph_node(atom_blk); VTR_ASSERT(pb_graph_node != nullptr); return get_pb_graph_node_class_physical_range(physical_tile, sub_tile, @@ -569,7 +567,7 @@ t_block_loc get_block_loc(const ParentBlockId& block_id, bool is_flat) { if (is_flat) { AtomBlockId atom_block_id = convert_to_atom_block_id(block_id); - auto& atom_look_up = g_vpr_ctx.atom().lookup; + auto& atom_look_up = g_vpr_ctx.atom().lookup(); cluster_block_id = atom_look_up.atom_clb(atom_block_id); } else { cluster_block_id = convert_to_cluster_block_id(block_id); @@ -706,7 +704,7 @@ InstPort parse_inst_port(const std::string& str) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find block type named %s", inst_port.instance_name().c_str()); } - int num_pins = find_tile_port_by_name(blk_type, inst_port.port_name().c_str()).num_pins; + int num_pins = find_tile_port_by_name(blk_type, inst_port.port_name()).num_pins; if (num_pins == OPEN) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find port %s on block type %s", inst_port.port_name().c_str(), inst_port.instance_name().c_str()); @@ -830,12 +828,12 @@ bool primitive_type_feasible(const AtomBlockId blk_id, const t_pb_type* cur_pb_t } auto& atom_ctx = g_vpr_ctx.atom(); - if (cur_pb_type->model != atom_ctx.nlist.block_model(blk_id)) { + if (cur_pb_type->model != atom_ctx.netlist().block_model(blk_id)) { //Primitive and atom do not match return false; } - VTR_ASSERT_MSG(atom_ctx.nlist.is_compressed(), "This function assumes a compressed/non-dirty netlist"); + VTR_ASSERT_MSG(atom_ctx.netlist().is_compressed(), "This function assumes a compressed/non-dirty netlist"); //Keep track of how many atom ports were checked. // @@ -851,13 +849,13 @@ bool primitive_type_feasible(const AtomBlockId blk_id, const t_pb_type* cur_pb_t const t_model_ports* pb_model_port = pb_port->model_port; //Find the matching port on the atom - auto port_id = atom_ctx.nlist.find_atom_port(blk_id, pb_model_port); + auto port_id = atom_ctx.netlist().find_atom_port(blk_id, pb_model_port); if (port_id) { //Port is used by the atom //In compressed form the atom netlist stores only in-use pins, //so we can query the number of required pins directly - int required_atom_pins = atom_ctx.nlist.port_pins(port_id).size(); + int required_atom_pins = atom_ctx.netlist().port_pins(port_id).size(); int available_pb_pins = pb_port->num_pins; @@ -874,7 +872,7 @@ bool primitive_type_feasible(const AtomBlockId blk_id, const t_pb_type* cur_pb_t //Similarly to pins, only in-use ports are stored in the compressed //atom netlist, so we can figure out how many ports should have been //checked directly - size_t atom_ports = atom_ctx.nlist.block_ports(blk_id).size(); + size_t atom_ports = atom_ctx.netlist().block_ports(blk_id).size(); //See if all the atom ports were checked if (checked_ports != atom_ports) { @@ -889,8 +887,7 @@ bool primitive_type_feasible(const AtomBlockId blk_id, const t_pb_type* cur_pb_t //Returns the sibling atom of a memory slice pb // Note that the pb must be part of a MEMORY_CLASS -AtomBlockId find_memory_sibling(const t_pb* pb) { - auto& atom_ctx = g_vpr_ctx.atom(); +const t_pb* find_memory_sibling(const t_pb* pb) { const t_pb_type* pb_type = pb->pb_graph_node->pb_type; @@ -902,10 +899,10 @@ AtomBlockId find_memory_sibling(const t_pb* pb) { const t_pb* sibling_pb = &memory_class_pb->child_pbs[pb->mode][isibling]; if (sibling_pb->name != nullptr) { - return atom_ctx.lookup.pb_atom(sibling_pb); + return sibling_pb; } } - return AtomBlockId::INVALID(); + return nullptr; } /** @@ -963,11 +960,11 @@ AtomPinId find_atom_pin(ClusterBlockId blk_id, const t_pb_graph_pin* pb_gpin) { AtomPinId atom_pin; //Look through all the pins on this net, looking for the matching pin - for (AtomPinId pin : atom_ctx.nlist.net_pins(atom_net)) { - AtomBlockId blk = atom_ctx.nlist.pin_block(pin); - if (atom_ctx.lookup.atom_clb(blk) == blk_id) { + for (AtomPinId pin : atom_ctx.netlist().net_pins(atom_net)) { + AtomBlockId blk = atom_ctx.netlist().pin_block(pin); + if (atom_ctx.lookup().atom_clb(blk) == blk_id) { //Part of the same CLB - if (atom_ctx.lookup.atom_pin_pb_graph_pin(pin) == pb_gpin) + if (atom_ctx.lookup().atom_pin_pb_graph_pin(pin) == pb_gpin) //The same pin atom_pin = pin; } @@ -978,15 +975,13 @@ AtomPinId find_atom_pin(ClusterBlockId blk_id, const t_pb_graph_pin* pb_gpin) { return atom_pin; } -//Retrieves the pb_graph_pin associated with an AtomPinId -// Currently this function just wraps get_pb_graph_node_pin_from_model_port_pin() -// in a more convenient interface. -const t_pb_graph_pin* find_pb_graph_pin(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, const AtomPinId pin_id) { +// Retrieves the pb_graph_pin associated with an AtomPinId +const t_pb_graph_pin* find_pb_graph_pin(const AtomNetlist& netlist, const AtomPBBimap& atom_pb_lookup, const AtomPinId pin_id) { VTR_ASSERT(pin_id); //Get the graph node AtomBlockId blk_id = netlist.pin_block(pin_id); - const t_pb_graph_node* pb_gnode = netlist_lookup.atom_pb_graph_node(blk_id); + const t_pb_graph_node* pb_gnode = atom_pb_lookup.atom_pb_graph_node(blk_id); VTR_ASSERT(pb_gnode); //The graph node and pin/block should agree on the model they represent @@ -1254,7 +1249,7 @@ std::vector get_cluster_internal_class_pairs(const AtomLookup& atom_lookup, const auto& cluster_atoms = cluster_ctx.atoms_lookup[cluster_block_id]; for (AtomBlockId atom_blk_id : cluster_atoms) { - auto atom_pb_graph_node = atom_lookup.atom_pb_graph_node(atom_blk_id); + auto atom_pb_graph_node = atom_lookup.atom_pb_bimap().atom_pb_graph_node(atom_blk_id); auto class_range = get_pb_graph_node_class_physical_range(physical_tile, sub_tile, logical_block, @@ -1347,16 +1342,16 @@ int num_ext_inputs_atom_block(AtomBlockId blk_id) { //Record the unique input nets auto& atom_ctx = g_vpr_ctx.atom(); - for (auto pin_id : atom_ctx.nlist.block_input_pins(blk_id)) { - auto net_id = atom_ctx.nlist.pin_net(pin_id); + for (auto pin_id : atom_ctx.netlist().block_input_pins(blk_id)) { + auto net_id = atom_ctx.netlist().pin_net(pin_id); input_nets.insert(net_id); } ext_inps = input_nets.size(); //Look through the output nets for any duplicates of the input nets - for (auto pin_id : atom_ctx.nlist.block_output_pins(blk_id)) { - auto net_id = atom_ctx.nlist.pin_net(pin_id); + for (auto pin_id : atom_ctx.netlist().block_output_pins(blk_id)) { + auto net_id = atom_ctx.netlist().pin_net(pin_id); if (input_nets.count(net_id)) { --ext_inps; } @@ -1367,7 +1362,17 @@ int num_ext_inputs_atom_block(AtomBlockId blk_id) { return (ext_inps); } -void free_pb(t_pb* pb) { +/** + * @brief Free pb and remove its lookup data. + * CLB lookup data is removed from the global context + * and PB to Atom bimap data is removed from atom_pb_bimap + * + * @param pb + * Pointer to t_pb to be freed + * @param atom_pb_bimap + * Reference to the atom to pb bimap to free the data from + */ +void free_pb(t_pb* pb, AtomPBBimap& atom_pb_bimap) { if (pb == nullptr) { return; } @@ -1387,7 +1392,7 @@ void free_pb(t_pb* pb) { for (i = 0; i < pb_type->modes[mode].num_pb_type_children && pb->child_pbs != nullptr; i++) { for (j = 0; j < pb_type->modes[mode].pb_type_children[i].num_pb && pb->child_pbs[i] != nullptr; j++) { if (pb->child_pbs[i][j].name != nullptr || pb->child_pbs[i][j].child_pbs != nullptr) { - free_pb(&pb->child_pbs[i][j]); + free_pb(&pb->child_pbs[i][j], atom_pb_bimap); } } if (pb->child_pbs[i]) { @@ -1405,13 +1410,13 @@ void free_pb(t_pb* pb) { } else { /* Primitive */ auto& atom_ctx = g_vpr_ctx.mutable_atom(); - auto blk_id = atom_ctx.lookup.pb_atom(pb); + auto blk_id = atom_pb_bimap.pb_atom(pb); if (blk_id) { //Update atom netlist mapping - atom_ctx.lookup.set_atom_clb(blk_id, ClusterBlockId::INVALID()); - atom_ctx.lookup.set_atom_pb(blk_id, nullptr); + atom_ctx.mutable_lookup().set_atom_clb(blk_id, ClusterBlockId::INVALID()); + atom_pb_bimap.set_atom_pb(blk_id, nullptr); } - atom_ctx.lookup.set_atom_pb(AtomBlockId::INVALID(), pb); + atom_pb_bimap.set_atom_pb(AtomBlockId::INVALID(), pb); } free_pb_stats(pb); } @@ -1473,7 +1478,8 @@ std::tuple parse_direct_pin_name(std::string std::string source_string{src_string}; // Replace '.' and '[' characters with ' ' - std::replace_if(source_string.begin(), source_string.end(), + std::replace_if( + source_string.begin(), source_string.end(), [](char c) { return c == '.' || c == '[' || c == ':' || c == ']'; }, ' '); @@ -1639,8 +1645,8 @@ int max_pins_per_grid_tile() { } int get_atom_pin_class_num(const AtomPinId atom_pin_id) { - auto& atom_look_up = g_vpr_ctx.atom().lookup; - auto& atom_net_list = g_vpr_ctx.atom().nlist; + auto& atom_look_up = g_vpr_ctx.atom().lookup(); + auto& atom_net_list = g_vpr_ctx.atom().netlist(); auto atom_blk_id = atom_net_list.pin_block(atom_pin_id); auto cluster_block_id = atom_look_up.atom_clb(atom_blk_id); @@ -1859,6 +1865,33 @@ bool node_in_same_physical_tile(RRNodeId node_first, RRNodeId node_second) { } } +bool directconnect_exists(RRNodeId src_rr_node, RRNodeId sink_rr_node) { + const auto& device_ctx = g_vpr_ctx.device(); + const auto& rr_graph = device_ctx.rr_graph; + + VTR_ASSERT(rr_graph.node_type(src_rr_node) == SOURCE && rr_graph.node_type(sink_rr_node) == SINK); + + // A direct connection is defined as a specific path: `SOURCE -> OPIN -> IPIN -> SINK`. + //TODO: This is a constant depth search, but still may be too slow + for (t_edge_size i_src_edge = 0; i_src_edge < rr_graph.num_edges(src_rr_node); ++i_src_edge) { + RRNodeId opin_rr_node = rr_graph.edge_sink_node(src_rr_node, i_src_edge); + + if (rr_graph.node_type(opin_rr_node) != OPIN) continue; + + for (t_edge_size i_opin_edge = 0; i_opin_edge < rr_graph.num_edges(opin_rr_node); ++i_opin_edge) { + RRNodeId ipin_rr_node = rr_graph.edge_sink_node(opin_rr_node, i_opin_edge); + if (rr_graph.node_type(ipin_rr_node) != IPIN) continue; + + for (t_edge_size i_ipin_edge = 0; i_ipin_edge < rr_graph.num_edges(ipin_rr_node); ++i_ipin_edge) { + if (sink_rr_node == rr_graph.edge_sink_node(ipin_rr_node, i_ipin_edge)) { + return true; + } + } + } + } + return false; +} + std::vector get_cluster_netlist_intra_tile_classes_at_loc(int layer, int i, int j, @@ -1866,7 +1899,7 @@ std::vector get_cluster_netlist_intra_tile_classes_at_loc(int layer, std::vector class_num_vec; const auto& place_ctx = g_vpr_ctx.placement(); - const auto& atom_lookup = g_vpr_ctx.atom().lookup; + const auto& atom_lookup = g_vpr_ctx.atom().lookup(); const auto& grid_block = place_ctx.grid_blocks(); class_num_vec.reserve(physical_type->primitive_class_inf.size()); @@ -1988,7 +2021,7 @@ void add_pb_child_to_list(std::list& pb_list, const t_pb* parent_pb void apply_route_constraints(const UserRouteConstraints& route_constraints) { ClusteringContext& mutable_cluster_ctx = g_vpr_ctx.mutable_clustering(); - // Iterate through all the nets + // Iterate through all the nets for (auto net_id : mutable_cluster_ctx.clb_nlist.nets()) { // Get the name of the current net std::string net_name = mutable_cluster_ctx.clb_nlist.net_name(net_id); diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index 37047ab7152..aa36ce3f03c 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -1,23 +1,19 @@ #ifndef VPR_UTILS_H #define VPR_UTILS_H -#include -#include - -#include "vpr_types.h" -#include "vtr_vector.h" - -#include "atom_netlist.h" -#include "clustered_netlist.h" -#include "netlist.h" #include "arch_util.h" -#include "physical_types_util.h" +#include "atom_netlist.h" +#include "device_grid.h" #include "rr_graph_utils.h" -#include "vpr_constraints.h" +#include "vpr_types.h" +#include "vtr_vector.h" +#include "atom_pb_bimap.h" +#include +#include +// Forward declaration class DeviceGrid; -class PlacerState; -class Prepacker; +class UserRouteConstraints; const t_model* find_model(const t_model* models, const std::string& name, bool required = true); const t_model_ports* find_model_port(const t_model* model, const std::string& name, bool required = true); @@ -171,6 +167,8 @@ const t_port* find_pb_graph_port(const t_pb_graph_node* pb_gnode, const std::str //Returns the graph pin matching name at pin index const t_pb_graph_pin* find_pb_graph_pin(const t_pb_graph_node* pb_gnode, const std::string& port_name, int index); +const t_pb_graph_pin* find_pb_graph_pin(const AtomNetlist& netlist, const AtomPBBimap& atom_pb_lookup, const AtomPinId pin_id); + AtomPinId find_atom_pin(ClusterBlockId blk_id, const t_pb_graph_pin* pb_gpin); //Returns the logical block type which is most common in the device grid @@ -191,7 +189,6 @@ int get_max_depth_of_pb_type(t_pb_type* pb_type); int get_max_nets_in_pb_type(const t_pb_type* pb_type); bool primitive_type_feasible(AtomBlockId blk_id, const t_pb_type* cur_pb_type); t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(const t_model_ports* model_port, const int model_pin, const t_pb_graph_node* pb_graph_node); -const t_pb_graph_pin* find_pb_graph_pin(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, const AtomPinId pin_id); /// @brief Gets the pb_graph_node pin at the given pin index for the given /// pb_graph_node. t_pb_graph_pin* get_pb_graph_node_pin_from_pb_graph_node(t_pb_graph_node* pb_graph_node, int ipin); @@ -225,12 +222,12 @@ int num_ext_inputs_atom_block(AtomBlockId blk_id); std::tuple parse_direct_pin_name(std::string_view src_string, int line); void free_pb_stats(t_pb* pb); -void free_pb(t_pb* pb); +void free_pb(t_pb* pb, AtomPBBimap& atom_pb_bimap); void print_switch_usage(); void print_usage_by_wire_length(); -AtomBlockId find_memory_sibling(const t_pb* pb); +const t_pb* find_memory_sibling(const t_pb* pb); int get_atom_pin_class_num(const AtomPinId atom_pin_id); @@ -271,9 +268,28 @@ RRNodeId get_class_rr_node_id(const RRSpatialLookup& rr_spatial_lookup, const int j, int class_physical_num); -// Check whether the given nodes are in the same cluster +/// @brief Check whether the given nodes are in the same cluster bool node_in_same_physical_tile(RRNodeId node_first, RRNodeId node_second); +/** + * @brief Checks if a direct connection exists between two RR nodes. + * + * A direct connection is defined as a specific path: `SOURCE -> OPIN -> IPIN -> SINK`. + * + * @param src_rr_node The source RR node (must be of type `SOURCE`). + * @param sink_rr_node The sink RR node (must be of type `SINK`). + * + * @return `true` if a direct connection exists between the source and sink nodes; + * otherwise, `false`. + * + * @details + * - The function performs a depth-limited search starting from the source node, + * traversing through OPIN, IPIN, and finally checking if the path reaches the sink node. + * - Ensures the specified node types are respected (e.g., source node must be of type `SOURCE`). + */ + +bool directconnect_exists(RRNodeId src_rr_node, RRNodeId sink_rr_node); + std::vector get_cluster_netlist_intra_tile_classes_at_loc(int layer, int i, int j, diff --git a/vpr/test/test_ap_netlist.cpp b/vpr/test/test_ap_netlist.cpp index 9dad87819ca..b88528c721e 100644 --- a/vpr/test/test_ap_netlist.cpp +++ b/vpr/test/test_ap_netlist.cpp @@ -11,7 +11,7 @@ #include "catch2/catch_test_macros.hpp" #include "ap_netlist.h" -#include "vpr_types.h" +#include "prepack.h" namespace { @@ -19,18 +19,18 @@ TEST_CASE("test_ap_netlist_data_storage", "[vpr_ap_netlist]") { // Create a test netlist object. APNetlist test_netlist("test_netlist"); // Create a few molecules. - t_pack_molecule mol_a; - t_pack_molecule mol_b; - t_pack_molecule mol_c; + PackMoleculeId mol_a_id; + PackMoleculeId mol_b_id; + PackMoleculeId mol_c_id; // Create blocks for these molecules. - APBlockId block_id_a = test_netlist.create_block("BlockA", &mol_a); - APBlockId block_id_b = test_netlist.create_block("BlockB", &mol_b); - APBlockId block_id_c = test_netlist.create_block("BlockC", &mol_c); + APBlockId block_id_a = test_netlist.create_block("BlockA", mol_a_id); + APBlockId block_id_b = test_netlist.create_block("BlockB", mol_b_id); + APBlockId block_id_c = test_netlist.create_block("BlockC", mol_c_id); SECTION("Test block_molecule returns the correct molecule after creation") { - REQUIRE(test_netlist.block_molecule(block_id_a) == &mol_a); - REQUIRE(test_netlist.block_molecule(block_id_b) == &mol_b); - REQUIRE(test_netlist.block_molecule(block_id_c) == &mol_c); + REQUIRE(test_netlist.block_molecule(block_id_a) == mol_a_id); + REQUIRE(test_netlist.block_molecule(block_id_b) == mol_b_id); + REQUIRE(test_netlist.block_molecule(block_id_c) == mol_c_id); } // Delete block B to reorganize the blocks internally. @@ -42,13 +42,13 @@ TEST_CASE("test_ap_netlist_data_storage", "[vpr_ap_netlist]") { block_id_c = test_netlist.find_block("BlockC"); SECTION("Test block_molecule returns the correct molecule after compression") { - REQUIRE(test_netlist.block_molecule(block_id_a) == &mol_a); - REQUIRE(test_netlist.block_molecule(block_id_c) == &mol_c); + REQUIRE(test_netlist.block_molecule(block_id_a) == mol_a_id); + REQUIRE(test_netlist.block_molecule(block_id_c) == mol_c_id); } // Create a new block, and fix its location. - t_pack_molecule fixed_mol; - APBlockId fixed_block_id = test_netlist.create_block("FixedBlock", &fixed_mol); + PackMoleculeId fixed_mol_id; + APBlockId fixed_block_id = test_netlist.create_block("FixedBlock", fixed_mol_id); APFixedBlockLoc fixed_block_loc; fixed_block_loc.x = 12; fixed_block_loc.y = 42; @@ -74,4 +74,3 @@ TEST_CASE("test_ap_netlist_data_storage", "[vpr_ap_netlist]") { } } // namespace - diff --git a/vpr/test/test_ap_partial_placement.cpp b/vpr/test/test_ap_partial_placement.cpp index c460df48227..29abf5b705b 100644 --- a/vpr/test/test_ap_partial_placement.cpp +++ b/vpr/test/test_ap_partial_placement.cpp @@ -12,7 +12,7 @@ #include "ap_netlist.h" #include "partial_placement.h" -#include "vpr_types.h" +#include "prepack.h" namespace { @@ -20,13 +20,13 @@ TEST_CASE("test_ap_partial_placement_verify", "[vpr_ap]") { // Create a test netlist object. APNetlist test_netlist("test_netlist"); // Create a few molecules. - t_pack_molecule mol_a; - t_pack_molecule mol_b; - t_pack_molecule mol_c; + PackMoleculeId mol_a_id; + PackMoleculeId mol_b_id; + PackMoleculeId mol_c_id; // Create blocks for these molecules. - APBlockId block_id_a = test_netlist.create_block("BlockA", &mol_a); - APBlockId block_id_b = test_netlist.create_block("BlockB", &mol_b); - APBlockId block_id_c = test_netlist.create_block("BlockC", &mol_c); + APBlockId block_id_a = test_netlist.create_block("BlockA", mol_a_id); + APBlockId block_id_b = test_netlist.create_block("BlockB", mol_b_id); + APBlockId block_id_c = test_netlist.create_block("BlockC", mol_c_id); // Fix BlockC. APFixedBlockLoc fixed_block_loc; fixed_block_loc.x = 12; @@ -131,4 +131,3 @@ TEST_CASE("test_ap_partial_placement_verify", "[vpr_ap]") { } } // namespace - diff --git a/vpr/test/test_ap_primitive_vector.cpp b/vpr/test/test_ap_primitive_vector.cpp index e1f114919bb..425f4e20f35 100644 --- a/vpr/test/test_ap_primitive_vector.cpp +++ b/vpr/test/test_ap_primitive_vector.cpp @@ -8,6 +8,7 @@ * PrimitiveVector object are working as expected. */ +#include #include "catch2/catch_test_macros.hpp" #include "primitive_vector.h" @@ -310,7 +311,60 @@ TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { res = PrimitiveVector::max(vec2, vec1); REQUIRE(res == golden); } + + SECTION("Test more operators and methods") { + PrimitiveVector vec1, vec2; + + // Subtract value from dimension + vec1.set_dim_val(0, 5.f); + vec1.subtract_val_from_dim(3.f, 0); + REQUIRE(vec1.get_dim_val(0) == 2.f); + + // Element-wise addition operator + vec1.clear(); + vec1.set_dim_val(0, 1.f); + vec1.set_dim_val(1, 2.f); + vec2.clear(); + vec2.set_dim_val(0, 3.f); + vec2.set_dim_val(1, 4.f); + PrimitiveVector vec_sum = vec1 + vec2; + REQUIRE(vec_sum.get_dim_val(0) == 4.f); + REQUIRE(vec_sum.get_dim_val(1) == 6.f); + + // Element-wise division operator + vec1.clear(); + vec1.set_dim_val(0, 10.f); + vec1.set_dim_val(1, 20.f); + vec1 /= 2.f; + REQUIRE(vec1.get_dim_val(0) == 5.f); + REQUIRE(vec1.get_dim_val(1) == 10.f); + + // Element-wise division operator (const) + vec1.clear(); + vec1.set_dim_val(0, 10.f); + vec1.set_dim_val(1, 20.f); + PrimitiveVector vec_div = vec1 / 2.f; + REQUIRE(vec_div.get_dim_val(0) == 5.f); + REQUIRE(vec_div.get_dim_val(1) == 10.f); + + // Get non-zero dimensions + vec1.clear(); + vec1.set_dim_val(0, 1.f); + vec1.set_dim_val(2, 3.f); + std::vector non_zero_dims = vec1.get_non_zero_dims(); + REQUIRE(std::find(non_zero_dims.begin(), non_zero_dims.end(), 0) != non_zero_dims.end()); + REQUIRE(std::find(non_zero_dims.begin(), non_zero_dims.end(), 2) != non_zero_dims.end()); + REQUIRE(std::find(non_zero_dims.begin(), non_zero_dims.end(), 1) == non_zero_dims.end()); + + // Test orthogonal vectors + vec1.clear(); + vec2.clear(); + vec1.set_dim_val(0, 1.f); + vec2.set_dim_val(1, 2.f); + REQUIRE(vec1.are_dims_disjoint(vec2)); + vec2.set_dim_val(0, 3.f); + REQUIRE(!vec1.are_dims_disjoint(vec2)); + } } } // namespace - diff --git a/vpr/test/test_bfs_routing.cpp b/vpr/test/test_bfs_routing.cpp index c0c03a9ad1d..61d98a3c200 100644 --- a/vpr/test/test_bfs_routing.cpp +++ b/vpr/test/test_bfs_routing.cpp @@ -139,4 +139,4 @@ TEST_CASE("test_route_flow", "[vpr_noc_bfs_routing]") { } } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_clustered_netlist.cpp b/vpr/test/test_clustered_netlist.cpp index cd0059c173e..bcd42988068 100644 --- a/vpr/test/test_clustered_netlist.cpp +++ b/vpr/test/test_clustered_netlist.cpp @@ -146,4 +146,4 @@ TEST_CASE("test_find_block_with_matching_name", "[vpr_clustered_netlist]") { REQUIRE((size_t)(block_id_from_name.find("router:noc_router_four|flit_out_two[0]~reg0")->second) == (size_t)test_router_id); } } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_compressed_grid.cpp b/vpr/test/test_compressed_grid.cpp index 86c2d1f6600..028a1164af9 100644 --- a/vpr/test/test_compressed_grid.cpp +++ b/vpr/test/test_compressed_grid.cpp @@ -12,8 +12,7 @@ namespace { -void set_type_tile_to_empty(const int x, const int y, - vtr::NdMatrix& grid) { +void set_type_tile_to_empty(const int x, const int y, vtr::NdMatrix& grid) { t_physical_tile_type_ptr type = grid[0][x][y].type; const int width_offset = grid[0][x][y].width_offset; const int height_offset = grid[0][x][y].height_offset; @@ -29,12 +28,9 @@ void set_type_tile_to_empty(const int x, const int y, } } } - } -void set_tile_type_at_loc(const int x_anchor, const int y_anchor, - vtr::NdMatrix& grid, - const t_physical_tile_type& tile_type) { +void set_tile_type_at_loc(const int x_anchor, const int y_anchor, vtr::NdMatrix& grid, const t_physical_tile_type& tile_type) { for (int i = x_anchor; i < x_anchor + tile_type.width; i++) { for (int j = y_anchor; j < y_anchor + tile_type.height; j++) { @@ -48,7 +44,6 @@ void set_tile_type_at_loc(const int x_anchor, const int y_anchor, } } - TEST_CASE("test_compressed_grid", "[vpr_compressed_grid]") { // test device grid name std::string device_grid_name = "test"; @@ -70,7 +65,6 @@ TEST_CASE("test_compressed_grid", "[vpr_compressed_grid]") { auto& logical_block_types = g_vpr_ctx.mutable_device().logical_block_types; logical_block_types.clear(); - t_physical_tile_type empty_tile; empty_tile.name = empty_tile_name; empty_tile.height = 1; @@ -87,7 +81,6 @@ TEST_CASE("test_compressed_grid", "[vpr_compressed_grid]") { empty_tile.sub_tiles.back().index = 0; empty_tile.sub_tiles.back().equivalent_sites.push_back(&EMPTY_LOGICAL_BLOCK_TYPE); - // create an io physical tile and assign its parameters t_physical_tile_type io_tile; io_tile.name = io_tile_name; @@ -130,7 +123,6 @@ TEST_CASE("test_compressed_grid", "[vpr_compressed_grid]") { tall_logical_type.equivalent_tiles.push_back(&tall_tile); logical_block_types.push_back(tall_logical_type); - tall_tile.sub_tiles.back().index = 0; tall_tile.sub_tiles.back().equivalent_sites.push_back(&tall_logical_type); @@ -148,7 +140,6 @@ TEST_CASE("test_compressed_grid", "[vpr_compressed_grid]") { large_tile.sub_tiles.back().index = 0; large_tile.sub_tiles.back().equivalent_sites.push_back(&large_logical_type); - for (int x = 0; x < test_grid_width; x++) { for (int y = 0; y < test_grid_height; y++) { test_grid[0][x][y].type = &io_tile; @@ -330,6 +321,7 @@ TEST_CASE("test_compressed_grid", "[vpr_compressed_grid]") { REQUIRE(grid_loc == t_physical_tile_loc{98, 98, 0}); } + logical_block_types.clear(); } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_connection_router.cpp b/vpr/test/test_connection_router.cpp index a106ad80a80..138e003b04e 100644 --- a/vpr/test/test_connection_router.cpp +++ b/vpr/test/test_connection_router.cpp @@ -8,7 +8,8 @@ #include "globals.h" #include "net_delay.h" #include "place_and_route.h" -#include "timing_place_lookup.h" +#include "connection_router.h" +#include "router_delay_profiling.h" static constexpr const char kArchFile[] = "../../vtr_flow/arch/timing/k6_frac_N10_mem32K_40nm.xml"; static constexpr int kMaxHops = 10; @@ -44,7 +45,7 @@ static float do_one_route(RRNodeId source_node, cost_params.astar_offset = router_opts.astar_offset; cost_params.bend_cost = router_opts.bend_cost; - const Netlist<>& net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + const Netlist<>& net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; route_budgets budgeting_inf(net_list, is_flat); RouterStats router_stats; @@ -142,19 +143,18 @@ TEST_CASE("connection_router", "[vpr]") { kArchFile, "wire.eblif", "--route_chan_width", "100"}; - vpr_init(sizeof(argv) / sizeof(argv[0]), argv, - &options, &vpr_setup, &arch); + vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); vpr_create_device_grid(vpr_setup, arch); vpr_setup_clock_networks(vpr_setup, arch); auto det_routing_arch = &vpr_setup.RoutingArch; auto& router_opts = vpr_setup.RouterOpts; - t_graph_type graph_directionality; + e_graph_type graph_directionality; if (router_opts.route_type == GLOBAL) { - graph_directionality = GRAPH_BIDIR; + graph_directionality = e_graph_type::BIDIR; } else { - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } auto chan_width = init_chan(vpr_setup.RouterOpts.fixed_channel_width, arch.Chans, graph_directionality); @@ -188,8 +188,7 @@ TEST_CASE("connection_router", "[vpr]") { // Clean up free_routing_structs(); - vpr_free_all(arch, - vpr_setup); + vpr_free_all(arch, vpr_setup); } } // namespace diff --git a/vpr/test/test_edge_groups.cpp b/vpr/test/test_edge_groups.cpp index 80bfea5e133..e8b83741afa 100644 --- a/vpr/test/test_edge_groups.cpp +++ b/vpr/test/test_edge_groups.cpp @@ -19,12 +19,12 @@ TEST_CASE("edge_groups_create_sets", "[vpr]") { // Build chains from the given connected sets int max_node_id = 0; std::vector> edges; - for (auto set : connected_sets) { + for (const auto& set : connected_sets) { int last = *set.cbegin(); std::for_each(std::next(set.cbegin()), set.cend(), [&](int node) { - edges.push_back(std::make_pair(last, node)); + edges.emplace_back(last, node); last = node; max_node_id = std::max(max_node_id, node); }); @@ -36,7 +36,7 @@ TEST_CASE("edge_groups_create_sets", "[vpr]") { // Initialize nodes to [0, 1, ..., max_node_id] std::iota(nodes.begin(), nodes.end(), 0); - // Create a Mersenne Twister psuedo-random number generator with seed 1 + // Create a Mersenne Twister pseudo-random number generator with seed 1 std::mt19937 g(1); // Run the test many times, the PRNG will give differently shuffled inputs @@ -66,12 +66,12 @@ TEST_CASE("edge_groups_create_sets", "[vpr]") { t_non_configurable_rr_sets sets = groups.output_sets(); // Check for the expected sets - for (auto set : connected_sets) { + for (const auto& set : connected_sets) { std::set random_set; for (auto elem : set) { random_set.insert(RRNodeId(random_nodes[elem])); } - REQUIRE(sets.node_sets.find(random_set) != sets.node_sets.end()); + REQUIRE(std::find(sets.node_sets.begin(), sets.node_sets.end(), random_set) != sets.node_sets.end()); } } } diff --git a/vpr/test/test_flat_placement_types.cpp b/vpr/test/test_flat_placement_types.cpp new file mode 100644 index 00000000000..b8daaaf61ea --- /dev/null +++ b/vpr/test/test_flat_placement_types.cpp @@ -0,0 +1,49 @@ +/** + * @file + * @author Alex Singer + * @date March 2025 + * @brief Unit tests for flat placement types + */ + +#include +#include "catch2/catch_test_macros.hpp" +#include "flat_placement_types.h" + +namespace { + +TEST_CASE("test_t_flat_pl_loc", "[vpr_flat_pl_types]") { + SECTION("Test addition operator") { + t_flat_pl_loc loc1{1.0f, 2.0f, 3.0f}; + t_flat_pl_loc loc2{4.0f, 5.0f, 6.0f}; + + loc1 += loc2; + + REQUIRE(loc1.x == Catch::Approx(5.0f)); + REQUIRE(loc1.y == Catch::Approx(7.0f)); + REQUIRE(loc1.layer == Catch::Approx(9.0f)); + } + + SECTION("Test division operator") { + t_flat_pl_loc loc{10.0f, 20.0f, 30.0f}; + + loc /= 2.0f; + + REQUIRE(loc.x == Catch::Approx(5.0f)); + REQUIRE(loc.y == Catch::Approx(10.0f)); + REQUIRE(loc.layer == Catch::Approx(15.0f)); + } + + SECTION("Test addition and division operators combined") { + t_flat_pl_loc loc1{1.0f, 2.0f, 3.0f}; + t_flat_pl_loc loc2{4.0f, 5.0f, 6.0f}; + + loc1 += loc2; + loc1 /= 2.0f; + + REQUIRE(loc1.x == Catch::Approx(2.5f)); + REQUIRE(loc1.y == Catch::Approx(3.5f)); + REQUIRE(loc1.layer == Catch::Approx(4.5f)); + } +} + +} // namespace diff --git a/vpr/test/test_interchange_device.cpp b/vpr/test/test_interchange_device.cpp index 6ab763ec5d8..f344adace1b 100644 --- a/vpr/test/test_interchange_device.cpp +++ b/vpr/test/test_interchange_device.cpp @@ -96,7 +96,7 @@ TEST_CASE("read_interchange_luts", "[vpr]") { for (auto lut_bel : lut_element.lut_bels) { CHECK(lut_bels.find(lut_bel.name) != lut_bels.end()); REQUIRE(lut_bel.output_pin == std::string("O")); - for (const std::string &lut_pin : lut_bel.input_pins) + for (const std::string& lut_pin : lut_bel.input_pins) CHECK(lut_bel_pins.find(lut_pin) != lut_bel_pins.end()); } } diff --git a/vpr/test/test_interchange_netlist.cpp b/vpr/test/test_interchange_netlist.cpp index 2af1b33a96f..ac1fdfb15f9 100644 --- a/vpr/test/test_interchange_netlist.cpp +++ b/vpr/test/test_interchange_netlist.cpp @@ -27,7 +27,7 @@ TEST_CASE("read_interchange_netlist", "[vpr]") { /* Read blif file and sweep unused components */ auto& atom_ctx = g_vpr_ctx.mutable_atom(); - atom_ctx.nlist = read_and_process_circuit(e_circuit_format::FPGA_INTERCHANGE, vpr_setup, arch); + atom_ctx.mutable_netlist() = read_and_process_circuit(e_circuit_format::FPGA_INTERCHANGE, vpr_setup, arch); } } // namespace diff --git a/vpr/test/test_noc_place_utils.cpp b/vpr/test/test_noc_place_utils.cpp index 59e8ca70cf2..515608c1a19 100644 --- a/vpr/test/test_noc_place_utils.cpp +++ b/vpr/test/test_noc_place_utils.cpp @@ -172,7 +172,7 @@ TEST_CASE("test_initial_noc_placement", "[noc_place_utils]") { // route it routing_algorithm->route_flow((NocRouterId)source_hard_router_id, (NocRouterId)sink_hard_routed_id, - (NocTrafficFlowId) traffic_flow_number, + (NocTrafficFlowId)traffic_flow_number, traffic_flow_route, noc_ctx.noc_model); } diff --git a/vpr/test/test_noc_storage.cpp b/vpr/test/test_noc_storage.cpp index 0320fa130dc..225614a43a2 100644 --- a/vpr/test/test_noc_storage.cpp +++ b/vpr/test/test_noc_storage.cpp @@ -457,4 +457,4 @@ TEST_CASE("test_generate_router_key_from_grid_location", "[vpr_noc]") { } } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_noc_traffic_flows.cpp b/vpr/test/test_noc_traffic_flows.cpp index 1afd37727e6..ea5806d3261 100644 --- a/vpr/test/test_noc_traffic_flows.cpp +++ b/vpr/test/test_noc_traffic_flows.cpp @@ -133,4 +133,4 @@ TEST_CASE("test_adding_traffic_flows", "[vpr_noc_traffic_flows]") { REQUIRE(traffic_flow_storage.get_traffic_flows_associated_to_router_block(invalid_block).empty()); } } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_odd_even_routing.cpp b/vpr/test/test_odd_even_routing.cpp index c0cf9278bee..4f00b7d2663 100644 --- a/vpr/test/test_odd_even_routing.cpp +++ b/vpr/test/test_odd_even_routing.cpp @@ -38,7 +38,6 @@ void compare_routes(const std::vector& golden_path, } } - void check_turn_legality(const vtr::vector>& traffic_flow_routes, const NocStorage& noc_model, const TurnModelRouting& routing_algorithm) { @@ -229,7 +228,7 @@ TEST_CASE("test_route_flow", "[vpr_noc_odd_even_routing]") { SECTION("Test case where multiple traffic flows are routed, and routes are checked for turn legality and deadlock freedom.") { std::random_device device; std::mt19937 rand_num_gen(device()); - std::uniform_int_distribution dist(0, 99); + std::uniform_int_distribution dist(0, 99); NocTrafficFlows traffic_flow_storage; @@ -264,4 +263,4 @@ TEST_CASE("test_route_flow", "[vpr_noc_odd_even_routing]") { } } -} \ No newline at end of file +} // namespace diff --git a/vpr/test/test_post_verilog.cpp b/vpr/test/test_post_verilog.cpp index a8344fa79d4..ca1a250b7d2 100644 --- a/vpr/test/test_post_verilog.cpp +++ b/vpr/test/test_post_verilog.cpp @@ -1,7 +1,7 @@ #include "catch2/catch_test_macros.hpp" #include "vpr_api.h" -#include "timing_place_lookup.h" +#include "router_delay_profiling.h" #include #include diff --git a/vpr/test/test_read_rr_edge_override.txt b/vpr/test/test_read_rr_edge_override.txt new file mode 100644 index 00000000000..05cccc8cbb9 --- /dev/null +++ b/vpr/test/test_read_rr_edge_override.txt @@ -0,0 +1,9 @@ +# edge Tdel +12 5.9e-11 +1586 4.2e-11 +1111 7.1e-11 +1324 9.4e-11 +(645, 127) 7.3e-11 +(591, 347) 7.9e-11 +(544, 45) 8.3e-11 +(37 , 511) 9.5e-11 \ No newline at end of file diff --git a/vpr/test/test_read_xml_noc_traffic_flows_file.cpp b/vpr/test/test_read_xml_noc_traffic_flows_file.cpp index f16a5d9feff..17aedd6bad1 100644 --- a/vpr/test/test_read_xml_noc_traffic_flows_file.cpp +++ b/vpr/test/test_read_xml_noc_traffic_flows_file.cpp @@ -553,4 +553,4 @@ TEST_CASE("test_get_cluster_blocks_compatible_with_noc_router_tiles", "[vpr_noc_ free_clustered_netlist(); } } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_server_convertutils.cpp b/vpr/test/test_server_convertutils.cpp index d3f64b81816..2006170de46 100644 --- a/vpr/test/test_server_convertutils.cpp +++ b/vpr/test/test_server_convertutils.cpp @@ -5,8 +5,7 @@ #include "convertutils.h" -TEST_CASE("test_server_convert_utils_to_int", "[vpr]") -{ +TEST_CASE("test_server_convert_utils_to_int", "[vpr]") { REQUIRE(std::optional{-2} == try_convert_to_int("-2")); REQUIRE(std::optional{0} == try_convert_to_int("0")); REQUIRE(std::optional{2} == try_convert_to_int("2")); @@ -18,4 +17,3 @@ TEST_CASE("test_server_convert_utils_to_int", "[vpr]") } #endif /* NO_SERVER */ - diff --git a/vpr/test/test_server_taskresolver.cpp b/vpr/test/test_server_taskresolver.cpp index eda8d5ae82f..20c6a865183 100644 --- a/vpr/test/test_server_taskresolver.cpp +++ b/vpr/test/test_server_taskresolver.cpp @@ -29,7 +29,7 @@ TEST_CASE("test_server_taskresolver_cmdSpamFilter", "[vpr]") { REQUIRE(finished.size() == 4); - for (const auto& task: finished) { + for (const auto& task : finished) { REQUIRE(task->is_finished()); REQUIRE(task->has_error()); REQUIRE(task->job_id() != 1); @@ -60,7 +60,7 @@ TEST_CASE("test_server_taskresolver_cmdOverrideFilter", "[vpr]") { REQUIRE(finished.size() == 2); - for (const server::TaskPtr& task: finished) { + for (const server::TaskPtr& task : finished) { REQUIRE(task->is_finished()); REQUIRE(task->has_error()); REQUIRE(task->job_id() != 3); @@ -112,4 +112,4 @@ TEST_CASE("test_server_taskresolver_cmdSpamAndOverrideOptions", "[vpr]") { REQUIRE(task1->options() == ""); } -#endif /* NO_SERVER */ \ No newline at end of file +#endif /* NO_SERVER */ diff --git a/vpr/test/test_server_telegrambuffer.cpp b/vpr/test/test_server_telegrambuffer.cpp index 6c5c793c3d2..1b20a3c312f 100644 --- a/vpr/test/test_server_telegrambuffer.cpp +++ b/vpr/test/test_server_telegrambuffer.cpp @@ -47,8 +47,7 @@ TEST_CASE("test_server_telegrambuffer_oneOpened", "[vpr]") { REQUIRE(std::string_view{buff.data()} == "111222"); } -TEST_CASE("test_server_telegrambuffer_notFilledTelegramButWithPrependedRubish", "[vpr]") -{ +TEST_CASE("test_server_telegrambuffer_notFilledTelegramButWithPrependedRubish", "[vpr]") { comm::TelegramBuffer tBuff; const comm::ByteArray rubbish{"#@!"}; @@ -65,8 +64,7 @@ TEST_CASE("test_server_telegrambuffer_notFilledTelegramButWithPrependedRubish", REQUIRE(msgHeader.buffer() == tBuff.data()); // the rubbish prefix fragment will be absent here } -TEST_CASE("test_server_telegrambuffer__oneFinishedOneOpened", "[vpr]") -{ +TEST_CASE("test_server_telegrambuffer__oneFinishedOneOpened", "[vpr]") { comm::TelegramBuffer tBuff; const comm::ByteArray msgBody1{"message1"}; @@ -80,7 +78,7 @@ TEST_CASE("test_server_telegrambuffer__oneFinishedOneOpened", "[vpr]") comm::ByteArray t2(msgHeader2.buffer()); t2.append(msgBody2); - t2.resize(t2.size()-2); // drop 2 last elements + t2.resize(t2.size() - 2); // drop 2 last elements tBuff.append(t1); tBuff.append(t2); @@ -94,8 +92,7 @@ TEST_CASE("test_server_telegrambuffer__oneFinishedOneOpened", "[vpr]") REQUIRE(t2 == tBuff.data()); } -TEST_CASE("test_server_telegrambuffer_twoFinished", "[vpr]") -{ +TEST_CASE("test_server_telegrambuffer_twoFinished", "[vpr]") { comm::TelegramBuffer tBuff; const comm::ByteArray msgBody1{"message1"}; @@ -123,8 +120,7 @@ TEST_CASE("test_server_telegrambuffer_twoFinished", "[vpr]") REQUIRE(comm::ByteArray{} == tBuff.data()); } -TEST_CASE("test_server_telegrambuffer_clear", "[vpr]") -{ +TEST_CASE("test_server_telegrambuffer_clear", "[vpr]") { comm::TelegramBuffer tBuff; const comm::ByteArray msgBody1{"message1"}; @@ -148,4 +144,4 @@ TEST_CASE("test_server_telegrambuffer_clear", "[vpr]") REQUIRE(comm::ByteArray{} == tBuff.data()); } -#endif /* NO_SERVER */ \ No newline at end of file +#endif /* NO_SERVER */ diff --git a/vpr/test/test_server_telegramoptions.cpp b/vpr/test/test_server_telegramoptions.cpp index d7b3160a0d1..e49b684bc72 100644 --- a/vpr/test/test_server_telegramoptions.cpp +++ b/vpr/test/test_server_telegramoptions.cpp @@ -27,4 +27,4 @@ TEST_CASE("test_server_telegramoptions_get_wrong_keys", "[vpr]") { REQUIRE(options.get_bool("_is_flat_routing", true) == true); } -#endif /* NO_SERVER */ \ No newline at end of file +#endif /* NO_SERVER */ diff --git a/vpr/test/test_server_telegramparser.cpp b/vpr/test/test_server_telegramparser.cpp index 0d7f0c2276c..a3ac0defa4e 100644 --- a/vpr/test/test_server_telegramparser.cpp +++ b/vpr/test/test_server_telegramparser.cpp @@ -5,8 +5,7 @@ #include "catch2/catch_test_macros.hpp" #include "catch2/matchers/catch_matchers_all.hpp" -TEST_CASE("test_server_telegram_parser_base", "[vpr]") -{ +TEST_CASE("test_server_telegram_parser_base", "[vpr]") { const std::string tdata{R"({"JOB_ID":"7","CMD":"2","OPTIONS":"type1:name1:value1;type2:name2:v a l u e 2;t3:n3:v3","DATA":"some_data...","STATUS":"1"})"}; REQUIRE(std::optional{7} == comm::TelegramParser::try_extract_field_job_id(tdata)); @@ -16,10 +15,9 @@ TEST_CASE("test_server_telegram_parser_base", "[vpr]") REQUIRE(std::optional{1} == comm::TelegramParser::try_extract_field_status(tdata)); } -TEST_CASE("test_server_telegram_parser_invalid_keys", "[vpr]") -{ +TEST_CASE("test_server_telegram_parser_invalid_keys", "[vpr]") { const std::string tBadData{R"({"_JOB_ID":"7","_CMD":"2","_OPTIONS":"type1:name1:value1;type2:name2:v a l u e 2;t3:n3:v3","_DATA":"some_data...","_STATUS":"1"})"}; - + REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_job_id(tBadData)); REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_cmd(tBadData)); REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_options(tBadData)); @@ -27,13 +25,12 @@ TEST_CASE("test_server_telegram_parser_invalid_keys", "[vpr]") REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_status(tBadData)); } -TEST_CASE("test_server_telegram_parser_invalid_types", "[vpr]") -{ +TEST_CASE("test_server_telegram_parser_invalid_types", "[vpr]") { const std::string tBadData{R"({"JOB_ID":"x","CMD":"y","STATUS":"z"})"}; - + REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_job_id(tBadData)); REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_cmd(tBadData)); REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_status(tBadData)); } -#endif /* NO_SERVER */ \ No newline at end of file +#endif /* NO_SERVER */ diff --git a/vpr/test/test_server_zlibutils.cpp b/vpr/test/test_server_zlibutils.cpp index c8978ab999f..4b5ecf76c30 100644 --- a/vpr/test/test_server_zlibutils.cpp +++ b/vpr/test/test_server_zlibutils.cpp @@ -5,8 +5,7 @@ #include "catch2/catch_test_macros.hpp" #include "catch2/matchers/catch_matchers_all.hpp" -TEST_CASE("test_server_zlib_utils", "[vpr]") -{ +TEST_CASE("test_server_zlib_utils", "[vpr]") { const std::string orig{"This string is going to be compressed now"}; std::optional compressedOpt = try_compress(orig); @@ -20,8 +19,3 @@ TEST_CASE("test_server_zlib_utils", "[vpr]") } #endif /* NO_SERVER */ - - - - - diff --git a/vpr/test/test_setup_noc.cpp b/vpr/test/test_setup_noc.cpp index d1c14c211a8..31dacd0b5d8 100644 --- a/vpr/test/test_setup_noc.cpp +++ b/vpr/test/test_setup_noc.cpp @@ -1249,4 +1249,4 @@ TEST_CASE("test_setup_noc", "[vpr_setup_noc]") { } } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_vpr.cpp b/vpr/test/test_vpr.cpp index d96c0389a5d..c05d33e54f9 100644 --- a/vpr/test/test_vpr.cpp +++ b/vpr/test/test_vpr.cpp @@ -132,7 +132,7 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") { vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); vpr_setup.RouterOpts.read_rr_edge_metadata = true; - vpr_create_device(vpr_setup, arch, false); + vpr_create_device(vpr_setup, arch); const auto& device_ctx = g_vpr_ctx.device(); auto& mutable_device_ctx = g_vpr_ctx.mutable_device(); @@ -195,7 +195,7 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") { vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); vpr_setup.RouterOpts.read_rr_edge_metadata = true; - vpr_create_device(vpr_setup, arch, false); + vpr_create_device(vpr_setup, arch); const auto& device_ctx = g_vpr_ctx.device(); @@ -232,4 +232,163 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") { vpr_free_all(arch, vpr_setup); } +TEST_CASE("read_rr_edge_override", "[vpr]") { + + const std::string RR_GRAPH_NAME = "test_read_rr_edge_override"; + const std::string RR_EDGE_OVERRIDE_FILENAME = "test_read_rr_edge_override.txt"; + const std::array file_extensions{".xml", ".bin"}; + + // We test both xml and binary file formats + for (const std::string& file_extension : file_extensions) { + std::string rr_graph_filename = RR_GRAPH_NAME + file_extension; + std::string overridden_rr_graph_filename = RR_GRAPH_NAME + "_overridden" + file_extension; + + RRNodeId src_inode = RRNodeId::INVALID(); + RRNodeId sink_inode = RRNodeId::INVALID(); + short switch_id = -1; + + { // Generate an RR graph and write it out + t_vpr_setup vpr_setup; + t_arch arch; + t_options options; + const char* argv[] = { + "test_vpr", + kArchFile, + "wire.eblif", + "--route_chan_width", + "100"}; + vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); + vpr_create_device(vpr_setup, arch); + + const auto& device_ctx = g_vpr_ctx.device(); + auto& mutable_device_ctx = g_vpr_ctx.mutable_device(); + const auto& rr_graph = device_ctx.rr_graph; + bool echo_enabled = getEchoEnabled() && isEchoFileEnabled(E_ECHO_RR_GRAPH_INDEXED_DATA); + const char* echo_file_name = getEchoFileName(E_ECHO_RR_GRAPH_INDEXED_DATA); + + for (const RRNodeId inode : device_ctx.rr_graph.nodes()) { + if ((rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY) && rr_graph.num_edges(inode) > 0) { + src_inode = inode; + break; + } + } + + REQUIRE(src_inode.is_valid()); + sink_inode = rr_graph.edge_sink_node(RRNodeId(src_inode), 0); + switch_id = rr_graph.edge_switch(RRNodeId(src_inode), 0); + + write_rr_graph(&mutable_device_ctx.rr_graph_builder, + &mutable_device_ctx.rr_graph, + device_ctx.physical_tile_types, + &mutable_device_ctx.rr_indexed_data, + &mutable_device_ctx.rr_rc_data, + device_ctx.grid, + device_ctx.arch_switch_inf, + device_ctx.arch, + &mutable_device_ctx.chan_width, + rr_graph_filename.c_str(), + echo_enabled, + echo_file_name, + false); + + vpr_free_all(arch, vpr_setup); + } + + REQUIRE(src_inode.is_valid()); + REQUIRE(sink_inode.is_valid()); + REQUIRE(switch_id != -1); + + { // Override edge attributes + t_vpr_setup vpr_setup; + t_arch arch; + t_options options; + const char* argv[] = { + "test_vpr", + kArchFile, + "wire.eblif", + "--route_chan_width", + "100", + "--read_rr_graph", + rr_graph_filename.c_str(), + "--read_rr_edge_override", + RR_EDGE_OVERRIDE_FILENAME.c_str()}; + + vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); + vpr_create_device(vpr_setup, arch); + + const auto& device_ctx = g_vpr_ctx.device(); + auto& mutable_device_ctx = g_vpr_ctx.mutable_device(); + bool echo_enabled = getEchoEnabled() && isEchoFileEnabled(E_ECHO_RR_GRAPH_INDEXED_DATA); + const char* echo_file_name = getEchoFileName(E_ECHO_RR_GRAPH_INDEXED_DATA); + + write_rr_graph(&mutable_device_ctx.rr_graph_builder, + &mutable_device_ctx.rr_graph, + device_ctx.physical_tile_types, + &mutable_device_ctx.rr_indexed_data, + &mutable_device_ctx.rr_rc_data, + device_ctx.grid, + device_ctx.arch_switch_inf, + device_ctx.arch, + &mutable_device_ctx.chan_width, + overridden_rr_graph_filename.c_str(), + echo_enabled, + echo_file_name, + false); + + vpr_free_all(arch, vpr_setup); + } + + { // Verify overridden values + t_vpr_setup vpr_setup; + t_arch arch; + t_options options; + const char* argv[] = { + "test_vpr", + kArchFile, + "wire.eblif", + "--route_chan_width", + "100", + "--read_rr_graph", + overridden_rr_graph_filename.c_str()}; + + vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); + vpr_create_device(vpr_setup, arch); + + const auto& device_ctx = g_vpr_ctx.device(); + const auto& rr_graph = device_ctx.rr_graph; + + switch_id = rr_graph.edge_switch((RREdgeId)12); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 5.9e-11f); + + switch_id = rr_graph.edge_switch((RREdgeId)1586); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 4.2e-11f); + + switch_id = rr_graph.edge_switch((RREdgeId)1111); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 7.1e-11f); + + switch_id = rr_graph.edge_switch((RREdgeId)1324); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 9.4e-11f); + + RREdgeId edge_id; + edge_id = rr_graph.rr_nodes().edge_id((RRNodeId)645, (RRNodeId)127); + switch_id = rr_graph.edge_switch(edge_id); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 7.3e-11f); + + edge_id = rr_graph.rr_nodes().edge_id((RRNodeId)591, (RRNodeId)347); + switch_id = rr_graph.edge_switch(edge_id); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 7.9e-11f); + + edge_id = rr_graph.rr_nodes().edge_id((RRNodeId)544, (RRNodeId)45); + switch_id = rr_graph.edge_switch(edge_id); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 8.3e-11f); + + edge_id = rr_graph.rr_nodes().edge_id((RRNodeId)37, (RRNodeId)511); + switch_id = rr_graph.edge_switch(edge_id); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 9.5e-11f); + + vpr_free_all(arch, vpr_setup); + } + } +} + } // namespace diff --git a/vpr/test/test_vpr_constraints.cpp b/vpr/test/test_vpr_constraints.cpp index d0b95e081e6..9069cc2ba2f 100644 --- a/vpr/test/test_vpr_constraints.cpp +++ b/vpr/test/test_vpr_constraints.cpp @@ -14,18 +14,16 @@ * UserPlaceConstraints, Region, PartitionRegions, and Partition. */ -namespace Catch -{ -template -struct StringMaker> -{ - static std::string convert(vtr::Rect const &value) { +namespace Catch { +template +struct StringMaker> { + static std::string convert(vtr::Rect const& value) { std::ostringstream oss; oss << "Rectangle: (" << value.xmin() << ", " << value.ymin() << ") to (" << value.xmax() << ", " << value.ymax() << ")"; return oss.str(); } }; -} +} // namespace Catch //Test Region class accessors and mutators TEST_CASE("Region", "[vpr]") { @@ -42,7 +40,6 @@ TEST_CASE("Region", "[vpr]") { REQUIRE(r1.get_layer_range() == std::make_pair(10, 11)); REQUIRE(r1.get_sub_tile() == 12); - //checking that default constructor creates an empty rectangle (999, 999,-1,-1) Region def_region; bool is_def_empty = def_region.empty(); @@ -73,7 +70,6 @@ TEST_CASE("PartitionRegion", "[vpr]") { REQUIRE(pr_regions[0].get_sub_tile() == 3); REQUIRE(pr_regions[1].get_sub_tile() == 2); - REQUIRE(pr_regions[0].get_rect() == vtr::Rect(2, 3, 6, 7)); REQUIRE(pr_regions[0].get_layer_range() == std::make_pair(0, 0)); @@ -97,7 +93,6 @@ TEST_CASE("Partition", "[vpr]") { r2 = Region(10, 10, 25, 30, 1, 2); r2.set_sub_tile(0); - PartitionRegion part_reg; part_reg.add_to_part_region(r1); part_reg.add_to_part_region(r2); @@ -200,7 +195,6 @@ TEST_CASE("RegionIntersect", "[vpr]") { REQUIRE(int_reg_2_ml.get_rect() == vtr::Rect(6, 3, 8, 6)); REQUIRE(int_reg_2_ml.get_layer_range() == std::make_pair(0, 2)); - //Test no intersection (rectangles don't overlap, intersect region will be returned empty) const Region int_reg_3 = intersection(region1, region3); REQUIRE(int_reg_3.empty() == TRUE); @@ -209,7 +203,6 @@ TEST_CASE("RegionIntersect", "[vpr]") { const Region int_reg_3_ml = intersection(region1, region2_ml); REQUIRE(int_reg_3_ml.empty() == TRUE); - //Test no intersection (rectangles overlap but different subtiles are specified, intersect region will be returned empty) region1.set_sub_tile(5); region2.set_sub_tile(3); @@ -253,7 +246,6 @@ TEST_CASE("PartRegionIntersect", "[vpr]") { pr1.add_to_part_region(r2); pr2.add_to_part_region(r3); - PartitionRegion int_pr = intersection(pr1, pr2); const std::vector& regions = int_pr.get_regions(); @@ -279,7 +271,6 @@ TEST_CASE("PartRegionIntersectMultiLayer", "[vpr]") { pr1.add_to_part_region(r2); pr2.add_to_part_region(r3); - PartitionRegion int_pr = intersection(pr1, pr2); const std::vector& regions = int_pr.get_regions(); @@ -310,7 +301,7 @@ TEST_CASE("PartRegionIntersect2", "[vpr]") { const std::vector& regions = int_pr.get_regions(); REQUIRE(regions.size() == 1); - REQUIRE(regions[0].get_rect() == vtr::Rect (0, 0, 2, 2)); + REQUIRE(regions[0].get_rect() == vtr::Rect(0, 0, 2, 2)); REQUIRE(regions[0].get_layer_range() == std::make_pair(0, 0)); } @@ -334,7 +325,7 @@ TEST_CASE("PartRegionIntersect2Multilayer", "[vpr]") { const std::vector& regions = int_pr.get_regions(); REQUIRE(regions.size() == 1); - REQUIRE(regions[0].get_rect() == vtr::Rect (0, 0, 2, 2)); + REQUIRE(regions[0].get_rect() == vtr::Rect(0, 0, 2, 2)); REQUIRE(regions[0].get_layer_range() == std::make_pair(1, 1)); } @@ -424,13 +415,12 @@ TEST_CASE("PartRegionIntersect4", "[vpr]") { pr2.add_to_part_region(r3); pr2.add_to_part_region(r4); - PartitionRegion int_pr = intersection(pr1, pr2); const std::vector& regions = int_pr.get_regions(); REQUIRE(regions.size() == 1); REQUIRE(regions[0].get_layer_range() == std::make_pair(0, 0)); - REQUIRE(regions[0].get_rect() == vtr::Rect (1, 2, 3, 4)); + REQUIRE(regions[0].get_rect() == vtr::Rect(1, 2, 3, 4)); REQUIRE(regions[0].get_sub_tile() == 2); } @@ -458,13 +448,12 @@ TEST_CASE("PartRegionIntersect4MultiLayer", "[vpr]") { pr2.add_to_part_region(r3); pr2.add_to_part_region(r4); - PartitionRegion int_pr = intersection(pr1, pr2); const std::vector& regions = int_pr.get_regions(); REQUIRE(regions.size() == 1); REQUIRE(regions[0].get_layer_range() == std::make_pair(1, 1)); - REQUIRE(regions[0].get_rect() == vtr::Rect (1, 2, 3, 4)); + REQUIRE(regions[0].get_rect() == vtr::Rect(1, 2, 3, 4)); REQUIRE(regions[0].get_sub_tile() == 2); } diff --git a/vpr/test/test_xy_routing.cpp b/vpr/test/test_xy_routing.cpp index 8b79960c4c8..b96331cc83a 100644 --- a/vpr/test/test_xy_routing.cpp +++ b/vpr/test/test_xy_routing.cpp @@ -389,4 +389,4 @@ TEST_CASE("test_route_flow when it fails in a non mesh topology.", "[vpr_noc_xy_ REQUIRE_THROWS_WITH(routing_algorithm.route_flow(start_router_id, sink_router_id, traffic_flow_id, found_path, noc_model), "No route could be found from starting router with ID:'3' and the destination router with ID:'1' using the XY-Routing algorithm."); } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/valgrind.supp b/vpr/valgrind.supp index fd7781cf70c..3dc4e6058d8 100644 --- a/vpr/valgrind.supp +++ b/vpr/valgrind.supp @@ -766,3 +766,803 @@ ... obj:*libgtk-3* } +#Parmys +{ + + Memcheck:Addr1 + fun:read_history_range + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:realloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:realloc + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:_Znwm + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:realloc + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:realloc + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:realloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:realloc + obj:* + obj:* + obj:* + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateNamespace + fun:TclGetNamespaceForQualName + fun:Tcl_FindNamespace + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateObjCommand + fun:Tcl_NRCreateCommand + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateNamespace + fun:TclGetNamespaceForQualName + fun:Tcl_FindNamespace + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateObjCommand + fun:Tcl_NRCreateCommand + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_DictObjPut + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_DStringSetLength + fun:Tcl_ExternalToUtfDString + fun:TclSetupEnv + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_GetThreadData + fun:TclpGetPwUid + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateNamespace + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_NewStringObj + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_EvalEx + fun:Tcl_Eval + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:TclpRealloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_AppendLimitedToObj + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_EvalEx + fun:Tcl_Eval + fun:_ZN5Yosys20yosys_tcl_iterp_initEP10Tcl_Interp + fun:_ZN5Yosys20yosys_get_tcl_interpEv +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:TclpRealloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_AppendLimitedToObj + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_EvalEx + fun:Tcl_Eval + fun:_ZN5Yosys20yosys_tcl_iterp_initEP10Tcl_Interp + fun:_ZN5Yosys20yosys_get_tcl_interpEv +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_EvalEx + fun:Tcl_Eval + fun:_ZN5Yosys20yosys_tcl_iterp_initEP10Tcl_Interp +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:TclpRealloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_AppendLimitedToObj + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:TclpRealloc + fun:Tcl_Realloc + fun:Tcl_DStringAppend + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclSetByteCodeFromAny + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclNREvalObjEx + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_NewStringObj + fun:TclCreateProc + fun:Tcl_ProcObjCmd + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_EvalEx + fun:Tcl_Eval + fun:_ZN5Yosys20yosys_tcl_iterp_initEP10Tcl_Interp + fun:_ZN5Yosys20yosys_get_tcl_interpEv +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateObjCommand + fun:Tcl_NRCreateCommand + fun:Tcl_ProcObjCmd + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_EvalEx + fun:Tcl_Eval + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclSetByteCodeFromAny + fun:TclProcCompileProc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclNRInterpProc + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:TclpRealloc + fun:Tcl_Realloc + fun:Tcl_DStringSetLength + fun:Tcl_ExternalToUtfDString + fun:TclSetupEnv + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_WriteObj + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_NewObj + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:realloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx +} +{ + + Memcheck:Cond + fun:read_history_range + fun:main +} +{ + + Memcheck:Cond + fun:read_history_range + fun:main +} diff --git a/vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml b/vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml index 8170d72b0e2..3a301bac3dd 100644 --- a/vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml +++ b/vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml @@ -744,6 +744,49 @@ --> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/multi_die/stratixiv_3d/3d_SB_inter_die_stratixiv_arch.timing.xml b/vtr_flow/arch/multi_die/stratixiv_3d/3d_SB_inter_die_stratixiv_arch.timing.xml index d671996b6f4..d2dc23f5005 100644 --- a/vtr_flow/arch/multi_die/stratixiv_3d/3d_SB_inter_die_stratixiv_arch.timing.xml +++ b/vtr_flow/arch/multi_die/stratixiv_3d/3d_SB_inter_die_stratixiv_arch.timing.xml @@ -5026,7 +5026,7 @@ - + + + + - - - + - + 1 1 1 1 1 1 1 1 1 - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/README.md b/vtr_flow/benchmarks/system_verilog/f4pga/README.md index 1887a0a2681..2d3e481d3a4 100644 --- a/vtr_flow/benchmarks/system_verilog/f4pga/README.md +++ b/vtr_flow/benchmarks/system_verilog/f4pga/README.md @@ -4,4 +4,14 @@ This folder contains the `button_controller`, `pulse_width_led` and `timer` benc The benchmarks are directly copied to avoid dealing with a significant amount of code by adding the F4PGA repository as a subtree to the VTR repository. The primary purpose of these benchmarks is to utilize them in VTR GitHub CI tests to continuously monitor the functionality of the Yosys SystemVerilog and UHDM plugins. -For more information please see the ['ChipsAlliance/F4PGA'](https://github.com/chipsalliance/f4pga) Github repository. \ No newline at end of file +For more information please see the ['ChipsAlliance/F4PGA'](https://github.com/chipsalliance/f4pga) Github repository. + +## SystemVerilog File Flattening with `make_sv_flattened.py` + +The current SystemVerilog tool, **Synlig**, cannot process multiple files as input (e.g., a top module and its dependencies). To address this limitation, use the script `make_sv_flattened.py` to flatten the files into a single SystemVerilog file. This will convert any design with dependencies into one flattened SystemVerilog file, ensuring compatibility with Synlig. + +### Instructions: +1. Ensure the `make_sv_flattened.py` script is located in the folder where your SystemVerilog files (e.g., the top module and its dependencies) are gathered. +2. Run the `make_sv_flattened.py` script on the gathered files in that folder. +3. The script will output a single flattened SystemVerilog file, ready for use with Synlig. + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/flattened_button_controller.sv b/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/flattened_button_controller.sv new file mode 100644 index 00000000000..13883b1f424 --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/flattened_button_controller.sv @@ -0,0 +1,241 @@ +// Content from button_controller.sv +`timescale 1ns / 1ps `default_nettype none + +module top ( + input wire logic clk, + btnu, + btnc, + output logic [3:0] anode, + output logic [7:0] segment +); + + + logic sync; + logic syncToDebounce; + logic debounceToOneShot; + logic f1, f2; + logic f3, f4; + logic oneShotToCounter; + logic [7:0] counterToSevenSegment; + logic [7:0] counterToSevenSegment2; + logic oneShotToCounter2; + logic s0, s1; + debounce d0 ( + .clk(clk), + .reset(btnu), + .noisy(syncToDebounce), + .debounced(debounceToOneShot) + ); + + assign oneShotToCounter = f1 && ~f2; + + assign oneShotToCounter2 = f3 && ~f4; + + timer #(.MOD_VALUE(256), .BIT_WIDTH(8)) T0 ( + .clk(clk), + .reset(btnu), + .increment(oneShotToCounter), + .rolling_over(s0), + .count(counterToSevenSegment) + ); + + timer #(.MOD_VALUE(256), .BIT_WIDTH(8)) T1 ( + .clk(clk), + .reset(btnu), + .increment(oneShotToCounter2), + .rolling_over(s1), + .count(counterToSevenSegment2) + ); + + + display_control DC0 ( + .clk(clk), + .reset(btnu), + .dataIn({counterToSevenSegment2, counterToSevenSegment}), + .digitDisplay(4'b1111), + .digitPoint(4'b0000), + .anode(anode), + .segment(segment) + ); + + always_ff @(posedge clk) begin + + sync <= btnc; + syncToDebounce <= sync; + + f1 <= debounceToOneShot; + f2 <= f1; + + f3 <= syncToDebounce; + f4 <= f3; + end +endmodule + + +// Content from debounce.sv +`timescale 1ns / 1ps `default_nettype none + +module debounce ( + input wire logic clk, + reset, + noisy, + output logic debounced +); + + logic timerDone, clrTimer; + + typedef enum logic [1:0] { + s0, + s1, + s2, + s3, + ERR = 'X + } state_type_e; + state_type_e ns, cs; + + logic [18:0] tA; + + timer #(.MOD_VALUE(500000), .BIT_WIDTH(19)) T0 ( + .clk(clk), + .reset(clrTimer), + .increment(1'b1), + .rolling_over(timerDone), + .count(tA) + ); + + always_comb begin + ns = ERR; + clrTimer = 0; + debounced = 0; + + if (reset) ns = s0; + else + case (cs) + s0: begin + clrTimer = 1'b1; + if (noisy) ns = s1; + else ns = s0; + end + s1: + if (noisy && timerDone) ns = s2; + else if (noisy && ~timerDone) ns = s1; + else ns = s0; + s2: begin + debounced = 1'b1; + clrTimer = 1'b1; + if (noisy) ns = s2; + else ns = s3; + end + s3: begin + debounced = 1'b1; + if (~noisy && timerDone) ns = s0; + else if (~noisy && ~timerDone) ns = s3; + else ns = s2; + end + endcase + end + + always_ff @(posedge clk) cs <= ns; +endmodule + + +// Content from display_control.sv +`default_nettype none + +module display_control ( + input wire logic clk, + input wire logic reset, + input wire logic [15:0] dataIn, + input wire logic [ 3:0] digitDisplay, + input wire logic [ 3:0] digitPoint, + output logic [ 3:0] anode, + output logic [ 7:0] segment +); + + parameter integer COUNT_BITS = 17; + + logic [COUNT_BITS-1:0] count_val; + logic [ 1:0] anode_select; + logic [ 3:0] cur_anode; + logic [ 3:0] cur_data_in; + + always_ff @(posedge clk) begin + if (reset) count_val <= 0; + else count_val <= count_val + 1; + end + + assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2]; + + assign cur_anode = + (anode_select == 2'b00) ? 4'b1110 : + (anode_select == 2'b01) ? 4'b1101 : + (anode_select == 2'b10) ? 4'b1011 : + 4'b0111; + + assign anode = cur_anode | (~digitDisplay); + + assign cur_data_in = + (anode_select == 2'b00) ? dataIn[3:0] : + (anode_select == 2'b01) ? dataIn[7:4] : + (anode_select == 2'b10) ? dataIn[11:8] : + dataIn[15:12] ; + + assign segment[7] = + (anode_select == 2'b00) ? ~digitPoint[0] : + (anode_select == 2'b01) ? ~digitPoint[1] : + (anode_select == 2'b10) ? ~digitPoint[2] : + ~digitPoint[3] ; + + assign segment[6:0] = + (cur_data_in == 0) ? 7'b1000000 : + (cur_data_in == 1) ? 7'b1111001 : + (cur_data_in == 2) ? 7'b0100100 : + (cur_data_in == 3) ? 7'b0110000 : + (cur_data_in == 4) ? 7'b0011001 : + (cur_data_in == 5) ? 7'b0010010 : + (cur_data_in == 6) ? 7'b0000010 : + (cur_data_in == 7) ? 7'b1111000 : + (cur_data_in == 8) ? 7'b0000000 : + (cur_data_in == 9) ? 7'b0010000 : + (cur_data_in == 10) ? 7'b0001000 : + (cur_data_in == 11) ? 7'b0000011 : + (cur_data_in == 12) ? 7'b1000110 : + (cur_data_in == 13) ? 7'b0100001 : + (cur_data_in == 14) ? 7'b0000110 : + 7'b0001110; + + +endmodule + + +// Content from timer.sv +`timescale 1ns / 1ps `default_nettype none + +module timer #( + parameter MOD_VALUE = 1, + parameter BIT_WIDTH = 1 +) ( + input wire logic clk, + reset, + increment, + output logic rolling_over, + output logic [BIT_WIDTH-1:0] count = 0 +); + + always_ff @(posedge clk) begin + if (reset) count <= 0; + else if (increment) begin + if (rolling_over) count <= 0; + else count <= count + 1'b1; + end + + end + + always_comb begin + if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1; + else rolling_over = 1'b0; + end + +endmodule + + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/make_sv_flattened.py b/vtr_flow/benchmarks/system_verilog/f4pga/make_sv_flattened.py new file mode 100644 index 00000000000..930d5fb40a6 --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/make_sv_flattened.py @@ -0,0 +1,71 @@ +""" +Module for flattening the SV design files. +""" + +import os +import re + + +def find_verilog_files(): + """Find all Verilog (.sv, .v) files in the current directory.""" + return [f for f in os.listdir(".") if f.endswith((".sv", ".v"))] + + +def identify_top_module(file_list): + """Identify the file containing the top module definition.""" + top_module_regex = re.compile(r"module\s+top\s*\(") + for file in file_list: + with open(file, "r") as f: + for line in f: + if top_module_regex.search(line): + return file + return None + + +def create_flattened_file(top_file, file_list): + """Create a flattened Verilog file with all file contents.""" + current_dir = os.path.basename(os.getcwd()) + output_file_name = f"flattened_{current_dir}.sv" + + with open(output_file_name, "w") as output_file: + if top_file: + # Write the top module first + with open(top_file, "r") as top_module: + output_file.write(f"// Content from {top_file}\n") + output_file.write(top_module.read()) + output_file.write("\n\n") + + # Write the rest of the files + for file in file_list: + if file != top_file: + with open(file, "r") as verilog_file: + output_file.write(f"// Content from {file}\n") + output_file.write(verilog_file.read()) + output_file.write("\n\n") + + print(f"Flattened file created: {output_file_name}") + + +def main(): + """Main function to generate the flattened Verilog file.""" + print("Searching for Verilog files...") + verilog_files = find_verilog_files() + + if not verilog_files: + print("No Verilog files found in the current directory.") + return + + print("Identifying the top module...") + top_file = identify_top_module(verilog_files) + + if top_file: + print(f"Top module found in: {top_file}") + else: + print("No top module found. Files will be combined in arbitrary order.") + + print("Creating flattened file...") + create_flattened_file(top_file, verilog_files) + + +if __name__ == "__main__": + main() diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/flattened_pulse_width_led.sv b/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/flattened_pulse_width_led.sv new file mode 100644 index 00000000000..74e32cc07fe --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/flattened_pulse_width_led.sv @@ -0,0 +1,52 @@ +// Content from pulse_led.v +module top ( + input wire clk, + input wire [3:0] sw, + input wire [3:0] btn, + output wire pulse_red, + pulse_blue, + pulse_green +); + wire [13:0] pulse_wideR, pulse_wideB, pulse_wideG; + + assign pulse_wideR = {1'b0, sw[3:1], 10'd0}; + assign pulse_wideG = {1'b0, sw[0], btn[3:2], 10'd0}; + assign pulse_wideB = {btn[1:0], 11'd0}; + + PWM R0 ( + .clk (clk), + .pulse(pulse_red), + .width(pulse_wideR) + ); + PWM B0 ( + .clk (clk), + .pulse(pulse_green), + .width(pulse_wideB) + ); + PWM G0 ( + .clk (clk), + .pulse(pulse_blue), + .width(pulse_wideG) + ); + + +endmodule + + +// Content from PWM.v +module PWM ( + input wire clk, + input wire [13:0] width, + output reg pulse +); + + reg [13:0] counter = 0; + + always @(posedge clk) begin + counter <= counter + 1; + if (counter < width) pulse <= 1'b1; + else pulse <= 1'b0; + end +endmodule + + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/timer/flattened_timer.sv b/vtr_flow/benchmarks/system_verilog/f4pga/timer/flattened_timer.sv new file mode 100644 index 00000000000..5891e940a15 --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/timer/flattened_timer.sv @@ -0,0 +1,230 @@ +// Content from clock.sv +`timescale 1ns / 1ps `default_nettype none + +module top ( + input wire logic clk, + btnc, + sw, + output logic [3:0] anode, + output logic [7:0] segment +); + + logic [15:0] digitData; + + timer TC0 ( + .clk(clk), + .reset(btnc), + .run(sw), + .digit0(digitData[3:0]), + .digit1(digitData[7:4]), + .digit2(digitData[11:8]), + .digit3(digitData[15:12]) + ); + display_control SSC0 ( + .clk(clk), + .reset(btnc), + .dataIn(digitData), + .digitDisplay(4'b1111), + .digitPoint(4'b0100), + .anode(anode), + .segment(segment) + ); +endmodule + + +// Content from modify_count.sv +`default_nettype none + +module modify_count #( + parameter MOD_VALUE = 10 +) ( + input wire logic clk, + reset, + increment, + output logic rolling_over, + output logic [3:0] count = 0 +); + + always_ff @(posedge clk) begin + if (reset) count <= 4'b0000; + else if (increment) begin + if (rolling_over) count <= 4'b0000; + else count <= count + 4'b0001; + end + end + + always_comb begin + if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1; + else rolling_over = 1'b0; + end + +endmodule + + +// Content from display_control.sv +`default_nettype none + + +module display_control ( + input wire logic clk, + input wire logic reset, + input wire logic [15:0] dataIn, + input wire logic [ 3:0] digitDisplay, + input wire logic [ 3:0] digitPoint, + output logic [ 3:0] anode, + output logic [ 7:0] segment +); + + parameter integer COUNT_BITS = 17; + + logic [COUNT_BITS-1:0] count_val; + logic [ 1:0] anode_select; + logic [ 3:0] cur_anode; + logic [ 3:0] cur_data_in; + + + always_ff @(posedge clk) begin + if (reset) count_val <= 0; + else count_val <= count_val + 1; + end + + assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2]; + + assign cur_anode = + (anode_select == 2'b00) ? 4'b1110 : + (anode_select == 2'b01) ? 4'b1101 : + (anode_select == 2'b10) ? 4'b1011 : + 4'b0111; + + assign anode = cur_anode | (~digitDisplay); + + assign cur_data_in = + (anode_select == 2'b00) ? dataIn[3:0] : + (anode_select == 2'b01) ? dataIn[7:4] : + (anode_select == 2'b10) ? dataIn[11:8] : + dataIn[15:12] ; + + assign segment[7] = + (anode_select == 2'b00) ? ~digitPoint[0] : + (anode_select == 2'b01) ? ~digitPoint[1] : + (anode_select == 2'b10) ? ~digitPoint[2] : + ~digitPoint[3] ; + + assign segment[6:0] = + (cur_data_in == 0) ? 7'b1000000 : + (cur_data_in == 1) ? 7'b1111001 : + (cur_data_in == 2) ? 7'b0100100 : + (cur_data_in == 3) ? 7'b0110000 : + (cur_data_in == 4) ? 7'b0011001 : + (cur_data_in == 5) ? 7'b0010010 : + (cur_data_in == 6) ? 7'b0000010 : + (cur_data_in == 7) ? 7'b1111000 : + (cur_data_in == 8) ? 7'b0000000 : + (cur_data_in == 9) ? 7'b0010000 : + (cur_data_in == 10) ? 7'b0001000 : + (cur_data_in == 11) ? 7'b0000011 : + (cur_data_in == 12) ? 7'b1000110 : + (cur_data_in == 13) ? 7'b0100001 : + (cur_data_in == 14) ? 7'b0000110 : + 7'b0001110; + + +endmodule + + +// Content from timer.sv +`timescale 1ns / 1ps `default_nettype none + +module timer ( + input wire logic clk, + reset, + run, + output logic [3:0] digit0, + digit1, + digit2, + digit3 +); + + logic inc0, inc1, inc2, inc3, inc4; + + logic [23:0] timerCount; + + modify_count #( + .MOD_VALUE(10) + ) M0 ( + .clk(clk), + .reset(reset), + .increment(inc0), + .rolling_over(inc1), + .count(digit0) + ); + modify_count #( + .MOD_VALUE(10) + ) M1 ( + .clk(clk), + .reset(reset), + .increment(inc1), + .rolling_over(inc2), + .count(digit1) + ); + modify_count #( + .MOD_VALUE(10) + ) M2 ( + .clk(clk), + .reset(reset), + .increment(inc2), + .rolling_over(inc3), + .count(digit2) + ); + modify_count #( + .MOD_VALUE(6) + ) M3 ( + .clk(clk), + .reset(reset), + .increment(inc3), + .rolling_over(inc4), + .count(digit3) + ); + + time_counter #( + .MOD_VALUE(1000000) + ) T0 ( + .clk(clk), + .reset(reset), + .increment(run), + .rolling_over(inc0), + .count(timerCount) + ); +endmodule + + +// Content from time_counter.sv +`timescale 1ns / 1ps `default_nettype none + +module time_counter #( + parameter MOD_VALUE = 1000000 +) ( + input wire logic clk, + reset, + increment, + output logic rolling_over, + output logic [23:0] count = 0 +); + + always_ff @(posedge clk) begin + if (reset) count <= 0; + else if (increment) begin + if (rolling_over) count <= 0; + else count <= count + 1'b1; + end + + end + + always_comb begin + if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1; + else rolling_over = 1'b0; + end + +endmodule + + diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl index 5015d587055..24bae6877cc 100644 --- a/vtr_flow/misc/yosys/synthesis.tcl +++ b/vtr_flow/misc/yosys/synthesis.tcl @@ -7,7 +7,15 @@ read_verilog -nomem2reg +/parmys/vtr_primitives.v setattr -mod -set keep_hierarchy 1 single_port_ram setattr -mod -set keep_hierarchy 1 dual_port_ram -puts "Using parmys as partial mapper" +# synlig path error handling +if {[catch {set synlig $::env(synlig_exe_path)} err]} { + puts "Error: $err" + puts "synlig_exe_path is not set" +} else { + set synlig $::env(synlig_exe_path) + puts "Using parmys as partial mapper" +} + # arch file: QQQ # input files: [XXX] @@ -18,15 +26,14 @@ puts "Using parmys as partial mapper" parmys_arch -a QQQ if {$env(PARSER) == "surelog" } { - puts "Using Yosys read_uhdm command" - plugin -i systemverilog - yosys -import - read_uhdm XXX + puts "Using Synlig read_uhdm command" + + exec $synlig -p "read_uhdm XXX" + } elseif {$env(PARSER) == "system-verilog" } { - puts "Using Yosys read_systemverilog command" - plugin -i systemverilog - yosys -import - read_systemverilog XXX + puts "Using Synlig read_systemverilog " + exec $synlig -p "read_systemverilog XXX" + } elseif {$env(PARSER) == "default" } { puts "Using Yosys read_verilog command" read_verilog -sv -nolatches XXX @@ -66,7 +73,14 @@ techmap -map +/parmys/aldffe2dff.v opt -full -parmys -a QQQ -nopass -c CCC YYY +# Separate options for Parmys execution (Verilog or SystemVerilog) +if {$env(PARSER) == "default"} { + # For Verilog, use -nopass for a simpler, faster flow + parmys -a QQQ -nopass -c CCC YYY +} elseif {$env(PARSER) == "system-verilog" || $env(PARSER) == "surelog"} { + # For Synlig SystemVerilog, run additional passes to handle complexity + parmys -a QQQ -c CCC YYY +} opt -full @@ -75,11 +89,10 @@ opt -fast dffunmap opt -fast -noff - #autoname stat hierarchy -check -auto-top -purge_lib -write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ +write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ \ No newline at end of file diff --git a/vtr_flow/parse/parse_config/common/vpr.place.txt b/vtr_flow/parse/parse_config/common/vpr.place.txt index 64da113842b..865a7d2159a 100644 --- a/vtr_flow/parse/parse_config/common/vpr.place.txt +++ b/vtr_flow/parse/parse_config/common/vpr.place.txt @@ -1,4 +1,5 @@ #VPR Place Metrics +initial_placed_wirelength_est;vpr.out;Initial placement BB estimate of wirelength:\s*(\d+) placed_wirelength_est;vpr.out;BB estimate of min-dist \(placement\) wire length: (\d+) #VPR Number of heap operations diff --git a/vtr_flow/parse/parse_config/timing/vpr.place.txt b/vtr_flow/parse/parse_config/timing/vpr.place.txt index ba0dc8a9307..42d3c904cd0 100644 --- a/vtr_flow/parse/parse_config/timing/vpr.place.txt +++ b/vtr_flow/parse/parse_config/timing/vpr.place.txt @@ -1,6 +1,7 @@ %include "../common/vpr.place.txt" #VPR Place Timing Metrics +initial_placed_CPD_est;vpr.out;Initial placement estimated Critical Path Delay \(CPD\): (.*) ns placed_CPD_est;vpr.out;Placement estimated critical path delay \(least slack\): (.*) ns placed_setup_TNS_est;vpr.out;Placement estimated setup Total Negative Slack \(sTNS\): (.*) ns placed_setup_WNS_est;vpr.out;Placement estimated setup Worst Negative Slack \(sWNS\): (.*) ns diff --git a/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt b/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt index a78ab6d191c..db69ba91d66 100644 --- a/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt +++ b/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt @@ -2,14 +2,25 @@ # channel width. vpr_status;output.txt;vpr_status=(.*) -total_wirelength;vpr.out;\s*Total wirelength: (\d+) -# Final critical path delay (least slack): 6.34202 ns, Fmax: 157.678 MHz crit_path_delay;vpr.out;Critical path: (.*) ns +post_gp_hpwl;vpr.out;\s*Placement HPWL: (.*) +post_fl_hpwl;vpr.out;Initial placement BB estimate of wirelength: (.*) +post_dp_hpwl;vpr.out;BB estimate of min-dist \(placement\) wire length: (.*) +total_wirelength;vpr.out;\s*Total wirelength: (\d+) +post_gp_overfilled_bins;vpr.out;\s*Number of overfilled bins: (\d+) +post_gp_avg_overfill;vpr.out;\s*Average overfill magnitude: (.*) +post_gp_num_misplaced_blocks;vpr.out;\s*Number of blocks in an incompatible bin: (\d+) +post_fl_cluster_err;vpr.out;\s*Percent of clusters with reconstruction errors: (.*) +post_fl_atom_err;vpr.out;\s*Percent of atoms misplaced from the flat placement: (.*) +post_fl_total_disp;vpr.out;\s*Total displacement of initial placement from flat placement: (.*) +post_fl_avg_disp;vpr.out;\s*Average atom displacement of initial placement from flat placement: (.*) +post_fl_max_disp;vpr.out;\s*Max atom displacement of initial placement from flat placement: (.*) ap_runtime;vpr.out;Analytical Placement took (.*) seconds -pack_runtime;vpr.out;Packing took (.*) seconds -# TODO: Figure out how to match Placement and not Analytical Placement better. -place_runtime;vpr.out;^(?!.*\bAnalytical\b).*Placement took (.*) seconds +ap_gp_runtime;vpr.out;AP Global Placer took (.*) seconds +ap_fl_runtime;vpr.out;AP Full Legalizer took (.*) seconds +ap_dp_runtime;vpr.out;AP Detailed Placer took (.*) seconds route_runtime;vpr.out;Routing took (.*) seconds total_runtime;vpr.out;The entire flow of VPR took (.*) seconds num_clb;vpr.out;Netlist clb blocks:\s*(\d+) +num_lab;vpr.out;Netlist LAB blocks:\s*(\d+) diff --git a/vtr_flow/scripts/arch_gen/arch_gen.py b/vtr_flow/scripts/arch_gen/arch_gen.py index 2039bf26e06..ef68cde7af5 100755 --- a/vtr_flow/scripts/arch_gen/arch_gen.py +++ b/vtr_flow/scripts/arch_gen/arch_gen.py @@ -172,7 +172,7 @@ def xLUT(LUT_size, num_LUT): def xCLB(k_LUT, N_BLE, I_CLB, I_BLE, fracture_level, num_FF, crossbar_str): - O_LUT = 2 ** fracture_level + O_LUT = 2**fracture_level O_soft = O_LUT O_ble = O_soft O_CLB = N_BLE * O_ble @@ -430,7 +430,7 @@ def xCLB(k_LUT, N_BLE, I_CLB, I_BLE, fracture_level, num_FF, crossbar_str): else: special_stage = False - num_LUT = 2 ** frac_stage + num_LUT = 2**frac_stage LUT_size = k_LUT - frac_stage idx = "[" + str(LUT_size - 1) + ":0]" diff --git a/vtr_flow/scripts/benchtracker/flask_cors/six.py b/vtr_flow/scripts/benchtracker/flask_cors/six.py index c06164c97d0..80c9e7e618d 100644 --- a/vtr_flow/scripts/benchtracker/flask_cors/six.py +++ b/vtr_flow/scripts/benchtracker/flask_cors/six.py @@ -687,7 +687,6 @@ def reraise(tp, value, tb=None): raise value.with_traceback(tb) raise value - else: def exec_(_code_, _globs_=None, _locs_=None): @@ -809,13 +808,13 @@ def wrapper(f): return wrapper - else: wraps = functools.wraps def with_metaclass(meta, *bases): """Create a base class with a metaclass.""" + # This requires a bit of explanation: the basic idea is to make a dummy # metaclass for one level of class instantiation that replaces itself with # the actual metaclass. diff --git a/vtr_flow/scripts/benchtracker/populate_db.py b/vtr_flow/scripts/benchtracker/populate_db.py index 39c898bde1e..358ef190fd7 100755 --- a/vtr_flow/scripts/benchtracker/populate_db.py +++ b/vtr_flow/scripts/benchtracker/populate_db.py @@ -25,6 +25,7 @@ nullval = "-1" type_map = {int: "INT", float: "REAL", str: "TEXT"} + # main program sequence def main(): params = Params() @@ -59,6 +60,7 @@ def update_db(params, db): # check if table for task exists; if not then create it task_table_name = params.task_table_name create_table(params, db, task_table_name) + # load up latest run and parsed date for task def check_last_runs_table(runs): natural_sort(runs) diff --git a/vtr_flow/scripts/blif_splicer.py b/vtr_flow/scripts/blif_splicer.py index dcfb71fc7d1..08058163f65 100755 --- a/vtr_flow/scripts/blif_splicer.py +++ b/vtr_flow/scripts/blif_splicer.py @@ -88,9 +88,11 @@ # and is not 're') with the name of the circuit. sections[sectionNumber] += " ".join( - name + "_" + word - if word != "re" and any(char not in nonNetChars for char in word) - else word + ( + name + "_" + word + if word != "re" and any(char not in nonNetChars for char in word) + else word + ) for word in line.split(" ") ) diff --git a/vtr_flow/scripts/download_noc_mlp.py b/vtr_flow/scripts/download_noc_mlp.py index c483da753df..c541c91c021 100755 --- a/vtr_flow/scripts/download_noc_mlp.py +++ b/vtr_flow/scripts/download_noc_mlp.py @@ -17,6 +17,7 @@ import shutil import errno + class ExtractionError(Exception): """ Raised when extracting the downlaoded file fails @@ -39,8 +40,9 @@ def parse_args(): does nothing (unless --force is specified). """ ) - parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter, - description=description) + parser = argparse.ArgumentParser( + formatter_class=argparse.ArgumentDefaultsHelpFormatter, description=description + ) parser.add_argument( "--vtr_flow_dir", @@ -132,7 +134,7 @@ def extract_to_vtr_flow_dir(args, tar_gz_filename): raise ExtractionError("{} should be a directory".format(directory)) # Create a temporary working directory - tmpdir = tempfile.mkdtemp(suffix="download_NoC_MLP", dir= os.path.abspath(".")) + tmpdir = tempfile.mkdtemp(suffix="download_NoC_MLP", dir=os.path.abspath(".")) try: # Extract the contents of the .tar.gz archive directly into the destination directory with tarfile.open(tar_gz_filename, "r:gz") as tar: diff --git a/vtr_flow/scripts/download_titan.py b/vtr_flow/scripts/download_titan.py index cf025dc38ab..483ba5c04d0 100755 --- a/vtr_flow/scripts/download_titan.py +++ b/vtr_flow/scripts/download_titan.py @@ -41,8 +41,9 @@ def parse_args(): does nothing (unless --force is specified). """ ) - parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter, - description=description) + parser = argparse.ArgumentParser( + formatter_class=argparse.ArgumentDefaultsHelpFormatter, description=description + ) parser.add_argument( "--titan_version", default="2.0.0", help="Titan release version to download" diff --git a/vtr_flow/scripts/python_libs/vtr/__init__.py b/vtr_flow/scripts/python_libs/vtr/__init__.py index 6a0b38d7639..9237e03be89 100644 --- a/vtr_flow/scripts/python_libs/vtr/__init__.py +++ b/vtr_flow/scripts/python_libs/vtr/__init__.py @@ -1,6 +1,7 @@ """ __init__ for the VTR python module """ + from .util import ( load_config_lines, CommandRunner, @@ -14,12 +15,12 @@ argparse_use_previous, argparse_str2bool, get_existing_run_dir, - get_latest_run_dir, - get_latest_run_number, + get_active_run_dir, get_next_run_dir, verify_file, pretty_print_table, find_task_dir, + RunDir, ) from .log_parse import ( determine_lut_size, diff --git a/vtr_flow/scripts/python_libs/vtr/abc/__init__.py b/vtr_flow/scripts/python_libs/vtr/abc/__init__.py index 26d376b3420..cdb3a62e69d 100644 --- a/vtr_flow/scripts/python_libs/vtr/abc/__init__.py +++ b/vtr_flow/scripts/python_libs/vtr/abc/__init__.py @@ -1,4 +1,5 @@ """ __init__ for abc module """ + from .abc import run, run_lec diff --git a/vtr_flow/scripts/python_libs/vtr/abc/abc.py b/vtr_flow/scripts/python_libs/vtr/abc/abc.py index 0ec3ca5ccef..a49de129d69 100644 --- a/vtr_flow/scripts/python_libs/vtr/abc/abc.py +++ b/vtr_flow/scripts/python_libs/vtr/abc/abc.py @@ -1,6 +1,7 @@ """ Module to run ABC with its various options """ + import shutil from collections import OrderedDict from pathlib import Path @@ -8,6 +9,7 @@ from vtr import paths from vtr.error import InspectError + # pylint: disable=too-many-arguments, too-many-locals def run( architecture_file, @@ -186,24 +188,26 @@ def run( ] ) if abc_script is None - else "; ".join( - [ - "read {pre_abc_blif}".format(pre_abc_blif=pre_abc_blif.name), - "time", - "resyn", - "resyn2", - "if -K {lut_size}".format(lut_size=lut_size), - "time", - "scleanup", - "write_hie {pre_abc_blif} {post_abc_raw_blif}".format( - pre_abc_blif=pre_abc_blif.name, - post_abc_raw_blif=post_abc_raw_blif.name, - ), - "print_stats", - ] + else ( + "; ".join( + [ + "read {pre_abc_blif}".format(pre_abc_blif=pre_abc_blif.name), + "time", + "resyn", + "resyn2", + "if -K {lut_size}".format(lut_size=lut_size), + "time", + "scleanup", + "write_hie {pre_abc_blif} {post_abc_raw_blif}".format( + pre_abc_blif=pre_abc_blif.name, + post_abc_raw_blif=post_abc_raw_blif.name, + ), + "print_stats", + ] + ) + if use_old_abc_script + else abc_script ) - if use_old_abc_script - else abc_script ) cmd = [abc_exec, "-c", abc_script] diff --git a/vtr_flow/scripts/python_libs/vtr/ace/__init__.py b/vtr_flow/scripts/python_libs/vtr/ace/__init__.py index 9666f7710ac..50682d93b35 100644 --- a/vtr_flow/scripts/python_libs/vtr/ace/__init__.py +++ b/vtr_flow/scripts/python_libs/vtr/ace/__init__.py @@ -1,4 +1,5 @@ """ init for the ACE module """ + from .ace import run diff --git a/vtr_flow/scripts/python_libs/vtr/ace/ace.py b/vtr_flow/scripts/python_libs/vtr/ace/ace.py index 7c5a274dc7e..a2e6af00fd5 100644 --- a/vtr_flow/scripts/python_libs/vtr/ace/ace.py +++ b/vtr_flow/scripts/python_libs/vtr/ace/ace.py @@ -1,9 +1,11 @@ """ Module to run ACE with its various options """ + from pathlib import Path from vtr import verify_file, CommandRunner, paths + # pylint: disable=too-many-arguments def run( circuit_file, diff --git a/vtr_flow/scripts/python_libs/vtr/flow.py b/vtr_flow/scripts/python_libs/vtr/flow.py index a1f14e2816e..fa0798fcd25 100644 --- a/vtr_flow/scripts/python_libs/vtr/flow.py +++ b/vtr_flow/scripts/python_libs/vtr/flow.py @@ -1,6 +1,7 @@ """ Module to run the VTR flow. This module calls other modules that then access the tools like VPR. """ + import shutil from pathlib import Path from collections import OrderedDict @@ -258,9 +259,9 @@ def run( if should_run_stage(VtrStage.ACE, start_stage, end_stage): vtr.ace.run( next_stage_netlist, - old_netlist=post_odin_netlist - if start_stage == VtrStage.ODIN - else post_yosys_netlist, + old_netlist=( + post_odin_netlist if start_stage == VtrStage.ODIN else post_yosys_netlist + ), output_netlist=post_ace_netlist, output_activity_file=post_ace_activity_file, command_runner=command_runner, @@ -297,8 +298,6 @@ def run( if ( "write_rr_graph" in vpr_args - or "analysis" in vpr_args - or "route" in vpr_args or "write_router_lookahead" in vpr_args or "write_intra_cluster_router_lookahead" in vpr_args ): @@ -399,8 +398,9 @@ def delete_intermediate_files( delete intermediate files """ next_stage_netlist.unlink() - exts = (".xml", ".sdf", ".v") - exts += (".net", ".place", ".route") if not keep_result_files else None + exts = (".xml", ".sdf", ".v", ".sv") + if not keep_result_files: + exts += (".net", ".place", ".route") for file in temp_dir.iterdir(): if file.suffix in exts: diff --git a/vtr_flow/scripts/python_libs/vtr/log_parse.py b/vtr_flow/scripts/python_libs/vtr/log_parse.py index 623c4545e22..69e8d72e7d7 100644 --- a/vtr_flow/scripts/python_libs/vtr/log_parse.py +++ b/vtr_flow/scripts/python_libs/vtr/log_parse.py @@ -1,6 +1,7 @@ """ module that contains functions to inspect various files to determine important values """ + import re from collections import OrderedDict from pathlib import Path @@ -25,7 +26,7 @@ def __init__(self, name, filename, regex_str, default_value=None): self._filename = filename # Look for the specified pattern somewhere in the line, but any characters # can occur before and after it. Detailed in GitHub Issue #2743. - self._regex = re.compile(f'^.*{regex_str}.*$') + self._regex = re.compile(f"^.*{regex_str}.*$") self._default_value = default_value def name(self): diff --git a/vtr_flow/scripts/python_libs/vtr/odin/__init__.py b/vtr_flow/scripts/python_libs/vtr/odin/__init__.py index b55d5c160cd..f1006248346 100644 --- a/vtr_flow/scripts/python_libs/vtr/odin/__init__.py +++ b/vtr_flow/scripts/python_libs/vtr/odin/__init__.py @@ -1,4 +1,5 @@ """ init for the ODIN module """ + from .odin import run diff --git a/vtr_flow/scripts/python_libs/vtr/odin/odin.py b/vtr_flow/scripts/python_libs/vtr/odin/odin.py index c4346d115b8..846b743b814 100644 --- a/vtr_flow/scripts/python_libs/vtr/odin/odin.py +++ b/vtr_flow/scripts/python_libs/vtr/odin/odin.py @@ -1,6 +1,7 @@ """ Module to run ODIN II with its various arguments """ + import os import shutil from collections import OrderedDict diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/__init__.py b/vtr_flow/scripts/python_libs/vtr/parmys/__init__.py index 581b8681c71..a8a520b91ed 100644 --- a/vtr_flow/scripts/python_libs/vtr/parmys/__init__.py +++ b/vtr_flow/scripts/python_libs/vtr/parmys/__init__.py @@ -1,5 +1,6 @@ """ init for the YOSYS module """ + from .parmys import run from .parmys import YOSYS_PARSERS diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py index cef45626828..c067ee7e7cf 100644 --- a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py +++ b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py @@ -1,6 +1,7 @@ """ Module to run Parmys with its various arguments """ + import os import shutil from collections import OrderedDict @@ -232,6 +233,13 @@ def run( odin_config_full_path, ) + # Set the synlig exe script path in the environment variable + # (handle if it is not set or system-verilog OFF) + try: + os.environ["synlig_exe_path"] = str(vtr.paths.synlig_exe_path) + except KeyError: + os.environ["synlig_exe_path"] = "/dummy/path" + # set the parser if parmys_args["parser"] in YOSYS_PARSERS: os.environ["PARSER"] = parmys_args["parser"] diff --git a/vtr_flow/scripts/python_libs/vtr/parse_vtr_flow.py b/vtr_flow/scripts/python_libs/vtr/parse_vtr_flow.py index d500eca0643..e238f2d9bb8 100755 --- a/vtr_flow/scripts/python_libs/vtr/parse_vtr_flow.py +++ b/vtr_flow/scripts/python_libs/vtr/parse_vtr_flow.py @@ -16,7 +16,6 @@ def parse_file_and_update_results(filename, patterns, results): - """ Find filename, and then look through for the matching patterns, updating results """ diff --git a/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py b/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py index d2aac387bcc..0eff7bbb75c 100755 --- a/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py +++ b/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py @@ -7,6 +7,7 @@ from pathlib import Path from pathlib import PurePath import sys +import os import argparse import textwrap import shutil @@ -18,13 +19,12 @@ from vtr import ( load_list_file, RawDefaultHelpFormatter, - get_latest_run_dir, + get_active_run_dir, load_task_config, find_task_config_file, load_pass_requirements, load_parse_results, parse_vtr_flow, - get_latest_run_number, pretty_print_table, find_task_dir, CommandError, @@ -32,6 +32,7 @@ VtrError, create_jobs, paths, + RunDir, ) # pylint: enable=wrong-import-position @@ -130,7 +131,12 @@ def vtr_command_argparser(prog=None): help="QoR geomeans are not computed by default", ) - parser.add_argument("-run", default=None, type=str, help="") + parser.add_argument( + "-run", + default=None, + type=str, + help="Parse the specified run directory. Defaults to the latest.", + ) parser.add_argument("-revision", default="", help="Revision number") @@ -144,6 +150,8 @@ def vtr_command_main(arg_list, prog=None): """ # Load the arguments args = vtr_command_argparser(prog).parse_args(arg_list) + if args.run is not None: + RunDir.set_user_run_dir_name(args.run) try: task_names = args.task @@ -208,7 +216,7 @@ def parse_task(config, config_jobs, flow_metrics_basename=FIRST_PARSE_FILE, alt_ max_arch_len = len("architecture") max_circuit_len = len("circuit") for job in config_jobs: - work_dir = job.work_dir(get_latest_run_dir(find_task_dir(config, alt_tasks_dir))) + work_dir = job.work_dir(get_active_run_dir(find_task_dir(config, alt_tasks_dir))) job.parse_command()[0] = work_dir # job.second_parse_command()[0] = work_dir job.qor_parse_command()[0] = work_dir @@ -433,7 +441,7 @@ def check_two_files( ) num_qor_failures = 0 # Verify that the first results pass each metric for all cases in the second results - for (arch, circuit, script_params) in second_primary_keys: + for arch, circuit, script_params in second_primary_keys: second_metrics = second_results.metrics(arch, circuit, script_params) first_metrics = first_results.metrics(arch, circuit, script_params) first_fail = True @@ -525,7 +533,7 @@ def calc_geomean(args, configs): first = False lines = summary.readlines() print( - get_latest_run_number(find_task_dir(configs[0], args.alt_tasks_dir)), + os.path.basename(get_active_run_dir(find_task_dir(configs[0], args.alt_tasks_dir))), file=out, end="\t", ) @@ -571,7 +579,7 @@ def find_latest_run_dir(config, alt_tasks_dir=None): """Find the latest run directory for given configuration""" task_dir = find_task_dir(config, alt_tasks_dir) - run_dir = get_latest_run_dir(task_dir) + run_dir = get_active_run_dir(task_dir) if not run_dir: raise InspectError( diff --git a/vtr_flow/scripts/python_libs/vtr/paths.py b/vtr_flow/scripts/python_libs/vtr/paths.py index 2df9317c81c..2ab1e4c31b5 100644 --- a/vtr_flow/scripts/python_libs/vtr/paths.py +++ b/vtr_flow/scripts/python_libs/vtr/paths.py @@ -22,6 +22,10 @@ yosys_tcl_path = vtr_flow_path / "misc" / "yosys" yosys_script_path = yosys_tcl_path / "synthesis.tcl" +# Synlig paths +synlig_path = root_path / "build" / "bin" / "synlig_install" +synlig_exe_path = synlig_path / "usr" / "local" / "bin" / "synlig" + # PARMYS paths parmys_path = root_path / "parmys" parmys_verify_path = parmys_path / "verify_parmys.sh" diff --git a/vtr_flow/scripts/python_libs/vtr/task.py b/vtr_flow/scripts/python_libs/vtr/task.py index 5af290578f7..3d063d05202 100644 --- a/vtr_flow/scripts/python_libs/vtr/task.py +++ b/vtr_flow/scripts/python_libs/vtr/task.py @@ -1,6 +1,7 @@ """ Module that contains the task functions """ + import itertools from pathlib import Path @@ -15,13 +16,14 @@ load_list_file, load_parse_results, get_existing_run_dir, - get_latest_run_dir, get_next_run_dir, + get_active_run_dir, find_task_dir, load_script_param, paths, ) + # pylint: disable=too-many-instance-attributes, too-many-arguments, too-many-locals, too-few-public-methods class TaskConfig: """ @@ -55,7 +57,7 @@ def __init__( pad_file=None, additional_files=None, additional_files_list_add=None, - circuit_constraint_list_add=None + circuit_constraint_list_add=None, ): self.task_name = task_name self.config_dir = config_dir @@ -82,9 +84,9 @@ def __init__( self.pad_file = pad_file self.additional_files = additional_files self.additional_files_list_add = additional_files_list_add - self.circuit_constraints = parse_circuit_constraint_list(circuit_constraint_list_add, - self.circuits, - self.archs) + self.circuit_constraints = parse_circuit_constraint_list( + circuit_constraint_list_add, self.circuits, self.archs + ) # pylint: enable=too-few-public-methods @@ -306,9 +308,8 @@ def check_include_fields(config_file, key_values): ) ) -def parse_circuit_constraint_list( - circuit_constraint_list, circuits_list, arch_list -) -> dict: + +def parse_circuit_constraint_list(circuit_constraint_list, circuits_list, arch_list) -> dict: """ Parse the circuit constraints passed in via the config file. Circuit constraints are expected to have the following syntax: @@ -343,38 +344,39 @@ def parse_circuit_constraint_list( # Parse the circuit constraint list for circuit_constraint in circuit_constraint_list: # Remove the round brackets. - if circuit_constraint[0] != '(' or circuit_constraint[-1] != ')': - raise VtrError(f"Circuit constraint syntax error: \"{circuit_constraint}\"") + if circuit_constraint[0] != "(" or circuit_constraint[-1] != ")": + raise VtrError(f'Circuit constraint syntax error: "{circuit_constraint}"') circuit_constraint = circuit_constraint[1:-1] # Split the circuit and the constraint - split_constraint_line = circuit_constraint.split(',') + split_constraint_line = circuit_constraint.split(",") if len(split_constraint_line) != 2: - raise VtrError(f"Circuit constraint has too many arguments: \"{circuit_constraint}\"") + raise VtrError(f'Circuit constraint has too many arguments: "{circuit_constraint}"') circuit = split_constraint_line[0].strip() constraint = split_constraint_line[1].strip() # Check that the circuit actually exists. if circuit not in circuits_list: - raise VtrError(f"Cannot constrain circuit \"{circuit}\", circuit has not been added") + raise VtrError(f'Cannot constrain circuit "{circuit}", circuit has not been added') # Parse the constraint split_constraint = constraint.split("=") if len(split_constraint) != 2: - raise VtrError(f"Circuit constraint syntax error: \"{circuit_constraint}\"") + raise VtrError(f'Circuit constraint syntax error: "{circuit_constraint}"') constr_key = split_constraint[0].strip() constr_val = split_constraint[1].strip() # Check that the constr_key is valid. if constr_key not in circuit_constraint_keys: - raise VtrError(f"Invalid constraint \"{constr_key}\" used on circuit \"{circuit}\"") + raise VtrError(f'Invalid constraint "{constr_key}" used on circuit "{circuit}"') # In the case of arch constraints, make sure this arch exists. if constr_key == "arch" and constr_val not in arch_list: - raise VtrError(f"Cannot constrain arch \"{constr_key}\", arch has not been added") + raise VtrError(f'Cannot constrain arch "{constr_key}", arch has not been added') # Make sure this circuit is not already constrained with this constr_arg if res_circuit_constraints[circuit][constr_key] is not None: - raise VtrError(f"Circuit \"{circuit}\" cannot be constrained more than once") + raise VtrError(f'Circuit "{circuit}" cannot be constrained more than once') # Add the constraint for this circuit res_circuit_constraints[circuit][constr_key] = constr_val return res_circuit_constraints + def shorten_task_names(configs, common_task_prefix): """ Shorten the task names of the configs by remove the common task prefix. @@ -407,7 +409,7 @@ def find_longest_task_description(configs): def get_work_dir_addr(arch, circuit, noc_traffic): - """ Get the work directory address under under run_dir """ + """Get the work directory address under under run_dir""" work_dir = None if noc_traffic: work_dir = str(PurePath(arch).joinpath(circuit).joinpath(noc_traffic)) @@ -418,7 +420,7 @@ def get_work_dir_addr(arch, circuit, noc_traffic): def create_second_parse_cmd(config): - """ Create the parse command to run the second time """ + """Create the parse command to run the second time""" second_parse_cmd = None if config.second_parse_file: second_parse_cmd = [ @@ -436,7 +438,7 @@ def create_second_parse_cmd(config): def create_cmd( abs_circuit_filepath, abs_arch_filepath, config, args, circuit, noc_traffic ) -> Tuple: - """ Create the command to run the task """ + """Create the command to run the task""" # Collect any extra script params from the config file cmd = [abs_circuit_filepath, abs_arch_filepath] @@ -583,10 +585,7 @@ def create_jobs(args, configs, after_run=False) -> List[Job]: work_dir = get_work_dir_addr(arch, circuit, noc_traffic) run_dir = ( - str( - Path(get_latest_run_dir(find_task_dir(config, args.alt_tasks_dir))) - / work_dir - ) + str(Path(get_active_run_dir(find_task_dir(config, args.alt_tasks_dir))) / work_dir) if after_run else str( Path(get_next_run_dir(find_task_dir(config, args.alt_tasks_dir))) / work_dir @@ -780,6 +779,7 @@ def ret_expected_vpr_status(arch, circuit, golden_results, script_params=None): return golden_metrics["vpr_status"] + def apply_cmd_line_circuit_constraints(cmd, circuit, config): """ Apply the circuit constraints to the command line. If the circuit is not @@ -798,6 +798,7 @@ def apply_cmd_line_circuit_constraints(cmd, circuit, config): if constrained_route_w is not None: cmd += ["--route_chan_width", constrained_route_w] + def resolve_vtr_source_file(config, filename, base_dir=""): """ Resolves an filename with a base_dir diff --git a/vtr_flow/scripts/python_libs/vtr/util.py b/vtr_flow/scripts/python_libs/vtr/util.py index 61b52ee991b..a80521f07e8 100644 --- a/vtr_flow/scripts/python_libs/vtr/util.py +++ b/vtr_flow/scripts/python_libs/vtr/util.py @@ -22,6 +22,31 @@ from vtr import paths +class RunDir: + """ + A class for representing a run directory. + """ + + # The run directory name passed by set_global_run_dir + # is the run directory name to parse. + # If it is None, the latest run directory will be parsed. + g_run_dir_name = None + + @classmethod + def set_user_run_dir_name(cls, current_run_dir_name): + """ + Set the run directory name passed by the user. + """ + cls.g_run_dir_name = current_run_dir_name + + @classmethod + def get_user_run_dir_name(cls): + """ + Get the run directory name passed by the user. + """ + return cls.g_run_dir_name + + class RawDefaultHelpFormatter( argparse.ArgumentDefaultsHelpFormatter, argparse.RawDescriptionHelpFormatter ): @@ -154,7 +179,7 @@ def run_system_command( # or RR graph files to VPR. PWD environment variable is updated # manually to prevent capnproto from throwing exceptions. modified_environ = os.environ.copy() - modified_environ['PWD'] = str(temp_dir) + modified_environ["PWD"] = str(temp_dir) proc = subprocess.Popen( cmd, @@ -162,7 +187,7 @@ def run_system_command( stderr=stderr, # stderr redirected to stderr universal_newlines=True, # Lines always end in \n cwd=str(temp_dir), # Where to run the command - env=modified_environ + env=modified_environ, ) # Read the output line-by-line and log it @@ -521,16 +546,18 @@ def find_task_dir(config, alt_tasks_dir=None): return str(task_dir) -def get_latest_run_dir(base_dir): +def get_active_run_dir(base_dir): """ - Returns the run directory with the highest run number in base_dir + Returns full path to the active run directory + locatedin base_dir """ - latest_run_number = get_latest_run_number(base_dir) + active_run_dir_name = get_active_run_dir_name(base_dir) - if latest_run_number is None: - return None + run_dir = None + if active_run_dir_name: + run_dir = str(PurePath(base_dir) / active_run_dir_name) - return str(PurePath(base_dir) / run_dir_name(latest_run_number)) + return run_dir def get_existing_run_dir(base_dir: str, run_dir: str) -> str: @@ -549,34 +576,40 @@ def get_next_run_number(base_dir): """ Returns the next available (i.e. non-existing) run number in base_dir """ - latest_run_number = get_latest_run_number(base_dir) - - if latest_run_number is None: - next_run_number = 1 - else: + latest_run_dir_name = get_active_run_dir_name(base_dir) + match = re.match(r"^run(\d{3})$", latest_run_dir_name) + next_run_number = 1 + if match: + latest_run_number = int(match.group(1)) next_run_number = latest_run_number + 1 return next_run_number -def get_latest_run_number(base_dir): +def get_active_run_dir_name(base_dir): """ - Returns the highest run number of all run directories with in base_dir + Returns the active run directory name. If the user has specified + a run directory name, it will be returned. Otherwise, the + highest run number of all run directories within in base_dir + will be returned. """ - run_number = 1 - run_dir = Path(base_dir) / run_dir_name(run_number) + active_run_dir_name = "" + if RunDir.get_user_run_dir_name() is not None: + active_run_dir_name = RunDir.get_user_run_dir_name() + else: + run_number = 1 + run_dir = Path(base_dir) / run_dir_name(run_number) - if not run_dir.exists(): - # No existing run directories - return None + if run_dir.exists(): + while run_dir.exists(): + run_number += 1 + run_dir = Path(base_dir) / run_dir_name(run_number) - while run_dir.exists(): - run_number += 1 - run_dir = Path(base_dir) / run_dir_name(run_number) + # Currently one-past the last existing run dir, + # to get latest existing, subtract one + active_run_dir_name = run_dir_name(run_number - 1) - # Currently one-past the last existing run dir, - # to get latest existing, subtract one - return run_number - 1 + return active_run_dir_name def run_dir_name(run_num): diff --git a/vtr_flow/scripts/python_libs/vtr/vpr/__init__.py b/vtr_flow/scripts/python_libs/vtr/vpr/__init__.py index 895950332ef..823908b93e2 100644 --- a/vtr_flow/scripts/python_libs/vtr/vpr/__init__.py +++ b/vtr_flow/scripts/python_libs/vtr/vpr/__init__.py @@ -1,4 +1,5 @@ """ __init__ for the VPR Module """ + from .vpr import run, run_relax_w, cmp_full_vs_incr_sta, run_second_time diff --git a/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py b/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py index 003adb9f8cb..50278757656 100644 --- a/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py +++ b/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py @@ -1,12 +1,14 @@ """ Module to interact with VPR and its various options """ + from collections import OrderedDict from pathlib import Path from os import environ from vtr import CommandRunner, relax_w, determine_min_w, verify_file, paths from vtr.error import InspectError + # pylint: disable=too-many-arguments,too-many-locals def run_relax_w( architecture, @@ -296,9 +298,9 @@ def run_second_time( if "write_intra_cluster_router_lookahead" in second_run_args: intra_cluster_router_lookahead = second_run_args["write_intra_cluster_router_lookahead"] second_run_args["read_intra_cluster_router_lookahead"] = intra_cluster_router_lookahead - second_run_args[ - "write_intra_cluster_router_lookahead" - ] = "intra_cluster_router_lookahead2.capnp" + second_run_args["write_intra_cluster_router_lookahead"] = ( + "intra_cluster_router_lookahead2.capnp" + ) # run VPR run( diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py index 3d584274e3f..70ff3f2ac9b 100755 --- a/vtr_flow/scripts/run_vtr_flow.py +++ b/vtr_flow/scripts/run_vtr_flow.py @@ -22,6 +22,7 @@ VTR_STAGES = ["odin", "parmys", "abc", "ace", "vpr"] + # pylint: disable=too-few-public-methods class VtrStageArgparseAction(argparse.Action): """ @@ -45,6 +46,7 @@ def __call__(self, parser, namespace, value, option_string=None): # pylint: enable=too-few-public-methods + # pylint: disable=too-many-statements def vtr_command_argparser(prog=None): """ @@ -459,10 +461,10 @@ def format_human_readable_memory(num_kbytes): """format the number of bytes given as a human readable value""" if num_kbytes < 1024: value = "%.2f KiB" % (num_kbytes) - elif num_kbytes < (1024 ** 2): - value = "%.2f MiB" % (num_kbytes / (1024 ** 1)) + elif num_kbytes < (1024**2): + value = "%.2f MiB" % (num_kbytes / (1024**1)) else: - value = "%.2f GiB" % (num_kbytes / (1024 ** 2)) + value = "%.2f GiB" % (num_kbytes / (1024**2)) return value @@ -550,9 +552,11 @@ def vtr_command_main(arg_list, prog=None): vpr_args["read_vpr_constraints"] = Path(vpr_constraint_file_copy).name print( - args.name - if args.name - else Path(args.architecture_file).stem + "/" + Path(args.circuit_file).stem, + ( + args.name + if args.name + else Path(args.architecture_file).stem + "/" + Path(args.circuit_file).stem + ), end="\t\t", ) # Run the flow diff --git a/vtr_flow/scripts/run_vtr_task.py b/vtr_flow/scripts/run_vtr_task.py index 0d9c5013181..ce16f44d518 100755 --- a/vtr_flow/scripts/run_vtr_task.py +++ b/vtr_flow/scripts/run_vtr_task.py @@ -471,9 +471,9 @@ def format_human_readable_time(seconds): def format_human_readable_memory(num_bytes): """format the number of bytes given as a human readable value""" - if num_bytes < 1024 ** 3: - return "%.2f MiB" % (num_bytes / (1024 ** 2)) - return "%.2f GiB" % (num_bytes / (1024 ** 3)) + if num_bytes < 1024**3: + return "%.2f MiB" % (num_bytes / (1024**2)) + return "%.2f GiB" % (num_bytes / (1024**3)) def run_vtr_flow_process(queue, run_dirs, job, script) -> None: diff --git a/vtr_flow/scripts/tuning_runs/control_runs.py b/vtr_flow/scripts/tuning_runs/control_runs.py index 825b3b7609c..c38e2cd7292 100755 --- a/vtr_flow/scripts/tuning_runs/control_runs.py +++ b/vtr_flow/scripts/tuning_runs/control_runs.py @@ -46,9 +46,7 @@ def parse_results(input_path): Parse the output results """ # Find the runXXX directory with the largest XXX - run_dirs = [ - d for d in os.listdir(input_path) if d.startswith("run") and d[3:].isdigit() - ] + run_dirs = [d for d in os.listdir(input_path) if d.startswith("run") and d[3:].isdigit()] if not run_dirs: print("No runXXX directories found in the specified input path.") sys.exit(1) @@ -63,9 +61,9 @@ def parse_results(input_path): sys.exit(1) # Read the parse_results.txt file and write to full_res.csv - with open( - os.path.join(largest_run_path, "parse_results.txt"), "r" - ) as txt_file, open(full_res_csv_path, "w", newline="") as csv_file: + with open(os.path.join(largest_run_path, "parse_results.txt"), "r") as txt_file, open( + full_res_csv_path, "w", newline="" + ) as csv_file: reader = csv.reader(txt_file, delimiter="\t") writer = csv.writer(csv_file) @@ -97,9 +95,7 @@ def parse_results(input_path): print("Generated average seed results") # Generate gmean_res.csv - generate_geomean_res_csv( - os.path.join(largest_run_path, "avg_seed.csv"), largest_run_path - ) + generate_geomean_res_csv(os.path.join(largest_run_path, "avg_seed.csv"), largest_run_path) print("Generated geometric average results over all the circuits") generate_xlsx(largest_run_path) @@ -147,8 +143,7 @@ def parse_script_params(script_params): j = i + key_length while j < len(parts) and not any( - parts[j : j + len(k.split("_"))] == k.split("_") - for k in PARAMS_DICT + parts[j : j + len(k.split("_"))] == k.split("_") for k in PARAMS_DICT ): value_parts.append(parts[j]) j += 1 diff --git a/vtr_flow/tasks/koios_task_list.txt b/vtr_flow/tasks/koios_task_list.txt new file mode 100644 index 00000000000..893a9cdd78b --- /dev/null +++ b/vtr_flow/tasks/koios_task_list.txt @@ -0,0 +1,6 @@ +regression_tests/vtr_reg_nightly_test4/koios_medium +regression_tests/vtr_reg_nightly_test6/koios_other +regression_tests/vtr_reg_weekly/koios_bwave_float_large +regression_tests/vtr_reg_weekly/koios_dla_large +regression_tests/vtr_reg_weekly/koios_large +regression_tests/vtr_reg_weekly/koios_proxy diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt index aab4bc19474..a19aa57c938 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 2.23 vpr 62.52 MiB -1 -1 0.44 18128 3 0.11 -1 -1 33248 -1 -1 71 99 1 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64024 99 130 353 483 1 222 301 13 13 169 clb auto 22.9 MiB 0.06 730 30541 5185 13290 12066 62.5 MiB 0.05 0.00 28 1583 11 3.33e+06 2.25e+06 384474. 2275.00 0.60 - k4_N10_memSize16384_memData64.xml diffeq1.v common 3.94 vpr 66.34 MiB -1 -1 0.54 23352 23 0.30 -1 -1 34272 -1 -1 77 162 0 5 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67928 162 96 1200 1141 1 675 340 13 13 169 clb auto 26.0 MiB 0.18 5120 92848 24971 61178 6699 66.3 MiB 0.19 0.00 52 9701 16 3.33e+06 2.76e+06 671819. 3975.26 1.21 - k4_N10_memSize16384_memData64.xml single_wire.v common 0.68 vpr 60.16 MiB -1 -1 0.06 16212 1 0.03 -1 -1 29556 -1 -1 0 1 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61604 1 1 1 2 0 1 2 3 3 9 -1 auto 21.3 MiB 0.00 2 3 0 3 0 60.2 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 - k4_N10_memSize16384_memData64.xml single_ff.v common 0.73 vpr 60.14 MiB -1 -1 0.15 16376 1 0.02 -1 -1 29780 -1 -1 1 2 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61580 2 1 3 4 1 3 4 3 3 9 -1 auto 21.3 MiB 0.00 6 9 6 0 3 60.1 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.01 + k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.71 vpr 62.29 MiB -1 -1 0.45 18372 3 0.09 -1 -1 33140 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63780 99 130 353 483 1 222 301 13 13 169 clb auto 22.7 MiB 0.06 730 30541 5185 13290 12066 62.3 MiB 0.05 0.00 28 1583 11 3.33e+06 2.25e+06 384474. 2275.00 0.18 + k4_N10_memSize16384_memData64.xml diffeq1.v common 3.90 vpr 66.30 MiB -1 -1 0.72 23492 23 0.30 -1 -1 34028 -1 -1 77 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67888 162 96 1200 1141 1 675 340 13 13 169 clb auto 25.9 MiB 0.18 5120 92848 24971 61178 6699 66.3 MiB 0.19 0.00 52 9637 13 3.33e+06 2.76e+06 671819. 3975.26 1.14 + k4_N10_memSize16384_memData64.xml single_wire.v common 2.10 vpr 59.81 MiB -1 -1 0.16 16372 1 0.17 -1 -1 29680 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 61244 1 1 1 2 0 1 2 3 3 9 -1 auto 21.3 MiB 0.00 2 3 0 3 0 59.8 MiB 0.01 0.00 2 1 1 30000 0 1489.46 165.495 0.01 + k4_N10_memSize16384_memData64.xml single_ff.v common 2.13 vpr 59.62 MiB -1 -1 0.15 16244 1 0.17 -1 -1 29552 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 61048 2 1 3 4 1 3 4 3 3 9 -1 auto 21.2 MiB 0.00 6 9 6 0 3 59.6 MiB 0.01 0.00 16 5 1 30000 30000 2550.78 283.420 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt index 67331c4ebeb..751bc75b90b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.79 vpr 64.14 MiB -1 -1 0.42 18236 3 0.09 -1 -1 33188 -1 -1 71 99 1 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65676 99 130 344 474 1 225 301 13 13 169 clb auto 24.4 MiB 0.09 670 76909 23210 36946 16753 64.1 MiB 0.26 0.00 2.16096 -124.917 -2.16096 2.16096 0.32 0.00129032 0.00122184 0.1026 0.0970333 -1 -1 -1 -1 32 1294 10 6.63067e+06 4.37447e+06 323148. 1912.12 1.31 0.41172 0.377314 11612 59521 -1 1127 11 526 869 34973 10462 1.97404 1.97404 -140.169 -1.97404 -0.343814 -0.101108 396943. 2348.77 0.10 0.05 0.06 -1 -1 0.10 0.0333808 0.0307491 - k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.81 vpr 64.05 MiB -1 -1 0.41 18040 3 0.09 -1 -1 33320 -1 -1 71 99 1 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65588 99 130 344 474 1 225 301 13 13 169 clb auto 24.3 MiB 0.09 670 76909 23210 36946 16753 64.1 MiB 0.26 0.00 2.16096 -124.917 -2.16096 2.16096 0.31 0.00129523 0.00122583 0.102212 0.0966604 -1 -1 -1 -1 32 1294 10 6.63067e+06 4.37447e+06 323148. 1912.12 1.31 0.406344 0.372511 11612 59521 -1 1127 11 526 869 34973 10462 1.97404 1.97404 -140.169 -1.97404 -0.343814 -0.101108 396943. 2348.77 0.10 0.05 0.06 -1 -1 0.10 0.0333856 0.0307499 - k6_N10_mem32K_40nm.xml diffeq1.v common 11.07 vpr 67.31 MiB -1 -1 0.73 22916 15 0.35 -1 -1 34340 -1 -1 61 162 0 5 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68924 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.9 MiB 0.28 5631 94844 28473 58959 7412 67.3 MiB 0.68 0.01 21.7383 -1576.03 -21.7383 21.7383 0.52 0.00334089 0.00313474 0.301598 0.282973 -1 -1 -1 -1 44 10661 49 1.21132e+07 5.26753e+06 665287. 2598.78 6.02 1.62204 1.48659 20656 131250 -1 8667 20 3482 8436 990185 277410 22.0559 22.0559 -1674.9 -22.0559 0 0 864808. 3378.16 0.21 0.34 0.12 -1 -1 0.21 0.151934 0.140555 - k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 11.23 vpr 67.06 MiB -1 -1 0.73 23204 15 0.35 -1 -1 34356 -1 -1 61 162 0 5 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68668 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.6 MiB 0.27 5631 94844 28473 58959 7412 67.1 MiB 0.69 0.01 21.7383 -1576.03 -21.7383 21.7383 0.52 0.00336493 0.00315749 0.301999 0.283119 -1 -1 -1 -1 44 10661 49 1.21132e+07 5.26753e+06 665287. 2598.78 6.18 1.63915 1.50303 20656 131250 -1 8667 20 3482 8436 990185 277410 22.0559 22.0559 -1674.9 -22.0559 0 0 864808. 3378.16 0.21 0.34 0.12 -1 -1 0.21 0.151674 0.140243 - k6_N10_mem32K_40nm.xml single_wire.v common 0.71 vpr 61.63 MiB -1 -1 0.15 16380 1 0.02 -1 -1 29720 -1 -1 0 1 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63108 1 1 1 2 0 1 2 3 3 9 -1 auto 23.0 MiB 0.00 2 3 0 3 0 61.6 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0494e-05 7.076e-06 7.8316e-05 5.7044e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00113075 0.00106709 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00105433 0.00102822 - k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.70 vpr 61.38 MiB -1 -1 0.14 16336 1 0.02 -1 -1 29760 -1 -1 0 1 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 62848 1 1 1 2 0 1 2 3 3 9 -1 auto 22.7 MiB 0.00 2 3 0 3 0 61.4 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0478e-05 7.086e-06 6.5653e-05 4.7198e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00141342 0.00135618 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00109338 0.00106763 - k6_N10_mem32K_40nm.xml single_ff.v common 0.72 vpr 61.40 MiB -1 -1 0.12 16364 1 0.02 -1 -1 29716 -1 -1 1 2 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 62872 2 1 3 4 1 3 4 3 3 9 -1 auto 22.8 MiB 0.00 6 9 3 5 1 61.4 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5219e-05 1.1422e-05 0.000111249 8.9402e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00146865 0.00138013 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00114176 0.00110413 - k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.75 vpr 61.35 MiB -1 -1 0.14 16260 1 0.02 -1 -1 29632 -1 -1 1 2 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 62820 2 1 3 4 1 3 4 3 3 9 -1 auto 22.7 MiB 0.00 6 9 3 5 1 61.3 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5145e-05 1.1318e-05 0.000103946 8.1944e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00129416 0.0012252 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00133017 0.00128358 + k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.47 vpr 63.16 MiB -1 -1 0.44 18236 3 0.17 -1 -1 33188 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64672 99 130 344 474 1 225 301 13 13 169 clb auto 23.3 MiB 0.09 736 75901 22924 36629 16348 63.2 MiB 0.26 0.00 2.16096 -125.507 -2.16096 2.16096 0.16 0.00128139 0.00121469 0.100824 0.095478 -1 -1 -1 -1 32 1361 16 6.63067e+06 4.37447e+06 323148. 1912.12 0.39 0.254103 0.235005 11612 59521 -1 1272 10 497 712 34049 10041 1.99692 1.99692 -142.118 -1.99692 -0.13959 -0.0561481 396943. 2348.77 0.01 0.05 0.06 -1 -1 0.01 0.0312641 0.0288189 + k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.44 vpr 63.16 MiB -1 -1 0.50 18152 3 0.14 -1 -1 33088 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 99 130 344 474 1 225 301 13 13 169 clb auto 23.2 MiB 0.11 736 75901 22924 36629 16348 63.2 MiB 0.26 0.00 2.16096 -125.507 -2.16096 2.16096 0.16 0.00128481 0.00121739 0.100806 0.0954483 -1 -1 -1 -1 32 1361 16 6.63067e+06 4.37447e+06 323148. 1912.12 0.39 0.254201 0.235091 11612 59521 -1 1272 10 497 712 34049 10041 1.99692 1.99692 -142.118 -1.99692 -0.13959 -0.0561481 396943. 2348.77 0.01 0.05 0.06 -1 -1 0.01 0.0311227 0.0286984 + k6_N10_mem32K_40nm.xml diffeq1.v common 9.49 vpr 67.11 MiB -1 -1 0.77 23280 15 0.36 -1 -1 34140 -1 -1 61 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 68724 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.7 MiB 0.29 5596 100404 30167 62963 7274 67.1 MiB 0.72 0.01 21.2727 -1572.97 -21.2727 21.2727 0.25 0.00332766 0.00312916 0.315543 0.296132 -1 -1 -1 -1 40 11119 33 1.21132e+07 5.26753e+06 612675. 2393.26 4.42 1.40293 1.28823 19892 118481 -1 8936 23 3487 7703 996102 285541 21.8294 21.8294 -1657.3 -21.8294 0 0 771607. 3014.09 0.03 0.36 0.10 -1 -1 0.03 0.165646 0.152968 + k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 9.36 vpr 66.73 MiB -1 -1 0.76 23068 15 0.37 -1 -1 34060 -1 -1 61 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 68332 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.4 MiB 0.27 5596 100404 30167 62963 7274 66.7 MiB 0.73 0.01 21.2727 -1572.97 -21.2727 21.2727 0.25 0.00332438 0.00312633 0.31865 0.29876 -1 -1 -1 -1 40 11119 33 1.21132e+07 5.26753e+06 612675. 2393.26 4.32 1.38842 1.27429 19892 118481 -1 8936 23 3487 7703 996102 285541 21.8294 21.8294 -1657.3 -21.8294 0 0 771607. 3014.09 0.03 0.36 0.10 -1 -1 0.03 0.165924 0.153299 + k6_N10_mem32K_40nm.xml single_wire.v common 2.19 vpr 61.04 MiB -1 -1 0.10 16040 1 0.17 -1 -1 29628 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62508 1 1 1 2 0 1 2 3 3 9 -1 auto 22.4 MiB 0.03 2 3 0 3 0 61.0 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0106e-05 6.693e-06 6.7577e-05 4.7955e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00184576 0.00171316 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00130358 0.00127692 + k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.14 vpr 61.03 MiB -1 -1 0.18 16180 1 0.17 -1 -1 29612 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62496 1 1 1 2 0 1 2 3 3 9 -1 auto 22.5 MiB 0.01 2 3 0 3 0 61.0 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 3.4991e-05 2.3839e-05 0.000154694 0.000110075 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.01 0.00205152 0.00184775 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00106138 0.00103434 + k6_N10_mem32K_40nm.xml single_ff.v common 2.12 vpr 60.94 MiB -1 -1 0.17 16352 1 0.17 -1 -1 29692 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62400 2 1 3 4 1 3 4 3 3 9 -1 auto 22.4 MiB 0.01 6 9 3 5 1 60.9 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5239e-05 1.148e-05 9.224e-05 7.1486e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00131631 0.00123081 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.0011347 0.00109647 + k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.11 vpr 61.02 MiB -1 -1 0.17 16384 1 0.17 -1 -1 29576 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62488 2 1 3 4 1 3 4 3 3 9 -1 auto 22.5 MiB 0.00 6 9 3 5 1 61.0 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.54e-05 1.1599e-05 9.8314e-05 7.6493e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.001247 0.00116724 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00104656 0.00101086 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt index f8224ce61bf..e5e577a6aa0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml mkPktMerge.v common 14.48 vpr 69.41 MiB -1 -1 1.43 25504 2 0.13 -1 -1 33808 -1 -1 43 311 15 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71080 311 156 972 1128 1 953 525 28 28 784 memory auto 28.9 MiB 0.44 9159 207991 76469 122068 9454 69.4 MiB 1.18 0.02 4.10864 -4363.81 -4.10864 4.10864 1.88 0.00581049 0.00492665 0.571738 0.503271 -1 -1 -1 -1 38 14134 13 4.25198e+07 1.05374e+07 1.95643e+06 2495.44 4.44 1.4407 1.2729 61576 387106 -1 13120 12 2507 3155 746004 220560 4.19903 4.19903 -4897.24 -4.19903 -19.5582 -0.360359 2.46901e+06 3149.24 0.67 0.31 0.33 -1 -1 0.67 0.171757 0.154277 + k6_N10_mem32K_40nm.xml mkPktMerge.v common 14.27 vpr 75.54 MiB -1 -1 1.67 25360 2 0.13 -1 -1 33796 -1 -1 43 311 15 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77356 311 156 972 1128 1 953 525 28 28 784 memory auto 28.9 MiB 0.44 8505 220693 82593 126911 11189 69.5 MiB 1.24 0.02 3.82651 -4329.36 -3.82651 3.82651 0.84 0.00554225 0.00490893 0.598549 0.528234 -1 -1 -1 -1 40 13414 12 4.25198e+07 1.05374e+07 2.03169e+06 2591.44 6.02 1.94301 1.71815 62360 400487 -1 12485 12 2406 2992 760238 228941 4.26893 4.26893 -4812.21 -4.26893 -13.8425 -0.321515 2.55406e+06 3257.73 0.09 0.29 0.34 -1 -1 0.09 0.16964 0.153486 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt index 02aded8804a..cbe871a6d70 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 2.65 vpr 62.39 MiB -1 -1 0.47 18396 3 0.09 -1 -1 33152 -1 -1 71 99 1 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63892 99 130 353 483 1 222 301 13 13 169 clb auto 22.7 MiB 0.06 723 26509 3069 10019 13421 62.4 MiB 0.04 0.00 28 1598 8 3.33e+06 2.25e+06 384474. 2275.00 0.98 +k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 2.71 vpr 61.64 MiB -1 -1 0.45 18444 3 0.09 -1 -1 32856 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63120 99 130 353 483 1 222 301 13 13 169 clb auto 21.8 MiB 0.06 723 26509 3069 10019 13421 61.6 MiB 0.04 0.00 28 1598 8 3.33e+06 2.25e+06 384474. 2275.00 0.18 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt index e28c0960805..1c07cad2e4f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.45 vpr 64.20 MiB -1 -1 0.07 20736 1 0.03 -1 -1 35464 -1 -1 2 6 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65736 6 1 13 14 2 8 9 4 4 16 clb auto 25.8 MiB 0.00 15 27 4 16 7 64.2 MiB 0.00 0.00 0.876768 -3.25729 -0.876768 0.545 0.01 3.3326e-05 2.4624e-05 0.000207932 0.000172543 20 18 16 107788 107788 10441.3 652.579 0.01 0.00186873 0.00161723 742 1670 -1 18 2 7 7 153 93 1.4073 0.545 -4.29789 -1.4073 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00108236 0.00102087 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.49 vpr 64.30 MiB -1 -1 0.09 20608 1 0.04 -1 -1 35572 -1 -1 2 3 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65840 3 -1 23 23 2 3 5 4 4 16 clb auto 26.0 MiB 0.01 2 12 2 3 7 64.3 MiB 0.00 0.00 0.545 -7.62503 -0.545 0.545 0.01 5.8243e-05 5.0672e-05 0.000432079 0.000390226 8 1 1 107788 107788 4888.88 305.555 0.02 0.00256655 0.00231135 622 902 -1 1 1 1 1 9 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00154902 0.00148079 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.91 vpr 62.53 MiB -1 -1 0.10 16916 1 0.05 -1 -1 32024 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64032 6 1 13 14 2 8 9 4 4 16 clb auto 23.8 MiB 0.01 22 27 6 15 6 62.5 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.8829e-05 2.8382e-05 0.000261465 0.000217889 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00235757 0.00212728 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00170712 0.00164334 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.93 vpr 62.57 MiB -1 -1 0.14 17260 1 0.06 -1 -1 31980 -1 -1 2 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64076 3 -1 23 23 2 3 5 4 4 16 clb auto 23.8 MiB 0.01 3 12 2 3 7 62.6 MiB 0.00 0.00 0.620297 -7.93119 -0.620297 0.545 0.01 6.0445e-05 5.1078e-05 0.000540631 0.00048682 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00313926 0.00293123 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00237872 0.0022794 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt index c5973b977a6..ace8a8d93f0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.56 vpr 64.33 MiB -1 -1 0.07 20736 1 0.04 -1 -1 35300 -1 -1 2 6 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65872 6 1 13 14 2 8 9 4 4 16 clb auto 26.0 MiB 0.00 15 27 4 16 7 64.3 MiB 0.00 0.00 0.876768 -3.25729 -0.876768 0.545 0.01 3.8575e-05 3.0523e-05 0.000220522 0.000177612 20 18 16 107788 107788 10441.3 652.579 0.01 0.00189872 0.00159852 742 1670 -1 18 2 7 7 153 93 1.4073 0.545 -4.29789 -1.4073 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00112306 0.00106033 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.57 vpr 64.14 MiB -1 -1 0.09 20736 1 0.04 -1 -1 35416 -1 -1 1 2 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65680 2 -1 16 16 1 2 3 3 3 9 -1 auto 25.9 MiB 0.01 2 6 3 0 3 64.1 MiB 0.00 0.00 0.545 -3.815 -0.545 0.545 0.00 6.3651e-05 3.6185e-05 0.000421892 0.000363995 2 1 1 53894 53894 1178.84 130.982 0.01 0.00245442 0.00219784 283 309 -1 1 1 1 1 9 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00140976 0.00134385 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.12 vpr 61.70 MiB -1 -1 0.11 16536 1 0.08 -1 -1 31596 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63184 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.7 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.8582e-05 2.7966e-05 0.000277936 0.000219445 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.02 0.00248443 0.00222718 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00178059 0.00171145 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.12 vpr 61.63 MiB -1 -1 0.15 16580 1 0.06 -1 -1 31648 -1 -1 1 2 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63112 2 -1 16 16 1 2 3 3 3 9 -1 auto 23.2 MiB 0.01 3 6 4 0 2 61.6 MiB 0.00 0.00 0.545 -3.815 -0.545 0.545 0.00 4.1349e-05 3.4027e-05 0.000423997 0.000380122 -1 -1 -1 -1 2 1 1 53894 53894 1178.84 130.982 0.00 0.00258339 0.00244324 283 309 -1 1 1 1 1 8 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00225406 0.00217221 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt index a82f6475eb8..2b26635347b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt @@ -1,11 +1,11 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml bigkey.blif common 5.34 vpr 66.09 MiB -1 -1 -1 -1 3 0.41 -1 -1 38400 -1 -1 53 229 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 67676 229 197 1023 1220 1 510 479 16 16 256 io auto 28.2 MiB 0.25 3590 165303 54609 101546 9148 66.1 MiB 0.56 0.01 2.09742 -520.234 -2.09742 2.09742 0.72 0.00198922 0.0017893 0.194468 0.174387 38 6231 19 1.05632e+07 2.85638e+06 667532. 2607.55 1.61 0.552311 0.501002 25328 137766 -1 5709 10 1328 2368 138222 31100 2.53491 2.53491 -631.681 -2.53491 0 0 843755. 3295.92 0.23 0.09 0.11 -1 -1 0.23 0.0694375 0.0651755 -k6_frac_N10_40nm.xml clma.blif common 5.81 vpr 63.61 MiB -1 -1 -1 -1 7 2.43 -1 -1 43060 -1 -1 77 36 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65132 36 82 542 624 1 390 195 11 11 121 clb auto 25.6 MiB 0.39 2049 40310 15727 18888 5695 63.6 MiB 0.19 0.00 4.12702 -139.772 -4.12702 4.12702 0.35 0.00089595 0.000795753 0.0662268 0.0581277 40 4765 27 4.36541e+06 4.14984e+06 303235. 2506.08 1.27 0.24116 0.212364 11571 60661 -1 3811 17 2179 7425 230352 49600 4.72633 4.72633 -172.493 -4.72633 0 0 379421. 3135.71 0.10 0.10 0.05 -1 -1 0.10 0.0504584 0.0466881 -k6_frac_N10_40nm.xml diffeq.blif common 3.47 vpr 65.28 MiB -1 -1 -1 -1 8 0.38 -1 -1 37780 -1 -1 51 64 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66848 64 39 941 980 1 450 154 10 10 100 clb auto 27.4 MiB 0.49 2676 18694 4142 13457 1095 65.3 MiB 0.17 0.00 4.29927 -776.73 -4.29927 4.29927 0.21 0.00140232 0.00123094 0.0782133 0.0687319 46 4588 16 3.44922e+06 2.74859e+06 276332. 2763.32 1.14 0.400394 0.355124 9816 55112 -1 4229 15 1767 5248 152494 32440 5.1527 5.1527 -909.086 -5.1527 0 0 354105. 3541.05 0.09 0.11 0.05 -1 -1 0.09 0.074353 0.068615 -k6_frac_N10_40nm.xml dsip.blif common 7.16 vpr 67.73 MiB -1 -1 -1 -1 3 0.29 -1 -1 38168 -1 -1 68 229 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 69360 229 197 1135 1332 1 648 494 16 16 256 io auto 29.8 MiB 0.61 4921 178126 59233 109418 9475 67.7 MiB 0.72 0.01 2.05678 -537.964 -2.05678 2.05678 0.70 0.00258579 0.00228238 0.249464 0.221181 36 8990 21 1.05632e+07 3.66479e+06 638738. 2495.07 2.87 0.913578 0.809462 24820 128426 -1 8106 12 2276 5612 323677 69139 2.59846 2.59846 -678.186 -2.59846 0 0 786978. 3074.13 0.24 0.17 0.11 -1 -1 0.24 0.102783 0.0965443 -k6_frac_N10_40nm.xml elliptic.blif common 11.17 vpr 75.88 MiB -1 -1 -1 -1 10 1.31 -1 -1 42108 -1 -1 133 131 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 77704 131 114 2471 2585 1 967 378 14 14 196 clb auto 38.7 MiB 2.04 9202 87802 25510 58148 4144 75.9 MiB 0.81 0.01 6.00251 -3050.7 -6.00251 6.00251 0.50 0.00442638 0.00375412 0.333118 0.286228 64 16031 41 7.76074e+06 7.1679e+06 810706. 4136.26 3.96 1.36942 1.18204 22444 164128 -1 14254 16 4284 17997 698961 120654 7.04139 7.04139 -3672.36 -7.04139 0 0 1.00880e+06 5146.95 0.27 0.37 0.15 -1 -1 0.27 0.21767 0.199157 -k6_frac_N10_40nm.xml frisc.blif common 20.76 vpr 77.35 MiB -1 -1 -1 -1 12 2.02 -1 -1 42412 -1 -1 153 20 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 79204 20 116 2477 2593 1 1097 289 15 15 225 clb auto 40.1 MiB 2.38 13235 56634 14640 37590 4404 77.3 MiB 0.80 0.01 7.08157 -3353.27 -7.08157 7.08157 0.61 0.00557214 0.00505815 0.329992 0.284762 80 22726 42 9.10809e+06 8.24578e+06 1.12687e+06 5008.33 11.88 2.38469 2.06328 28171 234221 -1 19580 15 5661 25029 1100753 177994 8.34828 8.34828 -3982.46 -8.34828 0 0 1.41774e+06 6301.08 0.40 0.47 0.23 -1 -1 0.40 0.24451 0.223131 -k6_frac_N10_40nm.xml s298.blif common 3.93 vpr 65.13 MiB -1 -1 -1 -1 8 0.54 -1 -1 37848 -1 -1 62 4 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66692 4 6 671 677 1 352 72 10 10 100 clb auto 27.2 MiB 0.63 3508 3797 558 3049 190 65.1 MiB 0.09 0.00 4.79301 -39.1818 -4.79301 4.79301 0.21 0.00107169 0.000871246 0.0396977 0.0348858 50 5642 44 3.44922e+06 3.34143e+06 295697. 2956.97 1.34 0.354454 0.310134 10016 58256 -1 5050 17 2138 10782 337740 61219 5.55589 5.55589 -47.4222 -5.55589 0 0 379824. 3798.24 0.09 0.16 0.05 -1 -1 0.09 0.0836831 0.0767868 -k6_frac_N10_40nm.xml s38417.blif common 18.17 vpr 81.67 MiB -1 -1 -1 -1 6 3.18 -1 -1 45752 -1 -1 178 29 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 83628 29 106 3450 3556 1 1206 313 16 16 256 clb auto 44.6 MiB 1.73 9735 73591 18515 47646 7430 81.7 MiB 1.01 0.01 4.1003 -2647.73 -4.1003 4.1003 0.71 0.00572737 0.00502875 0.490793 0.413594 50 16598 31 1.05632e+07 9.59313e+06 843755. 3295.92 8.36 2.66872 2.25339 27116 171776 -1 14184 14 5218 17339 563986 111457 4.90849 4.90849 -3063.34 -4.90849 0 0 1.08660e+06 4244.53 0.30 0.40 0.15 -1 -1 0.30 0.294514 0.26614 -k6_frac_N10_40nm.xml s38584.1.blif common 15.38 vpr 81.98 MiB -1 -1 -1 -1 6 2.31 -1 -1 44476 -1 -1 197 38 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 83944 38 304 3259 3563 1 1569 539 17 17 289 clb auto 45.1 MiB 2.22 10132 186859 56261 111331 19267 82.0 MiB 1.57 0.02 3.66766 -2189.34 -3.66766 3.66766 0.83 0.00720702 0.00587597 0.662359 0.559768 58 18045 29 1.21262e+07 1.06171e+07 1.11519e+06 3858.79 4.91 2.07239 1.77997 32499 230706 -1 16150 15 5235 13970 535313 110316 4.52216 4.52216 -2592.43 -4.52216 0 0 1.41877e+06 4909.24 0.44 0.45 0.21 -1 -1 0.44 0.337035 0.302445 -k6_frac_N10_40nm.xml tseng.blif common 3.22 vpr 63.44 MiB -1 -1 -1 -1 7 0.26 -1 -1 36620 -1 -1 34 52 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64964 52 122 664 786 1 355 208 8 8 64 io clb auto 25.5 MiB 0.48 1722 24848 5456 17914 1478 63.4 MiB 0.15 0.00 3.67867 -543.309 -3.67867 3.67867 0.13 0.00118347 0.00104151 0.0584783 0.0523041 60 3348 21 1.94018e+06 1.8324e+06 209903. 3279.73 1.38 0.400601 0.357549 6596 40562 -1 2925 12 1076 2803 103485 26847 4.47179 4.47179 -637.579 -4.47179 0 0 263485. 4116.95 0.06 0.07 0.04 -1 -1 0.06 0.0496902 0.0465196 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml bigkey.blif common 6.03 vpr 64.18 MiB -1 -1 -1 -1 3 0.52 -1 -1 34720 -1 -1 53 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65716 229 197 1023 1220 1 510 479 16 16 256 io auto 23.6 MiB 0.35 3641 154065 46430 98015 9620 64.2 MiB 0.72 0.01 2.42373 -577.247 -2.42373 2.42373 0.36 0.00384602 0.00349572 0.296143 0.271678 -1 -1 -1 -1 36 6328 35 1.05632e+07 2.85638e+06 638738. 2495.07 1.93 1.0007 0.917076 24820 128426 -1 5481 8 1306 2376 126862 31374 2.67597 2.67597 -632.008 -2.67597 0 0 786978. 3074.13 0.04 0.15 0.12 -1 -1 0.04 0.11083 0.104176 + k6_frac_N10_40nm.xml clma.blif common 9.71 vpr 61.27 MiB -1 -1 -1 -1 7 3.14 -1 -1 39932 -1 -1 79 36 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62740 36 82 542 624 1 389 197 11 11 121 clb auto 21.7 MiB 0.60 2089 43172 15722 20877 6573 61.3 MiB 0.31 0.01 4.60077 -165.07 -4.60077 4.60077 0.14 0.00147192 0.00133772 0.126064 0.114454 -1 -1 -1 -1 44 4139 30 4.36541e+06 4.25763e+06 327165. 2703.84 3.55 0.883664 0.783925 11931 67129 -1 3316 16 1708 5716 138864 32420 4.83136 4.83136 -175.151 -4.83136 0 0 426099. 3521.48 0.02 0.16 0.06 -1 -1 0.02 0.101559 0.0936106 + k6_frac_N10_40nm.xml diffeq.blif common 4.49 vpr 63.36 MiB -1 -1 -1 -1 8 0.52 -1 -1 34256 -1 -1 52 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64884 64 39 941 980 1 449 155 10 10 100 clb auto 23.4 MiB 0.76 2832 12635 2438 9282 915 63.4 MiB 0.20 0.01 4.98272 -882.824 -4.98272 4.98272 0.11 0.00295588 0.00259149 0.100311 0.0902062 -1 -1 -1 -1 46 4591 19 3.44922e+06 2.80249e+06 276332. 2763.32 1.60 0.775874 0.679691 9816 55112 -1 4111 18 1656 5042 136520 29654 5.41789 5.41789 -952.235 -5.41789 0 0 354105. 3541.05 0.01 0.17 0.05 -1 -1 0.01 0.125756 0.115657 + k6_frac_N10_40nm.xml dsip.blif common 7.14 vpr 64.52 MiB -1 -1 -1 -1 3 0.40 -1 -1 34652 -1 -1 68 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66068 229 197 1135 1332 1 648 494 16 16 256 io auto 24.8 MiB 0.78 5390 162510 50223 103313 8974 64.5 MiB 1.03 0.02 2.31397 -600.978 -2.31397 2.31397 0.34 0.00602326 0.00554387 0.451127 0.410954 -1 -1 -1 -1 34 9972 32 1.05632e+07 3.66479e+06 613832. 2397.78 2.69 1.43645 1.29189 24564 122629 -1 8332 13 2339 5868 306706 68264 2.51113 2.51113 -669.569 -2.51113 0 0 751777. 2936.63 0.04 0.27 0.11 -1 -1 0.04 0.172623 0.161651 + k6_frac_N10_40nm.xml elliptic.blif common 13.54 vpr 72.58 MiB -1 -1 -1 -1 10 1.77 -1 -1 37472 -1 -1 134 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74324 131 114 2471 2585 1 965 379 14 14 196 clb auto 31.6 MiB 3.12 9493 78526 21300 53244 3982 72.6 MiB 1.13 0.02 6.66989 -3362.18 -6.66989 6.66989 0.25 0.0073855 0.00682539 0.510617 0.432228 -1 -1 -1 -1 64 15463 36 7.76074e+06 7.2218e+06 810706. 4136.26 4.40 2.27 1.95789 22444 164128 -1 13666 16 4234 17970 605416 107406 6.78748 6.78748 -3469.91 -6.78748 0 0 1.00880e+06 5146.95 0.04 0.57 0.15 -1 -1 0.04 0.380082 0.346066 + k6_frac_N10_40nm.xml frisc.blif common 19.09 vpr 73.82 MiB -1 -1 -1 -1 12 2.63 -1 -1 37332 -1 -1 154 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75588 20 116 2477 2593 1 1095 290 15 15 225 clb auto 33.0 MiB 3.90 12890 61666 15631 41457 4578 73.8 MiB 1.29 0.02 8.02167 -3816.55 -8.02167 8.02167 0.29 0.00799854 0.00736702 0.607385 0.536113 -1 -1 -1 -1 74 21484 43 9.10809e+06 8.29968e+06 1.06098e+06 4715.46 6.97 3.19949 2.845 27275 217117 -1 19434 16 5788 25215 1069833 185373 8.27179 8.27179 -4029.23 -8.27179 0 0 1.32822e+06 5903.22 0.06 0.85 0.22 -1 -1 0.06 0.50277 0.462472 + k6_frac_N10_40nm.xml s298.blif common 6.89 vpr 61.61 MiB -1 -1 -1 -1 8 0.90 -1 -1 33640 -1 -1 61 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63092 4 6 671 677 1 350 71 10 10 100 clb auto 22.3 MiB 1.13 3495 3137 432 2529 176 61.6 MiB 0.13 0.00 5.3014 -43.7499 -5.3014 5.3014 0.10 0.00213324 0.00193977 0.0653912 0.0590662 -1 -1 -1 -1 54 5597 27 3.44922e+06 3.28753e+06 316276. 3162.76 2.70 0.969741 0.854177 10312 63908 -1 5157 17 2266 11525 327366 61505 5.48392 5.48392 -46.8399 -5.48392 0 0 411339. 4113.39 0.02 0.24 0.06 -1 -1 0.02 0.132836 0.122294 + k6_frac_N10_40nm.xml s38417.blif common 19.91 vpr 78.25 MiB -1 -1 -1 -1 6 4.38 -1 -1 42652 -1 -1 176 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80128 29 106 3450 3556 1 1190 311 16 16 256 clb auto 37.0 MiB 2.32 8949 65597 16026 43107 6464 78.2 MiB 1.45 0.02 4.50231 -2905.37 -4.50231 4.50231 0.31 0.013459 0.0123921 0.819893 0.68577 -1 -1 -1 -1 46 15732 39 1.05632e+07 9.48534e+06 786978. 3074.13 7.54 3.76391 3.16115 26604 162157 -1 13635 14 5142 17426 519616 106370 4.53102 4.53102 -2987.6 -4.53102 0 0 1.01084e+06 3948.58 0.05 0.64 0.15 -1 -1 0.05 0.491437 0.438055 + k6_frac_N10_40nm.xml s38584.1.blif common 19.73 vpr 78.57 MiB -1 -1 -1 -1 6 3.21 -1 -1 40768 -1 -1 203 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80452 38 304 3259 3563 1 1559 545 17 17 289 clb auto 37.4 MiB 3.40 10446 174095 49766 105233 19096 78.6 MiB 2.06 0.03 4.29015 -2399.8 -4.29015 4.29015 0.36 0.0108513 0.0100424 0.949535 0.807306 -1 -1 -1 -1 58 17767 23 1.21262e+07 1.09405e+07 1.11519e+06 3858.79 6.55 4.0366 3.46133 32499 230706 -1 16008 15 5250 14700 516522 110817 4.81093 4.81093 -2541.32 -4.81093 0 0 1.41877e+06 4909.24 0.08 0.69 0.21 -1 -1 0.08 0.542118 0.483109 + k6_frac_N10_40nm.xml tseng.blif common 4.86 vpr 60.55 MiB -1 -1 -1 -1 7 0.56 -1 -1 34224 -1 -1 33 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62000 52 122 664 786 1 358 207 8 8 64 io clb auto 20.9 MiB 0.71 1908 22239 4478 16280 1481 60.5 MiB 0.19 0.01 4.25559 -597.466 -4.25559 4.25559 0.07 0.00207961 0.0019366 0.0799798 0.0739686 -1 -1 -1 -1 58 3323 26 1.94018e+06 1.7785e+06 203254. 3175.84 1.37 0.640949 0.573504 6532 39661 -1 2850 14 1079 2916 89573 24965 4.64398 4.64398 -644.298 -4.64398 0 0 258247. 4035.11 0.01 0.11 0.03 -1 -1 0.01 0.0836637 0.0773858 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt index 2c1e5143a34..594c4215910 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.48 vpr 64.32 MiB -1 -1 0.08 20608 1 0.04 -1 -1 35284 -1 -1 2 6 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65868 6 1 13 14 2 8 9 4 4 16 clb auto 26.0 MiB 0.00 15 27 4 16 7 64.3 MiB 0.00 0.00 0.876768 -3.25729 -0.876768 0.545 0.01 4.3317e-05 3.4454e-05 0.000280058 0.000232486 20 18 16 107788 107788 10441.3 652.579 0.01 0.00200757 0.00171843 742 1670 -1 18 2 7 7 153 93 1.4073 0.545 -4.29789 -1.4073 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00115658 0.00109103 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.51 vpr 64.29 MiB -1 -1 0.08 20864 1 0.04 -1 -1 35208 -1 -1 2 3 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65828 3 -1 23 23 2 3 5 4 4 16 clb auto 25.9 MiB 0.01 2 12 2 3 7 64.3 MiB 0.00 0.00 0.545 -7.62503 -0.545 0.545 0.01 5.9477e-05 5.1394e-05 0.000445997 0.000401154 8 1 1 107788 107788 4888.88 305.555 0.02 0.00275649 0.00249621 622 902 -1 1 1 1 1 9 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00158614 0.00151091 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.42 vpr 64.03 MiB -1 -1 0.06 20352 1 0.01 -1 -1 33064 -1 -1 1 3 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65568 3 1 5 6 1 4 5 3 3 9 -1 auto 25.8 MiB 0.00 6 12 8 0 4 64.0 MiB 0.00 0.00 0.544641 -0.918653 -0.544641 0.544641 0.00 2.3999e-05 2.0452e-05 0.000114281 9.2013e-05 20 5 1 53894 53894 4880.82 542.314 0.00 0.00099982 0.000925813 379 725 -1 17 1 3 3 68 57 1.45014 1.45014 -1.99566 -1.45014 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000913044 0.000879537 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.08 vpr 61.77 MiB -1 -1 0.12 16500 1 0.10 -1 -1 31836 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63252 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.8 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.6498e-05 2.6643e-05 0.000260655 0.000218319 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00250948 0.00220504 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00176399 0.00169239 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.09 vpr 61.68 MiB -1 -1 0.15 16776 1 0.07 -1 -1 31648 -1 -1 2 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63160 3 -1 23 23 2 3 5 4 4 16 clb auto 23.2 MiB 0.01 3 12 2 3 7 61.7 MiB 0.00 0.00 0.620297 -7.93119 -0.620297 0.545 0.01 6.5504e-05 5.6164e-05 0.000543565 0.00049453 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00311117 0.00290556 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.01 0.00 -1 -1 0.00 0.00221081 0.00210995 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 2.05 vpr 61.70 MiB -1 -1 0.10 16420 1 0.10 -1 -1 30004 -1 -1 1 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63180 3 1 5 6 1 4 5 3 3 9 -1 auto 23.1 MiB 0.01 9 12 5 4 3 61.7 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.1504e-05 1.601e-05 0.000159881 0.000125763 -1 -1 -1 -1 20 10 1 53894 53894 4880.82 542.314 0.01 0.00174411 0.00161402 379 725 -1 22 1 3 3 79 69 1.8363 1.8363 -2.38182 -1.8363 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154197 0.00149823 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt index 33cdd16f53c..248d5d735f9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.57 vpr 64.32 MiB -1 -1 0.07 20096 1 0.04 -1 -1 35412 -1 -1 2 6 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65864 6 1 13 14 2 8 9 4 4 16 clb auto 25.9 MiB 0.00 15 27 4 16 7 64.3 MiB 0.00 0.00 0.876768 -3.25729 -0.876768 0.545 0.01 3.822e-05 2.8683e-05 0.0002492 0.000209176 20 18 16 107788 107788 10441.3 652.579 0.01 0.0019759 0.00167615 742 1670 -1 18 2 7 7 153 93 1.4073 0.545 -4.29789 -1.4073 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00115121 0.00108599 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.57 vpr 64.39 MiB -1 -1 0.09 20480 1 0.04 -1 -1 35548 -1 -1 1 2 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65932 2 -1 16 16 1 2 3 3 3 9 -1 auto 26.1 MiB 0.01 2 6 3 0 3 64.4 MiB 0.00 0.00 0.545 -3.815 -0.545 0.545 0.00 4.0902e-05 3.4981e-05 0.000354436 0.000323261 2 1 1 53894 53894 1178.84 130.982 0.01 0.00253626 0.00228473 283 309 -1 1 1 1 1 9 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00134392 0.00129235 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.08 vpr 61.64 MiB -1 -1 0.11 16584 1 0.10 -1 -1 31848 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63124 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.6 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 4.0075e-05 2.932e-05 0.00026592 0.0002219 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00240468 0.00215628 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00168822 0.00161939 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.11 vpr 61.76 MiB -1 -1 0.14 16908 1 0.09 -1 -1 31852 -1 -1 1 2 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63240 2 -1 16 16 1 2 3 3 3 9 -1 auto 23.3 MiB 0.01 3 6 4 0 2 61.8 MiB 0.01 0.00 0.545 -3.815 -0.545 0.545 0.01 6.1203e-05 5.2668e-05 0.000507564 0.000460754 -1 -1 -1 -1 2 1 1 53894 53894 1178.84 130.982 0.01 0.00295561 0.00280974 283 309 -1 1 1 1 1 8 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00212103 0.00204508 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt index 039f772d88f..e9d880c30a2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 11.99 vpr 255.45 MiB 0.11 36912 -1 -1 1 0.05 -1 -1 34700 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261584 6 1 13 14 2 8 9 4 4 16 clb auto 101.0 MiB 0.11 13 244.4 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000264546 0.000241337 0.00754986 0.00454282 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136677 0.00891098 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00722654 0.00593545 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 12.96 vpr 261.56 MiB 0.15 45980 -1 -1 1 0.06 -1 -1 34932 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 267836 3 1 25 26 2 8 6 4 4 16 clb auto 106.4 MiB 0.87 17 249.9 MiB 0.03 0 0.571 -8.64803 -0.571 0.557849 0.47 0.000543454 0.000488368 0.00346482 0.00253954 20 19 1 107788 107788 10441.3 652.579 0.67 0.0113116 0.00855232 742 1670 -1 27 1 6 6 63 36 0 0 63 36 6 6 0 0 9 6 0 0 9 9 0 0 6 6 0 0 18 3 0 0 15 6 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.82275 -0.865 0 0 13748.8 859.301 0.01 0.04 0.17 -1 -1 0.01 0.00501901 0.00409753 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 11.88 vpr 254.22 MiB 0.15 35980 -1 -1 1 0 -1 -1 32420 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260320 6 2 10 12 2 8 10 4 4 16 clb auto 100.4 MiB 0.06 12 243.6 MiB 0.03 0 0.544641 -1.83465 -0.544641 nan 0.47 0.000504445 0.000240584 0.00477542 0.00228264 20 15 1 107788 107788 10441.3 652.579 0.64 0.00804976 0.00416003 742 1670 -1 13 1 6 6 148 96 0 0 148 96 6 6 0 0 18 16 0 0 18 18 0 0 6 6 0 0 53 27 0 0 47 23 0 0 6 0 0 0 0 0 6 0 0 0.81248 nan -2.54321 -0.81248 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00215701 0.00121245 +k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 11.88 vpr 254.22 MiB 0.15 35980 -1 -1 1 0 -1 -1 32420 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260320 6 2 10 12 2 8 10 4 4 16 clb auto 100.4 MiB 0.06 12 243.6 MiB 0.03 0 0.544641 -1.83465 -0.544641 nan 0.47 0.000504445 0.000240584 0.00477542 0.00228264 20 27 1 107788 107788 10441.3 652.579 0.64 0.00804976 0.00416003 742 1670 -1 13 1 6 6 148 96 0 0 148 96 6 6 0 0 18 16 0 0 18 18 0 0 6 6 0 0 53 27 0 0 47 23 0 0 6 0 0 0 0 0 6 0 0 0.81248 nan -2.54321 -0.81248 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00215701 0.00121245 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/multiclock_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/multiclock_mcnc/config/golden_results.txt index dabe58c85d0..9a02931e25d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/multiclock_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/multiclock_mcnc/config/golden_results.txt @@ -1,11 +1,11 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml bigkey.blif common 5.28 -1 -1 3 0.34 -1 -1 35056 -1 -1 53 229 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 46028 229 197 1023 1220 1 510 479 16 16 256 io auto 0.21 3413 0.56 0.00 2.1735 -526.299 -2.1735 2.1735 0.39 0.00138821 0.00120378 0.19781 0.168309 40 6116 17 1.05632e+07 2.85638e+06 697968. 2726.44 2.40 0.722292 0.640772 5568 9 1309 2279 135603 31763 2.49868 2.49868 -621.799 -2.49868 0 0 870840. 3401.72 0.16 0.07 0.0510449 0.0478126 -k6_frac_N10_40nm.xml clma.blif common 5.08 -1 -1 7 2.05 -1 -1 39340 -1 -1 77 36 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 32676 36 82 542 624 1 390 195 11 11 121 clb auto 0.35 2039 0.33 0.00 4.11584 -147.948 -4.11584 4.11584 0.15 0.000539492 0.000452693 0.106625 0.0857617 40 4434 24 4.36541e+06 4.14984e+06 303235. 2506.08 1.15 0.303278 0.252285 3724 17 2001 6967 214647 45904 4.75061 4.75061 -182.205 -4.75061 0 0 379421. 3135.71 0.06 0.06 0.0359416 0.0326671 -k6_frac_N10_40nm.xml diffeq.blif common 3.20 -1 -1 8 0.40 -1 -1 34060 -1 -1 51 64 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 34940 64 39 941 980 1 450 154 10 10 100 clb auto 0.42 2664 0.24 0.00 4.29897 -783.884 -4.29897 4.29897 0.12 0.000839617 0.000669735 0.100486 0.0795009 46 5017 28 3.44922e+06 2.74859e+06 276332. 2763.32 1.05 0.326802 0.269909 4217 16 1848 5381 166684 35585 4.95374 4.95374 -932.485 -4.95374 0 0 354105. 3541.05 0.05 0.08 0.0542635 0.0494947 -k6_frac_N10_40nm.xml dsip.blif common 6.16 -1 -1 3 0.30 -1 -1 34940 -1 -1 68 229 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 47348 229 197 1135 1332 1 648 494 16 16 256 io auto 0.53 4829 0.66 0.01 2.11998 -540.899 -2.11998 2.11998 0.39 0.0015698 0.00130015 0.210921 0.176933 36 9346 20 1.05632e+07 3.66479e+06 638738. 2495.07 2.79 0.723593 0.631411 8188 14 2350 5770 322638 68924 2.64997 2.64997 -662.41 -2.64997 0 0 786978. 3074.13 0.15 0.12 0.076965 0.0713829 -k6_frac_N10_40nm.xml elliptic.blif common 10.48 -1 -1 10 1.16 -1 -1 37272 -1 -1 133 131 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 56752 131 114 2471 2585 1 967 378 14 14 196 clb auto 1.84 9009 0.83 0.01 6.26362 -3059.17 -6.26362 6.26362 0.28 0.00212795 0.00173305 0.286733 0.219064 64 15845 47 7.76074e+06 7.1679e+06 810706. 4136.26 4.27 1.22946 1.00099 14220 16 4723 20791 818717 140043 7.05815 7.05815 -3531.55 -7.05815 0 0 1.00880e+06 5146.95 0.16 0.27 0.154401 0.13779 -k6_frac_N10_40nm.xml frisc.blif common 13.84 -1 -1 12 1.91 -1 -1 37256 -1 -1 153 20 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62524 20 116 2477 2593 1 1097 289 15 15 225 clb auto 2.14 12755 0.94 0.01 6.79269 -3257.02 -6.79269 6.79269 0.34 0.00217438 0.00179657 0.327538 0.24583 76 21374 38 9.10809e+06 8.24578e+06 1.08042e+06 4801.85 6.09 1.27911 1.034 19100 16 5620 24310 1037891 171913 8.29693 8.29693 -3979.77 -8.29693 0 0 1.34805e+06 5991.31 0.22 0.35 0.179872 0.160752 -k6_frac_N10_40nm.xml s298.blif common 3.83 -1 -1 8 0.53 -1 -1 34316 -1 -1 62 4 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 34504 4 6 671 677 1 352 72 10 10 100 clb auto 0.56 3591 0.22 0.00 4.75477 -39.1418 -4.75477 4.75477 0.12 0.000769266 0.000586248 0.09084 0.0707559 52 5575 27 3.44922e+06 3.34143e+06 305142. 3051.42 1.47 0.36114 0.295188 5399 17 2374 11722 416659 74881 5.56322 5.56322 -46.7971 -5.56322 0 0 401807. 4018.07 0.06 0.11 0.0543908 0.049368 -k6_frac_N10_40nm.xml s38417.blif common 12.03 -1 -1 6 2.75 -1 -1 42360 -1 -1 177 29 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63792 29 106 3450 3556 1 1202 312 16 16 256 clb auto 1.56 8615 1.15 0.01 3.98518 -2557.22 -3.98518 3.98518 0.39 0.00302166 0.00218012 0.456703 0.332458 46 14847 24 1.05632e+07 9.53924e+06 786978. 3074.13 3.52 1.37805 1.08296 13205 15 5027 16599 520957 107073 4.83175 4.83175 -2954.7 -4.83175 0 0 1.01084e+06 3948.58 0.17 0.30 0.238471 0.215337 -k6_frac_N10_40nm.xml s38584.1.blif common 12.46 -1 -1 6 2.08 -1 -1 40804 -1 -1 194 38 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66920 38 304 3256 3560 1 1587 536 16 16 256 clb auto 1.98 10122 1.65 0.01 3.64177 -2138.5 -3.64177 3.64177 0.40 0.00317473 0.00262755 0.578661 0.434442 58 18006 25 1.05632e+07 1.04554e+07 977637. 3818.90 3.81 1.57474 1.25106 15785 16 5100 13564 505628 106920 4.7203 4.7203 -2481.9 -4.7203 0 0 1.24374e+06 4858.37 0.21 0.26 0.211794 0.191547 -k6_frac_N10_40nm.xml tseng.blif common 2.48 -1 -1 7 0.23 -1 -1 34700 -1 -1 34 52 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 31260 52 122 664 786 1 355 208 8 8 64 io clb auto 0.41 1686 0.21 0.00 3.70214 -536.987 -3.70214 3.70214 0.07 0.000641877 0.000544632 0.0739312 0.060713 58 3324 47 1.94018e+06 1.8324e+06 203254. 3175.84 0.73 0.26935 0.22784 2902 11 1075 2671 103928 28289 4.55633 4.55633 -641.099 -4.55633 0 0 258247. 4035.11 0.04 0.07 0.046514 0.0424413 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml bigkey.blif common 7.20 vpr 66.95 MiB -1 -1 -1 -1 3 0.52 -1 -1 38552 -1 -1 53 229 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68552 229 197 1023 1220 1 510 479 16 16 256 io auto 27.5 MiB 0.24 3857 159684 50415 100566 8703 66.9 MiB 0.65 0.01 2.28488 -572.083 -2.28488 2.28488 0.43 0.00217367 0.00193462 0.259289 0.232202 -1 -1 -1 -1 34 6784 36 1.05632e+07 2.85638e+06 613832. 2397.78 4.05 1.01365 0.918671 24564 122629 -1 5850 11 1312 2352 132518 32277 2.76257 2.76257 -655.553 -2.76257 0 0 751777. 2936.63 0.03 0.09 0.08 -1 -1 0.03 0.069929 0.0656002 + k6_frac_N10_40nm.xml clma.blif common 5.94 vpr 64.80 MiB -1 -1 -1 -1 7 2.23 -1 -1 42980 -1 -1 79 36 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66352 36 82 542 624 1 389 197 11 11 121 clb auto 25.3 MiB 0.48 2127 40880 16866 18710 5304 64.8 MiB 0.32 0.01 4.57111 -169.888 -4.57111 4.57111 0.20 0.00196234 0.001766 0.116536 0.103509 -1 -1 -1 -1 40 4700 26 4.36541e+06 4.25763e+06 303235. 2506.08 1.35 0.43712 0.38801 11571 60661 -1 3777 19 2230 7887 214455 46253 4.82804 4.82804 -186.1 -4.82804 0 0 379421. 3135.71 0.02 0.16 0.07 -1 -1 0.02 0.0896115 0.0822627 + k6_frac_N10_40nm.xml diffeq.blif common 2.92 vpr 66.61 MiB -1 -1 -1 -1 8 0.37 -1 -1 38160 -1 -1 52 64 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68208 64 39 941 980 1 449 155 10 10 100 clb auto 26.8 MiB 0.50 2810 15963 3441 11602 920 66.6 MiB 0.14 0.00 4.99118 -866.838 -4.99118 4.99118 0.09 0.00121728 0.00102812 0.0599001 0.0516492 -1 -1 -1 -1 46 4616 20 3.44922e+06 2.80249e+06 276332. 2763.32 0.93 0.392993 0.343157 9816 55112 -1 4188 15 1800 5546 151236 33167 5.08131 5.08131 -922.585 -5.08131 0 0 354105. 3541.05 0.01 0.11 0.04 -1 -1 0.01 0.0801531 0.0743673 + k6_frac_N10_40nm.xml dsip.blif common 8.04 vpr 68.18 MiB -1 -1 -1 -1 3 0.46 -1 -1 38252 -1 -1 68 229 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69816 229 197 1135 1332 1 648 494 16 16 256 io auto 28.6 MiB 0.85 5312 156654 46092 101923 8639 68.2 MiB 0.99 0.01 2.37422 -599.955 -2.37422 2.37422 0.49 0.00367277 0.00324389 0.347682 0.309361 -1 -1 -1 -1 36 8936 22 1.05632e+07 3.66479e+06 638738. 2495.07 3.13 1.35387 1.20985 24820 128426 -1 8053 12 2277 5560 281512 63324 2.6192 2.6192 -669.375 -2.6192 0 0 786978. 3074.13 0.05 0.25 0.18 -1 -1 0.05 0.157791 0.147117 + k6_frac_N10_40nm.xml elliptic.blif common 11.55 vpr 75.93 MiB -1 -1 -1 -1 10 1.41 -1 -1 42312 -1 -1 134 131 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 77748 131 114 2471 2585 1 965 379 14 14 196 clb auto 35.1 MiB 2.51 9456 89494 25858 59393 4243 75.9 MiB 0.77 0.01 6.79623 -3397.75 -6.79623 6.79623 0.20 0.00440022 0.00362715 0.301337 0.256198 -1 -1 -1 -1 66 15578 22 7.76074e+06 7.2218e+06 836700. 4268.88 4.49 1.74713 1.51878 22640 168496 -1 13700 18 4265 18260 614637 108468 7.3276 7.3276 -3617 -7.3276 0 0 1.03533e+06 5282.27 0.04 0.41 0.14 -1 -1 0.04 0.267713 0.242444 + k6_frac_N10_40nm.xml frisc.blif common 16.16 vpr 77.31 MiB -1 -1 -1 -1 12 2.01 -1 -1 42652 -1 -1 154 20 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79164 20 116 2477 2593 1 1095 290 15 15 225 clb auto 36.4 MiB 3.95 13105 58789 14981 39464 4344 77.3 MiB 1.35 0.02 8.00138 -3807.11 -8.00138 8.00138 0.43 0.0081328 0.00719848 0.558575 0.477365 -1 -1 -1 -1 76 21862 33 9.10809e+06 8.29968e+06 1.08042e+06 4801.85 5.74 1.98425 1.72803 27499 221939 -1 19174 16 5769 25045 1026308 173738 8.21541 8.21541 -3991.17 -8.21541 0 0 1.34805e+06 5991.31 0.05 0.46 0.18 -1 -1 0.05 0.251615 0.230637 + k6_frac_N10_40nm.xml s298.blif common 4.60 vpr 65.82 MiB -1 -1 -1 -1 8 0.82 -1 -1 37972 -1 -1 61 4 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67404 4 6 671 677 1 350 71 10 10 100 clb auto 26.5 MiB 1.11 3540 2845 401 2327 117 65.8 MiB 0.12 0.00 5.48084 -44.2852 -5.48084 5.48084 0.16 0.00206735 0.00177304 0.0590776 0.0525925 -1 -1 -1 -1 52 5763 37 3.44922e+06 3.28753e+06 305142. 3051.42 1.18 0.421351 0.369249 10212 61796 -1 5098 18 2211 10437 290027 55717 5.61219 5.61219 -47.3284 -5.61219 0 0 401807. 4018.07 0.01 0.15 0.05 -1 -1 0.01 0.0927923 0.0846279 + k6_frac_N10_40nm.xml s38417.blif common 17.91 vpr 81.74 MiB -1 -1 -1 -1 6 4.10 -1 -1 45508 -1 -1 176 29 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83700 29 106 3450 3556 1 1190 311 16 16 256 clb auto 40.6 MiB 2.62 8975 59279 14510 38832 5937 81.7 MiB 1.37 0.02 4.49038 -2868.52 -4.49038 4.49038 0.48 0.0101802 0.00890923 0.68275 0.55608 -1 -1 -1 -1 48 14949 25 1.05632e+07 9.48534e+06 819368. 3200.65 6.19 3.10939 2.62069 26860 167058 -1 13109 14 4799 16110 475247 99748 4.67678 4.67678 -2975.81 -4.67678 0 0 1.04748e+06 4091.72 0.04 0.38 0.13 -1 -1 0.04 0.295567 0.270634 + k6_frac_N10_40nm.xml s38584.1.blif common 17.99 vpr 82.03 MiB -1 -1 -1 -1 6 3.06 -1 -1 44604 -1 -1 203 38 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83996 38 304 3259 3563 1 1559 545 17 17 289 clb auto 41.0 MiB 3.38 10700 171870 46563 105348 19959 82.0 MiB 2.17 0.02 4.2184 -2435.96 -4.2184 4.2184 0.56 0.0059931 0.00531266 0.863249 0.745275 -1 -1 -1 -1 56 19548 40 1.21262e+07 1.09405e+07 1.07492e+06 3719.43 5.63 3.22677 2.77835 31923 220089 -1 16589 15 5335 14804 532142 114643 4.62993 4.62993 -2587.89 -4.62993 0 0 1.37091e+06 4743.65 0.05 0.41 0.17 -1 -1 0.05 0.315014 0.290558 + k6_frac_N10_40nm.xml tseng.blif common 3.72 vpr 64.95 MiB -1 -1 -1 -1 7 0.30 -1 -1 36976 -1 -1 33 52 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66504 52 122 664 786 1 358 207 8 8 64 io clb auto 25.4 MiB 0.60 1979 19791 3963 14597 1231 64.9 MiB 0.21 0.01 4.35959 -604.543 -4.35959 4.35959 0.09 0.00213824 0.00191283 0.0821371 0.0733419 -1 -1 -1 -1 58 3402 44 1.94018e+06 1.7785e+06 203254. 3175.84 1.42 0.631719 0.559346 6532 39661 -1 2996 15 1183 3162 100447 27815 4.60411 4.60411 -641.316 -4.60411 0 0 258247. 4035.11 0.01 0.12 0.05 -1 -1 0.01 0.0870702 0.080662 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt index b9631c0caf9..564cc8c3dc6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.22 vpr 254.93 MiB 0.1 37000 -1 -1 1 0.05 -1 -1 34808 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261052 6 1 13 14 2 8 9 4 4 16 clb auto 100.7 MiB 0.11 13 244.1 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000263443 0.000240838 0.00748415 0.00450484 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136082 0.00886525 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00739705 0.00603502 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 14.79 vpr 261.44 MiB 0.12 46076 -1 -1 1 0.05 -1 -1 34892 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 267712 3 1 25 26 2 8 6 4 4 16 clb auto 106.3 MiB 1 17 250.0 MiB 0.04 0 0.571 -8.64803 -0.571 0.557849 0.53 0.000560438 0.000505834 0.00360459 0.00262507 20 19 1 107788 107788 10441.3 652.579 0.76 0.0119539 0.00893362 742 1670 -1 27 1 6 6 63 36 0 0 63 36 6 6 0 0 9 6 0 0 9 9 0 0 6 6 0 0 18 3 0 0 15 6 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.82275 -0.865 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00502268 0.00406987 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.05 vpr 254.23 MiB 0.11 35864 -1 -1 1 0.01 -1 -1 32648 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260328 6 2 10 12 2 8 10 4 4 16 clb auto 100.4 MiB 0.06 12 243.6 MiB 0.03 0 0.544641 -1.83465 -0.544641 nan 0.47 0.000489919 0.000226814 0.00463432 0.00218307 20 15 1 107788 107788 10441.3 652.579 0.64 0.00773058 0.00396899 742 1670 -1 13 1 6 6 148 96 0 0 148 96 6 6 0 0 18 16 0 0 18 18 0 0 6 6 0 0 53 27 0 0 47 23 0 0 6 0 0 0 0 0 6 0 0 0.81248 nan -2.54321 -0.81248 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00224126 0.00124363 +k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.05 vpr 254.23 MiB 0.11 35864 -1 -1 1 0.01 -1 -1 32648 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260328 6 2 10 12 2 8 10 4 4 16 clb auto 100.4 MiB 0.06 12 243.6 MiB 0.03 0 0.544641 -1.83465 -0.544641 nan 0.47 0.000489919 0.000226814 0.00463432 0.00218307 20 27 1 107788 107788 10441.3 652.579 0.64 0.00773058 0.00396899 742 1670 -1 13 1 6 6 148 96 0 0 148 96 6 6 0 0 18 16 0 0 18 18 0 0 6 6 0 0 53 27 0 0 47 23 0 0 6 0 0 0 0 0 6 0 0 0.81248 nan -2.54321 -0.81248 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00224126 0.00124363 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/task_list.txt index 5c3e9b08ebb..53cfaf40acf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/task_list.txt @@ -1,5 +1,5 @@ regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket -regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket_odin +regression_tests/vtr_reg_multiclock_odin/func_multiclock/multiclock_mcnc regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative regression_tests/vtr_reg_multiclock_odin/func_multiclock/once regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt index 5c9945e3546..99080e3a8c6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt @@ -1,211 +1,211 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_004bits.v common 2.74 vpr 60.62 MiB -1 -1 0.15 17236 2 0.06 -1 -1 31940 -1 -1 2 9 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62076 9 5 28 33 1 21 16 17 17 289 -1 unnamed_device 22.0 MiB 0.01 135 76 35 40 1 60.6 MiB 0.00 0.00 0.900447 -11.7037 -0.900447 0.900447 0.66 8.645e-05 7.8124e-05 0.000583333 0.000531116 20 236 9 6.55708e+06 24110 394039. 1363.46 0.45 0.00366263 0.00324976 19870 87366 -1 236 7 61 67 5096 1298 0.83871 0.83871 -12.1586 -0.83871 0 0 477104. 1650.88 0.14 0.01 0.08 -1 -1 0.14 0.00258961 0.00232587 13 6 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 2.94 vpr 60.76 MiB -1 -1 0.14 17160 2 0.06 -1 -1 32004 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62220 11 6 34 40 1 24 19 17 17 289 -1 unnamed_device 22.1 MiB 0.01 55 569 131 359 79 60.8 MiB 0.01 0.00 0.900447 -11.5834 -0.900447 0.900447 0.65 0.00010434 9.5102e-05 0.00271084 0.00247011 26 205 12 6.55708e+06 24110 477104. 1650.88 0.56 0.0146662 0.0123484 21022 109990 -1 188 9 116 121 5329 1929 0.819447 0.819447 -12.7928 -0.819447 0 0 585099. 2024.56 0.17 0.01 0.10 -1 -1 0.17 0.00323617 0.00286903 16 7 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 2.81 vpr 60.62 MiB -1 -1 0.16 17216 3 0.05 -1 -1 31852 -1 -1 3 13 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62072 13 7 41 48 1 32 23 17 17 289 -1 unnamed_device 22.0 MiB 0.02 85 567 111 433 23 60.6 MiB 0.01 0.00 1.58811 -16.0101 -1.58811 1.58811 0.66 0.000125009 0.000114627 0.00264833 0.00243277 20 282 10 6.55708e+06 36165 394039. 1363.46 0.45 0.00862391 0.00785706 19870 87366 -1 238 10 108 128 6200 1949 1.50711 1.50711 -17.0526 -1.50711 0 0 477104. 1650.88 0.14 0.01 0.08 -1 -1 0.14 0.00386995 0.00340331 19 9 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 2.81 vpr 60.71 MiB -1 -1 0.15 17060 3 0.05 -1 -1 31872 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62172 15 8 47 55 1 38 26 17 17 289 -1 unnamed_device 22.0 MiB 0.01 208 862 165 657 40 60.7 MiB 0.01 0.00 1.23151 -19.784 -1.23151 1.23151 0.67 0.000144141 0.000132564 0.00370168 0.00340074 20 451 13 6.55708e+06 36165 394039. 1363.46 0.45 0.00903024 0.00801953 19870 87366 -1 409 8 146 164 9675 2532 1.05785 1.05785 -21.0828 -1.05785 0 0 477104. 1650.88 0.14 0.01 0.08 -1 -1 0.14 0.00383752 0.00340253 23 10 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 3.01 vpr 60.81 MiB -1 -1 0.12 17156 3 0.05 -1 -1 31920 -1 -1 4 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62268 17 9 56 65 1 42 30 17 17 289 -1 unnamed_device 22.1 MiB 0.05 126 720 180 518 22 60.8 MiB 0.01 0.00 1.70831 -21.3388 -1.70831 1.70831 0.67 0.000172392 0.000158744 0.00325091 0.00300139 26 341 10 6.55708e+06 48220 477104. 1650.88 0.58 0.0213417 0.017943 21022 109990 -1 308 11 131 145 7970 2470 1.58811 1.58811 -22.2734 -1.58811 0 0 585099. 2024.56 0.17 0.01 0.10 -1 -1 0.17 0.00523909 0.004569 25 14 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 3.13 vpr 61.11 MiB -1 -1 0.14 17116 4 0.05 -1 -1 31968 -1 -1 4 19 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62576 19 10 60 70 1 48 33 17 17 289 -1 unnamed_device 22.4 MiB 0.02 138 1593 371 925 297 61.1 MiB 0.02 0.00 1.58811 -24.9956 -1.58811 1.58811 0.66 0.00018571 0.000171683 0.00622386 0.00574361 30 399 18 6.55708e+06 48220 526063. 1820.29 0.66 0.0278424 0.0236006 21886 126133 -1 284 8 179 216 8061 2693 1.50711 1.50711 -23.7908 -1.50711 0 0 666494. 2306.21 0.19 0.01 0.11 -1 -1 0.19 0.00473893 0.0041935 29 13 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 4.03 vpr 60.91 MiB -1 -1 0.16 17260 4 0.06 -1 -1 31804 -1 -1 5 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62372 21 11 69 80 1 54 37 17 17 289 -1 unnamed_device 22.4 MiB 0.06 171 2965 791 1478 696 60.9 MiB 0.02 0.00 1.74751 -28.6395 -1.74751 1.74751 0.67 0.000207694 0.000192004 0.0107634 0.00994613 22 811 29 6.55708e+06 60275 420624. 1455.45 1.56 0.0517123 0.0436832 20158 92377 -1 540 10 251 342 20280 6103 1.62731 1.62731 -31.7476 -1.62731 0 0 500653. 1732.36 0.15 0.02 0.09 -1 -1 0.15 0.00574609 0.00502617 33 17 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 3.14 vpr 60.95 MiB -1 -1 0.16 17272 5 0.06 -1 -1 31920 -1 -1 6 23 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62412 23 12 76 88 1 61 41 17 17 289 -1 unnamed_device 22.4 MiB 0.02 238 4031 1480 1575 976 60.9 MiB 0.03 0.00 2.07857 -33.1668 -2.07857 2.07857 0.71 0.000224038 0.00020653 0.0136882 0.0126411 28 584 15 6.55708e+06 72330 500653. 1732.36 0.63 0.0387169 0.0335188 21310 115450 -1 529 13 230 289 18701 4954 1.7455 1.7455 -33.8966 -1.7455 0 0 612192. 2118.31 0.18 0.02 0.10 -1 -1 0.18 0.00707647 0.00615885 37 19 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.05 vpr 60.94 MiB -1 -1 0.17 17472 5 0.06 -1 -1 31972 -1 -1 6 25 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62400 25 13 83 96 1 66 44 17 17 289 -1 unnamed_device 22.5 MiB 0.02 377 3894 1439 2026 429 60.9 MiB 0.03 0.00 1.80097 -39.3305 -1.80097 1.80097 0.67 0.000245713 0.000227127 0.0131117 0.0121218 26 788 14 6.55708e+06 72330 477104. 1650.88 0.61 0.0394861 0.0342105 21022 109990 -1 751 16 314 450 35118 8247 1.77504 1.77504 -42.0175 -1.77504 0 0 585099. 2024.56 0.17 0.02 0.10 -1 -1 0.17 0.00872282 0.0075648 40 21 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.30 vpr 61.05 MiB -1 -1 0.12 17516 5 0.06 -1 -1 31788 -1 -1 7 27 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62520 27 14 91 105 1 70 48 17 17 289 -1 unnamed_device 22.5 MiB 0.02 268 2832 643 1749 440 61.1 MiB 0.02 0.00 1.74751 -36.363 -1.74751 1.74751 0.74 0.000271359 0.000251479 0.00969306 0.00898067 26 762 34 6.55708e+06 84385 477104. 1650.88 0.71 0.0479897 0.0409888 21022 109990 -1 661 16 290 427 42857 13493 1.53665 1.53665 -38.6649 -1.53665 0 0 585099. 2024.56 0.17 0.03 0.10 -1 -1 0.17 0.00953989 0.00824962 42 24 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 3.13 vpr 61.13 MiB -1 -1 0.16 17524 6 0.06 -1 -1 32148 -1 -1 7 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62600 29 15 95 110 1 74 51 17 17 289 -1 unnamed_device 22.6 MiB 0.04 461 5503 1446 3252 805 61.1 MiB 0.04 0.00 2.47436 -49.4238 -2.47436 2.47436 0.66 0.000279667 0.000258883 0.0172866 0.0160272 26 940 26 6.55708e+06 84385 477104. 1650.88 0.64 0.0530306 0.0459924 21022 109990 -1 852 12 295 406 27209 6503 2.23396 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62628 37 19 127 146 1 99 66 17 17 289 -1 unnamed_device 22.5 MiB 0.03 520 5519 1325 3449 745 61.2 MiB 0.04 0.00 3.12482 -68.231 -3.12482 3.12482 0.66 0.000366828 0.000340613 0.0162433 0.0150584 28 1061 11 6.55708e+06 120550 500653. 1732.36 0.65 0.0541799 0.0472377 21310 115450 -1 962 9 299 403 23764 6046 2.79176 2.79176 -68.6483 -2.79176 0 0 612192. 2118.31 0.18 0.03 0.10 -1 -1 0.18 0.0101929 0.00901767 59 35 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 3.22 vpr 61.16 MiB -1 -1 0.17 17408 8 0.06 -1 -1 32016 -1 -1 11 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62632 41 21 139 160 1 110 73 17 17 289 -1 unnamed_device 22.5 MiB 0.05 468 9497 2136 5919 1442 61.2 MiB 0.06 0.00 3.11516 -75.6589 -3.11516 3.11516 0.65 0.000398342 0.000369999 0.0261698 0.0243142 26 1200 13 6.55708e+06 132605 477104. 1650.88 0.68 0.0685837 0.0604621 21022 109990 -1 1055 11 406 541 31085 8462 2.9023 2.9023 -77.3553 -2.9023 0 0 585099. 2024.56 0.17 0.03 0.10 -1 -1 0.17 0.0106512 0.00938817 67 37 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 4.89 vpr 61.29 MiB -1 -1 0.18 17472 9 0.07 -1 -1 31956 -1 -1 13 45 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62760 45 23 153 176 1 123 81 17 17 289 -1 unnamed_device 22.5 MiB 0.21 636 10406 4261 6108 37 61.3 MiB 0.06 0.00 3.15236 -84.0115 -3.15236 3.15236 0.66 0.000433887 0.000402031 0.0271458 0.0251881 30 1243 13 6.55708e+06 156715 526063. 1820.29 2.09 0.137701 0.119279 21886 126133 -1 1121 13 401 514 24209 6555 3.0597 3.0597 -84.1453 -3.0597 0 0 666494. 2306.21 0.19 0.03 0.11 -1 -1 0.19 0.0126038 0.0110916 74 41 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 4.96 vpr 61.43 MiB -1 -1 0.19 17552 10 0.07 -1 -1 31968 -1 -1 12 49 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62904 49 25 166 191 1 129 86 17 17 289 -1 unnamed_device 22.7 MiB 0.09 684 7457 1697 4897 863 61.4 MiB 0.05 0.00 3.70816 -98.1534 -3.70816 3.70816 0.65 0.000469331 0.000436345 0.0199461 0.0185434 28 1493 34 6.55708e+06 144660 500653. 1732.36 2.28 0.135027 0.1168 21310 115450 -1 1272 12 423 577 35128 9092 3.58796 3.58796 -99.0644 -3.58796 0 0 612192. 2118.31 0.18 0.03 0.10 -1 -1 0.18 0.0133462 0.0118212 79 44 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 4.88 vpr 61.52 MiB -1 -1 0.16 17464 11 0.08 -1 -1 32180 -1 -1 14 57 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62992 57 29 198 227 1 159 100 17 17 289 -1 unnamed_device 23.0 MiB 0.18 886 14020 4097 8043 1880 61.5 MiB 0.08 0.00 4.12928 -123.627 -4.12928 4.12928 0.66 0.000569495 0.00052983 0.0360377 0.0335206 28 1846 13 6.55708e+06 168770 500653. 1732.36 2.10 0.162815 0.142082 21310 115450 -1 1677 11 546 710 49330 11707 3.87722 3.87722 -125.497 -3.87722 0 0 612192. 2118.31 0.18 0.04 0.10 -1 -1 0.18 0.0155799 0.013858 93 56 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 3.79 vpr 61.71 MiB -1 -1 0.21 17756 13 0.08 -1 -1 32116 -1 -1 16 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63188 65 33 224 257 1 180 114 17 17 289 -1 unnamed_device 23.1 MiB 0.22 826 13362 2721 10353 288 61.7 MiB 0.08 0.00 4.35602 -142.897 -4.35602 4.35602 0.65 0.000640239 0.000596542 0.032983 0.0307208 30 1923 15 6.55708e+06 192880 526063. 1820.29 0.88 0.103373 0.0916773 21886 126133 -1 1661 11 677 907 51084 13514 4.02296 4.02296 -140.256 -4.02296 0 0 666494. 2306.21 0.19 0.04 0.11 -1 -1 0.19 0.0164996 0.0146991 107 62 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 6.46 vpr 62.64 MiB -1 -1 0.26 18136 19 0.10 -1 -1 32292 -1 -1 24 97 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64144 97 49 340 389 1 266 170 17 17 289 -1 unnamed_device 23.5 MiB 0.21 1319 34480 11756 18994 3730 62.6 MiB 0.17 0.00 7.55025 -291.095 -7.55025 7.55025 0.66 0.000977538 0.000912289 0.0748882 0.0698031 36 2772 30 6.55708e+06 289320 612192. 2118.31 3.26 0.332618 0.296208 22750 144809 -1 2396 20 939 1325 112348 38851 6.97679 6.97679 -283.59 -6.97679 0 0 782063. 2706.10 0.21 0.08 0.13 -1 -1 0.21 0.0382111 0.0340511 161 98 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 5.00 vpr 63.37 MiB -1 -1 0.29 18284 26 0.10 -1 -1 32564 -1 -1 35 129 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64892 129 65 453 518 1 353 229 17 17 289 -1 unnamed_device 24.3 MiB 0.18 1825 50629 14926 30325 5378 63.4 MiB 0.24 0.00 10.2543 -489.043 -10.2543 10.2543 0.66 0.00132504 0.00123931 0.0996393 0.0931935 36 3634 13 6.55708e+06 421925 612192. 2118.31 1.66 0.352251 0.318118 22750 144809 -1 3317 12 1246 1770 111506 27954 9.31476 9.31476 -453.748 -9.31476 0 0 782063. 2706.10 0.21 0.08 0.13 -1 -1 0.21 0.0355162 0.0321623 213 131 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.56 abc 29.24 MiB -1 -1 0.14 17208 1 0.02 -1 -1 29944 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22848 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.56 abc 29.38 MiB -1 -1 0.11 17212 1 0.02 -1 -1 30084 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23212 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.54 abc 29.30 MiB -1 -1 0.13 17256 1 0.03 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23236 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.59 abc 29.38 MiB -1 -1 0.14 17256 1 0.02 -1 -1 30084 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22880 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.56 abc 29.37 MiB -1 -1 0.15 17124 1 0.02 -1 -1 30076 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23256 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.72 abc 29.29 MiB -1 -1 0.15 17228 1 0.03 -1 -1 29992 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22924 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.57 abc 29.33 MiB -1 -1 0.15 17228 1 0.03 -1 -1 30036 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23016 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.55 abc 29.37 MiB -1 -1 0.14 17056 1 0.02 -1 -1 30076 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23104 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.61 abc 29.31 MiB -1 -1 0.16 17212 1 0.02 -1 -1 30012 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23048 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.50 abc 29.54 MiB -1 -1 0.16 17304 1 0.02 -1 -1 30252 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23076 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.53 abc 29.37 MiB -1 -1 0.15 17292 1 0.02 -1 -1 30072 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23160 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.59 abc 29.30 MiB -1 -1 0.14 17224 1 0.03 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23064 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.57 abc 29.26 MiB -1 -1 0.17 17484 1 0.03 -1 -1 29964 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23044 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.50 abc 29.45 MiB -1 -1 0.14 17468 1 0.02 -1 -1 30152 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23228 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.56 abc 29.38 MiB -1 -1 0.14 17516 1 0.03 -1 -1 30088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23304 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.61 abc 29.27 MiB -1 -1 0.17 17408 1 0.03 -1 -1 29968 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23272 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.60 abc 29.45 MiB -1 -1 0.16 17440 1 0.03 -1 -1 30152 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23312 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.58 abc 29.36 MiB -1 -1 0.15 17364 1 0.03 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23572 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.62 abc 29.35 MiB -1 -1 0.17 17468 1 0.03 -1 -1 30052 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23328 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.50 abc 29.47 MiB -1 -1 0.12 17572 1 0.03 -1 -1 30176 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23700 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.68 abc 29.56 MiB -1 -1 0.20 17916 1 0.03 -1 -1 30272 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23988 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.48 abc 29.23 MiB -1 -1 0.10 17228 1 0.02 -1 -1 29928 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22800 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.54 abc 29.25 MiB -1 -1 0.14 17220 1 0.02 -1 -1 29952 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22588 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.57 abc 29.28 MiB -1 -1 0.13 17148 1 0.02 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22676 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.54 abc 29.30 MiB -1 -1 0.17 17192 1 0.02 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22740 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.56 abc 29.44 MiB -1 -1 0.15 17124 1 0.02 -1 -1 30148 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22664 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.55 abc 29.33 MiB -1 -1 0.15 17256 1 0.02 -1 -1 30032 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22620 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.56 abc 29.45 MiB -1 -1 0.14 17268 1 0.02 -1 -1 30156 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22640 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.49 abc 29.52 MiB -1 -1 0.07 17312 1 0.02 -1 -1 30232 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22884 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.59 abc 29.30 MiB -1 -1 0.16 17268 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22736 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.49 abc 29.35 MiB -1 -1 0.12 17312 1 0.02 -1 -1 30052 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22704 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.58 abc 29.40 MiB -1 -1 0.16 17208 1 0.02 -1 -1 30104 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22772 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.58 abc 29.38 MiB -1 -1 0.14 17612 1 0.02 -1 -1 30088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22948 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.47 abc 29.18 MiB -1 -1 0.15 17276 1 0.02 -1 -1 29880 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22728 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.57 abc 29.36 MiB -1 -1 0.14 17456 1 0.03 -1 -1 30064 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22852 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.58 abc 29.39 MiB -1 -1 0.16 17524 1 0.03 -1 -1 30100 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22860 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.54 abc 29.34 MiB -1 -1 0.15 17312 1 0.03 -1 -1 30044 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22936 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.60 abc 29.52 MiB -1 -1 0.16 17260 1 0.02 -1 -1 30228 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23004 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.57 abc 29.36 MiB -1 -1 0.16 17356 1 0.02 -1 -1 30064 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23028 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.63 abc 29.34 MiB -1 -1 0.16 17376 1 0.02 -1 -1 30040 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23240 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.71 abc 29.41 MiB -1 -1 0.18 17680 1 0.03 -1 -1 30120 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23440 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.64 abc 29.86 MiB -1 -1 0.20 17752 1 0.03 -1 -1 30572 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23736 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 3.80 vpr 61.16 MiB -1 -1 0.15 17284 1 0.02 -1 -1 29968 -1 -1 2 9 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62628 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 22.5 MiB 0.01 43 476 113 309 54 61.2 MiB 0.01 0.00 0.792048 -9.40096 -0.792048 0.792048 0.66 8.7514e-05 7.9344e-05 0.00236896 0.00214809 20 127 14 6.64007e+06 25116 394039. 1363.46 1.51 0.0133243 0.0111289 20530 87850 -1 129 9 85 85 5128 1673 0.901248 0.901248 -10.0628 -0.901248 0 0 477104. 1650.88 0.16 0.01 0.05 -1 -1 0.16 0.00289847 0.00258414 13 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 2.98 vpr 61.02 MiB -1 -1 0.15 17248 1 0.02 -1 -1 29876 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62480 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 22.4 MiB 0.01 57 869 279 533 57 61.0 MiB 0.01 0.00 0.803048 -11.5224 -0.803048 0.803048 0.66 0.00010455 9.5432e-05 0.00399114 0.0036423 26 182 43 6.64007e+06 25116 477104. 1650.88 0.59 0.0206078 0.0172257 21682 110474 -1 164 18 158 158 7451 2508 0.923248 0.923248 -12.587 -0.923248 0 0 585099. 2024.56 0.21 0.01 0.10 -1 -1 0.21 0.00462477 0.00398154 16 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 3.00 vpr 61.17 MiB -1 -1 0.13 17144 1 0.02 -1 -1 30000 -1 -1 4 13 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62640 13 7 48 49 1 32 24 17 17 289 -1 unnamed_device 22.5 MiB 0.01 117 1010 285 572 153 61.2 MiB 0.01 0.00 0.825048 -14.462 -0.825048 0.825048 0.66 0.000118471 0.000108009 0.00392714 0.00358242 26 316 12 6.64007e+06 50232 477104. 1650.88 0.58 0.0175211 0.0147768 21682 110474 -1 281 13 146 146 9424 2462 1.05445 1.05445 -17.1111 -1.05445 0 0 585099. 2024.56 0.17 0.01 0.13 -1 -1 0.17 0.00429923 0.00374286 20 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 2.99 vpr 61.23 MiB -1 -1 0.14 17292 1 0.02 -1 -1 30004 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62700 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 22.5 MiB 0.02 110 1508 446 794 268 61.2 MiB 0.01 0.00 1.18536 -16.9991 -1.18536 1.18536 0.66 0.000140568 0.000128858 0.00601152 0.00552509 26 285 13 6.64007e+06 37674 477104. 1650.88 0.63 0.0217539 0.0185572 21682 110474 -1 258 15 160 160 10027 2964 1.09645 1.09645 -19.1204 -1.09645 0 0 585099. 2024.56 0.17 0.01 0.10 -1 -1 0.17 0.00522504 0.00451674 22 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 3.12 vpr 61.25 MiB -1 -1 0.14 17264 1 0.02 -1 -1 29992 -1 -1 4 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62716 17 9 62 63 1 41 30 17 17 289 -1 unnamed_device 22.6 MiB 0.02 120 1870 496 982 392 61.2 MiB 0.02 0.00 1.19636 -19.4451 -1.19636 1.19636 0.66 0.000157592 0.000145272 0.00695102 0.00639888 32 282 10 6.64007e+06 50232 554710. 1919.41 0.66 0.0236195 0.0202305 22834 132086 -1 266 11 163 163 7509 2385 0.987248 0.987248 -20.6018 -0.987248 0 0 701300. 2426.64 0.20 0.01 0.14 -1 -1 0.20 0.00477563 0.00418139 25 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 2.91 vpr 61.45 MiB -1 -1 0.12 17204 1 0.02 -1 -1 30068 -1 -1 4 19 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62920 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 23.0 MiB 0.02 130 2165 691 1177 297 61.4 MiB 0.02 0.00 1.20736 -22.2309 -1.20736 1.20736 0.66 0.000174873 0.00016127 0.00782606 0.00722942 30 316 17 6.64007e+06 50232 526063. 1820.29 0.64 0.0282901 0.0242219 22546 126617 -1 254 13 166 166 8480 2498 0.943248 0.943248 -21.1902 -0.943248 0 0 666494. 2306.21 0.19 0.02 0.12 -1 -1 0.19 0.00568189 0.00493208 28 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 3.07 vpr 61.39 MiB -1 -1 0.12 17240 1 0.03 -1 -1 30136 -1 -1 5 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62868 21 11 76 77 1 49 37 17 17 289 -1 unnamed_device 22.9 MiB 0.03 165 2599 732 1310 557 61.4 MiB 0.02 0.00 1.21836 -25.3249 -1.21836 1.21836 0.69 0.000193189 0.000178691 0.00881087 0.00813973 26 421 16 6.64007e+06 62790 477104. 1650.88 0.60 0.0307987 0.0263916 21682 110474 -1 398 14 218 218 16639 4369 1.10745 1.10745 -27.6146 -1.10745 0 0 585099. 2024.56 0.17 0.02 0.10 -1 -1 0.17 0.00642337 0.00555372 31 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 3.09 vpr 61.24 MiB -1 -1 0.10 17368 1 0.02 -1 -1 30052 -1 -1 5 23 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62712 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 22.7 MiB 0.03 164 2828 891 1242 695 61.2 MiB 0.02 0.00 1.22936 -27.5958 -1.22936 1.22936 0.66 0.000210126 0.000194466 0.00937181 0.00868417 30 486 22 6.64007e+06 62790 526063. 1820.29 0.67 0.0349793 0.0299751 22546 126617 -1 367 11 239 239 12208 3632 1.12945 1.12945 -28.0041 -1.12945 0 0 666494. 2306.21 0.19 0.02 0.11 -1 -1 0.19 0.00589239 0.00513321 34 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.12 vpr 61.24 MiB -1 -1 0.12 17196 1 0.02 -1 -1 30092 -1 -1 5 25 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62708 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 22.8 MiB 0.05 222 3193 974 1551 668 61.2 MiB 0.02 0.00 1.24036 -30.5145 -1.24036 1.24036 0.66 0.000206241 0.000189613 0.0101926 0.00944232 32 527 13 6.64007e+06 62790 554710. 1919.41 0.68 0.0366008 0.0318265 22834 132086 -1 447 16 229 229 13941 3724 1.00925 1.00925 -30.3671 -1.00925 0 0 701300. 2426.64 0.20 0.02 0.12 -1 -1 0.20 0.00782296 0.00672908 37 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.22 vpr 61.45 MiB -1 -1 0.14 17216 1 0.02 -1 -1 30064 -1 -1 6 27 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62920 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 23.0 MiB 0.03 213 3743 1348 1918 477 61.4 MiB 0.03 0.00 1.25136 -33.0163 -1.25136 1.25136 0.72 0.000237901 0.000220345 0.0112493 0.0104016 30 584 22 6.64007e+06 75348 526063. 1820.29 0.68 0.0400304 0.0344975 22546 126617 -1 463 18 358 358 22591 6437 0.934248 0.934248 -31.8611 -0.934248 0 0 666494. 2306.21 0.19 0.03 0.11 -1 -1 0.19 0.0112772 0.00977003 40 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 3.16 vpr 61.38 MiB -1 -1 0.14 17212 1 0.02 -1 -1 29984 -1 -1 7 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62852 29 15 104 105 1 73 51 17 17 289 -1 unnamed_device 22.8 MiB 0.02 274 4093 1352 1973 768 61.4 MiB 0.03 0.00 1.26236 -36.4784 -1.26236 1.26236 0.66 0.000251147 0.000232594 0.0117031 0.0108389 28 654 15 6.64007e+06 87906 500653. 1732.36 0.72 0.0405765 0.0351595 21970 115934 -1 549 10 281 281 17248 4733 1.04225 1.04225 -36.7874 -1.04225 0 0 612192. 2118.31 0.18 0.02 0.11 -1 -1 0.18 0.00651327 0.00572868 44 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 3.20 vpr 61.29 MiB -1 -1 0.15 17164 1 0.02 -1 -1 30276 -1 -1 7 31 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62756 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 22.8 MiB 0.03 288 4848 1950 2799 99 61.3 MiB 0.03 0.00 1.62267 -39.6749 -1.62267 1.62267 0.65 0.000271475 0.000251522 0.0137149 0.0127063 32 617 15 6.64007e+06 87906 554710. 1919.41 0.70 0.0433545 0.037688 22834 132086 -1 575 13 332 332 22282 5973 1.08425 1.08425 -39.233 -1.08425 0 0 701300. 2426.64 0.20 0.02 0.12 -1 -1 0.20 0.0081444 0.00711377 46 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 3.18 vpr 61.52 MiB -1 -1 0.11 17260 1 0.02 -1 -1 30136 -1 -1 7 33 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62992 33 17 118 119 1 82 57 17 17 289 -1 unnamed_device 23.0 MiB 0.03 322 6597 2432 2696 1469 61.5 MiB 0.04 0.00 1.63367 -43.7768 -1.63367 1.63367 0.66 0.000292255 0.000270622 0.018541 0.017196 32 754 18 6.64007e+06 87906 554710. 1919.41 0.71 0.0556481 0.0485561 22834 132086 -1 622 14 383 383 25542 6916 1.09525 1.09525 -42.2648 -1.09525 0 0 701300. 2426.64 0.20 0.02 0.12 -1 -1 0.20 0.0090182 0.00784311 49 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 3.22 vpr 61.57 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30072 -1 -1 8 37 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63048 37 19 132 133 1 90 64 17 17 289 -1 unnamed_device 23.0 MiB 0.04 339 6795 2758 3901 136 61.6 MiB 0.05 0.00 1.66184 -49.3449 -1.66184 1.66184 0.66 0.000328879 0.000305453 0.0186569 0.0173502 30 877 21 6.64007e+06 100464 526063. 1820.29 0.72 0.0534963 0.046625 22546 126617 -1 725 16 455 455 38637 11330 1.11845 1.11845 -47.0517 -1.11845 0 0 666494. 2306.21 0.19 0.03 0.11 -1 -1 0.19 0.0110638 0.00958809 55 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 3.29 vpr 61.68 MiB -1 -1 0.16 17352 1 0.03 -1 -1 30360 -1 -1 8 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63160 41 21 146 147 1 102 70 17 17 289 -1 unnamed_device 23.0 MiB 0.04 391 7990 3267 4602 121 61.7 MiB 0.05 0.00 1.67767 -55.9871 -1.67767 1.67767 0.65 0.000358075 0.000332611 0.0210013 0.0195326 30 1076 48 6.64007e+06 100464 526063. 1820.29 0.77 0.0781432 0.0678559 22546 126617 -1 826 17 556 556 45036 11307 1.25945 1.25945 -54.9829 -1.25945 0 0 666494. 2306.21 0.19 0.03 0.11 -1 -1 0.19 0.0125554 0.0108745 61 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 3.36 vpr 61.55 MiB -1 -1 0.17 17408 1 0.02 -1 -1 30468 -1 -1 10 45 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63024 45 23 160 161 1 114 78 17 17 289 -1 unnamed_device 22.9 MiB 0.03 547 9208 3773 5318 117 61.5 MiB 0.06 0.00 1.69967 -63.665 -1.69967 1.69967 0.66 0.000390372 0.000363778 0.0228801 0.0212812 32 1215 20 6.64007e+06 125580 554710. 1919.41 0.75 0.068449 0.0601539 22834 132086 -1 988 17 576 576 45950 11224 1.17345 1.17345 -60.6848 -1.17345 0 0 701300. 2426.64 0.20 0.04 0.12 -1 -1 0.20 0.0135273 0.0117909 68 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 3.30 vpr 61.69 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30488 -1 -1 10 49 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63172 49 25 174 175 1 123 84 17 17 289 -1 unnamed_device 23.0 MiB 0.04 529 5574 1023 4232 319 61.7 MiB 0.04 0.00 2.07098 -70.8466 -2.07098 2.07098 0.66 0.000421093 0.000392253 0.0140061 0.0130568 30 1206 16 6.64007e+06 125580 526063. 1820.29 0.75 0.0609755 0.053322 22546 126617 -1 1033 12 520 520 32652 8716 1.31245 1.31245 -69.5843 -1.31245 0 0 666494. 2306.21 0.19 0.03 0.11 -1 -1 0.19 0.011216 0.00987288 73 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 3.41 vpr 62.00 MiB -1 -1 0.13 17528 1 0.02 -1 -1 30020 -1 -1 11 57 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63488 57 29 202 203 1 143 97 17 17 289 -1 unnamed_device 23.3 MiB 0.04 688 14749 3296 10627 826 62.0 MiB 0.08 0.00 2.11498 -86.7749 -2.11498 2.11498 0.68 0.000485921 0.00045307 0.0336544 0.0313608 32 1653 15 6.64007e+06 138138 554710. 1919.41 0.76 0.0862939 0.0768333 22834 132086 -1 1374 14 675 675 48554 12572 1.43265 1.43265 -84.9238 -1.43265 0 0 701300. 2426.64 0.20 0.04 0.12 -1 -1 0.20 0.0143687 0.0126195 85 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 3.52 vpr 62.02 MiB -1 -1 0.16 17364 1 0.03 -1 -1 30016 -1 -1 13 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63508 65 33 230 231 1 164 111 17 17 289 -1 unnamed_device 23.4 MiB 0.03 791 18731 4146 13545 1040 62.0 MiB 0.10 0.00 2.50829 -102.158 -2.50829 2.50829 0.66 0.000568801 0.000530582 0.0416036 0.0388114 32 1849 21 6.64007e+06 163254 554710. 1919.41 0.82 0.107446 0.0958091 22834 132086 -1 1541 21 798 798 73275 21259 1.30145 1.30145 -92.1899 -1.30145 0 0 701300. 2426.64 0.20 0.06 0.12 -1 -1 0.20 0.022426 0.0196464 97 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.77 vpr 62.88 MiB -1 -1 0.19 17720 1 0.03 -1 -1 30268 -1 -1 19 97 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64384 97 49 342 343 1 246 165 17 17 289 -1 unnamed_device 24.0 MiB 0.06 1480 31353 9242 19771 2340 62.9 MiB 0.18 0.00 3.38291 -181.53 -3.38291 3.38291 0.66 0.000869775 0.000815118 0.0622449 0.0583122 32 3008 21 6.64007e+06 238602 554710. 1919.41 0.89 0.16522 0.149537 22834 132086 -1 2560 16 1013 1013 92739 21618 1.53945 1.53945 -150.326 -1.53945 0 0 701300. 2426.64 0.21 0.08 0.12 -1 -1 0.21 0.0315009 0.028471 145 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 4.23 vpr 63.48 MiB -1 -1 0.21 17928 1 0.03 -1 -1 30708 -1 -1 25 129 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65000 129 65 454 455 1 328 219 17 17 289 -1 unnamed_device 24.3 MiB 0.08 2038 51621 17664 30557 3400 63.5 MiB 0.30 0.01 4.25753 -269.429 -4.25753 4.25753 0.66 0.00121076 0.00113937 0.0979391 0.0921344 32 3930 16 6.64007e+06 313950 554710. 1919.41 1.00 0.232884 0.213016 22834 132086 -1 3494 21 1388 1388 126838 29064 1.83045 1.83045 -210.947 -1.83045 0 0 701300. 2426.64 0.20 0.11 0.12 -1 -1 0.20 0.0468537 0.0421696 193 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 2.77 vpr 60.86 MiB -1 -1 0.08 17284 1 0.02 -1 -1 29916 -1 -1 2 9 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62324 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 22.2 MiB 0.01 41 456 116 304 36 60.9 MiB 0.01 0.00 0.781048 -9.22036 -0.781048 0.781048 0.66 0.000104203 9.5767e-05 0.00233402 0.00212179 26 126 10 6.65987e+06 25356 477104. 1650.88 0.50 0.00819264 0.00695085 21682 110474 -1 107 6 56 56 2239 782 0.71851 0.71851 -8.88158 -0.71851 0 0 585099. 2024.56 0.17 0.01 0.10 -1 -1 0.17 0.00252282 0.00228879 13 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 2.90 vpr 61.00 MiB -1 -1 0.15 17288 1 0.02 -1 -1 29916 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62460 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 22.3 MiB 0.01 72 1094 334 508 252 61.0 MiB 0.01 0.00 0.803048 -11.753 -0.803048 0.803048 0.66 0.000105682 9.6175e-05 0.00493217 0.00449786 26 213 10 6.65987e+06 25356 477104. 1650.88 0.57 0.0165703 0.014106 21682 110474 -1 158 11 121 121 5746 1754 0.912248 0.912248 -12.0702 -0.912248 0 0 585099. 2024.56 0.17 0.01 0.10 -1 -1 0.17 0.00360333 0.00316902 16 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 2.99 vpr 61.24 MiB -1 -1 0.17 16984 1 0.02 -1 -1 30068 -1 -1 4 13 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62708 13 7 48 49 1 32 24 17 17 289 -1 unnamed_device 22.5 MiB 0.01 113 670 139 437 94 61.2 MiB 0.01 0.00 0.825048 -14.1032 -0.825048 0.825048 0.66 0.000121874 0.000111722 0.00280615 0.0025762 26 293 16 6.65987e+06 50712 477104. 1650.88 0.59 0.0174431 0.014634 21682 110474 -1 283 18 187 187 18934 4701 1.06545 1.06545 -17.5297 -1.06545 0 0 585099. 2024.56 0.17 0.02 0.10 -1 -1 0.17 0.00532044 0.00456315 20 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 3.01 vpr 60.85 MiB -1 -1 0.15 17228 1 0.02 -1 -1 30000 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62308 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 22.2 MiB 0.01 111 1508 461 714 333 60.8 MiB 0.01 0.00 1.18536 -17.1757 -1.18536 1.18536 0.66 0.000139613 0.000128169 0.00599238 0.00550345 28 296 13 6.65987e+06 38034 500653. 1732.36 0.61 0.0216038 0.0184157 21970 115934 -1 262 9 136 136 8292 2563 1.08545 1.08545 -18.9312 -1.08545 0 0 612192. 2118.31 0.18 0.01 0.11 -1 -1 0.18 0.00402982 0.00356521 22 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 3.09 vpr 61.07 MiB -1 -1 0.15 17224 1 0.02 -1 -1 30180 -1 -1 4 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62540 17 9 62 63 1 41 30 17 17 289 -1 unnamed_device 22.6 MiB 0.01 119 1594 461 883 250 61.1 MiB 0.02 0.00 1.19636 -19.4942 -1.19636 1.19636 0.66 0.000159612 0.000146961 0.00596969 0.00549907 32 330 16 6.65987e+06 50712 554710. 1919.41 0.67 0.0240947 0.0205144 22834 132086 -1 281 13 133 133 8022 2338 1.09645 1.09645 -21.4834 -1.09645 0 0 701300. 2426.64 0.20 0.01 0.13 -1 -1 0.20 0.00530799 0.00462174 25 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 3.09 vpr 61.21 MiB -1 -1 0.15 17180 1 0.02 -1 -1 29948 -1 -1 4 19 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62676 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 22.7 MiB 0.01 130 2165 641 1112 412 61.2 MiB 0.02 0.00 1.20736 -22.0911 -1.20736 1.20736 0.66 0.000173899 0.000160531 0.00781201 0.00721594 26 359 15 6.65987e+06 50712 477104. 1650.88 0.64 0.0275906 0.0236264 21682 110474 -1 352 13 197 197 17592 4637 1.21665 1.21665 -25.5322 -1.21665 0 0 585099. 2024.56 0.17 0.02 0.10 -1 -1 0.17 0.00586274 0.00508496 28 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 3.09 vpr 61.23 MiB -1 -1 0.16 17160 1 0.03 -1 -1 30152 -1 -1 5 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62704 21 11 76 77 1 49 37 17 17 289 -1 unnamed_device 22.7 MiB 0.02 146 2599 849 1247 503 61.2 MiB 0.02 0.00 1.21836 -24.7702 -1.21836 1.21836 0.67 0.000193897 0.000178638 0.00884964 0.00818584 28 451 15 6.65987e+06 63390 500653. 1732.36 0.63 0.0309412 0.0265705 21970 115934 -1 403 18 284 284 24774 6503 1.14559 1.14559 -26.5125 -1.14559 0 0 612192. 2118.31 0.18 0.02 0.11 -1 -1 0.18 0.00760464 0.00650486 31 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 3.13 vpr 61.11 MiB -1 -1 0.16 17228 1 0.02 -1 -1 30068 -1 -1 5 23 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62572 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 22.6 MiB 0.02 164 2624 822 1205 597 61.1 MiB 0.02 0.00 1.22936 -27.5927 -1.22936 1.22936 0.71 0.000212415 0.00019654 0.00879453 0.00814611 28 553 19 6.65987e+06 63390 500653. 1732.36 0.65 0.0335815 0.0287785 21970 115934 -1 441 15 295 295 28098 7446 1.10745 1.10745 -28.9722 -1.10745 0 0 612192. 2118.31 0.18 0.02 0.11 -1 -1 0.18 0.00725138 0.00626258 34 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.20 vpr 61.31 MiB -1 -1 0.15 17200 1 0.02 -1 -1 30076 -1 -1 5 25 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62780 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 22.8 MiB 0.02 223 3193 975 1461 757 61.3 MiB 0.03 0.00 1.24036 -30.6298 -1.24036 1.24036 0.67 0.000223378 0.000206877 0.0103334 0.00956946 32 562 14 6.65987e+06 63390 554710. 1919.41 0.72 0.0352523 0.030479 22834 132086 -1 455 15 258 258 14799 4178 1.12945 1.12945 -31.8095 -1.12945 0 0 701300. 2426.64 0.20 0.02 0.12 -1 -1 0.20 0.00753138 0.00650194 37 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.26 vpr 61.30 MiB -1 -1 0.15 17140 1 0.02 -1 -1 30016 -1 -1 6 27 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62776 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 22.8 MiB 0.02 203 3743 1266 1895 582 61.3 MiB 0.04 0.00 1.25136 -33.0797 -1.25136 1.25136 0.69 0.000180835 0.000163976 0.0114849 0.010514 28 693 32 6.65987e+06 76068 500653. 1732.36 0.76 0.0446686 0.038274 21970 115934 -1 573 17 425 425 38592 10533 1.17465 1.17465 -34.4327 -1.17465 0 0 612192. 2118.31 0.18 0.03 0.11 -1 -1 0.18 0.00877668 0.00758502 40 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 3.18 vpr 61.19 MiB -1 -1 0.15 17488 1 0.02 -1 -1 30008 -1 -1 7 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62656 29 15 104 105 1 73 51 17 17 289 -1 unnamed_device 22.7 MiB 0.02 264 4093 1437 1752 904 61.2 MiB 0.03 0.00 1.26236 -36.2215 -1.26236 1.26236 0.66 0.000253145 0.000234295 0.011807 0.0109381 32 670 15 6.65987e+06 88746 554710. 1919.41 0.69 0.0396472 0.0343721 22834 132086 -1 581 23 359 359 103468 51390 1.17345 1.17345 -38.6162 -1.17345 0 0 701300. 2426.64 0.20 0.05 0.12 -1 -1 0.20 0.011457 0.00981357 44 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 3.29 vpr 61.08 MiB -1 -1 0.16 17596 1 0.02 -1 -1 30368 -1 -1 7 31 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62548 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 22.6 MiB 0.02 288 4848 1943 2811 94 61.1 MiB 0.03 0.00 1.62267 -39.7289 -1.62267 1.62267 0.66 0.000296047 0.000275111 0.0137689 0.012758 32 700 13 6.65987e+06 88746 554710. 1919.41 0.70 0.042975 0.0373677 22834 132086 -1 588 19 363 363 27152 7268 1.05125 1.05125 -39.1147 -1.05125 0 0 701300. 2426.64 0.20 0.03 0.12 -1 -1 0.20 0.0105454 0.00909287 46 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 3.25 vpr 61.33 MiB -1 -1 0.15 17480 1 0.02 -1 -1 30064 -1 -1 7 33 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62800 33 17 118 119 1 82 57 17 17 289 -1 unnamed_device 22.7 MiB 0.02 308 6597 2389 2698 1510 61.3 MiB 0.04 0.00 1.63367 -42.5457 -1.63367 1.63367 0.66 0.000296697 0.000275059 0.0184716 0.0171333 32 736 23 6.65987e+06 88746 554710. 1919.41 0.71 0.0510157 0.0445487 22834 132086 -1 635 17 405 405 33264 8740 1.19345 1.19345 -42.9014 -1.19345 0 0 701300. 2426.64 0.20 0.03 0.12 -1 -1 0.20 0.0103838 0.00898409 49 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 3.28 vpr 61.46 MiB -1 -1 0.16 17452 1 0.02 -1 -1 30060 -1 -1 8 37 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62932 37 19 132 133 1 90 64 17 17 289 -1 unnamed_device 22.9 MiB 0.02 338 6795 2757 3910 128 61.5 MiB 0.04 0.00 1.66184 -49.2226 -1.66184 1.66184 0.66 0.000327462 0.000304172 0.0184939 0.0172006 30 841 20 6.65987e+06 101424 526063. 1820.29 0.70 0.0569636 0.0496511 22546 126617 -1 737 14 426 426 36938 10631 1.14045 1.14045 -47.2201 -1.14045 0 0 666494. 2306.21 0.19 0.03 0.11 -1 -1 0.19 0.0102395 0.00889686 55 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 4.87 vpr 61.34 MiB -1 -1 0.16 17428 1 0.03 -1 -1 30360 -1 -1 8 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62816 41 21 146 147 1 102 70 17 17 289 -1 unnamed_device 22.7 MiB 0.03 394 7990 3280 4604 106 61.3 MiB 0.05 0.00 1.67767 -56.0732 -1.67767 1.67767 0.66 0.00035967 0.000334382 0.0209516 0.0194941 32 1087 23 6.65987e+06 101424 554710. 1919.41 2.30 0.105571 0.0908996 22834 132086 -1 908 14 558 558 45347 11907 1.25945 1.25945 -56.4254 -1.25945 0 0 701300. 2426.64 0.20 0.03 0.09 -1 -1 0.20 0.0109338 0.00953004 61 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 5.15 vpr 61.45 MiB -1 -1 0.16 17632 1 0.02 -1 -1 30336 -1 -1 10 45 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62924 45 23 160 161 1 114 78 17 17 289 -1 unnamed_device 22.8 MiB 0.03 488 9208 3771 5298 139 61.4 MiB 0.06 0.00 1.69967 -62.9619 -1.69967 1.69967 0.69 0.00039092 0.000363271 0.0226572 0.0210694 36 1124 25 6.65987e+06 126780 612192. 2118.31 2.52 0.126137 0.108853 23410 145293 -1 962 14 514 514 44638 11488 1.23745 1.23745 -61.3906 -1.23745 0 0 782063. 2706.10 0.21 0.04 0.13 -1 -1 0.21 0.0118808 0.0104196 68 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 3.30 vpr 61.90 MiB -1 -1 0.12 17348 1 0.02 -1 -1 30420 -1 -1 10 49 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63384 49 25 174 175 1 123 84 17 17 289 -1 unnamed_device 23.2 MiB 0.06 522 5025 948 3851 226 61.9 MiB 0.04 0.00 2.07098 -69.6207 -2.07098 2.07098 0.66 0.000420978 0.000392155 0.0127708 0.011908 30 1271 23 6.65987e+06 126780 526063. 1820.29 0.79 0.0636972 0.055469 22546 126617 -1 1026 17 511 511 34093 9196 1.56385 1.56385 -74.8887 -1.56385 0 0 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0.03 -1 -1 30016 -1 -1 13 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63244 65 33 230 231 1 164 111 17 17 289 -1 unnamed_device 23.2 MiB 0.03 796 12613 2902 8977 734 61.8 MiB 0.08 0.00 2.50829 -102.591 -2.50829 2.50829 0.68 0.000565242 0.000528385 0.0283548 0.0264917 30 1787 26 6.65987e+06 164814 526063. 1820.29 0.84 0.0999576 0.0884406 22546 126617 -1 1473 14 694 694 50016 13024 1.44759 1.44759 -96.299 -1.44759 0 0 666494. 2306.21 0.19 0.04 0.11 -1 -1 0.19 0.0164922 0.0145668 97 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.89 vpr 62.69 MiB -1 -1 0.18 17684 1 0.03 -1 -1 30276 -1 -1 19 97 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64196 97 49 342 343 1 246 165 17 17 289 -1 unnamed_device 23.8 MiB 0.05 1495 31353 9814 19140 2399 62.7 MiB 0.18 0.00 3.38291 -183.11 -3.38291 3.38291 0.65 0.000863126 0.000809109 0.0624506 0.0585064 32 3051 40 6.65987e+06 240882 554710. 1919.41 0.94 0.19035 0.171649 22834 132086 -1 2704 26 1139 1139 155858 42034 1.62545 1.62545 -154.798 -1.62545 0 0 701300. 2426.64 0.20 0.10 0.12 -1 -1 0.20 0.0405798 0.0361239 145 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 4.29 vpr 63.19 MiB -1 -1 0.20 17880 1 0.03 -1 -1 30500 -1 -1 25 129 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64708 129 65 454 455 1 328 219 17 17 289 -1 unnamed_device 24.3 MiB 0.08 2040 51621 17960 30273 3388 63.2 MiB 0.30 0.01 4.25753 -270.446 -4.25753 4.25753 0.66 0.00106095 0.0010003 0.0958688 0.0900199 32 4135 45 6.65987e+06 316950 554710. 1919.41 1.09 0.286974 0.260813 22834 132086 -1 3554 15 1373 1373 144561 33087 1.85245 1.85245 -211.327 -1.85245 0 0 701300. 2426.64 0.20 0.10 0.12 -1 -1 0.20 0.0359556 0.0324692 193 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_004bits.v common 2.86 vpr 61.84 MiB -1 -1 0.15 17184 1 0.02 -1 -1 29952 -1 -1 1 9 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63328 9 5 34 35 1 15 15 17 17 289 -1 unnamed_device 23.1 MiB 0.02 31 357 99 212 46 61.8 MiB 0.01 0.00 0.723895 -9.81308 -0.723895 0.723895 0.70 8.7282e-05 7.9147e-05 0.00204764 0.00185217 18 109 13 6.95648e+06 14475.7 376052. 1301.22 0.47 0.0126091 0.0106259 22882 88689 -1 106 10 63 63 4495 1485 0.74674 0.74674 -10.4754 -0.74674 0 0 470940. 1629.55 0.13 0.01 0.08 -1 -1 0.13 0.00303795 0.00270532 7 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_005bits.v common 3.92 vpr 61.95 MiB -1 -1 0.10 17236 1 0.02 -1 -1 29888 -1 -1 1 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63436 11 6 41 42 1 20 18 17 17 289 -1 unnamed_device 23.3 MiB 0.03 45 409 82 317 10 61.9 MiB 0.01 0.00 0.723895 -12.1585 -0.723895 0.723895 0.68 0.000104663 9.5475e-05 0.00223257 0.00203559 22 170 8 6.95648e+06 14475.7 443629. 1535.05 1.56 0.0190578 0.0157985 23458 102101 -1 133 9 59 59 3523 1154 0.723895 0.723895 -13.1609 -0.723895 0 0 531479. 1839.03 0.15 0.01 0.09 -1 -1 0.15 0.00347157 0.00310975 8 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_006bits.v common 3.89 vpr 61.98 MiB -1 -1 0.15 17192 1 0.02 -1 -1 30072 -1 -1 2 13 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63464 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 23.4 MiB 0.03 75 472 115 342 15 62.0 MiB 0.01 0.00 0.905094 -15.1774 -0.905094 0.905094 0.68 0.00012189 0.000111654 0.00233885 0.00214172 20 205 8 6.95648e+06 28951.4 414966. 1435.87 1.38 0.0122566 0.0104883 23170 95770 -1 200 10 84 84 5135 1594 0.87204 0.87204 -16.4471 -0.87204 0 0 503264. 1741.40 0.14 0.01 0.09 -1 -1 0.14 0.00388988 0.00344828 10 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 3.25 vpr 61.77 MiB -1 -1 0.17 17228 1 0.02 -1 -1 30004 -1 -1 2 15 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63256 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 23.3 MiB 0.03 182 997 285 587 125 61.8 MiB 0.01 0.00 0.852632 -19.1795 -0.852632 0.852632 0.70 0.000138925 0.000127494 0.00432536 0.00398115 24 369 14 6.95648e+06 28951.4 470940. 1629.55 0.59 0.0203047 0.0172057 24034 113901 -1 347 15 149 149 13529 3216 1.10323 1.10323 -22.1823 -1.10323 0 0 586450. 2029.24 0.16 0.02 0.10 -1 -1 0.16 0.005486 0.00477732 11 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_008bits.v common 3.06 vpr 61.90 MiB -1 -1 0.15 17124 1 0.02 -1 -1 30020 -1 -1 2 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63384 17 9 62 63 1 37 28 17 17 289 -1 unnamed_device 23.3 MiB 0.03 221 616 171 414 31 61.9 MiB 0.01 0.00 0.852632 -23.0752 -0.852632 0.852632 0.68 0.000156976 0.000144516 0.00281936 0.0025914 26 427 11 6.95648e+06 28951.4 503264. 1741.40 0.61 0.0198989 0.016773 24322 120374 -1 413 10 164 164 15751 3684 0.949732 0.949732 -24.7469 -0.949732 0 0 618332. 2139.56 0.17 0.01 0.11 -1 -1 0.17 0.00460572 0.00406062 13 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_009bits.v common 4.94 vpr 61.88 MiB -1 -1 0.16 17144 1 0.02 -1 -1 30232 -1 -1 2 19 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63368 19 10 69 70 1 44 31 17 17 289 -1 unnamed_device 23.4 MiB 0.04 108 2527 936 1406 185 61.9 MiB 0.02 0.00 0.874632 -21.915 -0.874632 0.874632 0.68 0.000174667 0.000161174 0.00982014 0.00906234 34 384 17 6.95648e+06 28951.4 618332. 2139.56 2.35 0.0519176 0.043602 25762 151098 -1 300 23 302 302 18535 6038 1.12523 1.12523 -23.9556 -1.12523 0 0 787024. 2723.27 0.21 0.02 0.13 -1 -1 0.21 0.00849309 0.00723359 14 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_010bits.v common 3.60 vpr 61.99 MiB -1 -1 0.15 17012 1 0.02 -1 -1 30176 -1 -1 2 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63476 21 11 76 77 1 49 34 17 17 289 -1 unnamed_device 23.5 MiB 0.04 124 1849 591 958 300 62.0 MiB 0.02 0.00 0.896632 -24.606 -0.896632 0.896632 0.67 0.000192675 0.000178253 0.00710392 0.00656778 34 464 39 6.95648e+06 28951.4 618332. 2139.56 1.07 0.0510483 0.0426537 25762 151098 -1 362 32 415 415 29570 8454 1.10803 1.10803 -26.2823 -1.10803 0 0 787024. 2723.27 0.21 0.03 0.13 -1 -1 0.21 0.011713 0.00986011 16 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_011bits.v common 3.24 vpr 62.27 MiB -1 -1 0.16 17232 1 0.02 -1 -1 30004 -1 -1 3 23 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63768 23 12 83 84 1 55 38 17 17 289 -1 unnamed_device 23.7 MiB 0.04 149 1424 335 1059 30 62.3 MiB 0.02 0.00 0.879432 -27.154 -0.879432 0.879432 0.68 0.000183203 0.000167598 0.00543142 0.00502988 28 532 47 6.95648e+06 43427 531479. 1839.03 0.73 0.0393068 0.0331151 24610 126494 -1 457 11 280 280 18391 5462 1.06403 1.06403 -32.0123 -1.06403 0 0 648988. 2245.63 0.18 0.02 0.11 -1 -1 0.18 0.00609298 0.00531886 17 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_012bits.v common 3.63 vpr 61.99 MiB -1 -1 0.15 17148 1 0.03 -1 -1 29996 -1 -1 3 25 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63476 25 13 90 91 1 60 41 17 17 289 -1 unnamed_device 23.4 MiB 0.04 191 1581 337 1210 34 62.0 MiB 0.02 0.00 0.918632 -30.4288 -0.918632 0.918632 0.68 0.000224111 0.000207562 0.00575802 0.00534334 34 576 15 6.95648e+06 43427 618332. 2139.56 1.06 0.0478747 0.040272 25762 151098 -1 469 13 301 301 25512 7050 1.14103 1.14103 -34.6799 -1.14103 0 0 787024. 2723.27 0.21 0.02 0.13 -1 -1 0.21 0.00708738 0.00617617 19 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 3.31 vpr 62.01 MiB -1 -1 0.15 17284 1 0.02 -1 -1 30108 -1 -1 3 27 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63496 27 14 97 98 1 66 44 17 17 289 -1 unnamed_device 23.5 MiB 0.04 373 2046 513 1237 296 62.0 MiB 0.02 0.00 0.951632 -36.1138 -0.951632 0.951632 0.68 0.000237905 0.000220439 0.00701976 0.00650806 30 806 29 6.95648e+06 43427 556674. 1926.21 0.73 0.0387382 0.0330004 25186 138497 -1 740 15 338 338 31466 6815 1.23953 1.23953 -40.3343 -1.23953 0 0 706193. 2443.58 0.19 0.02 0.12 -1 -1 0.19 0.00817822 0.0071029 20 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_014bits.v common 3.71 vpr 62.25 MiB -1 -1 0.16 17448 1 0.02 -1 -1 29992 -1 -1 4 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63740 29 15 104 105 1 72 48 17 17 289 -1 unnamed_device 23.6 MiB 0.03 471 3180 797 1969 414 62.2 MiB 0.03 0.00 0.951632 -40.3696 -0.951632 0.951632 0.68 0.000303996 0.000282063 0.0105737 0.00979692 34 943 21 6.95648e+06 57902.7 618332. 2139.56 1.11 0.0601265 0.051146 25762 151098 -1 907 13 383 383 44092 8818 1.17403 1.17403 -47.4039 -1.17403 0 0 787024. 2723.27 0.21 0.03 0.13 -1 -1 0.21 0.00787889 0.00688785 23 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_015bits.v common 3.83 vpr 62.00 MiB -1 -1 0.16 17504 1 0.03 -1 -1 30248 -1 -1 3 31 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63492 31 16 111 112 1 78 50 17 17 289 -1 unnamed_device 23.4 MiB 0.05 264 3822 1541 2241 40 62.0 MiB 0.03 0.00 1.33396 -40.3826 -1.33396 1.33396 0.68 0.000270886 0.000250971 0.0121153 0.0112397 34 748 29 6.95648e+06 43427 618332. 2139.56 1.17 0.0688746 0.0587304 25762 151098 -1 618 19 437 437 34249 8680 1.21603 1.21603 -44.255 -1.21603 0 0 787024. 2723.27 0.21 0.03 0.13 -1 -1 0.21 0.0107725 0.00930388 24 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_016bits.v common 5.00 vpr 62.34 MiB -1 -1 0.15 17420 1 0.03 -1 -1 30048 -1 -1 4 33 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63832 33 17 118 119 1 81 54 17 17 289 -1 unnamed_device 23.7 MiB 0.06 280 4848 1977 2824 47 62.3 MiB 0.04 0.00 1.34496 -43.4863 -1.34496 1.34496 0.68 0.000340372 0.000315622 0.0158838 0.0147285 34 846 37 6.95648e+06 57902.7 618332. 2139.56 2.29 0.112294 0.0951773 25762 151098 -1 606 14 401 401 28162 7406 1.20503 1.20503 -45.4821 -1.20503 0 0 787024. 2723.27 0.21 0.03 0.13 -1 -1 0.21 0.00922062 0.00805291 25 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_018bits.v common 4.06 vpr 62.36 MiB -1 -1 0.17 17484 1 0.02 -1 -1 30084 -1 -1 4 37 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63852 37 19 132 133 1 87 60 17 17 289 -1 unnamed_device 23.7 MiB 0.09 310 6963 2911 4006 46 62.4 MiB 0.05 0.00 1.36696 -49.8294 -1.36696 1.36696 0.68 0.000327057 0.000303873 0.0205925 0.0191589 34 994 23 6.95648e+06 57902.7 618332. 2139.56 1.35 0.0863385 0.0744203 25762 151098 -1 765 19 512 512 55670 13459 1.42263 1.42263 -55.9177 -1.42263 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.0128797 0.011132 28 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_020bits.v common 3.99 vpr 62.29 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30328 -1 -1 4 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63780 41 21 146 147 1 95 66 17 17 289 -1 unnamed_device 23.6 MiB 0.08 348 7115 2951 4114 50 62.3 MiB 0.05 0.00 1.38896 -56.0872 -1.38896 1.38896 0.68 0.000356708 0.000331613 0.0203231 0.018915 34 1081 30 6.95648e+06 57902.7 618332. 2139.56 1.26 0.0931371 0.0803289 25762 151098 -1 859 23 578 578 97985 34449 1.27723 1.27723 -60.4816 -1.27723 0 0 787024. 2723.27 0.21 0.05 0.13 -1 -1 0.21 0.0160421 0.0138688 31 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_022bits.v common 4.16 vpr 62.35 MiB -1 -1 0.17 17388 1 0.02 -1 -1 30308 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63960 49 25 174 175 1 119 79 17 17 289 -1 unnamed_device 23.8 MiB 0.09 521 10050 4309 5679 62 62.5 MiB 0.06 0.00 1.43296 -70.1603 -1.43296 1.43296 0.67 0.000421895 0.000392614 0.026221 0.0244102 36 1304 23 6.95648e+06 72378.4 648988. 2245.63 3.05 0.1406 0.121724 26050 158493 -1 1030 17 612 612 59690 13565 1.41353 1.41353 -73.8115 -1.41353 0 0 828058. 2865.25 0.22 0.04 0.14 -1 -1 0.22 0.0149726 0.013118 37 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_028bits.v common 6.65 vpr 62.59 MiB -1 -1 0.17 17464 1 0.03 -1 -1 30112 -1 -1 6 57 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64088 57 29 202 203 1 142 92 17 17 289 -1 unnamed_device 23.9 MiB 0.07 560 13961 5920 7973 68 62.6 MiB 0.08 0.00 1.47696 -82.5806 -1.47696 1.47696 0.68 0.000486994 0.000453244 0.0343411 0.0319713 44 1567 49 6.95648e+06 86854.1 787024. 2723.27 3.81 0.218821 0.190202 27778 195446 -1 1178 16 789 789 69897 17053 1.71293 1.71293 -93.4275 -1.71293 0 0 997811. 3452.63 0.26 0.05 0.17 -1 -1 0.26 0.0162237 0.0142906 43 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_032bits.v common 6.57 vpr 62.62 MiB -1 -1 0.17 17772 1 0.03 -1 -1 30088 -1 -1 7 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64128 65 33 230 231 1 162 105 17 17 289 -1 unnamed_device 24.1 MiB 0.08 758 16160 6842 9176 142 62.6 MiB 0.09 0.00 1.88129 -97.0955 -1.88129 1.88129 0.67 0.000568281 0.000530239 0.0389098 0.036328 46 1513 18 6.95648e+06 101330 828058. 2865.25 3.65 0.182353 0.160035 28066 200906 -1 1326 20 938 938 82737 18232 1.39433 1.39433 -94.6526 -1.39433 0 0 1.01997e+06 3529.29 0.26 0.06 0.17 -1 -1 0.26 0.0222592 0.0195882 49 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_048bits.v common 13.20 vpr 63.59 MiB -1 -1 0.19 17748 1 0.03 -1 -1 30248 -1 -1 10 97 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65116 97 49 342 343 1 243 156 17 17 289 -1 unnamed_device 24.4 MiB 0.10 1331 30743 8901 19960 1882 63.6 MiB 0.16 0.00 2.41762 -163.869 -2.41762 2.41762 0.68 0.000868882 0.000814468 0.0660178 0.0618779 46 2969 39 6.95648e+06 144757 828058. 2865.25 10.06 0.463365 0.412468 28066 200906 -1 2418 23 1272 1272 164877 46134 1.59703 1.59703 -158.435 -1.59703 0 0 1.01997e+06 3529.29 0.26 0.10 0.17 -1 -1 0.26 0.0374983 0.0335237 73 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_064bits.v common 8.79 vpr 64.01 MiB -1 -1 0.21 17776 1 0.03 -1 -1 30480 -1 -1 13 129 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65548 129 65 454 455 1 324 207 17 17 289 -1 unnamed_device 24.9 MiB 0.12 2090 36315 10749 23078 2488 64.0 MiB 0.21 0.01 2.95395 -243.637 -2.95395 2.95395 0.68 0.00119694 0.00112643 0.0741031 0.0697002 60 3530 29 6.95648e+06 188184 1.01997e+06 3529.29 5.38 0.462086 0.415678 30658 258169 -1 3123 16 1299 1299 131280 27013 1.66773 1.66773 -209.901 -1.66773 0 0 1.27783e+06 4421.56 0.32 0.10 0.22 -1 -1 0.32 0.0389481 0.0352944 97 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_004bits.v common 2.86 vpr 61.61 MiB -1 -1 0.14 17324 1 0.02 -1 -1 29988 -1 -1 1 9 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63092 9 5 34 35 1 17 15 17 17 289 -1 unnamed_device 22.9 MiB 0.01 35 375 107 237 31 61.6 MiB 0.01 0.00 0.712895 -9.56286 -0.712895 0.712895 0.68 8.7064e-05 7.8893e-05 0.00212669 0.0019303 22 122 12 6.99608e+06 14715.7 443629. 1535.05 0.53 0.0122226 0.010287 23458 102101 -1 88 10 56 56 2042 763 0.834592 0.834592 -9.47336 -0.834592 0 0 531479. 1839.03 0.15 0.01 0.09 -1 -1 0.15 0.00302037 0.00268799 7 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_005bits.v common 2.97 vpr 61.53 MiB -1 -1 0.15 17256 1 0.02 -1 -1 29912 -1 -1 1 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63008 11 6 41 42 1 20 18 17 17 289 -1 unnamed_device 22.8 MiB 0.01 44 409 92 302 15 61.5 MiB 0.01 0.00 0.837432 -12.9697 -0.837432 0.837432 0.68 0.000104705 9.5595e-05 0.00222083 0.00202997 22 151 9 6.99608e+06 14715.7 443629. 1535.05 0.55 0.0137541 0.0115757 23458 102101 -1 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17332 1 0.02 -1 -1 30148 -1 -1 2 15 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63032 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 22.8 MiB 0.02 80 745 225 479 41 61.6 MiB 0.01 0.00 0.859432 -18.0958 -0.859432 0.859432 0.68 0.000140434 0.000129114 0.00336029 0.003095 26 226 21 6.99608e+06 29431.4 503264. 1741.40 0.63 0.0207047 0.0174372 24322 120374 -1 219 8 108 108 6712 2063 0.940679 0.940679 -18.5361 -0.940679 0 0 618332. 2139.56 0.17 0.01 0.11 -1 -1 0.17 0.00383384 0.00341969 11 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_008bits.v common 3.09 vpr 62.01 MiB -1 -1 0.15 17212 1 0.04 -1 -1 30120 -1 -1 2 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63500 17 9 62 63 1 38 28 17 17 289 -1 unnamed_device 23.5 MiB 0.02 203 658 170 428 60 62.0 MiB 0.01 0.00 0.87204 -21.2308 -0.87204 0.87204 0.68 0.000155534 0.00014286 0.00291886 0.00268597 26 454 14 6.99608e+06 29431.4 503264. 1741.40 0.62 0.0208548 0.01753 24322 120374 -1 397 16 215 215 23320 5491 1.11618 1.11618 -24.5247 -1.11618 0 0 618332. 2139.56 0.17 0.02 0.11 -1 -1 0.17 0.00594626 0.00511258 13 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_009bits.v common 5.35 vpr 61.82 MiB -1 -1 0.15 17208 1 0.02 -1 -1 30064 -1 -1 2 19 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63304 19 10 69 70 1 44 31 17 17 289 -1 unnamed_device 23.3 MiB 0.02 110 2479 792 1104 583 61.8 MiB 0.02 0.00 0.846432 -21.9214 -0.846432 0.846432 0.68 0.000174702 0.000161124 0.00958988 0.00884645 36 343 46 6.99608e+06 29431.4 648988. 2245.63 2.80 0.0627426 0.0522955 26050 158493 -1 255 16 264 264 11899 3964 1.09703 1.09703 -22.5274 -1.09703 0 0 828058. 2865.25 0.22 0.02 0.14 -1 -1 0.22 0.00658358 0.00568186 14 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_010bits.v common 3.63 vpr 61.95 MiB -1 -1 0.15 17104 1 0.02 -1 -1 30080 -1 -1 2 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63436 21 11 76 77 1 49 34 17 17 289 -1 unnamed_device 23.5 MiB 0.02 134 1739 500 978 261 61.9 MiB 0.02 0.00 0.857432 -24.4123 -0.857432 0.857432 0.70 0.00019256 0.000177985 0.00675256 0.00624408 34 406 27 6.99608e+06 29431.4 618332. 2139.56 1.08 0.0469744 0.039314 25762 151098 -1 352 19 335 335 20191 5998 1.16733 1.16733 -25.6028 -1.16733 0 0 787024. 2723.27 0.21 0.02 0.13 -1 -1 0.21 0.00793836 0.0067661 16 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_011bits.v common 3.19 vpr 61.93 MiB -1 -1 0.15 17348 1 0.03 -1 -1 30000 -1 -1 3 23 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63420 23 12 83 84 1 54 38 17 17 289 -1 unnamed_device 23.4 MiB 0.02 157 1298 273 992 33 61.9 MiB 0.01 0.00 0.879432 -27.0809 -0.879432 0.879432 0.69 0.000209784 0.000194331 0.00498719 0.00462021 30 505 13 6.99608e+06 44147 556674. 1926.21 0.68 0.0282405 0.0240418 25186 138497 -1 420 17 320 320 22894 6682 1.13198 1.13198 -31.7562 -1.13198 0 0 706193. 2443.58 0.19 0.02 0.12 -1 -1 0.19 0.00791286 0.00680288 17 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_012bits.v common 3.19 vpr 61.80 MiB -1 -1 0.14 17248 1 0.02 -1 -1 29996 -1 -1 3 25 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63280 25 13 90 91 1 60 41 17 17 289 -1 unnamed_device 23.3 MiB 0.02 214 1861 414 1414 33 61.8 MiB 0.02 0.00 0.890432 -31.2249 -0.890432 0.890432 0.68 0.000223146 0.000206487 0.00656913 0.00606521 26 594 14 6.99608e+06 44147 503264. 1741.40 0.67 0.0311123 0.0265403 24322 120374 -1 540 14 356 356 28447 7724 1.08798 1.08798 -35.908 -1.08798 0 0 618332. 2139.56 0.17 0.02 0.11 -1 -1 0.17 0.00739638 0.00642002 19 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 3.23 vpr 61.92 MiB -1 -1 0.16 17132 1 0.02 -1 -1 30056 -1 -1 3 27 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63408 27 14 97 98 1 66 44 17 17 289 -1 unnamed_device 23.4 MiB 0.02 395 2354 574 1438 342 61.9 MiB 0.02 0.00 0.912432 -36.6204 -0.912432 0.912432 0.67 0.000244515 0.000221455 0.00801856 0.00743288 30 788 16 6.99608e+06 44147 556674. 1926.21 0.71 0.0349545 0.0299783 25186 138497 -1 710 15 331 331 30405 6379 1.18218 1.18218 -41.7645 -1.18218 0 0 706193. 2443.58 0.19 0.02 0.12 -1 -1 0.19 0.00813372 0.0070695 20 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_014bits.v common 3.71 vpr 61.95 MiB -1 -1 0.14 17028 1 0.02 -1 -1 29952 -1 -1 4 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63440 29 15 104 105 1 72 48 17 17 289 -1 unnamed_device 23.4 MiB 0.02 470 2571 633 1642 296 62.0 MiB 0.02 0.00 0.923432 -39.2056 -0.923432 0.923432 0.68 0.000250872 0.000232665 0.00822485 0.00762679 34 973 32 6.99608e+06 58862.7 618332. 2139.56 1.13 0.0617908 0.0524284 25762 151098 -1 866 15 496 496 57332 11353 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63560 37 19 132 133 1 87 60 17 17 289 -1 unnamed_device 23.5 MiB 0.03 309 6963 2905 3992 66 62.1 MiB 0.05 0.00 1.33876 -48.9536 -1.33876 1.33876 0.67 0.000328569 0.000305361 0.0205895 0.0191523 36 858 19 6.99608e+06 58862.7 648988. 2245.63 1.26 0.0838954 0.07231 26050 158493 -1 707 14 444 444 42628 10193 1.34133 1.34133 -53.1429 -1.34133 0 0 828058. 2865.25 0.22 0.03 0.14 -1 -1 0.22 0.0102672 0.00892568 28 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_020bits.v common 4.04 vpr 62.10 MiB -1 -1 0.16 17520 1 0.02 -1 -1 30328 -1 -1 4 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63588 41 21 146 147 1 94 66 17 17 289 -1 unnamed_device 23.5 MiB 0.03 346 7115 2925 4148 42 62.1 MiB 0.05 0.00 1.34976 -55.318 -1.34976 1.34976 0.68 0.000358867 0.000333622 0.0203294 0.0189181 34 1135 29 6.99608e+06 58862.7 618332. 2139.56 1.34 0.0959932 0.082851 25762 151098 -1 832 15 501 501 54380 12460 1.29733 1.29733 -59.146 -1.29733 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.011617 0.01012 31 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_022bits.v common 4.23 vpr 62.14 MiB -1 -1 0.15 17468 1 0.02 -1 -1 30340 -1 -1 5 45 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63632 45 23 160 161 1 107 73 17 17 289 -1 unnamed_device 23.6 MiB 0.03 396 9041 3748 5233 60 62.1 MiB 0.06 0.00 1.37176 -60.8627 -1.37176 1.37176 0.68 0.000388136 0.000360981 0.0243639 0.0226856 36 1189 23 6.99608e+06 73578.4 648988. 2245.63 1.55 0.101626 0.088275 26050 158493 -1 900 14 588 588 51751 12479 1.26003 1.26003 -64.2225 -1.26003 0 0 828058. 2865.25 0.22 0.04 0.14 -1 -1 0.22 0.0120573 0.0105776 34 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_024bits.v common 4.44 vpr 62.25 MiB -1 -1 0.16 17324 1 0.02 -1 -1 30332 -1 -1 5 49 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63740 49 25 174 175 1 118 79 17 17 289 -1 unnamed_device 23.6 MiB 0.04 446 10050 4202 5799 49 62.2 MiB 0.06 0.00 1.39376 -66.6204 -1.39376 1.39376 0.68 0.00042006 0.000390522 0.0262349 0.0244202 38 1265 21 6.99608e+06 73578.4 678818. 2348.85 1.69 0.108307 0.0943365 26626 170182 -1 974 15 641 641 56777 14042 1.26003 1.26003 -68.4016 -1.26003 0 0 902133. 3121.57 0.23 0.04 0.15 -1 -1 0.23 0.0136353 0.0119655 37 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_028bits.v common 6.07 vpr 62.44 MiB -1 -1 0.17 17468 1 0.03 -1 -1 30020 -1 -1 6 57 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63940 57 29 202 203 1 141 92 17 17 289 -1 unnamed_device 23.7 MiB 0.04 634 13961 5842 8023 96 62.4 MiB 0.08 0.00 1.44876 -81.1127 -1.44876 1.44876 0.67 0.00048998 0.000454837 0.03434 0.031956 36 1508 35 6.99608e+06 88294.1 648988. 2245.63 3.27 0.178122 0.155283 26050 158493 -1 1254 26 824 824 164581 67296 1.21798 1.21798 -79.2356 -1.21798 0 0 828058. 2865.25 0.22 0.08 0.14 -1 -1 0.22 0.0235237 0.0205368 43 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_032bits.v common 8.40 vpr 62.50 MiB -1 -1 0.17 17500 1 0.03 -1 -1 30004 -1 -1 7 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64000 65 33 230 231 1 162 105 17 17 289 -1 unnamed_device 23.7 MiB 0.04 748 16160 6967 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32092 -1 -1 1 9 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62468 9 5 28 33 1 16 15 17 17 289 -1 unnamed_device 22.4 MiB 0.01 35 357 92 226 39 61.0 MiB 0.01 0.00 0.883748 -9.933 -0.883748 0.883748 0.68 8.4734e-05 7.6497e-05 0.00196888 0.00178132 18 144 17 6.79088e+06 13472 376052. 1301.22 0.45 0.00665622 0.00588373 22222 88205 -1 110 7 44 44 1714 684 0.883748 0.883748 -10.7206 -0.883748 0 0 470940. 1629.55 0.13 0.01 0.08 -1 -1 0.13 0.00263552 0.00238471 8 6 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_005bits.v common 3.15 vpr 61.11 MiB -1 -1 0.15 17188 2 0.05 -1 -1 31992 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62572 11 6 34 40 1 23 19 17 17 289 -1 unnamed_device 22.5 MiB 0.01 56 369 83 271 15 61.1 MiB 0.01 0.00 1.02368 -13.1464 -1.02368 1.02368 0.67 0.000104014 9.4812e-05 0.00189463 0.00172822 30 193 10 6.79088e+06 26944 556674. 1926.21 0.65 0.0134574 0.0112841 24526 138013 -1 152 7 57 63 2733 866 1.02368 1.02368 -13.6271 -1.02368 0 0 706193. 2443.58 0.19 0.01 0.12 -1 -1 0.19 0.00305668 0.00274947 10 7 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_006bits.v common 2.91 vpr 61.02 MiB -1 -1 0.10 17192 3 0.05 -1 -1 31792 -1 -1 2 13 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62488 13 7 41 48 1 30 22 17 17 289 -1 unnamed_device 22.4 MiB 0.01 84 562 132 416 14 61.0 MiB 0.01 0.00 1.14898 -15.8855 -1.14898 1.14898 0.67 0.000124296 0.000113845 0.00272442 0.00249969 22 271 8 6.79088e+06 26944 443629. 1535.05 0.53 0.0157781 0.0133199 22798 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62660 19 10 60 70 1 47 31 17 17 289 -1 unnamed_device 22.7 MiB 0.07 125 1183 237 903 43 61.2 MiB 0.01 0.00 1.43883 -25.2844 -1.43883 1.43883 0.67 0.000182863 0.000168735 0.00508335 0.00468617 26 422 10 6.79088e+06 26944 503264. 1741.40 1.28 0.0436852 0.0363998 23662 119890 -1 385 8 159 169 9032 2746 1.38849 1.38849 -27.4637 -1.38849 0 0 618332. 2139.56 0.17 0.01 0.11 -1 -1 0.17 0.00465726 0.00411883 16 13 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_010bits.v common 4.73 vpr 61.26 MiB -1 -1 0.16 17116 4 0.06 -1 -1 31656 -1 -1 3 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62732 21 11 69 80 1 55 35 17 17 289 -1 unnamed_device 22.8 MiB 0.10 146 2315 597 1240 478 61.3 MiB 0.02 0.00 1.81478 -30.6537 -1.81478 1.81478 0.67 0.000233285 0.000212021 0.00979652 0.00898605 30 577 23 6.79088e+06 40416 556674. 1926.21 2.10 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63224 27 14 91 105 1 72 46 17 17 289 -1 unnamed_device 23.2 MiB 0.25 357 5294 1465 2962 867 61.7 MiB 0.05 0.00 2.15497 -46.2823 -2.15497 2.15497 0.67 0.000360865 0.000333566 0.0266747 0.0247208 30 821 13 6.79088e+06 67360 556674. 1926.21 1.51 0.0843095 0.0727651 24526 138013 -1 699 10 243 302 17846 4568 1.89323 1.89323 -44.8083 -1.89323 0 0 706193. 2443.58 0.19 0.02 0.12 -1 -1 0.19 0.0072577 0.00639563 28 24 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_014bits.v common 3.52 vpr 61.38 MiB -1 -1 0.18 17272 6 0.06 -1 -1 32108 -1 -1 4 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62852 29 15 95 110 1 77 48 17 17 289 -1 unnamed_device 22.9 MiB 0.21 360 2310 483 1816 11 61.4 MiB 0.02 0.00 2.44482 -48.4646 -2.44482 2.44482 0.67 0.000280721 0.000260207 0.00834682 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2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63092 37 19 127 146 1 99 62 17 17 289 -1 unnamed_device 23.0 MiB 0.81 464 4820 996 3804 20 61.6 MiB 0.04 0.00 3.16102 -73.9362 -3.16102 3.16102 0.67 0.00036881 0.00034252 0.0156651 0.0145648 30 1094 21 6.79088e+06 80832 556674. 1926.21 1.62 0.0958325 0.0820414 24526 138013 -1 930 12 343 419 31667 7571 2.82088 2.82088 -72.5283 -2.82088 0 0 706193. 2443.58 0.24 0.03 0.12 -1 -1 0.24 0.0106908 0.00940112 38 35 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_020bits.v common 5.50 vpr 61.51 MiB -1 -1 0.19 17548 8 0.06 -1 -1 31928 -1 -1 6 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62984 41 21 139 160 1 108 68 17 17 289 -1 unnamed_device 22.8 MiB 0.35 505 7106 1657 5163 286 61.5 MiB 0.05 0.00 2.83873 -77.6199 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63556 57 29 198 227 1 155 95 17 17 289 -1 unnamed_device 23.6 MiB 0.70 615 10463 2656 6907 900 62.1 MiB 0.06 0.00 4.24968 -125.714 -4.24968 4.24968 0.67 0.000571579 0.000532061 0.0293594 0.0273517 34 1590 48 6.79088e+06 121248 618332. 2139.56 1.34 0.163461 0.14228 25102 150614 -1 1284 13 514 639 38670 10280 4.07404 4.07404 -123.729 -4.07404 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.0165509 0.0145999 57 56 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_032bits.v common 6.51 vpr 62.35 MiB -1 -1 0.21 17704 13 0.08 -1 -1 32276 -1 -1 10 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63848 65 33 224 257 1 176 108 17 17 289 -1 unnamed_device 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success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63176 27 14 97 98 1 67 45 17 17 289 -1 unnamed_device 22.9 MiB 0.05 213 3965 1588 2336 41 61.7 MiB 0.03 0.00 1.2704 -36.288 -1.2704 1.2704 0.68 0.000237431 0.000219543 0.0125415 0.0115936 34 721 25 6.87369e+06 55895.4 618332. 2139.56 1.10 0.0609137 0.0518256 25762 151098 -1 589 20 464 464 40651 10612 1.19797 1.19797 -38.5769 -1.19797 0 0 787024. 2723.27 0.21 0.03 0.13 -1 -1 0.21 0.0098341 0.00843389 28 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_014bits.v common 5.04 vpr 61.62 MiB -1 -1 0.17 17636 1 0.02 -1 -1 29960 -1 -1 5 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63104 29 15 104 105 1 74 49 17 17 289 -1 unnamed_device 23.2 MiB 0.07 237 4232 1719 2454 59 61.6 MiB 0.03 0.00 1.2814 -39.5262 -1.2814 1.2814 0.69 0.00025177 0.000232586 0.0125905 0.0116432 34 871 25 6.87369e+06 69869.2 618332. 2139.56 2.40 0.079398 0.0672669 25762 151098 -1 667 19 530 530 42842 11447 1.19797 1.19797 -41.7719 -1.19797 0 0 787024. 2723.27 0.21 0.03 0.13 -1 -1 0.21 0.00987761 0.00848143 31 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_015bits.v common 4.14 vpr 61.68 MiB -1 -1 0.15 17472 1 0.02 -1 -1 30296 -1 -1 5 31 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63160 31 16 111 112 1 80 52 17 17 289 -1 unnamed_device 23.2 MiB 0.13 290 5096 2068 2936 92 61.7 MiB 0.04 0.00 1.65273 -43.1089 -1.65273 1.65273 0.68 0.000270835 0.000250663 0.0151058 0.0139874 30 651 17 6.87369e+06 69869.2 556674. 1926.21 1.61 0.0753013 0.06438 25186 138497 -1 555 14 349 349 20738 5613 1.18967 1.18967 -42.4244 -1.18967 0 0 706193. 2443.58 0.19 0.02 0.08 -1 -1 0.19 0.00848612 0.00736887 33 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_016bits.v common 3.31 vpr 61.83 MiB -1 -1 0.15 17556 1 0.02 -1 -1 30004 -1 -1 5 33 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63316 33 17 118 119 1 83 55 17 17 289 -1 unnamed_device 23.3 MiB 0.08 305 6087 2501 3496 90 61.8 MiB 0.04 0.00 1.66373 -46.473 -1.66373 1.66373 0.68 0.000289384 0.000268076 0.017735 0.016463 30 704 16 6.87369e+06 69869.2 556674. 1926.21 0.71 0.049865 0.0434789 25186 138497 -1 594 15 396 396 26462 7106 1.10837 1.10837 -44.7628 -1.10837 0 0 706193. 2443.58 0.19 0.03 0.12 -1 -1 0.19 0.00946652 0.00819901 34 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_018bits.v common 4.32 vpr 61.81 MiB -1 -1 0.16 17376 1 0.03 -1 -1 30088 -1 -1 5 37 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63296 37 19 132 133 1 89 61 17 17 289 -1 unnamed_device 23.2 MiB 0.07 338 5821 2339 3395 87 61.8 MiB 0.04 0.00 1.68573 -53.1446 -1.68573 1.68573 0.67 0.000331983 0.00030891 0.0168326 0.0156666 30 889 19 6.87369e+06 69869.2 556674. 1926.21 1.73 0.0876477 0.0749122 25186 138497 -1 717 13 426 426 32408 8353 1.25567 1.25567 -53.9391 -1.25567 0 0 706193. 2443.58 0.19 0.03 0.12 -1 -1 0.19 0.00950495 0.00826691 38 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_020bits.v common 3.83 vpr 61.99 MiB -1 -1 0.16 17440 1 0.02 -1 -1 30316 -1 -1 6 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63480 41 21 146 147 1 101 68 17 17 289 -1 unnamed_device 23.4 MiB 0.07 382 7382 2999 4271 112 62.0 MiB 0.05 0.00 1.70773 -60.515 -1.70773 1.70773 0.68 0.00036779 0.00034229 0.0202702 0.0188494 34 1055 16 6.87369e+06 83843 618332. 2139.56 1.15 0.0872034 0.0751779 25762 151098 -1 880 13 543 543 61364 17119 1.24467 1.24467 -58.6078 -1.24467 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.0103488 0.00905556 42 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_022bits.v common 4.02 vpr 62.00 MiB -1 -1 0.17 17468 1 0.02 -1 -1 30320 -1 -1 7 45 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63492 45 23 160 161 1 115 75 17 17 289 -1 unnamed_device 23.4 MiB 0.11 444 8449 3437 4860 152 62.0 MiB 0.05 0.00 1.72973 -67.7337 -1.72973 1.72973 0.68 0.000392695 0.000364823 0.0219802 0.0204547 34 1370 26 6.87369e+06 97816.9 618332. 2139.56 1.30 0.0832593 0.0724742 25762 151098 -1 1015 13 608 608 51492 13168 1.28867 1.28867 -65.2983 -1.28867 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.0111065 0.00972696 47 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_024bits.v common 4.01 vpr 62.07 MiB -1 -1 0.17 17528 1 0.02 -1 -1 30404 -1 -1 7 49 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63560 49 25 174 175 1 124 81 17 17 289 -1 unnamed_device 23.5 MiB 0.09 605 10056 2373 7370 313 62.1 MiB 0.07 0.00 2.11206 -78.5497 -2.11206 2.11206 0.67 0.000422072 0.000392985 0.0255691 0.0238238 34 1389 20 6.87369e+06 97816.9 618332. 2139.56 1.18 0.106841 0.0930413 25762 151098 -1 1234 14 660 660 60348 14534 1.34797 1.34797 -75.6162 -1.34797 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.0125046 0.010949 50 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_028bits.v common 4.05 vpr 62.18 MiB -1 -1 0.15 17476 1 0.02 -1 -1 29948 -1 -1 8 57 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63672 57 29 202 203 1 142 94 17 17 289 -1 unnamed_device 23.6 MiB 0.09 728 10957 2389 8188 380 62.2 MiB 0.07 0.00 2.15606 -94.7378 -2.15606 2.15606 0.68 0.000487876 0.000454841 0.0263095 0.0245419 34 1647 17 6.87369e+06 111791 618332. 2139.56 1.24 0.114196 0.100013 25762 151098 -1 1490 15 722 722 68358 15964 1.40297 1.40297 -91.1627 -1.40297 0 0 787024. 2723.27 0.21 0.05 0.13 -1 -1 0.21 0.0151007 0.0132963 58 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_032bits.v common 4.19 vpr 62.34 MiB -1 -1 0.16 17500 1 0.03 -1 -1 29988 -1 -1 9 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63840 65 33 230 231 1 165 107 17 17 289 -1 unnamed_device 23.6 MiB 0.09 980 16046 5179 9796 1071 62.3 MiB 0.10 0.00 2.56039 -112.877 -2.56039 2.56039 0.69 0.000564608 0.000527347 0.0374872 0.0350016 34 2030 21 6.87369e+06 125765 618332. 2139.56 1.34 0.147487 0.12985 25762 151098 -1 1789 14 795 795 84552 18473 1.56397 1.56397 -108.864 -1.56397 0 0 787024. 2723.27 0.21 0.05 0.13 -1 -1 0.21 0.016502 0.0145659 66 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_048bits.v common 4.53 vpr 62.94 MiB -1 -1 0.20 17760 1 0.03 -1 -1 30208 -1 -1 13 97 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64452 97 49 342 343 1 247 159 17 17 289 -1 unnamed_device 24.0 MiB 0.11 1359 29399 8657 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30060 -1 -1 3 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62856 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 22.7 MiB 0.03 62 641 164 455 22 61.4 MiB 0.01 0.00 0.817273 -12.6839 -0.817273 0.817273 0.67 0.00010533 9.6259e-05 0.00282302 0.0025714 26 209 13 6.89349e+06 42281.5 503264. 1741.40 1.82 0.0298085 0.0244578 24322 120374 -1 199 9 87 87 5417 1739 0.942573 0.942573 -14.086 -0.942573 0 0 618332. 2139.56 0.22 0.01 0.12 -1 -1 0.22 0.00325929 0.00289589 13 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_006bits.v common 3.10 vpr 61.35 MiB -1 -1 0.15 17092 1 0.02 -1 -1 29960 -1 -1 3 13 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62820 13 7 48 49 1 33 23 17 17 289 -1 unnamed_device 22.6 MiB 0.04 80 1015 241 576 198 61.3 MiB 0.01 0.00 0.833073 -15.3861 -0.833073 0.833073 0.67 0.000121884 0.000111712 0.00424574 0.00389074 28 312 20 6.89349e+06 42281.5 531479. 1839.03 0.64 0.0193223 0.0163021 24610 126494 -1 244 25 292 292 17449 5462 1.08367 1.08367 -16.6538 -1.08367 0 0 648988. 2245.63 0.18 0.02 0.11 -1 -1 0.18 0.00657205 0.00555051 15 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_007bits.v common 3.73 vpr 61.24 MiB -1 -1 0.11 17240 1 0.02 -1 -1 30064 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62712 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 22.6 MiB 0.06 110 1850 727 959 164 61.2 MiB 0.02 0.00 1.2044 -18.413 -1.2044 1.2044 0.68 0.000134194 0.00012004 0.00718063 0.0065967 26 295 32 6.89349e+06 42281.5 503264. 1741.40 1.29 0.0431683 0.0358815 24322 120374 -1 218 12 161 161 7484 2547 0.956373 0.956373 -18.2239 -0.956373 0 0 618332. 2139.56 0.17 0.01 0.11 -1 -1 0.17 0.00457467 0.00398854 17 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_008bits.v common 4.58 vpr 61.50 MiB -1 -1 0.15 17304 1 0.02 -1 -1 30032 -1 -1 3 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62972 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 22.8 MiB 0.04 120 2097 836 1147 114 61.5 MiB 0.02 0.00 1.2154 -21.3749 -1.2154 1.2154 0.68 0.000157577 0.0001451 0.00794598 0.00731835 32 320 18 6.89349e+06 42281.5 586450. 2029.24 2.03 0.0483007 0.0402159 25474 144626 -1 237 18 158 158 8304 2719 0.96932 0.96932 -20.6745 -0.96932 0 0 744469. 2576.02 0.20 0.02 0.13 -1 -1 0.20 0.00639046 0.00545052 18 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_009bits.v common 3.15 vpr 61.38 MiB -1 -1 0.15 17144 1 0.02 -1 -1 30004 -1 -1 3 19 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62852 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 22.6 MiB 0.04 132 2432 921 1234 277 61.4 MiB 0.02 0.00 1.2264 -24.2382 -1.2264 1.2264 0.70 0.00017559 0.000161937 0.00903211 0.00833549 26 385 13 6.89349e+06 42281.5 503264. 1741.40 0.61 0.028358 0.0243091 24322 120374 -1 326 13 188 188 11131 3367 1.12567 1.12567 -26.3034 -1.12567 0 0 618332. 2139.56 0.17 0.02 0.11 -1 -1 0.17 0.00566447 0.00489787 20 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_010bits.v common 4.69 vpr 61.70 MiB -1 -1 0.16 17240 1 0.02 -1 -1 30076 -1 -1 3 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63184 21 11 76 77 1 48 35 17 17 289 -1 unnamed_device 23.3 MiB 0.07 144 2657 904 1108 645 61.7 MiB 0.02 0.00 1.2374 -27.0223 -1.2374 1.2374 0.68 0.000193191 0.000178582 0.00958407 0.0088574 32 414 15 6.89349e+06 42281.5 586450. 2029.24 2.12 0.0593495 0.0495628 25474 144626 -1 365 13 200 200 17605 4541 1.14767 1.14767 -29.691 -1.14767 0 0 744469. 2576.02 0.20 0.02 0.13 -1 -1 0.20 0.00609421 0.00526856 22 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_011bits.v common 4.62 vpr 61.57 MiB -1 -1 0.14 17292 1 0.02 -1 -1 30000 -1 -1 4 23 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63048 23 12 83 84 1 53 39 17 17 289 -1 unnamed_device 22.9 MiB 0.05 161 3207 1169 1568 470 61.6 MiB 0.02 0.00 1.2484 -30.0849 -1.2484 1.2484 0.70 0.000208728 0.000192972 0.0107645 0.00995636 30 508 23 6.89349e+06 56375.4 556674. 1926.21 2.09 0.0559501 0.0471621 25186 138497 -1 412 16 276 276 21287 5430 1.14287 1.14287 -30.9185 -1.14287 0 0 706193. 2443.58 0.19 0.02 0.13 -1 -1 0.19 0.00749804 0.0064525 24 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_012bits.v common 4.31 vpr 61.73 MiB -1 -1 0.15 17184 1 0.02 -1 -1 30012 -1 -1 4 25 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63208 25 13 90 91 1 60 42 17 17 289 -1 unnamed_device 23.1 MiB 0.05 194 3066 1220 1817 29 61.7 MiB 0.02 0.00 1.2594 -33.4928 -1.2594 1.2594 0.71 0.000227703 0.000210777 0.0101504 0.00939565 28 566 20 6.89349e+06 56375.4 531479. 1839.03 1.75 0.0702117 0.0590204 24610 126494 -1 508 14 334 334 23293 6293 1.16062 1.16062 -34.8765 -1.16062 0 0 648988. 2245.63 0.18 0.02 0.11 -1 -1 0.18 0.00717823 0.0062033 26 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_013bits.v common 5.06 vpr 61.51 MiB -1 -1 0.13 17228 1 0.02 -1 -1 30056 -1 -1 4 27 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62988 27 14 97 98 1 67 45 17 17 289 -1 unnamed_device 22.8 MiB 0.05 212 3965 1580 2332 53 61.5 MiB 0.03 0.00 1.2704 -36.2189 -1.2704 1.2704 0.68 0.000237244 0.000219204 0.0124599 0.0115117 36 666 21 6.89349e+06 56375.4 648988. 2245.63 2.45 0.0794831 0.0670493 26050 158493 -1 565 17 407 407 30578 8238 1.18067 1.18067 -37.9109 -1.18067 0 0 828058. 2865.25 0.22 0.03 0.14 -1 -1 0.22 0.00861616 0.00741841 28 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_014bits.v common 4.56 vpr 61.76 MiB -1 -1 0.10 17164 1 0.02 -1 -1 29940 -1 -1 5 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63240 29 15 104 105 1 74 49 17 17 289 -1 unnamed_device 23.0 MiB 0.06 267 4232 1438 1805 989 61.8 MiB 0.03 0.00 1.2814 -39.3367 -1.2814 1.2814 0.68 0.00025057 0.000231901 0.0125591 0.0116212 32 800 16 6.89349e+06 70469.2 586450. 2029.24 1.95 0.0747419 0.0634269 25474 144626 -1 696 20 474 474 53826 12663 1.07887 1.07887 -41.1685 -1.07887 0 0 744469. 2576.02 0.20 0.03 0.13 -1 -1 0.20 0.0102231 0.00876635 31 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_015bits.v common 4.92 vpr 61.71 MiB -1 -1 0.16 17184 1 0.02 -1 -1 30348 -1 -1 5 31 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63196 31 16 111 112 1 80 52 17 17 289 -1 unnamed_device 23.2 MiB 0.08 290 5096 2068 2923 105 61.7 MiB 0.04 0.00 1.65273 -43.2743 -1.65273 1.65273 0.68 0.00026946 0.000249594 0.0148796 0.0137875 32 810 23 6.89349e+06 70469.2 586450. 2029.24 2.27 0.0753431 0.0641536 25474 144626 -1 607 17 388 388 32529 8494 1.21167 1.21167 -43.3168 -1.21167 0 0 744469. 2576.02 0.20 0.03 0.13 -1 -1 0.20 0.00970255 0.00836801 33 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_016bits.v common 4.21 vpr 61.70 MiB -1 -1 0.13 17256 1 0.03 -1 -1 30048 -1 -1 5 33 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63176 33 17 118 119 1 83 55 17 17 289 -1 unnamed_device 23.2 MiB 0.09 305 6087 2495 3491 101 61.7 MiB 0.04 0.00 1.66373 -47.069 -1.66373 1.66373 0.68 0.000290045 0.000268814 0.0179511 0.0166518 30 713 21 6.89349e+06 70469.2 556674. 1926.21 1.48 0.0734606 0.0630285 25186 138497 -1 602 13 392 392 27294 7261 1.21167 1.21167 -46.7 -1.21167 0 0 706193. 2443.58 0.22 0.03 0.16 -1 -1 0.22 0.00853679 0.00742914 34 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_018bits.v common 5.08 vpr 61.67 MiB -1 -1 0.13 17480 1 0.02 -1 -1 30160 -1 -1 5 37 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63148 37 19 132 133 1 89 61 17 17 289 -1 unnamed_device 23.2 MiB 0.07 342 5821 2357 3387 77 61.7 MiB 0.04 0.00 1.68573 -54.1107 -1.68573 1.68573 0.68 0.000328562 0.000305394 0.0168304 0.0156577 34 894 16 6.89349e+06 70469.2 618332. 2139.56 2.38 0.0827565 0.0708403 25762 151098 -1 786 12 419 419 34308 8532 1.35897 1.35897 -55.4515 -1.35897 0 0 787024. 2723.27 0.23 0.03 0.13 -1 -1 0.23 0.00896989 0.0078058 38 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 3.98 vpr 61.75 MiB -1 -1 0.15 17444 1 0.02 -1 -1 30440 -1 -1 6 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63236 41 21 146 147 1 101 68 17 17 289 -1 unnamed_device 23.1 MiB 0.07 382 7382 2994 4283 105 61.8 MiB 0.05 0.00 1.70773 -60.6787 -1.70773 1.70773 0.67 0.000356003 0.000330603 0.0200354 0.018613 34 1137 29 6.89349e+06 84563 618332. 2139.56 1.25 0.0941227 0.0810155 25762 151098 -1 896 14 497 497 49470 12006 1.27767 1.27767 -59.8203 -1.27767 0 0 787024. 2723.27 0.21 0.03 0.14 -1 -1 0.21 0.0133111 0.0116975 42 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 6.02 vpr 61.94 MiB -1 -1 0.14 17312 1 0.02 -1 -1 30336 -1 -1 7 45 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63424 45 23 160 161 1 115 75 17 17 289 -1 unnamed_device 23.3 MiB 0.09 440 8449 3423 4877 149 61.9 MiB 0.05 0.00 1.72973 -67.5802 -1.72973 1.72973 0.68 0.000388278 0.000360736 0.0217766 0.0202537 40 1047 17 6.89349e+06 98656.9 706193. 2443.58 3.27 0.145235 0.124592 26914 176310 -1 971 14 537 537 52525 12929 1.44227 1.44227 -66.651 -1.44227 0 0 926341. 3205.33 0.24 0.04 0.16 -1 -1 0.24 0.0115703 0.0100724 47 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_024bits.v common 4.08 vpr 62.10 MiB -1 -1 0.17 17524 1 0.02 -1 -1 30324 -1 -1 7 49 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63588 49 25 174 175 1 124 81 17 17 289 -1 unnamed_device 23.5 MiB 0.08 602 10056 2329 7462 265 62.1 MiB 0.06 0.00 2.11206 -78.5198 -2.11206 2.11206 0.68 0.000430072 0.000400231 0.0253041 0.0235722 34 1406 36 6.89349e+06 98656.9 618332. 2139.56 1.35 0.116771 0.10141 25762 151098 -1 1216 11 566 566 50636 12121 1.24467 1.24467 -73.5762 -1.24467 0 0 787024. 2723.27 0.21 0.03 0.14 -1 -1 0.21 0.0105211 0.00924665 50 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 3.99 vpr 61.96 MiB -1 -1 0.16 17572 1 0.02 -1 -1 30100 -1 -1 8 57 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63452 57 29 202 203 1 142 94 17 17 289 -1 unnamed_device 23.4 MiB 0.08 735 7975 1707 6009 259 62.0 MiB 0.06 0.00 2.15606 -94.8271 -2.15606 2.15606 0.68 0.000487556 0.000454494 0.0194204 0.0181076 34 1652 13 6.89349e+06 112751 618332. 2139.56 1.22 0.107832 0.0941081 25762 151098 -1 1422 12 657 657 62311 14519 1.26667 1.26667 -86.3714 -1.26667 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.0132587 0.0116877 58 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 4.10 vpr 62.23 MiB -1 -1 0.18 17400 1 0.02 -1 -1 30160 -1 -1 9 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63728 65 33 230 231 1 165 107 17 17 289 -1 unnamed_device 23.5 MiB 0.08 978 16046 4505 10523 1018 62.2 MiB 0.10 0.00 2.56039 -115.373 -2.56039 2.56039 0.68 0.000566344 0.000527588 0.0374318 0.0349269 34 2012 20 6.89349e+06 126845 618332. 2139.56 1.24 0.146585 0.129049 25762 151098 -1 1824 15 739 739 76313 16556 1.42297 1.42297 -105.171 -1.42297 0 0 787024. 2723.27 0.21 0.05 0.14 -1 -1 0.21 0.0176832 0.0156096 66 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 4.48 vpr 63.08 MiB -1 -1 0.15 17628 1 0.03 -1 -1 30272 -1 -1 13 97 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64592 97 49 342 343 1 247 159 17 17 289 -1 unnamed_device 24.1 MiB 0.11 1365 29399 8841 18664 1894 63.1 MiB 0.17 0.00 3.45705 -190.368 -3.45705 3.45705 0.67 0.000863648 0.000809352 0.0613637 0.0575136 34 3239 21 6.89349e+06 183220 618332. 2139.56 1.49 0.233748 0.209831 25762 151098 -1 2600 12 1016 1016 99325 23153 1.77997 1.77997 -168.573 -1.77997 0 0 787024. 2723.27 0.21 0.07 0.15 -1 -1 0.21 0.021962 0.0197184 98 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_064bits.v common 6.89 vpr 63.66 MiB -1 -1 0.20 18036 1 0.04 -1 -1 30528 -1 -1 17 129 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65184 129 65 454 455 1 329 211 17 17 289 -1 unnamed_device 24.7 MiB 0.12 1975 46609 14694 27844 4071 63.7 MiB 0.26 0.01 4.35372 -287.807 -4.35372 4.35372 0.68 0.00121008 0.00113985 0.0921106 0.0866821 36 4420 32 6.89349e+06 239595 648988. 2245.63 3.65 0.429033 0.387492 26050 158493 -1 3675 14 1471 1471 153704 34188 1.98497 1.98497 -234.187 -1.98497 0 0 828058. 2865.25 0.22 0.10 0.14 -1 -1 0.22 0.0341292 0.030824 130 2 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.81 vpr 61.53 MiB -1 -1 0.14 17176 2 0.05 -1 -1 31920 -1 -1 2 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63004 9 5 28 33 1 17 16 17 17 289 -1 unnamed_device 22.7 MiB 0.01 102 56 22 34 0 61.5 MiB 0.00 0.00 1.25905 -11.4776 -1.25905 1.25905 0.35 8.882e-05 8.0374e-05 0.000503367 0.000460617 -1 -1 -1 -1 20 177 7 6.55708e+06 24110 394039. 1363.46 0.24 0.00338036 0.00301975 19870 87366 -1 145 5 37 42 2127 683 1.13885 1.13885 -10.6853 -1.13885 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00234608 0.00214041 13 6 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.75 vpr 61.79 MiB -1 -1 0.15 17260 2 0.07 -1 -1 31784 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63268 11 6 34 40 1 20 19 17 17 289 -1 unnamed_device 23.1 MiB 0.01 68 419 92 314 13 61.8 MiB 0.01 0.00 1.13885 -12.6274 -1.13885 1.13885 0.36 0.000104018 9.4606e-05 0.00207701 0.00189506 -1 -1 -1 -1 20 166 5 6.55708e+06 24110 394039. 1363.46 0.25 0.00525114 0.0047588 19870 87366 -1 137 4 34 37 1601 538 1.01865 1.01865 -12.5587 -1.01865 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00240353 0.00219298 16 7 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.70 vpr 61.61 MiB -1 -1 0.12 17184 3 0.05 -1 -1 31860 -1 -1 3 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63088 13 7 41 48 1 27 23 17 17 289 -1 unnamed_device 22.9 MiB 0.01 135 631 147 469 15 61.6 MiB 0.01 0.00 1.37725 -16.6067 -1.37725 1.37725 0.32 0.000129747 0.00011854 0.00286597 0.002624 -1 -1 -1 -1 20 273 10 6.55708e+06 36165 394039. 1363.46 0.25 0.007305 0.00653074 19870 87366 -1 227 7 76 83 3857 1249 1.25705 1.25705 -17.2319 -1.25705 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0033876 0.00303842 19 9 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.80 vpr 61.52 MiB -1 -1 0.13 17272 3 0.04 -1 -1 31840 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62992 15 8 47 55 1 35 27 17 17 289 -1 unnamed_device 23.1 MiB 0.01 246 1107 227 797 83 61.5 MiB 0.01 0.00 1.23151 -21.1845 -1.23151 1.23151 0.32 0.000140574 0.000128754 0.00439077 0.0040239 -1 -1 -1 -1 22 399 8 6.55708e+06 48220 420624. 1455.45 0.33 0.0233791 0.0196844 20158 92377 -1 374 12 138 186 9733 2657 1.23151 1.23151 -21.7797 -1.23151 0 0 500653. 1732.36 0.02 0.01 0.05 -1 -1 0.02 0.00470751 0.00408781 23 10 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.98 vpr 61.69 MiB -1 -1 0.16 17380 3 0.05 -1 -1 32048 -1 -1 6 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63172 17 9 56 65 1 37 32 17 17 289 -1 unnamed_device 23.3 MiB 0.01 141 1132 207 843 82 61.7 MiB 0.01 0.00 1.73785 -23.0011 -1.73785 1.73785 0.32 0.000177397 0.000163282 0.00448382 0.00413693 -1 -1 -1 -1 26 292 10 6.55708e+06 72330 477104. 1650.88 0.34 0.0230579 0.0195262 21022 109990 -1 253 10 116 150 5905 2088 1.73785 1.73785 -22.979 -1.73785 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.00488895 0.00427019 26 14 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 2.00 vpr 61.60 MiB -1 -1 0.17 17588 4 0.08 -1 -1 31936 -1 -1 6 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63080 19 10 60 70 1 46 35 17 17 289 -1 unnamed_device 23.2 MiB 0.02 206 890 192 689 9 61.6 MiB 0.01 0.00 1.83817 -26.8738 -1.83817 1.83817 0.32 0.00018623 0.000172113 0.00345229 0.00318807 -1 -1 -1 -1 24 503 11 6.55708e+06 72330 448715. 1552.65 0.34 0.023586 0.0197806 20734 103517 -1 456 14 189 265 14696 4171 1.79897 1.79897 -29.1306 -1.79897 0 0 554710. 1919.41 0.02 0.02 0.09 -1 -1 0.02 0.00625358 0.00539304 29 13 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.85 vpr 61.68 MiB -1 -1 0.11 17620 4 0.06 -1 -1 31780 -1 -1 7 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63156 21 11 69 80 1 45 39 17 17 289 -1 unnamed_device 23.2 MiB 0.02 234 1425 276 1119 30 61.7 MiB 0.01 0.00 2.00308 -29.8235 -2.00308 2.00308 0.32 0.00021215 0.000195206 0.00517815 0.0047725 -1 -1 -1 -1 20 484 10 6.55708e+06 84385 394039. 1363.46 0.26 0.011519 0.0102836 19870 87366 -1 431 8 137 199 8705 2803 1.8657 1.8657 -30.3926 -1.8657 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00515178 0.00455678 33 17 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 2.06 vpr 61.65 MiB -1 -1 0.13 17464 5 0.06 -1 -1 32020 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63128 23 12 76 88 1 52 42 17 17 289 -1 unnamed_device 23.1 MiB 0.02 299 2130 460 1580 90 61.6 MiB 0.02 0.00 2.1851 -34.7155 -2.1851 2.1851 0.31 0.000225836 0.000208793 0.00737873 0.0068159 -1 -1 -1 -1 30 557 11 6.55708e+06 84385 526063. 1820.29 0.39 0.0385933 0.032892 21886 126133 -1 477 9 132 177 10121 2634 2.0649 2.0649 -34.6717 -2.0649 0 0 666494. 2306.21 0.03 0.01 0.10 -1 -1 0.03 0.0056861 0.00499978 36 19 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.97 vpr 61.68 MiB -1 -1 0.15 17448 5 0.06 -1 -1 32056 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63164 25 13 83 96 1 61 46 17 17 289 -1 unnamed_device 23.1 MiB 0.03 382 1604 307 1258 39 61.7 MiB 0.02 0.00 2.1433 -40.194 -2.1433 2.1433 0.32 0.0002374 0.000218617 0.00535399 0.0049428 -1 -1 -1 -1 20 750 24 6.55708e+06 96440 394039. 1363.46 0.28 0.0174527 0.0152737 19870 87366 -1 675 11 204 284 17644 4645 2.0231 2.0231 -41.4897 -2.0231 0 0 477104. 1650.88 0.02 0.02 0.08 -1 -1 0.02 0.00708701 0.00625295 39 21 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 1.98 vpr 61.82 MiB -1 -1 0.12 17548 5 0.06 -1 -1 31808 -1 -1 10 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 27 14 91 105 1 72 51 17 17 289 -1 unnamed_device 23.2 MiB 0.05 487 1931 345 1368 218 61.8 MiB 0.02 0.00 2.31696 -45.6334 -2.31696 2.31696 0.32 0.000303653 0.000273882 0.00640562 0.00591371 -1 -1 -1 -1 26 873 12 6.55708e+06 120550 477104. 1650.88 0.36 0.0365231 0.0313217 21022 109990 -1 816 8 208 332 18433 4780 1.9839 1.9839 -46.0894 -1.9839 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00631768 0.005585 44 24 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.92 vpr 61.82 MiB -1 -1 0.15 17672 6 0.07 -1 -1 32032 -1 -1 10 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 29 15 95 110 1 74 54 17 17 289 -1 unnamed_device 23.2 MiB 0.03 326 1992 324 1638 30 61.8 MiB 0.02 0.00 2.92362 -47.3926 -2.92362 2.92362 0.32 0.000283404 0.000262906 0.00638465 0.00592117 -1 -1 -1 -1 26 681 9 6.55708e+06 120550 477104. 1650.88 0.29 0.0229025 0.019846 21022 109990 -1 645 14 253 412 18759 5604 2.76422 2.76422 -48.0089 -2.76422 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00906397 0.00783781 46 23 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.02 vpr 61.88 MiB -1 -1 0.17 17476 6 0.07 -1 -1 31980 -1 -1 10 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63364 31 16 104 120 1 74 57 17 17 289 -1 unnamed_device 23.2 MiB 0.03 413 2455 496 1792 167 61.9 MiB 0.02 0.00 2.5437 -52.0473 -2.5437 2.5437 0.32 0.000314967 0.000292737 0.00803663 0.00746438 -1 -1 -1 -1 28 797 9 6.55708e+06 120550 500653. 1732.36 0.37 0.0394837 0.0339214 21310 115450 -1 706 7 169 223 12972 3468 2.5437 2.5437 -53.9588 -2.5437 0 0 612192. 2118.31 0.03 0.02 0.10 -1 -1 0.03 0.0066224 0.00586415 50 27 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_016bits.v common 1.89 vpr 61.88 MiB -1 -1 0.17 17512 7 0.07 -1 -1 32112 -1 -1 10 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63364 33 17 112 129 1 80 60 17 17 289 -1 unnamed_device 23.1 MiB 0.03 455 2400 450 1872 78 61.9 MiB 0.01 0.00 2.77173 -56.4743 -2.77173 2.77173 0.28 0.000151138 0.000138573 0.00382632 0.0035109 -1 -1 -1 -1 22 966 13 6.55708e+06 120550 420624. 1455.45 0.24 0.0223788 0.0192259 20158 92377 -1 820 14 243 337 17062 5047 2.6619 2.6619 -58.7642 -2.6619 0 0 500653. 1732.36 0.02 0.02 0.08 -1 -1 0.02 0.010673 0.0092982 54 30 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.09 vpr 61.96 MiB -1 -1 0.17 17540 7 0.06 -1 -1 31948 -1 -1 13 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63444 37 19 127 146 1 95 69 17 17 289 -1 unnamed_device 23.1 MiB 0.04 580 5286 1128 3575 583 62.0 MiB 0.04 0.00 2.83296 -65.8925 -2.83296 2.83296 0.32 0.000370259 0.000344095 0.0149742 0.013844 -1 -1 -1 -1 28 987 8 6.55708e+06 156715 500653. 1732.36 0.38 0.0517571 0.0451646 21310 115450 -1 947 6 224 327 15796 4347 2.6201 2.6201 -68.3998 -2.6201 0 0 612192. 2118.31 0.03 0.02 0.10 -1 -1 0.03 0.00692764 0.00618013 63 35 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.16 vpr 61.99 MiB -1 -1 0.15 17432 8 0.07 -1 -1 31996 -1 -1 14 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63480 41 21 139 160 1 106 76 17 17 289 -1 unnamed_device 22.9 MiB 0.04 588 8396 2008 5342 1046 62.0 MiB 0.05 0.00 3.1799 -77.5868 -3.1799 3.1799 0.34 0.000399995 0.000371199 0.0222085 0.0206233 -1 -1 -1 -1 26 1120 12 6.55708e+06 168770 477104. 1650.88 0.38 0.0643844 0.0565876 21022 109990 -1 1022 10 319 425 23447 6363 3.1799 3.1799 -79.2365 -3.1799 0 0 585099. 2024.56 0.03 0.02 0.12 -1 -1 0.03 0.00931512 0.00841851 67 37 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.19 vpr 62.45 MiB -1 -1 0.13 17484 9 0.07 -1 -1 31884 -1 -1 15 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63948 45 23 153 176 1 107 83 17 17 289 -1 unnamed_device 23.1 MiB 0.05 536 7643 1816 4897 930 62.4 MiB 0.05 0.00 4.01419 -88.5998 -4.01419 4.01419 0.32 0.000435711 0.000404292 0.0198098 0.0183771 -1 -1 -1 -1 26 1149 13 6.55708e+06 180825 477104. 1650.88 0.44 0.0661535 0.0580745 21022 109990 -1 1003 13 321 492 25700 7436 3.87922 3.87922 -89.4779 -3.87922 0 0 585099. 2024.56 0.03 0.03 0.10 -1 -1 0.03 0.0114958 0.0102772 73 41 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.19 vpr 62.10 MiB -1 -1 0.13 17776 10 0.07 -1 -1 32012 -1 -1 15 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63588 49 25 166 191 1 117 89 17 17 289 -1 unnamed_device 22.7 MiB 0.04 524 8207 1797 5151 1259 62.1 MiB 0.05 0.00 4.48062 -100.236 -4.48062 4.48062 0.32 0.000471573 0.000438453 0.0210235 0.0195468 -1 -1 -1 -1 26 1157 12 6.55708e+06 180825 477104. 1650.88 0.44 0.070761 0.0623165 21022 109990 -1 1039 10 321 455 24838 7158 4.40948 4.40948 -103.002 -4.40948 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.0115319 0.01024 78 44 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.40 vpr 62.41 MiB -1 -1 0.16 17836 11 0.07 -1 -1 32112 -1 -1 20 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63908 57 29 198 227 1 147 106 17 17 289 -1 unnamed_device 23.0 MiB 0.05 782 8606 1708 6393 505 62.4 MiB 0.06 0.00 4.94665 -134.466 -4.94665 4.94665 0.33 0.000571874 0.000532504 0.0215301 0.0200481 -1 -1 -1 -1 28 1522 13 6.55708e+06 241100 500653. 1732.36 0.43 0.0827513 0.0729032 21310 115450 -1 1371 8 367 517 27034 7537 4.59642 4.59642 -133.949 -4.59642 0 0 612192. 2118.31 0.03 0.03 0.11 -1 -1 0.03 0.0120118 0.0107143 93 56 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.50 vpr 62.60 MiB -1 -1 0.19 17800 13 0.08 -1 -1 32188 -1 -1 20 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 65 33 224 257 1 164 118 17 17 289 -1 unnamed_device 22.9 MiB 0.06 928 17169 4443 10653 2073 62.6 MiB 0.10 0.00 5.28408 -153.681 -5.28408 5.28408 0.36 0.000649312 0.000604542 0.0408491 0.0380181 -1 -1 -1 -1 30 1659 12 6.55708e+06 241100 526063. 1820.29 0.47 0.109688 0.0977858 21886 126133 -1 1555 13 429 584 31745 8729 5.08288 5.08288 -153.594 -5.08288 0 0 666494. 2306.21 0.04 0.03 0.12 -1 -1 0.04 0.016224 0.0145393 107 62 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.63 vpr 63.23 MiB -1 -1 0.20 18112 19 0.10 -1 -1 32232 -1 -1 34 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 97 49 340 389 1 260 180 17 17 289 -1 unnamed_device 23.4 MiB 0.10 1520 22532 5263 15517 1752 63.2 MiB 0.13 0.00 7.62655 -301.388 -7.62655 7.62655 0.29 0.000991752 0.000926486 0.0481233 0.0448481 -1 -1 -1 -1 30 2687 13 6.55708e+06 409870 526063. 1820.29 0.51 0.154423 0.138579 21886 126133 -1 2432 11 662 955 55712 14661 7.28333 7.28333 -297.521 -7.28333 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0249464 0.0224501 165 98 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.24 vpr 63.93 MiB -1 -1 0.28 18296 26 0.13 -1 -1 32396 -1 -1 41 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65464 129 65 453 518 1 334 235 17 17 289 -1 unnamed_device 24.1 MiB 0.10 1951 55259 16458 32932 5869 63.9 MiB 0.28 0.00 10.6369 -487.594 -10.6369 10.6369 0.34 0.00134162 0.00125451 0.10975 0.102432 -1 -1 -1 -1 30 3742 35 6.55708e+06 494255 526063. 1820.29 0.78 0.289369 0.262587 21886 126133 -1 3039 12 909 1148 67590 18881 10.0187 10.0187 -472.64 -10.0187 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0361792 0.0327806 210 131 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.49 abc 29.28 MiB -1 -1 0.10 17348 1 0.02 -1 -1 29980 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23980 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.58 abc 29.28 MiB -1 -1 0.12 17328 1 0.03 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23928 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.66 abc 29.27 MiB -1 -1 0.14 17352 1 0.02 -1 -1 29972 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24144 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.66 abc 29.22 MiB -1 -1 0.14 17312 1 0.02 -1 -1 29924 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24024 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.63 abc 29.30 MiB -1 -1 0.14 17436 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23980 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.61 abc 29.30 MiB -1 -1 0.15 17384 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24072 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.58 abc 29.34 MiB -1 -1 0.16 17320 1 0.03 -1 -1 30048 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23932 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.55 abc 29.36 MiB -1 -1 0.14 17188 1 0.02 -1 -1 30068 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24076 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.83 abc 29.29 MiB -1 -1 0.16 17156 1 0.02 -1 -1 29992 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23980 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.67 abc 29.23 MiB -1 -1 0.15 17352 1 0.02 -1 -1 29936 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23964 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.64 abc 29.44 MiB -1 -1 0.15 17296 1 0.02 -1 -1 30144 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24080 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.82 abc 29.46 MiB -1 -1 0.16 17372 1 0.02 -1 -1 30164 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24028 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.90 abc 29.28 MiB -1 -1 0.16 17348 1 0.02 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24032 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.13 abc 29.58 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30288 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24004 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 1.11 abc 29.28 MiB -1 -1 0.15 17584 1 0.03 -1 -1 29980 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24108 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 1.33 abc 29.30 MiB -1 -1 0.15 17496 1 0.04 -1 -1 30004 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24068 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 1.13 abc 29.30 MiB -1 -1 0.16 17684 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24012 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.59 abc 29.43 MiB -1 -1 0.16 17528 1 0.02 -1 -1 30140 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24212 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.61 abc 29.43 MiB -1 -1 0.14 17660 1 0.03 -1 -1 30136 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24056 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.60 abc 29.41 MiB -1 -1 0.12 17788 1 0.03 -1 -1 30116 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24088 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 1.42 abc 29.55 MiB -1 -1 0.21 18072 1 0.03 -1 -1 30256 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24028 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.58 abc 29.32 MiB -1 -1 0.15 17340 1 0.02 -1 -1 30024 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23756 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.56 abc 29.36 MiB -1 -1 0.14 17204 1 0.02 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23848 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.46 abc 29.20 MiB -1 -1 0.08 17420 1 0.02 -1 -1 29904 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23768 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.55 abc 29.36 MiB -1 -1 0.16 17368 1 0.02 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23832 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.50 abc 29.30 MiB -1 -1 0.11 17336 1 0.03 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23792 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.56 abc 29.30 MiB -1 -1 0.14 17268 1 0.02 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23780 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.64 abc 29.29 MiB -1 -1 0.15 17364 1 0.03 -1 -1 29996 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23676 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.77 abc 29.50 MiB -1 -1 0.15 17480 1 0.02 -1 -1 30208 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23908 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.87 abc 29.35 MiB -1 -1 0.13 17308 1 0.03 -1 -1 30056 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23860 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.78 abc 29.34 MiB -1 -1 0.15 17316 1 0.02 -1 -1 30044 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23840 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.90 abc 29.28 MiB -1 -1 0.13 17320 1 0.03 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23792 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.55 abc 29.28 MiB -1 -1 0.15 17412 1 0.02 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23760 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.57 abc 29.43 MiB -1 -1 0.14 17428 1 0.02 -1 -1 30136 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23804 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.59 abc 29.38 MiB -1 -1 0.15 17580 1 0.02 -1 -1 30084 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23888 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.59 abc 29.28 MiB -1 -1 0.16 17688 1 0.02 -1 -1 29980 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23704 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.54 abc 29.29 MiB -1 -1 0.14 17696 1 0.02 -1 -1 29988 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23960 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.53 abc 29.36 MiB -1 -1 0.09 17412 1 0.02 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23772 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.64 abc 29.38 MiB -1 -1 0.15 17288 1 0.03 -1 -1 30088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23700 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.68 abc 29.30 MiB -1 -1 0.17 17596 1 0.03 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23696 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.67 abc 29.53 MiB -1 -1 0.14 17704 1 0.03 -1 -1 30236 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23772 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.81 abc 29.84 MiB -1 -1 0.22 18144 1 0.04 -1 -1 30556 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23768 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.67 vpr 61.95 MiB -1 -1 0.09 17252 1 0.03 -1 -1 30116 -1 -1 3 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63432 9 5 34 35 1 20 17 17 17 289 -1 unnamed_device 23.2 MiB 0.01 145 80 29 46 5 61.9 MiB 0.00 0.00 0.83871 -12.0914 -0.83871 0.83871 0.32 8.9493e-05 8.1196e-05 0.000627793 0.000575929 -1 -1 -1 -1 20 218 6 6.64007e+06 37674 394039. 1363.46 0.25 0.00366787 0.00331915 20530 87850 -1 213 8 56 56 3444 969 0.890248 0.890248 -12.2124 -0.890248 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0028001 0.00250588 14 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.81 vpr 61.82 MiB -1 -1 0.15 17384 1 0.02 -1 -1 29928 -1 -1 4 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 11 6 41 42 1 26 21 17 17 289 -1 unnamed_device 23.1 MiB 0.01 179 525 133 355 37 61.8 MiB 0.01 0.00 0.803048 -13.1622 -0.803048 0.803048 0.33 0.000104816 9.5546e-05 0.00232117 0.00211796 -1 -1 -1 -1 20 294 8 6.64007e+06 50232 394039. 1363.46 0.25 0.00578063 0.00517738 20530 87850 -1 279 8 74 74 5640 1476 0.923248 0.923248 -15.592 -0.923248 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00307315 0.00274174 17 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.86 vpr 61.86 MiB -1 -1 0.14 17352 1 0.02 -1 -1 30052 -1 -1 5 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63344 13 7 48 49 1 32 25 17 17 289 -1 unnamed_device 23.5 MiB 0.01 158 889 183 672 34 61.9 MiB 0.01 0.00 0.825048 -14.9551 -0.825048 0.825048 0.32 0.00012299 0.000112599 0.00344711 0.00315992 -1 -1 -1 -1 22 332 15 6.64007e+06 62790 420624. 1455.45 0.31 0.0177773 0.0149893 20818 92861 -1 288 10 103 103 5874 1694 0.934248 0.934248 -16.7505 -0.934248 0 0 500653. 1732.36 0.02 0.01 0.08 -1 -1 0.02 0.00384738 0.00340089 20 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.89 vpr 61.98 MiB -1 -1 0.15 17472 1 0.02 -1 -1 30136 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63468 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 23.6 MiB 0.02 130 827 161 522 144 62.0 MiB 0.01 0.00 1.18536 -16.9426 -1.18536 1.18536 0.32 0.000141038 0.000129717 0.00333865 0.00306739 -1 -1 -1 -1 22 336 15 6.64007e+06 50232 420624. 1455.45 0.34 0.0179109 0.0151424 20818 92861 -1 281 7 118 118 7761 2504 1.08545 1.08545 -19.5322 -1.08545 0 0 500653. 1732.36 0.02 0.01 0.08 -1 -1 0.02 0.0039426 0.00354868 22 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 2.04 vpr 61.95 MiB -1 -1 0.14 17348 1 0.02 -1 -1 30048 -1 -1 5 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63440 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 23.5 MiB 0.02 156 1759 570 827 362 62.0 MiB 0.02 0.00 1.19636 -19.8289 -1.19636 1.19636 0.32 0.000158366 0.000145724 0.00632531 0.00582349 -1 -1 -1 -1 32 266 11 6.64007e+06 62790 554710. 1919.41 0.38 0.0232912 0.0199009 22834 132086 -1 249 10 97 97 4881 1477 0.834048 0.834048 -18.8492 -0.834048 0 0 701300. 2426.64 0.03 0.01 0.11 -1 -1 0.03 0.00447744 0.00392841 25 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.90 vpr 61.86 MiB -1 -1 0.14 17316 1 0.03 -1 -1 30144 -1 -1 5 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63348 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 23.4 MiB 0.02 160 1574 392 922 260 61.9 MiB 0.02 0.00 1.20736 -22.28 -1.20736 1.20736 0.31 0.000177199 0.000163665 0.00559114 0.00516294 -1 -1 -1 -1 22 389 20 6.64007e+06 62790 420624. 1455.45 0.33 0.0271204 0.0230692 20818 92861 -1 335 13 170 170 11128 3516 1.05245 1.05245 -23.8346 -1.05245 0 0 500653. 1732.36 0.03 0.02 0.09 -1 -1 0.03 0.00547305 0.00480176 28 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.93 vpr 62.00 MiB -1 -1 0.15 17268 1 0.03 -1 -1 30160 -1 -1 6 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63488 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 23.4 MiB 0.02 326 2054 512 1388 154 62.0 MiB 0.02 0.00 1.21836 -28.0305 -1.21836 1.21836 0.32 0.000193986 0.000179202 0.0069198 0.00639758 -1 -1 -1 -1 26 550 12 6.64007e+06 75348 477104. 1650.88 0.35 0.0275302 0.0234892 21682 110474 -1 504 11 163 163 10372 2794 1.00925 1.00925 -29.7279 -1.00925 0 0 585099. 2024.56 0.03 0.02 0.10 -1 -1 0.03 0.00561273 0.00490548 31 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.92 vpr 62.17 MiB -1 -1 0.10 17364 1 0.03 -1 -1 30004 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63660 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 23.5 MiB 0.02 202 2274 577 1358 339 62.2 MiB 0.02 0.00 1.22936 -27.3302 -1.22936 1.22936 0.32 0.000217044 0.000200805 0.00744746 0.00689241 -1 -1 -1 -1 26 516 20 6.64007e+06 87906 477104. 1650.88 0.37 0.03361 0.0286167 21682 110474 -1 423 19 254 254 15495 4842 1.14165 1.14165 -28.5397 -1.14165 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00847906 0.00723997 35 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 2.03 vpr 62.03 MiB -1 -1 0.13 17356 1 0.02 -1 -1 30120 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63516 25 13 90 91 1 61 46 17 17 289 -1 unnamed_device 23.5 MiB 0.02 225 3162 1067 1505 590 62.0 MiB 0.03 0.00 1.24036 -30.3091 -1.24036 1.24036 0.32 0.000223716 0.000206705 0.00935455 0.00864973 -1 -1 -1 -1 28 585 26 6.64007e+06 100464 500653. 1732.36 0.41 0.0378559 0.0324088 21970 115934 -1 409 25 362 362 24657 7379 1.02145 1.02145 -29.5255 -1.02145 0 0 612192. 2118.31 0.04 0.03 0.10 -1 -1 0.04 0.00908575 0.00781132 38 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.07 vpr 62.03 MiB -1 -1 0.15 17336 1 0.02 -1 -1 30088 -1 -1 9 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63520 27 14 97 98 1 67 50 17 17 289 -1 unnamed_device 23.5 MiB 0.02 251 4650 1464 2253 933 62.0 MiB 0.03 0.00 1.25136 -32.7881 -1.25136 1.25136 0.32 0.000239703 0.00022173 0.0129775 0.0119987 -1 -1 -1 -1 32 519 22 6.64007e+06 113022 554710. 1919.41 0.41 0.0419733 0.0362927 22834 132086 -1 437 14 276 276 16327 5300 1.03125 1.03125 -33.0873 -1.03125 0 0 701300. 2426.64 0.03 0.02 0.12 -1 -1 0.03 0.00771732 0.00669493 41 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.96 vpr 62.14 MiB -1 -1 0.15 17348 1 0.02 -1 -1 29924 -1 -1 9 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63628 29 15 104 105 1 73 53 17 17 289 -1 unnamed_device 23.5 MiB 0.01 462 4409 1391 2113 905 62.1 MiB 0.03 0.00 1.26236 -39.7652 -1.26236 1.26236 0.32 0.000252152 0.000233455 0.012075 0.0111778 -1 -1 -1 -1 26 812 23 6.64007e+06 113022 477104. 1650.88 0.39 0.0429496 0.0370839 21682 110474 -1 713 17 323 323 26583 6736 1.03125 1.03125 -39.6574 -1.03125 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.00919565 0.00794342 44 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.09 vpr 62.16 MiB -1 -1 0.15 17408 1 0.02 -1 -1 30248 -1 -1 9 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63656 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 23.5 MiB 0.03 343 4978 1636 2249 1093 62.2 MiB 0.04 0.00 1.62267 -39.5838 -1.62267 1.62267 0.30 0.000273462 0.000253412 0.0135717 0.0125654 -1 -1 -1 -1 30 686 17 6.64007e+06 113022 526063. 1820.29 0.40 0.0434449 0.0377212 22546 126617 -1 539 11 219 219 10604 3260 0.95891 0.95891 -36.3522 -0.95891 0 0 666494. 2306.21 0.03 0.02 0.10 -1 -1 0.03 0.00745402 0.00655316 46 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.01 vpr 62.13 MiB -1 -1 0.08 17640 1 0.02 -1 -1 30132 -1 -1 9 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63624 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 23.4 MiB 0.03 352 6329 2210 2989 1130 62.1 MiB 0.04 0.00 1.63367 -42.2226 -1.63367 1.63367 0.32 0.000292013 0.000271082 0.0171275 0.0158779 -1 -1 -1 -1 28 736 12 6.64007e+06 113022 500653. 1732.36 0.42 0.0478919 0.0418393 21970 115934 -1 618 18 335 335 18999 5605 1.21545 1.21545 -44.5486 -1.21545 0 0 612192. 2118.31 0.03 0.03 0.08 -1 -1 0.03 0.0108162 0.00934396 49 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.08 vpr 62.25 MiB -1 -1 0.14 17540 1 0.02 -1 -1 30084 -1 -1 11 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63740 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 23.5 MiB 0.03 393 6867 2746 3975 146 62.2 MiB 0.05 0.00 1.65567 -49.3018 -1.65567 1.65567 0.32 0.000329974 0.000306635 0.0176624 0.0164096 -1 -1 -1 -1 30 805 15 6.64007e+06 138138 526063. 1820.29 0.41 0.0534439 0.0465752 22546 126617 -1 630 14 325 325 20407 5991 1.07325 1.07325 -45.7613 -1.07325 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.0100761 0.0087606 55 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.04 vpr 62.60 MiB -1 -1 0.13 17640 1 0.03 -1 -1 30388 -1 -1 13 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 41 21 146 147 1 102 75 17 17 289 -1 unnamed_device 23.3 MiB 0.02 587 9239 3659 4903 677 62.6 MiB 0.06 0.00 1.67767 -57.8173 -1.67767 1.67767 0.32 0.000360642 0.000335237 0.0220756 0.0205309 -1 -1 -1 -1 30 1014 13 6.64007e+06 163254 526063. 1820.29 0.42 0.0603789 0.0531045 22546 126617 -1 868 10 304 304 26082 6742 1.02025 1.02025 -52.0508 -1.02025 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.00886711 0.00781227 62 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.27 vpr 62.54 MiB -1 -1 0.16 17708 1 0.02 -1 -1 30284 -1 -1 14 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64044 45 23 160 161 1 114 82 17 17 289 -1 unnamed_device 23.2 MiB 0.03 505 10228 3751 5231 1246 62.5 MiB 0.06 0.00 1.69967 -61.6923 -1.69967 1.69967 0.32 0.000396366 0.000369082 0.0236606 0.0219962 -1 -1 -1 -1 32 1098 29 6.64007e+06 175812 554710. 1919.41 0.53 0.0745634 0.0654141 22834 132086 -1 841 14 524 524 35053 10407 1.18565 1.18565 -55.6154 -1.18565 0 0 701300. 2426.64 0.03 0.03 0.11 -1 -1 0.03 0.0118029 0.0103314 68 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.22 vpr 62.62 MiB -1 -1 0.14 17656 1 0.03 -1 -1 30336 -1 -1 14 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64128 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 23.3 MiB 0.04 715 8278 1733 6367 178 62.6 MiB 0.06 0.00 2.07098 -71.4065 -2.07098 2.07098 0.32 0.000425886 0.000396892 0.0193216 0.0179715 -1 -1 -1 -1 30 1249 15 6.64007e+06 175812 526063. 1820.29 0.44 0.0656005 0.0577432 22546 126617 -1 1106 11 343 343 25695 6324 1.09525 1.09525 -65.1787 -1.09525 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.0113828 0.0101237 73 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.31 vpr 62.69 MiB -1 -1 0.16 17512 1 0.03 -1 -1 30076 -1 -1 18 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64196 57 29 202 203 1 143 104 17 17 289 -1 unnamed_device 23.3 MiB 0.04 774 16452 3708 11655 1089 62.7 MiB 0.10 0.00 2.11498 -86.7435 -2.11498 2.11498 0.32 0.000485084 0.000450927 0.0341069 0.0317077 -1 -1 -1 -1 32 1465 18 6.64007e+06 226044 554710. 1919.41 0.49 0.0895901 0.0796678 22834 132086 -1 1213 17 542 542 36079 10159 1.35645 1.35645 -81.4884 -1.35645 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.016593 0.0145733 86 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.38 vpr 62.91 MiB -1 -1 0.18 17672 1 0.03 -1 -1 30064 -1 -1 19 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64424 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 23.3 MiB 0.05 1165 18135 6420 10093 1622 62.9 MiB 0.11 0.00 2.50829 -108.778 -2.50829 2.50829 0.32 0.0005667 0.000528433 0.0374509 0.0349335 -1 -1 -1 -1 30 1825 43 6.64007e+06 238602 526063. 1820.29 0.51 0.122573 0.10861 22546 126617 -1 1603 14 500 500 39832 9325 1.21425 1.21425 -91.6209 -1.21425 0 0 666494. 2306.21 0.03 0.04 0.10 -1 -1 0.03 0.016578 0.0146599 97 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.65 vpr 63.45 MiB -1 -1 0.17 17900 1 0.03 -1 -1 30280 -1 -1 29 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64976 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 23.9 MiB 0.07 1660 32449 9442 20195 2812 63.5 MiB 0.20 0.00 3.38291 -180.139 -3.38291 3.38291 0.32 0.000868353 0.000813665 0.0603321 0.056479 -1 -1 -1 -1 30 2741 24 6.64007e+06 364182 526063. 1820.29 0.58 0.167976 0.151769 22546 126617 -1 2404 13 827 827 63818 16162 1.39605 1.39605 -140.523 -1.39605 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0236694 0.0212549 145 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 2.96 vpr 63.93 MiB -1 -1 0.19 18156 1 0.03 -1 -1 30516 -1 -1 39 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65460 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 24.4 MiB 0.11 2246 49637 16069 29592 3976 63.9 MiB 0.33 0.01 4.25753 -269.223 -4.25753 4.25753 0.32 0.00123279 0.00116168 0.0889312 0.0837218 -1 -1 -1 -1 32 3518 14 6.64007e+06 489762 554710. 1919.41 0.66 0.226555 0.20755 22834 132086 -1 3131 12 959 959 74779 19366 1.56805 1.56805 -190.941 -1.56805 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0304292 0.0275916 193 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.70 vpr 61.73 MiB -1 -1 0.12 17344 1 0.03 -1 -1 29928 -1 -1 3 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63216 9 5 34 35 1 20 17 17 17 289 -1 unnamed_device 22.9 MiB 0.01 148 80 29 46 5 61.7 MiB 0.00 0.00 0.83871 -11.7447 -0.83871 0.83871 0.32 8.8927e-05 8.028e-05 0.000604437 0.000548194 -1 -1 -1 -1 20 230 8 6.65987e+06 38034 394039. 1363.46 0.25 0.00388017 0.00347642 20530 87850 -1 214 10 61 61 5414 1452 0.83871 0.83871 -11.8866 -0.83871 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0031468 0.00280409 14 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.72 vpr 61.69 MiB -1 -1 0.14 17312 1 0.02 -1 -1 29920 -1 -1 4 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63168 11 6 41 42 1 26 21 17 17 289 -1 unnamed_device 23.0 MiB 0.01 189 525 130 355 40 61.7 MiB 0.01 0.00 0.803048 -13.1363 -0.803048 0.803048 0.32 0.000104272 9.5105e-05 0.00233488 0.00212885 -1 -1 -1 -1 20 304 9 6.65987e+06 50712 394039. 1363.46 0.26 0.00586479 0.00523143 20530 87850 -1 282 10 105 105 8718 2335 0.83871 0.83871 -14.5944 -0.83871 0 0 477104. 1650.88 0.03 0.01 0.08 -1 -1 0.03 0.00378422 0.00342251 17 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.86 vpr 61.82 MiB -1 -1 0.13 17280 1 0.02 -1 -1 29868 -1 -1 5 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 13 7 48 49 1 32 25 17 17 289 -1 unnamed_device 23.4 MiB 0.01 147 1105 244 814 47 61.8 MiB 0.01 0.00 0.830189 -14.844 -0.830189 0.830189 0.33 0.00012577 0.000112704 0.00426613 0.00390409 -1 -1 -1 -1 26 305 15 6.65987e+06 63390 477104. 1650.88 0.34 0.0191538 0.0162467 21682 110474 -1 272 12 128 128 8327 2403 0.950389 0.950389 -16.4625 -0.950389 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.00423977 0.00371064 20 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 2.02 vpr 61.80 MiB -1 -1 0.16 17392 1 0.02 -1 -1 30000 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63288 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 23.4 MiB 0.01 132 947 214 545 188 61.8 MiB 0.01 0.00 1.20253 -16.9819 -1.20253 1.20253 0.34 0.00014165 0.000130082 0.00397733 0.00363354 -1 -1 -1 -1 32 286 17 6.65987e+06 50712 554710. 1919.41 0.38 0.0203804 0.0172185 22834 132086 -1 207 12 103 103 5880 1787 0.856048 0.856048 -16.2356 -0.856048 0 0 701300. 2426.64 0.03 0.01 0.11 -1 -1 0.03 0.00468142 0.00409653 22 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.96 vpr 61.77 MiB -1 -1 0.14 17420 1 0.02 -1 -1 30048 -1 -1 5 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63256 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 23.4 MiB 0.02 169 1039 221 683 135 61.8 MiB 0.01 0.00 1.19636 -19.6785 -1.19636 1.19636 0.34 0.000160216 0.000147534 0.00392966 0.00362469 -1 -1 -1 -1 30 342 14 6.65987e+06 63390 526063. 1820.29 0.37 0.0217562 0.0183847 22546 126617 -1 290 13 143 143 7116 2212 0.823048 0.823048 -19.6378 -0.823048 0 0 666494. 2306.21 0.03 0.01 0.10 -1 -1 0.03 0.00533708 0.00464817 25 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.96 vpr 61.78 MiB -1 -1 0.10 17400 1 0.02 -1 -1 30056 -1 -1 5 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63264 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 23.3 MiB 0.02 158 1684 407 960 317 61.8 MiB 0.02 0.00 1.20736 -22.0789 -1.20736 1.20736 0.32 0.000176486 0.000162987 0.00597002 0.0055165 -1 -1 -1 -1 30 316 15 6.65987e+06 63390 526063. 1820.29 0.37 0.0258595 0.0220154 22546 126617 -1 281 20 183 183 9032 2990 1.07445 1.07445 -22.6488 -1.07445 0 0 666494. 2306.21 0.05 0.02 0.14 -1 -1 0.05 0.00796327 0.00683749 28 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.96 vpr 61.98 MiB -1 -1 0.14 17436 1 0.02 -1 -1 30148 -1 -1 6 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63472 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 23.4 MiB 0.02 335 1865 426 1314 125 62.0 MiB 0.02 0.00 1.21836 -28.0156 -1.21836 1.21836 0.32 0.000195988 0.000181389 0.00640653 0.00592412 -1 -1 -1 -1 26 555 11 6.65987e+06 76068 477104. 1650.88 0.35 0.0272629 0.0232932 21682 110474 -1 547 16 214 214 18567 4835 1.08545 1.08545 -31.2059 -1.08545 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00706697 0.00607694 31 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 2.03 vpr 62.06 MiB -1 -1 0.16 17404 1 0.02 -1 -1 30128 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63552 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 23.4 MiB 0.02 204 3498 1194 1551 753 62.1 MiB 0.03 0.00 1.22936 -27.6572 -1.22936 1.22936 0.32 0.000212462 0.000196166 0.0109339 0.0101005 -1 -1 -1 -1 30 454 21 6.65987e+06 88746 526063. 1820.29 0.39 0.0363204 0.0312013 22546 126617 -1 361 18 221 221 11264 3655 1.04739 1.04739 -26.9812 -1.04739 0 0 666494. 2306.21 0.03 0.02 0.10 -1 -1 0.03 0.00812448 0.00696129 35 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.99 vpr 61.94 MiB -1 -1 0.15 17252 1 0.02 -1 -1 29996 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63428 25 13 90 91 1 61 46 17 17 289 -1 unnamed_device 23.4 MiB 0.02 266 3244 1063 1597 584 61.9 MiB 0.03 0.00 1.24036 -31.1975 -1.24036 1.24036 0.32 0.000180091 0.000164931 0.00943785 0.00872483 -1 -1 -1 -1 28 564 34 6.65987e+06 101424 500653. 1732.36 0.43 0.046281 0.0393218 21970 115934 -1 503 13 227 227 15114 4347 1.14045 1.14045 -33.3649 -1.14045 0 0 612192. 2118.31 0.03 0.02 0.11 -1 -1 0.03 0.00698344 0.00607333 38 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.09 vpr 62.05 MiB -1 -1 0.15 17416 1 0.02 -1 -1 29976 -1 -1 9 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63544 27 14 97 98 1 67 50 17 17 289 -1 unnamed_device 23.4 MiB 0.02 267 4650 1648 2149 853 62.1 MiB 0.04 0.00 1.25136 -33.284 -1.25136 1.25136 0.32 0.000283328 0.000262351 0.0142241 0.0131692 -1 -1 -1 -1 32 627 21 6.65987e+06 114102 554710. 1919.41 0.42 0.0429261 0.0372136 22834 132086 -1 519 21 333 333 18881 5985 1.12945 1.12945 -35.2713 -1.12945 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0149715 0.0126565 41 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 2.07 vpr 61.92 MiB -1 -1 0.15 17644 1 0.02 -1 -1 29984 -1 -1 9 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63408 29 15 104 105 1 73 53 17 17 289 -1 unnamed_device 23.3 MiB 0.02 324 3518 788 2107 623 61.9 MiB 0.03 0.00 1.26236 -35.6797 -1.26236 1.26236 0.32 0.000253071 0.000234583 0.00979541 0.0090734 -1 -1 -1 -1 30 698 25 6.65987e+06 114102 526063. 1820.29 0.42 0.0425967 0.0366082 22546 126617 -1 520 15 327 327 17260 5451 1.02039 1.02039 -33.4205 -1.02039 0 0 666494. 2306.21 0.03 0.02 0.08 -1 -1 0.03 0.00850795 0.00740024 44 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.14 vpr 61.97 MiB -1 -1 0.16 17636 1 0.02 -1 -1 30264 -1 -1 9 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63460 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 23.3 MiB 0.02 363 4978 1495 2401 1082 62.0 MiB 0.04 0.00 1.62267 -39.2597 -1.62267 1.62267 0.32 0.000271456 0.000251613 0.0137065 0.0126797 -1 -1 -1 -1 28 787 18 6.65987e+06 114102 500653. 1732.36 0.43 0.0450106 0.0390537 21970 115934 -1 646 20 384 384 28172 7864 1.10039 1.10039 -40.1031 -1.10039 0 0 612192. 2118.31 0.03 0.03 0.10 -1 -1 0.03 0.0116488 0.010003 46 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.15 vpr 61.95 MiB -1 -1 0.15 17460 1 0.02 -1 -1 30056 -1 -1 9 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63440 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 23.3 MiB 0.02 358 6329 2576 3638 115 62.0 MiB 0.05 0.00 1.63367 -43.0819 -1.63367 1.63367 0.32 0.000297215 0.00027577 0.0173583 0.0161231 -1 -1 -1 -1 30 697 17 6.65987e+06 114102 526063. 1820.29 0.41 0.0506732 0.0443138 22546 126617 -1 563 18 309 309 15903 4551 0.975189 0.975189 -38.2274 -0.975189 0 0 666494. 2306.21 0.03 0.03 0.09 -1 -1 0.03 0.0107508 0.00928908 49 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.29 vpr 62.15 MiB -1 -1 0.17 17580 1 0.02 -1 -1 30004 -1 -1 11 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63640 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 23.3 MiB 0.03 395 6867 2582 3609 676 62.1 MiB 0.05 0.00 1.65567 -48.7086 -1.65567 1.65567 0.32 0.000325622 0.000302353 0.0174514 0.0161951 -1 -1 -1 -1 28 927 37 6.65987e+06 139458 500653. 1732.36 0.49 0.0658178 0.0568171 21970 115934 -1 701 14 374 374 29107 8630 1.23745 1.23745 -49.5635 -1.23745 0 0 612192. 2118.31 0.02 0.02 0.07 -1 -1 0.02 0.00594303 0.00527331 55 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.41 vpr 62.28 MiB -1 -1 0.12 17468 1 0.02 -1 -1 30460 -1 -1 13 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63772 41 21 146 147 1 102 75 17 17 289 -1 unnamed_device 23.0 MiB 0.03 491 9081 3707 5187 187 62.3 MiB 0.06 0.00 1.67767 -56.6155 -1.67767 1.67767 0.32 0.00035997 0.000334363 0.0218976 0.020333 -1 -1 -1 -1 30 1037 25 6.65987e+06 164814 526063. 1820.29 0.49 0.0667016 0.0582429 22546 126617 -1 743 15 369 369 22934 6790 1.02419 1.02419 -50.6361 -1.02419 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.0117394 0.0102506 62 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 3.61 vpr 62.31 MiB -1 -1 0.11 17580 1 0.02 -1 -1 30308 -1 -1 14 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63808 45 23 160 161 1 114 82 17 17 289 -1 unnamed_device 23.1 MiB 0.03 499 10228 3488 4555 2185 62.3 MiB 0.06 0.00 1.69967 -61.5408 -1.69967 1.69967 0.32 0.000393075 0.000365679 0.0237597 0.0221074 -1 -1 -1 -1 30 1113 21 6.65987e+06 177492 526063. 1820.29 1.46 0.127983 0.11047 22546 126617 -1 863 16 593 593 46003 13579 1.18459 1.18459 -55.1595 -1.18459 0 0 666494. 2306.21 0.03 0.04 0.10 -1 -1 0.03 0.0130362 0.0113889 68 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.71 vpr 62.41 MiB -1 -1 0.16 17728 1 0.02 -1 -1 30344 -1 -1 14 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63908 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 23.1 MiB 0.03 627 5353 1046 4033 274 62.4 MiB 0.04 0.00 2.07098 -70.3136 -2.07098 2.07098 0.32 0.000433307 0.000403645 0.0129451 0.0120394 -1 -1 -1 -1 32 1170 15 6.65987e+06 177492 554710. 1919.41 0.45 0.0588027 0.0514064 22834 132086 -1 1054 17 432 432 30738 8937 1.32345 1.32345 -69.7201 -1.32345 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0145867 0.0127516 73 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.29 vpr 62.52 MiB -1 -1 0.16 17584 1 0.04 -1 -1 30108 -1 -1 18 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64016 57 29 202 203 1 143 104 17 17 289 -1 unnamed_device 23.4 MiB 0.04 750 10596 2249 7776 571 62.5 MiB 0.07 0.00 2.11498 -85.1831 -2.11498 2.11498 0.31 0.000494895 0.000460975 0.0226536 0.02111 -1 -1 -1 -1 32 1479 15 6.65987e+06 228204 554710. 1919.41 0.47 0.0757256 0.0669986 22834 132086 -1 1199 18 520 520 35837 10747 1.36745 1.36745 -82.2692 -1.36745 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0174867 0.0153336 86 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.36 vpr 62.79 MiB -1 -1 0.14 17900 1 0.03 -1 -1 29940 -1 -1 19 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64296 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 23.2 MiB 0.04 1148 18135 6273 10055 1807 62.8 MiB 0.11 0.00 2.50829 -108.743 -2.50829 2.50829 0.31 0.000567141 0.000528695 0.0376235 0.035098 -1 -1 -1 -1 32 1762 17 6.65987e+06 240882 554710. 1919.41 0.48 0.101169 0.0902369 22834 132086 -1 1641 35 572 572 92037 50076 1.42045 1.42045 -99.1377 -1.42045 0 0 701300. 2426.64 0.03 0.09 0.11 -1 -1 0.03 0.034255 0.0298774 97 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.76 vpr 62.72 MiB -1 -1 0.15 17948 1 0.04 -1 -1 30296 -1 -1 29 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64224 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 23.6 MiB 0.05 1644 32449 9393 19839 3217 62.7 MiB 0.19 0.00 3.38291 -180.76 -3.38291 3.38291 0.32 0.000880433 0.000823692 0.0609751 0.0571335 -1 -1 -1 -1 32 2858 35 6.65987e+06 367662 554710. 1919.41 0.66 0.183589 0.165605 22834 132086 -1 2422 21 853 853 74293 19928 1.63645 1.63645 -152.543 -1.63645 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0343826 0.0306978 145 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.04 vpr 63.06 MiB -1 -1 0.22 18240 1 0.04 -1 -1 30524 -1 -1 39 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 24.1 MiB 0.07 2278 49637 16106 29325 4206 63.1 MiB 0.32 0.01 4.25753 -269.84 -4.25753 4.25753 0.32 0.00119888 0.00112752 0.0868525 0.0816403 -1 -1 -1 -1 32 3524 24 6.65987e+06 494442 554710. 1919.41 0.71 0.239232 0.218193 22834 132086 -1 3207 15 1082 1082 88606 22556 1.61205 1.61205 -194.499 -1.61205 0 0 701300. 2426.64 0.03 0.09 0.13 -1 -1 0.03 0.0362035 0.0327639 193 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_004bits.v common 1.77 vpr 62.61 MiB -1 -1 0.15 17432 1 0.02 -1 -1 30000 -1 -1 1 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64112 9 5 34 35 1 15 15 17 17 289 -1 unnamed_device 23.9 MiB 0.02 49 141 51 88 2 62.6 MiB 0.00 0.00 0.723895 -9.92304 -0.723895 0.723895 0.26 8.8052e-05 7.9849e-05 0.000999121 0.000908116 -1 -1 -1 -1 20 98 10 6.95648e+06 14475.7 414966. 1435.87 0.30 0.0111389 0.00932378 23170 95770 -1 97 7 39 39 2258 798 0.74674 0.74674 -9.97418 -0.74674 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00275107 0.00248696 7 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_005bits.v common 1.90 vpr 62.60 MiB -1 -1 0.14 17416 1 0.02 -1 -1 29904 -1 -1 1 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 11 6 41 42 1 20 18 17 17 289 -1 unnamed_device 24.1 MiB 0.05 62 455 89 352 14 62.6 MiB 0.01 0.00 0.723895 -12.1764 -0.723895 0.723895 0.34 0.000105243 9.602e-05 0.00245462 0.00224036 -1 -1 -1 -1 20 159 11 6.95648e+06 14475.7 414966. 1435.87 0.28 0.006791 0.00608146 23170 95770 -1 135 8 71 71 4591 1516 0.74674 0.74674 -13.0356 -0.74674 0 0 503264. 1741.40 0.02 0.01 0.10 -1 -1 0.02 0.00316305 0.00283131 8 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_006bits.v common 1.98 vpr 62.57 MiB -1 -1 0.14 17264 1 0.02 -1 -1 29984 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64076 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 24.1 MiB 0.05 78 532 113 404 15 62.6 MiB 0.01 0.00 0.802432 -14.5369 -0.802432 0.802432 0.35 0.00012283 0.00011251 0.00266091 0.00244373 -1 -1 -1 -1 22 226 14 6.95648e+06 28951.4 443629. 1535.05 0.33 0.0192559 0.0165149 23458 102101 -1 200 12 93 93 4853 1733 1.04203 1.04203 -16.6837 -1.04203 0 0 531479. 1839.03 0.02 0.01 0.10 -1 -1 0.02 0.00425953 0.003729 10 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 1.92 vpr 62.76 MiB -1 -1 0.09 17224 1 0.03 -1 -1 30004 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 24.3 MiB 0.03 198 745 185 473 87 62.8 MiB 0.01 0.00 0.852632 -19.2076 -0.852632 0.852632 0.34 0.000140716 0.00012916 0.00337215 0.00309938 -1 -1 -1 -1 26 321 13 6.95648e+06 28951.4 503264. 1741.40 0.36 0.0195341 0.0165326 24322 120374 -1 321 11 126 126 8370 2235 1.09223 1.09223 -20.8791 -1.09223 0 0 618332. 2139.56 0.04 0.01 0.12 -1 -1 0.04 0.00464353 0.00415812 11 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_008bits.v common 2.08 vpr 62.92 MiB -1 -1 0.15 17404 1 0.02 -1 -1 30132 -1 -1 2 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64428 17 9 62 63 1 37 28 17 17 289 -1 unnamed_device 24.4 MiB 0.03 223 1078 298 659 121 62.9 MiB 0.01 0.00 0.852632 -21.5769 -0.852632 0.852632 0.33 0.000157576 0.000145183 0.00461473 0.00425641 -1 -1 -1 -1 30 354 9 6.95648e+06 28951.4 556674. 1926.21 0.39 0.0212789 0.0180897 25186 138497 -1 308 12 127 127 6401 1953 0.959892 0.959892 -22.0373 -0.959892 0 0 706193. 2443.58 0.03 0.01 0.11 -1 -1 0.03 0.00509797 0.00446228 13 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_009bits.v common 2.35 vpr 62.62 MiB -1 -1 0.16 17360 1 0.02 -1 -1 30072 -1 -1 4 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64124 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 24.1 MiB 0.02 137 2113 694 1199 220 62.6 MiB 0.02 0.00 0.852632 -22.0391 -0.852632 0.852632 0.33 0.000175963 0.000162527 0.0077691 0.00716049 -1 -1 -1 -1 34 351 30 6.95648e+06 57902.7 618332. 2139.56 0.63 0.045466 0.0380876 25762 151098 -1 282 21 287 287 12600 4481 1.08603 1.08603 -23.81 -1.08603 0 0 787024. 2723.27 0.05 0.03 0.14 -1 -1 0.05 0.00901771 0.00775726 15 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_010bits.v common 2.12 vpr 62.77 MiB -1 -1 0.16 17304 1 0.03 -1 -1 30060 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 21 11 76 77 1 49 36 17 17 289 -1 unnamed_device 24.3 MiB 0.02 347 1157 244 770 143 62.8 MiB 0.01 0.00 0.896632 -29.3782 -0.896632 0.896632 0.34 0.000195865 0.000181237 0.00446093 0.00413933 -1 -1 -1 -1 32 570 14 6.95648e+06 57902.7 586450. 2029.24 0.45 0.0343905 0.0288988 25474 144626 -1 537 14 225 225 20970 4717 0.993732 0.993732 -31.9978 -0.993732 0 0 744469. 2576.02 0.03 0.02 0.10 -1 -1 0.03 0.00662926 0.0057376 17 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_011bits.v common 2.48 vpr 62.92 MiB -1 -1 0.16 17280 1 0.02 -1 -1 30048 -1 -1 4 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64432 23 12 83 84 1 55 39 17 17 289 -1 unnamed_device 24.3 MiB 0.02 176 2481 826 1259 396 62.9 MiB 0.02 0.00 0.896632 -27.0337 -0.896632 0.896632 0.34 0.000210709 0.000195162 0.00860788 0.00797035 -1 -1 -1 -1 34 483 24 6.95648e+06 57902.7 618332. 2139.56 0.67 0.0520092 0.0437792 25762 151098 -1 363 22 394 394 26948 8701 1.04203 1.04203 -28.5778 -1.04203 0 0 787024. 2723.27 0.04 0.03 0.16 -1 -1 0.04 0.00958538 0.00817473 18 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_012bits.v common 2.16 vpr 62.77 MiB -1 -1 0.15 17464 1 0.02 -1 -1 30040 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 24.1 MiB 0.02 224 1468 277 1132 59 62.8 MiB 0.02 0.00 0.918632 -30.5074 -0.918632 0.918632 0.34 0.000235964 0.000218668 0.00528816 0.00487691 -1 -1 -1 -1 28 585 18 6.95648e+06 72378.4 531479. 1839.03 0.42 0.0314017 0.026693 24610 126494 -1 522 14 291 291 16745 5276 1.13003 1.13003 -35.7088 -1.13003 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.00737591 0.00639021 20 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 2.17 vpr 62.77 MiB -1 -1 0.15 17312 1 0.02 -1 -1 30064 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64276 27 14 97 98 1 66 46 17 17 289 -1 unnamed_device 24.1 MiB 0.03 339 2916 911 1507 498 62.8 MiB 0.02 0.00 0.951632 -33.9905 -0.951632 0.951632 0.33 0.000237851 0.000219672 0.0093005 0.00860411 -1 -1 -1 -1 30 672 15 6.95648e+06 72378.4 556674. 1926.21 0.43 0.0359111 0.0309348 25186 138497 -1 538 13 312 312 21190 5519 1.20223 1.20223 -37.9867 -1.20223 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.0076564 0.00668502 21 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_014bits.v common 2.25 vpr 62.77 MiB -1 -1 0.16 17140 1 0.02 -1 -1 29948 -1 -1 5 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64276 29 15 104 105 1 72 49 17 17 289 -1 unnamed_device 24.1 MiB 0.03 501 2808 751 1668 389 62.8 MiB 0.02 0.00 0.951632 -40.8249 -0.951632 0.951632 0.34 0.000242718 0.000218442 0.00856423 0.00788443 -1 -1 -1 -1 28 933 14 6.95648e+06 72378.4 531479. 1839.03 0.51 0.0366332 0.0315532 24610 126494 -1 839 20 482 482 52768 11792 1.09223 1.09223 -45.6629 -1.09223 0 0 648988. 2245.63 0.03 0.03 0.14 -1 -1 0.03 0.0104657 0.00901245 23 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_015bits.v common 2.48 vpr 62.93 MiB -1 -1 0.17 17680 1 0.02 -1 -1 30380 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64444 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 24.2 MiB 0.04 310 4417 1777 2577 63 62.9 MiB 0.03 0.00 1.33396 -40.1371 -1.33396 1.33396 0.33 0.000271468 0.000251395 0.013265 0.0122886 -1 -1 -1 -1 36 703 18 6.95648e+06 72378.4 648988. 2245.63 0.68 0.065333 0.0558986 26050 158493 -1 570 15 424 424 34284 9332 1.09503 1.09503 -39.6024 -1.09503 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64376 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 24.1 MiB 0.07 367 6541 2699 3775 67 62.9 MiB 0.05 0.00 1.36696 -49.1573 -1.36696 1.36696 0.33 0.000329616 0.000306498 0.0189951 0.0176578 -1 -1 -1 -1 32 856 19 6.95648e+06 72378.4 586450. 2029.24 0.49 0.0571506 0.0498642 25474 144626 -1 628 18 477 477 33113 8842 1.22703 1.22703 -50.8059 -1.22703 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.0122266 0.0105782 28 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_020bits.v common 2.39 vpr 63.03 MiB -1 -1 0.17 17652 1 0.02 -1 -1 30388 -1 -1 5 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64544 41 21 146 147 1 95 67 17 17 289 -1 unnamed_device 24.0 MiB 0.07 409 6867 2815 3994 58 63.0 MiB 0.05 0.00 1.38896 -56.2399 -1.38896 1.38896 0.33 0.00036088 0.000335508 0.0193484 0.0179993 -1 -1 -1 -1 30 1163 35 6.95648e+06 72378.4 556674. 1926.21 0.60 0.0698336 0.0607412 25186 138497 -1 785 16 563 563 51275 13421 1.44463 1.44463 -60.8139 -1.44463 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0123152 0.0107333 31 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_022bits.v common 3.70 vpr 63.18 MiB -1 -1 0.17 17588 1 0.03 -1 -1 30316 -1 -1 6 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 45 23 160 161 1 108 74 17 17 289 -1 unnamed_device 24.0 MiB 0.08 466 7514 3111 4336 67 63.2 MiB 0.05 0.00 1.41096 -62.5444 -1.41096 1.41096 0.34 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65072 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 24.0 MiB 0.08 866 16299 6958 9195 146 63.5 MiB 0.10 0.00 1.88129 -97.7109 -1.88129 1.88129 0.34 0.000573807 0.000535131 0.0384883 0.0358947 -1 -1 -1 -1 42 1631 39 6.95648e+06 130281 744469. 2576.02 1.15 0.166265 0.146237 27202 183097 -1 1355 16 747 747 71025 18381 1.44933 1.44933 -95.5906 -1.44933 0 0 949917. 3286.91 0.04 0.05 0.15 -1 -1 0.04 0.0188154 0.0166379 50 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_048bits.v common 3.38 vpr 64.11 MiB -1 -1 0.18 17836 1 0.03 -1 -1 30336 -1 -1 14 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65644 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 24.3 MiB 0.11 1814 29672 12289 17319 64 64.1 MiB 0.18 0.00 2.41762 -170.667 -2.41762 2.41762 0.33 0.000869886 0.000815239 0.0621123 0.058191 -1 -1 -1 -1 48 2741 23 6.95648e+06 202660 865456. 2994.66 1.22 0.238027 0.213864 28354 207349 -1 2562 20 1103 1103 131768 29384 1.49993 1.49993 -156.421 -1.49993 0 0 1.05005e+06 3633.38 0.04 0.09 0.17 -1 -1 0.04 0.0335475 0.0300032 74 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_064bits.v common 4.45 vpr 64.69 MiB -1 -1 0.17 18212 1 0.04 -1 -1 30612 -1 -1 19 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66244 129 65 454 455 1 324 213 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2229 45933 16115 26949 2869 64.7 MiB 0.29 0.01 2.95395 -241.167 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2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64012 13 7 48 49 1 26 22 17 17 289 -1 unnamed_device 24.0 MiB 0.01 88 442 89 343 10 62.5 MiB 0.02 0.00 0.802432 -14.6238 -0.802432 0.802432 0.33 0.000416283 0.000382138 0.00349914 0.00321787 -1 -1 -1 -1 22 196 8 6.99608e+06 29431.4 443629. 1535.05 0.33 0.0164598 0.0139839 23458 102101 -1 190 12 106 106 6171 2132 0.793379 0.793379 -15.9608 -0.793379 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00429213 0.00376112 10 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_007bits.v common 1.96 vpr 62.73 MiB -1 -1 0.15 17312 1 0.02 -1 -1 30052 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64240 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 24.3 MiB 0.01 96 709 205 450 54 62.7 MiB 0.01 0.00 0.859432 -17.7199 -0.859432 0.859432 0.34 0.000140372 0.000128807 0.00323931 0.00297881 -1 -1 -1 -1 26 228 25 6.99608e+06 29431.4 503264. 1741.40 0.37 0.0216731 0.0182166 24322 120374 -1 198 12 131 131 4752 1834 0.927732 0.927732 -17.9149 -0.927732 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00468069 0.0040988 11 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_008bits.v common 2.08 vpr 62.63 MiB -1 -1 0.15 17184 1 0.02 -1 -1 30084 -1 -1 2 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64132 17 9 62 63 1 38 28 17 17 289 -1 unnamed_device 24.1 MiB 0.02 260 952 218 609 125 62.6 MiB 0.01 0.00 0.824432 -22.1673 -0.824432 0.824432 0.34 0.000156946 0.000144715 0.00406462 0.00375358 -1 -1 -1 -1 32 430 9 6.99608e+06 29431.4 586450. 2029.24 0.41 0.020757 0.0176249 25474 144626 -1 421 9 116 116 11800 2672 0.87204 0.87204 -23.6355 -0.87204 0 0 744469. 2576.02 0.03 0.01 0.12 -1 -1 0.03 0.00440788 0.00390181 13 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_009bits.v common 2.12 vpr 62.43 MiB -1 -1 0.16 17352 1 0.02 -1 -1 30028 -1 -1 4 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63932 19 10 69 70 1 43 33 17 17 289 -1 unnamed_device 23.9 MiB 0.02 137 2477 763 1101 613 62.4 MiB 0.02 0.00 0.846432 -21.9393 -0.846432 0.846432 0.38 0.000171382 0.000154709 0.00923131 0.00850779 -1 -1 -1 -1 28 370 18 6.99608e+06 58862.7 531479. 1839.03 0.39 0.0301008 0.0257969 24610 126494 -1 287 13 210 210 11679 4198 1.18933 1.18933 -23.5118 -1.18933 0 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-1 4 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64144 23 12 83 84 1 54 39 17 17 289 -1 unnamed_device 24.1 MiB 0.02 174 2481 746 1270 465 62.6 MiB 0.02 0.00 0.879432 -26.6557 -0.879432 0.879432 0.33 0.00021024 0.000194311 0.00857848 0.00793516 -1 -1 -1 -1 32 441 18 6.99608e+06 58862.7 586450. 2029.24 0.46 0.0332947 0.0284674 25474 144626 -1 372 12 266 266 17399 5603 0.993732 0.993732 -28.012 -0.993732 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00635172 0.00551661 18 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_012bits.v common 2.13 vpr 62.57 MiB -1 -1 0.16 17196 1 0.02 -1 -1 30032 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64072 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 23.9 MiB 0.03 255 1618 324 1252 42 62.6 MiB 0.02 0.00 0.890432 -31.1278 -0.890432 0.890432 0.34 0.000224588 0.000208394 0.00581343 0.00537445 -1 -1 -1 -1 30 526 13 6.99608e+06 73578.4 556674. 1926.21 0.42 0.0313334 0.0268842 25186 138497 -1 496 10 236 236 16715 4353 0.99734 0.99734 -33.2379 -0.99734 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00608414 0.00533822 20 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 2.17 vpr 62.79 MiB -1 -1 0.16 17396 1 0.02 -1 -1 29940 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64292 27 14 97 98 1 66 46 17 17 289 -1 unnamed_device 24.2 MiB 0.02 266 2916 905 1615 396 62.8 MiB 0.02 0.00 0.912432 -33.5679 -0.912432 0.912432 0.34 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0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.0099582 0.00858435 23 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_015bits.v common 2.27 vpr 62.73 MiB -1 -1 0.14 17584 1 0.02 -1 -1 30304 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64232 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 24.0 MiB 0.03 331 4514 1860 2555 99 62.7 MiB 0.03 0.00 1.29476 -39.8517 -1.29476 1.29476 0.33 0.000271418 0.000251586 0.0135538 0.0125405 -1 -1 -1 -1 30 845 48 6.99608e+06 73578.4 556674. 1926.21 0.52 0.0569387 0.0488876 25186 138497 -1 616 19 462 462 34517 8954 1.11703 1.11703 -42.4939 -1.11703 0 0 706193. 2443.58 0.03 0.03 0.12 -1 -1 0.03 0.0108951 0.00939784 24 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_016bits.v common 2.18 vpr 62.88 MiB -1 -1 0.09 17568 1 0.02 -1 -1 30068 -1 -1 5 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64384 33 17 118 119 1 81 55 17 17 289 -1 unnamed_device 24.1 MiB 0.03 328 4735 1886 2806 43 62.9 MiB 0.04 0.00 1.31676 -42.6858 -1.31676 1.31676 0.33 0.000291739 0.000270454 0.0141016 0.0130776 -1 -1 -1 -1 30 805 33 6.99608e+06 73578.4 556674. 1926.21 0.49 0.053817 0.046524 25186 138497 -1 641 16 399 399 31520 8272 1.15003 1.15003 -44.2826 -1.15003 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0101561 0.00881561 25 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_018bits.v common 2.07 vpr 62.99 MiB -1 -1 0.13 17664 1 0.03 -1 -1 30056 -1 -1 5 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64500 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 24.3 MiB 0.03 364 6541 2695 3784 62 63.0 MiB 0.02 0.00 1.33876 -49.2921 -1.33876 1.33876 0.26 0.000154524 0.000136787 0.00893174 0.00815638 -1 -1 -1 -1 32 939 42 6.99608e+06 73578.4 586450. 2029.24 0.51 0.05855 0.049823 25474 144626 -1 693 12 368 368 26349 7167 1.17203 1.17203 -49.9105 -1.17203 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.00929189 0.00813969 28 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_020bits.v common 2.35 vpr 62.70 MiB -1 -1 0.16 17492 1 0.02 -1 -1 30308 -1 -1 5 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64208 41 21 146 147 1 94 67 17 17 289 -1 unnamed_device 23.7 MiB 0.03 407 6867 2751 4056 60 62.7 MiB 0.05 0.00 1.34976 -54.4321 -1.34976 1.34976 0.33 0.000360265 0.000334878 0.0193038 0.0179451 -1 -1 -1 -1 32 961 35 6.99608e+06 73578.4 586450. 2029.24 0.57 0.0697677 0.0606438 25474 144626 -1 756 15 428 428 30944 8363 1.24903 1.24903 -58.4693 -1.24903 0 0 744469. 2576.02 0.04 0.03 0.12 -1 -1 0.04 0.0117671 0.0102516 31 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_022bits.v common 2.27 vpr 62.82 MiB -1 -1 0.16 17528 1 0.03 -1 -1 30348 -1 -1 6 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64332 45 23 160 161 1 107 74 17 17 289 -1 unnamed_device 23.7 MiB 0.04 530 7514 3084 4380 50 62.8 MiB 0.05 0.00 1.37176 -61.8029 -1.37176 1.37176 0.33 0.000390883 0.000363367 0.0200903 0.0186905 -1 -1 -1 -1 30 1126 15 6.99608e+06 88294.1 556674. 1926.21 0.48 0.0628619 0.0552343 25186 138497 -1 855 18 558 558 40666 10320 1.16968 1.16968 -63.7857 -1.16968 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.014469 0.0126338 34 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_024bits.v common 2.94 vpr 63.00 MiB -1 -1 0.14 17580 1 0.02 -1 -1 30244 -1 -1 8 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64512 49 25 174 175 1 118 82 17 17 289 -1 unnamed_device 23.8 MiB 0.04 521 10228 4171 5954 103 63.0 MiB 0.07 0.00 1.39376 -67.8066 -1.39376 1.39376 0.33 0.000422838 0.000393319 0.0255703 0.0237972 -1 -1 -1 -1 34 1390 34 6.99608e+06 117725 618332. 2139.56 1.09 0.117769 0.102435 25762 151098 -1 986 29 736 736 98243 38158 1.36333 1.36333 -70.765 -1.36333 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0224734 0.0194537 38 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_028bits.v common 3.07 vpr 63.10 MiB -1 -1 0.16 17624 1 0.03 -1 -1 30008 -1 -1 9 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64616 57 29 202 203 1 141 95 17 17 289 -1 unnamed_device 23.7 MiB 0.05 724 11543 4737 6716 90 63.1 MiB 0.07 0.00 1.44876 -82.7694 -1.44876 1.44876 0.34 0.000487581 0.000453293 0.0278211 0.0258836 -1 -1 -1 -1 38 1462 37 6.99608e+06 132441 678818. 2348.85 1.07 0.136751 0.119606 26626 170182 -1 1129 17 624 624 44907 12336 1.24188 1.24188 -80.687 -1.24188 0 0 902133. 3121.57 0.03 0.04 0.14 -1 -1 0.03 0.0169488 0.0148993 44 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_032bits.v common 3.01 vpr 63.09 MiB -1 -1 0.10 17544 1 0.03 -1 -1 30048 -1 -1 9 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 23.7 MiB 0.05 873 16299 6945 9215 139 63.1 MiB 0.10 0.00 1.85309 -97.7499 -1.85309 1.85309 0.34 0.000588436 0.000549662 0.0383991 0.0358314 -1 -1 -1 -1 40 1590 25 6.99608e+06 132441 706193. 2443.58 1.10 0.154029 0.135738 26914 176310 -1 1430 16 781 781 64746 16342 1.32403 1.32403 -95.1334 -1.32403 0 0 926341. 3205.33 0.04 0.05 0.14 -1 -1 0.04 0.0186641 0.0164658 50 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_048bits.v common 3.65 vpr 63.71 MiB -1 -1 0.17 17844 1 0.03 -1 -1 30352 -1 -1 14 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65236 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 24.0 MiB 0.08 1811 29672 12269 17337 66 63.7 MiB 0.18 0.00 2.38942 -170.114 -2.38942 2.38942 0.33 0.000881923 0.00082713 0.0624841 0.0585536 -1 -1 -1 -1 44 2886 50 6.99608e+06 206020 787024. 2723.27 1.45 0.277812 0.249067 27778 195446 -1 2550 19 1048 1048 107084 28330 1.70033 1.70033 -166.464 -1.70033 0 0 997811. 3452.63 0.04 0.08 0.16 -1 -1 0.04 0.032219 0.0288443 74 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_064bits.v common 4.33 vpr 64.00 MiB -1 -1 0.22 18124 1 0.04 -1 -1 30668 -1 -1 19 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65536 129 65 454 455 1 324 213 17 17 289 -1 unnamed_device 24.8 MiB 0.09 2249 45933 16327 26970 2636 64.0 MiB 0.27 0.01 2.92575 -237.867 -2.92575 2.92575 0.33 0.00120023 0.00112835 0.0902407 0.0848321 -1 -1 -1 -1 48 3564 45 6.99608e+06 279598 865456. 2994.66 1.93 0.385981 0.349472 28354 207349 -1 3147 13 1131 1131 98551 21708 1.67588 1.67588 -208.648 -1.67588 0 0 1.05005e+06 3633.38 0.04 0.09 0.17 -1 -1 0.04 0.0333912 0.0303126 98 2 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_004bits.v common 1.87 vpr 61.76 MiB -1 -1 0.13 17292 2 0.06 -1 -1 31964 -1 -1 1 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63244 9 5 28 33 1 16 15 17 17 289 -1 unnamed_device 23.0 MiB 0.01 54 141 47 92 2 61.8 MiB 0.00 0.00 0.883748 -10.0813 -0.883748 0.883748 0.33 8.5414e-05 7.7314e-05 0.000966256 0.000875122 -1 -1 -1 -1 20 116 6 6.79088e+06 13472 414966. 1435.87 0.29 0.0100954 0.00839297 22510 95286 -1 96 7 35 35 1420 501 0.883748 0.883748 -9.8435 -0.883748 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00269658 0.00243975 8 6 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_005bits.v common 1.90 vpr 61.89 MiB -1 -1 0.14 17340 2 0.07 -1 -1 31884 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63376 11 6 34 40 1 23 19 17 17 289 -1 unnamed_device 23.2 MiB 0.01 78 394 86 293 15 61.9 MiB 0.01 0.00 1.02368 -13.4328 -1.02368 1.02368 0.36 0.000106267 9.6689e-05 0.00206803 0.0018958 -1 -1 -1 -1 22 194 10 6.79088e+06 26944 443629. 1535.05 0.32 0.0137002 0.0115006 22798 101617 -1 190 9 83 96 4150 1453 1.02368 1.02368 -14.6764 -1.02368 0 0 531479. 1839.03 0.03 0.01 0.09 -1 -1 0.03 0.00336983 0.00298904 10 7 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_006bits.v common 1.81 vpr 61.99 MiB -1 -1 0.15 17184 3 0.06 -1 -1 31848 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63476 13 7 41 48 1 30 22 17 17 289 -1 unnamed_device 23.3 MiB 0.01 103 562 132 416 14 62.0 MiB 0.01 0.00 1.14898 -15.8855 -1.14898 1.14898 0.33 5.793e-05 5.1492e-05 0.00140278 0.00125839 -1 -1 -1 -1 22 254 12 6.79088e+06 26944 443629. 1535.05 0.33 0.0182156 0.0151027 22798 101617 -1 234 12 97 105 6113 2065 1.14898 1.14898 -17.5434 -1.14898 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00432033 0.00378435 11 9 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_007bits.v common 2.04 vpr 62.02 MiB -1 -1 0.15 17292 3 0.05 -1 -1 31872 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63512 15 8 47 55 1 35 25 17 17 289 -1 unnamed_device 23.6 MiB 0.04 109 1285 395 736 154 62.0 MiB 0.01 0.00 1.27433 -19.2894 -1.27433 1.27433 0.34 0.000142197 0.0001303 0.00559248 0.00513681 -1 -1 -1 -1 26 347 17 6.79088e+06 26944 503264. 1741.40 0.37 0.0227498 0.0192919 23662 119890 -1 248 14 147 157 5953 2292 1.27433 1.27433 -20.5245 -1.27433 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00522063 0.00452381 13 10 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_008bits.v common 2.16 vpr 61.95 MiB -1 -1 0.16 17260 3 0.06 -1 -1 31924 -1 -1 4 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63432 17 9 56 65 1 42 30 17 17 289 -1 unnamed_device 23.5 MiB 0.06 297 1272 281 862 129 61.9 MiB 0.02 0.00 1.56413 -26.212 -1.56413 1.56413 0.34 0.000175567 0.00016209 0.00553938 0.00510909 -1 -1 -1 -1 26 505 11 6.79088e+06 53888 503264. 1741.40 0.36 0.0254124 0.0215936 23662 119890 -1 454 9 113 140 9091 2260 1.31353 1.31353 -26.0895 -1.31353 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00473594 0.00420527 17 14 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_009bits.v common 2.16 vpr 61.99 MiB -1 -1 0.15 17304 4 0.06 -1 -1 31992 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63476 19 10 60 70 1 46 32 17 17 289 -1 unnamed_device 23.5 MiB 0.07 157 2582 733 1373 476 62.0 MiB 0.02 0.00 1.65028 -26.9205 -1.65028 1.65028 0.34 0.000185515 0.000170984 0.0102122 0.00942314 -1 -1 -1 -1 28 440 24 6.79088e+06 40416 531479. 1839.03 0.40 0.0336774 0.0287458 23950 126010 -1 341 14 189 208 10515 3869 1.68943 1.68943 -27.6328 -1.68943 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.00634766 0.00548015 17 13 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_010bits.v common 2.09 vpr 62.10 MiB -1 -1 0.16 17224 4 0.06 -1 -1 31688 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63592 21 11 69 80 1 54 36 17 17 289 -1 unnamed_device 23.6 MiB 0.06 276 1275 269 996 10 62.1 MiB 0.01 0.00 1.56413 -30.7636 -1.56413 1.56413 0.33 0.000211308 0.000195146 0.00522765 0.00483659 -1 -1 -1 -1 22 697 22 6.79088e+06 53888 443629. 1535.05 0.40 0.0360258 0.0302982 22798 101617 -1 574 14 232 281 20802 5741 1.51379 1.51379 -32.6549 -1.51379 0 0 531479. 1839.03 0.02 0.02 0.09 -1 -1 0.02 0.00716795 0.00620991 21 17 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_011bits.v common 1.98 vpr 62.01 MiB -1 -1 0.17 17236 5 0.06 -1 -1 31940 -1 -1 4 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63496 23 12 76 88 1 60 39 17 17 289 -1 unnamed_device 23.5 MiB 0.06 263 1359 262 1083 14 62.0 MiB 0.02 0.00 1.90432 -34.8738 -1.90432 1.90432 0.33 0.000227626 0.0002106 0.00540807 0.00501505 -1 -1 -1 -1 26 598 16 6.79088e+06 53888 503264. 1741.40 0.38 0.0309708 0.026345 23662 119890 -1 529 13 222 264 13917 4200 1.85054 1.85054 -36.679 -1.85054 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00719778 0.00628971 23 19 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_012bits.v common 2.14 vpr 62.08 MiB -1 -1 0.16 17296 5 0.06 -1 -1 32124 -1 -1 4 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63568 25 13 83 96 1 65 42 17 17 289 -1 unnamed_device 23.5 MiB 0.10 302 2634 595 2020 19 62.1 MiB 0.02 0.00 1.85398 -39.4801 -1.85398 1.85398 0.33 0.000241404 0.000222109 0.00947024 0.00873055 -1 -1 -1 -1 26 756 25 6.79088e+06 53888 503264. 1741.40 0.42 0.0400931 0.0343115 23662 119890 -1 611 16 260 323 16466 4828 1.76444 1.76444 -40.3833 -1.76444 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00875305 0.00755852 24 21 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_013bits.v common 2.20 vpr 62.27 MiB -1 -1 0.16 17516 5 0.06 -1 -1 31696 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63764 27 14 91 105 1 70 46 17 17 289 -1 unnamed_device 23.7 MiB 0.08 305 1686 354 1296 36 62.3 MiB 0.02 0.00 2.15497 -44.1132 -2.15497 2.15497 0.33 0.00032784 0.000303874 0.00737664 0.00683614 -1 -1 -1 -1 30 642 13 6.79088e+06 67360 556674. 1926.21 0.41 0.0366048 0.0314193 24526 138013 -1 572 14 257 360 19230 5544 1.89323 1.89323 -42.6809 -1.89323 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0153646 0.0131766 28 24 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_014bits.v common 2.32 vpr 62.30 MiB -1 -1 0.17 17720 6 0.06 -1 -1 32036 -1 -1 5 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63792 29 15 95 110 1 77 49 17 17 289 -1 unnamed_device 23.7 MiB 0.07 324 3342 734 2532 76 62.3 MiB 0.03 0.00 2.42352 -48.7848 -2.42352 2.42352 0.34 0.000283292 0.000262432 0.0115124 0.0106785 -1 -1 -1 -1 26 904 32 6.79088e+06 67360 503264. 1741.40 0.48 0.0553618 0.0473417 23662 119890 -1 757 13 322 384 23522 6789 2.15502 2.15502 -49.648 -2.15502 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00885209 0.00771765 29 23 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_015bits.v common 2.30 vpr 62.27 MiB -1 -1 0.17 17660 6 0.06 -1 -1 32064 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63764 31 16 104 120 1 81 52 17 17 289 -1 unnamed_device 23.5 MiB 0.08 317 3641 1047 1889 705 62.3 MiB 0.03 0.00 2.28032 -49.0709 -2.28032 2.28032 0.33 0.000311764 0.00028965 0.0128153 0.0118974 -1 -1 -1 -1 26 896 44 6.79088e+06 67360 503264. 1741.40 0.47 0.0611187 0.0522955 23662 119890 -1 675 11 298 344 27538 10777 2.15502 2.15502 -50.3725 -2.15502 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00864617 0.00757546 31 27 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_016bits.v common 2.48 vpr 62.32 MiB -1 -1 0.18 17592 7 0.06 -1 -1 32008 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63820 33 17 112 129 1 84 56 17 17 289 -1 unnamed_device 23.6 MiB 0.08 457 2945 706 2143 96 62.3 MiB 0.03 0.00 2.65628 -60.2407 -2.65628 2.65628 0.33 0.000333352 0.000308992 0.0102584 0.00951554 -1 -1 -1 -1 26 985 18 6.79088e+06 80832 503264. 1741.40 0.46 0.0482989 0.0416039 23662 119890 -1 884 27 360 465 59842 33846 2.35534 2.35534 -59.3742 -2.35534 0 0 618332. 2139.56 0.03 0.05 0.10 -1 -1 0.03 0.0169438 0.0145148 33 30 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_018bits.v common 2.73 vpr 62.16 MiB -1 -1 0.17 17536 7 0.06 -1 -1 31940 -1 -1 8 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63652 37 19 127 146 1 96 64 17 17 289 -1 unnamed_device 23.3 MiB 0.17 372 3620 797 2457 366 62.2 MiB 0.03 0.00 2.98184 -67.3807 -2.98184 2.98184 0.33 0.000368639 0.000342637 0.0117319 0.0108909 -1 -1 -1 -1 30 826 19 6.79088e+06 107776 556674. 1926.21 0.44 0.0543666 0.0470508 24526 138013 -1 708 9 322 399 17487 5742 2.85654 2.85654 -65.312 -2.85654 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00897272 0.00794271 39 35 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_020bits.v common 2.51 vpr 62.41 MiB -1 -1 0.18 17712 8 0.09 -1 -1 31984 -1 -1 9 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63912 41 21 139 160 1 106 71 17 17 289 -1 unnamed_device 23.3 MiB 0.12 468 7517 1635 5720 162 62.4 MiB 0.05 0.00 2.82083 -73.4935 -2.82083 2.82083 0.33 0.000396816 0.000367611 0.0218575 0.0202429 -1 -1 -1 -1 28 1210 23 6.79088e+06 121248 531479. 1839.03 0.51 0.0709664 0.0619985 23950 126010 -1 993 14 403 544 32469 9290 2.64519 2.64519 -75.7719 -2.64519 0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.0126456 0.0111096 41 37 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_022bits.v common 2.55 vpr 62.49 MiB -1 -1 0.18 17636 9 0.07 -1 -1 31924 -1 -1 9 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63988 45 23 153 176 1 119 77 17 17 289 -1 unnamed_device 23.3 MiB 0.15 477 7086 2063 3975 1048 62.5 MiB 0.05 0.00 3.57268 -91.263 -3.57268 3.57268 0.36 0.000445506 0.0004138 0.0204716 0.0190194 -1 -1 -1 -1 32 1120 12 6.79088e+06 121248 586450. 2029.24 0.47 0.0666694 0.0586499 24814 144142 -1 908 9 364 474 24629 7210 3.27175 3.27175 -87.1614 -3.27175 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.0105039 0.00938562 45 41 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_024bits.v common 2.58 vpr 62.59 MiB -1 -1 0.17 17684 10 0.08 -1 -1 31972 -1 -1 10 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64088 49 25 166 191 1 129 84 17 17 289 -1 unnamed_device 23.3 MiB 0.19 888 10149 2418 6579 1152 62.6 MiB 0.06 0.00 3.52584 -103.921 -3.52584 3.52584 0.33 0.000474217 0.000440445 0.028013 0.0260292 -1 -1 -1 -1 26 1697 15 6.79088e+06 134720 503264. 1741.40 0.43 0.0796154 0.0704286 23662 119890 -1 1585 14 501 640 47109 11368 3.40054 3.40054 -105.083 -3.40054 0 0 618332. 2139.56 0.03 0.04 0.10 -1 -1 0.03 0.014678 0.0129495 49 44 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_028bits.v common 2.81 vpr 62.74 MiB -1 -1 0.20 17628 11 0.08 -1 -1 32024 -1 -1 12 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64244 57 29 198 227 1 154 98 17 17 289 -1 unnamed_device 23.3 MiB 0.23 831 11348 3274 6773 1301 62.7 MiB 0.07 0.00 4.16358 -130.313 -4.16358 4.16358 0.33 0.000571622 0.000532297 0.0308967 0.0287436 -1 -1 -1 -1 26 1812 27 6.79088e+06 161664 503264. 1741.40 0.54 0.104091 0.0917454 23662 119890 -1 1543 14 611 793 48973 13212 3.94874 3.94874 -129.41 -3.94874 0 0 618332. 2139.56 0.03 0.04 0.10 -1 -1 0.03 0.0176699 0.0155753 57 56 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_032bits.v common 2.86 vpr 62.93 MiB -1 -1 0.20 17752 13 0.07 -1 -1 32144 -1 -1 11 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64436 65 33 224 257 1 172 109 17 17 289 -1 unnamed_device 23.4 MiB 0.21 818 8689 1747 6820 122 62.9 MiB 0.06 0.00 4.75448 -151.053 -4.75448 4.75448 0.33 0.000651059 0.000607364 0.0238685 0.0222369 -1 -1 -1 -1 30 1902 27 6.79088e+06 148192 556674. 1926.21 0.57 0.106315 0.0936834 24526 138013 -1 1542 15 621 853 49087 13080 4.45354 4.45354 -150.197 -4.45354 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.0208553 0.018485 67 62 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_048bits.v common 3.47 vpr 63.47 MiB -1 -1 0.26 18060 19 0.10 -1 -1 32316 -1 -1 20 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64996 97 49 340 389 1 268 166 17 17 289 -1 unnamed_device 23.8 MiB 0.35 1595 32542 9530 19534 3478 63.5 MiB 0.17 0.00 6.87725 -295.573 -6.87725 6.87725 0.33 0.000987348 0.000922056 0.0729955 0.0681292 -1 -1 -1 -1 32 3045 22 6.79088e+06 269440 586450. 2029.24 0.63 0.194659 0.175474 24814 144142 -1 2743 18 968 1302 86378 21246 6.58745 6.58745 -293.066 -6.58745 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0363793 0.0325585 103 98 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_064bits.v common 4.24 vpr 64.23 MiB -1 -1 0.16 18356 26 0.11 -1 -1 32464 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65776 129 65 453 518 1 344 218 17 17 289 -1 unnamed_device 24.5 MiB 0.57 1971 49998 15091 29566 5341 64.2 MiB 0.25 0.00 10.4784 -507.086 -10.4784 10.4784 0.33 0.00132893 0.00124528 0.106245 0.0993901 -1 -1 -1 -1 40 3524 26 6.79088e+06 323328 706193. 2443.58 1.34 0.392274 0.354177 26254 175826 -1 3188 13 1107 1495 97622 26410 9.85193 9.85193 -491.088 -9.85193 0 0 926341. 3205.33 0.04 0.11 0.14 -1 -1 0.04 0.0540559 0.0490496 131 131 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_004bits.v common 1.82 vpr 62.44 MiB -1 -1 0.10 17380 1 0.02 -1 -1 30064 -1 -1 2 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63936 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 23.6 MiB 0.04 79 296 89 204 3 62.4 MiB 0.01 0.00 0.789073 -10.6008 -0.789073 0.789073 0.34 8.7674e-05 7.9525e-05 0.00159518 0.00144518 -1 -1 -1 -1 20 151 10 6.87369e+06 27947.7 414966. 1435.87 0.28 0.00519648 0.00462685 23170 95770 -1 130 9 79 79 4463 1413 0.789073 0.789073 -11.1729 -0.789073 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00359292 0.00318991 10 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_005bits.v common 1.97 vpr 62.37 MiB -1 -1 0.08 17400 1 0.02 -1 -1 29904 -1 -1 3 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63864 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 23.6 MiB 0.04 163 695 168 481 46 62.4 MiB 0.01 0.00 0.811073 -14.7125 -0.811073 0.811073 0.40 9.2581e-05 8.1117e-05 0.00258582 0.00229127 -1 -1 -1 -1 20 310 13 6.87369e+06 41921.5 414966. 1435.87 0.31 0.00683924 0.00597313 23170 95770 -1 289 11 141 141 13137 3115 1.05067 1.05067 -17.0701 -1.05067 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00365303 0.00321754 13 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_006bits.v common 2.34 vpr 62.30 MiB -1 -1 0.13 17340 1 0.03 -1 -1 29940 -1 -1 4 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63796 13 7 48 49 1 33 24 17 17 289 -1 unnamed_device 23.8 MiB 0.06 100 806 191 526 89 62.3 MiB 0.01 0.00 0.833073 -15.3512 -0.833073 0.833073 0.34 0.000122088 0.000111989 0.00334155 0.00306422 -1 -1 -1 -1 36 229 22 6.87369e+06 55895.4 648988. 2245.63 0.63 0.0342161 0.0282667 26050 158493 -1 180 17 218 218 8477 3065 0.958373 0.958373 -15.1722 -0.958373 0 0 828058. 2865.25 0.05 0.03 0.11 -1 -1 0.05 0.00917581 0.00770806 15 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_007bits.v common 2.03 vpr 62.57 MiB -1 -1 0.14 17352 1 0.02 -1 -1 29992 -1 -1 3 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64072 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 24.2 MiB 0.05 134 1128 368 603 157 62.6 MiB 0.01 0.00 1.2044 -18.5156 -1.2044 1.2044 0.35 0.000154596 0.000139466 0.00453151 0.00408993 -1 -1 -1 -1 26 307 17 6.87369e+06 41921.5 503264. 1741.40 0.35 0.021363 0.0179662 24322 120374 -1 267 14 146 146 6496 2236 0.989373 0.989373 -20.3361 -0.989373 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00517942 0.0045165 16 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_008bits.v common 1.99 vpr 62.28 MiB -1 -1 0.08 17312 1 0.02 -1 -1 29984 -1 -1 3 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63776 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 23.8 MiB 0.05 146 1877 632 931 314 62.3 MiB 0.02 0.00 1.2154 -21.3035 -1.2154 1.2154 0.34 0.000157735 0.000145122 0.00722208 0.00664584 -1 -1 -1 -1 26 297 13 6.87369e+06 41921.5 503264. 1741.40 0.37 0.0248125 0.0212051 24322 120374 -1 273 13 150 150 7334 2479 1.00037 1.00037 -22.2134 -1.00037 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00528613 0.0045942 19 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_009bits.v common 2.16 vpr 62.50 MiB -1 -1 0.14 17120 1 0.02 -1 -1 30024 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63996 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 24.1 MiB 0.07 160 2332 796 1082 454 62.5 MiB 0.02 0.00 1.2264 -24.1787 -1.2264 1.2264 0.34 0.000175241 0.000161634 0.008706 0.00803815 -1 -1 -1 -1 32 327 12 6.87369e+06 41921.5 586450. 2029.24 0.41 0.0280777 0.0241535 25474 144626 -1 286 11 164 164 7398 2391 1.01137 1.01137 -24.7636 -1.01137 0 0 744469. 2576.02 0.04 0.01 0.12 -1 -1 0.04 0.00504681 0.00448936 20 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_010bits.v common 2.07 vpr 62.51 MiB -1 -1 0.15 17260 1 0.02 -1 -1 30120 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64008 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 24.0 MiB 0.07 175 2101 728 1079 294 62.5 MiB 0.02 0.00 1.2374 -27.2124 -1.2374 1.2374 0.34 0.000193984 0.000179478 0.00761103 0.00704442 -1 -1 -1 -1 30 382 13 6.87369e+06 55895.4 556674. 1926.21 0.41 0.0291491 0.0249416 25186 138497 -1 293 13 196 196 9565 2925 1.01137 1.01137 -26.4753 -1.01137 0 0 706193. 2443.58 0.03 0.01 0.08 -1 -1 0.03 0.00399551 0.00355068 22 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_011bits.v common 2.24 vpr 62.55 MiB -1 -1 0.15 17412 1 0.02 -1 -1 30040 -1 -1 5 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64052 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 24.0 MiB 0.05 194 2488 794 1203 491 62.6 MiB 0.02 0.00 1.2484 -30.0694 -1.2484 1.2484 0.33 0.000210963 0.000194687 0.00835745 0.00773003 -1 -1 -1 -1 32 434 17 6.87369e+06 69869.2 586450. 2029.24 0.45 0.0313966 0.026865 25474 144626 -1 373 20 274 274 18397 5227 1.13667 1.13667 -31.3415 -1.13667 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0135594 0.0114399 24 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_012bits.v common 2.22 vpr 62.56 MiB -1 -1 0.16 17376 1 0.02 -1 -1 30204 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64060 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 24.0 MiB 0.06 241 3493 1152 1593 748 62.6 MiB 0.03 0.00 1.2594 -33.5756 -1.2594 1.2594 0.34 0.00022384 0.000206819 0.0111138 0.0102745 -1 -1 -1 -1 32 501 21 6.87369e+06 69869.2 586450. 2029.24 0.43 0.0379716 0.0326576 25474 144626 -1 425 8 199 199 11182 3603 0.989373 0.989373 -33.3362 -0.989373 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00518953 0.00458893 26 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_013bits.v common 2.80 vpr 62.49 MiB -1 -1 0.15 17308 1 0.02 -1 -1 30232 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63988 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 23.9 MiB 0.06 240 2998 1051 1663 284 62.5 MiB 0.03 0.00 1.2773 -35.5756 -1.2773 1.2773 0.33 0.000246381 0.00022827 0.00947207 0.00876673 -1 -1 -1 -1 30 618 21 6.87369e+06 69869.2 556674. 1926.21 1.12 0.0733815 0.0616699 25186 138497 -1 480 17 350 350 21752 6218 1.04437 1.04437 -34.6874 -1.04437 0 0 706193. 2443.58 0.03 0.02 0.09 -1 -1 0.03 0.00875841 0.00753696 28 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_014bits.v common 2.19 vpr 62.53 MiB -1 -1 0.16 17388 1 0.02 -1 -1 30104 -1 -1 7 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64032 29 15 104 105 1 74 51 17 17 289 -1 unnamed_device 23.9 MiB 0.07 310 4093 1402 1938 753 62.5 MiB 0.03 0.00 1.2814 -39.7439 -1.2814 1.2814 0.33 0.000252751 0.00023371 0.0117669 0.0108889 -1 -1 -1 -1 28 763 21 6.87369e+06 97816.9 531479. 1839.03 0.43 0.041926 0.0362437 24610 126494 -1 614 12 343 343 23714 6541 1.12567 1.12567 -40.5186 -1.12567 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.00730899 0.00637495 31 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_015bits.v common 2.29 vpr 62.38 MiB -1 -1 0.15 17576 1 0.02 -1 -1 30264 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63880 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 23.7 MiB 0.08 337 6389 2578 2834 977 62.4 MiB 0.05 0.00 1.65963 -43.635 -1.65963 1.65963 0.34 0.000271225 0.000250996 0.0184151 0.0170486 -1 -1 -1 -1 32 726 25 6.87369e+06 83843 586450. 2029.24 0.47 0.0547587 0.0475343 25474 144626 -1 583 15 400 400 26645 7674 1.12567 1.12567 -42.064 -1.12567 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.00894667 0.007769 32 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_016bits.v common 2.23 vpr 62.55 MiB -1 -1 0.16 17600 1 0.02 -1 -1 30052 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64056 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 23.9 MiB 0.08 354 5727 2338 3295 94 62.6 MiB 0.04 0.00 1.66373 -46.576 -1.66373 1.66373 0.33 0.00029115 0.000269841 0.0164547 0.0152586 -1 -1 -1 -1 30 765 19 6.87369e+06 83843 556674. 1926.21 0.43 0.0498673 0.043428 25186 138497 -1 646 22 430 430 29960 8573 1.22267 1.22267 -46.6259 -1.22267 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0125804 0.0108044 35 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_018bits.v common 2.21 vpr 62.46 MiB -1 -1 0.15 17420 1 0.02 -1 -1 30192 -1 -1 7 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63956 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 23.7 MiB 0.08 390 6188 2490 3601 97 62.5 MiB 0.04 0.00 1.68573 -53.5906 -1.68573 1.68573 0.33 0.000329317 0.000306042 0.0173699 0.0161432 -1 -1 -1 -1 30 851 16 6.87369e+06 97816.9 556674. 1926.21 0.44 0.0537216 0.0467985 25186 138497 -1 693 11 381 381 25789 7299 1.13037 1.13037 -51.5244 -1.13037 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0086009 0.00751161 38 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_020bits.v common 2.36 vpr 62.71 MiB -1 -1 0.15 17564 1 0.02 -1 -1 30288 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64220 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 23.7 MiB 0.08 447 8134 3300 4657 177 62.7 MiB 0.06 0.00 1.70773 -60.3017 -1.70773 1.70773 0.33 0.00036247 0.000336699 0.0215112 0.0200033 -1 -1 -1 -1 32 937 23 6.87369e+06 111791 586450. 2029.24 0.50 0.0651527 0.0569837 25474 144626 -1 774 21 527 527 36101 10508 1.18067 1.18067 -56.9294 -1.18067 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0145839 0.0125579 42 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_022bits.v common 2.78 vpr 62.66 MiB -1 -1 0.17 17644 1 0.03 -1 -1 30472 -1 -1 10 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 45 23 160 161 1 115 78 17 17 289 -1 unnamed_device 23.6 MiB 0.11 503 9208 3768 5283 157 62.7 MiB 0.06 0.00 1.72973 -67.8771 -1.72973 1.72973 0.33 0.000386869 0.00035906 0.02257 0.0209781 -1 -1 -1 -1 36 1109 22 6.87369e+06 139738 648988. 2245.63 0.82 0.0992719 0.0860563 26050 158493 -1 898 22 643 643 58388 16256 1.24467 1.24467 -62.8028 -1.24467 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0165817 0.0143669 47 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_024bits.v common 2.34 vpr 62.91 MiB -1 -1 0.17 17604 1 0.02 -1 -1 30380 -1 -1 9 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64424 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 23.7 MiB 0.09 607 6023 1283 4464 276 62.9 MiB 0.05 0.00 2.11206 -76.1943 -2.11206 2.11206 0.33 0.000426528 0.000396958 0.0153869 0.0143251 -1 -1 -1 -1 32 1299 16 6.87369e+06 125765 586450. 2029.24 0.48 0.0620614 0.0543264 25474 144626 -1 1097 14 609 609 45524 12761 1.34167 1.34167 -75.6214 -1.34167 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0127044 0.0111413 51 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_028bits.v common 2.41 vpr 62.80 MiB -1 -1 0.17 17660 1 0.03 -1 -1 30076 -1 -1 11 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 23.5 MiB 0.09 789 12307 2769 8813 725 62.8 MiB 0.08 0.00 2.15606 -94.5222 -2.15606 2.15606 0.33 0.000492644 0.000458135 0.0286183 0.0266446 -1 -1 -1 -1 32 1559 17 6.87369e+06 153712 586450. 2029.24 0.53 0.0833133 0.0738776 25474 144626 -1 1393 18 688 688 59523 16512 1.49997 1.49997 -95.1329 -1.49997 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0173005 0.0151701 58 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_032bits.v common 2.57 vpr 63.14 MiB -1 -1 0.17 17576 1 0.03 -1 -1 30072 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 23.6 MiB 0.11 981 17205 4139 12245 821 63.1 MiB 0.11 0.00 2.56039 -112.802 -2.56039 2.56039 0.34 0.0005709 0.000533122 0.0389788 0.0363756 -1 -1 -1 -1 32 1799 22 6.87369e+06 167686 586450. 2029.24 0.56 0.106634 0.0949936 25474 144626 -1 1617 15 720 720 63562 16203 1.47797 1.47797 -105.078 -1.47797 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0173981 0.0153283 67 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_048bits.v common 2.89 vpr 63.28 MiB -1 -1 0.15 17828 1 0.03 -1 -1 30264 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 24.0 MiB 0.12 1584 31076 9475 18689 2912 63.3 MiB 0.19 0.00 3.45705 -193.743 -3.45705 3.45705 0.34 0.0008684 0.000814632 0.0625391 0.0585774 -1 -1 -1 -1 32 3068 37 6.87369e+06 251529 586450. 2029.24 0.78 0.189406 0.170897 25474 144626 -1 2611 15 1093 1093 100501 26292 1.79097 1.79097 -171.802 -1.79097 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0264197 0.0236566 99 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_064bits.v common 3.73 vpr 64.25 MiB -1 -1 0.22 18156 1 0.04 -1 -1 30548 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65796 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 24.5 MiB 0.14 1992 52618 19565 29996 3057 64.3 MiB 0.34 0.01 4.35372 -280.144 -4.35372 4.35372 0.36 0.00122296 0.00115029 0.100997 0.0950032 -1 -1 -1 -1 34 3707 21 6.87369e+06 335372 618332. 2139.56 1.28 0.350781 0.318364 25762 151098 -1 3199 18 1360 1360 119854 30025 1.75637 1.75637 -212.671 -1.75637 0 0 787024. 2723.27 0.03 0.10 0.12 -1 -1 0.03 0.04213 0.0380291 131 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_004bits.v common 1.95 vpr 62.20 MiB -1 -1 0.14 17356 1 0.02 -1 -1 29912 -1 -1 2 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63688 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 23.6 MiB 0.05 64 316 84 203 29 62.2 MiB 0.01 0.00 0.789073 -10.2315 -0.789073 0.789073 0.37 6.7432e-05 5.9105e-05 0.0014023 0.00123038 -1 -1 -1 -1 20 131 13 6.89349e+06 28187.7 414966. 1435.87 0.30 0.005288 0.00462994 23170 95770 -1 112 9 43 43 1879 665 0.79102 0.79102 -9.88956 -0.79102 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00293029 0.00260954 10 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_005bits.v common 1.92 vpr 62.25 MiB -1 -1 0.16 17372 1 0.02 -1 -1 29916 -1 -1 3 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63744 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 23.5 MiB 0.03 158 587 141 409 37 62.2 MiB 0.01 0.00 0.834592 -14.4431 -0.834592 0.834592 0.34 0.000109323 9.9479e-05 0.00278401 0.00252793 -1 -1 -1 -1 22 303 8 6.89349e+06 42281.5 443629. 1535.05 0.32 0.0144953 0.0122181 23458 102101 -1 278 9 87 87 6583 1789 0.914373 0.914373 -16.0104 -0.914373 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00331916 0.00294637 13 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_006bits.v common 2.05 vpr 62.27 MiB -1 -1 0.15 17272 1 0.02 -1 -1 30048 -1 -1 4 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63760 13 7 48 49 1 33 24 17 17 289 -1 unnamed_device 23.6 MiB 0.05 133 1044 310 591 143 62.3 MiB 0.01 0.00 0.833073 -15.9272 -0.833073 0.833073 0.34 0.000124785 0.000114174 0.00422947 0.00386489 -1 -1 -1 -1 26 290 13 6.89349e+06 56375.4 503264. 1741.40 0.36 0.0182724 0.0154763 24322 120374 -1 221 12 125 125 5631 2000 0.94932 0.94932 -16.2556 -0.94932 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.0041284 0.00360823 15 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_007bits.v common 2.07 vpr 62.25 MiB -1 -1 0.09 17396 1 0.03 -1 -1 30132 -1 -1 3 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63740 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 23.8 MiB 0.04 133 1204 333 631 240 62.2 MiB 0.01 0.00 1.2044 -18.4031 -1.2044 1.2044 0.34 0.000139573 0.000128145 0.0049121 0.00451093 -1 -1 -1 -1 32 295 12 6.89349e+06 42281.5 586450. 2029.24 0.41 0.0205912 0.0174698 25474 144626 -1 203 14 129 129 5391 1760 0.853073 0.853073 -17.6358 -0.853073 0 0 744469. 2576.02 0.03 0.01 0.12 -1 -1 0.03 0.00488954 0.00422668 16 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_008bits.v common 1.99 vpr 62.19 MiB -1 -1 0.15 17216 1 0.02 -1 -1 29988 -1 -1 3 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63680 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 23.7 MiB 0.05 147 1877 621 864 392 62.2 MiB 0.02 0.00 1.2154 -21.3086 -1.2154 1.2154 0.33 0.000157194 0.000144466 0.00719049 0.006617 -1 -1 -1 -1 26 326 10 6.89349e+06 42281.5 503264. 1741.40 0.36 0.0239307 0.0204765 24322 120374 -1 297 13 172 172 9130 2854 1.11467 1.11467 -23.1377 -1.11467 0 0 618332. 2139.56 0.03 0.01 0.08 -1 -1 0.03 0.00521984 0.00452385 19 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_009bits.v common 2.15 vpr 62.36 MiB -1 -1 0.15 17412 1 0.02 -1 -1 30144 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63856 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 23.9 MiB 0.04 160 2382 879 1128 375 62.4 MiB 0.02 0.00 1.2264 -24.2382 -1.2264 1.2264 0.35 0.000196203 0.000178208 0.0083255 0.00754874 -1 -1 -1 -1 26 391 28 6.89349e+06 42281.5 503264. 1741.40 0.41 0.0303822 0.0257506 24322 120374 -1 301 12 172 172 9169 2958 0.88802 0.88802 -24.0325 -0.88802 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.0054245 0.00471594 20 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_010bits.v common 2.13 vpr 62.29 MiB -1 -1 0.16 17316 1 0.02 -1 -1 30208 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63788 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 23.8 MiB 0.05 178 2101 697 1026 378 62.3 MiB 0.03 0.00 1.2374 -27.3972 -1.2374 1.2374 0.34 0.000272143 0.000242871 0.014502 0.0134048 -1 -1 -1 -1 26 398 15 6.89349e+06 56375.4 503264. 1741.40 0.41 0.0366146 0.031747 24322 120374 -1 357 12 211 211 13104 3962 1.00232 1.00232 -27.9123 -1.00232 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00586481 0.00508309 22 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_011bits.v common 2.14 vpr 62.36 MiB -1 -1 0.15 17312 1 0.02 -1 -1 30020 -1 -1 5 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63856 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 23.9 MiB 0.05 194 2488 804 1234 450 62.4 MiB 0.02 0.00 1.2484 -29.9141 -1.2484 1.2484 0.34 0.000209881 0.00019386 0.00831107 0.00768353 -1 -1 -1 -1 32 419 16 6.89349e+06 70469.2 586450. 2029.24 0.44 0.0369654 0.0314569 25474 144626 -1 365 14 187 187 12612 3522 1.15867 1.15867 -31.3059 -1.15867 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00694411 0.00599348 24 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_012bits.v common 2.17 vpr 62.26 MiB -1 -1 0.16 17436 1 0.02 -1 -1 30088 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63756 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 23.7 MiB 0.05 217 3493 1104 1725 664 62.3 MiB 0.05 0.00 1.2594 -32.5677 -1.2594 1.2594 0.34 0.000304479 0.000281407 0.0209988 0.0194009 -1 -1 -1 -1 32 482 20 6.89349e+06 70469.2 586450. 2029.24 0.43 0.0482192 0.0420835 25474 144626 -1 389 12 280 280 15448 4965 1.02237 1.02237 -32.661 -1.02237 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00656711 0.00568522 26 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_013bits.v common 2.48 vpr 62.37 MiB -1 -1 0.16 17368 1 0.02 -1 -1 30088 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63868 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 23.8 MiB 0.05 241 2998 936 1427 635 62.4 MiB 0.03 0.00 1.2704 -35.731 -1.2704 1.2704 0.34 0.000238318 0.000220139 0.00954251 0.00882072 -1 -1 -1 -1 36 554 23 6.89349e+06 70469.2 648988. 2245.63 0.68 0.0569241 0.0482567 26050 158493 -1 470 11 304 304 20930 6434 1.17597 1.17597 -35.5601 -1.17597 0 0 828058. 2865.25 0.03 0.02 0.15 -1 -1 0.03 0.00655121 0.00571957 28 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_014bits.v common 2.30 vpr 62.49 MiB -1 -1 0.15 17252 1 0.03 -1 -1 30068 -1 -1 7 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63988 29 15 104 105 1 74 51 17 17 289 -1 unnamed_device 23.8 MiB 0.06 311 4093 1430 1919 744 62.5 MiB 0.03 0.00 1.2814 -39.6 -1.2814 1.2814 0.34 0.00025249 0.000233658 0.0117448 0.0108621 -1 -1 -1 -1 32 651 22 6.89349e+06 98656.9 586450. 2029.24 0.45 0.0440558 0.0379748 25474 144626 -1 546 15 298 298 20497 5584 0.96032 0.96032 -37.5765 -0.96032 0 0 744469. 2576.02 0.03 0.02 0.13 -1 -1 0.03 0.00837419 0.00725538 31 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_015bits.v common 2.23 vpr 62.42 MiB -1 -1 0.16 17588 1 0.02 -1 -1 30232 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63916 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 23.7 MiB 0.07 342 6191 2383 2979 829 62.4 MiB 0.04 0.00 1.65273 -42.5434 -1.65273 1.65273 0.35 0.000272263 0.000252147 0.0177761 0.0164574 -1 -1 -1 -1 28 782 16 6.89349e+06 84563 531479. 1839.03 0.47 0.050838 0.0446254 24610 126494 -1 632 16 412 412 30562 8836 1.09932 1.09932 -43.4614 -1.09932 0 0 648988. 2245.63 0.03 0.03 0.11 -1 -1 0.03 0.00917276 0.00791503 32 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_016bits.v common 2.23 vpr 62.59 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30196 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 23.9 MiB 0.07 355 5727 2349 2359 1019 62.6 MiB 0.04 0.00 1.66373 -46.554 -1.66373 1.66373 0.34 0.00029317 0.000271463 0.0164277 0.0152439 -1 -1 -1 -1 30 761 18 6.89349e+06 84563 556674. 1926.21 0.43 0.0452337 0.0395422 25186 138497 -1 615 14 322 322 20560 5635 1.13667 1.13667 -43.9673 -1.13667 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00900274 0.00782068 35 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_018bits.v common 2.26 vpr 62.61 MiB -1 -1 0.15 17668 1 0.02 -1 -1 30096 -1 -1 7 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64116 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 24.0 MiB 0.07 391 6563 2630 3842 91 62.6 MiB 0.05 0.00 1.68573 -53.2796 -1.68573 1.68573 0.33 0.000328745 0.0003059 0.0180114 0.01674 -1 -1 -1 -1 30 836 17 6.89349e+06 98656.9 556674. 1926.21 0.44 0.0548421 0.0477938 25186 138497 -1 695 15 451 451 29891 8374 1.03337 1.03337 -49.3183 -1.03337 0 0 706193. 2443.58 0.03 0.03 0.13 -1 -1 0.03 0.0118554 0.0102459 38 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 2.36 vpr 62.61 MiB -1 -1 0.15 17628 1 0.02 -1 -1 30352 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64108 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 23.6 MiB 0.06 444 7702 3109 4434 159 62.6 MiB 0.05 0.00 1.70773 -59.9521 -1.70773 1.70773 0.33 0.000367369 0.000341624 0.0204269 0.0189835 -1 -1 -1 -1 32 990 21 6.89349e+06 112751 586450. 2029.24 0.51 0.0631649 0.0551747 25474 144626 -1 819 18 512 512 38144 10646 1.11467 1.11467 -55.3744 -1.11467 0 0 744469. 2576.02 0.06 0.04 0.12 -1 -1 0.06 0.0153282 0.0133693 42 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 2.91 vpr 62.58 MiB -1 -1 0.17 17744 1 0.02 -1 -1 30460 -1 -1 10 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 45 23 160 161 1 115 78 17 17 289 -1 unnamed_device 23.5 MiB 0.10 525 9208 3753 5295 160 62.6 MiB 0.06 0.00 1.72973 -67.5033 -1.72973 1.72973 0.34 0.000392949 0.000365341 0.0227959 0.0211971 -1 -1 -1 -1 38 1007 50 6.89349e+06 140938 678818. 2348.85 0.90 0.1159 0.10007 26626 170182 -1 870 15 498 498 29786 8882 1.34722 1.34722 -61.6964 -1.34722 0 0 902133. 3121.57 0.04 0.03 0.15 -1 -1 0.04 0.0128133 0.0111561 47 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_024bits.v common 2.37 vpr 62.61 MiB -1 -1 0.16 17696 1 0.02 -1 -1 30324 -1 -1 9 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64116 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 23.5 MiB 0.08 661 9623 2236 7262 125 62.6 MiB 0.07 0.00 2.11206 -77.8242 -2.11206 2.11206 0.33 0.000423349 0.000394636 0.0238414 0.0221996 -1 -1 -1 -1 32 1386 20 6.89349e+06 126845 586450. 2029.24 0.50 0.0733721 0.0645323 25474 144626 -1 1142 15 563 563 48813 12563 1.46697 1.46697 -78.8793 -1.46697 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0131862 0.0115318 51 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 2.40 vpr 63.05 MiB -1 -1 0.14 17632 1 0.02 -1 -1 30148 -1 -1 11 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64564 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 23.6 MiB 0.08 791 11419 2578 8125 716 63.1 MiB 0.07 0.00 2.15606 -94.8463 -2.15606 2.15606 0.33 0.000485905 0.00045224 0.0262913 0.0244792 -1 -1 -1 -1 32 1495 15 6.89349e+06 155032 586450. 2029.24 0.50 0.0789967 0.0700395 25474 144626 -1 1370 17 655 655 52543 14035 1.33262 1.33262 -89.2547 -1.33262 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0163034 0.0142892 58 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 2.53 vpr 63.12 MiB -1 -1 0.17 17808 1 0.03 -1 -1 30108 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 23.6 MiB 0.09 986 17205 3974 12341 890 63.1 MiB 0.11 0.00 2.56039 -113.021 -2.56039 2.56039 0.33 0.000575876 0.000537719 0.0387672 0.0362165 -1 -1 -1 -1 30 1859 34 6.89349e+06 169126 556674. 1926.21 0.57 0.116327 0.103243 25186 138497 -1 1589 16 746 746 58837 14814 1.31532 1.31532 -101.149 -1.31532 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.0180394 0.0158572 67 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 2.95 vpr 63.42 MiB -1 -1 0.17 17756 1 0.03 -1 -1 30288 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64940 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 23.9 MiB 0.11 1569 31076 8349 20038 2689 63.4 MiB 0.19 0.00 3.45705 -193.838 -3.45705 3.45705 0.33 0.000873253 0.000818313 0.0625323 0.0585782 -1 -1 -1 -1 32 3055 34 6.89349e+06 253689 586450. 2029.24 0.75 0.184089 0.166063 25474 144626 -1 2514 15 1003 1003 86721 22065 1.69397 1.69397 -165.636 -1.69397 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0259565 0.0232087 99 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_064bits.v common 3.51 vpr 63.59 MiB -1 -1 0.17 17944 1 0.03 -1 -1 30596 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65112 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 24.4 MiB 0.15 2051 53273 20114 30300 2859 63.6 MiB 0.35 0.01 4.35372 -281.486 -4.35372 4.35372 0.33 0.00119747 0.00112577 0.101104 0.0950117 -1 -1 -1 -1 34 3564 19 6.89349e+06 338252 618332. 2139.56 1.07 0.340154 0.308577 25762 151098 -1 3156 13 1279 1279 97169 24263 1.63107 1.63107 -202.647 -1.63107 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0325631 0.0294317 131 2 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt index 8e03af2eb66..8d0853d10c4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt @@ -1,1025 +1,1025 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 6.67 vpr 63.87 MiB -1 -1 0.38 21968 14 0.32 -1 -1 36964 -1 -1 27 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 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9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65528 32 32 292 324 1 216 94 17 17 289 -1 unnamed_device 25.2 MiB 0.48 1429 10318 2408 6874 1036 64.0 MiB 0.08 0.00 7.55004 -148.529 -7.55004 7.55004 0.89 0.000355121 0.000289641 0.0192998 0.0157331 -1 -1 -1 -1 30 3702 21 6.55708e+06 361650 526063. 1820.29 1.65 0.103989 0.0904622 21886 126133 -1 3032 18 1348 4431 211919 49585 6.6027 6.6027 -144.169 -6.6027 0 0 666494. 2306.21 0.28 0.08 0.11 -1 -1 0.28 0.0235718 0.0212618 199 198 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 5.98 vpr 63.45 MiB -1 -1 0.27 21368 12 0.25 -1 -1 36280 -1 -1 28 27 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64972 27 32 229 261 1 178 87 17 17 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64772 30 32 216 248 1 168 86 17 17 289 -1 unnamed_device 24.8 MiB 0.52 975 6890 1484 5091 315 63.3 MiB 0.05 0.00 7.2876 -142.231 -7.2876 7.2876 1.10 0.000226144 0.000179001 0.0105934 0.00869922 -1 -1 -1 -1 28 2669 16 6.55708e+06 289320 500653. 1732.36 1.81 0.0706326 0.0616944 21310 115450 -1 2344 20 978 2637 155411 35551 6.35264 6.35264 -138.448 -6.35264 0 0 612192. 2118.31 0.29 0.06 0.11 -1 -1 0.29 0.0188124 0.0168309 132 128 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_012.v common 7.22 vpr 63.11 MiB -1 -1 0.25 21300 12 0.22 -1 -1 36160 -1 -1 22 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64624 32 32 236 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65652 32 32 301 333 1 230 97 17 17 289 -1 unnamed_device 25.3 MiB 0.52 1403 9865 2364 6534 967 64.1 MiB 0.08 0.00 7.61832 -157.97 -7.61832 7.61832 0.99 0.000327782 0.000258845 0.0189479 0.0155529 -1 -1 -1 -1 34 4162 40 6.55708e+06 397815 585099. 2024.56 3.52 0.164137 0.141129 22462 138074 -1 3561 16 1531 5053 312901 69003 7.03204 7.03204 -158.379 -7.03204 0 0 742403. 2568.87 0.31 0.12 0.13 -1 -1 0.31 0.0327397 0.030075 209 207 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_017.v common 7.55 vpr 63.92 MiB -1 -1 0.53 22016 14 0.32 -1 -1 36528 -1 -1 29 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65452 32 32 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65552 32 32 354 285 1 202 96 17 17 289 -1 unnamed_device 25.2 MiB 0.35 1021 13017 3203 8186 1628 64.0 MiB 0.11 0.00 5.56529 -159.911 -5.56529 5.56529 0.99 0.000262042 0.000209334 0.0174063 0.0141423 -1 -1 -1 -1 32 2485 24 6.64007e+06 401856 554710. 1919.41 1.14 0.0768703 0.0652357 22834 132086 -1 2178 21 1579 2366 153039 36543 4.64968 4.64968 -151.131 -4.64968 0 0 701300. 2426.64 0.34 0.06 0.14 -1 -1 0.34 0.0160783 0.0141966 154 50 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 4.99 vpr 64.14 MiB -1 -1 0.20 21392 1 0.04 -1 -1 33844 -1 -1 25 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65676 30 32 363 293 1 196 87 17 17 289 -1 unnamed_device 25.3 MiB 0.36 1071 13527 3636 8473 1418 64.1 MiB 0.10 0.00 4.97921 -144.408 -4.97921 4.97921 0.97 0.000238803 0.000193386 0.0186601 0.015077 -1 -1 -1 -1 32 2399 23 6.64007e+06 313950 554710. 1919.41 1.01 0.0633653 0.0530196 22834 132086 -1 2149 20 1658 2519 162674 39380 4.22689 4.22689 -145.337 -4.22689 0 0 701300. 2426.64 0.32 0.07 0.14 -1 -1 0.32 0.0201902 0.0180317 141 63 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 6.17 vpr 63.65 MiB -1 -1 0.20 21440 1 0.04 -1 -1 33860 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65176 32 32 299 247 1 188 87 17 17 289 -1 unnamed_device 25.0 MiB 0.37 1084 15639 4927 8621 2091 63.6 MiB 0.13 0.00 4.35433 -126.133 -4.35433 4.35433 1.59 0.000353368 0.000291955 0.0217877 0.0179552 -1 -1 -1 -1 32 2438 19 6.64007e+06 288834 554710. 1919.41 1.25 0.0699429 0.0595596 22834 132086 -1 2059 19 1091 1550 105201 24017 3.66183 3.66183 -123.368 -3.66183 0 0 701300. 2426.64 0.32 0.05 0.13 -1 -1 0.32 0.0145392 0.0129226 126 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 5.32 vpr 63.88 MiB -1 -1 0.22 21504 1 0.06 -1 -1 33624 -1 -1 27 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65412 29 32 308 248 1 169 88 17 17 289 -1 unnamed_device 25.2 MiB 0.14 931 15103 4868 7954 2281 63.9 MiB 0.11 0.00 4.52953 -121.776 -4.52953 4.52953 1.05 0.00019656 0.000155738 0.0174707 0.0140635 -1 -1 -1 -1 32 2287 23 6.64007e+06 339066 554710. 1919.41 1.16 0.0700707 0.0594773 22834 132086 -1 1914 23 1465 2740 192952 43744 3.67063 3.67063 -116.076 -3.67063 0 0 701300. 2426.64 0.39 0.08 0.16 -1 -1 0.39 0.0184129 0.0163026 126 31 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 4.89 vpr 64.08 MiB -1 -1 0.22 21580 1 0.06 -1 -1 33800 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65616 32 32 336 268 1 174 87 17 17 289 -1 unnamed_device 25.2 MiB 0.16 1007 10071 2662 6608 801 64.1 MiB 0.08 0.00 4.57112 -132.997 -4.57112 4.57112 0.92 0.000203708 0.000161888 0.0128959 0.0104931 -1 -1 -1 -1 32 2498 20 6.64007e+06 288834 554710. 1919.41 0.96 0.053404 0.0450429 22834 132086 -1 2122 21 1503 2874 185659 42276 3.64943 3.64943 -130.19 -3.64943 0 0 701300. 2426.64 0.30 0.07 0.14 -1 -1 0.30 0.0166273 0.0146895 130 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 5.30 vpr 64.21 MiB -1 -1 0.27 21392 1 0.06 -1 -1 33776 -1 -1 34 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65748 32 32 366 295 1 189 98 17 17 289 -1 unnamed_device 25.4 MiB 0.21 1017 13373 3190 9207 976 64.2 MiB 0.11 0.00 3.5011 -120.17 -3.5011 3.5011 0.99 0.000318473 0.00026043 0.0171614 0.0139947 -1 -1 -1 -1 28 2759 36 6.64007e+06 426972 500653. 1732.36 1.31 0.0862329 0.0726462 21970 115934 -1 2279 18 1387 2237 156657 37609 2.89817 2.89817 -120.057 -2.89817 0 0 612192. 2118.31 0.28 0.06 0.11 -1 -1 0.28 0.0162124 0.0141661 142 58 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 4.61 vpr 63.41 MiB -1 -1 0.20 21408 1 0.05 -1 -1 34356 -1 -1 19 27 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64928 27 32 259 221 1 130 78 17 17 289 -1 unnamed_device 24.9 MiB 0.14 699 11034 3536 5995 1503 63.4 MiB 0.07 0.00 3.75638 -102.609 -3.75638 3.75638 0.94 0.000156739 0.000123123 0.0131456 0.0106723 -1 -1 -1 -1 32 1595 18 6.64007e+06 238602 554710. 1919.41 0.87 0.0417151 0.0348347 22834 132086 -1 1412 20 879 1541 105739 24721 3.09756 3.09756 -96.0776 -3.09756 0 0 701300. 2426.64 0.31 0.04 0.13 -1 -1 0.31 0.0115122 0.0101614 93 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 5.62 vpr 63.45 MiB -1 -1 0.18 21640 1 0.03 -1 -1 33768 -1 -1 31 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64968 31 32 271 219 1 162 94 17 17 289 -1 unnamed_device 24.7 MiB 0.21 827 11383 2423 8400 560 63.4 MiB 0.08 0.00 3.48559 -101.391 -3.48559 3.48559 1.10 0.000211519 0.000168259 0.0119728 0.00969488 -1 -1 -1 -1 28 2163 36 6.64007e+06 389298 500653. 1732.36 1.29 0.0670566 0.0567176 21970 115934 -1 1858 21 1080 1973 129274 30214 2.87017 2.87017 -99.5446 -2.87017 0 0 612192. 2118.31 0.30 0.05 0.15 -1 -1 0.30 0.0147154 0.0129521 115 4 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 5.57 vpr 63.82 MiB -1 -1 0.22 21488 1 0.04 -1 -1 34160 -1 -1 20 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65352 31 32 317 271 1 167 83 17 17 289 -1 unnamed_device 25.0 MiB 0.40 888 14123 4595 7521 2007 63.8 MiB 0.09 0.00 3.62422 -120.034 -3.62422 3.62422 1.08 0.000187515 0.000146379 0.0174094 0.0140366 -1 -1 -1 -1 32 1992 19 6.64007e+06 251160 554710. 1919.41 1.10 0.0554197 0.0466476 22834 132086 -1 1743 19 1121 1661 106825 24557 2.99817 2.99817 -113.252 -2.99817 0 0 701300. 2426.64 0.41 0.06 0.16 -1 -1 0.41 0.0187606 0.016777 111 64 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 5.16 vpr 63.52 MiB -1 -1 0.33 21600 1 0.04 -1 -1 33748 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65040 32 32 298 248 1 156 81 17 17 289 -1 unnamed_device 25.0 MiB 0.24 874 11631 3631 6742 1258 63.5 MiB 0.10 0.00 3.92955 -127.77 -3.92955 3.92955 0.95 0.000189701 0.000150054 0.01562 0.0126926 -1 -1 -1 -1 32 1957 19 6.64007e+06 213486 554710. 1919.41 1.03 0.0525554 0.0441712 22834 132086 -1 1753 19 1044 1681 109300 25609 2.90177 2.90177 -115.584 -2.90177 0 0 701300. 2426.64 0.34 0.06 0.13 -1 -1 0.34 0.0152293 0.0134552 112 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 5.31 vpr 63.82 MiB -1 -1 0.33 21556 1 0.04 -1 -1 33372 -1 -1 17 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65352 30 32 303 262 1 139 79 17 17 289 -1 unnamed_device 24.9 MiB 0.18 728 11571 3255 7389 927 63.8 MiB 0.08 0.00 4.13115 -112.218 -4.13115 4.13115 0.99 0.00019662 0.000157478 0.0166224 0.0136254 -1 -1 -1 -1 28 1735 19 6.64007e+06 213486 500653. 1732.36 1.07 0.0606006 0.0517093 21970 115934 -1 1482 19 805 1293 87516 20285 2.86597 2.86597 -102.428 -2.86597 0 0 612192. 2118.31 0.39 0.05 0.14 -1 -1 0.39 0.0153816 0.0137322 98 63 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 5.44 vpr 63.54 MiB -1 -1 0.26 21364 1 0.05 -1 -1 33692 -1 -1 18 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65064 32 32 276 237 1 166 82 17 17 289 -1 unnamed_device 25.0 MiB 0.43 793 12008 4621 6063 1324 63.5 MiB 0.09 0.00 3.82041 -120.517 -3.82041 3.82041 1.09 0.000206546 0.00016439 0.0165982 0.0136384 -1 -1 -1 -1 32 2253 40 6.64007e+06 226044 554710. 1919.41 1.09 0.0618556 0.0518993 22834 132086 -1 1803 21 1195 1619 115534 26931 3.04337 3.04337 -115.258 -3.04337 0 0 701300. 2426.64 0.31 0.05 0.16 -1 -1 0.31 0.0126872 0.0111863 109 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 5.32 vpr 64.04 MiB -1 -1 0.21 21500 1 0.05 -1 -1 33892 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65576 32 32 344 272 1 202 88 17 17 289 -1 unnamed_device 25.3 MiB 0.39 1104 18028 6323 9464 2241 64.0 MiB 0.14 0.00 4.4826 -145.148 -4.4826 4.4826 0.94 0.000209899 0.000165632 0.0218027 0.0175323 -1 -1 -1 -1 32 2419 20 6.64007e+06 301392 554710. 1919.41 0.97 0.0592191 0.0492291 22834 132086 -1 2198 21 1658 2485 165389 37416 3.29783 3.29783 -129.319 -3.29783 0 0 701300. 2426.64 0.30 0.06 0.12 -1 -1 0.30 0.0171025 0.0151608 139 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 5.28 vpr 64.12 MiB -1 -1 0.25 21504 1 0.06 -1 -1 33764 -1 -1 31 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65656 32 32 363 295 1 181 95 17 17 289 -1 unnamed_device 25.1 MiB 0.20 965 15215 3853 10047 1315 64.1 MiB 0.13 0.00 4.76344 -140.281 -4.76344 4.76344 0.96 0.000216134 0.000170764 0.0181941 0.0146872 -1 -1 -1 -1 28 2304 23 6.64007e+06 389298 500653. 1732.36 0.97 0.0576001 0.047902 21970 115934 -1 2045 22 1662 2823 167404 40668 3.88183 3.88183 -136.686 -3.88183 0 0 612192. 2118.31 0.31 0.08 0.12 -1 -1 0.31 0.0224895 0.0200196 134 61 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 4.69 vpr 63.23 MiB -1 -1 0.19 21300 1 0.04 -1 -1 33776 -1 -1 21 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64752 29 32 248 215 1 137 82 17 17 289 -1 unnamed_device 24.7 MiB 0.16 748 11118 2695 7379 1044 63.2 MiB 0.07 0.00 3.28519 -93.7186 -3.28519 3.28519 1.02 0.000177763 0.000143001 0.0123985 0.0100246 -1 -1 -1 -1 28 1645 23 6.64007e+06 263718 500653. 1732.36 0.88 0.044401 0.0373413 21970 115934 -1 1486 16 782 1301 86789 20385 2.71577 2.71577 -91.5176 -2.71577 0 0 612192. 2118.31 0.27 0.04 0.11 -1 -1 0.27 0.01224 0.0110447 98 27 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 5.02 vpr 63.95 MiB -1 -1 0.22 21472 1 0.05 -1 -1 33820 -1 -1 22 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65488 32 32 370 297 1 183 86 17 17 289 -1 unnamed_device 25.2 MiB 0.26 1002 9914 2245 7192 477 64.0 MiB 0.09 0.00 4.06227 -126.501 -4.06227 4.06227 1.04 0.000339478 0.000280459 0.0150671 0.0122767 -1 -1 -1 -1 32 2466 22 6.64007e+06 276276 554710. 1919.41 1.00 0.0625471 0.0525543 22834 132086 -1 2152 20 1479 2608 179323 41071 3.09436 3.09436 -120.061 -3.09436 0 0 701300. 2426.64 0.32 0.06 0.13 -1 -1 0.32 0.0175048 0.0154791 133 58 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 5.42 vpr 64.18 MiB -1 -1 0.19 21340 1 0.05 -1 -1 33692 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65720 32 32 338 269 1 196 87 17 17 289 -1 unnamed_device 25.2 MiB 0.36 1138 14679 4370 8457 1852 64.2 MiB 0.11 0.00 4.43584 -143.418 -4.43584 4.43584 1.02 0.000208117 0.000164792 0.0181344 0.0146421 -1 -1 -1 -1 30 2626 19 6.64007e+06 288834 526063. 1820.29 0.98 0.0603549 0.0505747 22546 126617 -1 2242 21 1375 2016 134012 29343 3.26883 3.26883 -128.611 -3.26883 0 0 666494. 2306.21 0.36 0.07 0.17 -1 -1 0.36 0.0224568 0.0201398 138 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 5.32 vpr 63.82 MiB -1 -1 0.30 21340 1 0.05 -1 -1 33492 -1 -1 29 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65352 32 32 323 276 1 153 93 17 17 289 -1 unnamed_device 25.0 MiB 0.26 793 7443 1484 5603 356 63.8 MiB 0.06 0.00 2.85064 -101.719 -2.85064 2.85064 1.07 0.000198513 0.000156054 0.00909122 0.00743855 -1 -1 -1 -1 30 1881 18 6.64007e+06 364182 526063. 1820.29 0.90 0.0436512 0.0367 22546 126617 -1 1524 20 1018 1637 84819 20502 2.06951 2.06951 -94.0823 -2.06951 0 0 666494. 2306.21 0.33 0.05 0.13 -1 -1 0.33 0.0163235 0.0143174 110 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 4.87 vpr 63.29 MiB -1 -1 0.22 21284 1 0.05 -1 -1 33884 -1 -1 15 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64812 30 32 222 206 1 117 77 17 17 289 -1 unnamed_device 24.7 MiB 0.09 601 7249 1675 5111 463 63.3 MiB 0.05 0.00 2.38033 -78.5571 -2.38033 2.38033 1.07 0.000226234 0.000187174 0.00846696 0.00685607 -1 -1 -1 -1 28 1432 21 6.64007e+06 188370 500653. 1732.36 0.93 0.041199 0.0342952 21970 115934 -1 1285 21 703 1012 85737 19690 2.04611 2.04611 -83.9383 -2.04611 0 0 612192. 2118.31 0.32 0.07 0.11 -1 -1 0.32 0.0196938 0.0172901 81 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 4.90 vpr 63.76 MiB -1 -1 0.20 21368 1 0.04 -1 -1 34160 -1 -1 20 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65288 31 32 291 243 1 171 83 17 17 289 -1 unnamed_device 25.2 MiB 0.32 927 14123 4588 7430 2105 63.8 MiB 0.11 0.00 4.95484 -148.86 -4.95484 4.95484 0.99 0.000188824 0.000149089 0.0186224 0.0151145 -1 -1 -1 -1 30 2054 21 6.64007e+06 251160 526063. 1820.29 0.95 0.0564355 0.0468617 22546 126617 -1 1848 20 956 1399 83300 19321 3.50023 3.50023 -130.959 -3.50023 0 0 666494. 2306.21 0.31 0.04 0.12 -1 -1 0.31 0.0130819 0.0114957 128 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 4.97 vpr 63.84 MiB -1 -1 0.20 21504 1 0.04 -1 -1 33988 -1 -1 31 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65368 32 32 342 271 1 179 95 17 17 289 -1 unnamed_device 24.9 MiB 0.14 927 7007 1409 5318 280 63.8 MiB 0.07 0.00 4.20815 -131.502 -4.20815 4.20815 1.01 0.00023098 0.000185719 0.00998554 0.00820313 -1 -1 -1 -1 30 2145 21 6.64007e+06 389298 526063. 1820.29 1.14 0.0561432 0.0479782 22546 126617 -1 1871 22 1181 1998 116468 26613 3.49343 3.49343 -124.596 -3.49343 0 0 666494. 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64908 32 32 285 227 1 165 85 17 17 289 -1 unnamed_device 24.9 MiB 0.13 995 9571 2665 6351 555 63.4 MiB 0.08 0.00 4.78226 -126.055 -4.78226 4.78226 0.96 0.000205893 0.000165719 0.0121023 0.00991669 -1 -1 -1 -1 28 2148 21 6.64007e+06 263718 500653. 1732.36 1.00 0.0515538 0.0439022 21970 115934 -1 1974 21 1150 2159 136149 31256 3.72363 3.72363 -120.986 -3.72363 0 0 612192. 2118.31 0.31 0.06 0.12 -1 -1 0.31 0.0155218 0.0138177 118 3 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 4.81 vpr 63.03 MiB -1 -1 0.19 21208 1 0.06 -1 -1 33524 -1 -1 14 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64540 32 32 173 169 1 116 78 17 17 289 -1 unnamed_device 24.6 MiB 0.08 542 9374 3354 4039 1981 63.0 MiB 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64932 32 32 284 241 1 145 80 17 17 289 -1 unnamed_device 24.7 MiB 0.12 785 11260 3393 5970 1897 63.4 MiB 0.07 0.00 3.03896 -100.907 -3.03896 3.03896 0.94 0.000176898 0.00013967 0.0136204 0.0110501 -1 -1 -1 -1 32 1803 19 6.64007e+06 200928 554710. 1919.41 0.91 0.0451775 0.0379823 22834 132086 -1 1509 18 768 1281 82415 19190 2.69497 2.69497 -101.097 -2.69497 0 0 701300. 2426.64 0.32 0.04 0.12 -1 -1 0.32 0.0127569 0.0112808 101 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 5.06 vpr 63.28 MiB -1 -1 0.32 21604 1 0.04 -1 -1 33544 -1 -1 23 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64800 30 32 262 227 1 135 85 17 17 289 -1 unnamed_device 24.8 MiB 0.12 760 10873 2730 7151 992 63.3 MiB 0.07 0.00 3.24119 -98.8846 -3.24119 3.24119 0.98 0.000228736 0.000184866 0.0130461 0.0105578 -1 -1 -1 -1 32 1618 23 6.64007e+06 288834 554710. 1919.41 0.95 0.0475561 0.0394843 22834 132086 -1 1566 17 817 1243 85514 19258 2.68277 2.68277 -96.8564 -2.68277 0 0 701300. 2426.64 0.48 0.07 0.14 -1 -1 0.48 0.0185708 0.0165051 97 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 4.97 vpr 63.43 MiB -1 -1 0.20 21612 1 0.04 -1 -1 33908 -1 -1 23 28 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64956 28 32 260 223 1 140 83 17 17 289 -1 unnamed_device 24.8 MiB 0.19 598 14123 3741 8412 1970 63.4 MiB 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65872 32 32 367 282 1 201 102 17 17 289 -1 unnamed_device 25.4 MiB 0.24 1108 10812 2420 7290 1102 64.3 MiB 0.10 0.00 4.35696 -124.357 -4.35696 4.35696 1.12 0.000281467 0.000232586 0.0135953 0.01126 -1 -1 -1 -1 26 3426 39 6.64007e+06 477204 477104. 1650.88 2.25 0.0816647 0.0694832 21682 110474 -1 2530 19 1336 2472 192577 43808 3.82982 3.82982 -127.968 -3.82982 0 0 585099. 2024.56 0.30 0.07 0.12 -1 -1 0.30 0.0175832 0.0156085 151 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 5.44 vpr 64.26 MiB -1 -1 0.24 21768 1 0.04 -1 -1 34128 -1 -1 37 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65716 31 32 352 285 1 184 94 17 17 289 -1 unnamed_device 25.3 MiB 0.24 1006 12661 3249 8412 1000 64.2 MiB 0.16 0.01 4.68524 -135.636 -4.68524 4.68524 1.03 0.000722622 0.000625663 0.0250127 0.0210209 -1 -1 -1 -1 32 2355 20 6.64007e+06 389298 554710. 1919.41 1.21 0.0832415 0.0717902 22834 132086 -1 2083 21 944 1573 101119 23699 3.58023 3.58023 -126.148 -3.58023 0 0 701300. 2426.64 0.32 0.05 0.15 -1 -1 0.32 0.0158948 0.0139738 135 55 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 5.56 vpr 63.61 MiB -1 -1 0.26 21404 1 0.03 -1 -1 33824 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65132 32 32 291 242 1 179 87 17 17 289 -1 unnamed_device 25.0 MiB 0.53 1073 14679 4707 8091 1881 63.6 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65572 32 32 349 284 1 183 97 17 17 289 -1 unnamed_device 25.2 MiB 0.25 884 8755 1783 6202 770 64.0 MiB 0.07 0.00 3.97129 -116.286 -3.97129 3.97129 0.94 0.000211094 0.000165612 0.0106346 0.00864227 -1 -1 -1 -1 30 2199 23 6.64007e+06 414414 526063. 1820.29 1.19 0.0625556 0.0533276 22546 126617 -1 1729 19 894 1557 79184 20282 3.00716 3.00716 -105.065 -3.00716 0 0 666494. 2306.21 0.30 0.04 0.12 -1 -1 0.30 0.0143951 0.0127001 131 53 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 5.18 vpr 63.77 MiB -1 -1 0.25 21256 1 0.05 -1 -1 33536 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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33904 -1 -1 29 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65020 32 32 306 248 1 166 93 17 17 289 -1 unnamed_device 24.9 MiB 0.14 831 7023 1481 5311 231 63.5 MiB 0.06 0.00 4.19967 -120.534 -4.19967 4.19967 0.89 0.000188041 0.000148682 0.00905889 0.00752255 -1 -1 -1 -1 30 2034 22 6.64007e+06 364182 526063. 1820.29 0.94 0.0439327 0.0370242 22546 126617 -1 1614 21 1040 1872 100357 23807 3.57043 3.57043 -112.869 -3.57043 0 0 666494. 2306.21 0.29 0.04 0.12 -1 -1 0.29 0.0137281 0.0120905 122 24 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 5.40 vpr 64.20 MiB -1 -1 0.19 21432 1 0.04 -1 -1 33776 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 319 257 1 198 88 17 17 289 -1 unnamed_device 25.2 MiB 0.45 1052 7888 1681 5591 616 64.2 MiB 0.08 0.00 5.2222 -143.082 -5.2222 5.2222 1.09 0.000318555 0.000263924 0.013931 0.0116803 -1 -1 -1 -1 28 2639 22 6.64007e+06 301392 500653. 1732.36 1.08 0.0632308 0.0538295 21970 115934 -1 2239 17 1340 1967 134731 31386 3.71362 3.71362 -131.242 -3.71362 0 0 612192. 2118.31 0.31 0.06 0.12 -1 -1 0.31 0.0160942 0.0142582 133 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 5.29 vpr 64.23 MiB -1 -1 0.22 21816 1 0.06 -1 -1 33676 -1 -1 25 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65776 31 32 373 299 1 202 88 17 17 289 -1 unnamed_device 25.4 MiB 0.39 1063 10423 2679 6644 1100 64.2 MiB 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65540 32 32 387 293 1 234 93 17 17 289 -1 unnamed_device 25.6 MiB 0.40 1389 17943 5716 10178 2049 64.0 MiB 0.17 0.00 5.4603 -164.178 -5.4603 5.4603 1.18 0.000282336 0.000220511 0.0250041 0.0204041 -1 -1 -1 -1 28 3504 25 6.64007e+06 364182 500653. 1732.36 1.52 0.0959882 0.0817493 21970 115934 -1 2796 23 2045 3229 234229 51765 4.64188 4.64188 -157.599 -4.64188 0 0 612192. 2118.31 0.27 0.08 0.11 -1 -1 0.27 0.0202234 0.0178275 169 31 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 5.19 vpr 63.91 MiB -1 -1 0.28 21560 1 0.04 -1 -1 33716 -1 -1 32 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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21180 1 0.05 -1 -1 33872 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65108 32 32 231 199 1 140 87 17 17 289 -1 unnamed_device 25.0 MiB 0.14 820 12375 3515 6889 1971 63.6 MiB 0.08 0.00 3.58247 -102.606 -3.58247 3.58247 0.97 0.000159828 0.000126602 0.0121084 0.00973774 -1 -1 -1 -1 26 1980 30 6.64007e+06 288834 477104. 1650.88 1.06 0.051103 0.0428844 21682 110474 -1 1821 19 887 1524 111639 25164 2.89497 2.89497 -103.885 -2.89497 0 0 585099. 2024.56 0.27 0.05 0.10 -1 -1 0.27 0.0120726 0.0105132 100 3 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 5.05 vpr 64.29 MiB -1 -1 0.23 21640 1 0.04 -1 -1 33820 -1 -1 34 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 349 273 1 191 98 17 17 289 -1 unnamed_device 25.5 MiB 0.20 1051 10223 2392 7301 530 64.3 MiB 0.10 0.00 5.62381 -137.312 -5.62381 5.62381 1.04 0.000244483 0.000192777 0.013702 0.011257 -1 -1 -1 -1 32 2518 24 6.64007e+06 426972 554710. 1919.41 1.12 0.0618896 0.0527029 22834 132086 -1 2171 22 1308 2453 164918 36700 4.71868 4.71868 -136.031 -4.71868 0 0 701300. 2426.64 0.32 0.06 0.13 -1 -1 0.32 0.0164181 0.0144813 139 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 4.59 vpr 63.52 MiB -1 -1 0.17 21200 1 0.05 -1 -1 33872 -1 -1 20 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65048 32 32 247 207 1 147 84 17 17 289 -1 unnamed_device 25.0 MiB 0.12 692 7404 1537 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65416 32 32 353 285 1 181 92 17 17 289 -1 unnamed_device 25.2 MiB 0.19 1028 16652 5035 9308 2309 63.9 MiB 0.14 0.00 4.7434 -142.045 -4.7434 4.7434 0.97 0.000229766 0.00018499 0.0243846 0.0198378 -1 -1 -1 -1 32 2433 20 6.64007e+06 351624 554710. 1919.41 1.00 0.06708 0.0561858 22834 132086 -1 2181 18 1038 1785 133597 29133 3.69062 3.69062 -131.911 -3.69062 0 0 701300. 2426.64 0.33 0.05 0.13 -1 -1 0.33 0.0149977 0.0132236 133 51 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 5.50 vpr 63.62 MiB -1 -1 0.21 21616 1 0.05 -1 -1 33724 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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21492 1 0.04 -1 -1 34116 -1 -1 18 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65384 30 32 317 269 1 152 80 17 17 289 -1 unnamed_device 25.1 MiB 0.18 685 9712 2247 6957 508 63.9 MiB 0.08 0.00 3.90078 -114.184 -3.90078 3.90078 0.96 0.000194964 0.000153905 0.0128951 0.0104153 -1 -1 -1 -1 28 1963 19 6.64007e+06 226044 500653. 1732.36 0.97 0.0472529 0.0394904 21970 115934 -1 1789 22 1400 2435 194018 45480 2.98097 2.98097 -109.97 -2.98097 0 0 612192. 2118.31 0.28 0.07 0.12 -1 -1 0.28 0.0167959 0.0148587 109 63 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 5.24 vpr 64.14 MiB -1 -1 0.33 21572 1 0.06 -1 -1 33652 -1 -1 21 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65104 30 32 272 232 1 147 81 17 17 289 -1 unnamed_device 24.9 MiB 0.16 720 9706 2873 5961 872 63.6 MiB 0.07 0.00 3.87875 -113.748 -3.87875 3.87875 0.91 0.00018793 0.000151889 0.0114303 0.00926962 -1 -1 -1 -1 26 1992 21 6.64007e+06 238602 477104. 1650.88 1.06 0.049573 0.0421375 21682 110474 -1 1698 18 953 1613 112771 26555 2.90297 2.90297 -105.777 -2.90297 0 0 585099. 2024.56 0.26 0.05 0.12 -1 -1 0.26 0.0129574 0.0114093 104 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 5.81 vpr 64.20 MiB -1 -1 0.22 21484 1 0.05 -1 -1 34016 -1 -1 23 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65700 29 32 378 310 1 177 92 17 17 289 -1 unnamed_device 25.4 MiB 0.23 991 14168 3722 8736 1710 64.2 MiB 0.10 0.00 4.90164 -138.394 -4.90164 4.90164 0.95 0.000240485 0.000190466 0.0175885 0.0141857 -1 -1 -1 -1 26 2358 19 6.64007e+06 389298 477104. 1650.88 0.87 0.0554864 0.0462143 21682 110474 -1 2059 21 1193 1929 132387 29914 3.62843 3.62843 -127.623 -3.62843 0 0 585099. 2024.56 0.25 0.05 0.11 -1 -1 0.25 0.0161528 0.0141862 132 85 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 4.70 vpr 63.33 MiB -1 -1 0.25 21144 1 0.05 -1 -1 33904 -1 -1 15 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64848 32 32 243 205 1 139 79 17 17 289 -1 unnamed_device 24.9 MiB 0.11 698 12416 3955 6725 1736 63.3 MiB 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65008 31 32 245 205 1 150 84 17 17 289 -1 unnamed_device 24.9 MiB 0.20 781 9417 2297 6451 669 63.5 MiB 0.07 0.00 3.81035 -109.522 -3.81035 3.81035 0.99 0.000163905 0.000129827 0.0101809 0.00828012 -1 -1 -1 -1 32 1805 21 6.64007e+06 263718 554710. 1919.41 1.21 0.072009 0.0621269 22834 132086 -1 1623 22 1006 1686 116113 26730 2.91397 2.91397 -103.946 -2.91397 0 0 701300. 2426.64 0.30 0.04 0.13 -1 -1 0.30 0.0115767 0.0101536 106 4 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 5.45 vpr 64.18 MiB -1 -1 0.23 21704 1 0.05 -1 -1 34084 -1 -1 26 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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0.04 -1 -1 34048 -1 -1 21 27 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64872 27 32 255 219 1 132 80 17 17 289 -1 unnamed_device 24.8 MiB 0.11 565 12120 3265 7503 1352 63.4 MiB 0.07 0.00 3.49724 -93.0073 -3.49724 3.49724 1.03 0.000169753 0.000135028 0.0143122 0.0115101 -1 -1 -1 -1 28 1552 21 6.64007e+06 263718 500653. 1732.36 0.90 0.0472616 0.0391207 21970 115934 -1 1349 20 1009 1487 99406 23958 2.83997 2.83997 -92.1671 -2.83997 0 0 612192. 2118.31 0.29 0.04 0.12 -1 -1 0.29 0.0120089 0.0104757 97 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 6.88 vpr 64.02 MiB -1 -1 0.23 21820 1 0.04 -1 -1 33960 -1 -1 26 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65560 32 32 421 327 1 232 90 17 17 289 -1 unnamed_device 25.5 MiB 0.40 1324 16572 5072 8808 2692 64.0 MiB 0.18 0.00 4.42635 -141.521 -4.42635 4.42635 1.59 0.00121267 0.00107701 0.0369494 0.0309745 -1 -1 -1 -1 32 3259 35 6.64007e+06 326508 554710. 1919.41 1.59 0.136479 0.117122 22834 132086 -1 2737 20 1821 3112 227397 48414 4.03623 4.03623 -137.329 -4.03623 0 0 701300. 2426.64 0.29 0.07 0.23 -1 -1 0.29 0.0169385 0.0148813 170 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 5.45 vpr 63.98 MiB -1 -1 0.23 21860 1 0.05 -1 -1 34032 -1 -1 23 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65512 31 32 365 296 1 193 86 17 17 289 -1 unnamed_device 25.2 MiB 0.47 1050 12371 3182 7852 1337 64.0 MiB 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65424 30 32 325 268 1 171 93 17 17 289 -1 unnamed_device 25.0 MiB 0.22 1000 10173 2480 6565 1128 63.9 MiB 0.12 0.00 3.68089 -112.079 -3.68089 3.68089 1.02 0.000444252 0.000360705 0.0216755 0.0182489 -1 -1 -1 -1 32 2189 21 6.64007e+06 389298 554710. 1919.41 1.11 0.0855121 0.0731107 22834 132086 -1 1934 21 992 1861 125297 27515 2.93217 2.93217 -104.52 -2.93217 0 0 701300. 2426.64 0.41 0.07 0.17 -1 -1 0.41 0.0232143 0.0207969 124 51 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 5.60 vpr 64.41 MiB -1 -1 0.27 21612 1 0.04 -1 -1 33768 -1 -1 25 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65960 32 32 350 275 1 214 89 17 17 289 -1 unnamed_device 25.5 MiB 0.43 1181 8207 1889 5862 456 64.4 MiB 0.09 0.00 5.21333 -162.921 -5.21333 5.21333 1.03 0.000226497 0.000177397 0.0119918 0.00982629 -1 -1 -1 -1 32 2916 22 6.64007e+06 313950 554710. 1919.41 1.32 0.0706068 0.0607564 22834 132086 -1 2540 21 1769 2749 219470 47322 4.11269 4.11269 -146.472 -4.11269 0 0 701300. 2426.64 0.31 0.07 0.12 -1 -1 0.31 0.0180291 0.0158781 148 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 5.98 vpr 64.14 MiB -1 -1 0.24 21904 1 0.05 -1 -1 33800 -1 -1 36 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65680 32 32 386 307 1 195 100 17 17 289 -1 unnamed_device 25.3 MiB 0.25 1091 17268 5141 9536 2591 64.1 MiB 0.13 0.00 4.75546 -148.32 -4.75546 4.75546 0.98 0.000234527 0.000184907 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0.05 -1 -1 33752 -1 -1 37 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65512 31 32 326 261 1 177 100 17 17 289 -1 unnamed_device 25.0 MiB 0.15 1008 6132 1183 4581 368 64.0 MiB 0.06 0.00 4.78944 -127.311 -4.78944 4.78944 0.95 0.000208465 0.000165707 0.00769296 0.00640021 -1 -1 -1 -1 26 2494 22 6.64007e+06 464646 477104. 1650.88 1.17 0.0580782 0.050279 21682 110474 -1 2169 20 1399 2498 165534 38412 3.93603 3.93603 -128.563 -3.93603 0 0 585099. 2024.56 0.35 0.06 0.11 -1 -1 0.35 0.0154133 0.0136646 129 33 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 5.34 vpr 63.46 MiB -1 -1 0.22 21368 1 0.04 -1 -1 33864 -1 -1 22 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64988 29 32 262 224 1 168 83 17 17 289 -1 unnamed_device 24.7 MiB 0.35 764 14303 4579 7529 2195 63.5 MiB 0.10 0.00 4.38281 -116.371 -4.38281 4.38281 1.05 0.000167696 0.000132554 0.0160852 0.0129068 -1 -1 -1 -1 28 2083 19 6.64007e+06 276276 500653. 1732.36 1.20 0.071621 0.0616544 21970 115934 -1 1681 20 1101 1443 96185 22508 3.23483 3.23483 -107.841 -3.23483 0 0 612192. 2118.31 0.26 0.04 0.12 -1 -1 0.26 0.0117702 0.0103844 109 31 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 5.19 vpr 63.41 MiB -1 -1 0.29 21540 1 0.05 -1 -1 34048 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64936 32 32 278 238 1 149 81 17 17 289 -1 unnamed_device 24.8 MiB 0.17 868 10406 2691 6847 868 63.4 MiB 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65736 31 32 396 325 1 183 95 17 17 289 -1 unnamed_device 25.4 MiB 0.32 974 12839 3425 8126 1288 64.2 MiB 0.10 0.00 4.34696 -135.951 -4.34696 4.34696 1.06 0.000228512 0.00018017 0.0161538 0.0130422 -1 -1 -1 -1 32 2188 19 6.64007e+06 401856 554710. 1919.41 0.95 0.0580896 0.0484063 22834 132086 -1 1958 21 1309 1812 123981 28855 3.33103 3.33103 -127.587 -3.33103 0 0 701300. 2426.64 0.35 0.05 0.13 -1 -1 0.35 0.0177756 0.0157005 138 91 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 5.16 vpr 63.85 MiB -1 -1 0.20 21480 1 0.04 -1 -1 33688 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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0.04 -1 -1 34104 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 393 312 1 213 88 17 17 289 -1 unnamed_device 25.2 MiB 0.43 846 9643 2135 6651 857 64.2 MiB 0.10 0.00 5.52409 -167.953 -5.52409 5.52409 1.02 0.000238583 0.000188463 0.0151312 0.0123654 -1 -1 -1 -1 34 2787 38 6.64007e+06 301392 585099. 2024.56 2.18 0.118619 0.100601 23122 138558 -1 1936 24 1573 2308 150807 38792 4.46809 4.46809 -156.232 -4.46809 0 0 742403. 2568.87 0.30 0.06 0.13 -1 -1 0.30 0.0185594 0.0162769 154 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 5.01 vpr 63.35 MiB -1 -1 0.27 21184 1 0.05 -1 -1 33660 -1 -1 18 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64872 31 32 229 197 1 138 81 17 17 289 -1 unnamed_device 24.9 MiB 0.18 599 7956 1801 5879 276 63.4 MiB 0.06 0.00 3.65226 -97.6941 -3.65226 3.65226 0.97 0.000190565 0.000150085 0.00942531 0.00774206 -1 -1 -1 -1 32 1638 19 6.64007e+06 226044 554710. 1919.41 0.96 0.0388896 0.0328137 22834 132086 -1 1460 18 787 1272 92647 21532 2.73697 2.73697 -94.3223 -2.73697 0 0 701300. 2426.64 0.36 0.04 0.14 -1 -1 0.36 0.0118549 0.0104435 96 4 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 5.43 vpr 64.33 MiB -1 -1 0.24 21600 1 0.04 -1 -1 33936 -1 -1 34 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65876 32 32 412 334 1 190 98 17 17 289 -1 unnamed_device 25.3 MiB 0.22 954 8873 1826 6622 425 64.3 MiB 0.08 0.00 4.24713 -140.193 -4.24713 4.24713 1.05 0.00023769 0.000187586 0.0117671 0.00955573 -1 -1 -1 -1 28 2572 31 6.64007e+06 426972 500653. 1732.36 1.22 0.0680236 0.0576681 21970 115934 -1 2175 22 1537 2339 173372 39376 3.93503 3.93503 -141.075 -3.93503 0 0 612192. 2118.31 0.36 0.08 0.15 -1 -1 0.36 0.0222961 0.0195268 145 90 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 5.14 vpr 63.83 MiB -1 -1 0.22 21560 1 0.04 -1 -1 33952 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65360 32 32 376 318 1 155 81 17 17 289 -1 unnamed_device 25.0 MiB 0.33 874 12856 4533 6666 1657 63.8 MiB 0.09 0.00 3.54047 -123.335 -3.54047 3.54047 1.01 0.000213253 0.000167159 0.0183628 0.0147903 -1 -1 -1 -1 32 1825 21 6.64007e+06 213486 554710. 1919.41 0.96 0.0594558 0.0495771 22834 132086 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65132 30 32 224 207 1 137 80 17 17 289 -1 unnamed_device 25.1 MiB 0.26 724 10744 2740 6987 1017 63.6 MiB 0.06 0.00 3.31307 -103.05 -3.31307 3.31307 1.04 0.000147902 0.000116257 0.0110141 0.00883102 -1 -1 -1 -1 32 1572 19 6.64007e+06 226044 554710. 1919.41 0.97 0.0409312 0.0340667 22834 132086 -1 1483 13 658 840 62111 14307 2.32491 2.32491 -94.088 -2.32491 0 0 701300. 2426.64 0.34 0.03 0.14 -1 -1 0.34 0.00919577 0.00818263 87 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 4.91 vpr 63.53 MiB -1 -1 0.33 21556 1 0.04 -1 -1 33684 -1 -1 16 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65052 30 32 286 239 1 134 78 17 17 289 -1 unnamed_device 24.8 MiB 0.11 653 10370 2942 6125 1303 63.5 MiB 0.07 0.00 4.12598 -117.274 -4.12598 4.12598 0.99 0.000203431 0.000163226 0.0139423 0.0113538 -1 -1 -1 -1 26 1686 20 6.64007e+06 200928 477104. 1650.88 0.98 0.0549514 0.0463637 21682 110474 -1 1476 18 837 1320 110296 24299 2.92297 2.92297 -108.566 -2.92297 0 0 585099. 2024.56 0.25 0.04 0.11 -1 -1 0.25 0.012556 0.0111293 92 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 5.01 vpr 62.90 MiB -1 -1 0.24 21556 1 0.03 -1 -1 33696 -1 -1 21 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64408 32 32 296 247 1 157 85 17 17 289 -1 unnamed_device 24.4 MiB 0.12 882 10687 2740 7287 660 62.9 MiB 0.08 0.00 3.50309 -113.66 -3.50309 3.50309 1.06 0.000193155 0.000153084 0.0131685 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1 0.06 -1 -1 34132 -1 -1 35 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65764 31 32 409 331 1 191 98 17 17 289 -1 unnamed_device 25.3 MiB 0.24 961 9998 2423 6940 635 64.2 MiB 0.09 0.00 4.49598 -142.588 -4.49598 4.49598 0.95 0.000241488 0.000191424 0.0138518 0.0113675 -1 -1 -1 -1 32 2313 19 6.64007e+06 439530 554710. 1919.41 0.95 0.0547129 0.0455445 22834 132086 -1 1958 17 1274 1962 116698 27985 3.33083 3.33083 -125.991 -3.33083 0 0 701300. 2426.64 0.34 0.05 0.16 -1 -1 0.34 0.0161459 0.0142364 143 90 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 5.29 vpr 64.05 MiB -1 -1 0.23 21492 1 0.06 -1 -1 33880 -1 -1 30 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65588 32 32 354 285 1 202 94 17 17 289 -1 unnamed_device 25.2 MiB 0.57 1143 17347 5477 9563 2307 64.1 MiB 0.14 0.00 5.20258 -155.488 -5.20258 5.20258 0.96 0.000274734 0.000221509 0.0207637 0.0168695 -1 -1 -1 -1 28 2696 21 6.65987e+06 380340 500653. 1732.36 1.00 0.0626627 0.0526058 21970 115934 -1 2338 20 1526 2351 162828 36705 4.16677 4.16677 -147.593 -4.16677 0 0 612192. 2118.31 0.31 0.06 0.11 -1 -1 0.31 0.0170185 0.0151521 152 50 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 5.43 vpr 64.19 MiB -1 -1 0.27 21612 1 0.06 -1 -1 33908 -1 -1 24 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65728 30 32 363 293 1 196 86 17 17 289 -1 unnamed_device 25.3 MiB 0.41 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554710. 1919.41 1.14 0.0744293 0.0627948 22834 132086 -1 2143 21 1316 1863 128998 30148 3.48731 3.48731 -116.645 -3.48731 0 0 701300. 2426.64 0.30 0.05 0.13 -1 -1 0.30 0.0139163 0.0123224 126 29 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 5.42 vpr 63.67 MiB -1 -1 0.26 21548 1 0.04 -1 -1 33992 -1 -1 27 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65196 29 32 308 248 1 169 88 17 17 289 -1 unnamed_device 25.0 MiB 0.21 937 15298 4951 7764 2583 63.7 MiB 0.12 0.00 4.29337 -115.569 -4.29337 4.29337 1.03 0.00019685 0.000155796 0.020236 0.016536 -1 -1 -1 -1 32 2306 30 6.65987e+06 342306 554710. 1919.41 1.05 0.066181 0.0558676 22834 132086 -1 1985 25 1504 2799 219919 50220 3.42411 3.42411 -111.097 -3.42411 0 0 701300. 2426.64 0.42 0.07 0.13 -1 -1 0.42 0.0157669 0.0138077 126 31 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 5.57 vpr 63.96 MiB -1 -1 0.20 21524 1 0.05 -1 -1 33920 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65496 32 32 336 268 1 174 87 17 17 289 -1 unnamed_device 25.3 MiB 0.21 1058 13911 3755 8078 2078 64.0 MiB 0.13 0.00 4.32255 -126.417 -4.32255 4.32255 1.04 0.000210081 0.000166405 0.0204754 0.0167115 -1 -1 -1 -1 32 2541 47 6.65987e+06 291594 554710. 1919.41 1.40 0.0922247 0.0790323 22834 132086 -1 2322 23 1597 3125 272365 58938 3.64831 3.64831 -124.147 -3.64831 0 0 701300. 2426.64 0.35 0.09 0.13 -1 -1 0.35 0.0212871 0.018745 130 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 5.47 vpr 63.91 MiB -1 -1 0.31 21560 1 0.04 -1 -1 34076 -1 -1 33 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65444 32 32 366 295 1 189 97 17 17 289 -1 unnamed_device 25.0 MiB 0.33 858 7201 1481 5496 224 63.9 MiB 0.08 0.00 3.30984 -111.675 -3.30984 3.30984 1.06 0.000223118 0.000177228 0.0107146 0.0089289 -1 -1 -1 -1 28 2339 24 6.65987e+06 418374 500653. 1732.36 1.22 0.0591409 0.0501912 21970 115934 -1 2009 20 1311 2041 126370 33362 3.01731 3.01731 -111.009 -3.01731 0 0 612192. 2118.31 0.28 0.06 0.12 -1 -1 0.28 0.0174678 0.0151561 141 58 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 4.87 vpr 63.41 MiB -1 -1 0.21 21468 1 0.04 -1 -1 34072 -1 -1 18 27 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64932 27 32 259 221 1 130 77 17 17 289 -1 unnamed_device 24.8 MiB 0.16 601 11976 3191 7496 1289 63.4 MiB 0.09 0.00 3.61795 -96.0414 -3.61795 3.61795 1.09 0.000190844 0.000151325 0.0183522 0.0149355 -1 -1 -1 -1 28 1542 20 6.65987e+06 228204 500653. 1732.36 0.96 0.0564805 0.0476777 21970 115934 -1 1408 20 793 1327 101908 22870 2.80071 2.80071 -94.1372 -2.80071 0 0 612192. 2118.31 0.31 0.05 0.12 -1 -1 0.31 0.014874 0.0130699 94 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 5.12 vpr 63.51 MiB -1 -1 0.21 21384 1 0.04 -1 -1 33700 -1 -1 31 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65032 31 32 271 219 1 162 94 17 17 289 -1 unnamed_device 24.9 MiB 0.19 811 9892 2186 7284 422 63.5 MiB 0.07 0.00 3.36433 -96.8901 -3.36433 3.36433 0.94 0.000201284 0.000160345 0.0108992 0.00878783 -1 -1 -1 -1 28 2347 24 6.65987e+06 393018 500653. 1732.36 1.38 0.057181 0.0486882 21970 115934 -1 1905 19 1011 1801 131698 30370 2.71485 2.71485 -95.6397 -2.71485 0 0 612192. 2118.31 0.26 0.05 0.10 -1 -1 0.26 0.0128759 0.0113856 115 4 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 5.30 vpr 63.75 MiB -1 -1 0.35 21472 1 0.05 -1 -1 33836 -1 -1 19 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65276 31 32 317 271 1 169 82 17 17 289 -1 unnamed_device 24.9 MiB 0.29 927 8804 2219 5962 623 63.7 MiB 0.07 0.00 3.4209 -115.766 -3.4209 3.4209 1.00 0.000214778 0.000172015 0.0123141 0.0100703 -1 -1 -1 -1 30 1946 21 6.65987e+06 240882 526063. 1820.29 1.00 0.0534342 0.0450337 22546 126617 -1 1679 22 876 1290 75993 17565 2.91031 2.91031 -109.66 -2.91031 0 0 666494. 2306.21 0.36 0.05 0.18 -1 -1 0.36 0.0170021 0.0147864 112 64 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 4.97 vpr 63.37 MiB -1 -1 0.19 21528 1 0.04 -1 -1 33820 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64892 32 32 298 248 1 156 81 17 17 289 -1 unnamed_device 24.9 MiB 0.42 719 10056 2390 7132 534 63.4 MiB 0.08 0.00 3.74029 -120.95 -3.74029 3.74029 0.94 0.000201688 0.000160176 0.0136315 0.0110771 -1 -1 -1 -1 28 2074 23 6.65987e+06 215526 500653. 1732.36 1.08 0.0640771 0.0541029 21970 115934 -1 1782 18 1142 1764 119209 29314 2.82871 2.82871 -113.841 -2.82871 0 0 612192. 2118.31 0.33 0.07 0.11 -1 -1 0.33 0.0185251 0.0165222 113 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 5.28 vpr 63.60 MiB -1 -1 0.32 21348 1 0.03 -1 -1 34136 -1 -1 17 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65124 30 32 303 262 1 139 79 17 17 289 -1 unnamed_device 24.9 MiB 0.37 575 5994 1238 4012 744 63.6 MiB 0.05 0.00 4.00989 -106.137 -4.00989 4.00989 1.03 0.00023233 0.000188038 0.00914136 0.00751987 -1 -1 -1 -1 32 1593 22 6.65987e+06 215526 554710. 1919.41 0.99 0.0500588 0.0421829 22834 132086 -1 1313 15 696 1067 62289 16243 2.70271 2.70271 -97.1718 -2.70271 0 0 701300. 2426.64 0.34 0.04 0.14 -1 -1 0.34 0.0128956 0.0114825 98 63 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 5.60 vpr 63.57 MiB -1 -1 0.20 21680 1 0.05 -1 -1 33864 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65092 32 32 276 237 1 166 81 17 17 289 -1 unnamed_device 25.0 MiB 0.33 795 6381 1346 4871 164 63.6 MiB 0.06 0.00 3.75729 -117.97 -3.75729 3.75729 1.01 0.000187526 0.000147758 0.00908277 0.00752482 -1 -1 -1 -1 28 2308 31 6.65987e+06 215526 500653. 1732.36 1.45 0.0735359 0.064043 21970 115934 -1 1893 16 1083 1444 121416 28692 2.92331 2.92331 -107.84 -2.92331 0 0 612192. 2118.31 0.31 0.05 0.21 -1 -1 0.31 0.0120498 0.0107571 106 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 5.64 vpr 64.14 MiB -1 -1 0.21 21512 1 0.05 -1 -1 33976 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65680 32 32 344 272 1 202 88 17 17 289 -1 unnamed_device 25.2 MiB 0.50 1032 9253 2342 6405 506 64.1 MiB 0.09 0.00 4.35378 -139.852 -4.35378 4.35378 0.98 0.000223018 0.000177097 0.0139518 0.0115179 -1 -1 -1 -1 32 2591 17 6.65987e+06 304272 554710. 1919.41 1.18 0.0658643 0.0565817 22834 132086 -1 2306 24 1781 2644 208357 48038 3.49111 3.49111 -130.916 -3.49111 0 0 701300. 2426.64 0.43 0.08 0.15 -1 -1 0.43 0.0206307 0.0181532 139 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 5.19 vpr 64.05 MiB -1 -1 0.21 21536 1 0.04 -1 -1 34092 -1 -1 30 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65588 32 32 363 295 1 181 94 17 17 289 -1 unnamed_device 25.2 MiB 0.28 904 11170 2626 8078 466 64.1 MiB 0.09 0.00 4.4708 -131.273 -4.4708 4.4708 1.04 0.000219459 0.000173615 0.014438 0.0117766 -1 -1 -1 -1 28 2436 21 6.65987e+06 380340 500653. 1732.36 1.11 0.0637349 0.0540783 21970 115934 -1 2247 23 1751 2879 209966 48329 3.76071 3.76071 -132.119 -3.76071 0 0 612192. 2118.31 0.28 0.08 0.12 -1 -1 0.28 0.019816 0.0175394 133 61 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 5.40 vpr 63.37 MiB -1 -1 0.27 21100 1 0.03 -1 -1 33528 -1 -1 21 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64888 29 32 248 215 1 137 82 17 17 289 -1 unnamed_device 24.8 MiB 0.37 775 11118 2644 7385 1089 63.4 MiB 0.07 0.00 3.16393 -91.7211 -3.16393 3.16393 1.00 0.000181808 0.000145431 0.012512 0.0101952 -1 -1 -1 -1 26 1874 19 6.65987e+06 266238 477104. 1650.88 1.04 0.0572575 0.0491675 21682 110474 -1 1569 19 924 1516 104371 25434 2.84691 2.84691 -93.5767 -2.84691 0 0 585099. 2024.56 0.29 0.05 0.11 -1 -1 0.29 0.0145335 0.012816 98 27 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 5.78 vpr 63.87 MiB -1 -1 0.24 21272 1 0.04 -1 -1 34148 -1 -1 21 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65404 32 32 370 297 1 183 85 17 17 289 -1 unnamed_device 25.1 MiB 0.59 1049 12733 3859 6982 1892 63.9 MiB 0.11 0.00 4.04739 -126.772 -4.04739 4.04739 1.05 0.000236508 0.000188286 0.0200991 0.0164663 -1 -1 -1 -1 32 2511 22 6.65987e+06 266238 554710. 1919.41 1.43 0.0852414 0.0732998 22834 132086 -1 2238 23 1445 2718 191051 43605 3.35377 3.35377 -121.168 -3.35377 0 0 701300. 2426.64 0.33 0.07 0.13 -1 -1 0.33 0.0198299 0.0174322 132 58 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 5.50 vpr 63.91 MiB -1 -1 0.21 21504 1 0.04 -1 -1 33684 -1 -1 21 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65448 32 32 338 269 1 196 85 17 17 289 -1 unnamed_device 25.1 MiB 0.40 1072 15523 5016 8339 2168 63.9 MiB 0.12 0.00 4.31458 -139.763 -4.31458 4.31458 0.91 0.000213337 0.000169806 0.0220797 0.01809 -1 -1 -1 -1 28 2915 21 6.65987e+06 266238 500653. 1732.36 1.25 0.0794588 0.0684275 21970 115934 -1 2316 19 1401 1989 160493 35788 3.26677 3.26677 -127.853 -3.26677 0 0 612192. 2118.31 0.33 0.07 0.15 -1 -1 0.33 0.0193526 0.0173998 137 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 5.20 vpr 63.85 MiB -1 -1 0.22 21428 1 0.04 -1 -1 33612 -1 -1 29 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65380 32 32 323 276 1 153 93 17 17 289 -1 unnamed_device 25.0 MiB 0.28 861 11433 2956 7633 844 63.8 MiB 0.08 0.00 2.85064 -102.994 -2.85064 2.85064 0.93 0.000233087 0.000188016 0.0140473 0.0114104 -1 -1 -1 -1 26 2153 22 6.65987e+06 367662 477104. 1650.88 1.11 0.0647541 0.0554807 21682 110474 -1 1816 19 977 1497 110865 25449 2.14751 2.14751 -97.7734 -2.14751 0 0 585099. 2024.56 0.32 0.05 0.13 -1 -1 0.32 0.0170404 0.0151823 110 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 4.52 vpr 63.00 MiB -1 -1 0.19 21216 1 0.04 -1 -1 33620 -1 -1 15 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64512 30 32 222 206 1 117 77 17 17 289 -1 unnamed_device 24.4 MiB 0.11 640 7086 1644 4840 602 63.0 MiB 0.04 0.00 2.24807 -77.7472 -2.24807 2.24807 0.90 0.000146079 0.000114661 0.00814634 0.0066777 -1 -1 -1 -1 32 1491 20 6.65987e+06 190170 554710. 1919.41 0.90 0.0334735 0.0280832 22834 132086 -1 1296 14 579 811 59607 14185 1.89185 1.89185 -79.7993 -1.89185 0 0 701300. 2426.64 0.38 0.05 0.14 -1 -1 0.38 0.0137347 0.0123977 81 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 5.64 vpr 63.55 MiB -1 -1 0.19 21416 1 0.04 -1 -1 33956 -1 -1 19 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65080 31 32 291 243 1 171 82 17 17 289 -1 unnamed_device 25.0 MiB 0.74 819 13254 3680 8313 1261 63.6 MiB 0.09 0.00 4.81074 -140.485 -4.81074 4.81074 0.98 0.000182772 0.000143938 0.0156644 0.0126589 -1 -1 -1 -1 28 2127 22 6.65987e+06 240882 500653. 1732.36 0.98 0.0553489 0.0466088 21970 115934 -1 1797 18 1099 1584 108008 26189 3.47917 3.47917 -126.534 -3.47917 0 0 612192. 2118.31 0.41 0.06 0.14 -1 -1 0.41 0.0166378 0.0149701 127 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 5.75 vpr 63.93 MiB -1 -1 0.19 21608 1 0.04 -1 -1 33928 -1 -1 31 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65468 32 32 342 271 1 179 95 17 17 289 -1 unnamed_device 25.1 MiB 0.32 945 6791 1317 5158 316 63.9 MiB 0.07 0.00 4.14893 -130.493 -4.14893 4.14893 1.03 0.000229934 0.000183929 0.0102179 0.00839391 -1 -1 -1 -1 30 2169 21 6.65987e+06 393018 526063. 1820.29 0.99 0.0537387 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65056 32 32 285 227 1 165 85 17 17 289 -1 unnamed_device 25.0 MiB 0.26 1008 10873 2978 7123 772 63.5 MiB 0.08 0.00 4.661 -123.259 -4.661 4.661 1.08 0.000200696 0.000161014 0.0134188 0.0110138 -1 -1 -1 -1 28 2311 31 6.65987e+06 266238 500653. 1732.36 1.01 0.0547584 0.0463224 21970 115934 -1 2059 21 1264 2355 164435 38396 3.79397 3.79397 -121.606 -3.79397 0 0 612192. 2118.31 0.27 0.05 0.11 -1 -1 0.27 0.0142969 0.0126592 118 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 4.86 vpr 62.88 MiB -1 -1 0.17 21108 1 0.04 -1 -1 33504 -1 -1 14 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64384 32 32 173 169 1 116 78 17 17 289 -1 unnamed_device 24.4 MiB 0.10 415 10370 2863 4808 2699 62.9 MiB 0.05 0.00 2.54569 -72.1104 -2.54569 2.54569 1.01 0.000130829 0.000101365 0.0105454 0.00855625 -1 -1 -1 -1 30 1192 29 6.65987e+06 177492 526063. 1820.29 0.97 0.0395417 0.0332815 22546 126617 -1 819 15 404 445 27960 7884 1.81985 1.81985 -66.7912 -1.81985 0 0 666494. 2306.21 0.30 0.03 0.12 -1 -1 0.30 0.00871213 0.00788207 79 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 5.21 vpr 63.51 MiB -1 -1 0.19 21476 1 0.03 -1 -1 33812 -1 -1 30 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65036 32 32 300 245 1 165 94 17 17 289 -1 unnamed_device 24.9 MiB 0.18 867 9679 2178 7022 479 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0.0486652 22546 126617 -1 1950 19 961 1748 104695 23724 2.60951 2.60951 -101.656 -2.60951 0 0 666494. 2306.21 0.30 0.05 0.14 -1 -1 0.30 0.0144722 0.0127854 128 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 5.09 vpr 63.92 MiB -1 -1 0.21 21484 1 0.03 -1 -1 33864 -1 -1 26 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65456 32 32 338 277 1 179 90 17 17 289 -1 unnamed_device 24.8 MiB 0.29 1026 15366 4954 8031 2381 63.9 MiB 0.14 0.00 4.40163 -128.768 -4.40163 4.40163 1.03 0.000263784 0.000190982 0.0218191 0.017596 -1 -1 -1 -1 28 2536 22 6.65987e+06 329628 500653. 1732.36 1.17 0.0701533 0.0586005 21970 115934 -1 2239 29 1748 3059 300303 101990 3.99999 3.99999 -130.531 -3.99999 0 0 612192. 2118.31 0.28 0.10 0.12 -1 -1 0.28 0.0213118 0.0184515 125 50 -1 -1 -1 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64932 30 32 262 227 1 135 85 17 17 289 -1 unnamed_device 24.7 MiB 0.14 765 12733 3276 8152 1305 63.4 MiB 0.07 0.00 2.99867 -95.3722 -2.99867 2.99867 1.04 0.00016599 0.00013095 0.013425 0.0108516 -1 -1 -1 -1 32 1733 17 6.65987e+06 291594 554710. 1919.41 1.01 0.045989 0.0387781 22834 132086 -1 1567 19 957 1467 111882 25763 2.66145 2.66145 -94.3977 -2.66145 0 0 701300. 2426.64 0.30 0.05 0.14 -1 -1 0.30 0.0130256 0.0115622 97 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 4.70 vpr 63.15 MiB -1 -1 0.22 21624 1 0.04 -1 -1 33856 -1 -1 23 28 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64668 28 32 260 223 1 140 83 17 17 289 -1 unnamed_device 24.5 MiB 0.15 635 14123 3811 8579 1733 63.2 MiB 0.09 0.00 3.31478 -92.4847 -3.31478 3.31478 0.99 0.00018014 0.000143849 0.0166834 0.0135061 -1 -1 -1 -1 28 1810 27 6.65987e+06 291594 500653. 1732.36 0.92 0.0506914 0.0419816 21970 115934 -1 1551 19 950 1652 120534 27810 2.73271 2.73271 -92.4594 -2.73271 0 0 612192. 2118.31 0.31 0.07 0.11 -1 -1 0.31 0.0181138 0.0159989 98 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_032.v common 4.86 vpr 63.42 MiB -1 -1 0.30 21160 1 0.04 -1 -1 33892 -1 -1 19 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64940 32 32 253 210 1 154 83 17 17 289 -1 unnamed_device 24.7 MiB 0.17 727 6383 1361 4583 439 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65392 32 32 391 311 1 192 100 17 17 289 -1 unnamed_device 25.0 MiB 0.34 918 16804 4626 9521 2657 63.9 MiB 0.14 0.00 3.76954 -123.355 -3.76954 3.76954 1.19 0.000353965 0.000284297 0.0242504 0.0197085 -1 -1 -1 -1 26 2803 43 6.65987e+06 456408 477104. 1650.88 1.57 0.103704 0.0874397 21682 110474 -1 2202 22 1787 2772 200753 48070 3.09111 3.09111 -121.86 -3.09111 0 0 585099. 2024.56 0.32 0.07 0.12 -1 -1 0.32 0.0184838 0.0162755 146 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 5.42 vpr 62.53 MiB -1 -1 0.20 21396 1 0.04 -1 -1 33556 -1 -1 17 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64032 31 32 279 237 1 161 80 17 17 289 -1 unnamed_device 24.1 MiB 0.63 795 7304 1575 5379 350 62.5 MiB 0.06 0.00 4.09732 -119.878 -4.09732 4.09732 1.02 0.000176779 0.000139104 0.00970252 0.00795085 -1 -1 -1 -1 28 2295 28 6.65987e+06 215526 500653. 1732.36 1.18 0.050986 0.0435131 21970 115934 -1 1888 21 1171 1638 142248 31897 2.88337 2.88337 -109.949 -2.88337 0 0 612192. 2118.31 0.26 0.05 0.11 -1 -1 0.26 0.0131063 0.0115533 109 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 5.20 vpr 63.11 MiB -1 -1 0.22 21396 1 0.04 -1 -1 33880 -1 -1 24 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64624 31 32 370 297 1 186 87 17 17 289 -1 unnamed_device 24.2 MiB 0.42 944 8727 2152 5844 731 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65252 32 32 291 242 1 179 86 17 17 289 -1 unnamed_device 25.1 MiB 0.29 922 8780 2172 6205 403 63.7 MiB 0.07 0.00 4.1266 -111.615 -4.1266 4.1266 1.05 0.000186119 0.000147103 0.0106879 0.0087129 -1 -1 -1 -1 26 2735 26 6.65987e+06 278916 477104. 1650.88 1.78 0.0605723 0.0514452 21682 110474 -1 2172 23 1525 2279 180283 42061 3.61865 3.61865 -116.354 -3.61865 0 0 585099. 2024.56 0.29 0.08 0.11 -1 -1 0.29 0.0218666 0.0195236 118 27 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 5.94 vpr 64.18 MiB -1 -1 0.25 21800 1 0.06 -1 -1 34148 -1 -1 38 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65720 32 32 457 356 1 223 102 17 17 289 -1 unnamed_device 25.8 MiB 0.46 1225 11764 2792 7889 1083 64.2 MiB 0.11 0.00 4.86514 -158.575 -4.86514 4.86514 1.22 0.000285867 0.000229446 0.0163593 0.0133778 -1 -1 -1 -1 28 3027 30 6.65987e+06 481764 500653. 1732.36 1.36 0.0918822 0.078505 21970 115934 -1 2643 23 1724 2712 187683 42451 3.79291 3.79291 -146.352 -3.79291 0 0 612192. 2118.31 0.29 0.08 0.12 -1 -1 0.29 0.0240298 0.0213049 172 87 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 4.83 vpr 63.30 MiB -1 -1 0.30 21576 1 0.03 -1 -1 33508 -1 -1 21 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64816 31 32 261 225 1 142 84 17 17 289 -1 unnamed_device 24.7 MiB 0.27 792 5391 1113 3866 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65524 32 32 353 287 1 198 86 17 17 289 -1 unnamed_device 25.1 MiB 0.45 1090 7835 1660 5643 532 64.0 MiB 0.08 0.00 4.46734 -132.214 -4.46734 4.46734 1.02 0.000205159 0.000162705 0.0134293 0.0109819 -1 -1 -1 -1 32 2503 28 6.65987e+06 278916 554710. 1919.41 1.03 0.0651839 0.0554538 22834 132086 -1 2254 16 1127 1532 112414 26836 3.20591 3.20591 -119.029 -3.20591 0 0 701300. 2426.64 0.32 0.05 0.18 -1 -1 0.32 0.0148755 0.0131789 136 55 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 6.32 vpr 63.97 MiB -1 -1 0.22 21632 1 0.04 -1 -1 33812 -1 -1 31 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65504 32 32 361 291 1 185 95 17 17 289 -1 unnamed_device 25.1 MiB 0.63 1025 8951 2023 6429 499 64.0 MiB 0.08 0.00 3.78594 -122.94 -3.78594 3.78594 1.09 0.000231515 0.000185545 0.0124475 0.010335 -1 -1 -1 -1 26 2851 30 6.65987e+06 393018 477104. 1650.88 1.84 0.0906537 0.077767 21682 110474 -1 2246 22 1338 2263 183303 40174 3.11131 3.11131 -122.127 -3.11131 0 0 585099. 2024.56 0.26 0.06 0.11 -1 -1 0.26 0.0167684 0.014701 132 55 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 5.55 vpr 64.07 MiB -1 -1 0.37 21548 1 0.06 -1 -1 33916 -1 -1 36 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65604 32 32 382 305 1 192 100 17 17 289 -1 unnamed_device 25.2 MiB 0.49 1095 17268 5091 9567 2610 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65568 32 32 387 315 1 189 85 17 17 289 -1 unnamed_device 25.2 MiB 0.35 901 8269 1876 5929 464 64.0 MiB 0.08 0.00 3.98149 -123.442 -3.98149 3.98149 0.95 0.000220892 0.000174602 0.0127458 0.0104703 -1 -1 -1 -1 32 2648 25 6.65987e+06 266238 554710. 1919.41 1.09 0.065438 0.0555498 22834 132086 -1 2151 21 1523 2669 176931 42791 3.46425 3.46425 -121.172 -3.46425 0 0 701300. 2426.64 0.32 0.06 0.14 -1 -1 0.32 0.0182481 0.0160657 135 77 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 4.96 vpr 63.25 MiB -1 -1 0.19 21124 1 0.04 -1 -1 33752 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65500 29 32 355 287 1 198 85 17 17 289 -1 unnamed_device 25.1 MiB 0.38 1014 15523 4859 8256 2408 64.0 MiB 0.12 0.00 4.24664 -124.159 -4.24664 4.24664 1.19 0.000216157 0.000172503 0.0207212 0.0168393 -1 -1 -1 -1 32 2519 21 6.65987e+06 304272 554710. 1919.41 0.96 0.0610155 0.051077 22834 132086 -1 2110 26 1456 2226 166870 38789 3.18497 3.18497 -112.254 -3.18497 0 0 701300. 2426.64 0.46 0.11 0.13 -1 -1 0.46 0.0333136 0.0293483 138 62 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 5.90 vpr 63.97 MiB -1 -1 0.21 21492 1 0.04 -1 -1 33852 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65504 32 32 358 289 1 175 88 17 17 289 -1 unnamed_device 25.2 MiB 0.30 813 6133 1250 4669 214 64.0 MiB 0.06 0.00 4.31499 -129.627 -4.31499 4.31499 1.23 0.000269975 0.000223102 0.0112372 0.00940652 -1 -1 -1 -1 30 1973 21 6.65987e+06 304272 526063. 1820.29 1.33 0.0794649 0.0682408 22546 126617 -1 1695 21 1155 1730 101267 23759 3.45917 3.45917 -120.941 -3.45917 0 0 666494. 2306.21 0.30 0.04 0.12 -1 -1 0.30 0.0154706 0.0136382 130 54 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 5.96 vpr 63.91 MiB -1 -1 0.20 21496 1 0.03 -1 -1 34036 -1 -1 27 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65440 32 32 353 285 1 181 91 17 17 289 -1 unnamed_device 25.1 MiB 0.33 1032 14575 3712 8961 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64932 28 32 277 229 1 155 95 17 17 289 -1 unnamed_device 24.9 MiB 0.25 923 12623 3487 7239 1897 63.4 MiB 0.14 0.00 4.05815 -100.085 -4.05815 4.05815 1.17 0.000282317 0.000225409 0.0206415 0.0168795 -1 -1 -1 -1 26 2151 41 6.65987e+06 443730 477104. 1650.88 1.29 0.0900948 0.0773508 21682 110474 -1 1846 35 1346 2687 324830 124278 3.61745 3.61745 -101.557 -3.61745 0 0 585099. 2024.56 0.25 0.16 0.14 -1 -1 0.25 0.0285601 0.0246591 115 27 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 5.76 vpr 63.70 MiB -1 -1 0.22 21504 1 0.04 -1 -1 34148 -1 -1 17 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65588 32 32 387 309 1 190 101 17 17 289 -1 unnamed_device 25.1 MiB 0.35 1091 6681 1303 5078 300 64.1 MiB 0.07 0.00 4.26912 -136.659 -4.26912 4.26912 1.04 0.000233561 0.000185446 0.00919908 0.00760708 -1 -1 -1 -1 28 2817 25 6.65987e+06 469086 500653. 1732.36 1.51 0.0738565 0.0639349 21970 115934 -1 2390 24 1458 2683 207005 46217 3.57931 3.57931 -129.096 -3.57931 0 0 612192. 2118.31 0.37 0.10 0.13 -1 -1 0.37 0.0306445 0.0276156 140 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 5.28 vpr 63.36 MiB -1 -1 0.21 21540 1 0.05 -1 -1 33636 -1 -1 19 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65696 32 32 365 294 1 185 84 17 17 289 -1 unnamed_device 25.4 MiB 0.31 1063 15273 4695 8692 1886 64.2 MiB 0.13 0.00 4.80469 -139.024 -4.80469 4.80469 1.04 0.000241712 0.000191897 0.0245582 0.0201745 -1 -1 -1 -1 32 2629 23 6.65987e+06 253560 554710. 1919.41 1.07 0.0781199 0.0653028 22834 132086 -1 2268 18 1507 2677 195261 43968 3.62631 3.62631 -130.943 -3.62631 0 0 701300. 2426.64 0.31 0.08 0.13 -1 -1 0.31 0.0215693 0.0191503 133 57 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 5.77 vpr 64.05 MiB -1 -1 0.22 21480 1 0.04 -1 -1 33976 -1 -1 29 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65592 29 32 378 310 1 177 90 17 17 289 -1 unnamed_device 25.2 MiB 0.43 958 9738 2610 6016 1112 64.1 MiB 0.09 0.00 4.45269 -125.734 -4.45269 4.45269 1.03 0.00030591 0.000251282 0.0162077 0.013419 -1 -1 -1 -1 32 2235 18 6.65987e+06 367662 554710. 1919.41 1.00 0.0615563 0.0516706 22834 132086 -1 1952 21 1256 2061 148316 34812 3.04431 3.04431 -110.646 -3.04431 0 0 701300. 2426.64 0.35 0.05 0.14 -1 -1 0.35 0.0163134 0.0143483 131 85 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 4.55 vpr 63.14 MiB -1 -1 0.17 21216 1 0.04 -1 -1 34124 -1 -1 15 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64656 32 32 243 205 1 139 79 17 17 289 -1 unnamed_device 24.7 MiB 0.18 690 12416 3929 6813 1674 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64780 31 32 245 205 1 150 84 17 17 289 -1 unnamed_device 24.6 MiB 0.16 780 8136 2089 5541 506 63.3 MiB 0.06 0.00 3.80235 -109.245 -3.80235 3.80235 1.02 0.000168167 0.000133684 0.0106798 0.00881916 -1 -1 -1 -1 26 2013 29 6.65987e+06 266238 477104. 1650.88 1.03 0.0468666 0.0398 21682 110474 -1 1810 21 1146 1877 153537 34871 3.03417 3.03417 -108.934 -3.03417 0 0 585099. 2024.56 0.33 0.07 0.18 -1 -1 0.33 0.0175115 0.0155868 106 4 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 5.34 vpr 64.10 MiB -1 -1 0.19 21588 1 0.05 -1 -1 34080 -1 -1 25 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65644 32 32 421 327 1 232 90 17 17 289 -1 unnamed_device 25.8 MiB 0.49 1325 16572 5545 8395 2632 64.1 MiB 0.18 0.00 4.13297 -134.503 -4.13297 4.13297 1.11 0.000357775 0.000294214 0.0364056 0.0306597 -1 -1 -1 -1 28 3732 33 6.65987e+06 329628 500653. 1732.36 1.82 0.10995 0.093406 21970 115934 -1 2910 22 2032 3461 269192 58352 3.78985 3.78985 -132.845 -3.78985 0 0 612192. 2118.31 0.27 0.09 0.13 -1 -1 0.27 0.0233614 0.0209297 170 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 6.05 vpr 64.05 MiB -1 -1 0.32 21756 1 0.04 -1 -1 34088 -1 -1 21 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65588 31 32 365 296 1 193 84 17 17 289 -1 unnamed_device 25.2 MiB 1.20 1078 12528 3903 6326 2299 64.1 MiB 0.10 0.00 5.17417 -148.706 -5.17417 5.17417 0.91 0.000224964 0.000178374 0.0185415 0.0150606 -1 -1 -1 -1 32 2682 40 6.65987e+06 266238 554710. 1919.41 1.14 0.0709059 0.0594337 22834 132086 -1 2210 21 1701 2586 216602 47829 4.53217 4.53217 -149.34 -4.53217 0 0 701300. 2426.64 0.32 0.08 0.14 -1 -1 0.32 0.0204275 0.0182516 150 64 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 6.17 vpr 63.77 MiB -1 -1 0.20 21532 1 0.04 -1 -1 33784 -1 -1 19 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65296 32 32 331 280 1 175 83 17 17 289 -1 unnamed_device 24.9 MiB 1.22 898 12323 4450 5685 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65624 32 32 350 275 1 214 88 17 17 289 -1 unnamed_device 25.4 MiB 0.34 1081 14713 4410 8000 2303 64.1 MiB 0.12 0.00 4.85897 -149.763 -4.85897 4.85897 1.12 0.000225065 0.000169391 0.0201529 0.0163419 -1 -1 -1 -1 32 3051 39 6.65987e+06 304272 554710. 1919.41 1.44 0.102627 0.0878269 22834 132086 -1 2442 22 1985 3010 225131 52194 4.07205 4.07205 -141.281 -4.07205 0 0 701300. 2426.64 0.30 0.07 0.13 -1 -1 0.30 0.0177122 0.0156745 147 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 5.61 vpr 63.86 MiB -1 -1 0.29 21768 1 0.05 -1 -1 33724 -1 -1 34 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65388 32 32 386 307 1 195 98 17 17 289 -1 unnamed_device 25.0 MiB 0.51 1057 18773 5404 10789 2580 63.9 MiB 0.15 0.00 4.57498 -141.429 -4.57498 4.57498 1.03 0.000226159 0.000177933 0.0231806 0.0188536 -1 -1 -1 -1 26 2887 23 6.65987e+06 431052 477104. 1650.88 1.21 0.0784627 0.0667168 21682 110474 -1 2397 18 1290 2019 146660 33279 3.71257 3.71257 -132.431 -3.71257 0 0 585099. 2024.56 0.29 0.05 0.11 -1 -1 0.29 0.0157803 0.0140274 143 62 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 4.95 vpr 63.14 MiB -1 -1 0.19 21484 1 0.04 -1 -1 34080 -1 -1 17 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64656 29 32 269 229 1 130 78 17 17 289 -1 unnamed_device 24.5 MiB 0.21 522 12528 3273 8240 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64744 32 32 278 238 1 149 80 17 17 289 -1 unnamed_device 24.6 MiB 0.24 840 12980 3474 8543 963 63.2 MiB 0.08 0.00 3.73708 -117.005 -3.73708 3.73708 0.97 0.000183186 0.000144283 0.015428 0.0124593 -1 -1 -1 -1 32 2020 18 6.65987e+06 202848 554710. 1919.41 0.99 0.0467346 0.039004 22834 132086 -1 1831 23 1462 2541 202733 45407 2.67845 2.67845 -105.711 -2.67845 0 0 701300. 2426.64 0.29 0.07 0.13 -1 -1 0.29 0.0149316 0.0131229 109 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 5.12 vpr 63.92 MiB -1 -1 0.27 21696 1 0.06 -1 -1 34000 -1 -1 35 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65456 31 32 373 300 1 181 98 17 17 289 -1 unnamed_device 25.1 MiB 0.33 932 18098 5272 9901 2925 63.9 MiB 0.13 0.00 4.00372 -119.439 -4.00372 4.00372 0.94 0.000219055 0.000172289 0.0205669 0.0163462 -1 -1 -1 -1 32 2122 19 6.65987e+06 443730 554710. 1919.41 1.07 0.0637094 0.0524413 22834 132086 -1 1876 20 1378 2071 131991 31106 2.96231 2.96231 -109.45 -2.96231 0 0 701300. 2426.64 0.32 0.05 0.13 -1 -1 0.32 0.016983 0.0148614 135 64 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 4.72 vpr 63.38 MiB -1 -1 0.22 21532 1 0.03 -1 -1 33676 -1 -1 19 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64900 31 32 265 230 1 164 82 17 17 289 -1 unnamed_device 24.8 MiB 0.30 729 5422 1011 4209 202 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65004 32 32 290 244 1 175 83 17 17 289 -1 unnamed_device 24.8 MiB 0.25 794 6203 1260 4522 421 63.5 MiB 0.06 0.00 4.22769 -129.19 -4.22769 4.22769 0.92 0.000192981 0.000153689 0.00893566 0.00737135 -1 -1 -1 -1 28 2478 30 6.65987e+06 240882 500653. 1732.36 1.24 0.0567572 0.0485113 21970 115934 -1 2072 18 1317 1923 149105 37380 3.16031 3.16031 -121.312 -3.16031 0 0 612192. 2118.31 0.39 0.11 0.12 -1 -1 0.39 0.0301283 0.0271604 115 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 4.92 vpr 63.86 MiB -1 -1 0.21 21492 1 0.04 -1 -1 33976 -1 -1 22 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65392 32 32 318 257 1 194 86 17 17 289 -1 unnamed_device 24.8 MiB 0.29 982 13505 4715 6575 2215 63.9 MiB 0.10 0.00 4.5425 -135.474 -4.5425 4.5425 0.90 0.000197258 0.000155465 0.0170356 0.0137727 -1 -1 -1 -1 32 2569 24 6.65987e+06 278916 554710. 1919.41 1.01 0.0549614 0.0459936 22834 132086 -1 2078 23 1533 2145 153331 36456 3.62971 3.62971 -124.599 -3.62971 0 0 701300. 2426.64 0.31 0.06 0.13 -1 -1 0.31 0.0183407 0.0162854 130 30 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 5.39 vpr 63.73 MiB -1 -1 0.27 21476 1 0.04 -1 -1 33900 -1 -1 28 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65264 29 32 324 268 1 168 89 17 17 289 -1 unnamed_device 24.8 MiB 0.58 892 10583 2559 7230 794 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65444 32 32 376 318 1 156 80 17 17 289 -1 unnamed_device 25.0 MiB 0.29 838 12464 4352 6338 1774 63.9 MiB 0.10 0.00 3.54047 -123.895 -3.54047 3.54047 1.06 0.000225521 0.000178436 0.0214698 0.0175208 -1 -1 -1 -1 30 1878 23 6.65987e+06 202848 526063. 1820.29 1.03 0.0666966 0.0558 22546 126617 -1 1542 22 1226 1790 98805 26832 2.87877 2.87877 -118.928 -2.87877 0 0 666494. 2306.21 0.28 0.05 0.12 -1 -1 0.28 0.0151246 0.013228 115 96 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 7.34 vpr 63.93 MiB -1 -1 0.24 21640 1 0.06 -1 -1 34008 -1 -1 31 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65464 32 32 360 293 1 179 95 17 17 289 -1 unnamed_device 25.1 MiB 0.47 983 16079 4676 8844 2559 63.9 MiB 0.24 0.00 4.19332 -128.664 -4.19332 4.19332 1.63 0.000605014 0.000519415 0.0551051 0.047835 -1 -1 -1 -1 32 2255 22 6.65987e+06 393018 554710. 1919.41 1.58 0.123022 0.106452 22834 132086 -1 1913 18 945 1398 91740 22097 3.08831 3.08831 -113.899 -3.08831 0 0 701300. 2426.64 0.30 0.04 0.14 -1 -1 0.30 0.0144483 0.0127817 130 60 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 7.26 vpr 63.84 MiB -1 -1 0.20 21860 1 0.04 -1 -1 34160 -1 -1 25 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65368 32 32 396 299 1 236 89 17 17 289 -1 unnamed_device 25.3 MiB 0.53 1359 11969 3395 7471 1103 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64772 25 32 216 194 1 122 84 17 17 289 -1 unnamed_device 24.8 MiB 0.13 451 9966 3308 4450 2208 63.3 MiB 0.05 0.00 3.08755 -72.8894 -3.08755 3.08755 1.13 0.000148394 0.000117353 0.0106207 0.0086907 -1 -1 -1 -1 30 1266 42 6.65987e+06 342306 526063. 1820.29 1.21 0.0578386 0.0493399 22546 126617 -1 972 64 992 2005 378014 232494 3.12459 3.12459 -67.2426 -3.12459 0 0 666494. 2306.21 0.34 0.15 0.13 -1 -1 0.34 0.024016 0.0204472 89 29 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 5.78 vpr 63.94 MiB -1 -1 0.22 21484 1 0.04 -1 -1 33800 -1 -1 20 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om 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9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66132 32 32 361 291 1 178 81 17 17 289 -1 unnamed_device 25.8 MiB 2.21 705 10581 4329 5826 426 64.6 MiB 0.07 0.00 3.235 -113.751 -3.235 3.235 1.07 0.000216793 0.000171308 0.0160907 0.0131381 -1 -1 -1 -1 46 2538 36 6.95648e+06 246087 828058. 2865.25 4.67 0.124548 0.10578 28066 200906 -1 1762 22 1596 2486 209871 53513 3.04467 3.04467 -116.161 -3.04467 0 0 1.01997e+06 3529.29 0.39 0.07 0.19 -1 -1 0.39 0.0178396 0.0158144 75 55 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_050.v common 17.69 vpr 64.84 MiB -1 -1 0.25 21476 1 0.03 -1 -1 33904 -1 -1 26 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66392 32 32 382 305 1 184 90 17 17 289 -1 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9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66108 32 32 387 315 1 183 77 17 17 289 -1 unnamed_device 25.9 MiB 1.70 875 12791 5461 6994 336 64.6 MiB 0.08 0.00 4.05245 -131.841 -4.05245 4.05245 0.92 0.000217618 0.000171367 0.0210095 0.0169789 -1 -1 -1 -1 40 2776 26 6.95648e+06 188184 706193. 2443.58 18.76 0.221147 0.187227 26914 176310 -1 2529 21 1721 2851 323085 71230 4.21512 4.21512 -142.266 -4.21512 0 0 926341. 3205.33 0.36 0.09 0.17 -1 -1 0.36 0.0194288 0.0173179 76 77 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_055.v common 12.67 vpr 63.85 MiB -1 -1 0.18 21260 1 0.04 -1 -1 33728 -1 -1 18 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65384 32 32 251 219 1 136 82 17 17 289 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on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65996 32 32 269 231 1 166 75 17 17 289 -1 unnamed_device 25.6 MiB 2.48 634 12083 4617 6209 1257 64.4 MiB 0.07 0.00 4.05037 -119.139 -4.05037 4.05037 0.96 0.000176467 0.00013924 0.0158701 0.0128694 -1 -1 -1 -1 40 2183 25 6.95648e+06 159232 706193. 2443.58 10.91 0.141175 0.119154 26914 176310 -1 1650 19 1252 1581 138724 32508 3.42592 3.42592 -119.97 -3.42592 0 0 926341. 3205.33 0.38 0.05 0.18 -1 -1 0.38 0.0131789 0.0117197 68 29 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_090.v common 7.33 vpr 64.03 MiB -1 -1 0.20 21200 1 0.04 -1 -1 34100 -1 -1 14 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65568 31 32 245 205 1 145 77 17 17 289 -1 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Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66264 31 32 373 300 1 174 87 17 17 289 -1 unnamed_device 25.9 MiB 1.28 760 14295 5473 6487 2335 64.7 MiB 0.09 0.00 3.48773 -117.233 -3.48773 3.48773 0.99 0.000248787 0.000200985 0.0201411 0.0162263 -1 -1 -1 -1 38 2353 27 6.95648e+06 347416 678818. 2348.85 2.59 0.0987226 0.0821954 26626 170182 -1 1741 20 1636 2188 161214 36056 3.39887 3.39887 -120.309 -3.39887 0 0 902133. 3121.57 0.40 0.07 0.16 -1 -1 0.40 0.0211996 0.0189943 79 64 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_110.v common 9.89 vpr 64.54 MiB -1 -1 0.23 21448 1 0.04 -1 -1 33604 -1 -1 12 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66084 31 32 265 230 1 159 75 17 17 289 -1 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GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65756 30 32 286 239 1 137 73 17 17 289 -1 unnamed_device 25.7 MiB 2.72 541 7673 3127 4256 290 64.2 MiB 0.04 0.00 3.61654 -109.463 -3.61654 3.61654 0.99 0.000176144 0.000138463 0.01098 0.00894104 -1 -1 -1 -1 36 1999 40 6.95648e+06 159232 648988. 2245.63 3.45 0.0792419 0.0661642 26050 158493 -1 1573 27 1433 2096 285043 86529 3.15927 3.15927 -115.804 -3.15927 0 0 828058. 2865.25 0.31 0.08 0.15 -1 -1 0.31 0.0147408 0.0128056 55 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_125.v common 8.40 vpr 64.14 MiB -1 -1 0.19 21568 1 0.04 -1 -1 33512 -1 -1 10 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65680 32 32 296 247 1 152 74 17 17 289 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9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66168 32 32 354 285 1 206 79 17 17 289 -1 unnamed_device 25.7 MiB 2.31 851 13599 5123 6301 2175 64.6 MiB 0.09 0.00 5.05471 -146.645 -5.05471 5.05471 1.03 0.000224334 0.000178624 0.0197154 0.0159003 -1 -1 -1 -1 40 2973 50 6.99608e+06 220735 706193. 2443.58 4.02 0.110297 0.0925107 26914 176310 -1 2391 21 1860 2633 243329 56741 4.97901 4.97901 -158.616 -4.97901 0 0 926341. 3205.33 0.36 0.07 0.17 -1 -1 0.36 0.0159987 0.0141671 88 50 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_002.v common 7.61 vpr 64.58 MiB -1 -1 0.22 21520 1 0.05 -1 -1 33684 -1 -1 18 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66128 30 32 363 293 1 224 80 17 17 289 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Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66032 32 32 370 297 1 222 80 17 17 289 -1 unnamed_device 25.8 MiB 2.25 1140 12464 4408 6591 1465 64.5 MiB 0.09 0.00 3.78769 -130.542 -3.78769 3.78769 0.93 0.000229561 0.000181976 0.019761 0.0160942 -1 -1 -1 -1 42 3336 48 6.99608e+06 235451 744469. 2576.02 2.77 0.106145 0.0888427 27202 183097 -1 2553 23 2137 3282 294346 60400 3.53451 3.53451 -137.204 -3.53451 0 0 949917. 3286.91 0.36 0.09 0.17 -1 -1 0.36 0.0205908 0.0182084 96 58 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_017.v common 8.80 vpr 64.45 MiB -1 -1 0.17 21604 1 0.04 -1 -1 33496 -1 -1 15 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65992 32 32 338 269 1 198 79 17 17 289 -1 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GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65984 32 32 341 285 1 214 79 17 17 289 -1 unnamed_device 25.5 MiB 1.04 872 9036 3191 4723 1122 64.4 MiB 0.06 0.00 3.89113 -140.293 -3.89113 3.89113 0.87 0.000201335 0.00015834 0.0146925 0.0122 -1 -1 -1 -1 44 3087 35 6.99608e+06 220735 787024. 2723.27 3.33 0.0883414 0.0739486 27778 195446 -1 2004 20 1867 2519 222462 45910 3.68341 3.68341 -137.359 -3.68341 0 0 997811. 3452.63 0.36 0.06 0.20 -1 -1 0.36 0.0131524 0.0115286 93 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_057.v common 8.74 vpr 65.02 MiB -1 -1 0.20 21804 1 0.04 -1 -1 34108 -1 -1 16 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 387 293 1 226 80 17 17 289 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Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66132 32 32 350 275 1 202 78 17 17 289 -1 unnamed_device 25.6 MiB 1.38 829 10204 4200 5555 449 64.6 MiB 0.06 0.00 4.50341 -148.643 -4.50341 4.50341 0.91 0.000205857 0.000161727 0.0150649 0.0122181 -1 -1 -1 -1 48 2835 33 6.99608e+06 206020 865456. 2994.66 19.69 0.169073 0.142889 28354 207349 -1 2230 20 1749 2578 220453 49752 4.10901 4.10901 -145.953 -4.10901 0 0 1.05005e+06 3633.38 0.50 0.06 0.19 -1 -1 0.50 0.0160984 0.0143082 86 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_077.v common 8.03 vpr 64.67 MiB -1 -1 0.21 21440 1 0.03 -1 -1 34032 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66224 32 32 385 308 1 237 81 17 17 289 -1 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Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 349 286 1 207 79 17 17 289 -1 unnamed_device 25.5 MiB 1.50 1045 14275 6069 7825 381 64.5 MiB 0.09 0.00 3.51899 -121.288 -3.51899 3.51899 0.88 0.000231565 0.000188562 0.0196182 0.0158497 -1 -1 -1 -1 38 2528 20 6.99608e+06 220735 678818. 2348.85 2.37 0.0847683 0.0709587 26626 170182 -1 2176 20 1461 1984 153571 32028 3.28376 3.28376 -123.98 -3.28376 0 0 902133. 3121.57 0.33 0.05 0.15 -1 -1 0.33 0.0141429 0.012478 91 57 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_112.v common 9.05 vpr 64.88 MiB -1 -1 0.22 21784 1 0.03 -1 -1 33892 -1 -1 20 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66440 31 32 396 325 1 254 83 17 17 289 -1 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65288 31 32 291 243 1 178 82 17 17 289 -1 unnamed_device 25.1 MiB 4.81 940 10406 3145 6506 755 63.8 MiB 0.08 0.00 5.00887 -149.776 -5.00887 5.00887 0.86 0.00017477 0.000138479 0.0117171 0.00940101 -1 -1 -1 -1 30 2234 22 6.87369e+06 265503 556674. 1926.21 0.89 0.0415066 0.0342714 25186 138497 -1 1813 18 871 1255 70103 17136 3.44261 3.44261 -132.101 -3.44261 0 0 706193. 2443.58 0.27 0.03 0.12 -1 -1 0.27 0.01055 0.00924348 116 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_021.v common 5.59 vpr 64.50 MiB -1 -1 0.17 21616 1 0.03 -1 -1 34020 -1 -1 35 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66048 32 32 342 271 1 181 99 17 17 289 -1 unnamed_device 25.6 MiB 1.32 1070 16515 4276 10581 1658 64.5 MiB 0.11 0.00 4.18253 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64804 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 24.7 MiB 0.87 415 9836 3792 4975 1069 63.3 MiB 0.04 0.00 2.58823 -76.4648 -2.58823 2.58823 0.87 0.000125104 9.7628e-05 0.00884574 0.00709388 -1 -1 -1 -1 34 1145 25 6.87369e+06 167686 618332. 2139.56 1.32 0.0430803 0.0355142 25762 151098 -1 885 16 568 649 42105 11703 1.91852 1.91852 -73.9266 -1.91852 0 0 787024. 2723.27 0.31 0.02 0.14 -1 -1 0.31 0.00643702 0.00563631 65 3 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_026.v common 5.43 vpr 63.78 MiB -1 -1 0.17 21612 1 0.03 -1 -1 34048 -1 -1 30 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65312 32 32 300 245 1 169 94 17 17 289 -1 unnamed_device 25.1 MiB 1.40 1004 15430 3940 9856 1634 63.8 MiB 0.10 0.00 4.64012 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66044 31 32 383 305 1 212 90 17 17 289 -1 unnamed_device 25.8 MiB 5.58 920 11145 2994 7135 1016 64.5 MiB 0.10 0.00 5.24874 -155.932 -5.24874 5.24874 0.86 0.00022297 0.000174611 0.0140711 0.011303 -1 -1 -1 -1 34 2724 30 6.87369e+06 377294 618332. 2139.56 1.58 0.07622 0.0624516 25762 151098 -1 2074 21 1789 2709 186218 47251 4.63715 4.63715 -156.683 -4.63715 0 0 787024. 2723.27 0.31 0.06 0.13 -1 -1 0.31 0.0148903 0.0129278 152 64 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_041.v common 8.04 vpr 64.29 MiB -1 -1 0.18 21348 1 0.03 -1 -1 33760 -1 -1 25 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65832 31 32 352 285 1 186 88 17 17 289 -1 unnamed_device 25.4 MiB 3.70 890 9058 2302 6004 752 64.3 MiB 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65896 31 32 337 267 1 207 86 17 17 289 -1 unnamed_device 25.5 MiB 3.84 1158 13127 3358 8192 1577 64.4 MiB 0.10 0.00 4.80948 -147.413 -4.80948 4.80948 0.87 0.000204709 0.000158017 0.0158426 0.0124126 -1 -1 -1 -1 30 3059 23 6.87369e+06 321398 556674. 1926.21 0.98 0.0516685 0.0423348 25186 138497 -1 2479 20 1353 2038 146343 31929 3.92376 3.92376 -138.461 -3.92376 0 0 706193. 2443.58 0.27 0.05 0.12 -1 -1 0.27 0.0125177 0.0108805 140 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_046.v common 6.85 vpr 64.09 MiB -1 -1 0.18 21568 1 0.04 -1 -1 34064 -1 -1 32 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65632 32 32 349 284 1 183 96 17 17 289 -1 unnamed_device 25.3 MiB 2.56 1064 11703 2949 7949 805 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 431 332 1 239 89 17 17 289 -1 unnamed_device 25.7 MiB 7.23 1345 13553 3739 8295 1519 64.7 MiB 0.11 0.00 5.88501 -174.993 -5.88501 5.88501 0.86 0.000245323 0.00019343 0.0187615 0.015055 -1 -1 -1 -1 36 3244 24 6.87369e+06 349346 648988. 2245.63 2.31 0.0880204 0.0724885 26050 158493 -1 2821 22 2283 3476 317566 69187 4.6476 4.6476 -163.711 -4.6476 0 0 828058. 2865.25 0.31 0.08 0.14 -1 -1 0.31 0.0167235 0.0144216 171 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_061.v common 8.17 vpr 64.32 MiB -1 -1 0.21 21516 1 0.03 -1 -1 34060 -1 -1 35 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65864 32 32 336 268 1 182 99 17 17 289 -1 unnamed_device 25.5 MiB 3.96 991 19023 5843 10714 2466 64.3 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65660 31 32 319 272 1 176 80 17 17 289 -1 unnamed_device 25.4 MiB 3.59 852 9712 2603 6178 931 64.1 MiB 0.07 0.00 3.7214 -119.25 -3.7214 3.7214 0.86 0.000183259 0.000144617 0.0122168 0.00983741 -1 -1 -1 -1 34 2440 41 6.87369e+06 237555 618332. 2139.56 1.60 0.0696976 0.0571619 25762 151098 -1 1987 23 1447 2180 181291 41758 3.2835 3.2835 -120.806 -3.2835 0 0 787024. 2723.27 0.30 0.06 0.14 -1 -1 0.30 0.0142525 0.0123797 114 64 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_071.v common 7.19 vpr 64.22 MiB -1 -1 0.19 21500 1 0.03 -1 -1 33836 -1 -1 34 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65760 30 32 329 273 1 167 96 17 17 289 -1 unnamed_device 25.4 MiB 3.11 924 12798 3409 8384 1005 64.2 MiB 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65560 31 32 293 230 1 175 94 17 17 289 -1 unnamed_device 25.3 MiB 1.36 1012 10744 2561 7474 709 64.0 MiB 0.08 0.00 4.55512 -132.128 -4.55512 4.55512 0.89 0.000186951 0.00014754 0.0111891 0.00879744 -1 -1 -1 -1 30 2480 24 6.87369e+06 433189 556674. 1926.21 1.04 0.0428633 0.0353869 25186 138497 -1 2052 22 1079 2002 143467 30775 3.3592 3.3592 -119.088 -3.3592 0 0 706193. 2443.58 0.28 0.05 0.14 -1 -1 0.28 0.0152971 0.0133835 129 4 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_076.v common 10.53 vpr 64.43 MiB -1 -1 0.19 21692 1 0.03 -1 -1 33520 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65980 32 32 350 275 1 214 87 17 17 289 -1 unnamed_device 25.5 MiB 4.85 991 16023 4565 8930 2528 64.4 MiB 0.12 0.00 4.82048 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65196 27 32 255 219 1 139 80 17 17 289 -1 unnamed_device 25.2 MiB 1.36 647 12980 4064 8068 848 63.7 MiB 0.07 0.00 3.48275 -97.807 -3.48275 3.48275 0.87 0.000162659 0.000121533 0.0131598 0.0103956 -1 -1 -1 -1 34 1699 22 6.87369e+06 293451 618332. 2139.56 1.35 0.0546758 0.0444766 25762 151098 -1 1429 20 1057 1601 114649 26035 2.72966 2.72966 -93.4311 -2.72966 0 0 787024. 2723.27 0.31 0.04 0.13 -1 -1 0.31 0.00939077 0.00809281 96 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_096.v common 10.49 vpr 64.57 MiB -1 -1 0.20 21792 1 0.03 -1 -1 33988 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66120 32 32 421 327 1 233 88 17 17 289 -1 unnamed_device 25.8 MiB 5.43 1306 7108 1644 4961 503 64.6 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65860 31 32 373 294 1 197 97 17 17 289 -1 unnamed_device 25.7 MiB 2.53 994 11641 2686 8324 631 64.3 MiB 0.09 0.00 4.45728 -128.707 -4.45728 4.45728 0.86 0.000227679 0.00018129 0.0138821 0.0112255 -1 -1 -1 -1 26 2822 32 6.87369e+06 475111 503264. 1741.40 1.09 0.056187 0.0464994 24322 120374 -1 2420 24 1643 2677 211161 49524 4.10046 4.10046 -136.732 -4.10046 0 0 618332. 2139.56 0.24 0.06 0.11 -1 -1 0.24 0.0155306 0.0133668 149 50 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_101.v common 7.02 vpr 64.16 MiB -1 -1 0.20 21500 1 0.03 -1 -1 34140 -1 -1 31 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65700 30 32 325 268 1 172 93 17 17 289 -1 unnamed_device 25.4 MiB 2.68 790 16473 4651 9095 2727 64.2 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65616 32 32 310 266 1 175 81 17 17 289 -1 unnamed_device 25.4 MiB 2.69 963 14081 4182 8130 1769 64.1 MiB 0.09 0.00 3.97822 -122.829 -3.97822 3.97822 0.89 0.000188158 0.000146273 0.0169303 0.0134773 -1 -1 -1 -1 34 2188 24 6.87369e+06 237555 618332. 2139.56 1.48 0.0683485 0.0558112 25762 151098 -1 1967 18 1248 1705 141947 30974 3.3007 3.3007 -124.41 -3.3007 0 0 787024. 2723.27 0.31 0.04 0.13 -1 -1 0.31 0.0107915 0.0093941 112 58 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 6.51 vpr 64.37 MiB -1 -1 0.19 21512 1 0.03 -1 -1 33732 -1 -1 39 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65912 31 32 326 261 1 178 102 17 17 289 -1 unnamed_device 25.5 MiB 2.06 880 19380 5710 10605 3065 64.4 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65600 31 32 265 230 1 169 80 17 17 289 -1 unnamed_device 25.3 MiB 3.90 763 6616 1499 4719 398 64.1 MiB 0.05 0.00 3.6942 -114.024 -3.6942 3.6942 0.89 0.000163157 0.00012855 0.00835915 0.00689354 -1 -1 -1 -1 34 2136 24 6.87369e+06 237555 618332. 2139.56 1.48 0.0552961 0.0457836 25762 151098 -1 1636 20 1101 1571 107353 27112 3.19991 3.19991 -110.054 -3.19991 0 0 787024. 2723.27 0.32 0.04 0.14 -1 -1 0.32 0.0102804 0.00894007 105 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_111.v common 8.31 vpr 64.49 MiB -1 -1 0.20 21412 1 0.03 -1 -1 33884 -1 -1 31 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 349 286 1 177 95 17 17 289 -1 unnamed_device 25.4 MiB 3.80 991 15431 4685 8411 2335 64.5 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65548 32 32 318 257 1 197 86 17 17 289 -1 unnamed_device 25.4 MiB 4.36 1100 9914 2382 6266 1266 64.0 MiB 0.07 0.00 4.82651 -140.217 -4.82651 4.82651 0.87 0.000191462 0.000151394 0.0116126 0.00936138 -1 -1 -1 -1 34 2714 26 6.87369e+06 307425 618332. 2139.56 1.60 0.0657325 0.0541548 25762 151098 -1 2273 23 1641 2291 162066 37556 4.02506 4.02506 -136.33 -4.02506 0 0 787024. 2723.27 0.30 0.05 0.13 -1 -1 0.30 0.0129756 0.0111949 132 30 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_116.v common 7.46 vpr 64.21 MiB -1 -1 0.19 21508 1 0.03 -1 -1 33928 -1 -1 29 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65756 29 32 324 268 1 169 90 17 17 289 -1 unnamed_device 25.5 MiB 3.40 896 9336 2254 6420 662 64.2 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65920 32 32 376 318 1 168 80 17 17 289 -1 unnamed_device 25.6 MiB 5.53 879 12808 3950 7474 1384 64.4 MiB 0.09 0.00 3.59615 -129.411 -3.59615 3.59615 0.86 0.000208218 0.000161966 0.0174581 0.0138737 -1 -1 -1 -1 34 2239 23 6.87369e+06 223581 618332. 2139.56 1.44 0.072401 0.0589299 25762 151098 -1 1862 21 1602 2312 183384 40198 2.87886 2.87886 -123.177 -2.87886 0 0 787024. 2723.27 0.30 0.06 0.13 -1 -1 0.30 0.0134128 0.0115365 114 96 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_121.v common 7.83 vpr 64.27 MiB -1 -1 0.20 21420 1 0.03 -1 -1 33892 -1 -1 32 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65816 32 32 360 293 1 182 96 17 17 289 -1 unnamed_device 25.3 MiB 3.71 1029 16083 4329 9310 2444 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65832 30 32 363 293 1 229 88 17 17 289 -1 unnamed_device 25.4 MiB 2.64 1124 13738 3850 8296 1592 64.3 MiB 0.11 0.00 4.83304 -147.244 -4.83304 4.83304 0.89 0.000206477 0.000163244 0.016513 0.0131582 -1 -1 -1 -1 34 2963 23 6.89349e+06 366440 618332. 2139.56 1.69 0.0724681 0.059149 25762 151098 -1 2412 24 2103 3099 213515 50520 4.35719 4.35719 -147.275 -4.35719 0 0 787024. 2723.27 0.30 0.06 0.13 -1 -1 0.30 0.0146084 0.0125248 158 63 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_003.v common 7.49 vpr 63.85 MiB -1 -1 0.17 21364 1 0.03 -1 -1 33896 -1 -1 21 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65380 32 32 299 247 1 190 85 17 17 289 -1 unnamed_device 25.3 MiB 2.76 986 10315 2668 7087 560 63.8 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2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65496 32 32 338 269 1 205 86 17 17 289 -1 unnamed_device 25.2 MiB 2.72 1059 14450 4622 7260 2568 64.0 MiB 0.10 0.00 4.13204 -133.409 -4.13204 4.13204 0.86 0.000207884 0.000163843 0.0176867 0.0141329 -1 -1 -1 -1 34 2659 50 6.89349e+06 310065 618332. 2139.56 1.95 0.087335 0.0716111 25762 151098 -1 2275 19 1487 2177 187547 40425 3.10146 3.10146 -121.303 -3.10146 0 0 787024. 2723.27 0.29 0.05 0.13 -1 -1 0.29 0.0119671 0.0103802 142 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_018.v common 8.10 vpr 63.51 MiB -1 -1 0.20 21580 1 0.03 -1 -1 33508 -1 -1 21 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65036 32 32 323 276 1 215 85 17 17 289 -1 unnamed_device 24.8 MiB 3.11 1220 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Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65216 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 25.1 MiB 1.09 988 16079 4364 9917 1798 63.7 MiB 0.12 0.00 3.39295 -107.482 -3.39295 3.39295 0.95 0.000186774 0.000147218 0.0155786 0.012451 -1 -1 -1 -1 28 2520 24 6.89349e+06 436909 531479. 1839.03 1.02 0.0495745 0.040932 24610 126494 -1 2310 22 1455 2525 183042 43297 2.94641 2.94641 -112.319 -2.94641 0 0 648988. 2245.63 0.26 0.05 0.11 -1 -1 0.26 0.0121503 0.0104621 130 3 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_028.v common 8.50 vpr 64.37 MiB -1 -1 0.22 21404 1 0.03 -1 -1 33868 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65916 32 32 338 277 1 215 87 17 17 289 -1 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GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65248 31 32 279 237 1 167 81 17 17 289 -1 unnamed_device 25.1 MiB 2.32 891 12681 4633 6140 1908 63.7 MiB 0.08 0.00 4.00748 -121.286 -4.00748 4.00748 0.88 0.000167801 0.00013189 0.0136682 0.0109159 -1 -1 -1 -1 34 2241 20 6.89349e+06 253689 618332. 2139.56 1.70 0.0604483 0.0494803 25762 151098 -1 1909 20 958 1482 148975 31008 3.08205 3.08205 -114.277 -3.08205 0 0 787024. 2723.27 0.31 0.05 0.14 -1 -1 0.31 0.0109286 0.00945882 109 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_038.v common 8.63 vpr 64.05 MiB -1 -1 0.20 21568 1 0.03 -1 -1 34192 -1 -1 25 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65592 31 32 370 297 1 235 88 17 17 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Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65176 32 32 291 230 1 175 90 17 17 289 -1 unnamed_device 25.1 MiB 1.19 980 8934 2029 6214 691 63.6 MiB 0.08 0.00 4.26729 -129.015 -4.26729 4.26729 0.88 0.000186274 0.00014782 0.0105544 0.00863692 -1 -1 -1 -1 32 2710 19 6.89349e+06 366440 586450. 2029.24 0.95 0.039582 0.032944 25474 144626 -1 2224 21 1333 2551 219755 47788 3.5072 3.5072 -124.725 -3.5072 0 0 744469. 2576.02 0.29 0.06 0.14 -1 -1 0.29 0.0115817 0.00996786 123 3 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_048.v common 8.25 vpr 64.01 MiB -1 -1 0.20 21420 1 0.03 -1 -1 33776 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65548 32 32 353 287 1 220 87 17 17 289 -1 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critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 3.42 vpr 62.79 MiB -1 -1 0.38 18688 14 0.25 -1 -1 32944 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64300 32 32 277 309 1 202 103 17 17 289 -1 unnamed_device 23.7 MiB 0.13 1547 9502 2152 6495 855 62.8 MiB 0.09 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64488 32 32 302 334 1 214 106 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1672 9856 2131 7054 671 63.0 MiB 0.11 0.00 8.06277 -168.566 -8.06277 8.06277 0.32 0.00100468 0.000929012 0.0474751 0.0438051 -1 -1 -1 -1 32 3848 27 6.55708e+06 506310 554710. 1919.41 0.76 0.185353 0.162891 22174 131602 -1 3263 16 1310 4212 205623 50945 7.27044 7.27044 -162.359 -7.27044 0 0 701300. 2426.64 0.04 0.09 0.11 -1 -1 0.04 0.0385923 0.0343556 217 208 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_006.v common 3.24 vpr 62.84 MiB -1 -1 0.39 18616 13 0.24 -1 -1 32908 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64352 32 32 292 324 1 214 105 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1522 10479 2742 6826 911 62.8 MiB 0.11 0.00 8.0037 -160.293 -8.0037 8.0037 0.32 0.000938065 0.000869644 0.0437923 0.0405003 -1 -1 -1 -1 30 3477 18 6.55708e+06 494255 526063. 1820.29 0.74 0.158732 0.139622 21886 126133 -1 2963 16 1237 4638 205817 50427 6.61036 6.61036 -146.138 -6.61036 0 0 666494. 2306.21 0.03 0.09 0.12 -1 -1 0.03 0.0341773 0.0301008 207 198 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 2.76 vpr 62.60 MiB -1 -1 0.28 17976 12 0.19 -1 -1 32644 -1 -1 38 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 27 32 229 261 1 167 97 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1076 6757 1422 4783 552 62.6 MiB 0.06 0.00 7.57737 -131.413 -7.57737 7.57737 0.35 0.000740353 0.000687695 0.0254221 0.0235468 -1 -1 -1 -1 30 2249 15 6.55708e+06 458090 526063. 1820.29 0.51 0.107135 0.0937171 21886 126133 -1 1995 16 754 2397 101760 26051 6.58844 6.58844 -121.637 -6.58844 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0301412 0.0274345 162 150 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_008.v common 3.27 vpr 62.58 MiB -1 -1 0.30 18408 12 0.19 -1 -1 32680 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64080 31 32 229 261 1 172 96 17 17 289 -1 unnamed_device 23.3 MiB 0.11 1185 7761 1749 4997 1015 62.6 MiB 0.07 0.00 6.59345 -131.227 -6.59345 6.59345 0.32 0.000740267 0.000683218 0.0287775 0.0266122 -1 -1 -1 -1 26 3514 29 6.55708e+06 397815 477104. 1650.88 0.94 0.134112 0.117297 21022 109990 -1 2674 30 1375 5142 317498 101013 5.83766 5.83766 -127.871 -5.83766 0 0 585099. 2024.56 0.03 0.13 0.09 -1 -1 0.03 0.0413928 0.0359352 148 138 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_009.v common 3.39 vpr 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64212 32 32 250 282 1 185 101 17 17 289 -1 unnamed_device 23.5 MiB 0.13 1310 8561 1766 6158 637 62.7 MiB 0.08 0.00 7.32681 -164.785 -7.32681 7.32681 0.32 0.000806421 0.000748231 0.032678 0.0302492 -1 -1 -1 -1 22 3707 41 6.55708e+06 446035 420624. 1455.45 0.96 0.159714 0.139055 20158 92377 -1 3144 22 1536 4703 302925 83797 7.11044 7.11044 -169.479 -7.11044 0 0 500653. 1732.36 0.02 0.12 0.08 -1 -1 0.02 0.0377263 0.0330363 169 156 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_011.v common 3.04 vpr 62.66 MiB -1 -1 0.32 18360 12 0.18 -1 -1 32500 -1 -1 34 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 30 32 216 248 1 156 96 17 17 289 -1 unnamed_device 23.5 MiB 0.10 1085 13455 3502 7863 2090 62.7 MiB 0.11 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63936 32 32 154 186 1 117 91 17 17 289 -1 unnamed_device 23.0 MiB 0.06 804 12127 3272 7580 1275 62.4 MiB 0.08 0.00 4.197 -96.967 -4.197 4.197 0.31 0.000509299 0.000472577 0.0323362 0.0300116 -1 -1 -1 -1 26 1624 14 6.55708e+06 325485 477104. 1650.88 0.54 0.0861366 0.0759918 21022 109990 -1 1429 12 453 1098 55059 14583 3.85168 3.85168 -96.2848 -3.85168 0 0 585099. 2024.56 0.03 0.04 0.09 -1 -1 0.03 0.0142867 0.0125614 83 60 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_026.v common 2.98 vpr 62.74 MiB -1 -1 0.23 18368 15 0.23 -1 -1 32684 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64248 32 32 254 286 1 185 105 17 17 289 -1 unnamed_device 23.5 MiB 0.10 1357 8750 1852 5899 999 62.7 MiB 0.08 0.00 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64384 30 32 213 245 1 156 93 17 17 289 -1 unnamed_device 23.3 MiB 0.08 1055 6813 1438 4810 565 62.9 MiB 0.06 0.00 6.26019 -134.121 -6.26019 6.26019 0.31 0.00068437 0.000634858 0.0248044 0.0229674 -1 -1 -1 -1 30 2151 16 6.55708e+06 373705 526063. 1820.29 0.56 0.102637 0.0897125 21886 126133 -1 1944 16 673 2039 82756 21710 5.59726 5.59726 -126.076 -5.59726 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0238631 0.0209819 135 125 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_031.v common 2.76 vpr 62.54 MiB -1 -1 0.27 18100 11 0.19 -1 -1 32736 -1 -1 38 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64040 28 32 227 259 1 163 98 17 17 289 -1 unnamed_device 23.3 MiB 0.09 1081 10223 2473 6798 952 62.5 MiB 0.09 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64224 31 32 276 308 1 208 108 17 17 289 -1 unnamed_device 23.6 MiB 0.13 1520 8332 1703 5917 712 62.7 MiB 0.09 0.00 7.94503 -161.931 -7.94503 7.94503 0.32 0.000907456 0.000836347 0.0336936 0.031227 -1 -1 -1 -1 26 4333 40 6.55708e+06 542475 477104. 1650.88 1.02 0.173665 0.151349 21022 109990 -1 3482 17 1358 4203 231179 55264 7.22664 7.22664 -160.684 -7.22664 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0333933 0.0294144 200 185 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_041.v common 3.27 vpr 62.66 MiB -1 -1 0.39 18500 13 0.25 -1 -1 32904 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64160 31 32 269 301 1 187 100 17 17 289 -1 unnamed_device 23.6 MiB 0.12 1368 6596 1290 4863 443 62.7 MiB 0.07 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 31 32 284 316 1 196 104 17 17 289 -1 unnamed_device 23.7 MiB 0.14 1353 8400 1833 5671 896 62.8 MiB 0.08 0.00 8.00359 -155.245 -8.00359 8.00359 0.31 0.000908757 0.000841742 0.0358726 0.0331558 -1 -1 -1 -1 24 3710 27 6.55708e+06 494255 448715. 1552.65 1.43 0.161372 0.140867 20734 103517 -1 3127 19 1328 4863 261396 62929 7.33356 7.33356 -160.506 -7.33356 0 0 554710. 1919.41 0.02 0.10 0.09 -1 -1 0.02 0.0370573 0.032434 201 193 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_046.v common 3.51 vpr 62.97 MiB -1 -1 0.36 18516 12 0.23 -1 -1 32672 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64484 32 32 303 335 1 212 104 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1559 7424 1464 5587 373 63.0 MiB 0.08 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65464 32 32 351 383 1 255 115 17 17 289 -1 unnamed_device 24.2 MiB 0.16 1912 10996 2333 7725 938 63.9 MiB 0.12 0.00 9.61395 -186.411 -9.61395 9.61395 0.32 0.0011181 0.00103394 0.0489481 0.0452034 -1 -1 -1 -1 30 4514 22 6.55708e+06 614805 526063. 1820.29 0.99 0.19515 0.17157 21886 126133 -1 3814 18 1702 6171 283766 68025 8.38947 8.38947 -178.746 -8.38947 0 0 666494. 2306.21 0.03 0.11 0.10 -1 -1 0.03 0.0451658 0.0398477 263 257 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_061.v common 3.50 vpr 63.46 MiB -1 -1 0.27 18540 13 0.31 -1 -1 32704 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64988 32 32 297 329 1 211 102 17 17 289 -1 unnamed_device 23.7 MiB 0.14 1494 7004 1387 5016 601 63.5 MiB 0.08 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63972 30 32 228 260 1 158 97 17 17 289 -1 unnamed_device 23.4 MiB 0.09 1101 6979 1478 4733 768 62.5 MiB 0.06 0.00 7.33897 -151.074 -7.33897 7.33897 0.32 0.000743562 0.000688744 0.0262544 0.0243127 -1 -1 -1 -1 28 2502 19 6.55708e+06 421925 500653. 1732.36 0.53 0.114578 0.100017 21310 115450 -1 2128 14 720 2386 111841 28645 6.59044 6.59044 -145.015 -6.59044 0 0 612192. 2118.31 0.04 0.08 0.12 -1 -1 0.04 0.0296621 0.0262135 152 140 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_066.v common 3.19 vpr 62.88 MiB -1 -1 0.40 18500 12 0.27 -1 -1 33148 -1 -1 41 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64392 29 32 275 307 1 195 102 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1359 6290 1245 4520 525 62.9 MiB 0.07 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64248 29 32 262 294 1 197 101 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1268 9501 2060 6462 979 62.7 MiB 0.09 0.00 7.09867 -136.55 -7.09867 7.09867 0.32 0.000888396 0.000824305 0.0394313 0.0365356 -1 -1 -1 -1 28 3329 23 6.55708e+06 482200 500653. 1732.36 0.81 0.153343 0.134375 21310 115450 -1 2580 16 1111 3693 174673 45072 6.17838 6.17838 -129.615 -6.17838 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.031461 0.0277134 187 177 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_086.v common 2.70 vpr 62.45 MiB -1 -1 0.30 18100 13 0.16 -1 -1 32568 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63952 32 32 222 254 1 166 98 17 17 289 -1 unnamed_device 23.2 MiB 0.09 1204 5273 829 4270 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64220 31 32 244 276 1 183 99 17 17 289 -1 unnamed_device 23.5 MiB 0.10 1234 5343 953 4107 283 62.7 MiB 0.06 0.00 7.43715 -158.003 -7.43715 7.43715 0.32 0.000792845 0.000735142 0.0216441 0.0200635 -1 -1 -1 -1 28 3024 19 6.55708e+06 433980 500653. 1732.36 0.69 0.116315 0.10146 21310 115450 -1 2710 15 1091 3540 165817 43066 6.44632 6.44632 -152.105 -6.44632 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0262288 0.023126 164 153 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_091.v common 3.79 vpr 62.85 MiB -1 -1 0.37 18668 12 0.29 -1 -1 32728 -1 -1 44 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64356 32 32 300 332 1 220 108 17 17 289 -1 unnamed_device 23.6 MiB 0.12 1579 8332 1506 5759 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63892 27 32 219 251 1 154 95 17 17 289 -1 unnamed_device 23.1 MiB 0.08 1050 6359 1311 4459 589 62.4 MiB 0.06 0.00 6.77412 -124.861 -6.77412 6.77412 0.32 0.000713459 0.000661731 0.0237722 0.0219985 -1 -1 -1 -1 26 2518 28 6.55708e+06 433980 477104. 1650.88 0.64 0.117944 0.102417 21022 109990 -1 2290 18 974 3227 154423 38178 5.86158 5.86158 -120.568 -5.86158 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0275303 0.0241178 147 140 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_096.v common 4.52 vpr 63.91 MiB -1 -1 0.42 19032 13 0.44 -1 -1 32772 -1 -1 54 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65444 32 32 380 412 1 268 118 17 17 289 -1 unnamed_device 24.4 MiB 0.25 1943 11678 2402 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63888 32 32 235 267 1 175 100 17 17 289 -1 unnamed_device 23.1 MiB 0.09 1209 8452 1924 5669 859 62.4 MiB 0.08 0.00 7.00455 -144.749 -7.00455 7.00455 0.31 0.000733587 0.000678251 0.02952 0.0272855 -1 -1 -1 -1 30 2684 30 6.55708e+06 433980 526063. 1820.29 0.61 0.127043 0.110742 21886 126133 -1 2234 16 921 2754 114752 30025 6.07044 6.07044 -136.126 -6.07044 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0260629 0.022921 156 141 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_106.v common 3.36 vpr 62.86 MiB -1 -1 0.35 18372 13 0.31 -1 -1 32832 -1 -1 43 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64368 31 32 294 326 1 209 106 17 17 289 -1 unnamed_device 23.7 MiB 0.13 1483 8106 1671 5747 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64396 31 32 225 257 1 161 101 17 17 289 -1 unnamed_device 23.1 MiB 0.09 1212 6916 1486 4812 618 62.9 MiB 0.06 0.00 7.22863 -147.66 -7.22863 7.22863 0.32 0.00069335 0.000652807 0.0238351 0.022098 -1 -1 -1 -1 28 2636 14 6.55708e+06 458090 500653. 1732.36 0.62 0.103974 0.0910087 21310 115450 -1 2360 14 823 2439 123719 30628 6.45858 6.45858 -142.003 -6.45858 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0230327 0.0203696 147 134 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_111.v common 3.33 vpr 63.38 MiB -1 -1 0.35 18436 12 0.20 -1 -1 32828 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64904 32 32 288 320 1 207 102 17 17 289 -1 unnamed_device 23.7 MiB 0.13 1453 7242 1384 5338 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 32 32 285 317 1 211 104 17 17 289 -1 unnamed_device 23.6 MiB 0.14 1523 12304 3016 8156 1132 62.7 MiB 0.12 0.00 8.0432 -171.219 -8.0432 8.0432 0.31 0.000924381 0.000858307 0.0502871 0.0466214 -1 -1 -1 -1 26 4101 25 6.55708e+06 482200 477104. 1650.88 1.03 0.169712 0.149072 21022 109990 -1 3342 18 1458 4644 236912 56442 6.94704 6.94704 -162.816 -6.94704 0 0 585099. 2024.56 0.03 0.09 0.11 -1 -1 0.03 0.0358245 0.0314794 203 191 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_116.v common 3.23 vpr 62.64 MiB -1 -1 0.34 18344 11 0.19 -1 -1 33160 -1 -1 36 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64140 29 32 243 275 1 177 97 17 17 289 -1 unnamed_device 23.4 MiB 0.10 1302 7201 1461 5220 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64020 32 32 238 270 1 177 101 17 17 289 -1 unnamed_device 23.5 MiB 0.09 1218 9501 2083 6458 960 62.5 MiB 0.08 0.00 7.91043 -170.443 -7.91043 7.91043 0.32 0.000758064 0.000703417 0.0336526 0.0311554 -1 -1 -1 -1 26 2922 26 6.55708e+06 446035 477104. 1650.88 0.67 0.133295 0.11664 21022 109990 -1 2523 22 1300 4049 241032 73323 6.78444 6.78444 -160.626 -6.78444 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0332941 0.0290198 163 144 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_121.v common 3.25 vpr 62.82 MiB -1 -1 0.38 18620 12 0.22 -1 -1 32676 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64328 32 32 269 301 1 187 99 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1308 9675 2304 6571 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64356 32 32 264 296 1 189 102 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1292 11050 2366 7675 1009 62.8 MiB 0.10 0.00 7.4882 -160.311 -7.4882 7.4882 0.32 0.000852834 0.000791169 0.0431371 0.0399693 -1 -1 -1 -1 32 2688 19 6.55708e+06 458090 554710. 1919.41 0.53 0.143565 0.126182 22174 131602 -1 2548 15 967 2908 141203 35435 6.62964 6.62964 -153.549 -6.62964 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0282648 0.0249116 183 170 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_126.v common 2.43 vpr 62.57 MiB -1 -1 0.27 17920 9 0.15 -1 -1 32444 -1 -1 32 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 25 32 183 215 1 133 89 17 17 289 -1 unnamed_device 22.9 MiB 0.07 884 9791 2362 5778 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64504 30 32 363 293 1 196 92 17 17 289 -1 unnamed_device 23.9 MiB 0.21 1149 17066 4987 10364 1715 63.0 MiB 0.18 0.00 4.95721 -143.504 -4.95721 4.95721 0.32 0.000710438 0.000660775 0.0614398 0.0570745 -1 -1 -1 -1 32 2427 21 6.64007e+06 376740 554710. 1919.41 0.57 0.145575 0.129108 22834 132086 -1 2154 19 1350 2068 152921 33916 3.93949 3.93949 -135.593 -3.93949 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0272536 0.0238064 147 63 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 2.68 vpr 62.80 MiB -1 -1 0.23 18488 1 0.03 -1 -1 30312 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 32 32 299 247 1 188 95 17 17 289 -1 unnamed_device 23.6 MiB 0.21 995 8519 1888 6283 348 62.8 MiB 0.09 0.00 4.69952 -119.793 -4.69952 4.69952 0.32 0.000629047 0.000585652 0.0270416 0.0251595 -1 -1 -1 -1 26 2703 22 6.64007e+06 389298 477104. 1650.88 0.59 0.103803 0.0908653 21682 110474 -1 2071 19 1134 1713 100741 25334 3.82002 3.82002 -121.448 -3.82002 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0245892 0.021454 129 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.64 vpr 62.60 MiB -1 -1 0.24 18320 1 0.03 -1 -1 30340 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 23.5 MiB 0.07 1008 16445 5394 8747 2304 62.6 MiB 0.16 0.00 4.53207 -121.894 -4.53207 4.53207 0.31 0.000634108 0.000588823 0.0522809 0.04853 -1 -1 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0.09 -1 -1 0.03 0.0306004 0.0266689 134 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 2.73 vpr 62.80 MiB -1 -1 0.25 18556 1 0.03 -1 -1 30344 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64308 32 32 366 295 1 189 103 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1006 15768 4339 8895 2534 62.8 MiB 0.15 0.00 3.38256 -114.774 -3.38256 3.38256 0.32 0.000724938 0.000673003 0.0497796 0.04616 -1 -1 -1 -1 32 2303 19 6.64007e+06 489762 554710. 1919.41 0.56 0.133213 0.117724 22834 132086 -1 1827 17 1074 1725 91804 23651 3.05137 3.05137 -112.229 -3.05137 0 0 701300. 2426.64 0.03 0.06 0.10 -1 -1 0.03 0.0301609 0.0264063 145 58 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.43 vpr 63.12 MiB -1 -1 0.23 18080 1 0.03 -1 -1 30572 -1 -1 21 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64636 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 23.5 MiB 0.08 751 11948 4103 6020 1825 63.1 MiB 0.10 0.00 3.76738 -102.601 -3.76738 3.76738 0.32 0.000553592 0.000515184 0.0404029 0.0376175 -1 -1 -1 -1 28 1527 20 6.64007e+06 263718 500653. 1732.36 0.48 0.10499 0.0926546 21970 115934 -1 1471 20 917 1568 101266 24667 2.74477 2.74477 -95.077 -2.74477 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0224191 0.0194903 97 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.59 vpr 62.68 MiB -1 -1 0.24 17844 1 0.03 -1 -1 30220 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64188 31 32 271 219 1 162 98 17 17 289 -1 unnamed_device 23.6 MiB 0.06 965 15848 4431 8849 2568 62.7 MiB 0.14 0.00 3.47227 -101.06 -3.47227 3.47227 0.35 0.000595573 0.000554221 0.0440162 0.0408999 -1 -1 -1 -1 32 1850 22 6.64007e+06 439530 554710. 1919.41 0.50 0.116127 0.102699 22834 132086 -1 1654 15 788 1468 75522 19037 2.60777 2.60777 -91.3107 -2.60777 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.019078 0.0167327 123 4 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 2.86 vpr 62.68 MiB -1 -1 0.24 18476 1 0.03 -1 -1 30096 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64184 31 32 317 271 1 168 87 17 17 289 -1 unnamed_device 23.5 MiB 0.16 906 5655 1194 4208 253 62.7 MiB 0.07 0.00 3.60222 -117.559 -3.60222 3.60222 0.32 0.000639636 0.000594878 0.0209485 0.0195041 -1 -1 -1 -1 28 2705 33 6.64007e+06 301392 500653. 1732.36 0.81 0.108644 0.0943614 21970 115934 -1 2030 20 1272 1882 135466 32452 3.48643 3.48643 -121.992 -3.48643 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0250351 0.0217808 117 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.55 vpr 62.54 MiB -1 -1 0.23 18256 1 0.03 -1 -1 30068 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64036 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 23.5 MiB 0.13 936 12323 3600 6804 1919 62.5 MiB 0.12 0.00 3.85841 -126.873 -3.85841 3.85841 0.32 0.000619093 0.000576413 0.0446968 0.0416188 -1 -1 -1 -1 32 1786 19 6.64007e+06 238602 554710. 1919.41 0.52 0.11678 0.103252 22834 132086 -1 1612 19 841 1348 82679 19678 2.65457 2.65457 -110.251 -2.65457 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0229212 0.0201044 115 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 2.54 vpr 62.74 MiB -1 -1 0.25 18388 1 0.03 -1 -1 30384 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64248 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 23.6 MiB 0.12 895 11106 3427 6381 1298 62.7 MiB 0.11 0.00 3.83641 -113.668 -3.83641 3.83641 0.32 0.00061658 0.000573067 0.0411971 0.0383264 -1 -1 -1 -1 32 1647 21 6.64007e+06 238602 554710. 1919.41 0.50 0.113563 0.100095 22834 132086 -1 1460 17 663 1021 62497 14760 2.80297 2.80297 -100.224 -2.80297 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0216856 0.0189302 101 63 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 2.69 vpr 62.66 MiB -1 -1 0.23 18084 1 0.03 -1 -1 30100 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64164 32 32 276 237 1 167 87 17 17 289 -1 unnamed_device 23.6 MiB 0.23 914 15063 5013 7393 2657 62.7 MiB 0.14 0.00 3.80941 -119.793 -3.80941 3.80941 0.32 0.000593224 0.000551677 0.0487755 0.0453526 -1 -1 -1 -1 30 2022 22 6.64007e+06 288834 526063. 1820.29 0.52 0.12086 0.107095 22546 126617 -1 1661 17 830 1209 74992 17561 2.80297 2.80297 -107.181 -2.80297 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0208561 0.0182301 111 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 2.65 vpr 62.78 MiB -1 -1 0.13 18376 1 0.03 -1 -1 30344 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64284 32 32 344 272 1 202 93 17 17 289 -1 unnamed_device 23.8 MiB 0.21 1145 10803 2724 7364 715 62.8 MiB 0.12 0.00 4.40284 -140.386 -4.40284 4.40284 0.32 0.000709355 0.000659531 0.0383752 0.035603 -1 -1 -1 -1 30 2401 22 6.64007e+06 364182 526063. 1820.29 0.58 0.122776 0.107981 22546 126617 -1 2127 21 1359 2094 110426 27165 3.25703 3.25703 -124.202 -3.25703 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0291253 0.0254331 147 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 2.80 vpr 63.43 MiB -1 -1 0.16 18368 1 0.03 -1 -1 30268 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64948 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 23.8 MiB 0.13 989 17873 5923 8850 3100 63.4 MiB 0.17 0.00 4.77444 -137.586 -4.77444 4.77444 0.32 0.000712912 0.000662078 0.0594743 0.0552107 -1 -1 -1 -1 28 2617 24 6.64007e+06 426972 500653. 1732.36 0.75 0.150152 0.13295 21970 115934 -1 2048 20 1394 2351 145782 36264 4.26142 4.26142 -132.668 -4.26142 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.028755 0.0251025 139 61 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.41 vpr 62.78 MiB -1 -1 0.22 18068 1 0.03 -1 -1 30400 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64288 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 23.2 MiB 0.08 694 9234 2301 6256 677 62.8 MiB 0.08 0.00 3.09179 -89.0655 -3.09179 3.09179 0.32 0.000541072 0.000503614 0.0294454 0.0273744 -1 -1 -1 -1 28 1661 20 6.64007e+06 288834 500653. 1732.36 0.48 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64288 32 32 323 276 1 153 98 17 17 289 -1 unnamed_device 23.6 MiB 0.09 912 16523 5279 8659 2585 62.8 MiB 0.15 0.00 2.85064 -102.219 -2.85064 2.85064 0.31 0.000652995 0.000606818 0.0503687 0.0467251 -1 -1 -1 -1 32 1754 21 6.64007e+06 426972 554710. 1919.41 0.54 0.125923 0.111248 22834 132086 -1 1560 18 1067 1888 103791 25844 1.91191 1.91191 -89.0293 -1.91191 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0239531 0.0208594 115 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 2.31 vpr 62.77 MiB -1 -1 0.21 18116 1 0.03 -1 -1 30064 -1 -1 17 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 30 32 222 206 1 117 79 17 17 289 -1 unnamed_device 23.6 MiB 0.06 532 9543 2250 6629 664 62.8 MiB 0.07 0.00 2.4343 -77.8363 -2.4343 2.4343 0.31 0.000498159 0.00046299 0.0295526 0.0274642 -1 -1 -1 -1 28 1401 21 6.64007e+06 213486 500653. 1732.36 0.51 0.087921 0.0771578 21970 115934 -1 1137 19 688 980 63827 17614 1.86811 1.86811 -77.6028 -1.86811 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0187935 0.0163088 85 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 2.70 vpr 62.58 MiB -1 -1 0.24 18244 1 0.03 -1 -1 30440 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 31 32 291 243 1 171 88 17 17 289 -1 unnamed_device 23.5 MiB 0.24 847 10423 2562 6326 1535 62.6 MiB 0.10 0.00 5.02597 -142.893 -5.02597 5.02597 0.32 0.000610921 0.000568644 0.0349955 0.0325792 -1 -1 -1 -1 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0.03 0.03006 0.0262474 140 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 2.91 vpr 62.91 MiB -1 -1 0.26 18548 1 0.03 -1 -1 30292 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64416 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 23.8 MiB 0.23 1260 17591 5360 9925 2306 62.9 MiB 0.19 0.00 4.72719 -143.457 -4.72719 4.72719 0.35 0.000740177 0.000688771 0.0632155 0.0586458 -1 -1 -1 -1 32 2623 20 6.64007e+06 389298 554710. 1919.41 0.56 0.148536 0.131775 22834 132086 -1 2332 17 1286 2056 118473 28953 3.90649 3.90649 -129.764 -3.90649 0 0 701300. 2426.64 0.03 0.06 0.09 -1 -1 0.03 0.0257533 0.0225868 151 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 2.44 vpr 62.62 MiB -1 -1 0.21 18080 1 0.03 -1 -1 30528 -1 -1 20 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64124 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 23.2 MiB 0.09 426 10536 3993 4440 2103 62.6 MiB 0.07 0.00 2.50053 -67.6186 -2.50053 2.50053 0.32 0.000436929 0.000400303 0.0290515 0.0268679 -1 -1 -1 -1 32 1026 22 6.64007e+06 251160 554710. 1919.41 0.51 0.0817182 0.0716779 22834 132086 -1 874 18 548 811 45228 13433 1.97731 1.97731 -65.3841 -1.97731 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0152356 0.0132622 81 30 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 2.53 vpr 62.68 MiB -1 -1 0.22 17864 1 0.03 -1 -1 30276 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64184 32 32 285 227 1 165 89 17 17 289 -1 unnamed_device 23.6 MiB 0.07 962 6821 1380 5168 273 62.7 MiB 0.08 0.00 4.45587 -122.025 -4.45587 4.45587 0.32 0.000632837 0.000579639 0.0236586 0.0219696 -1 -1 -1 -1 32 2155 19 6.64007e+06 313950 554710. 1919.41 0.55 0.0955033 0.0835082 22834 132086 -1 1903 22 1221 2303 145599 33656 3.56023 3.56023 -116.407 -3.56023 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0269469 0.0234776 125 3 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.40 vpr 62.68 MiB -1 -1 0.20 17616 1 0.02 -1 -1 30032 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64184 32 32 173 169 1 116 81 17 17 289 -1 unnamed_device 23.4 MiB 0.05 506 11281 3424 5287 2570 62.7 MiB 0.07 0.00 2.72793 -76.1863 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62.79 MiB -1 -1 0.24 18376 1 0.03 -1 -1 30248 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64296 32 32 338 277 1 179 99 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1102 15147 4066 9723 1358 62.8 MiB 0.15 0.00 4.9076 -137.928 -4.9076 4.9076 0.32 0.000693713 0.000642192 0.0478832 0.0443651 -1 -1 -1 -1 30 2217 21 6.64007e+06 439530 526063. 1820.29 0.53 0.127985 0.112974 22546 126617 -1 1976 19 975 1710 85252 20817 3.73962 3.73962 -125.26 -3.73962 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0265032 0.0231786 133 50 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 2.44 vpr 63.14 MiB -1 -1 0.22 18024 1 0.03 -1 -1 30044 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 32 32 284 241 1 145 85 17 17 289 -1 unnamed_device 23.3 MiB 0.07 891 9943 2356 6701 886 63.1 MiB 0.10 0.00 3.06979 -104.718 -3.06979 3.06979 0.31 0.000603833 0.000560397 0.0349301 0.0324289 -1 -1 -1 -1 32 1751 17 6.64007e+06 263718 554710. 1919.41 0.49 0.1021 0.0898442 22834 132086 -1 1528 20 825 1366 74902 18215 2.59557 2.59557 -98.7069 -2.59557 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0250366 0.0217718 107 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 2.20 vpr 62.54 MiB -1 -1 0.22 18104 1 0.03 -1 -1 30208 -1 -1 28 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64044 30 32 262 227 1 135 90 17 17 289 -1 unnamed_device 23.2 MiB 0.04 680 8733 1889 6137 707 62.5 MiB 0.08 0.00 3.24119 -95.6654 -3.24119 3.24119 0.24 0.000566872 0.000527984 0.0264591 0.0246154 -1 -1 -1 -1 32 1467 24 6.64007e+06 351624 554710. 1919.41 0.50 0.0951258 0.0831051 22834 132086 -1 1268 15 541 823 48367 12287 2.78097 2.78097 -89.3799 -2.78097 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0180998 0.0158592 100 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 2.42 vpr 62.76 MiB -1 -1 0.23 18080 1 0.03 -1 -1 30176 -1 -1 27 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64264 28 32 260 223 1 140 87 17 17 289 -1 unnamed_device 23.4 MiB 0.07 639 10263 2494 7193 576 62.8 MiB 0.09 0.00 3.42827 -93.8875 -3.42827 3.42827 0.32 0.00043274 0.000391438 0.0289215 0.0266058 -1 -1 -1 -1 32 1562 21 6.64007e+06 339066 554710. 1919.41 0.47 0.0861484 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fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 2.40 vpr 62.91 MiB -1 -1 0.18 17992 1 0.03 -1 -1 30284 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64420 31 32 271 231 1 148 96 17 17 289 -1 unnamed_device 23.9 MiB 0.07 762 8199 1685 6175 339 62.9 MiB 0.08 0.00 3.50227 -101.986 -3.50227 3.50227 0.32 0.000585689 0.000544952 0.0239081 0.0222302 -1 -1 -1 -1 26 1895 22 6.64007e+06 414414 477104. 1650.88 0.55 0.0985801 0.0861158 21682 110474 -1 1634 19 992 1839 102453 25790 2.84297 2.84297 -101.016 -2.84297 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0222234 0.0193272 111 30 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 2.55 vpr 63.14 MiB -1 -1 0.23 18392 1 0.03 -1 -1 30376 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 29 32 291 250 1 153 92 17 17 289 -1 unnamed_device 23.6 MiB 0.13 926 8579 2243 5615 721 63.1 MiB 0.09 0.00 3.38029 -105.574 -3.38029 3.38029 0.32 0.000606378 0.000563299 0.0269435 0.0250583 -1 -1 -1 -1 32 1817 16 6.64007e+06 389298 554710. 1919.41 0.52 0.0856407 0.0752452 22834 132086 -1 1610 20 846 1287 80837 19336 2.46117 2.46117 -95.63 -2.46117 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0238605 0.0207606 112 54 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 2.62 vpr 63.50 MiB -1 -1 0.18 18424 1 0.03 -1 -1 30488 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1231 12606 3242 8430 934 63.5 MiB 0.13 0.00 4.47716 -125.986 -4.47716 4.47716 0.34 0.000742465 0.000690503 0.040033 0.0371622 -1 -1 -1 -1 30 2392 22 6.64007e+06 527436 526063. 1820.29 0.57 0.121338 0.107295 22546 126617 -1 2206 21 1094 2094 127085 27888 3.60143 3.60143 -119.17 -3.60143 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0305183 0.026678 158 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 2.79 vpr 63.49 MiB -1 -1 0.25 18340 1 0.04 -1 -1 30180 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65012 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1118 12208 2919 8273 1016 63.5 MiB 0.17 0.00 3.91238 -131.369 -3.91238 3.91238 0.32 0.000761885 0.000699352 0.055694 0.0515452 -1 -1 -1 -1 28 2461 21 6.64007e+06 514878 500653. 1732.36 0.57 0.144934 0.12814 21970 115934 -1 2208 19 1586 2620 148161 36739 2.95517 2.95517 -121.08 -2.95517 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0289413 0.0253146 150 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 2.72 vpr 62.75 MiB -1 -1 0.22 18372 1 0.03 -1 -1 30040 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64252 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 23.6 MiB 0.18 947 12938 4038 6585 2315 62.7 MiB 0.13 0.00 4.39563 -129.442 -4.39563 4.39563 0.31 0.000592796 0.000550729 0.0448114 0.0415629 -1 -1 -1 -1 28 2146 18 6.64007e+06 288834 500653. 1732.36 0.64 0.112874 0.0997387 21970 115934 -1 1870 18 1048 1494 96179 23713 3.25683 3.25683 -117.68 -3.25683 0 0 612192. 2118.31 0.03 0.06 0.10 -1 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64588 31 32 377 302 1 234 99 17 17 289 -1 unnamed_device 24.2 MiB 0.36 1443 12183 2916 8073 1194 63.1 MiB 0.15 0.00 5.78896 -175.168 -5.78896 5.78896 0.34 0.000730371 0.000678859 0.042079 0.0390942 -1 -1 -1 -1 28 3186 22 6.64007e+06 452088 500653. 1732.36 0.59 0.124257 0.109624 21970 115934 -1 2704 21 1544 2373 159211 37709 4.84135 4.84135 -166.082 -4.84135 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0305437 0.0267185 178 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 2.98 vpr 62.88 MiB -1 -1 0.25 18228 1 0.03 -1 -1 30372 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64388 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 23.8 MiB 0.31 1234 12191 3319 7524 1348 62.9 MiB 0.14 0.00 5.10379 -154.62 -5.10379 5.10379 0.32 0.000745353 0.000692519 0.0442067 0.0410231 -1 -1 -1 -1 30 2528 23 6.64007e+06 401856 526063. 1820.29 0.56 0.134313 0.118402 22546 126617 -1 2128 20 1112 1738 94826 23161 4.27288 4.27288 -144.151 -4.27288 0 0 666494. 2306.21 0.04 0.08 0.11 -1 -1 0.04 0.0377662 0.0337785 167 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 2.73 vpr 62.80 MiB -1 -1 0.26 18420 1 0.03 -1 -1 30316 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1115 12860 3466 8442 952 62.8 MiB 0.13 0.00 4.70003 -136.748 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23971 3.50942 3.50942 -116.943 -3.50942 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0231839 0.0203345 125 27 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 3.03 vpr 63.46 MiB -1 -1 0.27 18732 1 0.03 -1 -1 30432 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64984 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 24.6 MiB 0.16 1312 16552 4366 10580 1606 63.5 MiB 0.18 0.00 5.1085 -163.706 -5.1085 5.1085 0.32 0.000866276 0.000805627 0.0599784 0.0556569 -1 -1 -1 -1 26 3108 25 6.64007e+06 539994 477104. 1650.88 0.74 0.169209 0.149122 21682 110474 -1 2610 21 1586 2418 149034 35187 4.18489 4.18489 -152.922 -4.18489 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0364613 0.0317981 176 87 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.51 vpr 62.67 MiB -1 -1 0.23 18088 1 0.03 -1 -1 30204 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64176 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 23.4 MiB 0.08 705 8213 2081 5243 889 62.7 MiB 0.08 0.00 3.75024 -98.8591 -3.75024 3.75024 0.32 0.0005679 0.000526595 0.0263248 0.0244408 -1 -1 -1 -1 32 1549 22 6.64007e+06 288834 554710. 1919.41 0.53 0.100546 0.0878178 22834 132086 -1 1406 19 899 1604 92734 23078 2.74057 2.74057 -95.4429 -2.74057 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0216482 0.0188058 104 28 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 2.78 vpr 62.98 MiB -1 -1 0.25 18292 1 0.03 -1 -1 30248 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64492 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 24.0 MiB 0.22 1232 11863 3185 7621 1057 63.0 MiB 0.13 0.00 5.0773 -152.378 -5.0773 5.0773 0.32 0.000685702 0.000638075 0.0388617 0.0361442 -1 -1 -1 -1 30 2607 19 6.64007e+06 426972 526063. 1820.29 0.54 0.117632 0.103629 22546 126617 -1 2248 21 1248 1852 100468 23985 3.96729 3.96729 -135.475 -3.96729 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0289625 0.0253341 149 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.99 vpr 62.95 MiB -1 -1 0.17 18472 1 0.03 -1 -1 30352 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64456 32 32 349 284 1 183 102 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1221 11764 2967 7709 1088 62.9 MiB 0.12 0.00 3.95307 -117.525 -3.95307 3.95307 0.32 0.000696024 0.000644408 0.0366916 0.0340243 -1 -1 -1 -1 22 3240 30 6.64007e+06 477204 420624. 1455.45 0.98 0.131608 0.11527 20818 92861 -1 2548 19 1326 2488 176484 42475 3.19957 3.19957 -118.379 -3.19957 0 0 500653. 1732.36 0.02 0.07 0.08 -1 -1 0.02 0.0262585 0.0229142 137 53 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 2.58 vpr 62.59 MiB -1 -1 0.23 17800 1 0.03 -1 -1 30212 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64096 32 32 291 230 1 168 91 17 17 289 -1 unnamed_device 23.5 MiB 0.07 900 13147 4476 6141 2530 62.6 MiB 0.13 0.00 4.20356 -122.292 -4.20356 4.20356 0.31 0.000620913 0.00057678 0.0422596 0.0392478 -1 -1 -1 -1 32 2124 24 6.64007e+06 339066 554710. 1919.41 0.57 0.118883 0.104795 22834 132086 -1 1774 20 1016 2010 121136 29266 3.34003 3.34003 -110.91 -3.34003 0 0 701300. 2426.64 0.03 0.06 0.12 -1 -1 0.03 0.0252076 0.0219955 127 3 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 2.84 vpr 63.38 MiB -1 -1 0.23 18376 1 0.03 -1 -1 30420 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64904 32 32 353 287 1 198 94 17 17 289 -1 unnamed_device 23.8 MiB 0.24 1217 9679 2220 6521 938 63.4 MiB 0.12 0.00 4.87535 -142.566 -4.87535 4.87535 0.32 0.00070198 0.000652914 0.0343575 0.0319558 -1 -1 -1 -1 28 2610 19 6.64007e+06 376740 500653. 1732.36 0.55 0.115739 0.101618 21970 115934 -1 2275 19 1225 1679 117927 28569 3.29983 3.29983 -124.736 -3.29983 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0264037 0.0231204 142 55 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 2.88 vpr 62.88 MiB -1 -1 0.24 18384 1 0.03 -1 -1 30292 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64388 32 32 361 291 1 185 103 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1032 10466 2519 7358 589 62.9 MiB 0.11 0.00 3.87166 -121.484 -3.87166 3.87166 0.33 0.000728678 0.00067732 0.03387 0.0314019 -1 -1 -1 -1 26 2492 21 6.64007e+06 489762 477104. 1650.88 0.70 0.123703 0.108661 21682 110474 -1 2122 22 1168 2158 142549 33751 3.01017 3.01017 -112.725 -3.01017 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0306578 0.0267168 139 55 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.92 vpr 63.10 MiB -1 -1 0.26 18372 1 0.03 -1 -1 30420 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 32 32 382 305 1 192 104 17 17 289 -1 unnamed_device 23.9 MiB 0.13 1185 14744 3959 8963 1822 63.1 MiB 0.15 0.00 4.29207 -132.639 -4.29207 4.29207 0.32 0.000732956 0.000680596 0.0468908 0.0434674 -1 -1 -1 -1 28 2570 18 6.64007e+06 502320 500653. 1732.36 0.59 0.13304 0.117512 21970 115934 -1 2290 20 1435 2358 148680 35355 3.36377 3.36377 -121.085 -3.36377 0 0 612192. 2118.31 0.03 0.10 0.14 -1 -1 0.03 0.0322143 0.0281537 149 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 2.45 vpr 62.71 MiB -1 -1 0.14 18284 1 0.03 -1 -1 30308 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64216 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 23.6 MiB 0.07 1023 10540 2564 7150 826 62.7 MiB 0.10 0.00 4.27093 -125.084 -4.27093 4.27093 0.30 0.000635854 0.000590624 0.0312502 0.0290072 -1 -1 -1 -1 32 2034 20 6.64007e+06 452088 554710. 1919.41 0.53 0.105906 0.0929137 22834 132086 -1 1819 20 1043 1996 118484 27523 3.47223 3.47223 -116.792 -3.47223 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0255077 0.0222584 127 24 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 2.67 vpr 62.80 MiB -1 -1 0.14 18480 1 0.03 -1 -1 30144 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 32 32 319 257 1 198 93 17 17 289 -1 unnamed_device 23.8 MiB 0.21 1094 10173 2429 6748 996 62.8 MiB 0.11 0.00 5.10621 -136.906 -5.10621 5.10621 0.32 0.000655901 0.000609938 0.0340695 0.0316782 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0.08 0.10 -1 -1 0.03 0.0299494 0.0260903 152 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 2.73 vpr 62.93 MiB -1 -1 0.19 18476 1 0.03 -1 -1 30188 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64444 32 32 387 315 1 189 89 17 17 289 -1 unnamed_device 23.8 MiB 0.15 1136 14147 4526 7649 1972 62.9 MiB 0.16 0.00 4.38816 -135.074 -4.38816 4.38816 0.32 0.000743004 0.000687682 0.0564022 0.052172 -1 -1 -1 -1 30 2565 21 6.64007e+06 313950 526063. 1820.29 0.59 0.145234 0.128316 22546 126617 -1 2247 16 1212 2170 142450 32357 3.63163 3.63163 -128.953 -3.63163 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0246587 0.0216156 141 77 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 2.63 vpr 63.07 MiB -1 -1 0.22 18120 1 0.03 -1 -1 30300 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 32 32 251 219 1 140 94 17 17 289 -1 unnamed_device 23.3 MiB 0.08 923 15643 4702 9042 1899 63.1 MiB 0.13 0.00 3.5543 -104.7 -3.5543 3.5543 0.32 0.00055848 0.000519887 0.0433436 0.0403444 -1 -1 -1 -1 28 1834 21 6.64007e+06 376740 500653. 1732.36 0.56 0.108027 0.0957526 21970 115934 -1 1668 22 937 1393 89639 21079 2.65657 2.65657 -97.5617 -2.65657 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0239942 0.0208508 101 23 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 2.67 vpr 63.50 MiB -1 -1 0.16 18272 1 0.03 -1 -1 30040 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65020 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 23.9 MiB 0.19 1003 17023 5521 9148 2354 63.5 MiB 0.17 0.00 4.05053 -136.563 -4.05053 4.05053 0.32 0.000667134 0.000619094 0.0589093 0.0547082 -1 -1 -1 -1 32 2363 20 6.64007e+06 339066 554710. 1919.41 0.56 0.140709 0.125069 22834 132086 -1 2016 20 1250 1804 125844 29633 3.39003 3.39003 -130.188 -3.39003 0 0 701300. 2426.64 0.03 0.07 0.09 -1 -1 0.03 0.02694 0.0234839 133 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 2.84 vpr 62.91 MiB -1 -1 0.26 18464 1 0.03 -1 -1 30344 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64416 32 32 387 293 1 234 99 17 17 289 -1 unnamed_device 24.0 MiB 0.21 1435 16059 4481 10134 1444 62.9 MiB 0.17 0.00 5.58406 -162.308 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27017 2.85617 2.85617 -116.634 -2.85617 0 0 701300. 2426.64 0.03 0.07 0.10 -1 -1 0.03 0.0294348 0.0256088 141 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 2.47 vpr 62.55 MiB -1 -1 0.24 18040 1 0.03 -1 -1 30292 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64052 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 23.5 MiB 0.05 787 15647 4513 8348 2786 62.6 MiB 0.13 0.00 3.51327 -106.246 -3.51327 3.51327 0.32 0.000603837 0.000561213 0.0453604 0.0421794 -1 -1 -1 -1 32 1767 19 6.64007e+06 414414 554710. 1919.41 0.51 0.113315 0.100197 22834 132086 -1 1434 19 732 1177 64731 16326 2.73257 2.73257 -98.3112 -2.73257 0 0 701300. 2426.64 0.03 0.04 0.12 -1 -1 0.03 0.0169393 0.0148555 111 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 3.53 vpr 63.23 MiB -1 -1 0.26 18632 1 0.03 -1 -1 30244 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64744 32 32 431 332 1 235 97 17 17 289 -1 unnamed_device 24.4 MiB 0.31 1370 17635 5043 10114 2478 63.2 MiB 0.21 0.00 6.37067 -183.955 -6.37067 6.37067 0.32 0.000827281 0.000769095 0.0686146 0.0637394 -1 -1 -1 -1 26 3739 28 6.64007e+06 414414 477104. 1650.88 1.06 0.183963 0.163024 21682 110474 -1 2914 23 2106 3156 231468 52338 5.05174 5.05174 -171.67 -5.05174 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0364787 0.031749 177 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 2.78 vpr 62.80 MiB -1 -1 0.24 18536 1 0.03 -1 -1 30456 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 32 32 336 268 1 174 102 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1059 19142 5710 10959 2473 62.8 MiB 0.17 0.00 4.53287 -137.071 -4.53287 4.53287 0.35 0.000694142 0.000645825 0.0585836 0.0543714 -1 -1 -1 -1 32 2159 21 6.64007e+06 477204 554710. 1919.41 0.56 0.141425 0.1254 22834 132086 -1 1899 16 1017 1621 90851 21605 3.65443 3.65443 -127.571 -3.65443 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0232201 0.0203952 136 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 2.57 vpr 62.96 MiB -1 -1 0.21 17880 1 0.05 -1 -1 30276 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64468 32 32 231 199 1 140 93 17 17 289 -1 unnamed_device 23.4 MiB 0.06 697 14793 4064 8312 2417 63.0 MiB 0.12 0.00 3.58247 -96.388 -3.58247 3.58247 0.34 0.000536007 0.000498696 0.0399856 0.0372164 -1 -1 -1 -1 30 1597 22 6.64007e+06 364182 526063. 1820.29 0.51 0.104438 0.0921129 22546 126617 -1 1300 17 603 1018 57376 14793 2.68557 2.68557 -89.2135 -2.68557 0 0 666494. 2306.21 0.03 0.05 0.09 -1 -1 0.03 0.0188683 0.0164977 103 3 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.72 vpr 63.45 MiB -1 -1 0.13 18472 1 0.03 -1 -1 30204 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 23.8 MiB 0.10 1247 19624 5520 11864 2240 63.4 MiB 0.19 0.00 5.68826 -140.03 -5.68826 5.68826 0.39 0.000705253 0.000655769 0.0593179 0.0551102 -1 -1 -1 -1 32 2366 18 6.64007e+06 502320 554710. 1919.41 0.54 0.139797 0.12415 22834 132086 -1 2129 14 824 1693 109078 25009 4.42708 4.42708 -129.323 -4.42708 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.021665 0.0190537 147 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.60 vpr 62.49 MiB -1 -1 0.22 17892 1 0.03 -1 -1 30152 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63992 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 23.2 MiB 0.07 838 15831 5106 8362 2363 62.5 MiB 0.13 0.00 3.5273 -107.609 -3.5273 3.5273 0.34 0.000557504 0.000519197 0.0480485 0.0446917 -1 -1 -1 -1 28 1874 20 6.64007e+06 288834 500653. 1732.36 0.55 0.114684 0.101665 21970 115934 -1 1689 20 1084 1860 116033 27873 2.77177 2.77177 -103.603 -2.77177 0 0 612192. 2118.31 0.03 0.06 0.11 -1 -1 0.03 0.0221893 0.0192968 107 3 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 2.88 vpr 62.60 MiB -1 -1 0.26 18212 1 0.02 -1 -1 30088 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 23.5 MiB 0.11 893 14252 4195 7695 2362 62.6 MiB 0.12 0.00 4.06561 -110.624 -4.06561 4.06561 0.32 0.000598189 0.000554889 0.0387015 0.0359501 -1 -1 -1 -1 28 2003 16 6.64007e+06 477204 500653. 1732.36 0.52 0.105135 0.0927138 21970 115934 -1 1666 21 1086 2090 130293 30391 2.82057 2.82057 -103.094 -2.82057 0 0 612192. 2118.31 0.03 0.07 0.13 -1 -1 0.03 0.0242583 0.0209963 110 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 2.80 vpr 62.91 MiB -1 -1 0.23 18388 1 0.03 -1 -1 30260 -1 -1 32 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64424 29 32 355 287 1 198 93 17 17 289 -1 unnamed_device 23.9 MiB 0.21 964 10173 2395 7060 718 62.9 MiB 0.11 0.00 4.65946 -131.109 -4.65946 4.65946 0.31 0.000693587 0.000645337 0.0360007 0.0334599 -1 -1 -1 -1 28 2771 28 6.64007e+06 401856 500653. 1732.36 0.68 0.125412 0.10974 21970 115934 -1 2174 20 1456 2237 139279 35165 3.62642 3.62642 -121.356 -3.62642 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0276567 0.0241107 146 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 2.60 vpr 62.84 MiB -1 -1 0.17 18284 1 0.03 -1 -1 30432 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64348 32 32 358 289 1 175 91 17 17 289 -1 unnamed_device 23.8 MiB 0.11 925 11719 2758 8119 842 62.8 MiB 0.12 0.00 4.42033 -138.276 -4.42033 4.42033 0.32 0.00071589 0.000664168 0.0433359 0.0402562 -1 -1 -1 -1 32 2161 23 6.64007e+06 339066 554710. 1919.41 0.57 0.129395 0.113987 22834 132086 -1 1727 20 1284 1944 114196 28932 3.78702 3.78702 -131.455 -3.78702 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0279344 0.02439 135 54 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 2.92 vpr 62.80 MiB -1 -1 0.21 18364 1 0.03 -1 -1 30232 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1091 11798 3080 7487 1231 62.8 MiB 0.13 0.00 4.78258 -142.686 -4.78258 4.78258 0.32 0.000714923 0.00066408 0.0396764 0.0368336 -1 -1 -1 -1 32 2192 17 6.64007e+06 426972 554710. 1919.41 0.80 0.12021 0.105957 22834 132086 -1 2011 16 897 1626 93283 22441 3.62362 3.62362 -128.218 -3.62362 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0237017 0.020821 136 51 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.70 vpr 62.63 MiB -1 -1 0.23 18024 1 0.03 -1 -1 30240 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64136 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 23.5 MiB 0.22 888 6701 1459 4931 311 62.6 MiB 0.08 0.00 4.75515 -130.083 -4.75515 4.75515 0.32 0.00061059 0.000568906 0.023214 0.021603 -1 -1 -1 -1 32 1842 19 6.64007e+06 276276 554710. 1919.41 0.51 0.0918828 0.0803618 22834 132086 -1 1618 15 639 896 58501 14060 3.29883 3.29883 -115.297 -3.29883 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0190421 0.0167372 107 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 3.10 vpr 63.02 MiB -1 -1 0.24 18248 1 0.03 -1 -1 30368 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64532 31 32 319 272 1 169 88 17 17 289 -1 unnamed_device 23.9 MiB 0.18 793 16078 4554 9333 2191 63.0 MiB 0.15 0.00 4.00036 -122.569 -4.00036 4.00036 0.35 0.000662037 0.000616691 0.0553256 0.0514457 -1 -1 -1 -1 26 2534 43 6.64007e+06 313950 477104. 1650.88 0.88 0.155968 0.137486 21682 110474 -1 1828 21 1216 1787 118458 32053 3.24903 3.24903 -118.128 -3.24903 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0261712 0.0227742 117 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 2.80 vpr 63.27 MiB -1 -1 0.23 18488 1 0.03 -1 -1 30384 -1 -1 36 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64788 30 32 329 273 1 166 98 17 17 289 -1 unnamed_device 23.5 MiB 0.10 943 16973 4825 9365 2783 63.3 MiB 0.16 0.00 3.65867 -98.2101 -3.65867 3.65867 0.36 0.000510479 0.000470115 0.0491293 0.0452299 -1 -1 -1 -1 26 2242 21 6.64007e+06 452088 477104. 1650.88 0.67 0.122474 0.109111 21682 110474 -1 1867 18 917 1784 103434 25819 2.77377 2.77377 -96.2306 -2.77377 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0239279 0.0208916 128 57 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 2.56 vpr 62.76 MiB -1 -1 0.22 18036 1 0.03 -1 -1 30368 -1 -1 39 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 23.6 MiB 0.07 826 16971 4935 9183 2853 62.8 MiB 0.13 0.00 4.21293 -101.023 -4.21293 4.21293 0.33 0.000596135 0.000555002 0.0460918 0.0427488 -1 -1 -1 -1 28 1907 22 6.64007e+06 489762 500653. 1732.36 0.56 0.117192 0.10326 21970 115934 -1 1601 16 895 1627 90491 22777 3.47223 3.47223 -98.8073 -3.47223 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.0195628 0.0171324 122 27 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 2.69 vpr 62.73 MiB -1 -1 0.24 18280 1 0.03 -1 -1 30360 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64232 30 32 317 269 1 152 84 17 17 289 -1 unnamed_device 23.6 MiB 0.13 892 13809 4602 7006 2201 62.7 MiB 0.14 0.00 3.90078 -115.622 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64380 32 32 385 308 1 182 101 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1057 12556 3111 8883 562 62.9 MiB 0.13 0.00 4.57304 -141.272 -4.57304 4.57304 0.31 0.000744694 0.000690509 0.0434462 0.0401677 -1 -1 -1 -1 32 2404 16 6.64007e+06 464646 554710. 1919.41 0.58 0.125349 0.110487 22834 132086 -1 2052 22 1123 2086 137496 32021 3.42483 3.42483 -130.344 -3.42483 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.029294 0.0260026 143 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 3.17 vpr 63.51 MiB -1 -1 0.26 18504 1 0.03 -1 -1 30284 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 32 32 387 309 1 190 107 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1171 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64272 31 32 340 275 1 196 98 17 17 289 -1 unnamed_device 23.8 MiB 0.19 1123 13148 3656 8360 1132 62.8 MiB 0.13 0.00 5.23915 -149.423 -5.23915 5.23915 0.31 0.000682659 0.00063482 0.0427424 0.0397167 -1 -1 -1 -1 32 2371 21 6.64007e+06 439530 554710. 1919.41 0.54 0.123323 0.108794 22834 132086 -1 2007 20 1118 1785 91779 24235 4.30908 4.30908 -140.1 -4.30908 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0272733 0.0238268 151 47 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 2.71 vpr 62.93 MiB -1 -1 0.16 18440 1 0.03 -1 -1 30492 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64440 30 32 377 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64492 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 23.9 MiB 0.20 1044 14235 4068 7633 2534 63.0 MiB 0.16 0.00 4.71503 -140.381 -4.71503 4.71503 0.32 0.000736638 0.000684303 0.0542958 0.0503407 -1 -1 -1 -1 32 2187 20 6.64007e+06 439530 554710. 1919.41 0.64 0.16213 0.14341 22834 132086 -1 1906 20 1054 1793 106697 26383 3.63163 3.63163 -128.238 -3.63163 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0285345 0.0249014 135 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 2.91 vpr 62.84 MiB -1 -1 0.16 18280 1 0.03 -1 -1 30280 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64344 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 23.8 MiB 0.15 1159 10979 2643 7096 1240 62.8 MiB 0.13 0.00 4.8332 -152.333 -4.8332 4.8332 0.31 0.000764668 0.000709401 0.0465756 0.0431972 -1 -1 -1 -1 32 2514 24 6.64007e+06 313950 554710. 1919.41 0.63 0.140961 0.124202 22834 132086 -1 2265 22 1721 2851 169988 41091 3.69343 3.69343 -141.542 -3.69343 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0324477 0.0282823 155 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 2.86 vpr 62.62 MiB -1 -1 0.23 18156 1 0.03 -1 -1 30408 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64128 32 32 269 231 1 170 89 17 17 289 -1 unnamed_device 23.6 MiB 0.19 1035 13157 3525 7788 1844 62.6 MiB 0.12 0.00 4.01361 -116.472 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65028 32 32 349 260 1 204 107 17 17 289 -1 unnamed_device 23.8 MiB 0.08 1267 17817 5114 10804 1899 63.5 MiB 0.17 0.00 5.50127 -148.27 -5.50127 5.50127 0.32 0.000728707 0.000677247 0.0534885 0.0496414 -1 -1 -1 -1 26 3165 21 6.64007e+06 539994 477104. 1650.88 0.75 0.150128 0.133373 21682 110474 -1 2620 21 1637 3007 196047 46131 4.58248 4.58248 -146.607 -4.58248 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0303632 0.0265432 162 3 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 2.47 vpr 63.33 MiB -1 -1 0.16 18544 1 0.03 -1 -1 30320 -1 -1 35 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64852 30 32 316 264 1 162 97 17 17 289 -1 unnamed_device 23.6 MiB 0.11 960 10531 2688 6948 895 63.3 MiB 0.10 0.00 3.53527 -104.629 -3.53527 3.53527 0.31 0.000642209 0.000597715 0.0327903 0.0304946 -1 -1 -1 -1 32 2029 21 6.64007e+06 439530 554710. 1919.41 0.53 0.108188 0.0949357 22834 132086 -1 1762 19 983 1688 92821 22824 2.84297 2.84297 -99.6625 -2.84297 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0302453 0.0267024 124 52 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 2.41 vpr 62.96 MiB -1 -1 0.21 18040 1 0.04 -1 -1 30284 -1 -1 25 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64472 27 32 255 219 1 132 84 17 17 289 -1 unnamed_device 23.4 MiB 0.06 787 11430 3535 6029 1866 63.0 MiB 0.09 0.00 3.4653 -96.8105 -3.4653 3.4653 0.31 0.000547949 0.000510433 0.0361061 0.0336224 -1 -1 -1 -1 26 1657 21 6.64007e+06 313950 477104. 1650.88 0.51 0.100455 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64180 32 32 331 280 1 174 87 17 17 289 -1 unnamed_device 23.5 MiB 0.29 989 13335 4742 6776 1817 62.7 MiB 0.13 0.00 4.37915 -137.641 -4.37915 4.37915 0.32 0.000658109 0.000611873 0.048245 0.0448417 -1 -1 -1 -1 32 1903 19 6.64007e+06 288834 554710. 1919.41 0.52 0.124693 0.110299 22834 132086 -1 1693 13 628 883 56758 13715 3.17522 3.17522 -121.439 -3.17522 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0196211 0.017333 130 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 2.90 vpr 63.40 MiB -1 -1 0.24 18384 1 0.03 -1 -1 30344 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1105 13092 3416 8740 936 63.4 MiB 0.13 0.00 5.28888 -136.917 -5.28888 5.28888 0.32 0.000682744 0.000636151 0.0406021 0.0377399 -1 -1 -1 -1 26 2483 21 6.64007e+06 452088 477104. 1650.88 0.57 0.121401 0.10708 21682 110474 -1 2105 18 1009 1726 98465 23986 3.85982 3.85982 -125.513 -3.85982 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0247052 0.0216352 133 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 3.03 vpr 63.57 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30372 -1 -1 38 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65096 31 32 373 294 1 196 101 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1122 12321 3316 8274 731 63.6 MiB 0.13 0.00 4.92332 -128.094 -4.92332 4.92332 0.34 0.00073579 0.000681292 0.0411424 0.0381693 -1 -1 -1 -1 26 2511 21 6.64007e+06 477204 477104. 1650.88 0.52 0.127987 0.112686 21682 110474 -1 2210 19 1199 1943 114142 28132 3.83382 3.83382 -125.259 -3.83382 0 0 585099. 2024.56 0.03 0.07 0.08 -1 -1 0.03 0.0283169 0.0247367 151 50 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 2.79 vpr 63.06 MiB -1 -1 0.21 18440 1 0.03 -1 -1 30380 -1 -1 36 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 30 32 325 268 1 171 98 17 17 289 -1 unnamed_device 23.9 MiB 0.12 937 16973 5746 8109 3118 63.1 MiB 0.15 0.00 3.65167 -103.348 -3.65167 3.65167 0.31 0.000656815 0.000608992 0.0517459 0.048035 -1 -1 -1 -1 30 2391 26 6.64007e+06 452088 526063. 1820.29 0.71 0.136006 0.120034 22546 126617 -1 1842 21 1098 2007 113299 28167 2.97317 2.97317 -100.808 -2.97317 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 32 32 386 307 1 195 106 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1118 16856 4639 9867 2350 63.5 MiB 0.19 0.00 4.29207 -131.028 -4.29207 4.29207 0.31 0.000745147 0.000691805 0.0590137 0.0547729 -1 -1 -1 -1 28 2771 25 6.64007e+06 527436 500653. 1732.36 0.64 0.152811 0.135193 21970 115934 -1 2232 22 1473 2458 171773 41912 3.24756 3.24756 -122.119 -3.24756 0 0 612192. 2118.31 0.03 0.09 0.10 -1 -1 0.03 0.0326766 0.0284409 151 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 2.35 vpr 62.91 MiB -1 -1 0.23 18128 1 0.02 -1 -1 30284 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64416 29 32 269 229 1 129 80 17 17 289 -1 unnamed_device 23.4 MiB 0.06 778 14184 4385 8482 1317 62.9 MiB 0.12 0.00 4.07075 -112.667 -4.07075 4.07075 0.32 0.000580699 0.000540923 0.0493007 0.0459016 -1 -1 -1 -1 28 1504 20 6.64007e+06 238602 500653. 1732.36 0.47 0.116766 0.103529 21970 115934 -1 1377 18 774 1155 75021 18193 2.75077 2.75077 -97.232 -2.75077 0 0 612192. 2118.31 0.03 0.05 0.07 -1 -1 0.03 0.020975 0.0182859 93 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 2.71 vpr 62.80 MiB -1 -1 0.24 18332 1 0.03 -1 -1 30448 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 32 32 310 266 1 176 89 17 17 289 -1 unnamed_device 23.7 MiB 0.18 1008 13949 3776 8315 1858 62.8 MiB 0.13 0.00 4.57978 -129.405 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x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 31 32 373 300 1 181 103 17 17 289 -1 unnamed_device 24.2 MiB 0.12 994 11671 2882 8064 725 63.2 MiB 0.12 0.00 4.09378 -121.668 -4.09378 4.09378 0.32 0.000726427 0.000674778 0.0377137 0.034953 -1 -1 -1 -1 26 2376 23 6.64007e+06 502320 477104. 1650.88 0.55 0.125439 0.109976 21682 110474 -1 1958 22 1532 2565 145610 36094 3.06217 3.06217 -117.244 -3.06217 0 0 585099. 2024.56 0.05 0.08 0.10 -1 -1 0.05 0.0315397 0.0275332 141 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 2.73 vpr 62.66 MiB -1 -1 0.23 18040 1 0.03 -1 -1 30328 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64164 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 23.7 MiB 0.16 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64152 32 32 290 244 1 177 90 17 17 289 -1 unnamed_device 23.5 MiB 0.19 925 8532 1785 6264 483 62.6 MiB 0.09 0.00 4.36984 -131.165 -4.36984 4.36984 0.31 0.00061324 0.000570288 0.0280339 0.026075 -1 -1 -1 -1 28 2708 24 6.64007e+06 326508 500653. 1732.36 0.64 0.104096 0.0910882 21970 115934 -1 1954 20 1359 2003 122646 30886 3.38923 3.38923 -122.625 -3.38923 0 0 612192. 2118.31 0.02 0.04 0.07 -1 -1 0.02 0.0135228 0.0119375 124 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 2.77 vpr 62.77 MiB -1 -1 0.23 18380 1 0.03 -1 -1 30208 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64276 32 32 318 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65200 32 32 412 334 1 190 101 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1132 12791 3491 8287 1013 63.7 MiB 0.15 0.00 4.42516 -144.482 -4.42516 4.42516 0.32 0.000777421 0.000722358 0.0449905 0.0417837 -1 -1 -1 -1 32 2175 23 6.64007e+06 464646 554710. 1919.41 0.56 0.138643 0.121972 22834 132086 -1 1928 20 1161 1813 106830 26306 3.76183 3.76183 -135.978 -3.76183 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0308308 0.0269198 146 90 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 2.52 vpr 62.92 MiB -1 -1 0.16 18316 1 0.03 -1 -1 30184 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64428 32 32 376 318 1 155 82 17 17 289 -1 unnamed_device 23.7 MiB 0.14 961 14678 5153 7870 1655 62.9 MiB 0.15 0.00 3.5251 -126.262 -3.5251 3.5251 0.32 0.000716805 0.000665017 0.061699 0.0573065 -1 -1 -1 -1 32 1789 17 6.64007e+06 226044 554710. 1919.41 0.53 0.141368 0.125423 22834 132086 -1 1636 19 1061 1511 101615 23343 2.65957 2.65957 -115.251 -2.65957 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0272319 0.0237407 116 96 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.68 vpr 63.50 MiB -1 -1 0.15 18392 1 0.03 -1 -1 30252 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1040 16059 4498 9094 2467 63.5 MiB 0.16 0.00 4.08563 -122.248 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2.45 vpr 62.72 MiB -1 -1 0.23 18136 1 0.03 -1 -1 30324 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64228 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 23.3 MiB 0.06 689 6731 1618 4756 357 62.7 MiB 0.08 0.00 4.09512 -115.35 -4.09512 4.09512 0.32 0.000599086 0.000557828 0.0252094 0.023468 -1 -1 -1 -1 30 1441 21 6.64007e+06 238602 526063. 1820.29 0.50 0.0996073 0.0873472 22546 126617 -1 1294 18 678 1174 70897 17025 2.86577 2.86577 -104.274 -2.86577 0 0 666494. 2306.21 0.03 0.05 0.11 -1 -1 0.03 0.0219962 0.0192113 95 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 2.63 vpr 62.67 MiB -1 -1 0.22 18180 1 0.03 -1 -1 30216 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64172 32 32 296 247 1 157 90 17 17 289 -1 unnamed_device 23.6 MiB 0.08 942 12552 3467 7974 1111 62.7 MiB 0.12 0.00 3.49427 -115.718 -3.49427 3.49427 0.32 0.000632151 0.000578248 0.041451 0.0384616 -1 -1 -1 -1 32 2080 20 6.64007e+06 326508 554710. 1919.41 0.62 0.114609 0.101229 22834 132086 -1 1868 22 1056 2009 127408 29897 2.69957 2.69957 -109.166 -2.69957 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0268929 0.0233414 119 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_126.v common 2.61 vpr 62.79 MiB -1 -1 0.22 18028 1 0.03 -1 -1 30192 -1 -1 31 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64296 25 32 216 194 1 122 88 17 17 289 -1 unnamed_device 23.3 MiB 0.06 601 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64956 30 32 363 293 1 196 92 17 17 289 -1 unnamed_device 23.7 MiB 0.09 1161 17066 4950 10267 1849 63.4 MiB 0.18 0.00 4.92316 -142.534 -4.92316 4.92316 0.32 0.000711495 0.000661377 0.0607483 0.05633 -1 -1 -1 -1 32 2317 19 6.65987e+06 380340 554710. 1919.41 0.56 0.14224 0.126171 22834 132086 -1 2201 20 1285 1969 141789 31778 3.96643 3.96643 -135.327 -3.96643 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0286017 0.0250073 147 63 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 2.92 vpr 62.58 MiB -1 -1 0.23 18252 1 0.03 -1 -1 30424 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 32 32 299 247 1 188 95 17 17 289 -1 unnamed_device 23.4 MiB 0.10 1005 7223 1515 5389 319 62.6 MiB 0.08 0.00 4.5072 -115.093 -4.5072 4.5072 0.32 0.000638459 0.000593954 0.023343 0.021723 -1 -1 -1 -1 26 2482 19 6.65987e+06 393018 477104. 1650.88 0.57 0.096452 0.084355 21682 110474 -1 2175 22 1225 1807 128173 38231 3.65077 3.65077 -115.591 -3.65077 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0283391 0.0248207 129 29 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.43 vpr 63.12 MiB -1 -1 0.17 18364 1 0.04 -1 -1 30272 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64640 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 23.3 MiB 0.04 1008 16445 5063 9076 2306 63.1 MiB 0.16 0.00 4.28955 -115.789 -4.28955 4.28955 0.31 0.000630792 0.000586242 0.0527628 0.0490015 -1 -1 -1 -1 32 2107 21 6.65987e+06 393018 554710. 1919.41 0.54 0.127475 0.112807 22834 132086 -1 1923 24 1162 2468 162514 37920 3.42191 3.42191 -111.417 -3.42191 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0300343 0.0260368 132 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 2.88 vpr 62.64 MiB -1 -1 0.23 18404 1 0.03 -1 -1 30412 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64144 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 23.6 MiB 0.06 926 17066 4722 10092 2252 62.6 MiB 0.18 0.00 4.32246 -124.084 -4.32246 4.32246 0.31 0.000682381 0.000633432 0.0584903 0.0542653 -1 -1 -1 -1 28 2659 35 6.65987e+06 354984 500653. 1732.36 0.85 0.156528 0.138194 21970 115934 -1 1952 22 1359 2592 155691 39529 3.65631 3.65631 -123.935 -3.65631 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0292856 0.0255564 134 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 2.51 vpr 62.75 MiB -1 -1 0.15 18452 1 0.03 -1 -1 30268 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64252 32 32 366 295 1 189 103 17 17 289 -1 unnamed_device 23.6 MiB 0.08 1006 10707 2558 7056 1093 62.7 MiB 0.11 0.00 3.2981 -110.874 -3.2981 3.2981 0.32 0.000715102 0.000664192 0.0344872 0.0320276 -1 -1 -1 -1 32 2059 17 6.65987e+06 494442 554710. 1919.41 0.52 0.114776 0.10094 22834 132086 -1 1766 16 1009 1653 81293 21469 2.93011 2.93011 -107.664 -2.93011 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0244838 0.0214969 145 58 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.33 vpr 62.35 MiB -1 -1 0.16 18212 1 0.03 -1 -1 30572 -1 -1 21 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63844 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 23.0 MiB 0.05 662 8508 2183 5532 793 62.3 MiB 0.08 0.00 3.64612 -97.2036 -3.64612 3.64612 0.32 0.000556352 0.000518731 0.02948 0.0274761 -1 -1 -1 -1 26 1488 20 6.65987e+06 266238 477104. 1650.88 0.46 0.0948889 0.0832974 21682 110474 -1 1285 19 839 1443 84061 21350 2.55211 2.55211 -89.8292 -2.55211 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0217986 0.0189775 97 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.55 vpr 62.41 MiB -1 -1 0.22 17868 1 0.03 -1 -1 30072 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63904 31 32 271 219 1 162 98 17 17 289 -1 unnamed_device 23.4 MiB 0.05 879 17198 5694 8745 2759 62.4 MiB 0.14 0.00 3.28184 -95.5565 -3.28184 3.28184 0.36 0.000595736 0.000552841 0.0478346 0.044364 -1 -1 -1 -1 32 2096 17 6.65987e+06 443730 554710. 1919.41 0.52 0.110623 0.0981322 22834 132086 -1 1775 20 943 1802 114464 28225 2.55445 2.55445 -90.648 -2.55445 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0241442 0.0210605 123 4 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 2.40 vpr 62.57 MiB -1 -1 0.15 18384 1 0.03 -1 -1 30052 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 31 32 317 271 1 168 87 17 17 289 -1 unnamed_device 23.4 MiB 0.09 925 6807 1453 4944 410 62.6 MiB 0.08 0.00 3.3699 -114.313 -3.3699 3.3699 0.32 0.000493922 0.000454414 0.024486 0.0227415 -1 -1 -1 -1 28 2084 19 6.65987e+06 304272 500653. 1732.36 0.51 0.0981972 0.0857413 21970 115934 -1 1840 15 921 1353 95741 23607 2.83031 2.83031 -109.983 -2.83031 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0207326 0.0181803 117 64 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.56 vpr 62.51 MiB -1 -1 0.22 18156 1 0.03 -1 -1 30016 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64008 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 23.4 MiB 0.09 817 6383 1432 4490 461 62.5 MiB 0.08 0.00 3.76232 -120.722 -3.76232 3.76232 0.32 0.000636848 0.000593635 0.024309 0.0226498 -1 -1 -1 -1 26 2054 21 6.65987e+06 240882 477104. 1650.88 0.54 0.0984567 0.0861078 21682 110474 -1 1799 19 1068 1672 105244 26336 2.74751 2.74751 -112.355 -2.74751 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.024046 0.0210051 115 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 2.55 vpr 62.52 MiB -1 -1 0.20 18352 1 0.03 -1 -1 30424 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 23.4 MiB 0.12 855 11106 3144 6574 1388 62.5 MiB 0.10 0.00 3.77152 -110.328 -3.77152 3.77152 0.34 0.000678385 0.000627002 0.0360956 0.0334026 -1 -1 -1 -1 32 1610 20 6.65987e+06 240882 554710. 1919.41 0.50 0.106565 0.093619 22834 132086 -1 1486 18 705 1168 66043 16527 2.64251 2.64251 -96.0214 -2.64251 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0227846 0.019903 101 63 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 2.74 vpr 62.46 MiB -1 -1 0.23 18072 1 0.03 -1 -1 30144 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63964 32 32 276 237 1 167 87 17 17 289 -1 unnamed_device 23.4 MiB 0.09 923 15063 4954 7940 2169 62.5 MiB 0.14 0.00 3.60095 -114.988 -3.60095 3.60095 0.32 0.000589529 0.000548359 0.048608 0.0452215 -1 -1 -1 -1 28 2245 30 6.65987e+06 291594 500653. 1732.36 0.75 0.136128 0.120028 21970 115934 -1 1857 21 1021 1396 110915 26979 3.05825 3.05825 -111.367 -3.05825 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.024645 0.0214555 111 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 2.79 vpr 62.86 MiB -1 -1 0.24 18380 1 0.08 -1 -1 30308 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64372 32 32 344 272 1 202 93 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1172 12063 3279 7731 1053 62.9 MiB 0.16 0.00 4.32078 -139.492 -4.32078 4.32078 0.33 0.000703373 0.000645846 0.0505267 0.04694 -1 -1 -1 -1 32 2466 23 6.65987e+06 367662 554710. 1919.41 0.56 0.135329 0.119646 22834 132086 -1 2158 23 1534 2364 144012 35379 3.01857 3.01857 -118.122 -3.01857 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0312134 0.027204 147 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 2.74 vpr 62.80 MiB -1 -1 0.24 18376 1 0.03 -1 -1 30196 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64308 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 23.8 MiB 0.10 971 17873 5392 9032 3449 62.8 MiB 0.19 0.00 4.50383 -130.941 -4.50383 4.50383 0.33 0.000717123 0.000666062 0.0669834 0.0620637 -1 -1 -1 -1 32 2088 18 6.65987e+06 431052 554710. 1919.41 0.57 0.148521 0.131949 22834 132086 -1 1825 20 1420 2352 139941 35041 3.57251 3.57251 -121.811 -3.57251 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0286098 0.0250144 139 61 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.47 vpr 62.38 MiB -1 -1 0.22 18052 1 0.03 -1 -1 30508 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63872 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 23.3 MiB 0.10 694 9600 2464 6430 706 62.4 MiB 0.08 0.00 2.92253 -85.631 -2.92253 2.92253 0.32 0.000543549 0.000506216 0.0305384 0.0284177 -1 -1 -1 -1 26 1711 20 6.65987e+06 291594 477104. 1650.88 0.48 0.0942953 0.0827929 21682 110474 -1 1601 22 1045 1797 119370 29179 2.51431 2.51431 -87.2887 -2.51431 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0234018 0.0202863 103 27 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 2.88 vpr 63.29 MiB -1 -1 0.27 18480 1 0.03 -1 -1 30296 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 32 32 370 297 1 183 91 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1152 16003 4822 9403 1778 63.3 MiB 0.16 0.00 4.09572 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64080 31 32 291 243 1 171 88 17 17 289 -1 unnamed_device 23.4 MiB 0.20 786 13738 3441 7180 3117 62.6 MiB 0.12 0.00 4.80308 -136.113 -4.80308 4.80308 0.31 0.000610132 0.000568245 0.0452547 0.0421109 -1 -1 -1 -1 32 2211 46 6.65987e+06 316950 554710. 1919.41 0.80 0.142447 0.124997 22834 132086 -1 1576 21 899 1285 88683 23465 3.84671 3.84671 -129.866 -3.84671 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0258407 0.0225526 127 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 3.39 vpr 63.26 MiB -1 -1 0.23 18456 1 0.03 -1 -1 30396 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64776 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 23.6 MiB 0.07 1092 18196 6057 9791 2348 63.3 MiB 0.17 0.00 4.25196 -133.154 -4.25196 4.25196 0.31 0.000696776 0.000647631 0.0565156 0.0524726 -1 -1 -1 -1 28 2596 21 6.65987e+06 469086 500653. 1732.36 0.78 0.140877 0.125047 21970 115934 -1 2180 20 1359 2318 167321 39385 3.69683 3.69683 -128.953 -3.69683 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0280309 0.0245652 140 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 3.33 vpr 62.74 MiB -1 -1 0.25 18336 1 0.03 -1 -1 30284 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64248 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 23.9 MiB 0.10 1229 17591 4978 10084 2529 62.7 MiB 0.19 0.00 4.43635 -136.819 -4.43635 4.43635 0.31 0.000723595 0.000672722 0.061937 0.0574339 -1 -1 -1 -1 32 2470 18 6.65987e+06 393018 554710. 1919.41 0.54 0.143942 0.127773 22834 132086 -1 2229 19 1285 1974 116123 28589 3.51771 3.51771 -123.874 -3.51771 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0285167 0.0249981 151 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 2.43 vpr 62.46 MiB -1 -1 0.14 18020 1 0.02 -1 -1 30524 -1 -1 20 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63960 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 23.1 MiB 0.07 431 10536 3837 3941 2758 62.5 MiB 0.07 0.00 2.35224 -64.6209 -2.35224 2.35224 0.32 0.000426133 0.000395077 0.0283186 0.0262801 -1 -1 -1 -1 28 1419 31 6.65987e+06 253560 500653. 1732.36 0.63 0.086015 0.075317 21970 115934 -1 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 32 32 300 245 1 165 95 17 17 289 -1 unnamed_device 23.5 MiB 0.09 898 10247 2366 7380 501 62.6 MiB 0.10 0.00 4.32789 -118.536 -4.32789 4.32789 0.32 0.000639255 0.000594623 0.0326551 0.0303542 -1 -1 -1 -1 26 2424 21 6.65987e+06 393018 477104. 1650.88 0.66 0.109099 0.0958696 21682 110474 -1 1959 20 1096 1916 134943 33891 3.50931 3.50931 -114.521 -3.50931 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0257508 0.0224904 126 24 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 2.57 vpr 62.66 MiB -1 -1 0.18 17776 1 0.03 -1 -1 30360 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64164 32 32 297 233 1 177 103 17 17 289 -1 unnamed_device 23.7 MiB 0.06 986 15527 4364 9095 2068 62.7 MiB 0.15 0.00 3.58941 -102.662 -3.58941 3.58941 0.32 0.00064423 0.000597693 0.0438764 0.0407061 -1 -1 -1 -1 32 2052 20 6.65987e+06 494442 554710. 1919.41 0.53 0.118788 0.104869 22834 132086 -1 1757 21 995 1984 121842 28850 2.78377 2.78377 -93.9889 -2.78377 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0253086 0.0224502 136 3 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 3.09 vpr 63.31 MiB -1 -1 0.15 18280 1 0.03 -1 -1 30412 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 32 32 338 277 1 179 99 17 17 289 -1 unnamed_device 23.7 MiB 0.08 1132 18339 5277 10722 2340 63.3 MiB 0.17 0.00 4.42603 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63936 32 32 253 210 1 154 85 17 17 289 -1 unnamed_device 23.4 MiB 0.07 733 14035 5318 6638 2079 62.4 MiB 0.12 0.00 3.67009 -108.082 -3.67009 3.67009 0.32 0.000572926 0.000532536 0.0451769 0.0419649 -1 -1 -1 -1 32 1862 31 6.65987e+06 266238 554710. 1919.41 0.57 0.122063 0.107575 22834 132086 -1 1508 20 909 1486 90599 23830 2.64951 2.64951 -100.091 -2.64951 0 0 701300. 2426.64 0.04 0.06 0.10 -1 -1 0.04 0.0273808 0.0243873 116 3 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 2.57 vpr 62.43 MiB -1 -1 0.24 18192 1 0.03 -1 -1 30544 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63928 31 32 271 231 1 148 96 17 17 289 -1 unnamed_device 23.3 MiB 0.06 765 8199 1674 6237 288 62.4 MiB 0.08 0.00 3.38101 -98.7431 -3.38101 3.38101 0.32 0.000579578 0.000540067 0.0238147 0.0221697 -1 -1 -1 -1 26 1967 21 6.65987e+06 418374 477104. 1650.88 0.55 0.0977505 0.0853359 21682 110474 -1 1633 20 906 1519 84512 22222 2.82071 2.82071 -102.673 -2.82071 0 0 585099. 2024.56 0.04 0.06 0.10 -1 -1 0.04 0.0264682 0.0233523 111 30 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 2.70 vpr 62.84 MiB -1 -1 0.23 18384 1 0.03 -1 -1 30436 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64352 29 32 291 250 1 153 92 17 17 289 -1 unnamed_device 23.7 MiB 0.10 919 13961 3585 8809 1567 62.8 MiB 0.12 0.00 3.21564 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fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 2.53 vpr 62.52 MiB -1 -1 0.22 18272 1 0.03 -1 -1 30232 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 23.4 MiB 0.09 916 12938 4123 6955 1860 62.5 MiB 0.12 0.00 4.11632 -122.804 -4.11632 4.11632 0.32 0.000592092 0.000550918 0.0429113 0.0399086 -1 -1 -1 -1 32 1802 19 6.65987e+06 291594 554710. 1919.41 0.50 0.112424 0.099407 22834 132086 -1 1621 21 899 1293 89858 21635 2.75411 2.75411 -103.631 -2.75411 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0251542 0.0219007 114 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 2.66 vpr 62.81 MiB -1 -1 0.25 18388 1 0.03 -1 -1 30428 -1 -1 29 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64316 31 32 370 297 1 186 92 17 17 289 -1 unnamed_device 23.7 MiB 0.10 962 14375 4628 7389 2358 62.8 MiB 0.15 0.00 4.01529 -116.343 -4.01529 4.01529 0.31 0.000715968 0.000664875 0.0525152 0.0487842 -1 -1 -1 -1 32 2097 20 6.65987e+06 367662 554710. 1919.41 0.55 0.136711 0.120978 22834 132086 -1 1740 19 953 1608 91219 23548 2.83077 2.83077 -103.661 -2.83077 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0283605 0.0250845 145 61 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 2.65 vpr 62.97 MiB -1 -1 0.26 18260 1 0.03 -1 -1 30408 -1 -1 36 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64480 31 32 377 302 1 234 99 17 17 289 -1 unnamed_device 24.1 MiB 0.07 1386 11043 2787 7293 963 63.0 MiB 0.13 0.00 5.91489 -170.972 -5.91489 5.91489 0.32 0.000736886 0.000685819 0.0385686 0.0358586 -1 -1 -1 -1 32 2873 20 6.65987e+06 456408 554710. 1919.41 0.57 0.124678 0.109747 22834 132086 -1 2486 19 1319 1924 126550 30073 4.39548 4.39548 -152.161 -4.39548 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0287112 0.0251583 178 64 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 3.22 vpr 63.42 MiB -1 -1 0.26 18348 1 0.03 -1 -1 30388 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64944 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 23.9 MiB 0.62 1238 16511 4791 9794 1926 63.4 MiB 0.18 0.00 4.89912 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63956 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 23.4 MiB 0.09 737 9536 2387 5857 1292 62.5 MiB 0.09 0.00 3.48098 -96.6191 -3.48098 3.48098 0.32 0.000575726 0.000535589 0.0306291 0.0284653 -1 -1 -1 -1 30 1612 20 6.65987e+06 291594 526063. 1820.29 0.52 0.0958834 0.0841792 22546 126617 -1 1405 22 877 1491 83669 20744 2.47931 2.47931 -90.4761 -2.47931 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0247778 0.0215726 104 28 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 3.00 vpr 62.80 MiB -1 -1 0.26 18284 1 0.03 -1 -1 30132 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 23.8 MiB 0.08 1249 13195 3658 8262 1275 62.8 MiB 0.14 0.00 4.79192 -144.824 -4.79192 4.79192 0.34 0.000683955 0.000635929 0.0433617 0.0402853 -1 -1 -1 -1 24 3134 28 6.65987e+06 431052 448715. 1552.65 0.88 0.138378 0.12188 21394 104001 -1 2453 22 1503 2172 141924 34169 4.03451 4.03451 -135.006 -4.03451 0 0 554710. 1919.41 0.02 0.07 0.11 -1 -1 0.02 0.0296631 0.0258945 149 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.75 vpr 62.68 MiB -1 -1 0.24 18408 1 0.03 -1 -1 30420 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64180 32 32 349 284 1 183 102 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1155 13906 3407 9168 1331 62.7 MiB 0.13 0.00 3.8576 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1165 2183 127461 31331 3.47345 3.47345 -112.519 -3.47345 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0280871 0.0244558 127 3 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 2.78 vpr 62.70 MiB -1 -1 0.25 18404 1 0.03 -1 -1 30280 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64204 32 32 353 287 1 198 94 17 17 289 -1 unnamed_device 23.6 MiB 0.17 1224 8827 1935 6242 650 62.7 MiB 0.11 0.00 4.61566 -135.209 -4.61566 4.61566 0.31 0.000712229 0.000661663 0.0318336 0.0295804 -1 -1 -1 -1 30 2511 23 6.65987e+06 380340 526063. 1820.29 0.53 0.117116 0.102706 22546 126617 -1 2136 19 928 1310 71774 17944 3.20951 3.20951 -118.608 -3.20951 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0274664 0.0240917 142 55 -1 -1 -1 -1 + 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 32 32 382 305 1 192 104 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1186 14744 3810 9393 1541 62.8 MiB 0.15 0.00 4.08875 -126.488 -4.08875 4.08875 0.32 0.000742546 0.000689999 0.0475827 0.0441969 -1 -1 -1 -1 26 2813 24 6.65987e+06 507120 477104. 1650.88 0.66 0.141553 0.124844 21682 110474 -1 2375 21 1537 2519 161666 39095 3.04491 3.04491 -117.668 -3.04491 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0308635 0.0269302 149 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 2.60 vpr 62.52 MiB -1 -1 0.22 17992 1 0.03 -1 -1 30320 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 23.4 MiB 0.09 1036 11932 2960 7977 995 62.5 MiB 0.11 0.00 3.95041 -117.901 -3.95041 3.95041 0.32 0.000629355 0.000583689 0.0352423 0.0326696 -1 -1 -1 -1 32 2001 21 6.65987e+06 456408 554710. 1919.41 0.54 0.112167 0.0985244 22834 132086 -1 1850 20 1003 1814 115866 27374 3.08765 3.08765 -108.602 -3.08765 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0250013 0.0219994 127 24 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 2.52 vpr 63.28 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30132 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64800 32 32 319 257 1 198 93 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1087 10383 2461 6851 1071 63.3 MiB 0.12 0.00 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64188 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 23.7 MiB 0.08 996 17023 5758 8918 2347 62.7 MiB 0.17 0.00 3.96847 -134.773 -3.96847 3.96847 0.32 0.000673933 0.000625952 0.0586522 0.0544351 -1 -1 -1 -1 28 2722 23 6.65987e+06 342306 500653. 1732.36 0.70 0.142328 0.126048 21970 115934 -1 2070 19 1306 1855 127035 31021 3.38897 3.38897 -128.298 -3.38897 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0258283 0.0225418 133 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 2.77 vpr 62.88 MiB -1 -1 0.24 18520 1 0.03 -1 -1 30352 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64392 32 32 387 293 1 234 99 17 17 289 -1 unnamed_device 23.9 MiB 0.11 1433 14463 4059 9245 1159 62.9 MiB 0.16 0.00 5.18108 -151.87 -5.18108 5.18108 0.32 0.000764555 0.000710159 0.0512314 0.0475868 -1 -1 -1 -1 32 3076 23 6.65987e+06 443730 554710. 1919.41 0.58 0.144273 0.127505 22834 132086 -1 2769 21 1634 2613 161131 38979 4.04551 4.04551 -142.419 -4.04551 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.032354 0.0283413 174 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 2.52 vpr 62.75 MiB -1 -1 0.24 18392 1 0.03 -1 -1 30380 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64256 32 32 340 270 1 181 102 17 17 289 -1 unnamed_device 23.7 MiB 0.08 1064 9622 2158 6803 661 62.8 MiB 0.10 0.00 4.25077 -131.82 -4.25077 4.25077 0.32 0.000689443 0.000641753 0.030528 0.0283813 -1 -1 -1 -1 26 2445 19 6.65987e+06 481764 477104. 1650.88 0.54 0.111197 0.0976738 21682 110474 -1 2100 20 1180 2009 122888 30587 2.98991 2.98991 -119.17 -2.98991 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0282445 0.0247036 141 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 2.97 vpr 62.47 MiB -1 -1 0.22 18020 1 0.02 -1 -1 30388 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63972 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 23.4 MiB 0.06 873 7655 1741 5556 358 62.5 MiB 0.08 0.00 3.46801 -106.861 -3.46801 3.46801 0.29 0.000592529 0.000551119 0.0230086 0.0213939 -1 -1 -1 -1 26 1985 22 6.65987e+06 418374 477104. 1650.88 1.09 0.101588 0.0889863 21682 110474 -1 1566 19 872 1628 93100 23067 2.89891 2.89891 -101.232 -2.89891 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0227936 0.0198726 111 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 3.74 vpr 63.60 MiB -1 -1 0.27 18632 1 0.03 -1 -1 30348 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65124 32 32 431 332 1 235 97 17 17 289 -1 unnamed_device 24.1 MiB 0.16 1373 17857 5541 9729 2587 63.6 MiB 0.21 0.00 6.00689 -175.284 -6.00689 6.00689 0.32 0.000829838 0.000770463 0.0699701 0.065028 -1 -1 -1 -1 26 3848 37 6.65987e+06 418374 477104. 1650.88 1.45 0.197086 0.174141 21682 110474 -1 3002 21 1997 2930 217962 52054 5.28897 5.28897 -171.079 -5.28897 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0353896 0.0309506 177 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 2.72 vpr 62.68 MiB -1 -1 0.23 18428 1 0.03 -1 -1 30384 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64180 32 32 336 268 1 174 102 17 17 289 -1 unnamed_device 23.7 MiB 0.11 1017 19142 6169 10401 2572 62.7 MiB 0.18 0.00 4.49092 -134.922 -4.49092 4.49092 0.32 0.000688964 0.000639258 0.058669 0.0542224 -1 -1 -1 -1 32 2057 20 6.65987e+06 481764 554710. 1919.41 0.55 0.138961 0.123175 22834 132086 -1 1855 18 1006 1647 91104 22583 3.46031 3.46031 -122.488 -3.46031 0 0 701300. 2426.64 0.05 0.07 0.08 -1 -1 0.05 0.027125 0.0239429 136 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 2.42 vpr 62.38 MiB -1 -1 0.20 17912 1 0.05 -1 -1 30352 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63880 32 32 231 199 1 140 93 17 17 289 -1 unnamed_device 23.1 MiB 0.06 757 14793 4373 7837 2583 62.4 MiB 0.13 0.00 3.29469 -92.947 -3.29469 3.29469 0.32 0.000538264 0.000501659 0.0461663 0.0429533 -1 -1 -1 -1 30 1671 23 6.65987e+06 367662 526063. 1820.29 0.50 0.111364 0.098657 22546 126617 -1 1389 20 700 1220 66685 16954 2.41305 2.41305 -85.9205 -2.41305 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.021408 0.0186665 103 3 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.75 vpr 63.34 MiB -1 -1 0.23 18472 1 0.04 -1 -1 30316 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64860 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1150 19624 5000 12637 1987 63.3 MiB 0.19 0.00 5.1064 -126.138 -5.1064 5.1064 0.32 0.000704936 0.000655185 0.059793 0.055533 -1 -1 -1 -1 28 2459 23 6.65987e+06 507120 500653. 1732.36 0.57 0.147213 0.130679 21970 115934 -1 2168 22 1287 2791 166610 39959 3.96919 3.96919 -118.971 -3.96919 0 0 612192. 2118.31 0.03 0.08 0.12 -1 -1 0.03 0.0303989 0.0264907 147 29 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.52 vpr 63.21 MiB -1 -1 0.22 17964 1 0.03 -1 -1 30112 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64728 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 23.4 MiB 0.06 872 15831 4931 8734 2166 63.2 MiB 0.14 0.00 3.5083 -107.383 -3.5083 3.5083 0.32 0.000561581 0.00052297 0.050766 0.0471046 -1 -1 -1 -1 32 1802 23 6.65987e+06 291594 554710. 1919.41 0.51 0.118787 0.105164 22834 132086 -1 1692 22 1001 1708 115538 28004 2.61951 2.61951 -100.831 -2.61951 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0241798 0.0210207 107 3 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 2.78 vpr 62.54 MiB -1 -1 0.24 18124 1 0.03 -1 -1 30336 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64040 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 23.4 MiB 0.11 879 14252 3836 8169 2247 62.5 MiB 0.12 0.00 4.01069 -108.355 -4.01069 4.01069 0.34 0.000599354 0.000550843 0.0387901 0.0359731 -1 -1 -1 -1 26 2025 24 6.65987e+06 481764 477104. 1650.88 0.69 0.11377 0.100057 21682 110474 -1 1739 19 906 1763 110431 27178 2.97191 2.97191 -105.651 -2.97191 0 0 585099. 2024.56 0.03 0.06 0.07 -1 -1 0.03 0.0225145 0.0196321 110 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 3.39 vpr 63.42 MiB -1 -1 0.25 18252 1 0.03 -1 -1 30480 -1 -1 32 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64944 29 32 355 287 1 198 93 17 17 289 -1 unnamed_device 23.7 MiB 0.10 935 10383 2371 7436 576 63.4 MiB 0.12 0.00 4.5774 -127.327 -4.5774 4.5774 0.32 0.000695523 0.000647079 0.0369925 0.0343684 -1 -1 -1 -1 26 3076 43 6.65987e+06 405696 477104. 1650.88 1.04 0.149016 0.130089 21682 110474 -1 2152 21 1391 2137 138462 37475 3.39717 3.39717 -116.441 -3.39717 0 0 585099. 2024.56 0.04 0.09 0.10 -1 -1 0.04 0.0365452 0.031807 146 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 2.56 vpr 62.78 MiB -1 -1 0.24 18248 1 0.03 -1 -1 30348 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64288 32 32 358 289 1 175 91 17 17 289 -1 unnamed_device 23.8 MiB 0.09 929 8251 1789 6085 377 62.8 MiB 0.10 0.00 4.29907 -134.356 -4.29907 4.29907 0.32 0.000692743 0.000642667 0.0308125 0.0285985 -1 -1 -1 -1 32 2220 22 6.65987e+06 342306 554710. 1919.41 0.56 0.116133 0.101656 22834 132086 -1 1882 22 1411 2117 134488 33129 3.89817 3.89817 -131.246 -3.89817 0 0 701300. 2426.64 0.03 0.07 0.08 -1 -1 0.03 0.0309356 0.0270608 135 54 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 2.62 vpr 63.35 MiB -1 -1 0.23 18572 1 0.04 -1 -1 30276 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 23.7 MiB 0.11 1075 15173 3870 9435 1868 63.3 MiB 0.15 0.00 4.58626 -136.867 -4.58626 4.58626 0.32 0.000705923 0.000655882 0.0503308 0.046744 -1 -1 -1 -1 32 2211 20 6.65987e+06 431052 554710. 1919.41 0.55 0.132979 0.11753 22834 132086 -1 1968 17 847 1531 91027 22240 3.35191 3.35191 -122.638 -3.35191 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0253636 0.0223258 136 51 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.47 vpr 63.35 MiB -1 -1 0.25 18168 1 0.04 -1 -1 30140 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64872 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 23.7 MiB 0.10 901 6701 1571 4713 417 63.4 MiB 0.08 0.00 4.569 -127.264 -4.569 4.569 0.32 0.000598546 0.000556821 0.0231644 0.0215639 -1 -1 -1 -1 26 2033 20 6.65987e+06 278916 477104. 1650.88 0.48 0.0923268 0.0807068 21682 110474 -1 1721 21 882 1189 70078 18621 3.26691 3.26691 -112.036 -3.26691 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0140382 0.0124423 107 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 2.64 vpr 62.48 MiB -1 -1 0.20 18340 1 0.03 -1 -1 30296 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63980 31 32 319 272 1 169 88 17 17 289 -1 unnamed_device 23.6 MiB 0.09 802 16273 4920 8724 2629 62.5 MiB 0.15 0.00 3.75784 -117.415 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/home/elgamma8/research/release/vtr-verilog-to-routing 64396 31 32 293 230 1 175 100 17 17 289 -1 unnamed_device 23.7 MiB 0.06 1091 10540 2548 6838 1154 62.9 MiB 0.11 0.00 4.26866 -122.654 -4.26866 4.26866 0.29 0.000634407 0.000589944 0.031125 0.0289309 -1 -1 -1 -1 28 2517 21 6.65987e+06 469086 500653. 1732.36 0.62 0.10807 0.0950411 21970 115934 -1 2180 23 1405 2540 172113 40649 3.40705 3.40705 -114.855 -3.40705 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0283837 0.0247165 134 4 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 3.53 vpr 62.97 MiB -1 -1 0.23 18332 1 0.07 -1 -1 30300 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64484 32 32 350 275 1 209 94 17 17 289 -1 unnamed_device 24.2 MiB 0.12 1246 10957 2695 7343 919 63.0 MiB 0.14 0.00 4.99112 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64176 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 23.6 MiB 0.13 1064 12365 3291 6967 2107 62.7 MiB 0.13 0.00 4.67895 -138.029 -4.67895 4.67895 0.31 0.000725007 0.000674131 0.0480908 0.0447495 -1 -1 -1 -1 28 2343 23 6.65987e+06 342306 500653. 1732.36 0.62 0.136452 0.120796 21970 115934 -1 1980 22 1486 2399 145841 36399 3.50937 3.50937 -127.985 -3.50937 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0317457 0.027759 147 63 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 2.65 vpr 63.50 MiB -1 -1 0.23 18316 1 0.03 -1 -1 30344 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65028 32 32 340 270 1 200 94 17 17 289 -1 unnamed_device 23.8 MiB 0.10 1145 13939 3986 8000 1953 63.5 MiB 0.15 0.00 5.09463 -149.184 -5.09463 5.09463 0.29 0.000696151 0.000641679 0.0475882 0.0442297 -1 -1 -1 -1 30 2536 25 6.65987e+06 380340 526063. 1820.29 0.55 0.133121 0.117514 22546 126617 -1 2135 21 1195 1902 103374 25035 3.52651 3.52651 -127.669 -3.52651 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0288516 0.0252219 145 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 3.16 vpr 62.95 MiB -1 -1 0.25 18368 1 0.03 -1 -1 30256 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64464 31 32 340 275 1 196 98 17 17 289 -1 unnamed_device 23.9 MiB 0.18 1110 13148 3427 8545 1176 63.0 MiB 0.13 0.00 5.06667 -144.178 -5.06667 5.06667 0.32 0.000692547 0.00064179 0.0430229 0.0399631 -1 -1 -1 -1 34 2291 34 6.65987e+06 443730 585099. 2024.56 0.95 0.190217 0.165664 23122 138558 -1 2068 20 1254 2153 127671 32495 3.93437 3.93437 -132.32 -3.93437 0 0 742403. 2568.87 0.03 0.07 0.11 -1 -1 0.03 0.0277139 0.0242435 151 47 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 3.18 vpr 63.29 MiB -1 -1 0.25 18368 1 0.03 -1 -1 30392 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64808 30 32 377 310 1 177 100 17 17 289 -1 unnamed_device 23.6 MiB 0.48 1101 17500 4849 10565 2086 63.3 MiB 0.18 0.00 4.57218 -136.411 -4.57218 4.57218 0.32 0.000708472 0.000656727 0.0563314 0.0522355 -1 -1 -1 -1 32 2218 20 6.65987e+06 481764 554710. 1919.41 0.57 0.140582 0.124466 22834 132086 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63808 32 32 243 205 1 139 83 17 17 289 -1 unnamed_device 23.1 MiB 0.10 885 6923 1715 4767 441 62.3 MiB 0.07 0.00 3.77952 -113.03 -3.77952 3.77952 0.32 0.000553392 0.000515609 0.0230724 0.0214826 -1 -1 -1 -1 26 1838 17 6.65987e+06 240882 477104. 1650.88 0.52 0.0857542 0.0752007 21682 110474 -1 1658 19 797 1244 78852 19566 2.69545 2.69545 -103.315 -2.69545 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0288758 0.0251878 99 3 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 2.84 vpr 62.77 MiB -1 -1 0.25 18268 1 0.04 -1 -1 30308 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64272 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 23.7 MiB 0.14 1014 14691 4446 7278 2967 62.8 MiB 0.14 0.00 4.39152 -132.525 -4.39152 4.39152 0.32 0.000727586 0.00067249 0.0500078 0.046285 -1 -1 -1 -1 32 2332 30 6.65987e+06 443730 554710. 1919.41 0.69 0.146265 0.128769 22834 132086 -1 1872 23 1191 1892 138049 33056 3.67671 3.67671 -122.883 -3.67671 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0328304 0.0289108 135 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 2.92 vpr 62.82 MiB -1 -1 0.27 18284 1 0.04 -1 -1 30228 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64324 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 23.9 MiB 0.24 1125 9989 2357 6341 1291 62.8 MiB 0.12 0.00 4.65798 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 356 289 1 202 101 17 17 289 -1 unnamed_device 23.9 MiB 0.18 1270 17021 5150 9608 2263 63.3 MiB 0.16 0.00 5.06049 -146.913 -5.06049 5.06049 0.32 0.000326262 0.000301131 0.0486664 0.0450209 -1 -1 -1 -1 26 2988 41 6.65987e+06 469086 477104. 1650.88 0.74 0.159099 0.140044 21682 110474 -1 2434 19 1509 2359 161130 37560 4.17677 4.17677 -139.903 -4.17677 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0275016 0.0240929 157 56 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 3.13 vpr 63.51 MiB -1 -1 0.16 18148 1 0.03 -1 -1 30108 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 32 32 331 280 1 175 87 17 17 289 -1 unnamed_device 23.4 MiB 0.40 1020 11991 3560 6392 2039 63.2 MiB 0.15 0.00 4.25169 -136.039 -4.25169 4.25169 0.32 0.000864673 0.000803635 0.0533516 0.0496012 -1 -1 -1 -1 32 2019 16 6.65987e+06 291594 554710. 1919.41 0.53 0.127172 0.112926 22834 132086 -1 1798 18 782 1100 71252 17324 3.25897 3.25897 -123.619 -3.25897 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0245208 0.0215202 131 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 2.95 vpr 62.66 MiB -1 -1 0.24 18380 1 0.03 -1 -1 30324 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 23.7 MiB 0.09 1117 12164 3459 7844 861 62.7 MiB 0.12 0.00 4.92174 -128.183 -4.92174 4.92174 0.31 0.00066283 0.000615913 0.0374864 0.0347847 -1 -1 -1 -1 26 2516 22 6.65987e+06 456408 477104. 1650.88 0.54 0.119342 0.104951 21682 110474 -1 2181 18 1043 1793 114022 27754 3.30585 3.30585 -116.367 -3.30585 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0251273 0.0220676 133 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 3.01 vpr 63.32 MiB -1 -1 0.20 18484 1 0.04 -1 -1 30424 -1 -1 38 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64840 31 32 373 294 1 196 101 17 17 289 -1 unnamed_device 23.8 MiB 0.09 1058 9971 2285 7156 530 63.3 MiB 0.12 0.00 4.48315 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fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 2.80 vpr 63.50 MiB -1 -1 0.25 18400 1 0.03 -1 -1 30040 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 386 307 1 195 106 17 17 289 -1 unnamed_device 24.0 MiB 0.11 1068 16856 4579 8928 3349 63.5 MiB 0.14 0.00 4.17081 -125.313 -4.17081 4.17081 0.32 0.000746376 0.000693057 0.0533797 0.0495831 -1 -1 -1 -1 32 2577 35 6.65987e+06 532476 554710. 1919.41 0.67 0.159111 0.140204 22834 132086 -1 2028 24 1434 2300 146117 37601 2.97097 2.97097 -114.135 -2.97097 0 0 701300. 2426.64 0.03 0.09 0.11 -1 -1 0.03 0.034841 0.0304283 151 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 2.34 vpr 62.36 MiB -1 -1 0.11 18144 1 0.03 -1 -1 30284 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63860 29 32 269 229 1 129 80 17 17 289 -1 unnamed_device 23.4 MiB 0.05 783 14184 4630 8014 1540 62.4 MiB 0.12 0.00 4.07075 -112.394 -4.07075 4.07075 0.32 0.000576339 0.000535755 0.0495872 0.0461609 -1 -1 -1 -1 32 1449 20 6.65987e+06 240882 554710. 1919.41 0.49 0.116661 0.103432 22834 132086 -1 1346 20 716 1069 69828 16923 2.81477 2.81477 -95.7948 -2.81477 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0229956 0.0200317 93 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 2.80 vpr 62.46 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30332 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63964 32 32 310 266 1 175 89 17 17 289 -1 unnamed_device 23.3 MiB 0.08 1007 13949 3952 8258 1739 62.5 MiB 0.12 0.00 4.24766 -126.418 -4.24766 4.24766 0.32 0.000481589 0.000443594 0.0432888 0.0401085 -1 -1 -1 -1 32 1793 18 6.65987e+06 316950 554710. 1919.41 0.52 0.11537 0.101824 22834 132086 -1 1672 14 756 1020 62601 15811 3.06877 3.06877 -112.763 -3.06877 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0198489 0.017478 122 58 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 3.17 vpr 63.25 MiB -1 -1 0.14 18252 1 0.03 -1 -1 30304 -1 -1 42 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 31 32 326 261 1 177 105 17 17 289 -1 unnamed_device 23.7 MiB 0.08 926 12208 3208 7327 1673 63.2 MiB 0.12 0.00 4.58372 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63972 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 23.3 MiB 0.07 930 10228 2669 6535 1024 62.5 MiB 0.10 0.00 3.8161 -117.091 -3.8161 3.8161 0.32 0.000591034 0.000543686 0.0323042 0.0300571 -1 -1 -1 -1 32 1836 21 6.65987e+06 316950 554710. 1919.41 0.49 0.100283 0.0881994 22834 132086 -1 1638 17 808 1220 76603 18529 2.93457 2.93457 -107.171 -2.93457 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0213134 0.0187932 115 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 2.63 vpr 62.65 MiB -1 -1 0.23 18412 1 0.03 -1 -1 30008 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64156 32 32 349 286 1 171 101 17 17 289 -1 unnamed_device 23.6 MiB 0.11 1077 18196 4934 11069 2193 62.7 MiB 0.16 0.00 3.54324 -109.963 -3.54324 3.54324 0.32 0.000538895 0.000495325 0.0514617 0.0475687 -1 -1 -1 -1 32 2182 22 6.65987e+06 469086 554710. 1919.41 0.56 0.134851 0.118993 22834 132086 -1 1852 21 982 1748 107334 25210 2.76771 2.76771 -104.243 -2.76771 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0290857 0.025433 131 57 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 2.95 vpr 63.34 MiB -1 -1 0.25 18248 1 0.03 -1 -1 30416 -1 -1 36 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 23.6 MiB 0.43 972 13779 3191 9639 949 63.3 MiB 0.14 0.00 3.95996 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 29 32 324 268 1 168 97 17 17 289 -1 unnamed_device 23.5 MiB 0.11 1042 6535 1424 4454 657 62.8 MiB 0.07 0.00 4.20872 -115.808 -4.20872 4.20872 0.31 0.000653114 0.000605773 0.021466 0.0199964 -1 -1 -1 -1 30 1967 16 6.65987e+06 456408 526063. 1820.29 0.50 0.0934942 0.0815178 22546 126617 -1 1808 19 714 1267 68406 16641 2.71491 2.71491 -97.6025 -2.71491 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0257432 0.0225677 129 55 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 2.87 vpr 63.45 MiB -1 -1 0.23 18276 1 0.03 -1 -1 30480 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 32 32 393 312 1 213 94 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1136 17773 5438 9801 2534 63.4 MiB 0.19 0.00 5.18709 -160.79 -5.18709 5.18709 0.32 0.000751899 0.000698984 0.0661306 0.0614276 -1 -1 -1 -1 32 2400 22 6.65987e+06 380340 554710. 1919.41 0.61 0.167742 0.148709 22834 132086 -1 2213 22 1428 1987 125431 30881 3.96237 3.96237 -142.636 -3.96237 0 0 701300. 2426.64 0.04 0.10 0.11 -1 -1 0.04 0.0400136 0.0353947 159 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 2.46 vpr 62.59 MiB -1 -1 0.23 17952 1 0.03 -1 -1 30084 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 31 32 229 197 1 138 84 17 17 289 -1 unnamed_device 23.3 MiB 0.07 877 10515 2651 6990 874 62.6 MiB 0.10 0.00 3.28101 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1104 1594 96411 24003 3.39911 3.39911 -128.845 -3.39911 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0296925 0.0260202 146 90 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 2.64 vpr 62.69 MiB -1 -1 0.24 18448 1 0.03 -1 -1 30108 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 32 32 376 318 1 156 82 17 17 289 -1 unnamed_device 23.7 MiB 0.11 914 11474 3086 6952 1436 62.7 MiB 0.13 0.00 3.54227 -124.771 -3.54227 3.54227 0.32 0.000718606 0.000667277 0.049602 0.046095 -1 -1 -1 -1 32 1720 17 6.65987e+06 228204 554710. 1919.41 0.53 0.129159 0.114224 22834 132086 -1 1578 21 1236 1858 105693 26868 2.87077 2.87077 -119.337 -2.87077 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0294216 0.0256661 117 96 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.69 vpr 63.28 MiB -1 -1 0.15 18304 1 0.03 -1 -1 30320 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 23.6 MiB 0.09 987 16059 4384 8773 2902 63.3 MiB 0.15 0.00 3.84552 -115.819 -3.84552 3.84552 0.33 0.000588113 0.000522126 0.0529609 0.0491666 -1 -1 -1 -1 32 2087 20 6.65987e+06 443730 554710. 1919.41 0.55 0.136764 0.121046 22834 132086 -1 1731 18 919 1426 73695 19390 2.62331 2.62331 -97.5338 -2.62331 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0269736 0.023685 134 60 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 3.78 vpr 63.52 MiB -1 -1 0.15 18496 1 0.03 -1 -1 30488 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65040 32 32 396 299 1 236 98 17 17 289 -1 unnamed_device 23.9 MiB 0.16 1229 18773 5439 9701 3633 63.5 MiB 0.18 0.00 6.00689 -176.035 -6.00689 6.00689 0.34 0.000348158 0.00032017 0.0661284 0.0613889 -1 -1 -1 -1 36 2968 23 6.65987e+06 431052 612192. 2118.31 1.43 0.227075 0.199663 23410 145293 -1 2288 21 1763 2474 164498 42055 4.85537 4.85537 -153.246 -4.85537 0 0 782063. 2706.10 0.04 0.07 0.11 -1 -1 0.04 0.0231769 0.0207501 177 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 2.52 vpr 62.36 MiB -1 -1 0.16 18020 1 0.03 -1 -1 30244 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63860 30 32 224 207 1 138 84 17 17 289 -1 unnamed_device 23.1 MiB 0.06 852 12894 3845 7396 1653 62.4 MiB 0.10 0.00 3.23481 -100.258 -3.23481 3.23481 0.34 0.000510384 0.000474865 0.0371748 0.0345906 -1 -1 -1 -1 26 1611 17 6.65987e+06 278916 477104. 1650.88 0.51 0.0938904 0.0829793 21682 110474 -1 1486 21 811 1082 72254 17229 2.47811 2.47811 -92.0662 -2.47811 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0207099 0.0179707 92 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.53 vpr 62.52 MiB -1 -1 0.22 18088 1 0.03 -1 -1 30344 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 23.4 MiB 0.13 726 6206 1469 4338 399 62.5 MiB 0.07 0.00 3.83543 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64356 31 32 409 331 1 191 105 17 17 289 -1 unnamed_device 23.9 MiB 0.11 987 19124 5334 10330 3460 62.8 MiB 0.19 0.00 3.91658 -124.769 -3.91658 3.91658 0.32 0.000756341 0.000701237 0.0615584 0.0570229 -1 -1 -1 -1 32 2113 20 6.65987e+06 532476 554710. 1919.41 0.60 0.154524 0.136607 22834 132086 -1 1837 19 1226 1995 117145 29196 2.79751 2.79751 -109.839 -2.79751 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0292829 0.0256389 148 90 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_001.v common 11.61 vpr 64.05 MiB -1 -1 0.24 18320 1 0.03 -1 -1 30228 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65588 32 32 354 285 1 191 88 17 17 289 -1 unnamed_device 24.5 MiB 1.20 903 15298 5538 7704 2056 64.1 MiB 0.13 0.00 5.15265 -149.781 -5.15265 5.15265 0.35 0.000701928 0.000652099 0.0579569 0.0538537 -1 -1 -1 -1 40 2487 22 6.95648e+06 347416 706193. 2443.58 8.24 0.381864 0.330066 26914 176310 -1 2069 20 1681 2521 193589 46028 4.70236 4.70236 -152.72 -4.70236 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0283789 0.0248703 85 50 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_002.v common 6.23 vpr 63.55 MiB -1 -1 0.25 18552 1 0.03 -1 -1 30328 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65072 30 32 363 293 1 187 80 17 17 289 -1 unnamed_device 24.5 MiB 1.72 822 9540 3866 5233 441 63.5 MiB 0.10 0.00 4.21658 -127.866 -4.21658 4.21658 0.35 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0 902133. 3121.57 0.04 0.07 0.14 -1 -1 0.04 0.0271238 0.023716 74 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_004.v common 4.01 vpr 64.01 MiB -1 -1 0.24 18400 1 0.03 -1 -1 30284 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65548 29 32 308 248 1 162 84 17 17 289 -1 unnamed_device 24.3 MiB 0.21 713 12894 4756 6364 1774 64.0 MiB 0.11 0.00 3.96328 -113.694 -3.96328 3.96328 0.33 0.000637533 0.000592304 0.046852 0.043548 -1 -1 -1 -1 36 2424 31 6.95648e+06 332941 648988. 2245.63 1.85 0.192789 0.167961 26050 158493 -1 1795 24 1592 2700 214858 50665 4.07691 4.07691 -125.389 -4.07691 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0184205 0.016334 73 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_005.v common 4.13 vpr 63.91 MiB -1 -1 0.24 18416 1 0.03 -1 -1 30432 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65440 32 32 336 268 1 167 85 17 17 289 -1 unnamed_device 24.2 MiB 0.30 799 12919 4266 6230 2423 63.9 MiB 0.14 0.00 3.92082 -123.639 -3.92082 3.92082 0.33 0.000689843 0.000640891 0.0579711 0.053704 -1 -1 -1 -1 40 2419 26 6.95648e+06 303989 706193. 2443.58 1.73 0.195597 0.171434 26914 176310 -1 1974 23 1432 2633 220972 49560 4.01942 4.01942 -133.562 -4.01942 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0306242 0.026712 76 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_006.v common 4.55 vpr 63.35 MiB -1 -1 0.25 18324 1 0.03 -1 -1 30296 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 366 295 1 182 89 17 17 289 -1 unnamed_device 24.5 MiB 0.40 1004 13949 3867 8912 1170 63.3 MiB 0.13 0.00 3.1127 -117.428 -3.1127 3.1127 0.33 0.000898578 0.000838343 0.0537559 0.0498994 -1 -1 -1 -1 34 2773 40 6.95648e+06 361892 618332. 2139.56 2.07 0.217268 0.189412 25762 151098 -1 2255 18 1337 2010 155622 35041 3.22637 3.22637 -127.705 -3.22637 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0266073 0.0233266 81 58 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_007.v common 6.63 vpr 63.88 MiB -1 -1 0.23 18196 1 0.03 -1 -1 30616 -1 -1 14 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65412 27 32 259 221 1 124 73 17 17 289 -1 unnamed_device 24.3 MiB 2.35 446 7825 3025 3749 1051 63.9 MiB 0.07 0.00 3.35433 -89.8611 -3.35433 3.35433 0.33 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65348 32 32 298 248 1 150 75 17 17 289 -1 unnamed_device 24.4 MiB 0.82 631 10503 4334 5853 316 63.8 MiB 0.10 0.00 3.30308 -115.551 -3.30308 3.30308 0.33 0.0006312 0.000584843 0.0439573 0.0408989 -1 -1 -1 -1 42 1721 25 6.95648e+06 159232 744469. 2576.02 1.03 0.17109 0.149045 27202 183097 -1 1354 19 1057 1489 99641 25380 3.14782 3.14782 -113.598 -3.14782 0 0 949917. 3286.91 0.04 0.06 0.15 -1 -1 0.04 0.0240878 0.0210586 60 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_011.v common 4.30 vpr 63.69 MiB -1 -1 0.24 18432 1 0.03 -1 -1 30336 -1 -1 13 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65216 30 32 303 262 1 135 75 17 17 289 -1 unnamed_device 24.3 MiB 0.89 501 7975 2162 4189 1624 63.7 MiB 0.07 0.00 3.32418 -98.7921 -3.32418 3.32418 0.33 0.000626842 0.000583299 0.033361 0.031035 -1 -1 -1 -1 42 1361 50 6.95648e+06 188184 744469. 2576.02 1.38 0.180268 0.155588 27202 183097 -1 1018 21 1057 1561 93379 26253 2.99162 2.99162 -104.394 -2.99162 0 0 949917. 3286.91 0.04 0.06 0.15 -1 -1 0.04 0.0261378 0.022782 54 63 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_012.v common 4.57 vpr 63.32 MiB -1 -1 0.23 18088 1 0.03 -1 -1 30204 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 32 32 276 237 1 161 77 17 17 289 -1 unnamed_device 24.3 MiB 1.18 717 11487 4799 6349 339 63.3 MiB 0.05 0.00 3.36853 -108.171 -3.36853 3.36853 0.32 0.000263884 0.000242125 0.0203308 0.0187078 -1 -1 -1 -1 42 2258 41 6.95648e+06 188184 744469. 2576.02 1.40 0.152874 0.131337 27202 183097 -1 1691 23 1303 1654 162426 40261 3.05107 3.05107 -115.385 -3.05107 0 0 949917. 3286.91 0.04 0.07 0.14 -1 -1 0.04 0.0263999 0.0229264 61 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_013.v common 11.03 vpr 63.34 MiB -1 -1 0.25 18344 1 0.03 -1 -1 30272 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64864 32 32 344 272 1 194 81 17 17 289 -1 unnamed_device 24.4 MiB 1.33 963 14256 6124 7652 480 63.3 MiB 0.13 0.00 4.10048 -133.291 -4.10048 4.10048 0.33 0.000688322 0.000638252 0.0586569 0.0544325 -1 -1 -1 -1 52 2682 48 6.95648e+06 246087 926341. 3205.33 7.55 0.399651 0.344428 29218 227130 -1 2046 22 1527 2342 196802 44603 3.49922 3.49922 -129.355 -3.49922 0 0 1.14541e+06 3963.36 0.05 0.09 0.18 -1 -1 0.05 0.0310755 0.02722 80 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_014.v common 11.11 vpr 63.53 MiB -1 -1 0.14 18364 1 0.03 -1 -1 30292 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65052 32 32 363 295 1 174 89 17 17 289 -1 unnamed_device 24.5 MiB 0.37 807 13751 4140 6609 3002 63.5 MiB 0.12 0.00 4.30188 -129.441 -4.30188 4.30188 0.34 0.000722024 0.000670873 0.0521037 0.0484003 -1 -1 -1 -1 42 2744 33 6.95648e+06 361892 744469. 2576.02 8.61 0.359569 0.310163 27202 183097 -1 1947 24 1856 2848 247962 58594 4.34321 4.34321 -142.631 -4.34321 0 0 949917. 3286.91 0.04 0.10 0.15 -1 -1 0.04 0.0323478 0.0281415 78 61 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_015.v common 4.18 vpr 63.60 MiB -1 -1 0.22 18040 1 0.03 -1 -1 30504 -1 -1 18 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65124 29 32 248 215 1 132 79 17 17 289 -1 unnamed_device 24.2 MiB 0.43 542 11064 3839 5079 2146 63.6 MiB 0.10 0.00 2.93656 -85.9547 -2.93656 2.93656 0.33 0.000543369 0.000504995 0.0449064 0.0417544 -1 -1 -1 -1 38 1739 25 6.95648e+06 260562 678818. 2348.85 1.60 0.163141 0.142452 26626 170182 -1 1156 20 930 1476 86830 22287 2.86467 2.86467 -90.2809 -2.86467 0 0 902133. 3121.57 0.03 0.05 0.14 -1 -1 0.03 0.0219637 0.0191139 55 27 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_016.v common 9.89 vpr 64.18 MiB -1 -1 0.25 18480 1 0.03 -1 -1 30292 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65720 32 32 370 297 1 178 81 17 17 289 -1 unnamed_device 24.6 MiB 0.55 1116 11456 4128 5618 1710 64.2 MiB 0.11 0.00 3.1427 -121.494 -3.1427 3.1427 0.33 0.000717433 0.000666227 0.0497802 0.0462674 -1 -1 -1 -1 38 2695 25 6.95648e+06 246087 678818. 2348.85 7.13 0.321783 0.277821 26626 170182 -1 2317 20 1511 2426 195538 40467 3.13107 3.13107 -128.649 -3.13107 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.029045 0.0253744 77 58 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_017.v common 5.39 vpr 64.05 MiB -1 -1 0.23 18332 1 0.03 -1 -1 30084 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65592 32 32 338 269 1 190 81 17 17 289 -1 unnamed_device 24.2 MiB 1.49 1015 13031 4708 5937 2386 64.1 MiB 0.12 0.00 3.87402 -125.064 -3.87402 3.87402 0.34 0.000692755 0.000644535 0.0542598 0.0504807 -1 -1 -1 -1 36 2757 49 6.95648e+06 246087 648988. 2245.63 1.76 0.226187 0.197378 26050 158493 -1 2291 25 1915 2601 250174 70472 3.35447 3.35447 -133.03 -3.35447 0 0 828058. 2865.25 0.03 0.11 0.13 -1 -1 0.03 0.0331884 0.0289165 78 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_018.v common 3.96 vpr 63.38 MiB -1 -1 0.24 18420 1 0.03 -1 -1 30336 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64896 32 32 323 276 1 148 87 17 17 289 -1 unnamed_device 24.3 MiB 0.59 786 10071 3578 4718 1775 63.4 MiB 0.09 0.00 2.31531 -95.0474 -2.31531 2.31531 0.34 0.000651323 0.000604716 0.0365085 0.0338373 -1 -1 -1 -1 40 1891 23 6.95648e+06 332941 706193. 2443.58 1.30 0.171573 0.148913 26914 176310 -1 1667 24 1362 2073 174745 41485 2.52138 2.52138 -102.073 -2.52138 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0295211 0.02561 65 65 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_019.v common 3.21 vpr 63.24 MiB -1 -1 0.21 18132 1 0.03 -1 -1 30076 -1 -1 11 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 30 32 222 206 1 114 73 17 17 289 -1 unnamed_device 23.7 MiB 0.15 430 7217 2897 3955 365 63.2 MiB 0.06 0.00 2.19546 -77.9644 -2.19546 2.19546 0.34 0.000496364 0.000461914 0.0252717 0.023525 -1 -1 -1 -1 38 1129 22 6.95648e+06 159232 678818. 2348.85 1.10 0.125104 0.108162 26626 170182 -1 802 21 683 938 55231 15482 2.06418 2.06418 -79.525 -2.06418 0 0 902133. 3121.57 0.04 0.05 0.14 -1 -1 0.04 0.0206062 0.0179189 44 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_020.v common 4.62 vpr 63.34 MiB -1 -1 0.24 18252 1 0.03 -1 -1 30452 -1 -1 14 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64860 31 32 291 243 1 166 77 17 17 289 -1 unnamed_device 24.2 MiB 1.53 1007 11976 3355 7225 1396 63.3 MiB 0.10 0.00 4.40603 -142.381 -4.40603 4.40603 0.33 0.000608611 0.000566303 0.0470857 0.043836 -1 -1 -1 -1 34 2380 24 6.95648e+06 202660 618332. 2139.56 1.06 0.169043 0.147544 25762 151098 -1 2003 20 1207 1675 119064 27189 3.98032 3.98032 -146.92 -3.98032 0 0 787024. 2723.27 0.03 0.06 0.12 -1 -1 0.03 0.0247293 0.0215758 68 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_021.v common 4.70 vpr 63.46 MiB -1 -1 0.26 18472 1 0.03 -1 -1 30432 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64984 32 32 342 271 1 172 91 17 17 289 -1 unnamed_device 24.5 MiB 0.23 777 13351 4773 6428 2150 63.5 MiB 0.11 0.00 3.69009 -122.34 -3.69009 3.69009 0.33 0.000688999 0.000639455 0.047794 0.0443687 -1 -1 -1 -1 40 2451 40 6.95648e+06 390843 706193. 2443.58 2.28 0.208193 0.181318 26914 176310 -1 1989 23 1600 2424 223141 68263 3.89406 3.89406 -135.843 -3.89406 0 0 926341. 3205.33 0.04 0.12 0.15 -1 -1 0.04 0.0334966 0.029147 79 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_022.v common 4.94 vpr 63.62 MiB -1 -1 0.25 18268 1 0.03 -1 -1 30280 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65148 32 32 372 300 1 200 80 17 17 289 -1 unnamed_device 24.6 MiB 1.09 929 10228 2968 5474 1786 63.6 MiB 0.10 0.00 4.43786 -126.086 -4.43786 4.43786 0.33 0.000725922 0.000674137 0.0459557 0.042749 -1 -1 -1 -1 52 2444 39 6.95648e+06 231611 926341. 3205.33 1.71 0.211794 0.184632 29218 227130 -1 1697 21 1603 2467 172559 43849 3.84822 3.84822 -125.024 -3.84822 0 0 1.14541e+06 3963.36 0.04 0.08 0.18 -1 -1 0.04 0.0302014 0.0263891 82 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_023.v common 2.81 vpr 63.27 MiB -1 -1 0.22 18188 1 0.02 -1 -1 30624 -1 -1 14 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64784 26 32 190 182 1 104 72 17 17 289 -1 unnamed_device 23.9 MiB 0.33 469 6926 2796 3691 439 63.3 MiB 0.05 0.00 2.27636 -67.9936 -2.27636 2.27636 0.35 0.000429337 0.000398799 0.0215449 0.020025 -1 -1 -1 -1 32 1196 21 6.95648e+06 202660 586450. 2029.24 0.59 0.0725739 0.0635235 25474 144626 -1 953 24 615 774 90885 31923 2.28603 2.28603 -73.7824 -2.28603 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0199648 0.017303 43 30 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_024.v common 8.18 vpr 63.14 MiB -1 -1 0.15 17796 1 0.03 -1 -1 30324 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 32 32 285 227 1 159 81 17 17 289 -1 unnamed_device 24.1 MiB 0.45 719 9531 2772 5216 1543 63.1 MiB 0.09 0.00 4.35141 -115.734 -4.35141 4.35141 0.34 0.00062324 0.000578477 0.03622 0.0336562 -1 -1 -1 -1 42 2136 41 6.95648e+06 246087 744469. 2576.02 5.73 0.308778 0.265688 27202 183097 -1 1474 23 1312 2219 179928 44050 4.15656 4.15656 -120.492 -4.15656 0 0 949917. 3286.91 0.04 0.08 0.15 -1 -1 0.04 0.0278794 0.0242966 66 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_025.v common 2.64 vpr 63.15 MiB -1 -1 0.11 17612 1 0.03 -1 -1 29988 -1 -1 10 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 32 32 173 169 1 111 74 17 17 289 -1 unnamed_device 23.8 MiB 0.10 456 10459 4198 5595 666 63.1 MiB 0.07 0.00 2.13126 -69.3153 -2.13126 2.13126 0.31 0.00042468 0.000394535 0.0302253 0.0280834 -1 -1 -1 -1 36 1204 23 6.95648e+06 144757 648988. 2245.63 0.91 0.11542 0.100517 26050 158493 -1 915 21 632 749 65534 16835 2.05118 2.05118 -75.2428 -2.05118 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0176879 0.0153969 43 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_026.v common 3.91 vpr 63.34 MiB -1 -1 0.23 18124 1 0.03 -1 -1 30152 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64864 32 32 300 245 1 159 83 17 17 289 -1 unnamed_device 24.2 MiB 0.46 705 11063 3344 5374 2345 63.3 MiB 0.09 0.00 4.42909 -119.059 -4.42909 4.42909 0.34 0.000632235 0.000588523 0.0414738 0.0385764 -1 -1 -1 -1 42 1926 27 6.95648e+06 275038 744469. 2576.02 1.35 0.176041 0.153466 27202 183097 -1 1512 20 1112 1881 126839 32424 3.69636 3.69636 -116.75 -3.69636 0 0 949917. 3286.91 0.04 0.07 0.15 -1 -1 0.04 0.0258126 0.0225697 67 24 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_027.v common 3.35 vpr 63.43 MiB -1 -1 0.22 17828 1 0.03 -1 -1 30316 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64956 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 24.2 MiB 0.18 1111 14983 4654 8769 1560 63.4 MiB 0.12 0.00 2.9965 -108.481 -2.9965 2.9965 0.33 0.000637683 0.000592435 0.0491689 0.0456907 -1 -1 -1 -1 36 2380 21 6.95648e+06 390843 648988. 2245.63 1.14 0.174104 0.152271 26050 158493 -1 2077 22 1257 1942 162231 34962 3.00062 3.00062 -113.678 -3.00062 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0273556 0.0238501 77 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_028.v common 4.13 vpr 64.05 MiB -1 -1 0.25 18384 1 0.03 -1 -1 30268 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65592 32 32 338 277 1 172 87 17 17 289 -1 unnamed_device 24.3 MiB 0.61 815 11991 3979 6088 1924 64.1 MiB 0.06 0.00 4.25013 -125.291 -4.25013 4.25013 0.25 0.00030205 0.000277272 0.0210826 0.0194187 -1 -1 -1 -1 44 2504 50 6.95648e+06 332941 787024. 2723.27 1.53 0.179622 0.15507 27778 195446 -1 1851 23 1415 2385 195085 45432 4.07246 4.07246 -131.405 -4.07246 0 0 997811. 3452.63 0.06 0.10 0.16 -1 -1 0.06 0.0384545 0.0340278 74 50 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_029.v common 3.59 vpr 63.65 MiB -1 -1 0.18 18148 1 0.03 -1 -1 30076 -1 -1 15 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65176 32 32 284 241 1 139 79 17 17 289 -1 unnamed_device 24.3 MiB 0.44 636 11740 4501 5598 1641 63.6 MiB 0.10 0.00 2.8872 -98.3416 -2.8872 2.8872 0.33 0.000600815 0.000558186 0.0439891 0.0409118 -1 -1 -1 -1 36 2014 26 6.95648e+06 217135 648988. 2245.63 1.18 0.166398 0.144912 26050 158493 -1 1620 23 1058 1616 135085 32903 3.47502 3.47502 -113.126 -3.47502 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0266523 0.0231135 57 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_030.v common 3.40 vpr 63.58 MiB -1 -1 0.14 18124 1 0.03 -1 -1 30096 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65108 30 32 262 227 1 134 84 17 17 289 -1 unnamed_device 24.0 MiB 0.24 598 12894 4167 6970 1757 63.6 MiB 0.10 0.00 3.17414 -94.0877 -3.17414 3.17414 0.34 0.000573241 0.00052658 0.0418466 0.0387546 -1 -1 -1 -1 38 1729 50 6.95648e+06 318465 678818. 2348.85 1.28 0.180547 0.156592 26626 170182 -1 1167 20 965 1502 93858 23736 2.85952 2.85952 -93.9328 -2.85952 0 0 902133. 3121.57 0.04 0.06 0.14 -1 -1 0.04 0.0228669 0.0198687 60 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_031.v common 3.67 vpr 63.50 MiB -1 -1 0.17 18060 1 0.03 -1 -1 30096 -1 -1 21 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65028 28 32 260 223 1 135 81 17 17 289 -1 unnamed_device 23.9 MiB 0.20 526 9881 3467 4910 1504 63.5 MiB 0.08 0.00 2.9041 -89.8524 -2.9041 2.9041 0.35 0.000561846 0.000519378 0.0338285 0.0314291 -1 -1 -1 -1 44 1510 25 6.95648e+06 303989 787024. 2723.27 1.54 0.153363 0.133271 27778 195446 -1 1252 20 976 1638 120916 31896 3.14012 3.14012 -100.347 -3.14012 0 0 997811. 3452.63 0.04 0.06 0.16 -1 -1 0.04 0.0226749 0.0197469 60 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_032.v common 3.36 vpr 63.54 MiB -1 -1 0.20 17740 1 0.02 -1 -1 30304 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65060 32 32 253 210 1 149 77 17 17 289 -1 unnamed_device 23.9 MiB 0.12 872 7412 1986 4690 736 63.5 MiB 0.07 0.00 3.33963 -114.641 -3.33963 3.33963 0.34 0.000569591 0.000529726 0.0281963 0.026277 -1 -1 -1 -1 36 2003 21 6.95648e+06 188184 648988. 2245.63 1.37 0.144816 0.125617 26050 158493 -1 1836 21 1303 1920 176626 40606 3.03682 3.03682 -116.712 -3.03682 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0242923 0.0211886 59 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_033.v common 3.55 vpr 63.59 MiB -1 -1 0.23 18256 1 0.03 -1 -1 30228 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65120 31 32 271 231 1 143 88 17 17 289 -1 unnamed_device 24.3 MiB 0.20 648 8278 1868 6118 292 63.6 MiB 0.08 0.00 3.26818 -103.77 -3.26818 3.26818 0.34 0.000593505 0.000551506 0.0271878 0.0252563 -1 -1 -1 -1 38 2153 30 6.95648e+06 361892 678818. 2348.85 1.39 0.152159 0.131517 26626 170182 -1 1564 20 1067 1757 135431 31600 3.25942 3.25942 -106.518 -3.25942 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65800 32 32 367 282 1 193 97 17 17 289 -1 unnamed_device 24.6 MiB 0.36 911 15193 4522 7149 3522 64.3 MiB 0.12 0.00 4.10963 -121.284 -4.10963 4.10963 0.35 0.000733576 0.00068136 0.0533783 0.0495534 -1 -1 -1 -1 46 2654 40 6.95648e+06 477698 828058. 2865.25 1.98 0.238984 0.209506 28066 200906 -1 2029 21 1409 2479 179633 42774 3.83601 3.83601 -125.609 -3.83601 0 0 1.01997e+06 3529.29 0.04 0.08 0.14 -1 -1 0.04 0.0318055 0.0278818 91 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_036.v common 4.86 vpr 63.55 MiB -1 -1 0.24 18284 1 0.03 -1 -1 30264 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 64916 32 32 349 284 1 175 90 17 17 289 -1 unnamed_device 24.2 MiB 0.44 1076 13557 4204 7841 1512 63.4 MiB 0.12 0.00 3.1047 -113.61 -3.1047 3.1047 0.34 0.000697786 0.000646852 0.0494433 0.0459023 -1 -1 -1 -1 40 2543 44 6.95648e+06 376368 706193. 2443.58 1.74 0.218193 0.190007 26914 176310 -1 2184 21 1482 2483 204735 44012 3.10107 3.10107 -117.005 -3.10107 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0301622 0.026338 78 53 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_047.v common 4.11 vpr 63.94 MiB -1 -1 0.22 17896 1 0.03 -1 -1 30096 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65476 32 32 291 230 1 161 83 17 17 289 -1 unnamed_device 24.3 MiB 0.30 727 11963 4343 5980 1640 63.9 MiB 0.11 0.00 4.01417 -117.763 -4.01417 4.01417 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65688 32 32 382 305 1 184 93 17 17 289 -1 unnamed_device 24.5 MiB 0.29 1111 12693 3643 7264 1786 64.1 MiB 0.12 0.00 3.72599 -128.052 -3.72599 3.72599 0.33 0.000745259 0.000691766 0.0478964 0.0445264 -1 -1 -1 -1 38 2710 39 6.95648e+06 419795 678818. 2348.85 1.56 0.214278 0.18655 26626 170182 -1 2296 18 1570 2524 191579 41155 3.34267 3.34267 -126.01 -3.34267 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.0273508 0.0239439 87 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_051.v common 3.83 vpr 63.89 MiB -1 -1 0.23 18064 1 0.03 -1 -1 30284 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65424 32 32 306 248 1 160 86 17 17 289 -1 unnamed_device 24.2 MiB 0.41 714 10859 2768 5884 2207 63.9 MiB 0.09 0.00 4.21985 -115.841 -4.21985 4.21985 0.33 0.00064033 0.000594103 0.0392175 0.0364135 -1 -1 -1 -1 42 2281 32 6.95648e+06 318465 744469. 2576.02 1.40 0.175454 0.152417 27202 183097 -1 1639 21 1114 1829 140230 35033 4.10836 4.10836 -123.57 -4.10836 0 0 949917. 3286.91 0.04 0.07 0.15 -1 -1 0.04 0.0269904 0.0236075 70 24 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_052.v common 5.19 vpr 63.96 MiB -1 -1 0.16 18348 1 0.03 -1 -1 30124 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65500 32 32 319 257 1 191 80 17 17 289 -1 unnamed_device 24.2 MiB 0.86 1059 13152 4245 6889 2018 64.0 MiB 0.12 0.00 4.15748 -130.263 -4.15748 4.15748 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/home/elgamma8/research/release/vtr-verilog-to-routing 65452 32 32 341 285 1 183 79 17 17 289 -1 unnamed_device 24.2 MiB 0.89 876 11740 4893 6611 236 63.9 MiB 0.11 0.00 3.1615 -120.209 -3.1615 3.1615 0.33 0.000675863 0.000627489 0.0490628 0.0456216 -1 -1 -1 -1 42 2500 26 6.95648e+06 217135 744469. 2576.02 1.50 0.18957 0.165472 27202 183097 -1 2089 22 1764 2523 256092 54542 3.40957 3.40957 -131.031 -3.40957 0 0 949917. 3286.91 0.04 0.09 0.15 -1 -1 0.04 0.0290865 0.0252833 73 65 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_057.v common 6.03 vpr 64.38 MiB -1 -1 0.26 18368 1 0.03 -1 -1 30288 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65928 32 32 387 293 1 226 83 17 17 289 -1 unnamed_device 24.8 MiB 0.86 1199 13043 4951 6384 1708 64.4 MiB 0.14 0.00 4.83158 -154.41 -4.83158 4.83158 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66024 32 32 431 332 1 227 82 17 17 289 -1 unnamed_device 24.8 MiB 1.43 1077 13076 5478 7292 306 64.5 MiB 0.14 0.00 5.30235 -160.109 -5.30235 5.30235 0.33 0.000839666 0.00078032 0.064804 0.0602835 -1 -1 -1 -1 46 3075 31 6.95648e+06 260562 828058. 2865.25 1.52 0.244686 0.214294 28066 200906 -1 2516 23 2235 3373 300793 65578 4.88325 4.88325 -159.437 -4.88325 0 0 1.01997e+06 3529.29 0.04 0.11 0.16 -1 -1 0.04 0.0373225 0.0326244 95 65 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_061.v common 4.87 vpr 63.32 MiB -1 -1 0.15 18504 1 0.03 -1 -1 30536 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64840 32 32 336 268 1 169 89 17 17 289 -1 unnamed_device 24.4 MiB 0.98 769 14543 4279 7650 2614 63.3 MiB 0.13 0.00 4.37605 -128.976 -4.37605 4.37605 0.33 0.00068609 0.000637719 0.0529336 0.0491554 -1 -1 -1 -1 36 2640 45 6.95648e+06 361892 648988. 2245.63 1.95 0.220043 0.191748 26050 158493 -1 1899 19 1368 2103 168161 39340 4.52236 4.52236 -147.419 -4.52236 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0268261 0.0234869 75 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_062.v common 3.23 vpr 63.44 MiB -1 -1 0.21 17720 1 0.03 -1 -1 30332 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64964 32 32 231 199 1 136 81 17 17 289 -1 unnamed_device 23.9 MiB 0.17 862 10581 3669 5472 1440 63.4 MiB 0.08 0.00 2.966 -103.091 -2.966 2.966 0.33 0.000535623 0.000498652 0.0341868 0.0318378 -1 -1 -1 -1 34 2090 46 6.95648e+06 246087 618332. 2139.56 1.15 0.159354 0.137994 25762 151098 -1 1817 19 973 1591 134001 28878 2.85037 2.85037 -106.975 -2.85037 0 0 787024. 2723.27 0.03 0.06 0.12 -1 -1 0.03 0.0206185 0.0179498 55 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_063.v common 9.87 vpr 63.93 MiB -1 -1 0.25 18488 1 0.03 -1 -1 30120 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65464 32 32 349 273 1 184 95 17 17 289 -1 unnamed_device 24.1 MiB 0.34 1079 15647 5481 7915 2251 63.9 MiB 0.14 0.00 4.80547 -133.695 -4.80547 4.80547 0.34 0.000706749 0.000655878 0.0539142 0.0500534 -1 -1 -1 -1 36 3258 49 6.95648e+06 448746 648988. 2245.63 7.26 0.323114 0.280424 26050 158493 -1 2539 33 2032 3613 445607 138907 4.93896 4.93896 -147.631 -4.93896 0 0 828058. 2865.25 0.03 0.17 0.13 -1 -1 0.03 0.0442362 0.0384999 85 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_064.v common 2.85 vpr 63.78 MiB -1 -1 0.22 17988 1 0.03 -1 -1 30204 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65308 32 32 247 207 1 142 80 17 17 289 -1 unnamed_device 24.2 MiB 0.24 726 11088 4552 6360 176 63.8 MiB 0.09 0.00 2.9793 -102.962 -2.9793 2.9793 0.33 0.000555866 0.000516817 0.0383305 0.035649 -1 -1 -1 -1 32 2182 43 6.95648e+06 231611 586450. 2029.24 0.75 0.122287 0.107128 25474 144626 -1 1659 22 1307 1969 160538 36320 3.10097 3.10097 -116.017 -3.10097 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0134192 0.0118545 58 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_065.v common 4.25 vpr 63.77 MiB -1 -1 0.22 18148 1 0.03 -1 -1 30204 -1 -1 25 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65304 30 32 278 235 1 141 87 17 17 289 -1 unnamed_device 24.3 MiB 0.57 775 12567 4624 6004 1939 63.8 MiB 0.10 0.00 3.23198 -106.153 -3.23198 3.23198 0.35 0.000590718 0.000549282 0.0409618 0.0381017 -1 -1 -1 -1 36 1945 49 6.95648e+06 361892 648988. 2245.63 1.58 0.19865 0.172724 26050 158493 -1 1651 24 1219 1928 159003 35682 3.51472 3.51472 -122.539 -3.51472 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0269613 0.0233639 64 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_066.v common 5.16 vpr 63.41 MiB -1 -1 0.25 18380 1 0.03 -1 -1 30368 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64936 29 32 355 287 1 191 80 17 17 289 -1 unnamed_device 24.5 MiB 1.05 862 13840 5371 6156 2313 63.4 MiB 0.13 0.00 3.49789 -109.385 -3.49789 3.49789 0.33 0.000692113 0.000642977 0.05874 0.0545889 -1 -1 -1 -1 42 2967 32 6.95648e+06 275038 744469. 2576.02 1.93 0.213693 0.18699 27202 183097 -1 2258 20 1883 2806 223583 51789 3.35977 3.35977 -120.027 -3.35977 0 0 949917. 3286.91 0.04 0.08 0.15 -1 -1 0.04 0.0279475 0.0244354 81 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_067.v common 3.65 vpr 63.48 MiB -1 -1 0.25 18396 1 0.03 -1 -1 30320 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65000 32 32 358 289 1 171 83 17 17 289 -1 unnamed_device 24.5 MiB 0.52 803 13763 3951 8222 1590 63.5 MiB 0.13 0.00 4.16158 -131.727 -4.16158 4.16158 0.33 0.000704942 0.00065495 0.0566393 0.0526354 -1 -1 -1 -1 36 2250 32 6.95648e+06 275038 648988. 2245.63 1.05 0.205864 0.179723 26050 158493 -1 1841 23 1629 2363 177966 42287 4.23702 4.23702 -141.59 -4.23702 0 0 828058. 2865.25 0.03 0.08 0.13 -1 -1 0.03 0.031816 0.0277356 74 54 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_068.v common 4.55 vpr 63.49 MiB -1 -1 0.26 18396 1 0.03 -1 -1 30200 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65012 32 32 353 285 1 175 84 17 17 289 -1 unnamed_device 24.5 MiB 0.59 796 11064 4038 5325 1701 63.5 MiB 0.10 0.00 4.14068 -130.872 -4.14068 4.14068 0.33 0.000702369 0.000652314 0.0451848 0.0419956 -1 -1 -1 -1 42 2677 27 6.95648e+06 289514 744469. 2576.02 1.44 0.192639 0.167021 27202 183097 -1 2130 23 1519 2391 190633 45446 4.10536 4.10536 -140.291 -4.10536 0 0 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64896 31 32 319 272 1 165 78 17 17 289 -1 unnamed_device 24.2 MiB 1.36 768 11366 3602 6339 1425 63.4 MiB 0.10 0.00 3.45953 -112.445 -3.45953 3.45953 0.33 0.000648061 0.000602589 0.0466726 0.0434327 -1 -1 -1 -1 40 2406 47 6.95648e+06 217135 706193. 2443.58 6.67 0.308184 0.265354 26914 176310 -1 1941 30 1706 2536 269805 79255 3.50087 3.50087 -130.33 -3.50087 0 0 926341. 3205.33 0.04 0.12 0.14 -1 -1 0.04 0.0358129 0.0310119 66 64 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_071.v common 3.25 vpr 63.91 MiB -1 -1 0.27 18412 1 0.03 -1 -1 30368 -1 -1 29 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 65672 32 32 350 275 1 201 81 17 17 289 -1 unnamed_device 24.5 MiB 1.27 1129 13906 5547 6652 1707 64.1 MiB 0.15 0.00 4.25269 -145.404 -4.25269 4.25269 0.33 0.00070617 0.000655642 0.0622307 0.0578098 -1 -1 -1 -1 46 2914 38 6.95648e+06 246087 828058. 2865.25 1.96 0.211017 0.18524 28066 200906 -1 2416 22 1670 2541 234855 47792 4.12906 4.12906 -150.919 -4.12906 0 0 1.01997e+06 3529.29 0.04 0.09 0.16 -1 -1 0.04 0.0305654 0.0267071 83 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_077.v common 4.62 vpr 63.66 MiB -1 -1 0.15 18396 1 0.03 -1 -1 30276 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65184 32 32 385 308 1 176 91 17 17 289 -1 unnamed_device 24.6 MiB 0.98 819 15595 5661 7312 2622 63.7 MiB 0.14 0.00 4.05218 -132.756 -4.05218 4.05218 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/home/elgamma8/research/release/vtr-verilog-to-routing 65128 32 32 340 270 1 193 82 17 17 289 -1 unnamed_device 24.7 MiB 1.18 893 10762 4413 5950 399 63.6 MiB 0.10 0.00 4.53151 -135.826 -4.53151 4.53151 0.34 0.000687293 0.000638631 0.0444127 0.041307 -1 -1 -1 -1 44 2872 50 6.95648e+06 260562 787024. 2723.27 2.17 0.218431 0.190231 27778 195446 -1 2052 21 1735 2824 235601 56350 4.03512 4.03512 -138.699 -4.03512 0 0 997811. 3452.63 0.04 0.09 0.16 -1 -1 0.04 0.0293526 0.0257142 80 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_082.v common 4.77 vpr 64.19 MiB -1 -1 0.26 18356 1 0.03 -1 -1 30112 -1 -1 16 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65728 31 32 340 275 1 188 79 17 17 289 -1 unnamed_device 24.6 MiB 1.18 809 10557 4353 5772 432 64.2 MiB 0.10 0.00 5.4697 -148.249 -5.4697 5.4697 0.34 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0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64972 29 32 378 310 1 170 86 17 17 289 -1 unnamed_device 24.4 MiB 0.65 761 11048 4050 5112 1886 63.4 MiB 0.10 0.00 3.45953 -109.092 -3.45953 3.45953 0.33 0.00071549 0.000663573 0.0445526 0.0413859 -1 -1 -1 -1 36 2656 42 6.95648e+06 361892 648988. 2245.63 2.06 0.211083 0.183304 26050 158493 -1 2025 23 1711 2675 260514 63101 3.36572 3.36572 -118.625 -3.36572 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0319609 0.0278008 78 85 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_086.v common 3.67 vpr 63.50 MiB -1 -1 0.21 17852 1 0.03 -1 -1 30432 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 243 205 1 140 76 17 17 289 -1 unnamed_device 23.9 MiB 0.62 631 7916 2533 3644 1739 63.5 MiB 0.07 0.00 3.37543 -105.078 -3.37543 3.37543 0.34 0.000557086 0.000517598 0.0302229 0.0281436 -1 -1 -1 -1 36 1928 35 6.95648e+06 173708 648988. 2245.63 1.08 0.134647 0.116993 26050 158493 -1 1572 21 1088 1579 130575 31333 2.97567 2.97567 -108.699 -2.97567 0 0 828058. 2865.25 0.03 0.06 0.13 -1 -1 0.03 0.0238637 0.0206275 55 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_087.v common 6.31 vpr 64.27 MiB -1 -1 0.24 18476 1 0.03 -1 -1 30208 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65816 32 32 373 302 1 170 91 17 17 289 -1 unnamed_device 24.6 MiB 2.58 966 14983 5125 7592 2266 64.3 MiB 0.13 0.00 4.09512 -134.157 -4.09512 4.09512 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64992 31 32 245 205 1 144 79 17 17 289 -1 unnamed_device 23.9 MiB 0.21 813 9543 2639 6153 751 63.5 MiB 0.08 0.00 3.28943 -107.171 -3.28943 3.28943 0.33 0.000552058 0.000513941 0.0332108 0.0309347 -1 -1 -1 -1 30 2091 23 6.95648e+06 231611 556674. 1926.21 0.75 0.101378 0.0892292 25186 138497 -1 1788 22 1361 2041 160912 34813 2.97572 2.97572 -111.872 -2.97572 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0241773 0.0210133 59 4 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_091.v common 4.99 vpr 64.19 MiB -1 -1 0.24 18380 1 0.03 -1 -1 30480 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65732 32 32 348 274 1 203 82 17 17 289 -1 unnamed_device 24.6 MiB 1.05 911 13788 5176 6984 1628 64.2 MiB 0.13 0.00 4.12648 -135.504 -4.12648 4.12648 0.33 0.000699074 0.000649372 0.0567967 0.0528143 -1 -1 -1 -1 42 2629 45 6.95648e+06 260562 744469. 2576.02 1.88 0.220087 0.192147 27202 183097 -1 1945 23 2032 2844 200495 50646 3.92702 3.92702 -143.111 -3.92702 0 0 949917. 3286.91 0.03 0.05 0.11 -1 -1 0.03 0.0177332 0.0156956 82 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_092.v common 5.22 vpr 64.19 MiB -1 -1 0.15 18440 1 0.03 -1 -1 30296 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65728 32 32 356 289 1 195 87 17 17 289 -1 unnamed_device 24.6 MiB 0.74 1160 14487 4690 8180 1617 64.2 MiB 0.13 0.00 4.82888 -148.206 -4.82888 4.82888 0.33 0.000712138 0.000661648 0.0557283 0.0517813 -1 -1 -1 -1 34 3080 48 6.95648e+06 332941 618332. 2139.56 2.48 0.235318 0.205766 25762 151098 -1 2599 30 2158 3120 284278 71454 4.92206 4.92206 -162.846 -4.92206 0 0 787024. 2723.27 0.03 0.12 0.12 -1 -1 0.03 0.0391423 0.0339394 84 56 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_093.v common 3.98 vpr 63.39 MiB -1 -1 0.24 18200 1 0.03 -1 -1 30160 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64912 32 32 349 260 1 195 93 17 17 289 -1 unnamed_device 24.4 MiB 0.22 1004 12903 4488 6360 2055 63.4 MiB 0.12 0.00 4.68117 -141.413 -4.68117 4.68117 0.33 0.000720343 0.00066916 0.0469684 0.0436423 -1 -1 -1 -1 46 2499 25 6.95648e+06 419795 828058. 2865.25 1.60 0.19455 0.170056 28066 200906 -1 2004 22 1773 2931 237482 50990 4.37331 4.37331 -138.259 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-1 19 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65060 27 32 255 219 1 128 78 17 17 289 -1 unnamed_device 24.0 MiB 0.22 722 7050 2096 4338 616 63.5 MiB 0.06 0.00 2.9635 -93.8648 -2.9635 2.9635 0.33 0.000545241 0.00050719 0.0250802 0.0233661 -1 -1 -1 -1 30 1680 25 6.95648e+06 275038 556674. 1926.21 0.56 0.0935952 0.0816389 25186 138497 -1 1383 22 1105 1543 104085 23514 2.95552 2.95552 -103.065 -2.95552 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0237341 0.0205911 59 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_096.v common 5.41 vpr 64.35 MiB -1 -1 0.26 18844 1 0.03 -1 -1 30304 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65892 32 32 421 327 1 224 82 17 17 289 -1 unnamed_device 24.7 MiB 0.89 1281 15390 5999 6748 2643 64.3 MiB 0.16 0.00 3.89055 -132.538 -3.89055 3.89055 0.33 0.000813615 0.000756466 0.0730744 0.0678737 -1 -1 -1 -1 42 3669 39 6.95648e+06 260562 744469. 2576.02 2.12 0.258872 0.226973 27202 183097 -1 3041 54 3734 6186 866572 315736 4.00842 4.00842 -141.9 -4.00842 0 0 949917. 3286.91 0.04 0.33 0.15 -1 -1 0.04 0.0739409 0.0637852 93 65 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_097.v common 7.93 vpr 63.49 MiB -1 -1 0.21 18296 1 0.04 -1 -1 30416 -1 -1 17 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65016 31 32 365 296 1 191 80 17 17 289 -1 unnamed_device 24.5 MiB 3.68 1050 11776 4191 5452 2133 63.5 MiB 0.12 0.00 5.15055 -152.017 -5.15055 5.15055 0.35 0.000718301 0.000667584 0.0516793 0.0480382 -1 -1 -1 -1 38 2588 31 6.95648e+06 246087 678818. 2348.85 1.94 0.206918 0.180683 26626 170182 -1 2229 25 1746 2589 260957 73631 4.60096 4.60096 -155.355 -4.60096 0 0 902133. 3121.57 0.04 0.12 0.14 -1 -1 0.04 0.035326 0.030777 81 64 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_098.v common 6.94 vpr 63.92 MiB -1 -1 0.17 18372 1 0.03 -1 -1 30488 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65456 32 32 331 280 1 171 77 17 17 289 -1 unnamed_device 24.2 MiB 3.06 846 8879 3445 4513 921 63.9 MiB 0.09 0.00 3.71344 -127.299 -3.71344 3.71344 0.33 0.000662152 0.000616044 0.0396078 0.0367971 -1 -1 -1 -1 34 2721 49 6.95648e+06 188184 618332. 2139.56 1.88 0.20583 0.178674 25762 151098 -1 2098 21 1594 2255 229437 53251 3.98836 3.98836 -149.148 -3.98836 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0275507 0.0240338 69 65 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_099.v common 4.40 vpr 63.30 MiB -1 -1 0.24 18352 1 0.03 -1 -1 30464 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64820 32 32 326 263 1 169 91 17 17 289 -1 unnamed_device 24.2 MiB 0.19 870 13759 5668 7640 451 63.3 MiB 0.12 0.00 4.15778 -125.912 -4.15778 4.15778 0.33 0.000671759 0.00062482 0.0479104 0.0444404 -1 -1 -1 -1 38 2577 27 6.95648e+06 390843 678818. 2348.85 2.16 0.187441 0.163621 26626 170182 -1 1942 23 1477 2327 174711 43122 4.19391 4.19391 -133.252 -4.19391 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.0297229 0.0258967 78 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_100.v common 4.48 vpr 63.51 MiB -1 -1 0.13 18436 1 0.03 -1 -1 30584 -1 -1 26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65032 31 32 373 294 1 188 89 17 17 289 -1 unnamed_device 24.5 MiB 0.47 873 14543 4744 7116 2683 63.5 MiB 0.13 0.00 4.28865 -123.708 -4.28865 4.28865 0.33 0.000725918 0.000673454 0.0562397 0.05222 -1 -1 -1 -1 36 2840 47 6.95648e+06 376368 648988. 2245.63 1.95 0.231301 0.201645 26050 158493 -1 2024 22 1600 2407 161278 40379 4.11982 4.11982 -132.03 -4.11982 0 0 828058. 2865.25 0.03 0.08 0.13 -1 -1 0.03 0.0319741 0.0279464 86 50 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_101.v common 4.86 vpr 63.29 MiB -1 -1 0.23 18392 1 0.03 -1 -1 30376 -1 -1 26 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64812 30 32 325 268 1 165 88 17 17 289 -1 unnamed_device 24.2 MiB 0.47 772 13153 5458 7079 616 63.3 MiB 0.11 0.00 3.0694 -97.4086 -3.0694 3.0694 0.33 0.000653895 0.000606982 0.0467319 0.0433975 -1 -1 -1 -1 40 2419 50 6.95648e+06 376368 706193. 2443.58 2.36 0.206789 0.179782 26914 176310 -1 1811 25 1374 2302 189877 47043 3.14317 3.14317 -106.853 -3.14317 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0309509 0.0268435 73 51 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_102.v common 5.54 vpr 64.13 MiB -1 -1 0.23 18252 1 0.03 -1 -1 30276 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65668 32 32 350 275 1 209 82 17 17 289 -1 unnamed_device 24.5 MiB 0.97 990 11296 4658 6209 429 64.1 MiB 0.11 0.00 4.17918 -138.94 -4.17918 4.17918 0.33 0.000701844 0.000651419 0.0471705 0.0438467 -1 -1 -1 -1 56 2616 30 6.95648e+06 260562 973134. 3367.25 2.33 0.203793 0.178063 29794 239141 -1 2154 22 1945 2922 305600 70699 3.94732 3.94732 -136.513 -3.94732 0 0 1.19926e+06 4149.71 0.05 0.11 0.19 -1 -1 0.05 0.0317994 0.0278462 87 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_103.v common 4.21 vpr 63.58 MiB -1 -1 0.26 18312 1 0.03 -1 -1 30104 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65108 32 32 386 307 1 187 93 17 17 289 -1 unnamed_device 24.5 MiB 0.41 1037 8913 3105 4740 1068 63.6 MiB 0.08 0.00 3.51453 -125.823 -3.51453 3.51453 0.33 0.000744025 0.000689753 0.0342182 0.0318076 -1 -1 -1 -1 34 2812 26 6.95648e+06 419795 618332. 2139.56 1.61 0.190691 0.165539 25762 151098 -1 2314 20 1644 2351 206052 44179 3.21107 3.21107 -131.121 -3.21107 0 0 787024. 2723.27 0.03 0.09 0.12 -1 -1 0.03 0.0303118 0.026521 89 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_104.v common 5.39 vpr 63.66 MiB -1 -1 0.23 18188 1 0.03 -1 -1 30236 -1 -1 14 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65192 29 32 269 229 1 131 75 17 17 289 -1 unnamed_device 24.0 MiB 2.38 503 8765 3597 4670 498 63.7 MiB 0.07 0.00 3.77092 -99.7617 -3.77092 3.77092 0.34 0.000572882 0.00053298 0.0340432 0.0316733 -1 -1 -1 -1 36 1465 44 6.95648e+06 202660 648988. 2245.63 1.01 0.166036 0.14345 26050 158493 -1 1156 28 1151 1593 112172 28468 3.00497 3.00497 -101.661 -3.00497 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0297575 0.0257352 55 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_105.v common 7.27 vpr 63.48 MiB -1 -1 0.23 18364 1 0.03 -1 -1 30324 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65000 32 32 310 266 1 169 78 17 17 289 -1 unnamed_device 24.3 MiB 0.79 819 11864 4595 6100 1169 63.5 MiB 0.10 0.00 3.1157 -110.455 -3.1157 3.1157 0.33 0.000617386 0.000572641 0.0470302 0.0437382 -1 -1 -1 -1 38 2084 30 6.95648e+06 202660 678818. 2348.85 4.41 0.281604 0.242479 26626 170182 -1 1651 21 1499 1900 148274 33656 3.11207 3.11207 -115.72 -3.11207 0 0 902133. 3121.57 0.03 0.07 0.14 -1 -1 0.03 0.0261644 0.0227736 66 58 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_106.v common 13.24 vpr 63.42 MiB -1 -1 0.25 18348 1 0.08 -1 -1 30416 -1 -1 31 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64944 31 32 326 261 1 170 94 17 17 289 -1 unnamed_device 24.2 MiB 0.29 807 17347 5453 8954 2940 63.4 MiB 0.14 0.00 3.99218 -119.823 -3.99218 3.99218 0.33 0.000669928 0.000620402 0.0570896 0.0529137 -1 -1 -1 -1 38 2796 47 6.95648e+06 448746 678818. 2348.85 10.76 0.37726 0.326276 26626 170182 -1 2010 24 1596 2698 256761 68889 4.44846 4.44846 -129.239 -4.44846 0 0 902133. 3121.57 0.03 0.10 0.14 -1 -1 0.03 0.031009 0.0270206 80 33 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_107.v common 4.22 vpr 63.23 MiB -1 -1 0.25 17992 1 0.03 -1 -1 30348 -1 -1 16 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 29 32 262 224 1 162 77 17 17 289 -1 unnamed_device 24.2 MiB 0.73 751 10183 4226 5557 400 63.2 MiB 0.09 0.00 4.02427 -114.705 -4.02427 4.02427 0.34 0.000562056 0.000522712 0.0372432 0.0346484 -1 -1 -1 -1 36 2194 39 6.95648e+06 231611 648988. 2245.63 1.48 0.169094 0.146733 26050 158493 -1 1759 20 1128 1442 125538 30209 3.91432 3.91432 -123.418 -3.91432 0 0 828058. 2865.25 0.03 0.06 0.13 -1 -1 0.03 0.022937 0.0199794 66 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_108.v common 4.19 vpr 63.57 MiB -1 -1 0.20 18176 1 0.03 -1 -1 30004 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65096 32 32 278 238 1 144 76 17 17 289 -1 unnamed_device 24.2 MiB 0.99 681 10636 4393 6016 227 63.6 MiB 0.10 0.00 3.83566 -112.084 -3.83566 3.83566 0.33 0.000597626 0.000555977 0.0419891 0.0390707 -1 -1 -1 -1 40 1767 23 6.95648e+06 173708 706193. 2443.58 1.10 0.159787 0.139126 26914 176310 -1 1559 22 1276 1977 179411 40906 3.25122 3.25122 -115.603 -3.25122 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65324 31 32 265 230 1 159 77 17 17 289 -1 unnamed_device 24.3 MiB 1.45 950 11650 3937 6122 1591 63.8 MiB 0.10 0.00 3.38663 -109.663 -3.38663 3.38663 0.33 0.000568518 0.000528957 0.0431381 0.040133 -1 -1 -1 -1 34 2390 49 6.95648e+06 202660 618332. 2139.56 2.03 0.185926 0.161626 25762 151098 -1 2037 21 1191 1753 178422 38700 3.51307 3.51307 -126.052 -3.51307 0 0 787024. 2723.27 0.03 0.07 0.13 -1 -1 0.03 0.0243167 0.0212093 61 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_111.v common 4.51 vpr 63.45 MiB -1 -1 0.24 18408 1 0.03 -1 -1 30004 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 318 257 1 190 80 17 17 289 -1 unnamed_device 24.3 MiB 0.76 833 12292 3904 6196 2192 63.5 MiB 0.11 0.00 4.24288 -124.746 -4.24288 4.24288 0.33 0.000654747 0.00060808 0.0492224 0.0457578 -1 -1 -1 -1 40 2755 42 6.95648e+06 231611 706193. 2443.58 2.25 0.20883 0.182198 26914 176310 -1 1933 21 1493 2038 146228 37477 4.53772 4.53772 -141.377 -4.53772 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.028074 0.024611 76 30 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_116.v common 3.93 vpr 63.96 MiB -1 -1 0.22 18400 1 0.03 -1 -1 30096 -1 -1 25 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 65184 25 32 216 194 1 119 82 17 17 289 -1 unnamed_device 24.3 MiB 0.17 476 12186 4413 5265 2508 63.7 MiB 0.08 0.00 3.29759 -75.7686 -3.29759 3.29759 0.33 0.000479342 0.000443744 0.0344437 0.0319592 -1 -1 -1 -1 36 1639 41 6.95648e+06 361892 648988. 2245.63 1.21 0.144471 0.125015 26050 158493 -1 1187 21 863 1360 103903 26463 3.13012 3.13012 -84.3189 -3.13012 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0200072 0.0173432 55 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_127.v common 13.58 vpr 63.39 MiB -1 -1 0.23 18344 1 0.03 -1 -1 30268 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 32 32 376 307 1 179 78 17 17 289 -1 unnamed_device 24.4 MiB 0.69 806 10370 3831 4684 1855 63.4 MiB 0.10 0.00 3.9218 -122.886 -3.9218 3.9218 0.34 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-1 -1 18 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64980 27 32 259 221 1 152 77 17 17 289 -1 unnamed_device 23.8 MiB 0.34 572 10835 3549 5392 1894 63.5 MiB 0.09 0.00 3.41253 -95.9445 -3.41253 3.41253 0.33 0.000550141 0.000512325 0.038635 0.0359856 -1 -1 -1 -1 40 1445 25 6.99608e+06 264882 706193. 2443.58 1.11 0.149802 0.130204 26914 176310 -1 1146 23 1101 1637 114171 28235 3.23432 3.23432 -101.208 -3.23432 0 0 926341. 3205.33 0.04 0.06 0.14 -1 -1 0.04 0.0246258 0.0213493 65 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_008.v common 3.99 vpr 63.69 MiB -1 -1 0.22 17916 1 0.03 -1 -1 30120 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65220 31 32 271 219 1 157 90 17 17 289 -1 unnamed_device 24.4 MiB 0.17 727 10140 3383 5019 1738 63.7 MiB 0.08 0.00 2.73675 -88.7663 -2.73675 2.73675 0.33 0.000595211 0.00055369 0.0323175 0.030008 -1 -1 -1 -1 38 2221 27 6.99608e+06 397324 678818. 2348.85 1.89 0.157817 0.136976 26626 170182 -1 1662 18 1028 1750 116894 29647 3.01977 3.01977 -98.9875 -3.01977 0 0 902133. 3121.57 0.03 0.06 0.14 -1 -1 0.03 0.0219675 0.0191938 69 4 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_009.v common 4.50 vpr 63.79 MiB -1 -1 0.25 18444 1 0.03 -1 -1 30152 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65320 31 32 317 271 1 204 81 17 17 289 -1 unnamed_device 24.0 MiB 0.38 980 13556 5192 6525 1839 63.8 MiB 0.12 0.00 3.3916 -120.616 -3.3916 3.3916 0.33 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65092 32 32 276 237 1 165 78 17 17 289 -1 unnamed_device 23.9 MiB 0.38 879 10204 2698 5461 2045 63.6 MiB 0.09 0.00 3.35769 -110.064 -3.35769 3.35769 0.33 0.000592848 0.000552053 0.0387 0.0360475 -1 -1 -1 -1 38 2132 28 6.99608e+06 206020 678818. 2348.85 0.97 0.160199 0.139218 26626 170182 -1 1867 22 1244 1659 127512 28292 2.95567 2.95567 -112.42 -2.95567 0 0 902133. 3121.57 0.03 0.06 0.14 -1 -1 0.03 0.0255903 0.0222615 65 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_013.v common 11.21 vpr 64.02 MiB -1 -1 0.23 18352 1 0.03 -1 -1 30428 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65556 32 32 344 272 1 201 82 17 17 289 -1 unnamed_device 24.4 MiB 0.42 989 13788 5751 7551 486 64.0 MiB 0.13 0.00 3.85182 -127.119 -3.85182 3.85182 0.33 0.000695996 0.000645706 0.056467 0.0525052 -1 -1 -1 -1 40 2714 27 6.99608e+06 264882 706193. 2443.58 8.55 0.342056 0.295528 26914 176310 -1 2180 20 1618 2438 198461 44961 3.37586 3.37586 -121.862 -3.37586 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0280737 0.0245708 85 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_014.v common 4.89 vpr 63.34 MiB -1 -1 0.23 18476 1 0.03 -1 -1 30296 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64860 32 32 363 295 1 228 85 17 17 289 -1 unnamed_device 24.3 MiB 0.49 1022 13849 4401 6534 2914 63.3 MiB 0.13 0.00 4.71142 -142.574 -4.71142 4.71142 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/home/elgamma8/research/release/vtr-verilog-to-routing 65728 32 32 323 276 1 210 81 17 17 289 -1 unnamed_device 24.7 MiB 0.42 1112 13206 4762 6252 2192 64.2 MiB 0.12 0.00 2.94164 -116.816 -2.94164 2.94164 0.33 0.000653202 0.000607503 0.0515789 0.0479923 -1 -1 -1 -1 38 2627 37 6.99608e+06 250167 678818. 2348.85 2.14 0.19862 0.173499 26626 170182 -1 2110 21 1395 1843 145157 31738 2.96141 2.96141 -120.522 -2.96141 0 0 902133. 3121.57 0.04 0.07 0.15 -1 -1 0.04 0.0270508 0.0236021 83 65 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_019.v common 4.12 vpr 63.28 MiB -1 -1 0.22 18208 1 0.02 -1 -1 30056 -1 -1 14 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 30 32 222 206 1 135 76 17 17 289 -1 unnamed_device 24.1 MiB 0.27 523 9676 3992 5183 501 63.3 MiB 0.07 0.00 2.34646 -82.0889 -2.34646 2.34646 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65552 32 32 372 300 1 225 84 17 17 289 -1 unnamed_device 24.3 MiB 0.42 1287 11430 3124 6919 1387 64.0 MiB 0.12 0.00 4.28762 -137.056 -4.28762 4.28762 0.34 0.000725791 0.000674218 0.0481271 0.0447389 -1 -1 -1 -1 36 3638 47 6.99608e+06 294314 648988. 2245.63 2.54 0.226737 0.197277 26050 158493 -1 2909 22 2179 3181 270199 57321 4.16172 4.16172 -146.771 -4.16172 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0312828 0.0273115 97 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_023.v common 2.73 vpr 63.21 MiB -1 -1 0.19 18128 1 0.03 -1 -1 30684 -1 -1 16 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64728 26 32 190 182 1 123 74 17 17 289 -1 unnamed_device 23.7 MiB 0.24 509 11389 4872 5794 723 63.2 MiB 0.08 0.00 2.5304 -71.4335 -2.5304 2.5304 0.36 0.000430528 0.000399577 0.0334196 0.0310487 -1 -1 -1 -1 32 1512 40 6.99608e+06 235451 586450. 2029.24 0.67 0.0982233 0.0860666 25474 144626 -1 1053 19 675 830 60421 15815 2.32772 2.32772 -75.6559 -2.32772 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0167778 0.014619 51 30 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_024.v common 10.38 vpr 63.32 MiB -1 -1 0.13 17988 1 0.03 -1 -1 30404 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 32 32 285 227 1 160 81 17 17 289 -1 unnamed_device 24.0 MiB 0.46 809 9531 2907 4788 1836 63.3 MiB 0.08 0.00 4.23145 -111.771 -4.23145 4.23145 0.34 0.000616405 0.000573415 0.0358425 0.0333522 -1 -1 -1 -1 42 2262 42 6.99608e+06 250167 744469. 2576.02 7.98 0.31279 0.269362 27202 183097 -1 1628 23 1395 2382 183546 47317 3.75671 3.75671 -123.108 -3.75671 0 0 949917. 3286.91 0.04 0.08 0.14 -1 -1 0.04 0.0277763 0.0241395 66 3 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_025.v common 2.85 vpr 62.96 MiB -1 -1 0.21 17552 1 0.02 -1 -1 30000 -1 -1 10 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64468 32 32 173 169 1 111 74 17 17 289 -1 unnamed_device 23.6 MiB 0.11 432 8289 2731 4140 1418 63.0 MiB 0.06 0.00 2.03911 -66.1576 -2.03911 2.03911 0.34 0.00043102 0.000399846 0.0244169 0.0226669 -1 -1 -1 -1 34 1237 26 6.99608e+06 147157 618332. 2139.56 0.86 0.114623 0.0995893 25762 151098 -1 1004 18 606 753 61569 17014 1.93402 1.93402 -73.9607 -1.93402 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64620 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 24.0 MiB 0.17 933 10087 2140 7381 566 63.1 MiB 0.09 0.00 2.84195 -100.69 -2.84195 2.84195 0.34 0.000645685 0.000599204 0.0341485 0.0317824 -1 -1 -1 -1 36 2408 26 6.99608e+06 397324 648988. 2245.63 1.49 0.170187 0.148059 26050 158493 -1 1956 25 1433 2511 172697 38909 3.03892 3.03892 -108.258 -3.03892 0 0 828058. 2865.25 0.03 0.08 0.13 -1 -1 0.03 0.0302885 0.0263341 77 3 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_028.v common 4.63 vpr 63.82 MiB -1 -1 0.23 18284 1 0.03 -1 -1 30280 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65356 32 32 338 277 1 204 83 17 17 289 -1 unnamed_device 24.3 MiB 0.52 923 8003 1947 5085 971 63.8 MiB 0.09 0.00 4.17173 -123.211 -4.17173 4.17173 0.36 0.000695055 0.000646514 0.0331131 0.0308269 -1 -1 -1 -1 46 2562 33 6.99608e+06 279598 828058. 2865.25 1.99 0.189042 0.16453 28066 200906 -1 1783 21 1525 2326 154442 36408 3.79266 3.79266 -121.653 -3.79266 0 0 1.01997e+06 3529.29 0.04 0.07 0.16 -1 -1 0.04 0.0283844 0.0247975 86 50 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_029.v common 3.94 vpr 63.37 MiB -1 -1 0.23 18112 1 0.03 -1 -1 30208 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64892 32 32 284 241 1 168 78 17 17 289 -1 unnamed_device 24.1 MiB 0.70 870 11200 3386 5818 1996 63.4 MiB 0.10 0.00 3.16334 -110.479 -3.16334 3.16334 0.35 0.000610997 0.00056735 0.043289 0.0402908 -1 -1 -1 -1 34 2372 25 6.99608e+06 206020 618332. 2139.56 1.18 0.16887 0.147246 25762 151098 -1 1876 20 1333 1908 143533 32529 3.00782 3.00782 -119.005 -3.00782 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0242376 0.0211286 68 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_030.v common 3.73 vpr 63.51 MiB -1 -1 0.23 18100 1 0.03 -1 -1 30148 -1 -1 16 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 30 32 262 227 1 160 78 17 17 289 -1 unnamed_device 23.9 MiB 0.25 863 7216 1781 5114 321 63.5 MiB 0.07 0.00 3.77123 -111.817 -3.77123 3.77123 0.33 0.000564297 0.000525618 0.0265931 0.0247595 -1 -1 -1 -1 34 2210 47 6.99608e+06 235451 618332. 2139.56 1.44 0.1607 0.138405 25762 151098 -1 1918 20 1240 1920 164311 36185 3.63166 3.63166 -117.226 -3.63166 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0228113 0.0198785 65 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_031.v common 4.12 vpr 63.31 MiB -1 -1 0.24 18092 1 0.03 -1 -1 30088 -1 -1 20 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64832 28 32 260 223 1 152 80 17 17 289 -1 unnamed_device 23.7 MiB 0.28 611 12808 5071 5723 2014 63.3 MiB 0.10 0.00 3.4808 -106.362 -3.4808 3.4808 0.33 0.00055397 0.000515379 0.0431477 0.0400832 -1 -1 -1 -1 42 2077 35 6.99608e+06 294314 744469. 2576.02 1.76 0.166583 0.14464 27202 183097 -1 1523 23 1079 1820 147840 36523 3.50036 3.50036 -112.715 -3.50036 0 0 949917. 3286.91 0.04 0.07 0.17 -1 -1 0.04 0.025129 0.0218287 71 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_032.v common 3.51 vpr 63.40 MiB -1 -1 0.22 17868 1 0.03 -1 -1 30284 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 32 32 253 210 1 149 77 17 17 289 -1 unnamed_device 23.9 MiB 0.21 869 10835 2990 6954 891 63.4 MiB 0.09 0.00 3.30043 -111.689 -3.30043 3.30043 0.33 0.000571124 0.000531379 0.0397191 0.036997 -1 -1 -1 -1 38 1933 22 6.99608e+06 191304 678818. 2348.85 1.28 0.154408 0.134664 26626 170182 -1 1681 20 1206 1902 143421 30990 3.03062 3.03062 -114.764 -3.03062 0 0 902133. 3121.57 0.03 0.06 0.14 -1 -1 0.03 0.0227464 0.0198249 59 3 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_033.v common 3.57 vpr 63.41 MiB -1 -1 0.14 18096 1 0.03 -1 -1 30152 -1 -1 15 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64932 31 32 271 231 1 164 78 17 17 289 -1 unnamed_device 23.8 MiB 0.32 848 11200 4155 5330 1715 63.4 MiB 0.10 0.00 3.30638 -108.083 -3.30638 3.30638 0.33 0.000594049 0.000553686 0.041933 0.0390598 -1 -1 -1 -1 36 2468 47 6.99608e+06 220735 648988. 2245.63 1.38 0.18323 0.159726 26050 158493 -1 1921 22 1298 1864 154372 34321 3.07012 3.07012 -110.48 -3.07012 0 0 828058. 2865.25 0.06 0.08 0.11 -1 -1 0.06 0.0273368 0.02388 65 30 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_034.v common 3.43 vpr 63.68 MiB -1 -1 0.24 18268 1 0.03 -1 -1 30436 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65208 29 32 291 250 1 177 80 17 17 289 -1 unnamed_device 24.1 MiB 0.41 894 13840 5313 6055 2472 63.7 MiB 0.11 0.00 2.84515 -98.5413 -2.84515 2.84515 0.33 0.000596794 0.000555651 0.0503236 0.0468031 -1 -1 -1 -1 32 2473 34 6.99608e+06 279598 586450. 2029.24 1.01 0.134807 0.118765 25474 144626 -1 2001 19 1322 1717 133560 29772 2.71322 2.71322 -107.002 -2.71322 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0306834 0.0265408 77 54 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_035.v common 4.30 vpr 64.22 MiB -1 -1 0.13 18472 1 0.03 -1 -1 30424 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65764 32 32 367 282 1 214 86 17 17 289 -1 unnamed_device 24.6 MiB 0.33 1071 15773 6281 8017 1475 64.2 MiB 0.15 0.00 4.08568 -124.656 -4.08568 4.08568 0.33 0.000745003 0.000692275 0.0644112 0.0598632 -1 -1 -1 -1 40 2932 31 6.99608e+06 323745 706193. 2443.58 1.79 0.223533 0.196102 26914 176310 -1 2492 23 1688 2754 246406 62644 4.27126 4.27126 -132.221 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/home/elgamma8/research/release/vtr-verilog-to-routing 65556 31 32 370 297 1 227 86 17 17 289 -1 unnamed_device 24.4 MiB 0.43 1217 14072 4085 8314 1673 64.0 MiB 0.07 0.00 3.60415 -128.157 -3.60415 3.60415 0.25 0.000323073 0.000297377 0.0260474 0.0240278 -1 -1 -1 -1 40 2752 44 6.99608e+06 338461 706193. 2443.58 1.49 0.192261 0.16592 26914 176310 -1 2485 21 1636 2359 186290 40291 3.67861 3.67861 -135.017 -3.67861 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0300731 0.0262642 99 61 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_039.v common 4.59 vpr 63.48 MiB -1 -1 0.28 18352 1 0.03 -1 -1 30284 -1 -1 22 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65008 31 32 377 302 1 235 85 17 17 289 -1 unnamed_device 24.4 MiB 0.41 1068 13477 4250 6738 2489 63.5 MiB 0.13 0.00 5.0573 -155.975 -5.0573 5.0573 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/home/elgamma8/research/release/vtr-verilog-to-routing 65492 32 32 353 287 1 209 82 17 17 289 -1 unnamed_device 24.4 MiB 0.46 1220 8092 1924 5321 847 64.0 MiB 0.09 0.00 3.85238 -122.663 -3.85238 3.85238 0.34 0.000716879 0.000666652 0.0349023 0.0324524 -1 -1 -1 -1 36 2897 23 6.99608e+06 264882 648988. 2245.63 1.53 0.182246 0.158709 26050 158493 -1 2508 21 1547 2144 170292 36759 3.35806 3.35806 -125.954 -3.35806 0 0 828058. 2865.25 0.03 0.08 0.13 -1 -1 0.03 0.0295558 0.0258317 90 55 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_049.v common 4.34 vpr 63.87 MiB -1 -1 0.25 18368 1 0.03 -1 -1 30260 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65400 32 32 361 291 1 214 86 17 17 289 -1 unnamed_device 24.3 MiB 0.51 1060 15017 4116 9319 1582 63.9 MiB 0.15 0.00 3.54419 -122.946 -3.54419 3.54419 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/home/elgamma8/research/release/vtr-verilog-to-routing 65140 31 32 373 299 1 223 85 17 17 289 -1 unnamed_device 24.5 MiB 0.43 1149 13663 5356 6563 1744 63.6 MiB 0.14 0.00 4.32027 -135.237 -4.32027 4.32027 0.36 0.000721821 0.000670744 0.056146 0.0521455 -1 -1 -1 -1 40 3112 25 6.99608e+06 323745 706193. 2443.58 1.16 0.145809 0.129022 26914 176310 -1 2617 22 2047 3207 244307 54446 3.98626 3.98626 -135.777 -3.98626 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0310617 0.0270555 100 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_054.v common 4.66 vpr 63.48 MiB -1 -1 0.24 18356 1 0.03 -1 -1 30420 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65008 32 32 387 315 1 239 84 17 17 289 -1 unnamed_device 24.4 MiB 0.53 1208 10332 3432 4948 1952 63.5 MiB 0.11 0.00 4.04752 -134.676 -4.04752 4.04752 0.33 0.000750424 0.000697188 0.0448985 0.0417269 -1 -1 -1 -1 40 3452 41 6.99608e+06 294314 706193. 2443.58 1.78 0.214316 0.186475 26914 176310 -1 2865 20 2129 3202 274718 60596 4.10366 4.10366 -143.201 -4.10366 0 0 926341. 3205.33 0.04 0.12 0.18 -1 -1 0.04 0.038728 0.0339315 104 77 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_055.v common 3.16 vpr 63.21 MiB -1 -1 0.17 18024 1 0.03 -1 -1 30400 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64724 32 32 251 219 1 151 76 17 17 289 -1 unnamed_device 23.7 MiB 0.22 902 5996 1423 4213 360 63.2 MiB 0.07 0.00 3.24518 -106.32 -3.24518 3.24518 0.34 0.00056176 0.00052322 0.0230302 0.0214129 -1 -1 -1 -1 38 2061 22 6.99608e+06 176588 678818. 2348.85 1.09 0.135173 0.116914 26626 170182 -1 1739 19 995 1488 114516 24820 2.76922 2.76922 -103.921 -2.76922 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/home/elgamma8/research/release/vtr-verilog-to-routing 64820 32 32 353 285 1 210 82 17 17 289 -1 unnamed_device 24.3 MiB 0.53 1034 11652 4187 4869 2596 63.3 MiB 0.12 0.00 4.57817 -141.46 -4.57817 4.57817 0.34 0.000705394 0.000654779 0.0487977 0.0453192 -1 -1 -1 -1 40 2926 29 6.99608e+06 264882 706193. 2443.58 1.94 0.20213 0.1763 26914 176310 -1 2361 20 1727 2500 217768 50608 4.35045 4.35045 -146.549 -4.35045 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0291737 0.0255574 91 51 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_069.v common 4.39 vpr 63.36 MiB -1 -1 0.23 18088 1 0.03 -1 -1 30020 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64884 32 32 276 237 1 160 78 17 17 289 -1 unnamed_device 24.0 MiB 0.43 717 10536 3258 5329 1949 63.4 MiB 0.09 0.00 3.47185 -106.975 -3.47185 3.47185 0.34 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/home/elgamma8/research/release/vtr-verilog-to-routing 64868 30 32 317 269 1 200 81 17 17 289 -1 unnamed_device 24.1 MiB 0.37 1051 7256 1625 5219 412 63.3 MiB 0.08 0.00 4.19642 -135.689 -4.19642 4.19642 0.33 0.000641856 0.000596751 0.0288339 0.0268375 -1 -1 -1 -1 36 2537 33 6.99608e+06 279598 648988. 2245.63 1.35 0.166224 0.143652 26050 158493 -1 2196 23 1975 2671 215318 47546 3.80181 3.80181 -135.851 -3.80181 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0159451 0.0140711 84 63 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_074.v common 5.49 vpr 63.22 MiB -1 -1 0.23 18368 1 0.03 -1 -1 30212 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64740 32 32 335 282 1 216 82 17 17 289 -1 unnamed_device 24.2 MiB 0.39 930 12542 4675 5838 2029 63.2 MiB 0.12 0.00 3.0313 -115.382 -3.0313 3.0313 0.33 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30084 -1 -1 19 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65440 31 32 340 275 1 195 82 17 17 289 -1 unnamed_device 24.4 MiB 0.61 919 7736 2635 4162 939 63.9 MiB 0.08 0.00 5.0765 -140.835 -5.0765 5.0765 0.34 0.000683595 0.000635788 0.0323016 0.0300513 -1 -1 -1 -1 40 2827 34 6.99608e+06 279598 706193. 2443.58 2.01 0.183624 0.159375 26914 176310 -1 1996 18 1403 2053 154708 36864 4.34151 4.34151 -139.438 -4.34151 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.0256852 0.022549 87 47 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_083.v common 4.34 vpr 64.08 MiB -1 -1 0.26 18548 1 0.03 -1 -1 30088 -1 -1 24 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65616 30 32 377 310 1 234 86 17 17 289 -1 unnamed_device 24.3 MiB 0.48 1149 6134 1189 4745 200 64.1 MiB 0.08 0.00 4.12466 -127.491 -4.12466 4.12466 0.34 0.000726629 0.000675798 0.0261685 0.0243289 -1 -1 -1 -1 38 3100 45 6.99608e+06 353176 678818. 2348.85 1.79 0.202351 0.174984 26626 170182 -1 2499 22 2217 3173 237661 53581 3.66761 3.66761 -131.006 -3.66761 0 0 902133. 3121.57 0.03 0.09 0.14 -1 -1 0.03 0.0311754 0.0271766 106 83 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_084.v common 4.50 vpr 63.91 MiB -1 -1 0.26 18392 1 0.03 -1 -1 30268 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65440 32 32 365 294 1 223 83 17 17 289 -1 unnamed_device 24.3 MiB 0.51 1094 12143 4447 5317 2379 63.9 MiB 0.13 0.00 4.71643 -147.438 -4.71643 4.71643 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21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65648 32 32 373 302 1 234 85 17 17 289 -1 unnamed_device 24.4 MiB 0.27 1243 16081 5953 7939 2189 64.1 MiB 0.16 0.00 4.8168 -157 -4.8168 4.8168 0.26 0.000731852 0.000679799 0.0658794 0.0611482 -1 -1 -1 -1 40 2915 24 6.99608e+06 309029 706193. 2443.58 1.51 0.221118 0.194285 26914 176310 -1 2455 21 1930 2730 203339 43779 5.01301 5.01301 -164.294 -5.01301 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.030157 0.026347 99 65 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_088.v common 5.66 vpr 64.08 MiB -1 -1 0.24 18396 1 0.03 -1 -1 30260 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65616 32 32 397 314 1 249 85 17 17 289 -1 unnamed_device 24.6 MiB 0.46 1158 15523 5731 7092 2700 64.1 MiB 0.15 0.00 4.69632 -158.476 -4.69632 4.69632 0.36 0.000762962 0.000708836 0.0665301 0.0618197 -1 -1 -1 -1 38 3758 42 6.99608e+06 309029 678818. 2348.85 3.07 0.255062 0.223742 26626 170182 -1 2698 21 2446 3392 270440 61960 4.80151 4.80151 -168.488 -4.80151 0 0 902133. 3121.57 0.03 0.06 0.10 -1 -1 0.03 0.0180729 0.0160962 105 65 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_089.v common 3.97 vpr 63.32 MiB -1 -1 0.23 18196 1 0.04 -1 -1 30352 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64836 32 32 269 231 1 163 78 17 17 289 -1 unnamed_device 23.7 MiB 0.32 733 12528 5239 6931 358 63.3 MiB 0.11 0.00 3.76077 -112.543 -3.76077 3.76077 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-1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65652 32 32 356 289 1 217 82 17 17 289 -1 unnamed_device 24.4 MiB 0.45 1087 8448 3166 4532 750 64.1 MiB 0.09 0.00 4.61807 -140.276 -4.61807 4.61807 0.33 0.000707102 0.000656576 0.0369544 0.034304 -1 -1 -1 -1 34 3563 30 6.99608e+06 264882 618332. 2139.56 1.99 0.187407 0.162638 25762 151098 -1 2617 25 2032 2765 272549 80736 4.66331 4.66331 -154.076 -4.66331 0 0 787024. 2723.27 0.03 0.12 0.12 -1 -1 0.03 0.0348237 0.0303706 91 56 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_093.v common 4.28 vpr 63.95 MiB -1 -1 0.25 18204 1 0.03 -1 -1 30132 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65488 32 32 349 260 1 195 93 17 17 289 -1 unnamed_device 24.4 MiB 0.20 1086 13533 4315 6748 2470 64.0 MiB 0.13 0.00 4.52621 -140.196 -4.52621 4.52621 0.33 0.000723358 0.00066428 0.0494366 0.0457611 -1 -1 -1 -1 38 2778 46 6.99608e+06 426755 678818. 2348.85 1.90 0.22108 0.192512 26626 170182 -1 2295 21 1739 3136 215099 47757 4.5307 4.5307 -144.202 -4.5307 0 0 902133. 3121.57 0.03 0.09 0.14 -1 -1 0.03 0.0300168 0.0261575 90 3 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_094.v common 4.68 vpr 63.35 MiB -1 -1 0.26 18260 1 0.03 -1 -1 30392 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 30 32 316 264 1 192 84 17 17 289 -1 unnamed_device 24.1 MiB 0.46 927 14175 4952 6503 2720 63.3 MiB 0.12 0.00 3.59117 -104.78 -3.59117 3.59117 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65552 31 32 365 296 1 229 84 17 17 289 -1 unnamed_device 24.4 MiB 0.41 1271 10515 2847 5946 1722 64.0 MiB 0.11 0.00 5.41693 -155.818 -5.41693 5.41693 0.34 0.000714768 0.000664242 0.0440555 0.0409587 -1 -1 -1 -1 40 2971 24 6.99608e+06 309029 706193. 2443.58 1.68 0.194532 0.169876 26914 176310 -1 2506 19 1927 2738 217010 45892 4.58734 4.58734 -155.424 -4.58734 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0158808 0.0141898 96 64 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_098.v common 3.88 vpr 63.83 MiB -1 -1 0.25 18352 1 0.03 -1 -1 30360 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65364 32 32 331 280 1 215 82 17 17 289 -1 unnamed_device 24.3 MiB 0.41 1019 12898 5003 5774 2121 63.8 MiB 0.12 0.00 4.02148 -135.181 -4.02148 4.02148 0.34 0.000675106 0.000626565 0.0511943 0.0476231 -1 -1 -1 -1 40 2554 27 6.99608e+06 264882 706193. 2443.58 1.32 0.190559 0.166595 26914 176310 -1 2119 21 1505 2040 162418 36238 3.52995 3.52995 -133.179 -3.52995 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.0276916 0.0241046 87 65 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_099.v common 3.90 vpr 64.20 MiB -1 -1 0.12 18384 1 0.03 -1 -1 30420 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65736 32 32 326 263 1 198 81 17 17 289 -1 unnamed_device 24.5 MiB 0.35 947 12506 5206 6883 417 64.2 MiB 0.12 0.00 4.17438 -127.536 -4.17438 4.17438 0.34 0.000670822 0.000624314 0.0505488 0.0470101 -1 -1 -1 -1 40 2648 27 6.99608e+06 250167 706193. 2443.58 1.61 0.192834 0.168737 26914 176310 -1 2105 21 1427 1931 160580 36723 3.62241 3.62241 -127.407 -3.62241 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.0276199 0.0241137 80 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_100.v common 4.13 vpr 63.98 MiB -1 -1 0.26 18396 1 0.03 -1 -1 30400 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65516 31 32 373 294 1 217 84 17 17 289 -1 unnamed_device 24.3 MiB 0.41 991 13077 4725 6680 1672 64.0 MiB 0.13 0.00 4.19793 -122.509 -4.19793 4.19793 0.34 0.000731044 0.000678936 0.0555421 0.0516292 -1 -1 -1 -1 40 2836 26 6.99608e+06 309029 706193. 2443.58 1.62 0.214199 0.187745 26914 176310 -1 2141 23 1964 2996 200616 48065 3.88241 3.88241 -125.837 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-1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64928 32 32 350 275 1 209 82 17 17 289 -1 unnamed_device 24.3 MiB 0.40 979 11296 4199 5586 1511 63.4 MiB 0.11 0.00 4.18128 -137.803 -4.18128 4.18128 0.35 0.000700566 0.000651095 0.0474618 0.044136 -1 -1 -1 -1 40 3397 41 6.99608e+06 264882 706193. 2443.58 10.45 0.385824 0.332557 26914 176310 -1 2446 25 2427 3705 324428 72341 4.38436 4.38436 -149.497 -4.38436 0 0 926341. 3205.33 0.04 0.11 0.14 -1 -1 0.04 0.0341054 0.0297049 87 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_103.v common 10.20 vpr 64.19 MiB -1 -1 0.24 18476 1 0.03 -1 -1 30092 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65728 32 32 386 307 1 240 85 17 17 289 -1 unnamed_device 24.5 MiB 0.41 1172 14779 4944 7940 1895 64.2 MiB 0.14 0.00 3.49383 -123.038 -3.49383 3.49383 0.35 0.000744675 0.000690682 0.0623874 0.0579082 -1 -1 -1 -1 38 3062 42 6.99608e+06 309029 678818. 2348.85 7.53 0.401185 0.347255 26626 170182 -1 2503 21 2030 2756 207605 45774 3.22392 3.22392 -130.363 -3.22392 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0313101 0.0274444 101 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_104.v common 3.37 vpr 63.54 MiB -1 -1 0.22 18176 1 0.03 -1 -1 30312 -1 -1 17 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65068 29 32 269 229 1 166 78 17 17 289 -1 unnamed_device 23.9 MiB 0.27 653 11698 4829 5917 952 63.5 MiB 0.10 0.00 3.87612 -110.458 -3.87612 3.87612 0.33 0.000576824 0.00053597 0.0425092 0.0395708 -1 -1 -1 -1 36 1983 34 6.99608e+06 250167 648988. 2245.63 1.06 0.166516 0.144952 26050 158493 -1 1462 21 1445 1913 139306 32789 3.36942 3.36942 -114.909 -3.36942 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0246534 0.0215084 68 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_105.v common 3.78 vpr 63.19 MiB -1 -1 0.23 18272 1 0.03 -1 -1 30280 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 32 32 310 266 1 184 80 17 17 289 -1 unnamed_device 24.0 MiB 0.39 769 12292 3548 6982 1762 63.2 MiB 0.11 0.00 3.56989 -117.422 -3.56989 3.56989 0.34 0.000639731 0.000595039 0.0476767 0.0443352 -1 -1 -1 -1 48 1921 23 6.99608e+06 235451 865456. 2994.66 1.32 0.176243 0.153877 28354 207349 -1 1369 21 1242 1698 118545 29084 3.32086 3.32086 -112.996 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30324 -1 -1 16 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 29 32 262 224 1 162 77 17 17 289 -1 unnamed_device 23.8 MiB 0.36 695 10346 4286 5606 454 63.4 MiB 0.09 0.00 3.75967 -107.452 -3.75967 3.75967 0.33 0.000564484 0.000525149 0.0379166 0.0352817 -1 -1 -1 -1 42 2064 29 6.99608e+06 235451 744469. 2576.02 1.18 0.155295 0.134907 27202 183097 -1 1555 21 1113 1458 123164 29262 3.29971 3.29971 -107.37 -3.29971 0 0 949917. 3286.91 0.04 0.06 0.15 -1 -1 0.04 0.0233802 0.0203302 67 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_108.v common 3.91 vpr 63.50 MiB -1 -1 0.23 18172 1 0.03 -1 -1 30120 -1 -1 15 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 278 238 1 178 79 17 17 289 -1 unnamed_device 24.4 MiB 0.31 796 9881 3787 3524 2570 63.5 MiB 0.08 0.00 3.83776 -116.677 -3.83776 3.83776 0.34 0.000602466 0.000560405 0.0375036 0.0348051 -1 -1 -1 -1 40 2236 47 6.99608e+06 220735 706193. 2443.58 1.65 0.18307 0.158721 26914 176310 -1 1723 22 1490 2039 151424 35617 3.27792 3.27792 -122.849 -3.27792 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.0262726 0.0228775 70 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_109.v common 3.86 vpr 64.20 MiB -1 -1 0.16 18264 1 0.03 -1 -1 30352 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65736 31 32 373 300 1 230 86 17 17 289 -1 unnamed_device 24.5 MiB 0.40 1185 13505 4820 6538 2147 64.2 MiB 0.13 0.00 4.07096 -136.622 -4.07096 4.07096 0.34 0.000729681 0.000677527 0.0547725 0.0508854 -1 -1 -1 -1 42 2958 22 6.99608e+06 338461 744469. 2576.02 1.31 0.208461 0.182792 27202 183097 -1 2422 18 1969 2848 217495 47098 3.51536 3.51536 -133.165 -3.51536 0 0 949917. 3286.91 0.04 0.08 0.15 -1 -1 0.04 0.0276423 0.0242731 100 64 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_110.v common 4.04 vpr 63.46 MiB -1 -1 0.24 18104 1 0.03 -1 -1 30292 -1 -1 15 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64988 31 32 265 230 1 170 78 17 17 289 -1 unnamed_device 23.8 MiB 0.36 907 8876 2820 4643 1413 63.5 MiB 0.08 0.00 3.24748 -103.016 -3.24748 3.24748 0.33 0.00057241 0.000532529 0.032623 0.0303397 -1 -1 -1 -1 36 2282 37 6.99608e+06 220735 648988. 2245.63 1.56 0.159617 0.138207 26050 158493 -1 1955 18 1210 1690 151023 32590 3.12312 3.12312 -115.765 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-1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65700 31 32 396 325 1 257 87 17 17 289 -1 unnamed_device 24.6 MiB 0.44 1349 14103 4011 7972 2120 64.2 MiB 0.14 0.00 4.40154 -151.265 -4.40154 4.40154 0.33 0.000751009 0.00069733 0.0583701 0.0541383 -1 -1 -1 -1 38 3173 30 6.99608e+06 353176 678818. 2348.85 1.58 0.224464 0.196682 26626 170182 -1 2642 24 2358 3345 246804 52357 4.09905 4.09905 -148.278 -4.09905 0 0 902133. 3121.57 0.03 0.10 0.14 -1 -1 0.03 0.034493 0.0300425 111 91 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_113.v common 3.68 vpr 63.35 MiB -1 -1 0.16 18120 1 0.03 -1 -1 30264 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 303 262 1 189 80 17 17 289 -1 unnamed_device 24.2 MiB 0.39 882 11604 4388 5877 1339 63.3 MiB 0.11 0.00 3.12442 -108.534 -3.12442 3.12442 0.33 0.000626026 0.000581342 0.0442632 0.0411357 -1 -1 -1 -1 40 2100 25 6.99608e+06 235451 706193. 2443.58 1.25 0.169644 0.147609 26914 176310 -1 1761 21 1458 2022 155648 35832 3.10012 3.10012 -112.487 -3.10012 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.0262352 0.0228162 80 57 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_114.v common 3.73 vpr 63.70 MiB -1 -1 0.13 18116 1 0.02 -1 -1 30224 -1 -1 15 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65224 32 32 290 244 1 174 79 17 17 289 -1 unnamed_device 24.1 MiB 0.38 908 12585 5135 6794 656 63.7 MiB 0.11 0.00 3.42763 -113.296 -3.42763 3.42763 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/home/elgamma8/research/release/vtr-verilog-to-routing 64692 31 32 229 197 1 138 78 17 17 289 -1 unnamed_device 23.7 MiB 0.48 649 8378 3363 4684 331 63.2 MiB 0.07 0.00 3.20338 -90.6125 -3.20338 3.20338 0.33 0.000536852 0.000500057 0.0285834 0.0266282 -1 -1 -1 -1 38 1740 26 6.99608e+06 220735 678818. 2348.85 1.36 0.137751 0.119285 26626 170182 -1 1408 23 1078 1745 129004 28747 2.71597 2.71597 -95.6168 -2.71597 0 0 902133. 3121.57 0.03 0.06 0.14 -1 -1 0.03 0.0241496 0.0209859 55 4 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_119.v common 4.78 vpr 64.14 MiB -1 -1 0.26 18268 1 0.03 -1 -1 30284 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65676 32 32 412 334 1 258 87 17 17 289 -1 unnamed_device 24.6 MiB 0.43 1319 11991 3957 5960 2074 64.1 MiB 0.12 0.00 4.93268 -164.708 -4.93268 4.93268 0.33 0.000771802 0.0007156 0.0512591 0.0475308 -1 -1 -1 -1 36 4054 47 6.99608e+06 338461 648988. 2245.63 2.21 0.243207 0.211496 26050 158493 -1 2858 22 2200 2781 251702 57095 5.2633 5.2633 -181.627 -5.2633 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0334506 0.0292332 114 90 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_120.v common 4.24 vpr 64.18 MiB -1 -1 0.15 18404 1 0.03 -1 -1 30156 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65716 32 32 376 318 1 253 86 17 17 289 -1 unnamed_device 24.5 MiB 0.45 1337 12182 2801 8441 940 64.2 MiB 0.12 0.00 4.37262 -158.739 -4.37262 4.37262 0.37 0.000711764 0.00066043 0.0487485 0.0452791 -1 -1 -1 -1 46 2963 26 6.99608e+06 323745 828058. 2865.25 1.71 0.203017 0.17733 28066 200906 -1 2457 21 1963 2529 189545 39868 4.11305 4.11305 -157.703 -4.11305 0 0 1.01997e+06 3529.29 0.04 0.08 0.16 -1 -1 0.04 0.0298197 0.0260554 105 96 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_121.v common 4.40 vpr 63.93 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30296 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65468 32 32 360 293 1 219 83 17 17 289 -1 unnamed_device 24.3 MiB 0.39 1211 12683 3755 7514 1414 63.9 MiB 0.12 0.00 3.36853 -122.175 -3.36853 3.36853 0.34 0.000707294 0.000657276 0.0529326 0.049187 -1 -1 -1 -1 38 2800 43 6.99608e+06 279598 678818. 2348.85 1.88 0.220766 0.19246 26626 170182 -1 2343 24 1786 2393 200580 41794 3.23592 3.23592 -123.11 -3.23592 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.0326012 0.0283387 94 60 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_122.v common 12.44 vpr 64.27 MiB -1 -1 0.24 18692 1 0.03 -1 -1 30400 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65812 32 32 396 299 1 231 85 17 17 289 -1 unnamed_device 24.5 MiB 0.32 1108 13105 3671 7584 1850 64.3 MiB 0.14 0.00 5.6322 -158.993 -5.6322 5.6322 0.33 0.000777235 0.000722016 0.0575258 0.0534752 -1 -1 -1 -1 44 3147 38 6.99608e+06 309029 787024. 2723.27 9.94 0.396837 0.342694 27778 195446 -1 2287 34 2017 3107 304138 115013 4.85505 4.85505 -154.503 -4.85505 0 0 997811. 3452.63 0.04 0.15 0.16 -1 -1 0.04 0.0485984 0.0422188 99 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_123.v common 3.20 vpr 63.57 MiB -1 -1 0.17 18072 1 0.03 -1 -1 30108 -1 -1 13 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65100 30 32 224 207 1 134 75 17 17 289 -1 unnamed_device 24.1 MiB 0.28 577 10029 4242 5446 341 63.6 MiB 0.08 0.00 2.33546 -85.6612 -2.33546 2.33546 0.33 0.000504067 0.000469255 0.0336791 0.0313571 -1 -1 -1 -1 36 1749 31 6.99608e+06 191304 648988. 2245.63 1.08 0.138424 0.120065 26050 158493 -1 1357 21 893 1110 100119 24717 2.39608 2.39608 -90.4929 -2.39608 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0205929 0.0178716 52 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_124.v common 5.20 vpr 63.46 MiB -1 -1 0.12 18016 1 0.03 -1 -1 30352 -1 -1 16 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64980 30 32 286 239 1 159 78 17 17 289 -1 unnamed_device 24.1 MiB 1.18 829 10868 4869 5663 336 63.5 MiB 0.09 0.00 3.98607 -129.511 -3.98607 3.98607 0.33 0.000597854 0.000554481 0.0409971 0.0380891 -1 -1 -1 -1 36 2107 25 6.99608e+06 235451 648988. 2245.63 2.17 0.233413 0.20137 26050 158493 -1 1748 17 1098 1623 130284 30423 3.71161 3.71161 -136.48 -3.71161 0 0 828058. 2865.25 0.03 0.06 0.13 -1 -1 0.03 0.0214257 0.018737 71 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_125.v common 4.67 vpr 63.82 MiB -1 -1 0.23 18140 1 0.03 -1 -1 30060 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65348 32 32 296 247 1 182 85 17 17 289 -1 unnamed_device 24.2 MiB 0.32 859 13477 5604 7598 275 63.8 MiB 0.12 0.00 3.71535 -130.45 -3.71535 3.71535 0.36 0.000628988 0.00058134 0.0476797 0.0443348 -1 -1 -1 -1 38 2908 46 6.99608e+06 309029 678818. 2348.85 2.29 0.197424 0.171974 26626 170182 -1 2101 23 1401 2302 222408 54792 4.32052 4.32052 -140.632 -4.32052 0 0 902133. 3121.57 0.04 0.09 0.14 -1 -1 0.04 0.0284077 0.0247235 77 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_126.v common 3.44 vpr 63.14 MiB -1 -1 0.21 18088 1 0.03 -1 -1 30336 -1 -1 19 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64660 25 32 216 194 1 134 76 17 17 289 -1 unnamed_device 23.8 MiB 0.25 507 10956 4030 4533 2393 63.1 MiB 0.08 0.00 3.37063 -78.72 -3.37063 3.37063 0.33 0.000480281 0.000446164 0.0343935 0.0319653 -1 -1 -1 -1 38 1738 27 6.99608e+06 279598 678818. 2348.85 1.26 0.132985 0.115295 26626 170182 -1 1108 17 744 1072 69349 18454 3.14737 3.14737 -85.6299 -3.14737 0 0 902133. 3121.57 0.03 0.04 0.14 -1 -1 0.03 0.0171683 0.0150118 56 29 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_127.v common 6.40 vpr 63.52 MiB -1 -1 0.25 18276 1 0.03 -1 -1 30348 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65044 32 32 376 307 1 230 83 17 17 289 -1 unnamed_device 24.4 MiB 0.51 1070 13583 5650 7491 442 63.5 MiB 0.13 0.00 4.04452 -130.09 -4.04452 4.04452 0.34 0.000728734 0.000675996 0.0578889 0.0536675 -1 -1 -1 -1 40 3557 32 6.99608e+06 279598 706193. 2443.58 3.62 0.22235 0.194456 26914 176310 -1 2744 21 2050 3040 252988 64010 4.43451 4.43451 -145.309 -4.43451 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0305214 0.0266633 100 72 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_128.v common 4.47 vpr 63.53 MiB -1 -1 0.26 18432 1 0.03 -1 -1 30404 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65052 31 32 409 331 1 257 87 17 17 289 -1 unnamed_device 24.6 MiB 0.47 1269 16023 5206 8626 2191 63.5 MiB 0.16 0.00 4.27167 -145.144 -4.27167 4.27167 0.34 0.000768802 0.000713617 0.0673126 0.0624982 -1 -1 -1 -1 38 3325 48 6.99608e+06 353176 678818. 2348.85 1.74 0.259733 0.227383 26626 170182 -1 2713 23 2420 3261 279104 64299 3.9869 3.9869 -150.259 -3.9869 0 0 902133. 3121.57 0.04 0.11 0.14 -1 -1 0.04 0.035037 0.0305796 115 90 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_001.v common 5.45 vpr 63.17 MiB -1 -1 0.37 18628 14 0.27 -1 -1 32696 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64684 32 32 277 309 1 198 86 17 17 289 -1 unnamed_device 23.9 MiB 1.02 1216 8402 2148 5464 790 63.2 MiB 0.10 0.00 8.60211 -177.555 -8.60211 8.60211 0.33 0.000906651 0.000841051 0.0440023 0.04089 -1 -1 -1 -1 36 3343 23 6.79088e+06 296384 648988. 2245.63 1.66 0.234664 0.204625 25390 158009 -1 2918 20 1215 3530 210135 48583 7.25706 7.25706 -164.252 -7.25706 0 0 828058. 2865.25 0.03 0.09 0.13 -1 -1 0.03 0.0372184 0.0326547 134 183 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_002.v common 4.27 vpr 63.08 MiB -1 -1 0.39 18612 14 0.28 -1 -1 32752 -1 -1 23 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64592 30 32 272 304 1 201 85 17 17 289 -1 unnamed_device 23.8 MiB 0.54 1069 6595 1508 3894 1193 63.1 MiB 0.08 0.00 7.62679 -156.019 -7.62679 7.62679 0.33 0.000897571 0.000832492 0.0356274 0.0329963 -1 -1 -1 -1 30 3252 22 6.79088e+06 309856 556674. 1926.21 1.19 0.153656 0.134616 24526 138013 -1 2437 15 1240 3174 155047 38736 7.03519 7.03519 -154.218 -7.03519 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65124 29 32 275 307 1 198 84 17 17 289 -1 unnamed_device 23.8 MiB 0.58 1159 7221 1730 4679 812 63.6 MiB 0.08 0.00 7.12458 -141.442 -7.12458 7.12458 0.33 0.000907899 0.000842156 0.0393057 0.0364311 -1 -1 -1 -1 36 3012 26 6.79088e+06 309856 648988. 2245.63 1.25 0.235956 0.204904 25390 158009 -1 2527 17 1156 3212 170442 40925 6.40858 6.40858 -139.574 -6.40858 0 0 828058. 2865.25 0.03 0.08 0.14 -1 -1 0.03 0.034688 0.0306631 138 190 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_005.v common 4.73 vpr 63.32 MiB -1 -1 0.37 18332 13 0.27 -1 -1 32836 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64224 31 32 235 267 1 193 83 17 17 289 -1 unnamed_device 23.5 MiB 0.49 1267 9443 2350 5394 1699 62.7 MiB 0.09 0.00 7.00394 -146.716 -7.00394 7.00394 0.33 0.00075893 0.000701998 0.0425388 0.039409 -1 -1 -1 -1 38 3104 44 6.79088e+06 269440 678818. 2348.85 1.40 0.217188 0.188472 25966 169698 -1 2511 13 1067 2786 145991 34263 6.13878 6.13878 -139.908 -6.13878 0 0 902133. 3121.57 0.03 0.06 0.13 -1 -1 0.03 0.0236132 0.0210078 109 144 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_010.v common 4.65 vpr 62.76 MiB -1 -1 0.34 18032 13 0.19 -1 -1 32656 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 32 32 250 282 1 179 81 17 17 289 -1 unnamed_device 23.8 MiB 0.50 1090 10931 3367 5780 1784 62.8 MiB 0.11 0.00 7.28577 -164.664 -7.28577 7.28577 0.34 0.000813571 0.000754847 0.0542084 0.0503226 -1 -1 -1 -1 28 3533 41 6.79088e+06 229024 531479. 1839.03 1.91 0.185087 0.16268 23950 126010 -1 2752 19 1252 3064 186322 44716 6.83133 6.83133 -163.201 -6.83133 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0192374 0.0173001 110 156 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_011.v common 3.96 vpr 63.13 MiB -1 -1 0.34 17980 12 0.18 -1 -1 32420 -1 -1 20 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 30 32 216 248 1 158 82 17 17 289 -1 unnamed_device 23.7 MiB 0.64 1013 7736 2109 4154 1473 63.1 MiB 0.07 0.00 7.00052 -148.469 -7.00052 7.00052 0.34 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65432 32 32 303 335 1 223 88 17 17 289 -1 unnamed_device 24.1 MiB 0.93 1381 7108 1510 4813 785 63.9 MiB 0.09 0.00 8.68737 -182.159 -8.68737 8.68737 0.33 0.000971373 0.000899383 0.0395476 0.0366407 -1 -1 -1 -1 32 4290 36 6.79088e+06 323328 586450. 2029.24 1.15 0.190555 0.16651 24814 144142 -1 3144 21 1610 4237 239711 58120 7.62947 7.62947 -174.383 -7.62947 0 0 744469. 2576.02 0.03 0.11 0.12 -1 -1 0.03 0.0443311 0.0389765 154 209 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_015.v common 3.50 vpr 63.13 MiB -1 -1 0.17 18192 11 0.17 -1 -1 32568 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64648 29 32 225 257 1 169 84 17 17 289 -1 unnamed_device 23.7 MiB 0.44 916 10515 3062 5421 2032 63.1 MiB 0.09 0.00 6.53813 -131.787 -6.53813 6.53813 0.34 0.000725706 0.000672408 0.0448337 0.0415415 -1 -1 -1 -1 32 2757 29 6.79088e+06 309856 586450. 2029.24 0.69 0.142599 0.125231 24814 144142 -1 2124 15 1029 2591 137318 34249 5.82544 5.82544 -128.803 -5.82544 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0251747 0.0222641 108 140 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_016.v common 5.08 vpr 63.88 MiB -1 -1 0.38 18624 12 0.27 -1 -1 32832 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65408 32 32 301 333 1 219 91 17 17 289 -1 unnamed_device 24.2 MiB 0.77 1438 8863 2011 6147 705 63.9 MiB 0.10 0.00 7.59173 -165.075 -7.59173 7.59173 0.33 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64240 30 32 175 207 1 132 76 17 17 289 -1 unnamed_device 23.3 MiB 0.29 730 7916 1923 5695 298 62.7 MiB 0.04 0.00 4.80476 -119.7 -4.80476 4.80476 0.26 0.000256369 0.000236382 0.0143765 0.0132661 -1 -1 -1 -1 30 2018 34 6.79088e+06 188608 556674. 1926.21 0.77 0.095688 0.0827056 24526 138013 -1 1498 16 687 1592 79762 20616 4.17477 4.17477 -114.477 -4.17477 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.0198998 0.0174803 65 87 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_020.v common 4.36 vpr 63.16 MiB -1 -1 0.33 17996 13 0.18 -1 -1 32604 -1 -1 20 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64852 32 32 238 270 1 178 83 17 17 289 -1 unnamed_device 23.8 MiB 0.65 1148 12143 3041 7670 1432 63.3 MiB 0.11 0.00 6.34459 -146.944 -6.34459 6.34459 0.33 0.000750706 0.000694298 0.0538223 0.0498043 -1 -1 -1 -1 38 2647 17 6.79088e+06 255968 678818. 2348.85 1.33 0.2063 0.18023 25966 169698 -1 2328 17 947 2403 123447 29193 5.48874 5.48874 -138.211 -5.48874 0 0 902133. 3121.57 0.04 0.07 0.11 -1 -1 0.04 0.0286228 0.0252657 107 144 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_030.v common 5.13 vpr 63.04 MiB -1 -1 0.31 18240 11 0.15 -1 -1 32708 -1 -1 21 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 30 32 213 245 1 165 83 17 17 289 -1 unnamed_device 23.7 MiB 0.61 974 10343 3278 5049 2016 63.0 MiB 0.09 0.00 6.09388 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/home/elgamma8/research/release/vtr-verilog-to-routing 64524 29 32 220 252 1 166 80 17 17 289 -1 unnamed_device 23.6 MiB 0.45 940 6788 1590 4069 1129 63.0 MiB 0.07 0.00 5.87088 -123.319 -5.87088 5.87088 0.33 0.000727256 0.000674214 0.0314234 0.0291543 -1 -1 -1 -1 32 2784 27 6.79088e+06 255968 586450. 2029.24 0.81 0.125126 0.109442 24814 144142 -1 2184 23 928 2818 218996 73994 5.15963 5.15963 -121.159 -5.15963 0 0 744469. 2576.02 0.03 0.10 0.12 -1 -1 0.03 0.0346152 0.0304083 103 135 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_035.v common 6.98 vpr 63.85 MiB -1 -1 0.40 19044 13 0.29 -1 -1 32872 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65384 32 32 315 347 1 230 88 17 17 289 -1 unnamed_device 24.1 MiB 0.96 1348 13153 3284 8043 1826 63.9 MiB 0.15 0.00 8.14776 -167.632 -8.14776 8.14776 0.33 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64600 31 32 307 339 1 222 88 17 17 289 -1 unnamed_device 24.1 MiB 1.21 1407 7498 1735 4811 952 63.1 MiB 0.09 0.00 7.34976 -154.275 -7.34976 7.34976 0.34 0.000981071 0.000910313 0.0420093 0.0389437 -1 -1 -1 -1 40 3418 20 6.79088e+06 336800 706193. 2443.58 1.73 0.246794 0.215022 26254 175826 -1 3093 18 1523 4851 283645 64150 6.47011 6.47011 -145.98 -6.47011 0 0 926341. 3205.33 0.04 0.10 0.14 -1 -1 0.04 0.0386713 0.0341337 147 216 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_039.v common 4.12 vpr 63.12 MiB -1 -1 0.29 18700 14 0.33 -1 -1 32668 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 31 32 293 325 1 209 86 17 17 289 -1 unnamed_device 24.1 MiB 0.66 1309 5189 1008 3816 365 63.1 MiB 0.07 0.00 8.47715 -171.11 -8.47715 8.47715 0.33 0.000951617 0.000883008 0.0299557 0.0278273 -1 -1 -1 -1 32 3922 37 6.79088e+06 309856 586450. 2029.24 1.02 0.169292 0.147146 24814 144142 -1 2985 16 1354 3764 205238 49818 7.35086 7.35086 -163.299 -7.35086 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.035856 0.0317914 145 202 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_040.v common 7.66 vpr 63.05 MiB -1 -1 0.41 18940 13 0.26 -1 -1 32728 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64560 31 32 276 308 1 213 90 17 17 289 -1 unnamed_device 23.9 MiB 0.91 1374 8733 1936 6161 636 63.0 MiB 0.10 0.00 8.23594 -169.125 -8.23594 8.23594 0.34 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65196 32 32 271 303 1 213 86 17 17 289 -1 unnamed_device 23.9 MiB 0.48 1392 6323 1417 4337 569 63.7 MiB 0.08 0.00 7.43607 -167.439 -7.43607 7.43607 0.34 0.000883475 0.000818429 0.0332858 0.0308115 -1 -1 -1 -1 32 3852 24 6.79088e+06 296384 586450. 2029.24 1.13 0.154314 0.134981 24814 144142 -1 3039 31 1428 4021 302952 101633 6.58083 6.58083 -166.434 -6.58083 0 0 744469. 2576.02 0.03 0.09 0.08 -1 -1 0.03 0.0285554 0.0252491 137 177 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_059.v common 3.59 vpr 62.98 MiB -1 -1 0.29 18232 11 0.21 -1 -1 32800 -1 -1 20 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 30 32 235 267 1 168 80 17 17 289 -1 unnamed_device 23.6 MiB 0.93 1017 9368 2381 5580 1407 63.2 MiB 0.09 0.00 7.37863 -147.299 -7.37863 7.37863 0.33 0.000762423 0.00070602 0.0447211 0.0414357 -1 -1 -1 -1 30 2602 19 6.79088e+06 242496 556674. 1926.21 0.82 0.135703 0.11964 24526 138013 -1 2239 15 965 2628 129907 31874 6.45553 6.45553 -140.988 -6.45553 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0261016 0.0231301 106 147 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_074.v common 5.26 vpr 63.01 MiB -1 -1 0.36 18368 12 0.25 -1 -1 32488 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65428 32 32 318 350 1 235 87 17 17 289 -1 unnamed_device 24.1 MiB 0.56 1568 4887 902 3684 301 63.9 MiB 0.07 0.00 9.02019 -190.009 -9.02019 9.02019 0.34 0.00104181 0.000961409 0.0318736 0.0295113 -1 -1 -1 -1 36 4105 46 6.79088e+06 309856 648988. 2245.63 2.61 0.292466 0.253271 25390 158009 -1 3306 18 1498 4099 235444 53438 7.68756 7.68756 -176.02 -7.68756 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0414283 0.0365895 161 224 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_118.v common 3.77 vpr 63.05 MiB -1 -1 0.29 17912 12 0.16 -1 -1 32496 -1 -1 20 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64564 31 32 222 254 1 182 83 17 17 289 -1 unnamed_device 23.6 MiB 0.49 1069 9983 2406 6498 1079 63.1 MiB 0.09 0.00 6.74398 -150.531 -6.74398 6.74398 0.33 0.000713695 0.000661577 0.0425082 0.0394239 -1 -1 -1 -1 38 2477 16 6.79088e+06 269440 678818. 2348.85 1.06 0.169114 0.147666 25966 169698 -1 2099 19 1023 2452 121285 30063 5.80973 5.80973 -140.663 -5.80973 0 0 902133. 3121.57 0.03 0.07 0.14 -1 -1 0.03 0.0287622 0.0252832 105 131 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_119.v common 5.67 vpr 63.24 MiB -1 -1 0.41 18960 13 0.27 -1 -1 32740 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 32 32 282 314 1 205 88 17 17 289 -1 unnamed_device 24.2 MiB 0.68 1353 7498 1790 4732 976 63.2 MiB 0.09 0.00 7.75713 -161.394 -7.75713 7.75713 0.33 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65728 32 32 350 382 1 253 93 17 17 289 -1 unnamed_device 24.4 MiB 0.80 1534 15843 4073 9876 1894 64.2 MiB 0.20 0.00 9.26624 -195.349 -9.26624 9.26624 0.33 0.00114344 0.00105332 0.0911082 0.0837944 -1 -1 -1 -1 36 4424 47 6.79088e+06 390688 648988. 2245.63 2.27 0.375645 0.327516 25390 158009 -1 3688 20 2137 6480 362108 83352 8.22795 8.22795 -186.796 -8.22795 0 0 828058. 2865.25 0.03 0.13 0.13 -1 -1 0.03 0.050897 0.0448721 188 256 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_123.v common 3.06 vpr 62.77 MiB -1 -1 0.29 17780 10 0.10 -1 -1 32524 -1 -1 13 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64272 30 32 174 206 1 132 75 17 17 289 -1 unnamed_device 23.2 MiB 0.33 648 7817 1916 5610 291 62.8 MiB 0.07 0.00 5.06221 -116.743 -5.06221 5.06221 0.33 0.000563723 0.000524027 0.0299828 0.0278843 -1 -1 -1 -1 32 2039 40 6.79088e+06 175136 586450. 2029.24 0.68 0.114078 0.0994672 24814 144142 -1 1601 16 716 1708 100263 26208 4.63261 4.63261 -119.111 -4.63261 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0195277 0.0171444 66 86 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_124.v common 3.60 vpr 62.99 MiB -1 -1 0.33 18044 13 0.25 -1 -1 32752 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64500 30 32 228 260 1 177 80 17 17 289 -1 unnamed_device 23.5 MiB 0.41 977 10744 3187 5417 2140 63.0 MiB 0.10 0.00 7.96187 -158.87 -7.96187 7.96187 0.33 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65304 32 32 300 332 1 225 89 17 17 289 -1 unnamed_device 24.1 MiB 0.37 1417 10979 2888 6604 1487 63.8 MiB 0.12 0.00 7.28043 -165.449 -7.28043 7.28043 0.33 0.000948654 0.000879079 0.0577509 0.0533375 -1 -1 -1 -1 32 4329 46 6.79088e+06 336800 586450. 2029.24 1.37 0.214521 0.187812 24814 144142 -1 3568 20 1714 4669 291667 67052 6.45537 6.45537 -165.272 -6.45537 0 0 744469. 2576.02 0.03 0.11 0.12 -1 -1 0.03 0.0397058 0.0352465 149 206 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_128.v common 4.87 vpr 63.24 MiB -1 -1 0.42 18912 13 0.31 -1 -1 32660 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64756 31 32 290 322 1 212 86 17 17 289 -1 unnamed_device 24.2 MiB 0.69 1276 4622 899 3442 281 63.2 MiB 0.06 0.00 8.4013 -172.333 -8.4013 8.4013 0.34 0.000957164 0.000887561 0.0274008 0.0254206 -1 -1 -1 -1 34 3859 32 6.79088e+06 309856 618332. 2139.56 1.54 0.247346 0.214205 25102 150614 -1 3160 20 1508 4342 240659 56587 7.44571 7.44571 -165.463 -7.44571 0 0 787024. 2723.27 0.03 0.10 0.12 -1 -1 0.03 0.0400711 0.0351655 150 199 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_001.v common 4.66 vpr 63.26 MiB -1 -1 0.25 18400 1 0.03 -1 -1 30288 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64776 32 32 354 285 1 207 95 17 17 289 -1 unnamed_device 24.3 MiB 2.00 1147 13487 3979 8243 1265 63.3 MiB 0.14 0.00 5.50182 -164.026 -5.50182 5.50182 0.34 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65260 29 32 308 248 1 172 90 17 17 289 -1 unnamed_device 24.1 MiB 0.86 892 10140 2486 6760 894 63.7 MiB 0.11 0.00 4.60038 -123.753 -4.60038 4.60038 0.33 0.000633932 0.000589803 0.0345913 0.0320554 -1 -1 -1 -1 32 2149 25 6.87369e+06 405241 586450. 2029.24 0.58 0.111836 0.0978729 25474 144626 -1 1602 29 1438 2570 137658 37022 3.4118 3.4118 -110.106 -3.4118 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0330296 0.0285014 124 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_005.v common 4.32 vpr 63.72 MiB -1 -1 0.24 18380 1 0.04 -1 -1 30476 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65248 32 32 336 268 1 181 91 17 17 289 -1 unnamed_device 24.0 MiB 1.54 976 16411 4511 9390 2510 63.7 MiB 0.15 0.00 4.59502 -132.541 -4.59502 4.59502 0.32 0.000701689 0.000651586 0.0483871 0.0448305 -1 -1 -1 -1 32 2485 25 6.87369e+06 377294 586450. 2029.24 0.64 0.133884 0.117944 25474 144626 -1 1977 21 1412 2809 153940 39270 3.7944 3.7944 -130.207 -3.7944 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0280558 0.024416 132 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_006.v common 3.84 vpr 63.56 MiB -1 -1 0.26 18328 1 0.03 -1 -1 30288 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65088 32 32 366 295 1 189 96 17 17 289 -1 unnamed_device 24.6 MiB 1.24 1097 10170 2509 6996 665 63.6 MiB 0.11 0.00 3.40153 -118.348 -3.40153 3.40153 0.34 0.000718937 0.00066798 0.0357972 0.0332493 -1 -1 -1 -1 28 2662 22 6.87369e+06 447163 531479. 1839.03 0.56 0.122325 0.107375 24610 126494 -1 2380 23 1512 2419 162698 39915 3.07761 3.07761 -124.592 -3.07761 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0315109 0.0273292 138 58 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_007.v common 4.43 vpr 63.20 MiB -1 -1 0.23 18008 1 0.03 -1 -1 30656 -1 -1 20 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64716 27 32 259 221 1 141 79 17 17 289 -1 unnamed_device 23.6 MiB 1.99 786 12585 3639 7320 1626 63.2 MiB 0.11 0.00 3.84098 -106.539 -3.84098 3.84098 0.33 0.000553599 0.000515588 0.0428643 0.0399218 -1 -1 -1 -1 30 1555 20 6.87369e+06 279477 556674. 1926.21 0.52 0.107252 0.0947091 25186 138497 -1 1281 20 867 1509 82468 20053 2.68236 2.68236 -96.0091 -2.68236 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 31 32 317 271 1 175 83 17 17 289 -1 unnamed_device 24.0 MiB 1.95 910 8723 2060 6322 341 63.1 MiB 0.09 0.00 3.31917 -111.486 -3.31917 3.31917 0.34 0.00063441 0.000590038 0.0329474 0.0306471 -1 -1 -1 -1 32 2150 19 6.87369e+06 279477 586450. 2029.24 0.58 0.106092 0.093061 25474 144626 -1 1748 20 1043 1565 98545 24803 2.91151 2.91151 -112.578 -2.91151 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0244429 0.0212104 110 64 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_010.v common 6.12 vpr 63.35 MiB -1 -1 0.22 18120 1 0.03 -1 -1 30076 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64872 32 32 298 248 1 162 81 17 17 289 -1 unnamed_device 23.6 MiB 3.62 974 4631 910 3488 233 63.4 MiB 0.06 0.00 3.98344 -131.884 -3.98344 3.98344 0.33 0.000626678 0.000583326 0.0185195 0.0172494 -1 -1 -1 -1 30 2081 18 6.87369e+06 237555 556674. 1926.21 0.54 0.0883308 0.0768845 25186 138497 -1 1827 21 1179 2019 124096 30001 2.82686 2.82686 -118.966 -2.82686 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0253455 0.0219646 107 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_011.v common 5.19 vpr 63.25 MiB -1 -1 0.25 18396 1 0.03 -1 -1 30308 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 30 32 303 262 1 148 80 17 17 289 -1 unnamed_device 23.6 MiB 2.64 812 9368 2251 6434 683 63.2 MiB 0.10 0.00 3.87398 -114.403 -3.87398 3.87398 0.33 0.000612514 0.000569112 0.0353925 0.0329109 -1 -1 -1 -1 26 1876 20 6.87369e+06 251529 503264. 1741.40 0.61 0.106442 0.0934101 24322 120374 -1 1676 21 1167 1874 125726 31327 3.02256 3.02256 -110.18 -3.02256 0 0 618332. 2139.56 0.03 0.04 0.11 -1 -1 0.03 0.0147437 0.0129497 99 63 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_012.v common 5.15 vpr 63.40 MiB -1 -1 0.24 18128 1 0.03 -1 -1 30064 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64920 32 32 276 237 1 171 82 17 17 289 -1 unnamed_device 23.8 MiB 2.09 828 9338 2215 6345 778 63.4 MiB 0.09 0.00 3.67066 -113.699 -3.67066 3.67066 0.34 0.000590743 0.000549309 0.0329731 0.0306745 -1 -1 -1 -1 28 2764 43 6.87369e+06 251529 531479. 1839.03 1.09 0.127315 0.111059 24610 126494 -1 1961 20 1277 1700 137309 35657 3.08581 3.08581 -116.238 -3.08581 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 32 32 363 295 1 181 95 17 17 289 -1 unnamed_device 23.9 MiB 2.12 926 9599 2091 6833 675 63.1 MiB 0.11 0.00 4.83358 -141.45 -4.83358 4.83358 0.33 0.000713803 0.000663884 0.0340711 0.0316564 -1 -1 -1 -1 30 2718 27 6.87369e+06 433189 556674. 1926.21 0.65 0.123589 0.10815 25186 138497 -1 1936 20 1247 1954 117467 30151 4.17226 4.17226 -144.094 -4.17226 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.014747 0.0130134 133 61 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_015.v common 4.22 vpr 63.17 MiB -1 -1 0.23 18132 1 0.03 -1 -1 30400 -1 -1 21 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64684 29 32 248 215 1 142 82 17 17 289 -1 unnamed_device 23.9 MiB 1.70 711 8982 2096 6475 411 63.2 MiB 0.08 0.00 3.07868 -92.9683 -3.07868 3.07868 0.33 0.000544701 0.000507131 0.0291861 0.0271418 -1 -1 -1 -1 30 1671 24 6.87369e+06 293451 556674. 1926.21 0.54 0.09513 0.0832085 25186 138497 -1 1338 20 791 1267 69154 17413 2.61566 2.61566 -91.2171 -2.61566 0 0 706193. 2443.58 0.04 0.06 0.11 -1 -1 0.04 0.0269583 0.0234237 94 27 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_016.v common 5.24 vpr 63.32 MiB -1 -1 0.24 18324 1 0.03 -1 -1 30280 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 32 32 370 297 1 191 88 17 17 289 -1 unnamed_device 24.0 MiB 1.91 1084 8668 1982 6147 539 63.3 MiB 0.10 0.00 3.90567 -127.707 -3.90567 3.90567 0.34 0.000723408 0.000672104 0.0345784 0.0321445 -1 -1 -1 -1 26 3264 40 6.87369e+06 335372 503264. 1741.40 1.11 0.146809 0.128202 24322 120374 -1 2399 26 1846 3235 222891 55287 3.67301 3.67301 -130.22 -3.67301 0 0 618332. 2139.56 0.03 0.10 0.10 -1 -1 0.03 0.0345238 0.0298759 135 58 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_017.v common 5.98 vpr 63.31 MiB -1 -1 0.14 18332 1 0.03 -1 -1 30080 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 32 32 338 269 1 204 87 17 17 289 -1 unnamed_device 24.0 MiB 3.16 1041 6615 1468 4357 790 63.3 MiB 0.09 0.00 4.18227 -133.396 -4.18227 4.18227 0.34 0.000705916 0.000657167 0.0262471 0.0244203 -1 -1 -1 -1 30 2762 25 6.87369e+06 321398 556674. 1926.21 0.64 0.11193 0.0976763 25186 138497 -1 1904 18 1127 1583 94947 23325 3.4571 3.4571 -119.55 -3.4571 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0250568 0.0218957 136 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_018.v common 4.85 vpr 63.07 MiB -1 -1 0.17 18456 1 0.03 -1 -1 30260 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 32 32 323 276 1 156 93 17 17 289 -1 unnamed_device 23.9 MiB 2.21 961 14583 4168 8594 1821 63.1 MiB 0.13 0.00 2.88754 -107.489 -2.88754 2.88754 0.34 0.000653129 0.000606854 0.0473539 0.0439444 -1 -1 -1 -1 26 2202 23 6.87369e+06 405241 503264. 1741.40 0.71 0.126735 0.111657 24322 120374 -1 1966 21 1193 2019 142695 34226 2.22712 2.22712 -101.935 -2.22712 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0260927 0.0225956 110 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_019.v common 3.10 vpr 63.05 MiB -1 -1 0.16 18180 1 0.03 -1 -1 30184 -1 -1 15 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64560 30 32 222 206 1 117 77 17 17 289 -1 unnamed_device 23.7 MiB 0.66 689 12139 3691 7050 1398 63.0 MiB 0.09 0.00 2.38778 -83.5564 -2.38778 2.38778 0.34 0.000495747 0.000461876 0.038516 0.0358607 -1 -1 -1 -1 32 1442 23 6.87369e+06 209608 586450. 2029.24 0.50 0.0985935 0.0870204 25474 144626 -1 1219 18 585 811 57943 14080 2.01382 2.01382 -84.6315 -2.01382 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0179977 0.0155952 71 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_020.v common 5.39 vpr 63.12 MiB -1 -1 0.24 18340 1 0.03 -1 -1 30384 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 31 32 291 243 1 178 84 17 17 289 -1 unnamed_device 24.1 MiB 2.65 926 13626 5074 6419 2133 63.1 MiB 0.14 0.00 4.99433 -147.969 -4.99433 4.99433 0.33 0.00061624 0.000572644 0.0477352 0.04437 -1 -1 -1 -1 32 2269 22 6.87369e+06 293451 586450. 2029.24 0.61 0.120075 0.105959 25474 144626 -1 1823 19 1094 1607 107959 26850 3.64821 3.64821 -133.065 -3.64821 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0229829 0.0199895 114 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_021.v common 3.77 vpr 63.66 MiB -1 -1 0.24 18488 1 0.03 -1 -1 30524 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65192 32 32 342 271 1 181 99 17 17 289 -1 unnamed_device 23.9 MiB 0.98 1087 13779 3849 8710 1220 63.7 MiB 0.14 0.00 4.23509 -137.221 -4.23509 4.23509 0.41 0.000700481 0.000649025 0.0450399 0.041707 -1 -1 -1 -1 32 2379 21 6.87369e+06 489084 586450. 2029.24 0.59 0.126272 0.11115 25474 144626 -1 1994 21 1330 2152 132705 31355 3.6621 3.6621 -128.504 -3.6621 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0278376 0.0241709 137 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_022.v common 4.99 vpr 63.32 MiB -1 -1 0.24 18356 1 0.03 -1 -1 30268 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64836 32 32 372 300 1 206 87 17 17 289 -1 unnamed_device 24.2 MiB 2.22 1217 10647 2492 7086 1069 63.3 MiB 0.12 0.00 4.31025 -134.205 -4.31025 4.31025 0.33 0.000725524 0.000675176 0.0426199 0.0396102 -1 -1 -1 -1 32 2810 25 6.87369e+06 321398 586450. 2029.24 0.63 0.131393 0.11554 25474 144626 -1 2136 16 1278 2034 131099 31365 3.74246 3.74246 -129.143 -3.74246 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0238439 0.020874 138 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_023.v common 4.12 vpr 62.94 MiB -1 -1 0.22 18228 1 0.02 -1 -1 30548 -1 -1 17 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64448 26 32 190 182 1 108 75 17 17 289 -1 unnamed_device 23.6 MiB 1.58 480 8133 3281 4323 529 62.9 MiB 0.06 0.00 2.38158 -69.4238 -2.38158 2.38158 0.34 0.00047137 0.000434655 0.0191877 0.0175956 -1 -1 -1 -1 28 1220 24 6.87369e+06 237555 531479. 1839.03 0.52 0.0720773 0.0625468 24610 126494 -1 1036 17 707 988 65067 17945 2.18312 2.18312 -75.9258 -2.18312 0 0 648988. 2245.63 0.03 0.04 0.10 -1 -1 0.03 0.014802 0.0128753 67 30 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_024.v common 3.76 vpr 63.39 MiB -1 -1 0.22 17868 1 0.03 -1 -1 30344 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 32 32 285 227 1 169 87 17 17 289 -1 unnamed_device 23.8 MiB 1.15 1002 13719 4614 6837 2268 63.4 MiB 0.14 0.00 4.57022 -130.066 -4.57022 4.57022 0.33 0.00061934 0.000575759 0.0461905 0.0429273 -1 -1 -1 -1 30 2201 25 6.87369e+06 321398 556674. 1926.21 0.60 0.122115 0.10779 25186 138497 -1 1821 21 1157 2162 119285 29514 3.7041 3.7041 -123.476 -3.7041 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0254677 0.0220817 119 3 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_025.v common 2.97 vpr 63.02 MiB -1 -1 0.12 17552 1 0.02 -1 -1 30008 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64536 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 23.8 MiB 0.62 529 9036 3698 5030 308 63.0 MiB 0.07 0.00 2.64533 -79.7813 -2.64533 2.64533 0.34 0.000423617 0.000392859 0.0254041 0.0235785 -1 -1 -1 -1 28 1296 30 6.87369e+06 167686 531479. 1839.03 0.56 0.0819974 0.0717561 24610 126494 -1 1030 14 522 612 45566 12360 2.19737 2.19737 -79.5748 -2.19737 0 0 648988. 2245.63 0.03 0.05 0.10 -1 -1 0.03 0.0206278 0.0179992 65 3 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_026.v common 3.58 vpr 63.64 MiB -1 -1 0.23 18288 1 0.03 -1 -1 30140 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65172 32 32 300 245 1 169 94 17 17 289 -1 unnamed_device 24.0 MiB 0.98 1049 16069 4575 9607 1887 63.6 MiB 0.15 0.00 4.58208 -129.699 -4.58208 4.58208 0.33 0.000638368 0.000594438 0.0502991 0.046754 -1 -1 -1 -1 26 2413 24 6.87369e+06 419215 503264. 1741.40 0.61 0.127158 0.112378 24322 120374 -1 2176 20 1211 1947 151498 35401 3.8557 3.8557 -129.062 -3.8557 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0251252 0.0218207 120 24 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_027.v common 3.62 vpr 63.05 MiB -1 -1 0.23 17932 1 0.03 -1 -1 30524 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64560 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 24.0 MiB 0.87 1082 17591 5231 9950 2410 63.0 MiB 0.16 0.00 3.50229 -113.775 -3.50229 3.50229 0.33 0.000639768 0.000594765 0.0541889 0.0503085 -1 -1 -1 -1 26 2515 20 6.87369e+06 433189 503264. 1741.40 0.72 0.128188 0.113567 24322 120374 -1 2222 18 1165 2078 132215 32194 3.07956 3.07956 -114.993 -3.07956 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 32 32 284 241 1 148 82 17 17 289 -1 unnamed_device 23.7 MiB 0.94 856 12720 4032 6930 1758 63.3 MiB 0.12 0.00 3.07458 -105.313 -3.07458 3.07458 0.33 0.000608 0.000559447 0.0450373 0.0417759 -1 -1 -1 -1 32 1770 20 6.87369e+06 251529 586450. 2029.24 0.53 0.114315 0.100881 25474 144626 -1 1498 21 757 1288 84508 20239 2.64866 2.64866 -104.259 -2.64866 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0130009 0.0114168 101 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_030.v common 3.53 vpr 63.14 MiB -1 -1 0.14 18236 1 0.03 -1 -1 30272 -1 -1 25 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 30 32 262 227 1 138 87 17 17 289 -1 unnamed_device 23.6 MiB 1.11 850 14103 4319 8139 1645 63.1 MiB 0.12 0.00 3.14772 -102.363 -3.14772 3.14772 0.33 0.00056828 0.000529209 0.0435607 0.0405281 -1 -1 -1 -1 32 1755 31 6.87369e+06 349346 586450. 2029.24 0.57 0.118019 0.103831 25474 144626 -1 1498 19 881 1432 93880 22924 2.79396 2.79396 -97.0612 -2.79396 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0210251 0.018223 97 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_031.v common 3.40 vpr 63.08 MiB -1 -1 0.16 18000 1 0.02 -1 -1 30160 -1 -1 24 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64596 28 32 260 223 1 140 84 17 17 289 -1 unnamed_device 23.5 MiB 0.98 762 14175 5132 6824 2219 63.1 MiB 0.12 0.00 3.46791 -98.5079 -3.46791 3.46791 0.34 0.000563734 0.000522844 0.045193 0.0418736 -1 -1 -1 -1 32 1793 20 6.87369e+06 335372 586450. 2029.24 0.55 0.110531 0.0973165 25474 144626 -1 1515 22 1016 1832 127699 30852 2.85696 2.85696 -98.0028 -2.85696 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.023617 0.0204119 98 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_032.v common 3.74 vpr 63.33 MiB -1 -1 0.16 17904 1 0.03 -1 -1 30268 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64848 32 32 253 210 1 156 82 17 17 289 -1 unnamed_device 23.7 MiB 1.29 755 8448 1958 6116 374 63.3 MiB 0.09 0.00 3.92118 -117.55 -3.92118 3.92118 0.33 0.000566959 0.000528139 0.0291684 0.0271468 -1 -1 -1 -1 28 2136 22 6.87369e+06 251529 531479. 1839.03 0.64 0.0969963 0.0849626 24610 126494 -1 1789 21 1303 2060 129617 33406 3.24686 3.24686 -120.536 -3.24686 0 0 648988. 2245.63 0.03 0.07 0.11 -1 -1 0.03 0.0233859 0.0202504 101 3 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_033.v common 3.22 vpr 63.34 MiB -1 -1 0.21 18088 1 0.03 -1 -1 30404 -1 -1 26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 31 32 271 231 1 149 89 17 17 289 -1 unnamed_device 23.7 MiB 0.85 947 11771 3021 7217 1533 63.3 MiB 0.11 0.00 3.40475 -107.115 -3.40475 3.40475 0.34 0.000611176 0.000561225 0.0377071 0.0349827 -1 -1 -1 -1 32 2054 22 6.87369e+06 363320 586450. 2029.24 0.56 0.10753 0.0944819 25474 144626 -1 1803 18 928 1643 117337 27902 2.95826 2.95826 -108.892 -2.95826 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0114211 0.0100919 102 30 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_034.v common 4.89 vpr 63.20 MiB -1 -1 0.17 18508 1 0.03 -1 -1 30520 -1 -1 25 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64712 29 32 291 250 1 154 86 17 17 289 -1 unnamed_device 23.6 MiB 2.42 855 9536 2217 6358 961 63.2 MiB 0.09 0.00 3.08002 -99.9202 -3.08002 3.08002 0.34 0.000605347 0.000562439 0.0322847 0.0300207 -1 -1 -1 -1 32 1836 20 6.87369e+06 349346 586450. 2029.24 0.54 0.101683 0.0890847 25474 144626 -1 1618 17 896 1401 87699 22004 2.36147 2.36147 -96.2223 -2.36147 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0208019 0.0180997 105 54 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_035.v common 5.60 vpr 63.82 MiB -1 -1 0.22 18412 1 0.04 -1 -1 30340 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65356 32 32 367 282 1 201 104 17 17 289 -1 unnamed_device 24.2 MiB 2.99 1201 11572 2628 7875 1069 63.8 MiB 0.12 0.00 4.28409 -125.895 -4.28409 4.28409 0.33 0.000745621 0.000691639 0.0376247 0.0349383 -1 -1 -1 -1 32 2850 21 6.87369e+06 558954 586450. 2029.24 0.60 0.123608 0.108597 25474 144626 -1 2283 22 1202 2387 140467 34356 3.5931 3.5931 -122.354 -3.5931 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0309075 0.0268465 156 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_036.v common 5.65 vpr 63.77 MiB -1 -1 0.25 18384 1 0.03 -1 -1 30256 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65304 32 32 391 311 1 194 104 17 17 289 -1 unnamed_device 24.1 MiB 2.85 1115 17428 4398 11199 1831 63.8 MiB 0.18 0.00 4.01296 -135.521 -4.01296 4.01296 0.33 0.000766942 0.000704452 0.0562864 0.0519881 -1 -1 -1 -1 32 2421 26 6.87369e+06 558954 586450. 2029.24 0.61 0.150049 0.132322 25474 144626 -1 2065 20 1509 2448 142727 34833 3.01616 3.01616 -125.596 -3.01616 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.029391 0.0255786 149 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_037.v common 4.36 vpr 63.29 MiB -1 -1 0.22 18292 1 0.13 -1 -1 30024 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 31 32 279 237 1 166 81 17 17 289 -1 unnamed_device 23.6 MiB 1.83 846 9881 2610 5928 1343 63.3 MiB 0.10 0.00 4.09163 -121.619 -4.09163 4.09163 0.33 0.000593945 0.000552927 0.0353443 0.0329006 -1 -1 -1 -1 32 1941 25 6.87369e+06 251529 586450. 2029.24 0.56 0.108321 0.0951512 25474 144626 -1 1646 21 1100 1628 113634 27943 2.96331 2.96331 -109.173 -2.96331 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0136148 0.011982 105 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_038.v common 5.10 vpr 63.34 MiB -1 -1 0.20 18388 1 0.03 -1 -1 30396 -1 -1 26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 31 32 370 297 1 187 89 17 17 289 -1 unnamed_device 24.3 MiB 2.43 1023 15533 5566 7049 2918 63.3 MiB 0.16 0.00 3.72294 -120.106 -3.72294 3.72294 0.33 0.000718031 0.000666124 0.0592263 0.0550182 -1 -1 -1 -1 30 2608 22 6.87369e+06 363320 556674. 1926.21 0.67 0.14449 0.127836 25186 138497 -1 2002 16 1255 2178 123141 30081 3.01531 3.01531 -116.913 -3.01531 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0236042 0.0206111 136 61 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_039.v common 6.30 vpr 63.29 MiB -1 -1 0.23 18360 1 0.03 -1 -1 30336 -1 -1 29 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 31 32 377 302 1 237 92 17 17 289 -1 unnamed_device 24.3 MiB 3.21 1226 11477 3074 7440 963 63.3 MiB 0.14 0.00 5.94301 -174.677 -5.94301 5.94301 0.33 0.000740882 0.00068947 0.0435873 0.0404978 -1 -1 -1 -1 32 3381 27 6.87369e+06 405241 586450. 2029.24 0.86 0.135821 0.119293 25474 144626 -1 2594 21 2065 3065 259228 59072 4.91379 4.91379 -168.168 -4.91379 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.030074 0.0261518 156 64 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_040.v common 10.36 vpr 63.25 MiB -1 -1 0.13 18256 1 0.03 -1 -1 30432 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64772 31 32 383 305 1 212 91 17 17 289 -1 unnamed_device 24.2 MiB 3.73 1111 18247 5857 8950 3440 63.3 MiB 0.17 0.00 5.17369 -157.317 -5.17369 5.17369 0.34 0.000735997 0.000683017 0.0685617 0.0636389 -1 -1 -1 -1 32 3441 45 6.87369e+06 391268 586450. 2029.24 4.57 0.366723 0.317795 25474 144626 -1 2256 24 1622 2535 185379 47271 4.9157 4.9157 -166.109 -4.9157 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0333739 0.0289693 151 64 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_041.v common 5.01 vpr 63.19 MiB -1 -1 0.19 18320 1 0.03 -1 -1 30352 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 31 32 352 285 1 186 91 17 17 289 -1 unnamed_device 24.0 MiB 2.47 1131 11311 2943 7349 1019 63.2 MiB 0.13 0.00 4.13563 -130.877 -4.13563 4.13563 0.33 0.000699135 0.000649874 0.0415874 0.0386624 -1 -1 -1 -1 32 2600 24 6.87369e+06 391268 586450. 2029.24 0.59 0.128261 0.113076 25474 144626 -1 2128 18 1230 2196 131110 32142 3.01051 3.01051 -116.588 -3.01051 0 0 744469. 2576.02 0.04 0.07 0.13 -1 -1 0.04 0.0280873 0.0248281 132 55 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_042.v common 4.67 vpr 63.59 MiB -1 -1 0.14 18176 1 0.04 -1 -1 30420 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65116 32 32 291 242 1 183 86 17 17 289 -1 unnamed_device 24.0 MiB 2.08 1141 9158 2504 6028 626 63.6 MiB 0.10 0.00 4.45965 -121.916 -4.45965 4.45965 0.33 0.00062293 0.000575167 0.0320274 0.0298167 -1 -1 -1 -1 26 2762 22 6.87369e+06 307425 503264. 1741.40 0.76 0.106328 0.0931794 24322 120374 -1 2331 25 1513 2202 176135 41792 4.13656 4.13656 -128.468 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-1 20 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64740 31 32 261 225 1 148 83 17 17 289 -1 unnamed_device 23.7 MiB 1.65 712 6743 1427 4646 670 63.2 MiB 0.07 0.00 3.53695 -102.057 -3.53695 3.53695 0.33 0.000580111 0.000533635 0.0235301 0.0218269 -1 -1 -1 -1 30 1801 19 6.87369e+06 279477 556674. 1926.21 1.25 0.14987 0.128847 25186 138497 -1 1472 24 1139 2012 112446 28814 2.71766 2.71766 -99.2166 -2.71766 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.025589 0.0220302 95 28 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_045.v common 5.49 vpr 63.11 MiB -1 -1 0.21 18396 1 0.03 -1 -1 30176 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64620 31 32 337 267 1 207 88 17 17 289 -1 unnamed_device 23.9 MiB 2.51 1167 9448 2299 6357 792 63.1 MiB 0.12 0.00 4.84783 -145.415 -4.84783 4.84783 0.33 0.000681899 0.000634009 0.0364431 0.0338906 -1 -1 -1 -1 26 3222 39 6.87369e+06 349346 503264. 1741.40 0.88 0.136534 0.11933 24322 120374 -1 2636 21 1907 2825 215476 51329 4.38896 4.38896 -148.594 -4.38896 0 0 618332. 2139.56 0.03 0.08 0.08 -1 -1 0.03 0.0276589 0.0240477 139 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_046.v common 4.53 vpr 63.29 MiB -1 -1 0.23 18428 1 0.02 -1 -1 30416 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 32 32 349 284 1 183 96 17 17 289 -1 unnamed_device 24.0 MiB 1.74 1161 10170 2713 6697 760 63.3 MiB 0.12 0.00 3.7235 -118.305 -3.7235 3.7235 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 32 32 361 291 1 189 97 17 17 289 -1 unnamed_device 24.1 MiB 2.80 942 18079 4845 10579 2655 63.1 MiB 0.17 0.00 3.80724 -119.205 -3.80724 3.80724 0.33 0.000719091 0.000668366 0.0611155 0.0567946 -1 -1 -1 -1 32 2842 49 6.87369e+06 461137 586450. 2029.24 0.76 0.175295 0.154435 25474 144626 -1 2003 21 1296 2243 161130 40238 3.17181 3.17181 -117.395 -3.17181 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0299406 0.0260509 137 55 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_050.v common 5.43 vpr 63.39 MiB -1 -1 0.26 18356 1 0.03 -1 -1 30236 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64916 32 32 382 305 1 193 99 17 17 289 -1 unnamed_device 24.3 MiB 2.75 1194 15147 4115 8922 2110 63.4 MiB 0.17 0.00 4.12873 -137.061 -4.12873 4.12873 0.33 0.000747128 0.000694047 0.0516993 0.0480117 -1 -1 -1 -1 30 2637 23 6.87369e+06 489084 556674. 1926.21 0.62 0.140245 0.123846 25186 138497 -1 2186 20 1312 2080 127606 30703 3.18081 3.18081 -123.292 -3.18081 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0284563 0.0247655 145 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_051.v common 3.96 vpr 63.45 MiB -1 -1 0.26 18084 1 0.03 -1 -1 30416 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 32 32 306 248 1 170 97 17 17 289 -1 unnamed_device 24.3 MiB 0.96 1051 16969 4458 10747 1764 63.4 MiB 0.16 0.00 4.25889 -127.121 -4.25889 4.25889 0.33 0.000643879 0.000599022 0.0513577 0.0476883 -1 -1 -1 -1 28 2418 26 6.87369e+06 461137 531479. 1839.03 0.59 0.132297 0.11702 24610 126494 -1 2119 22 1403 2481 165711 40053 4.2163 4.2163 -131.586 -4.2163 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0267192 0.0231603 124 24 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_052.v common 4.58 vpr 63.15 MiB -1 -1 0.18 18544 1 0.03 -1 -1 30256 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 32 32 319 257 1 203 87 17 17 289 -1 unnamed_device 24.0 MiB 1.82 1159 5847 1196 4159 492 63.1 MiB 0.07 0.00 4.90813 -141.116 -4.90813 4.90813 0.33 0.000655955 0.000610109 0.0221425 0.0206032 -1 -1 -1 -1 30 2614 20 6.87369e+06 321398 556674. 1926.21 0.61 0.0978835 0.0853734 25186 138497 -1 2189 21 1298 1910 108067 26664 3.78346 3.78346 -130.411 -3.78346 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.026572 0.023122 131 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_053.v common 4.84 vpr 63.18 MiB -1 -1 0.15 18304 1 0.03 -1 -1 30300 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 31 32 373 299 1 204 87 17 17 289 -1 unnamed_device 23.9 MiB 2.11 1104 15639 5017 7583 3039 63.2 MiB 0.17 0.00 4.75448 -143.415 -4.75448 4.75448 0.34 0.000721909 0.000671142 0.0613266 0.0569853 -1 -1 -1 -1 32 2855 22 6.87369e+06 335372 586450. 2029.24 0.69 0.149738 0.132769 25474 144626 -1 2208 19 1430 2340 173817 40610 3.83796 3.83796 -133.557 -3.83796 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.030116 0.0262036 140 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_054.v common 5.03 vpr 63.30 MiB -1 -1 0.14 18384 1 0.03 -1 -1 30284 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 32 32 387 315 1 194 86 17 17 289 -1 unnamed_device 24.2 MiB 2.41 1107 13883 4421 7374 2088 63.3 MiB 0.15 0.00 4.4264 -134.375 -4.4264 4.4264 0.34 0.00074745 0.000694485 0.0572042 0.0531062 -1 -1 -1 -1 32 2766 23 6.87369e+06 307425 586450. 2029.24 0.63 0.14684 0.129797 25474 144626 -1 2283 20 1421 2543 162506 40189 3.63536 3.63536 -132.707 -3.63536 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0293206 0.0255442 134 77 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_055.v common 3.49 vpr 63.16 MiB -1 -1 0.22 18112 1 0.03 -1 -1 30340 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 32 32 251 219 1 141 87 17 17 289 -1 unnamed_device 23.7 MiB 0.88 781 8151 1829 5687 635 63.2 MiB 0.08 0.00 3.42581 -102.974 -3.42581 3.42581 0.41 0.000559902 0.000521562 0.0254085 0.0236473 -1 -1 -1 -1 28 1904 23 6.87369e+06 321398 531479. 1839.03 0.53 0.0929223 0.0810831 24610 126494 -1 1688 22 1081 1762 117647 29623 2.79596 2.79596 -101.105 -2.79596 0 0 648988. 2245.63 0.03 0.06 0.10 -1 -1 0.03 0.0233409 0.0201884 93 23 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_056.v common 4.41 vpr 63.22 MiB -1 -1 0.25 18552 1 0.03 -1 -1 30108 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64736 32 32 341 285 1 188 84 17 17 289 -1 unnamed_device 24.0 MiB 1.74 910 13260 3607 7806 1847 63.2 MiB 0.14 0.00 3.77904 -129.086 -3.77904 3.77904 0.33 0.000677957 0.000630665 0.0508368 0.047249 -1 -1 -1 -1 32 2421 25 6.87369e+06 279477 586450. 2029.24 0.62 0.133094 0.117462 25474 144626 -1 1923 21 1469 2059 133480 33321 3.30611 3.30611 -126.077 -3.30611 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0269363 0.0233703 120 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_057.v common 5.27 vpr 63.93 MiB -1 -1 0.25 18328 1 0.03 -1 -1 30320 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65460 32 32 387 293 1 235 91 17 17 289 -1 unnamed_device 24.2 MiB 2.26 1446 16003 4513 9679 1811 63.9 MiB 0.20 0.00 5.45062 -164.1 -5.45062 5.45062 0.33 0.000765113 0.000710511 0.0625287 0.0580806 -1 -1 -1 -1 28 3827 27 6.87369e+06 377294 531479. 1839.03 0.95 0.162884 0.144247 24610 126494 -1 3174 24 2379 3636 266572 63430 5.026 5.026 -170.437 -5.026 0 0 648988. 2245.63 0.03 0.11 0.11 -1 -1 0.03 0.0356458 0.0310264 163 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_058.v common 5.19 vpr 63.83 MiB -1 -1 0.22 18408 1 0.03 -1 -1 30368 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65364 32 32 340 270 1 185 98 17 17 289 -1 unnamed_device 24.0 MiB 2.64 1118 12923 3108 8715 1100 63.8 MiB 0.14 0.00 4.49891 -142.201 -4.49891 4.49891 0.33 0.000673492 0.000619904 0.0430244 0.0399706 -1 -1 -1 -1 32 2521 22 6.87369e+06 475111 586450. 2029.24 0.58 0.126419 0.1116 25474 144626 -1 2072 19 1267 2113 137525 33579 3.11326 3.11326 -127.341 -3.11326 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0256752 0.0223967 137 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_059.v common 3.23 vpr 63.53 MiB -1 -1 0.24 18052 1 0.03 -1 -1 30460 -1 -1 25 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65052 30 32 278 235 1 150 87 17 17 289 -1 unnamed_device 23.8 MiB 0.67 780 11991 2894 8475 622 63.5 MiB 0.11 0.00 3.57685 -110.542 -3.57685 3.57685 0.30 0.00059148 0.000550047 0.0366114 0.0339228 -1 -1 -1 -1 26 2085 23 6.87369e+06 349346 503264. 1741.40 0.76 0.10767 0.0943904 24322 120374 -1 1811 21 1236 2012 147312 38902 3.10156 3.10156 -113.453 -3.10156 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.023601 0.0204161 104 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_060.v common 6.87 vpr 63.43 MiB -1 -1 0.27 18568 1 0.03 -1 -1 30284 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64956 32 32 431 332 1 239 91 17 17 289 -1 unnamed_device 24.5 MiB 4.02 1420 13147 3569 8315 1263 63.4 MiB 0.16 0.00 5.92629 -174.407 -5.92629 5.92629 0.34 0.000833342 0.00077516 0.0564343 0.0524045 -1 -1 -1 -1 32 3147 27 6.87369e+06 377294 586450. 2029.24 0.69 0.163689 0.144051 25474 144626 -1 2602 19 1701 2677 174677 41715 4.7336 4.7336 -161.132 -4.7336 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0308763 0.0269051 166 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_061.v common 5.42 vpr 63.79 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30364 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65316 32 32 336 268 1 182 99 17 17 289 -1 unnamed_device 24.0 MiB 2.76 1022 11043 2817 7461 765 63.8 MiB 0.11 0.00 4.68232 -141.336 -4.68232 4.68232 0.33 0.000696088 0.000647253 0.0357086 0.0331238 -1 -1 -1 -1 32 2244 25 6.87369e+06 489084 586450. 2029.24 0.59 0.120339 0.105641 25474 144626 -1 1837 21 1382 2159 118015 30016 3.5788 3.5788 -126.007 -3.5788 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0276469 0.0240155 135 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_062.v common 4.03 vpr 63.44 MiB -1 -1 0.22 17936 1 0.03 -1 -1 30292 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64960 32 32 231 199 1 142 92 17 17 289 -1 unnamed_device 23.9 MiB 0.76 952 13754 3685 8569 1500 63.4 MiB 0.12 0.00 3.65166 -105.903 -3.65166 3.65166 0.34 0.000538237 0.000500843 0.0381477 0.0354746 -1 -1 -1 -1 28 2055 22 6.87369e+06 391268 531479. 1839.03 0.54 0.102196 0.0900138 24610 126494 -1 1741 19 874 1554 114632 26729 3.03561 3.03561 -105.274 -3.03561 0 0 648988. 2245.63 0.03 0.06 0.08 -1 -1 0.03 0.0203082 0.0175966 96 3 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_063.v common 4.89 vpr 63.26 MiB -1 -1 0.23 18412 1 0.03 -1 -1 30272 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64776 32 32 349 273 1 191 101 17 17 289 -1 unnamed_device 24.0 MiB 2.00 1239 18196 5620 10238 2338 63.3 MiB 0.18 0.00 5.34161 -141.066 -5.34161 5.34161 0.33 0.000710511 0.000657709 0.0583585 0.0538307 -1 -1 -1 -1 30 2783 24 6.87369e+06 517032 556674. 1926.21 0.72 0.154647 0.136888 25186 138497 -1 2319 21 1461 2924 184023 42728 4.22195 4.22195 -135.723 -4.22195 0 0 706193. 2443.58 0.03 0.08 0.11 -1 -1 0.03 0.0286229 0.0248525 145 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_064.v common 3.54 vpr 63.56 MiB -1 -1 0.15 17904 1 0.03 -1 -1 30144 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65084 32 32 247 207 1 153 85 17 17 289 -1 unnamed_device 23.9 MiB 1.05 897 15337 5119 7874 2344 63.6 MiB 0.13 0.00 3.56305 -113.438 -3.56305 3.56305 0.33 0.000555907 0.000516935 0.048281 0.0448719 -1 -1 -1 -1 32 2070 20 6.87369e+06 293451 586450. 2029.24 0.56 0.113008 0.100078 25474 144626 -1 1815 21 1262 2238 153889 35786 2.87996 2.87996 -110.843 -2.87996 0 0 744469. 2576.02 0.03 0.07 0.13 -1 -1 0.03 0.0224254 0.0194167 99 3 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_065.v common 4.50 vpr 63.21 MiB -1 -1 0.24 18168 1 0.03 -1 -1 30436 -1 -1 34 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 30 32 278 235 1 151 96 17 17 289 -1 unnamed_device 23.6 MiB 2.07 912 16302 4828 9136 2338 63.2 MiB 0.08 0.00 3.98176 -118.667 -3.98176 3.98176 0.26 0.000276471 0.000248271 0.0217191 0.01981 -1 -1 -1 -1 26 2091 22 6.87369e+06 475111 503264. 1741.40 0.50 0.0611662 0.0536977 24322 120374 -1 1886 19 1130 2030 131294 33386 3.10226 3.10226 -114.681 -3.10226 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0221492 0.0191797 109 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_066.v common 5.18 vpr 63.14 MiB -1 -1 0.26 18392 1 0.03 -1 -1 30332 -1 -1 26 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 29 32 355 287 1 200 87 17 17 289 -1 unnamed_device 23.9 MiB 2.47 1138 9879 2524 6508 847 63.1 MiB 0.11 0.00 4.16737 -125.588 -4.16737 4.16737 0.34 0.00070545 0.000656964 0.038101 0.0354197 -1 -1 -1 -1 26 3080 23 6.87369e+06 363320 503264. 1741.40 0.65 0.124906 0.109698 24322 120374 -1 2586 20 1688 2528 198148 46939 3.83206 3.83206 -130.566 -3.83206 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0271976 0.0236497 136 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_067.v common 4.61 vpr 63.30 MiB -1 -1 0.14 18396 1 0.03 -1 -1 30300 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64820 32 32 358 289 1 183 90 17 17 289 -1 unnamed_device 24.0 MiB 2.07 1034 14763 4115 8879 1769 63.3 MiB 0.15 0.00 4.56255 -145.294 -4.56255 4.56255 0.33 0.000706084 0.000656237 0.0540242 0.050208 -1 -1 -1 -1 32 2336 21 6.87369e+06 363320 586450. 2029.24 0.63 0.138549 0.122618 25474 144626 -1 1904 17 1252 1923 121500 28801 3.85766 3.85766 -135.319 -3.85766 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0134867 0.0119686 132 54 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_068.v common 5.03 vpr 63.16 MiB -1 -1 0.26 18412 1 0.03 -1 -1 30232 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 32 32 353 285 1 188 93 17 17 289 -1 unnamed_device 23.9 MiB 2.18 1032 17103 5602 8670 2831 63.2 MiB 0.17 0.00 4.79103 -139.615 -4.79103 4.79103 0.34 0.000696183 0.000646015 0.0590853 0.0548123 -1 -1 -1 -1 32 2900 27 6.87369e+06 405241 586450. 2029.24 0.67 0.149928 0.132477 25474 144626 -1 2176 23 1449 2597 174377 41794 3.66236 3.66236 -128.606 -3.66236 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0307027 0.0267017 134 51 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_069.v common 4.97 vpr 63.34 MiB -1 -1 0.12 18092 1 0.03 -1 -1 30112 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 32 32 276 237 1 165 81 17 17 289 -1 unnamed_device 23.7 MiB 2.62 947 9706 2619 6448 639 63.3 MiB 0.10 0.00 4.51686 -127.927 -4.51686 4.51686 0.34 0.000594314 0.000552804 0.0348864 0.0324832 -1 -1 -1 -1 32 2103 29 6.87369e+06 237555 586450. 2029.24 0.57 0.11248 0.0986961 25474 144626 -1 1866 21 1041 1496 114762 27029 3.13531 3.13531 -117.494 -3.13531 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0134532 0.0118711 101 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_070.v common 4.98 vpr 63.09 MiB -1 -1 0.25 18468 1 0.03 -1 -1 30400 -1 -1 20 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 31 32 319 272 1 176 83 17 17 289 -1 unnamed_device 24.0 MiB 2.28 815 11963 2932 8103 928 63.1 MiB 0.11 0.00 3.7214 -117.821 -3.7214 3.7214 0.33 0.000642969 0.000598055 0.0446753 0.0415087 -1 -1 -1 -1 32 2447 35 6.87369e+06 279477 586450. 2029.24 0.65 0.132911 0.116764 25474 144626 -1 1648 18 1255 1811 115960 30273 3.13061 3.13061 -113.813 -3.13061 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.023017 0.0200541 110 64 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_071.v common 4.91 vpr 63.10 MiB -1 -1 0.25 18340 1 0.03 -1 -1 30372 -1 -1 34 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 30 32 329 273 1 167 96 17 17 289 -1 unnamed_device 23.9 MiB 2.19 1016 17616 5582 9654 2380 63.1 MiB 0.16 0.00 3.48905 -102.473 -3.48905 3.48905 0.34 0.000658679 0.000611852 0.055243 0.0512742 -1 -1 -1 -1 28 2346 23 6.87369e+06 475111 531479. 1839.03 0.56 0.135181 0.119563 24610 126494 -1 2025 22 1317 2333 143046 35830 2.93056 2.93056 -101.97 -2.93056 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0274558 0.0237741 124 57 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_072.v common 4.74 vpr 63.03 MiB -1 -1 0.23 18160 1 0.03 -1 -1 30408 -1 -1 35 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64544 28 32 277 229 1 156 95 17 17 289 -1 unnamed_device 23.7 MiB 1.62 942 17375 5412 9917 2046 63.0 MiB 0.14 0.00 4.15879 -107.762 -4.15879 4.15879 0.33 0.000596877 0.000555385 0.0497932 0.046256 -1 -1 -1 -1 26 2158 21 6.87369e+06 489084 503264. 1741.40 0.68 0.128929 0.113776 24322 120374 -1 1940 81 3637 6717 511772 117111 3.947 3.947 -114.579 -3.947 0 0 618332. 2139.56 0.03 0.21 0.07 -1 -1 0.03 0.0759938 0.0645077 117 27 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_073.v common 5.24 vpr 63.37 MiB -1 -1 0.12 18380 1 0.03 -1 -1 30424 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64892 30 32 317 269 1 156 80 17 17 289 -1 unnamed_device 24.0 MiB 2.72 914 13496 4233 7612 1651 63.4 MiB 0.14 0.00 3.85608 -120.401 -3.85608 3.85608 0.34 0.000630011 0.000585172 0.051381 0.0476878 -1 -1 -1 -1 32 2066 24 6.87369e+06 251529 586450. 2029.24 0.61 0.132137 0.116563 25474 144626 -1 1808 22 1276 2281 150695 35758 3.09126 3.09126 -120.425 -3.09126 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0273207 0.0236964 105 63 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_074.v common 4.59 vpr 63.08 MiB -1 -1 0.24 18356 1 0.03 -1 -1 30072 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64592 32 32 335 282 1 189 84 17 17 289 -1 unnamed_device 23.9 MiB 2.01 1004 6855 1530 4961 364 63.1 MiB 0.08 0.00 3.6946 -124.308 -3.6946 3.6946 0.33 0.000666465 0.000620289 0.0269554 0.0250659 -1 -1 -1 -1 28 2476 23 6.87369e+06 279477 531479. 1839.03 0.58 0.106325 0.0927977 24610 126494 -1 2194 23 1488 2178 170330 42033 3.28611 3.28611 -130.137 -3.28611 0 0 648988. 2245.63 0.03 0.08 0.12 -1 -1 0.03 0.0285581 0.0246782 118 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_075.v common 3.51 vpr 63.07 MiB -1 -1 0.24 17948 1 0.03 -1 -1 30292 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 31 32 293 230 1 175 96 17 17 289 -1 unnamed_device 24.0 MiB 0.92 1091 9075 2015 6280 780 63.1 MiB 0.10 0.00 4.61548 -132.875 -4.61548 4.61548 0.33 0.000631977 0.000587553 0.028804 0.0267387 -1 -1 -1 -1 26 2616 23 6.87369e+06 461137 503264. 1741.40 0.69 0.105235 0.0920603 24322 120374 -1 2293 21 1418 2488 166028 39907 3.8604 3.8604 -130.723 -3.8604 0 0 618332. 2139.56 0.02 0.04 0.07 -1 -1 0.02 0.0137315 0.012053 130 4 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_076.v common 5.58 vpr 63.24 MiB -1 -1 0.15 18428 1 0.03 -1 -1 30448 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64756 32 32 350 275 1 214 89 17 17 289 -1 unnamed_device 24.3 MiB 2.94 1200 15731 4693 8579 2459 63.2 MiB 0.17 0.00 4.80258 -153.363 -4.80258 4.80258 0.33 0.000703729 0.0006543 0.0576808 0.053582 -1 -1 -1 -1 32 3003 23 6.87369e+06 349346 586450. 2029.24 0.66 0.14232 0.126023 25474 144626 -1 2526 21 1639 2470 197373 45896 4.12826 4.12826 -146.013 -4.12826 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0284546 0.0247738 142 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_077.v common 6.24 vpr 63.32 MiB -1 -1 0.26 18460 1 0.03 -1 -1 30252 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64836 32 32 385 308 1 195 101 17 17 289 -1 unnamed_device 24.2 MiB 3.49 1124 13496 3681 8868 947 63.3 MiB 0.15 0.00 5.22228 -150.906 -5.22228 5.22228 0.34 0.000752487 0.000696927 0.0455464 0.0421192 -1 -1 -1 -1 30 2530 21 6.87369e+06 517032 556674. 1926.21 0.66 0.135733 0.119283 25186 138497 -1 2081 21 1252 2234 136986 32950 3.78145 3.78145 -137.672 -3.78145 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0298214 0.0259139 147 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_078.v common 6.11 vpr 63.93 MiB -1 -1 0.26 18560 1 0.03 -1 -1 30276 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65468 32 32 387 309 1 192 105 17 17 289 -1 unnamed_device 24.2 MiB 2.74 987 13690 3687 9358 645 63.9 MiB 0.14 0.00 4.53808 -140.381 -4.53808 4.53808 0.33 0.000749439 0.000696383 0.0438679 0.0405747 -1 -1 -1 -1 40 2022 24 6.87369e+06 572927 706193. 2443.58 1.23 0.19167 0.166443 26914 176310 -1 1886 21 1261 2401 156153 39758 3.6171 3.6171 -127.506 -3.6171 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0300207 0.0261017 148 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_079.v common 4.70 vpr 63.23 MiB -1 -1 0.23 18128 1 0.03 -1 -1 30216 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64748 30 32 272 232 1 151 80 17 17 289 -1 unnamed_device 23.6 MiB 2.20 813 9024 2370 5899 755 63.2 MiB 0.10 0.00 3.89188 -117.262 -3.89188 3.89188 0.33 0.000584829 0.000544928 0.0324753 0.0302551 -1 -1 -1 -1 32 1912 21 6.87369e+06 251529 586450. 2029.24 0.55 0.100521 0.0882835 25474 144626 -1 1652 20 1057 1880 121709 29083 2.97696 2.97696 -107.258 -2.97696 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226212 0.0196254 99 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_080.v common 5.57 vpr 63.89 MiB -1 -1 0.14 18284 1 0.02 -1 -1 30372 -1 -1 23 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65424 30 32 375 299 1 188 85 17 17 289 -1 unnamed_device 24.0 MiB 3.12 1029 9757 2105 6512 1140 63.9 MiB 0.12 0.00 4.57902 -143.928 -4.57902 4.57902 0.33 0.000730298 0.000678703 0.0403111 0.0374677 -1 -1 -1 -1 28 2535 23 6.87369e+06 321398 531479. 1839.03 0.64 0.127412 0.111966 24610 126494 -1 2307 21 1874 2865 205104 49082 3.9547 3.9547 -144.752 -3.9547 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0166106 0.0146556 137 63 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_081.v common 5.03 vpr 63.10 MiB -1 -1 0.24 18356 1 0.03 -1 -1 30352 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 32 32 340 270 1 204 89 17 17 289 -1 unnamed_device 23.9 MiB 2.02 1137 13355 3696 8021 1638 63.1 MiB 0.15 0.00 5.16481 -152.482 -5.16481 5.16481 0.33 0.00068747 0.000638496 0.0488585 0.0454013 -1 -1 -1 -1 28 3018 30 6.87369e+06 349346 531479. 1839.03 0.86 0.140547 0.123885 24610 126494 -1 2524 24 1875 2946 236442 55729 4.90886 4.90886 -155.241 -4.90886 0 0 648988. 2245.63 0.03 0.09 0.11 -1 -1 0.03 0.0312093 0.027068 136 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_082.v common 6.14 vpr 63.24 MiB -1 -1 0.24 18392 1 0.03 -1 -1 30196 -1 -1 31 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 31 32 340 275 1 201 94 17 17 289 -1 unnamed_device 24.0 MiB 2.51 1095 17560 6469 8624 2467 63.2 MiB 0.17 0.00 5.28104 -147.847 -5.28104 5.28104 0.33 0.000689075 0.000639545 0.0588762 0.0546834 -1 -1 -1 -1 28 3079 44 6.87369e+06 433189 531479. 1839.03 1.22 0.166584 0.14682 24610 126494 -1 2291 23 1877 3073 206403 52519 4.5206 4.5206 -147.07 -4.5206 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64784 32 32 365 294 1 187 86 17 17 289 -1 unnamed_device 24.0 MiB 2.29 977 11804 3582 6996 1226 63.3 MiB 0.15 0.00 4.77578 -141.077 -4.77578 4.77578 0.34 0.000721237 0.000668993 0.0471484 0.0438001 -1 -1 -1 -1 30 2619 21 6.87369e+06 307425 556674. 1926.21 0.66 0.132756 0.116983 25186 138497 -1 2066 20 1426 2450 128813 33448 3.90766 3.90766 -135.71 -3.90766 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0277408 0.024151 132 57 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_085.v common 5.03 vpr 63.49 MiB -1 -1 0.27 18544 1 0.03 -1 -1 30308 -1 -1 29 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65016 29 32 378 310 1 179 90 17 17 289 -1 unnamed_device 24.2 MiB 2.28 945 16170 4095 11127 948 63.5 MiB 0.16 0.00 4.12999 -122.875 -4.12999 4.12999 0.33 0.000715356 0.000664292 0.0600459 0.055713 -1 -1 -1 -1 32 2398 22 6.87369e+06 405241 586450. 2029.24 0.61 0.145064 0.128358 25474 144626 -1 1959 21 1386 2247 136731 34828 3.12181 3.12181 -115.774 -3.12181 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0291387 0.025244 132 85 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_086.v common 3.69 vpr 63.22 MiB -1 -1 0.21 17864 1 0.03 -1 -1 30328 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64736 32 32 243 205 1 149 82 17 17 289 -1 unnamed_device 23.6 MiB 1.07 892 12542 3412 7235 1895 63.2 MiB 0.11 0.00 3.98264 -119.291 -3.98264 3.98264 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65128 32 32 269 231 1 170 82 17 17 289 -1 unnamed_device 23.9 MiB 2.13 994 9694 2678 5995 1021 63.6 MiB 0.10 0.00 4.37292 -124.998 -4.37292 4.37292 0.33 0.00058825 0.000548397 0.0336292 0.0313019 -1 -1 -1 -1 26 2325 22 6.87369e+06 251529 503264. 1741.40 0.62 0.103077 0.090504 24322 120374 -1 2098 22 1212 1576 117648 28606 3.4928 3.4928 -124.305 -3.4928 0 0 618332. 2139.56 0.03 0.06 0.10 -1 -1 0.03 0.0245323 0.0212581 103 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_090.v common 3.70 vpr 63.16 MiB -1 -1 0.23 17880 1 0.03 -1 -1 30368 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64680 31 32 245 205 1 153 84 17 17 289 -1 unnamed_device 23.7 MiB 1.09 879 14358 4211 8419 1728 63.2 MiB 0.13 0.00 3.81898 -115.032 -3.81898 3.81898 0.33 0.000551096 0.000512803 0.0451184 0.0419713 -1 -1 -1 -1 32 1927 21 6.87369e+06 293451 586450. 2029.24 0.58 0.11685 0.103169 25474 144626 -1 1705 21 1147 1895 134417 30219 2.80196 2.80196 -107.148 -2.80196 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226517 0.0196196 100 4 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_091.v common 5.14 vpr 63.21 MiB -1 -1 0.24 18416 1 0.03 -1 -1 30464 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 32 32 348 274 1 215 88 17 17 289 -1 unnamed_device 24.0 MiB 2.49 1167 13738 4717 6121 2900 63.2 MiB 0.14 0.00 4.82535 -151.45 -4.82535 4.82535 0.34 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65128 30 32 316 264 1 165 96 17 17 289 -1 unnamed_device 24.0 MiB 2.11 882 12798 3427 7781 1590 63.6 MiB 0.12 0.00 3.60295 -105.856 -3.60295 3.60295 0.33 0.000644126 0.000598529 0.0398531 0.0369682 -1 -1 -1 -1 30 1919 24 6.87369e+06 475111 556674. 1926.21 0.60 0.11996 0.10565 25186 138497 -1 1665 19 1031 1845 92885 24170 2.80666 2.80666 -100.682 -2.80666 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0237563 0.0206309 119 52 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_095.v common 3.39 vpr 63.20 MiB -1 -1 0.12 18080 1 0.03 -1 -1 30460 -1 -1 24 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64720 27 32 255 219 1 139 83 17 17 289 -1 unnamed_device 23.6 MiB 0.98 659 7643 1786 5184 673 63.2 MiB 0.07 0.00 3.59463 -97.3218 -3.59463 3.59463 0.34 0.000551197 0.000513497 0.0250754 0.0233186 -1 -1 -1 -1 30 1508 21 6.87369e+06 335372 556674. 1926.21 0.53 0.0893672 0.0779488 25186 138497 -1 1307 22 912 1404 85222 19958 2.71066 2.71066 -92.8097 -2.71066 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0229535 0.0198213 97 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_096.v common 5.57 vpr 63.50 MiB -1 -1 0.26 18408 1 0.03 -1 -1 30300 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65020 32 32 421 327 1 233 90 17 17 289 -1 unnamed_device 24.5 MiB 2.67 1401 16170 4964 9023 2183 63.5 MiB 0.19 0.00 4.57338 -144.339 -4.57338 4.57338 0.34 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64592 32 32 326 263 1 176 97 17 17 289 -1 unnamed_device 23.9 MiB 1.26 996 18079 6285 9338 2456 63.1 MiB 0.17 0.00 5.05545 -135.157 -5.05545 5.05545 0.34 0.0006787 0.00062261 0.0569607 0.0526736 -1 -1 -1 -1 28 2735 32 6.87369e+06 461137 531479. 1839.03 0.90 0.150988 0.132992 24610 126494 -1 2184 23 1538 2474 186286 44655 3.7844 3.7844 -127.117 -3.7844 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0289064 0.0250237 129 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_100.v common 4.36 vpr 63.26 MiB -1 -1 0.27 18324 1 0.03 -1 -1 30424 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64776 31 32 373 294 1 197 97 17 17 289 -1 unnamed_device 24.2 MiB 1.61 975 8977 1882 6473 622 63.3 MiB 0.10 0.00 4.47518 -127.7 -4.47518 4.47518 0.34 0.000735349 0.000682437 0.0320028 0.0296931 -1 -1 -1 -1 30 2526 22 6.87369e+06 475111 556674. 1926.21 0.65 0.121632 0.106372 25186 138497 -1 1772 20 1161 1988 89442 23941 3.59926 3.59926 -123.864 -3.59926 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0287372 0.0250502 149 50 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_101.v common 4.69 vpr 63.14 MiB -1 -1 0.25 18476 1 0.03 -1 -1 30092 -1 -1 31 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 30 32 325 268 1 172 93 17 17 289 -1 unnamed_device 24.0 MiB 1.89 1016 17523 5783 9680 2060 63.1 MiB 0.16 0.00 3.6935 -107.395 -3.6935 3.6935 0.33 0.000656932 0.000610154 0.0564618 0.0524435 -1 -1 -1 -1 32 2389 47 6.87369e+06 433189 586450. 2029.24 0.66 0.157482 0.138428 25474 144626 -1 2002 22 1287 2224 135136 33535 3.14781 3.14781 -106.636 -3.14781 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0272988 0.0236707 124 51 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_102.v common 6.12 vpr 63.13 MiB -1 -1 0.25 18248 1 0.03 -1 -1 30228 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 32 32 350 275 1 215 88 17 17 289 -1 unnamed_device 24.1 MiB 3.33 1248 13738 4274 7446 2018 63.1 MiB 0.15 0.00 4.85883 -154.737 -4.85883 4.85883 0.33 0.000713451 0.000654801 0.0520909 0.0481021 -1 -1 -1 -1 32 3121 22 6.87369e+06 335372 586450. 2029.24 0.63 0.136198 0.12007 25474 144626 -1 2484 20 1815 2844 200706 47665 4.17706 4.17706 -148.515 -4.17706 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0274458 0.0239019 143 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_103.v common 5.85 vpr 63.91 MiB -1 -1 0.25 18376 1 0.03 -1 -1 30128 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65444 32 32 386 307 1 196 100 17 17 289 -1 unnamed_device 24.3 MiB 3.01 1086 10308 2517 7280 511 63.9 MiB 0.12 0.00 4.14663 -136.709 -4.14663 4.14663 0.34 0.000747845 0.000694676 0.0358158 0.0332704 -1 -1 -1 -1 28 2852 22 6.87369e+06 503058 531479. 1839.03 0.74 0.128014 0.1121 24610 126494 -1 2345 20 1518 2459 158677 39350 3.26061 3.26061 -128.829 -3.26061 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0293717 0.0255279 148 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_104.v common 4.20 vpr 63.19 MiB -1 -1 0.22 18280 1 0.03 -1 -1 30284 -1 -1 20 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64708 29 32 269 229 1 150 81 17 17 289 -1 unnamed_device 23.5 MiB 1.73 676 13381 4841 5719 2821 63.2 MiB 0.12 0.00 3.95844 -115.993 -3.95844 3.95844 0.33 0.000576391 0.00053603 0.0458306 0.0426133 -1 -1 -1 -1 32 1602 21 6.87369e+06 279477 586450. 2029.24 0.54 0.11245 0.0993597 25474 144626 -1 1303 20 1078 1620 101124 24300 3.02726 3.02726 -105.477 -3.02726 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226321 0.0196502 101 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_105.v common 4.33 vpr 63.11 MiB -1 -1 0.24 18380 1 0.03 -1 -1 30284 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64624 32 32 310 266 1 175 84 17 17 289 -1 unnamed_device 24.0 MiB 1.51 1025 15456 4644 9539 1273 63.1 MiB 0.15 0.00 3.98516 -120.978 -3.98516 3.98516 0.33 0.000629119 0.000584837 0.0550716 0.051179 -1 -1 -1 -1 26 2517 27 6.87369e+06 279477 503264. 1741.40 0.77 0.135191 0.119354 24322 120374 -1 2108 22 1426 1967 170507 40619 3.43941 3.43941 -126.369 -3.43941 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0266223 0.0230652 108 58 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 4.68 vpr 63.76 MiB -1 -1 0.15 18476 1 0.03 -1 -1 30344 -1 -1 39 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65292 31 32 326 261 1 178 102 17 17 289 -1 unnamed_device 24.0 MiB 1.43 987 18428 5110 10243 3075 63.8 MiB 0.17 0.00 4.59612 -128.416 -4.59612 4.59612 0.33 0.00066769 0.000620041 0.0537939 0.049922 -1 -1 -1 -1 26 2846 38 6.87369e+06 544980 503264. 1741.40 1.16 0.153274 0.135079 24322 120374 -1 2300 23 1587 2983 214840 50593 4.066 4.066 -137.302 -4.066 0 0 618332. 2139.56 0.02 0.05 0.07 -1 -1 0.02 0.0152959 0.0134031 135 33 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_107.v common 4.72 vpr 63.51 MiB -1 -1 0.22 18056 1 0.03 -1 -1 30240 -1 -1 20 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65032 29 32 262 224 1 168 81 17 17 289 -1 unnamed_device 23.9 MiB 2.21 926 13031 3833 7297 1901 63.5 MiB 0.12 0.00 4.39772 -121.351 -4.39772 4.39772 0.34 0.000564946 0.000526026 0.0438255 0.0407939 -1 -1 -1 -1 26 2366 26 6.87369e+06 279477 503264. 1741.40 0.58 0.115317 0.101479 24322 120374 -1 1950 21 1326 1745 124283 31179 3.5018 3.5018 -119.379 -3.5018 0 0 618332. 2139.56 0.03 0.06 0.10 -1 -1 0.03 0.0230083 0.0198986 103 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_108.v common 6.22 vpr 63.16 MiB -1 -1 0.23 18184 1 0.03 -1 -1 30060 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64672 32 32 278 238 1 158 81 17 17 289 -1 unnamed_device 23.5 MiB 3.10 830 13556 5623 7156 777 63.2 MiB 0.12 0.00 3.89598 -121.823 -3.89598 3.89598 0.34 0.000599774 0.000558122 0.0486182 0.0452549 -1 -1 -1 -1 30 2401 40 6.87369e+06 237555 556674. 1926.21 1.16 0.151662 0.13314 25186 138497 -1 1517 22 1110 1832 122846 32031 2.91031 2.91031 -105.79 -2.91031 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0248086 0.0215212 102 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_109.v common 5.22 vpr 63.86 MiB -1 -1 0.26 18380 1 0.03 -1 -1 30372 -1 -1 38 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65392 31 32 373 300 1 185 101 17 17 289 -1 unnamed_device 24.3 MiB 2.52 996 8326 1655 6069 602 63.9 MiB 0.09 0.00 3.95528 -124.82 -3.95528 3.95528 0.33 0.00073019 0.000672729 0.028011 0.0259846 -1 -1 -1 -1 30 2187 19 6.87369e+06 531006 556674. 1926.21 0.58 0.110267 0.0962367 25186 138497 -1 1812 19 1272 2135 103364 26073 2.96596 2.96596 -116.595 -2.96596 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0270136 0.0235073 142 64 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_110.v common 4.45 vpr 63.19 MiB -1 -1 0.23 18184 1 0.03 -1 -1 30328 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 31 32 265 230 1 169 81 17 17 289 -1 unnamed_device 23.5 MiB 1.98 964 7606 1989 5205 412 63.2 MiB 0.08 0.00 3.71466 -116.831 -3.71466 3.71466 0.33 0.00058092 0.000541652 0.026736 0.0248919 -1 -1 -1 -1 30 2104 20 6.87369e+06 251529 556674. 1926.21 0.54 0.0928595 0.0811791 25186 138497 -1 1736 21 950 1365 79050 19847 3.06461 3.06461 -112.199 -3.06461 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0278341 0.0244082 101 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_111.v common 5.45 vpr 63.81 MiB -1 -1 0.25 18348 1 0.03 -1 -1 29996 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65340 32 32 349 286 1 177 96 17 17 289 -1 unnamed_device 24.1 MiB 2.52 1048 13455 3508 9157 790 63.8 MiB 0.13 0.00 3.8199 -117.926 -3.8199 3.8199 0.34 0.000698483 0.000649166 0.0451115 0.0418957 -1 -1 -1 -1 26 2805 33 6.87369e+06 447163 503264. 1741.40 0.91 0.145167 0.127573 24322 120374 -1 2183 29 1347 2248 170016 40039 3.04151 3.04151 -116.867 -3.04151 0 0 618332. 2139.56 0.03 0.09 0.10 -1 -1 0.03 0.0361119 0.0312691 130 57 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_112.v common 5.38 vpr 63.44 MiB -1 -1 0.15 18316 1 0.04 -1 -1 30280 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64960 31 32 396 325 1 185 96 17 17 289 -1 unnamed_device 24.4 MiB 2.88 1015 16959 5374 8849 2736 63.4 MiB 0.17 0.00 3.7606 -128.355 -3.7606 3.7606 0.33 0.000748216 0.000694083 0.0605097 0.0561856 -1 -1 -1 -1 32 2262 24 6.87369e+06 461137 586450. 2029.24 0.59 0.150753 0.133203 25474 144626 -1 1821 20 1416 2136 127559 31716 2.80391 2.80391 -117.048 -2.80391 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0156045 0.0137633 138 91 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_113.v common 4.70 vpr 63.33 MiB -1 -1 0.24 18292 1 0.03 -1 -1 30324 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64852 32 32 303 262 1 154 81 17 17 289 -1 unnamed_device 24.0 MiB 2.09 926 11806 3071 7035 1700 63.3 MiB 0.11 0.00 3.46595 -111.033 -3.46595 3.46595 0.34 0.000626318 0.000581564 0.0441167 0.0410371 -1 -1 -1 -1 32 1999 19 6.87369e+06 237555 586450. 2029.24 0.56 0.115252 0.101659 25474 144626 -1 1755 16 874 1380 84592 21150 2.99146 2.99146 -110.25 -2.99146 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0205676 0.0179449 99 57 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_114.v common 4.69 vpr 63.04 MiB -1 -1 0.23 18180 1 0.03 -1 -1 30264 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 32 32 290 244 1 176 83 17 17 289 -1 unnamed_device 24.0 MiB 1.70 868 9623 2653 6092 878 63.0 MiB 0.10 0.00 4.12463 -125.158 -4.12463 4.12463 0.29 0.000611296 0.000568942 0.0346504 0.0322298 -1 -1 -1 -1 28 2577 24 6.87369e+06 265503 531479. 1839.03 0.64 0.108794 0.0953846 24610 126494 -1 2089 21 1614 2365 175909 43157 3.21861 3.21861 -122.623 -3.21861 0 0 648988. 2245.63 0.03 0.08 0.07 -1 -1 0.03 0.0247676 0.021436 110 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_115.v common 4.68 vpr 63.23 MiB -1 -1 0.12 18288 1 0.03 -1 -1 30172 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 32 32 318 257 1 196 86 17 17 289 -1 unnamed_device 24.1 MiB 2.03 1052 5567 1101 4155 311 63.2 MiB 0.07 0.00 4.84388 -137.106 -4.84388 4.84388 0.33 0.000657365 0.000611273 0.0214686 0.0199696 -1 -1 -1 -1 26 2782 21 6.87369e+06 307425 503264. 1741.40 0.77 0.101909 0.0887736 24322 120374 -1 2258 23 1745 2467 162233 39815 4.05606 4.05606 -137.797 -4.05606 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0293776 0.0254551 128 30 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_116.v common 5.13 vpr 63.11 MiB -1 -1 0.25 18372 1 0.03 -1 -1 30196 -1 -1 29 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64624 29 32 324 268 1 169 90 17 17 289 -1 unnamed_device 24.0 MiB 2.37 1060 14562 4184 8868 1510 63.1 MiB 0.14 0.00 4.11363 -115.792 -4.11363 4.11363 0.34 0.000654586 0.000608681 0.0494721 0.0459961 -1 -1 -1 -1 30 2285 32 6.87369e+06 405241 556674. 1926.21 0.70 0.138159 0.121704 25186 138497 -1 1890 18 982 1734 104165 24665 3.11651 3.11651 -108.645 -3.11651 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.023576 0.0205441 123 55 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_117.v common 6.17 vpr 64.10 MiB -1 -1 0.26 18404 1 0.03 -1 -1 30556 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65640 32 32 393 312 1 215 88 17 17 289 -1 unnamed_device 24.4 MiB 2.82 1203 9838 2479 6641 718 64.1 MiB 0.07 0.00 5.21116 -164.931 -5.21116 5.21116 0.32 0.000342348 0.000315851 0.0195076 0.017971 -1 -1 -1 -1 26 3413 41 6.87369e+06 335372 503264. 1741.40 1.24 0.136273 0.117963 24322 120374 -1 2693 21 2122 3152 243393 57965 4.48486 4.48486 -163.249 -4.48486 0 0 618332. 2139.56 0.03 0.10 0.10 -1 -1 0.03 0.0332255 0.0289183 148 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_118.v common 3.52 vpr 63.05 MiB -1 -1 0.13 17992 1 0.03 -1 -1 30080 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64568 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 23.5 MiB 1.06 844 13556 4454 6953 2149 63.1 MiB 0.11 0.00 3.44201 -103.957 -3.44201 3.44201 0.33 0.000529031 0.000492592 0.0429559 0.0399555 -1 -1 -1 -1 32 1714 22 6.87369e+06 251529 586450. 2029.24 0.52 0.105722 0.0934036 25474 144626 -1 1496 19 749 1215 76767 19027 2.80296 2.80296 -100.579 -2.80296 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0199165 0.0172949 93 4 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_119.v common 4.64 vpr 64.04 MiB -1 -1 0.26 18464 1 0.03 -1 -1 30180 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65572 32 32 412 334 1 194 99 17 17 289 -1 unnamed_device 24.3 MiB 1.86 1127 14007 4056 9039 912 64.0 MiB 0.15 0.00 4.44135 -147.306 -4.44135 4.44135 0.33 0.000765121 0.0007102 0.0495822 0.0459695 -1 -1 -1 -1 32 2681 24 6.87369e+06 489084 586450. 2029.24 0.63 0.142967 0.125789 25474 144626 -1 2165 21 1488 2138 146818 34899 3.61706 3.61706 -138.505 -3.61706 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0315295 0.0274102 145 90 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_120.v common 6.55 vpr 63.58 MiB -1 -1 0.24 18480 1 0.03 -1 -1 30084 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65104 32 32 376 318 1 168 82 17 17 289 -1 unnamed_device 24.3 MiB 3.93 818 7914 1986 4991 937 63.6 MiB 0.09 0.00 3.65241 -126.689 -3.65241 3.65241 0.33 0.000716521 0.000665697 0.0339799 0.0315396 -1 -1 -1 -1 32 2064 21 6.87369e+06 251529 586450. 2029.24 0.59 0.116999 0.102344 25474 144626 -1 1733 19 1279 1863 114597 28329 3.23576 3.23576 -126.641 -3.23576 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0262627 0.022804 114 96 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_121.v common 6.17 vpr 63.64 MiB -1 -1 0.25 18384 1 0.03 -1 -1 30248 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65164 32 32 360 293 1 182 97 17 17 289 -1 unnamed_device 23.9 MiB 2.69 898 12973 3607 6302 3064 63.6 MiB 0.12 0.00 4.14663 -123.081 -4.14663 4.14663 0.34 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 30 32 286 239 1 151 82 17 17 289 -1 unnamed_device 23.7 MiB 1.04 731 7380 1917 5120 343 63.3 MiB 0.08 0.00 3.87678 -118.42 -3.87678 3.87678 0.33 0.000600531 0.000558766 0.026782 0.0248795 -1 -1 -1 -1 32 1689 23 6.87369e+06 279477 586450. 2029.24 0.55 0.0992538 0.0866565 25474 144626 -1 1447 20 1008 1567 100138 24264 2.91726 2.91726 -109.833 -2.91726 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.023328 0.0202272 106 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_125.v common 3.96 vpr 63.45 MiB -1 -1 0.23 18024 1 0.03 -1 -1 30136 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 32 32 354 285 1 223 90 17 17 289 -1 unnamed_device 23.9 MiB 1.53 1144 16773 5687 8252 2834 63.1 MiB 0.17 0.00 5.45687 -159.577 -5.45687 5.45687 0.34 0.000707441 0.000653701 0.061291 0.0568531 -1 -1 -1 -1 34 2960 24 6.89349e+06 366440 618332. 2139.56 1.09 0.207628 0.181784 25762 151098 -1 2314 21 1560 2311 158787 38584 4.32749 4.32749 -146.434 -4.32749 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0285389 0.0248246 147 50 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_002.v common 4.15 vpr 63.02 MiB -1 -1 0.15 18292 1 0.03 -1 -1 30292 -1 -1 27 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64528 30 32 363 293 1 229 89 17 17 289 -1 unnamed_device 23.8 MiB 1.45 1225 15929 4471 9301 2157 63.0 MiB 0.17 0.00 4.93328 -152.269 -4.93328 4.93328 0.33 0.00070826 0.000658533 0.059288 0.0551026 -1 -1 -1 -1 32 2735 20 6.89349e+06 380534 586450. 2029.24 0.63 0.140514 0.124521 25474 144626 -1 2348 22 1808 2627 169139 39727 4.37429 4.37429 -148.001 -4.37429 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0294465 0.0255588 152 63 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_003.v common 3.95 vpr 63.16 MiB -1 -1 0.15 18440 1 0.03 -1 -1 30276 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64680 32 32 299 247 1 190 86 17 17 289 -1 unnamed_device 23.8 MiB 1.46 1082 9347 2400 6379 568 63.2 MiB 0.11 0.00 4.40779 -123.677 -4.40779 4.40779 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/home/elgamma8/research/release/vtr-verilog-to-routing 64608 27 32 259 221 1 159 82 17 17 289 -1 unnamed_device 23.4 MiB 1.06 879 11118 3409 5655 2054 63.1 MiB 0.10 0.00 4.18543 -114.454 -4.18543 4.18543 0.33 0.000554655 0.000516362 0.0367097 0.0341929 -1 -1 -1 -1 32 1862 23 6.89349e+06 324158 586450. 2029.24 0.56 0.103219 0.0906636 25474 144626 -1 1552 19 1103 1617 122140 28845 3.05681 3.05681 -101.377 -3.05681 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.020955 0.0181463 104 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_008.v common 3.23 vpr 63.25 MiB -1 -1 0.24 17896 1 0.03 -1 -1 30072 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64768 31 32 271 219 1 164 96 17 17 289 -1 unnamed_device 23.7 MiB 0.69 1005 15426 4709 8488 2229 63.2 MiB 0.13 0.00 3.4228 -103.716 -3.4228 3.4228 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/home/elgamma8/research/release/vtr-verilog-to-routing 64692 32 32 276 237 1 171 82 17 17 289 -1 unnamed_device 23.6 MiB 1.10 901 12008 3961 5948 2099 63.2 MiB 0.06 0.00 3.74726 -113.02 -3.74726 3.74726 0.25 0.00026857 0.000246966 0.0193216 0.0178049 -1 -1 -1 -1 32 2217 28 6.89349e+06 253689 586450. 2029.24 0.42 0.0559151 0.0489354 25474 144626 -1 1652 16 887 1232 89434 21858 2.94461 2.94461 -102.907 -2.94461 0 0 744469. 2576.02 0.03 0.05 0.13 -1 -1 0.03 0.0193158 0.016865 103 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_013.v common 4.97 vpr 63.11 MiB -1 -1 0.25 18540 1 0.03 -1 -1 30284 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64620 32 32 344 272 1 209 89 17 17 289 -1 unnamed_device 23.9 MiB 1.57 1074 17909 6040 8736 3133 63.1 MiB 0.19 0.00 4.12632 -131.306 -4.12632 4.12632 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27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 32 32 370 297 1 234 91 17 17 289 -1 unnamed_device 24.0 MiB 2.18 1431 13351 3686 8381 1284 63.2 MiB 0.16 0.00 4.1691 -138.277 -4.1691 4.1691 0.34 0.000725196 0.000673597 0.0499479 0.0463746 -1 -1 -1 -1 32 3294 30 6.89349e+06 380534 586450. 2029.24 0.77 0.151269 0.133213 25474 144626 -1 2734 21 1994 3084 228982 52255 3.74455 3.74455 -136.57 -3.74455 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0292561 0.0254045 157 58 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_017.v common 4.44 vpr 63.09 MiB -1 -1 0.15 18504 1 0.03 -1 -1 30092 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64604 32 32 338 269 1 205 89 17 17 289 -1 unnamed_device 23.9 MiB 1.60 1160 9593 2673 5745 1175 63.1 MiB 0.11 0.00 4.11158 -133.367 -4.11158 4.11158 0.33 0.000685651 0.000637337 0.0352935 0.0328014 -1 -1 -1 -1 34 2547 20 6.89349e+06 352346 618332. 2139.56 0.97 0.173434 0.15089 25762 151098 -1 2202 19 1226 1793 150582 33445 2.96516 2.96516 -117.404 -2.96516 0 0 787024. 2723.27 0.03 0.04 0.09 -1 -1 0.03 0.0144492 0.0127946 138 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_018.v common 5.42 vpr 62.96 MiB -1 -1 0.14 18316 1 0.03 -1 -1 30408 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64476 32 32 323 276 1 215 88 17 17 289 -1 unnamed_device 23.8 MiB 1.51 1219 7888 1702 5732 454 63.0 MiB 0.10 0.00 3.59345 -126.377 -3.59345 3.59345 0.34 0.000652743 0.000606899 0.0293208 0.0272933 -1 -1 -1 -1 30 2682 34 6.89349e+06 338252 556674. 1926.21 1.97 0.239653 0.205887 25186 138497 -1 2052 17 1244 1673 101028 24727 2.79796 2.79796 -117.425 -2.79796 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0223332 0.0194694 128 65 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_019.v common 3.07 vpr 63.13 MiB -1 -1 0.20 18224 1 0.03 -1 -1 30144 -1 -1 16 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 30 32 222 206 1 141 78 17 17 289 -1 unnamed_device 23.7 MiB 0.69 830 12694 4493 6588 1613 63.1 MiB 0.10 0.00 2.70263 -92.4151 -2.70263 2.70263 0.33 0.000497119 0.000462474 0.0395541 0.0367909 -1 -1 -1 -1 26 1667 21 6.89349e+06 225501 503264. 1741.40 0.57 0.098353 0.0869129 24322 120374 -1 1469 15 644 725 56762 13692 2.10807 2.10807 -91.092 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35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 32 32 342 271 1 207 99 17 17 289 -1 unnamed_device 23.9 MiB 1.31 1197 19479 5549 11862 2068 63.1 MiB 0.19 0.00 4.72649 -149.912 -4.72649 4.72649 0.37 0.000706398 0.000656772 0.0619063 0.0575159 -1 -1 -1 -1 34 2608 22 6.89349e+06 493284 618332. 2139.56 1.01 0.197307 0.172912 25762 151098 -1 2194 20 1354 2047 139470 34278 4.03544 4.03544 -144.363 -4.03544 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0275815 0.0240026 150 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_022.v common 4.77 vpr 63.10 MiB -1 -1 0.25 18376 1 0.03 -1 -1 30376 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 32 32 372 300 1 229 89 17 17 289 -1 unnamed_device 23.9 MiB 1.25 1325 9791 2524 6598 669 63.1 MiB 0.13 0.00 4.60648 -139.803 -4.60648 4.60648 0.33 0.000731497 0.000680237 0.0409879 0.0380157 -1 -1 -1 -1 26 3361 41 6.89349e+06 352346 503264. 1741.40 1.33 0.161648 0.141511 24322 120374 -1 2926 25 2536 3825 316091 89851 3.9097 3.9097 -143.697 -3.9097 0 0 618332. 2139.56 0.03 0.12 0.10 -1 -1 0.03 0.0337451 0.0292678 154 62 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_023.v common 3.15 vpr 63.02 MiB -1 -1 0.21 18180 1 0.02 -1 -1 30560 -1 -1 19 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64532 26 32 190 182 1 126 77 17 17 289 -1 unnamed_device 23.6 MiB 0.72 539 10346 4260 5337 749 63.0 MiB 0.07 0.00 2.69961 -73.3828 -2.69961 2.69961 0.34 0.000428627 0.000398029 0.0284074 0.0263245 -1 -1 -1 -1 28 1430 47 6.89349e+06 267783 531479. 1839.03 0.60 0.100975 0.0884533 24610 126494 -1 1019 14 577 682 43677 12108 2.11835 2.11835 -70.8739 -2.11835 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.0077792 0.00694829 72 30 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_024.v common 4.58 vpr 63.12 MiB -1 -1 0.23 17996 1 0.03 -1 -1 30308 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64640 32 32 285 227 1 169 87 17 17 289 -1 unnamed_device 23.6 MiB 0.98 1063 11799 3182 7057 1560 63.1 MiB 0.12 0.00 4.60563 -130.083 -4.60563 4.60563 0.33 0.000618593 0.000574802 0.0400595 0.0372659 -1 -1 -1 -1 32 2381 24 6.89349e+06 324158 586450. 2029.24 1.59 0.232922 0.201157 25474 144626 -1 1999 22 1208 2278 146746 35126 3.61225 3.61225 -118.524 -3.61225 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0317339 0.0274249 119 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_025.v common 3.02 vpr 62.83 MiB -1 -1 0.21 17648 1 0.02 -1 -1 30064 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64340 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 23.6 MiB 0.50 458 9356 2990 4431 1935 62.8 MiB 0.06 0.00 2.39862 -72.6001 -2.39862 2.39862 0.33 0.000423472 0.000392915 0.0258794 0.024019 -1 -1 -1 -1 28 1318 45 6.89349e+06 169126 531479. 1839.03 0.63 0.0914474 0.079783 24610 126494 -1 1010 26 617 760 72909 29156 2.06796 2.06796 -77.4474 -2.06796 0 0 648988. 2245.63 0.03 0.06 0.10 -1 -1 0.03 0.0206634 0.0178415 65 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_026.v common 4.11 vpr 63.18 MiB -1 -1 0.24 18204 1 0.03 -1 -1 30152 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 32 32 300 245 1 187 86 17 17 289 -1 unnamed_device 23.8 MiB 1.33 1053 11993 3304 7573 1116 63.2 MiB 0.13 0.00 4.96363 -136.721 -4.96363 4.96363 0.33 0.000634294 0.000590454 0.0424028 0.0394305 -1 -1 -1 -1 26 2626 25 6.89349e+06 310065 503264. 1741.40 0.71 0.126284 0.111236 24322 120374 -1 2255 19 1275 1846 130434 31937 4.03626 4.03626 -132.507 -4.03626 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0237551 0.0206724 121 24 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_027.v common 4.10 vpr 63.39 MiB -1 -1 0.13 17964 1 0.03 -1 -1 30384 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64916 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 23.7 MiB 0.72 1102 17591 5006 10257 2328 63.4 MiB 0.16 0.00 3.451 -111.885 -3.451 3.451 0.33 0.00063647 0.000592222 0.0539327 0.050037 -1 -1 -1 -1 28 2445 37 6.89349e+06 436909 531479. 1839.03 0.74 0.144368 0.127087 24610 126494 -1 2122 22 1263 2289 148196 36337 2.70081 2.70081 -107.98 -2.70081 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0265493 0.0230306 130 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_028.v common 4.69 vpr 63.19 MiB -1 -1 0.22 18324 1 0.04 -1 -1 30232 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 32 32 338 277 1 215 89 17 17 289 -1 unnamed_device 24.0 MiB 1.53 1243 15731 5322 7942 2467 63.2 MiB 0.16 0.00 4.85308 -135.583 -4.85308 4.85308 0.34 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 28 32 260 223 1 163 85 17 17 289 -1 unnamed_device 23.6 MiB 1.23 910 14593 5077 7414 2102 63.1 MiB 0.13 0.00 4.29929 -120.332 -4.29929 4.29929 0.34 0.000557357 0.000518617 0.0461162 0.0428912 -1 -1 -1 -1 32 2100 20 6.89349e+06 352346 586450. 2029.24 0.56 0.111197 0.098241 25474 144626 -1 1696 21 895 1529 95985 22999 3.23235 3.23235 -110.54 -3.23235 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0122668 0.0107644 108 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_032.v common 3.76 vpr 63.04 MiB -1 -1 0.23 17900 1 0.03 -1 -1 30224 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 32 32 253 210 1 156 82 17 17 289 -1 unnamed_device 23.5 MiB 1.06 749 9160 2232 6447 481 63.0 MiB 0.09 0.00 3.86328 -116.366 -3.86328 3.86328 0.33 0.000573773 0.000532341 0.031373 0.0291874 -1 -1 -1 -1 28 2273 28 6.89349e+06 253689 531479. 1839.03 0.68 0.104099 0.0910894 24610 126494 -1 1785 34 1750 3035 275769 99959 2.87716 2.87716 -113.369 -2.87716 0 0 648988. 2245.63 0.03 0.12 0.10 -1 -1 0.03 0.0338085 0.0290584 101 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_033.v common 3.63 vpr 63.10 MiB -1 -1 0.24 18240 1 0.03 -1 -1 30132 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 31 32 271 231 1 172 84 17 17 289 -1 unnamed_device 23.5 MiB 1.03 896 7770 1848 5501 421 63.1 MiB 0.09 0.00 3.62655 -110.965 -3.62655 3.62655 0.33 0.000583477 0.000543265 0.0267762 0.0249136 -1 -1 -1 -1 26 2417 31 6.89349e+06 295971 503264. 1741.40 0.65 0.104233 0.0908852 24322 120374 -1 1997 26 1435 2066 169243 52516 2.81636 2.81636 -107.029 -2.81636 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0282252 0.024338 105 30 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_034.v common 4.52 vpr 63.24 MiB -1 -1 0.24 18424 1 0.03 -1 -1 30452 -1 -1 24 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 29 32 291 250 1 185 85 17 17 289 -1 unnamed_device 23.9 MiB 1.72 987 11989 3361 6675 1953 63.2 MiB 0.11 0.00 3.73533 -108.087 -3.73533 3.73533 0.34 0.000596376 0.000554792 0.0403117 0.0374762 -1 -1 -1 -1 26 2360 26 6.89349e+06 338252 503264. 1741.40 0.89 0.122772 0.107939 24322 120374 -1 2030 21 1210 1703 126678 30193 2.95146 2.95146 -109.609 -2.95146 0 0 618332. 2139.56 0.02 0.04 0.07 -1 -1 0.02 0.0132468 0.0116048 117 54 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_035.v common 5.23 vpr 63.10 MiB -1 -1 0.24 18260 1 0.03 -1 -1 30420 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64616 32 32 367 282 1 224 92 17 17 289 -1 unnamed_device 23.9 MiB 1.16 1265 10649 3041 6726 882 63.1 MiB 0.13 0.00 4.57545 -131.234 -4.57545 4.57545 0.33 0.000735448 0.000683785 0.0403333 0.0374629 -1 -1 -1 -1 28 3232 44 6.89349e+06 394628 531479. 1839.03 2.16 0.272148 0.23506 24610 126494 -1 2714 22 1537 2644 200999 47427 3.7547 3.7547 -129.761 -3.7547 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0172363 0.0151812 155 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_036.v common 4.75 vpr 63.11 MiB -1 -1 0.25 18380 1 0.03 -1 -1 30400 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64628 32 32 391 311 1 250 93 17 17 289 -1 unnamed_device 24.1 MiB 1.73 1433 15423 4226 9063 2134 63.1 MiB 0.18 0.00 4.56723 -154.163 -4.56723 4.56723 0.33 0.000759097 0.000705105 0.0586858 0.0546043 -1 -1 -1 -1 30 3141 34 6.89349e+06 408721 556674. 1926.21 0.84 0.164331 0.145039 25186 138497 -1 2546 22 2111 2906 187308 44776 3.63025 3.63025 -138.661 -3.63025 0 0 706193. 2443.58 0.03 0.09 0.11 -1 -1 0.03 0.0322373 0.0280504 162 65 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_037.v common 3.71 vpr 63.12 MiB -1 -1 0.24 18508 1 0.03 -1 -1 30236 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 31 32 279 237 1 166 81 17 17 289 -1 unnamed_device 23.6 MiB 1.01 863 12331 3145 7318 1868 63.1 MiB 0.12 0.00 4.00748 -119.789 -4.00748 4.00748 0.34 0.000603096 0.000561509 0.0437123 0.0406478 -1 -1 -1 -1 32 1949 21 6.89349e+06 253689 586450. 2029.24 0.58 0.11396 0.100554 25474 144626 -1 1645 19 873 1326 100623 24502 3.22455 3.22455 -109.63 -3.22455 0 0 744469. 2576.02 0.03 0.06 0.14 -1 -1 0.03 0.0229871 0.0200214 106 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_038.v common 4.53 vpr 63.14 MiB -1 -1 0.28 18500 1 0.03 -1 -1 30392 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 31 32 370 297 1 235 91 17 17 289 -1 unnamed_device 24.2 MiB 1.85 1334 16615 5524 9183 1908 63.1 MiB 0.18 0.00 4.35803 -138.286 -4.35803 4.35803 0.33 0.000727677 0.000676594 0.0611783 0.0568038 -1 -1 -1 -1 32 3139 23 6.89349e+06 394628 586450. 2029.24 0.64 0.148113 0.131113 25474 144626 -1 2593 17 1393 2113 153401 34955 3.66925 3.66925 -132.64 -3.66925 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0137367 0.0121843 154 61 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_039.v common 4.31 vpr 63.20 MiB -1 -1 0.26 18304 1 0.03 -1 -1 30332 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64720 31 32 377 302 1 241 91 17 17 289 -1 unnamed_device 24.1 MiB 1.60 1343 10699 2924 7083 692 63.2 MiB 0.07 0.00 5.62498 -166.87 -5.62498 5.62498 0.26 0.000327803 0.000302305 0.0189607 0.0174255 -1 -1 -1 -1 34 3178 21 6.89349e+06 394628 618332. 2139.56 0.88 0.100962 0.0873837 25762 151098 -1 2774 21 2014 3034 249717 56521 4.87549 4.87549 -160.742 -4.87549 0 0 787024. 2723.27 0.03 0.09 0.12 -1 -1 0.03 0.0301309 0.0261619 159 64 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_040.v common 4.99 vpr 63.14 MiB -1 -1 0.26 18304 1 0.03 -1 -1 30548 -1 -1 30 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 31 32 383 305 1 240 93 17 17 289 -1 unnamed_device 24.1 MiB 2.16 1180 16893 5958 8269 2666 63.1 MiB 0.18 0.00 5.57018 -172.63 -5.57018 5.57018 0.33 0.000739064 0.000686488 0.0616354 0.0572376 -1 -1 -1 -1 32 2992 25 6.89349e+06 422815 586450. 2029.24 0.67 0.153088 0.135511 25474 144626 -1 2271 22 1773 2638 157146 39758 4.86068 4.86068 -161.708 -4.86068 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0314788 0.0273736 163 64 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_041.v common 4.16 vpr 63.20 MiB -1 -1 0.26 18440 1 0.03 -1 -1 30376 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64720 31 32 352 285 1 223 90 17 17 289 -1 unnamed_device 24.0 MiB 1.25 1293 12150 3370 7532 1248 63.2 MiB 0.14 0.00 4.06478 -128.581 -4.06478 4.06478 0.34 0.000699316 0.000650208 0.0445193 0.0413753 -1 -1 -1 -1 30 2866 44 6.89349e+06 380534 556674. 1926.21 0.76 0.154584 0.135395 25186 138497 -1 2238 19 1372 2024 123195 28998 2.85031 2.85031 -111.874 -2.85031 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.026008 0.0226341 146 55 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_042.v common 3.87 vpr 63.28 MiB -1 -1 0.15 18076 1 0.03 -1 -1 30476 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 32 32 291 242 1 188 86 17 17 289 -1 unnamed_device 23.7 MiB 1.37 1096 9347 2440 6352 555 63.3 MiB 0.10 0.00 4.52484 -122.151 -4.52484 4.52484 0.34 0.000629764 0.000586024 0.0325575 0.0302635 -1 -1 -1 -1 26 2789 28 6.89349e+06 310065 503264. 1741.40 0.59 0.119867 0.104736 24322 120374 -1 2323 23 1271 1766 129816 31818 4.20376 4.20376 -129.093 -4.20376 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0269782 0.0233675 114 27 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_043.v common 5.49 vpr 63.48 MiB -1 -1 0.28 18520 1 0.03 -1 -1 30440 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65000 32 32 457 356 1 296 99 17 17 289 -1 unnamed_device 24.4 MiB 2.27 1650 16971 5334 10464 1173 63.5 MiB 0.21 0.00 5.33145 -171.907 -5.33145 5.33145 0.33 0.000866659 0.000806268 0.0674064 0.0626669 -1 -1 -1 -1 30 4216 33 6.89349e+06 493284 556674. 1926.21 0.96 0.188556 0.166125 25186 138497 -1 3338 24 2618 3983 274830 62997 4.22004 4.22004 -160.102 -4.22004 0 0 706193. 2443.58 0.03 0.11 0.11 -1 -1 0.03 0.038707 0.0334571 198 87 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_044.v common 3.45 vpr 63.15 MiB -1 -1 0.22 18152 1 0.03 -1 -1 30152 -1 -1 19 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64668 31 32 261 225 1 171 82 17 17 289 -1 unnamed_device 23.6 MiB 0.92 942 13966 3994 8618 1354 63.2 MiB 0.13 0.00 3.7719 -110.938 -3.7719 3.7719 0.34 0.00056775 0.000527039 0.0461714 0.0428804 -1 -1 -1 -1 32 2071 21 6.89349e+06 267783 586450. 2029.24 0.55 0.112744 0.0995375 25474 144626 -1 1805 18 1021 1430 85739 21011 2.97291 2.97291 -107.69 -2.97291 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0206187 0.0179139 101 28 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_045.v common 4.28 vpr 63.04 MiB -1 -1 0.25 18404 1 0.03 -1 -1 30324 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64556 31 32 337 267 1 207 88 17 17 289 -1 unnamed_device 23.9 MiB 1.40 1128 5158 1029 3935 194 63.0 MiB 0.07 0.00 4.79572 -142.454 -4.79572 4.79572 0.33 0.000682908 0.000635379 0.020152 0.018729 -1 -1 -1 -1 30 3093 24 6.89349e+06 352346 556674. 1926.21 0.79 0.10569 0.0919385 25186 138497 -1 2432 21 1436 2183 149532 35823 3.8035 3.8035 -133.873 -3.8035 0 0 706193. 2443.58 0.03 0.10 0.11 -1 -1 0.03 0.0356862 0.030933 139 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_046.v common 4.46 vpr 62.96 MiB -1 -1 0.24 18576 1 0.03 -1 -1 30268 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64468 32 32 349 284 1 222 90 17 17 289 -1 unnamed_device 23.8 MiB 1.47 1260 16572 5549 8089 2934 63.0 MiB 0.18 0.00 4.31681 -131.797 -4.31681 4.31681 0.33 0.000692411 0.000641627 0.0595607 0.0553191 -1 -1 -1 -1 30 3482 26 6.89349e+06 366440 556674. 1926.21 0.88 0.149362 0.132119 25186 138497 -1 2487 19 1298 2160 137638 32282 3.5623 3.5623 -128.005 -3.5623 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0258789 0.0225371 144 53 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_047.v common 3.55 vpr 63.14 MiB -1 -1 0.22 17968 1 0.03 -1 -1 30124 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64660 32 32 291 230 1 175 91 17 17 289 -1 unnamed_device 23.5 MiB 0.86 1024 12535 4004 6635 1896 63.1 MiB 0.12 0.00 4.24939 -127.739 -4.24939 4.24939 0.34 0.000626882 0.000582042 0.0404428 0.0375685 -1 -1 -1 -1 30 2604 24 6.89349e+06 380534 556674. 1926.21 0.80 0.121426 0.106891 25186 138497 -1 2002 21 1172 2290 138411 33291 3.7797 3.7797 -124.432 -3.7797 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.0133723 0.0117291 123 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_048.v common 4.77 vpr 63.05 MiB -1 -1 0.28 18268 1 0.03 -1 -1 30436 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64568 32 32 353 287 1 220 90 17 17 289 -1 unnamed_device 23.9 MiB 1.62 1205 14160 4623 7104 2433 63.1 MiB 0.15 0.00 4.53365 -132.672 -4.53365 4.53365 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64464 32 32 340 270 1 204 89 17 17 289 -1 unnamed_device 23.8 MiB 0.94 1210 12365 3326 7764 1275 63.0 MiB 0.08 0.00 5.21531 -154.715 -5.21531 5.21531 0.26 0.000308828 0.000284704 0.0209834 0.0193316 -1 -1 -1 -1 30 2780 24 6.89349e+06 352346 556674. 1926.21 0.47 0.0641112 0.0562922 25186 138497 -1 2260 20 1189 2085 141591 32513 3.706 3.706 -133.226 -3.706 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0265655 0.0231263 137 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_082.v common 4.42 vpr 63.12 MiB -1 -1 0.25 18396 1 0.03 -1 -1 30196 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64640 31 32 340 275 1 211 90 17 17 289 -1 unnamed_device 23.9 MiB 1.73 1088 9336 2201 6577 558 63.1 MiB 0.11 0.00 5.04444 -145.956 -5.04444 5.04444 0.33 0.000682831 0.000634779 0.0339186 0.0315045 -1 -1 -1 -1 30 3021 26 6.89349e+06 380534 556674. 1926.21 0.72 0.119856 0.104908 25186 138497 -1 2171 23 1498 2362 145453 36505 4.09269 4.09269 -138.021 -4.09269 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0293748 0.0254617 142 47 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_083.v common 4.58 vpr 63.17 MiB -1 -1 0.14 18380 1 0.03 -1 -1 30344 -1 -1 31 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64688 30 32 377 310 1 239 93 17 17 289 -1 unnamed_device 24.1 MiB 2.01 1323 12063 3354 7850 859 63.2 MiB 0.14 0.00 4.83716 -144.714 -4.83716 4.83716 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/home/elgamma8/research/release/vtr-verilog-to-routing 64480 32 32 356 289 1 224 90 17 17 289 -1 unnamed_device 23.8 MiB 1.71 1387 15768 4665 9408 1695 63.0 MiB 0.16 0.00 4.93824 -150.865 -4.93824 4.93824 0.33 0.000707307 0.00065752 0.0579457 0.0538599 -1 -1 -1 -1 32 2960 23 6.89349e+06 366440 586450. 2029.24 0.61 0.142278 0.12601 25474 144626 -1 2441 19 1502 2031 146713 34429 4.31335 4.31335 -145.674 -4.31335 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0149205 0.0132196 146 56 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_093.v common 3.84 vpr 62.96 MiB -1 -1 0.24 18176 1 0.03 -1 -1 30164 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64468 32 32 349 260 1 204 100 17 17 289 -1 unnamed_device 23.8 MiB 0.63 1297 14020 4001 8993 1026 63.0 MiB 0.16 0.00 5.06861 -145.864 -5.06861 5.06861 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30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 32 32 421 327 1 271 94 17 17 289 -1 unnamed_device 24.2 MiB 1.97 1509 10957 2826 6796 1335 63.3 MiB 0.14 0.00 4.63892 -149.381 -4.63892 4.63892 0.33 0.00080454 0.000748076 0.043944 0.0407989 -1 -1 -1 -1 28 4136 42 6.89349e+06 422815 531479. 1839.03 1.38 0.170393 0.149095 24610 126494 -1 3075 22 2130 3307 228365 66158 4.43289 4.43289 -149.976 -4.43289 0 0 648988. 2245.63 0.03 0.10 0.11 -1 -1 0.03 0.0340225 0.0295636 180 65 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_097.v common 4.62 vpr 63.55 MiB -1 -1 0.15 18416 1 0.03 -1 -1 30312 -1 -1 26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65080 31 32 365 296 1 233 89 17 17 289 -1 unnamed_device 23.8 MiB 1.82 1244 11771 3259 7075 1437 63.6 MiB 0.13 0.00 5.7998 -165.192 -5.7998 5.7998 0.33 0.000716053 0.000665573 0.0448739 0.0416641 -1 -1 -1 -1 32 2788 40 6.89349e+06 366440 586450. 2029.24 0.77 0.149219 0.130667 25474 144626 -1 2412 21 1884 2692 188955 47019 4.67615 4.67615 -156.175 -4.67615 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0298131 0.0259191 151 64 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_098.v common 4.36 vpr 63.19 MiB -1 -1 0.24 18252 1 0.03 -1 -1 30300 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64708 32 32 331 280 1 221 87 17 17 289 -1 unnamed_device 24.0 MiB 1.50 1210 16215 5301 8723 2191 63.2 MiB 0.16 0.00 4.58923 -148.326 -4.58923 4.58923 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0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.013763 0.0121788 131 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_100.v common 4.05 vpr 63.06 MiB -1 -1 0.26 18404 1 0.03 -1 -1 30484 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 31 32 373 294 1 231 91 17 17 289 -1 unnamed_device 23.8 MiB 1.46 1232 10291 2595 7126 570 63.1 MiB 0.13 0.00 4.53972 -131.904 -4.53972 4.53972 0.33 0.000731723 0.000679966 0.0398017 0.0369928 -1 -1 -1 -1 30 2836 17 6.89349e+06 394628 556674. 1926.21 0.57 0.120718 0.106209 25186 138497 -1 2405 21 1646 2522 144904 35098 3.7514 3.7514 -127.877 -3.7514 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0296711 0.0258196 158 50 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_101.v common 4.41 vpr 63.09 MiB -1 -1 0.25 18444 1 0.03 -1 -1 30376 -1 -1 26 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 30 32 325 268 1 210 88 17 17 289 -1 unnamed_device 23.9 MiB 1.46 1228 15493 4762 8305 2426 63.1 MiB 0.16 0.00 4.32549 -122.97 -4.32549 4.32549 0.33 0.000656747 0.000610369 0.0543623 0.0505311 -1 -1 -1 -1 32 2960 24 6.89349e+06 366440 586450. 2029.24 0.62 0.134116 0.118568 25474 144626 -1 2431 20 1284 2055 142826 33487 3.4732 3.4732 -117.819 -3.4732 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.025544 0.0221956 135 51 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_102.v common 4.78 vpr 63.11 MiB -1 -1 0.23 18348 1 0.03 -1 -1 30356 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64620 32 32 350 275 1 215 88 17 17 289 -1 unnamed_device 23.9 MiB 1.99 1263 13738 4130 7532 2076 63.1 MiB 0.15 0.00 4.94548 -156.272 -4.94548 4.94548 0.34 0.000704088 0.000654957 0.0519574 0.0483078 -1 -1 -1 -1 30 3289 25 6.89349e+06 338252 556674. 1926.21 0.72 0.141395 0.124798 25186 138497 -1 2682 20 1660 2612 206101 48392 4.08826 4.08826 -148.158 -4.08826 0 0 706193. 2443.58 0.03 0.08 0.11 -1 -1 0.03 0.027773 0.0241643 143 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_103.v common 4.90 vpr 63.29 MiB -1 -1 0.26 18364 1 0.03 -1 -1 29992 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64812 32 32 386 307 1 246 93 17 17 289 -1 unnamed_device 24.2 MiB 2.08 1385 10173 2853 6391 929 63.3 MiB 0.13 0.00 4.14004 -138.199 -4.14004 4.14004 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26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64536 31 32 326 261 1 204 89 17 17 289 -1 unnamed_device 23.9 MiB 1.17 1108 10583 2739 6769 1075 63.0 MiB 0.12 0.00 5.02183 -139.303 -5.02183 5.02183 0.33 0.000666098 0.000619577 0.0377341 0.0350695 -1 -1 -1 -1 36 2340 22 6.89349e+06 366440 648988. 2245.63 1.15 0.169204 0.14718 26050 158493 -1 2066 18 1163 1883 137081 32533 3.75856 3.75856 -127.625 -3.75856 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0242178 0.0211161 134 33 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_107.v common 4.07 vpr 63.09 MiB -1 -1 0.25 18156 1 0.03 -1 -1 30312 -1 -1 20 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64600 29 32 262 224 1 168 81 17 17 289 -1 unnamed_device 23.5 MiB 1.30 845 8306 2095 5417 794 63.1 MiB 0.09 0.00 4.25195 -113.857 -4.25195 4.25195 0.33 0.000574 0.000535503 0.0287148 0.0267542 -1 -1 -1 -1 28 2177 33 6.89349e+06 281877 531479. 1839.03 0.68 0.104971 0.0914314 24610 126494 -1 1920 28 1357 1777 186903 65337 3.169 3.169 -109.113 -3.169 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0289744 0.0249371 104 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_108.v common 4.81 vpr 63.11 MiB -1 -1 0.23 18156 1 0.03 -1 -1 30064 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64620 32 32 278 238 1 182 84 17 17 289 -1 unnamed_device 23.5 MiB 1.41 1019 13809 4194 7374 2241 63.1 MiB 0.13 0.00 4.20123 -130.77 -4.20123 4.20123 0.34 0.000595178 0.00055434 0.0468899 0.0436464 -1 -1 -1 -1 28 2671 42 6.89349e+06 281877 531479. 1839.03 0.95 0.140562 0.123393 24610 126494 -1 2173 24 1552 2167 196263 44101 3.30321 3.30321 -128.538 -3.30321 0 0 648988. 2245.63 0.03 0.08 0.11 -1 -1 0.03 0.0270876 0.0233899 109 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_109.v common 4.58 vpr 63.64 MiB -1 -1 0.26 18424 1 0.03 -1 -1 30380 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65164 31 32 373 300 1 237 91 17 17 289 -1 unnamed_device 23.8 MiB 1.80 1293 14983 4153 9099 1731 63.6 MiB 0.17 0.00 4.61837 -148.41 -4.61837 4.61837 0.33 0.00072392 0.000673027 0.0559176 0.0519563 -1 -1 -1 -1 28 3195 26 6.89349e+06 394628 531479. 1839.03 0.65 0.14627 0.129198 24610 126494 -1 2553 20 1986 2698 186531 44431 3.81965 3.81965 -141.172 -3.81965 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0281923 0.0245186 155 64 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_110.v common 3.60 vpr 63.05 MiB -1 -1 0.23 18092 1 0.03 -1 -1 30472 -1 -1 19 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64568 31 32 265 230 1 175 82 17 17 289 -1 unnamed_device 23.5 MiB 1.02 883 8804 2413 5751 640 63.1 MiB 0.09 0.00 3.61555 -111.504 -3.61555 3.61555 0.33 0.00057191 0.000532928 0.0300125 0.0279299 -1 -1 -1 -1 30 2116 21 6.89349e+06 267783 556674. 1926.21 0.54 0.0967442 0.0847373 25186 138497 -1 1746 22 1000 1418 88147 21633 2.90311 2.90311 -110.877 -2.90311 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0237371 0.0205404 104 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_111.v common 4.24 vpr 63.06 MiB -1 -1 0.15 18416 1 0.03 -1 -1 30020 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 32 32 349 286 1 221 89 17 17 289 -1 unnamed_device 23.8 MiB 1.50 1245 11969 3140 7616 1213 63.1 MiB 0.13 0.00 4.39413 -130.035 -4.39413 4.39413 0.34 0.000697558 0.00064848 0.0442265 0.0410941 -1 -1 -1 -1 30 2800 29 6.89349e+06 352346 556674. 1926.21 0.70 0.136708 0.120083 25186 138497 -1 2259 17 1056 1557 104303 24463 3.1503 3.1503 -117.968 -3.1503 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0240403 0.021017 142 57 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_112.v common 5.19 vpr 63.09 MiB -1 -1 0.29 18380 1 0.03 -1 -1 30260 -1 -1 30 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 31 32 396 325 1 259 93 17 17 289 -1 unnamed_device 24.0 MiB 2.12 1311 17313 4833 10070 2410 63.1 MiB 0.19 0.00 4.94622 -159.495 -4.94622 4.94622 0.33 0.000741991 0.000685776 0.0638633 0.0592945 -1 -1 -1 -1 32 3396 38 6.89349e+06 422815 586450. 2029.24 0.81 0.172103 0.15195 25474 144626 -1 2671 23 1970 2785 193766 45890 4.04249 4.04249 -151.176 -4.04249 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0322965 0.0279992 166 91 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_113.v common 4.65 vpr 63.05 MiB -1 -1 0.25 18472 1 0.03 -1 -1 30280 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64560 32 32 303 262 1 200 85 17 17 289 -1 unnamed_device 23.9 MiB 1.42 1134 7153 1649 5156 348 63.0 MiB 0.09 0.00 3.69791 -119.314 -3.69791 3.69791 0.33 0.000617724 0.000574295 0.0263615 0.0244812 -1 -1 -1 -1 26 3014 50 6.89349e+06 295971 503264. 1741.40 0.74 0.12603 0.109223 24322 120374 -1 2497 19 1652 2257 182227 43841 3.70126 3.70126 -131.815 -3.70126 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0236811 0.0205417 121 57 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_114.v common 3.82 vpr 63.18 MiB -1 -1 0.22 18576 1 0.03 -1 -1 30256 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64700 32 32 290 244 1 176 83 17 17 289 -1 unnamed_device 23.6 MiB 1.05 898 9983 2681 6247 1055 63.2 MiB 0.12 0.00 4.17923 -126.577 -4.17923 4.17923 0.38 0.000618611 0.000576399 0.0436637 0.0406308 -1 -1 -1 -1 32 2248 27 6.89349e+06 267783 586450. 2029.24 0.63 0.121099 0.106383 25474 144626 -1 1913 21 1176 1778 129091 30495 3.09046 3.09046 -115.484 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-1 28 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64516 29 32 324 268 1 207 89 17 17 289 -1 unnamed_device 23.9 MiB 1.34 1163 13949 4509 7225 2215 63.0 MiB 0.14 0.00 4.06068 -113.604 -4.06068 4.06068 0.36 0.000648988 0.000603481 0.0483598 0.0449987 -1 -1 -1 -1 32 2498 22 6.89349e+06 394628 586450. 2029.24 0.57 0.125864 0.111182 25474 144626 -1 2113 18 1091 1529 102409 24986 3.1726 3.1726 -107.969 -3.1726 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0235466 0.0205043 136 55 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_117.v common 5.04 vpr 63.17 MiB -1 -1 0.26 18540 1 0.03 -1 -1 30420 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64684 32 32 393 312 1 243 90 17 17 289 -1 unnamed_device 24.1 MiB 2.00 1197 8532 1944 6080 508 63.2 MiB 0.11 0.00 5.6615 -176.256 -5.6615 5.6615 0.33 0.000765182 0.000711071 0.034673 0.0322116 -1 -1 -1 -1 32 3572 28 6.89349e+06 366440 586450. 2029.24 0.87 0.132281 0.11584 25474 144626 -1 2640 22 1876 2860 206960 49868 4.38809 4.38809 -163.546 -4.38809 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0314949 0.0273942 161 65 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_118.v common 3.73 vpr 63.07 MiB -1 -1 0.23 17908 1 0.03 -1 -1 30152 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64588 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 23.5 MiB 0.88 858 12156 3731 6704 1721 63.1 MiB 0.11 0.00 3.31865 -102.092 -3.31865 3.31865 0.33 0.000531063 0.000495106 0.0385232 0.0358846 -1 -1 -1 -1 30 1864 18 6.89349e+06 253689 556674. 1926.21 0.52 0.0984705 0.0870618 25186 138497 -1 1477 21 802 1292 78949 19537 2.35985 2.35985 -93.6869 -2.35985 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.0215092 0.0186059 93 4 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_119.v common 4.40 vpr 63.87 MiB -1 -1 0.25 18480 1 0.03 -1 -1 30404 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65400 32 32 412 334 1 269 94 17 17 289 -1 unnamed_device 24.2 MiB 1.70 1511 17773 5393 10213 2167 63.9 MiB 0.19 0.00 5.64972 -177.297 -5.64972 5.64972 0.33 0.000351025 0.000323302 0.0594056 0.0549061 -1 -1 -1 -1 32 3132 28 6.89349e+06 422815 586450. 2029.24 0.51 0.130668 0.115927 25474 144626 -1 2549 18 1654 2142 127890 31978 4.60024 4.60024 -163.543 -4.60024 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0277509 0.0242359 173 90 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_120.v common 4.89 vpr 63.25 MiB -1 -1 0.15 18432 1 0.03 -1 -1 30176 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 32 32 376 318 1 259 92 17 17 289 -1 unnamed_device 24.2 MiB 1.84 1293 9614 2367 6489 758 63.2 MiB 0.12 0.00 4.89568 -164.328 -4.89568 4.89568 0.33 0.000704531 0.000653159 0.0352242 0.0326131 -1 -1 -1 -1 32 3167 23 6.89349e+06 394628 586450. 2029.24 0.73 0.122092 0.106854 25474 144626 -1 2517 22 2283 2786 179066 44397 4.21384 4.21384 -161.857 -4.21384 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0296871 0.0257565 155 96 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_121.v common 4.27 vpr 63.02 MiB -1 -1 0.25 18248 1 0.03 -1 -1 30208 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64532 32 32 360 293 1 226 91 17 17 289 -1 unnamed_device 23.8 MiB 1.40 1307 13759 4403 8202 1154 63.0 MiB 0.17 0.00 4.10168 -130.557 -4.10168 4.10168 0.33 0.000711311 0.00066117 0.0570836 0.0530446 -1 -1 -1 -1 32 2791 48 6.89349e+06 380534 586450. 2029.24 0.71 0.169513 0.148957 25474 144626 -1 2228 17 1439 1975 125236 30124 2.97891 2.97891 -117.401 -2.97891 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0245511 0.0214454 147 60 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_122.v common 5.73 vpr 63.15 MiB -1 -1 0.14 18740 1 0.03 -1 -1 30328 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64668 32 32 396 299 1 240 92 17 17 289 -1 unnamed_device 24.1 MiB 2.03 1350 12098 3111 7804 1183 63.2 MiB 0.17 0.00 5.93815 -178.759 -5.93815 5.93815 0.34 0.000774961 0.000720753 0.0484735 0.0450489 -1 -1 -1 -1 30 3179 30 6.89349e+06 394628 556674. 1926.21 1.07 0.154751 0.136253 25186 138497 -1 2629 22 1591 2517 184543 45433 4.56655 4.56655 -159.834 -4.56655 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0173111 0.0152944 167 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_123.v common 3.42 vpr 63.09 MiB -1 -1 0.18 18056 1 0.03 -1 -1 30168 -1 -1 17 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 30 32 224 207 1 138 79 17 17 289 -1 unnamed_device 23.6 MiB 0.86 744 11064 2972 6586 1506 63.1 MiB 0.09 0.00 3.06986 -93.837 -3.06986 3.06986 0.33 0.00050022 0.000465468 0.0342512 0.0318795 -1 -1 -1 -1 32 1608 21 6.89349e+06 239595 586450. 2029.24 0.51 0.0930254 0.0819585 25474 144626 -1 1362 19 746 975 64274 15732 2.15637 2.15637 -86.663 -2.15637 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0186802 0.0161973 80 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 4.09 vpr 63.19 MiB -1 -1 0.24 18064 1 0.03 -1 -1 30332 -1 -1 23 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64708 30 32 286 239 1 176 85 17 17 289 -1 unnamed_device 23.6 MiB 1.17 970 14221 4684 7353 2184 63.2 MiB 0.13 0.00 4.47457 -139.461 -4.47457 4.47457 0.33 0.000598059 0.000556233 0.0476839 0.0443531 -1 -1 -1 -1 32 2088 19 6.89349e+06 324158 586450. 2029.24 0.57 0.116239 0.102831 25474 144626 -1 1798 19 1209 1755 123419 28254 3.20405 3.20405 -123.196 -3.20405 0 0 744469. 2576.02 0.04 0.06 0.14 -1 -1 0.04 0.0213811 0.0188746 120 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_125.v common 4.64 vpr 63.24 MiB -1 -1 0.14 18164 1 0.04 -1 -1 30036 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64756 32 32 296 247 1 187 89 17 17 289 -1 unnamed_device 23.9 MiB 1.81 1127 15137 4309 8906 1922 63.2 MiB 0.15 0.00 4.30299 -142.144 -4.30299 4.30299 0.33 0.000624179 0.000580082 0.0500647 0.0464926 -1 -1 -1 -1 32 2632 22 6.89349e+06 352346 586450. 2029.24 0.65 0.124241 0.109743 25474 144626 -1 2086 21 1194 2198 152487 35249 3.2979 3.2979 -129.639 -3.2979 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0252727 0.0218883 119 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_126.v common 3.81 vpr 63.04 MiB -1 -1 0.23 18076 1 0.03 -1 -1 30284 -1 -1 22 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64552 25 32 216 194 1 138 79 17 17 289 -1 unnamed_device 23.6 MiB 0.97 598 9881 3477 4123 2281 63.0 MiB 0.07 0.00 3.7089 -85.4656 -3.7089 3.7089 0.33 0.000478077 0.000444482 0.0293864 0.0272887 -1 -1 -1 -1 36 1448 42 6.89349e+06 310065 648988. 2245.63 1.04 0.136492 0.117908 26050 158493 -1 1138 18 657 975 59260 15977 2.93981 2.93981 -80.0624 -2.93981 0 0 828058. 2865.25 0.03 0.03 0.09 -1 -1 0.03 0.00980015 0.00865384 88 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 4.99 vpr 63.14 MiB -1 -1 0.15 18352 1 0.03 -1 -1 30352 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64660 32 32 376 307 1 242 90 17 17 289 -1 unnamed_device 24.1 MiB 2.30 1430 16170 4616 9563 1991 63.1 MiB 0.18 0.00 4.51899 -138.857 -4.51899 4.51899 0.33 0.000721273 0.000669662 0.0603201 0.0559474 -1 -1 -1 -1 32 3301 26 6.89349e+06 366440 586450. 2029.24 0.66 0.151815 0.134188 25474 144626 -1 2662 22 1825 2779 185735 42367 3.63286 3.63286 -129.152 -3.63286 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0164302 0.0144632 156 72 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_128.v common 5.19 vpr 63.29 MiB -1 -1 0.27 18404 1 0.03 -1 -1 30280 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64812 31 32 409 331 1 264 96 17 17 289 -1 unnamed_device 24.2 MiB 2.08 1431 11703 3152 7474 1077 63.3 MiB 0.14 0.00 4.84775 -156.008 -4.84775 4.84775 0.33 0.000772559 0.000718063 0.0435525 0.0403604 -1 -1 -1 -1 26 3450 37 6.89349e+06 465097 503264. 1741.40 0.87 0.155585 0.13616 24322 120374 -1 3021 21 2266 3099 239025 58139 4.43869 4.43869 -159.514 -4.43869 0 0 618332. 2139.56 0.03 0.09 0.10 -1 -1 0.03 0.0309079 0.0268354 175 90 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt index 14b02df4c6e..2aa73474bd1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 1864.14 vpr 957.58 MiB -1 -1 22.42 331380 27 13.20 -1 -1 142432 -1 -1 5694 641 0 0 success v8.0.0-10948-g76f6d280f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-44-generic x86_64 2024-08-02T13:50:03 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 980564 641 128 52026 52154 1 24058 6463 90 90 8100 clb auto 349.0 MiB 173.06 299893 8009738 3248634 4687011 74093 957.6 MiB 90.11 0.74 14.696 -38781.3 -14.696 14.696 78.67 0.0454146 0.0364574 6.41213 5.29191 66 440752 49 2.50222e+08 6.86455e+07 3.39805e+07 4195.12 1395.25 30.8998 26.3648 844532 8713078 -1 405206 17 108336 237098 17288222 3304110 13.1078 13.1078 -35765.6 -13.1078 0 0 4.24114e+07 5235.97 21.75 5.86 5.90 -1 -1 21.75 2.25901 2.0474 41833 14777 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 7.58 vpr 64.93 MiB -1 -1 0.84 29792 11 0.37 -1 -1 37192 -1 -1 47 54 0 0 success v8.0.0-10948-g76f6d280f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-44-generic x86_64 2024-08-02T13:50:03 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 66492 54 51 461 512 1 307 152 10 10 100 clb auto 26.7 MiB 0.17 2373 13922 2643 10142 1137 64.9 MiB 0.13 0.00 6.47024 -256.927 -6.47024 6.47024 0.33 0.00042886 0.000357536 0.0688225 0.0500239 54 5335 26 1.91864e+06 566585 279084. 2790.84 3.59 0.401441 0.318793 8874 64549 -1 4508 18 1941 9258 477400 107312 5.64329 5.64329 -238.143 -5.64329 0 0 343682. 3436.82 0.14 0.15 0.08 -1 -1 0.14 0.031029 0.0281091 351 351 -1 -1 -1 -1 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 496.86 vpr 906.63 MiB -1 -1 14.92 221280 1 3.28 -1 -1 149256 -1 -1 5125 641 0 0 success v8.0.0-10948-g76f6d280f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-44-generic x86_64 2024-08-02T13:50:03 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 928388 641 128 55563 47815 1 19235 5894 85 85 7225 clb auto 357.9 MiB 53.49 222909 7988444 3311697 4529990 146757 906.6 MiB 158.12 1.29 7.30188 -25593.7 -7.30188 7.30188 59.85 0.0346093 0.0287273 5.37677 4.40327 72 301784 47 2.22196e+08 6.43647e+07 3.24327e+07 4488.96 129.63 18.1686 15.4729 798746 8418143 -1 279076 27 66623 107145 10680598 2015876 5.67328 5.67328 -22253.4 -5.67328 0 0 4.04835e+07 5603.25 23.02 4.40 5.91 -1 -1 23.02 2.21605 1.94489 39986 2048 -1 -1 -1 -1 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 8.87 vpr 65.29 MiB -1 -1 0.79 28728 4 0.20 -1 -1 36472 -1 -1 41 54 0 0 success v8.0.0-10948-g76f6d280f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-44-generic x86_64 2024-08-02T13:50:03 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 66852 54 51 503 502 1 302 146 10 10 100 clb auto 27.3 MiB 2.56 2020 13202 2597 9296 1309 65.3 MiB 0.11 0.00 4.8288 -228.616 -4.8288 4.8288 0.37 0.000364269 0.000298402 0.0192023 0.0163646 54 4296 26 1.94278e+06 514878 279084. 2790.84 2.89 0.263514 0.235912 9066 64687 -1 3771 16 1579 6792 333407 78376 3.86988 3.86988 -205.334 -3.86988 0 0 343682. 3436.82 0.12 0.10 0.06 -1 -1 0.12 0.0312726 0.0289765 310 279 -1 -1 -1 -1 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 1397.07 vpr 910.60 MiB -1 -1 14.85 221360 1 3.28 -1 -1 149104 -1 -1 5176 641 0 0 success v8.0.0-10948-g76f6d280f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-44-generic x86_64 2024-08-02T13:50:03 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 932456 641 128 55563 47815 1 19575 5945 86 86 7396 clb auto 365.9 MiB 147.36 216449 8026913 3325604 4544181 157128 910.6 MiB 163.05 1.15 7.79808 -26173.5 -7.79808 7.79808 74.45 0.0333148 0.0256067 5.40235 4.3967 64 296093 41 2.34635e+08 6.56264e+07 3.02030e+07 4083.70 918.35 25.6673 21.649 786056 7778811 -1 273121 29 74523 108445 10800591 2118622 5.10857 5.10857 -22338.5 -5.10857 0 0 3.78329e+07 5115.32 18.90 4.37 4.97 -1 -1 18.90 2.1942 1.92409 40262 2048 -1 -1 -1 -1 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 7.20 vpr 65.30 MiB -1 -1 0.75 28880 4 0.23 -1 -1 36456 -1 -1 39 54 0 0 success v8.0.0-10948-g76f6d280f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-44-generic x86_64 2024-08-02T13:50:03 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 66864 54 51 503 502 1 307 144 10 10 100 clb auto 27.3 MiB 1.64 2063 8438 1287 6455 696 65.3 MiB 0.11 0.04 4.75191 -227.336 -4.75191 4.75191 0.39 0.0381416 0.0380647 0.0525767 0.050608 52 4645 30 1.94854e+06 494442 271502. 2715.02 1.67 0.208403 0.193565 8966 63017 -1 3899 50 1667 6383 746112 263022 3.83606 3.83606 -202.472 -3.83606 0 0 335037. 3350.37 0.15 0.37 0.15 -1 -1 0.15 0.120279 0.114452 305 279 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 346.85 vpr 1.15 GiB -1 -1 34.22 328308 27 15.05 -1 -1 138296 -1 -1 6514 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1202304 641 128 52026 52154 1 22211 7283 96 96 9216 clb auto 299.9 MiB 22.55 298865 9039475 3705368 5259409 74698 1174.1 MiB 99.58 0.80 15.6652 -38327.4 -15.6652 15.6652 30.26 0.094057 0.0773765 12.1503 10.1571 -1 -1 -1 -1 52 436843 31 2.87242e+08 7.85314e+07 3.22264e+07 3496.79 84.03 34.4054 28.6501 876764 7891077 -1 405234 17 92350 208771 15162225 3092956 14.5295 14.5295 -35310.2 -14.5295 0 0 3.95636e+07 4292.92 2.28 8.25 6.87 -1 -1 2.28 3.81485 3.27893 44137 14777 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 4.27 vpr 64.04 MiB -1 -1 0.87 26712 11 0.25 -1 -1 33516 -1 -1 51 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65580 54 51 461 512 1 281 156 11 11 121 clb auto 24.7 MiB 0.16 2356 11469 1919 8714 836 64.0 MiB 0.12 0.00 5.64506 -244.834 -5.64506 5.64506 0.13 0.00146196 0.00133342 0.0458162 0.0422569 -1 -1 -1 -1 48 5066 26 2.09946e+06 614805 317060. 2620.33 1.31 0.36651 0.319953 10252 71876 -1 4625 16 1697 8023 407060 95904 5.13857 5.13857 -230.591 -5.13857 0 0 382250. 3159.09 0.01 0.15 0.06 -1 -1 0.01 0.0499744 0.0448408 351 351 -1 -1 -1 -1 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 399.84 vpr 1.07 GiB -1 -1 21.81 218380 1 3.70 -1 -1 145176 -1 -1 5511 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1117152 641 128 55563 47815 1 19087 6280 89 89 7921 clb auto 300.2 MiB 18.05 230047 8461724 3459022 4875110 127592 1091.0 MiB 204.82 1.70 7.09259 -24894.9 -7.09259 7.09259 27.46 0.0722137 0.0620773 11.1205 9.22983 -1 -1 -1 -1 66 309563 40 2.46893e+08 6.92128e+07 3.31523e+07 4185.37 68.55 29.6499 24.5503 846610 8512169 -1 289933 30 70505 114345 10785585 2091912 4.98188 4.98188 -21717.1 -4.98188 0 0 4.13768e+07 5223.69 2.61 7.93 7.55 -1 -1 2.61 4.60052 3.86111 40340 2050 -1 -1 -1 -1 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 5.46 vpr 64.67 MiB -1 -1 0.88 25784 4 0.13 -1 -1 33088 -1 -1 47 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66224 54 51 503 502 1 293 152 10 10 100 clb auto 25.4 MiB 1.53 2207 8657 1268 6725 664 64.7 MiB 0.12 0.00 4.72142 -243.243 -4.72142 4.72142 0.10 0.00138683 0.00126889 0.0371909 0.0344533 -1 -1 -1 -1 44 4688 46 1.94278e+06 590226 231289. 2312.89 1.36 0.376354 0.326721 8470 54129 -1 4028 17 1662 7146 368098 92041 3.78868 3.78868 -208.146 -3.78868 0 0 291571. 2915.71 0.01 0.14 0.05 -1 -1 0.01 0.0559049 0.0498459 310 281 -1 -1 -1 -1 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 415.20 vpr 1.04 GiB -1 -1 21.75 218308 1 4.05 -1 -1 145180 -1 -1 5620 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1088640 641 128 55563 47815 1 19638 6389 89 89 7921 clb auto 308.1 MiB 52.99 226704 9072863 3788850 5116203 167810 1063.1 MiB 189.74 1.45 7.32093 -25503.3 -7.32093 7.32093 27.00 0.0695794 0.0596563 11.1854 9.32085 -1 -1 -1 -1 62 301435 41 2.47551e+08 7.12563e+07 3.13221e+07 3954.32 64.63 30.1669 25.0298 822850 7925305 -1 280695 33 74632 110486 9460418 1906659 4.74051 4.74051 -21753 -4.74051 0 0 3.86383e+07 4877.96 2.36 8.35 6.62 -1 -1 2.36 5.11529 4.30965 40780 2050 -1 -1 -1 -1 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 5.14 vpr 64.61 MiB -1 -1 0.49 25988 4 0.16 -1 -1 33144 -1 -1 50 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66164 54 51 503 502 1 302 155 11 11 121 clb auto 25.5 MiB 0.55 2264 11803 2091 8793 919 64.6 MiB 0.15 0.01 4.6074 -231.734 -4.6074 4.6074 0.13 0.00143538 0.00131584 0.0463156 0.0428406 -1 -1 -1 -1 46 4761 36 2.13871e+06 633900 304223. 2514.24 1.58 0.37716 0.328993 10384 69934 -1 4032 15 1433 6356 300467 73316 3.80829 3.80829 -202.73 -3.80829 0 0 371547. 3070.64 0.01 0.12 0.06 -1 -1 0.01 0.0507242 0.0453634 307 281 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt index 36a72a857e2..e0e23492818 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt @@ -1,11 +1,11 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_2ripple_N8_22nm.xml Md5Core.v common 967.55 vpr 763.48 MiB -1 -1 21.42 218260 1 3.55 -1 -1 145252 -1 -1 2765 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 781804 641 128 55563 47815 1 18442 3534 63 63 3969 clb auto 281.1 MiB 538.53 193346 3958863 1550116 2317083 91664 724.9 MiB 91.43 0.78 7.15591 -24783.9 -7.15591 7.15591 35.35 0.069551 0.0596698 11.0083 9.1981 -1 -1 -1 -1 100 265108 28 1.26034e+08 4.00259e+07 2.46425e+07 6208.74 216.16 44.9729 37.3415 555724 6871176 -1 241564 19 87044 109997 12783883 2167446 5.78182 5.78182 -22734.5 -5.78182 0 0 3.14324e+07 7919.47 11.63 6.19 5.58 -1 -1 11.63 3.3327 2.85451 20869 2050 -1 -1 -1 -1 - k6_frac_2ripple_N8_22nm.xml cordic.v common 8.95 vpr 64.59 MiB -1 -1 0.89 26192 4 0.16 -1 -1 33384 -1 -1 31 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66140 54 51 503 502 1 316 136 9 9 81 clb auto 25.8 MiB 3.67 1981 10606 1997 7706 903 64.6 MiB 0.14 0.01 4.17161 -228.336 -4.17161 4.17161 0.15 0.00186072 0.00171427 0.0514286 0.0475525 -1 -1 -1 -1 64 3792 30 1.45065e+06 448746 257695. 3181.41 2.54 0.574843 0.497531 8184 62525 -1 3344 18 1920 7095 335845 82840 3.72075 3.72075 -206.153 -3.72075 0 0 325495. 4018.46 0.07 0.13 0.06 -1 -1 0.07 0.0566057 0.0503365 223 281 -1 -1 -1 -1 - k6_frac_2uripple_N8_22nm.xml Md5Core.v common 1559.25 vpr 722.84 MiB -1 -1 21.49 218496 1 3.59 -1 -1 145220 -1 -1 2755 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 740192 641 128 55563 47815 1 18420 3524 63 63 3969 clb auto 275.9 MiB 401.16 189162 3756364 1484461 2184211 87692 722.8 MiB 82.41 0.75 6.93106 -24149.1 -6.93106 6.93106 33.22 0.0717932 0.0614288 10.2573 8.56904 -1 -1 -1 -1 96 272845 49 1.26708e+08 4.05424e+07 2.39085e+07 6023.80 957.73 60.3389 49.6676 543820 6559920 -1 240871 21 88185 112391 12448748 2170100 5.42465 5.42465 -22151.3 -5.42465 0 0 2.98904e+07 7530.95 11.16 6.44 5.45 -1 -1 11.16 3.58618 3.05396 20824 2050 -1 -1 -1 -1 - k6_frac_2uripple_N8_22nm.xml cordic.v common 4.56 vpr 64.47 MiB -1 -1 0.86 25908 4 0.16 -1 -1 33380 -1 -1 31 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66020 54 51 503 502 1 317 136 9 9 81 clb auto 25.8 MiB 0.24 1985 6767 1049 5344 374 64.5 MiB 0.10 0.00 4.17356 -220.898 -4.17356 4.17356 0.15 0.00138081 0.00127221 0.0330425 0.0306558 -1 -1 -1 -1 60 3856 40 1.45905e+06 456186 242836. 2997.97 1.76 0.429337 0.371533 7944 58396 -1 3350 17 1679 5954 301000 77818 3.8968 3.8968 -205.243 -3.8968 0 0 304930. 3764.57 0.07 0.12 0.06 -1 -1 0.07 0.0544767 0.0485746 223 281 -1 -1 -1 -1 - k6_frac_N8_22nm.xml Md5Core.v common 1120.51 vpr 806.71 MiB -1 -1 35.59 328120 27 14.77 -1 -1 138400 -1 -1 3317 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 826068 641 128 52026 52154 1 23512 4086 69 69 4761 clb auto 272.8 MiB 754.36 261133 4150890 1586658 2510234 53998 806.7 MiB 66.92 0.57 15.1822 -39318.8 -15.1822 15.1822 40.15 0.0882437 0.0769439 12.042 10.1836 -1 -1 -1 -1 86 398717 44 1.50071e+08 4.46866e+07 2.62257e+07 5508.44 135.32 40.4871 34.0228 609466 7129297 -1 363314 18 111266 235135 19285517 3561010 13.209 13.209 -36299.7 -13.209 0 0 3.28825e+07 6906.63 13.30 9.39 5.66 -1 -1 13.30 4.36645 3.79962 24398 14777 -1 -1 -1 -1 - k6_frac_N8_22nm.xml cordic.v common 5.30 vpr 64.01 MiB -1 -1 0.90 26384 11 0.25 -1 -1 33576 -1 -1 32 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65548 54 51 461 512 1 320 137 9 9 81 clb auto 24.8 MiB 0.23 2288 7197 1051 5690 456 64.0 MiB 0.10 0.00 6.24973 -250.56 -6.24973 6.24973 0.15 0.00144607 0.00132918 0.0370165 0.0342281 -1 -1 -1 -1 68 4737 28 1.41552e+06 431104 273575. 3377.47 2.36 0.459262 0.397505 8204 65576 -1 4227 16 2032 7777 430507 103502 5.511 5.511 -231.556 -5.511 0 0 341260. 4213.08 0.07 0.09 0.04 -1 -1 0.07 0.0317702 0.0289934 248 351 -1 -1 -1 -1 - k6_frac_ripple_N8_22nm.xml Md5Core.v common 1137.63 vpr 796.55 MiB -1 -1 21.77 218484 1 3.71 -1 -1 145332 -1 -1 3347 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 815668 641 128 55563 47815 1 19485 4116 69 69 4761 clb auto 265.0 MiB 674.41 209187 4719112 1762947 2769356 186809 796.6 MiB 133.07 1.12 7.50454 -24350.9 -7.50454 7.50454 41.02 0.0732288 0.0593247 10.5586 8.73373 -1 -1 -1 -1 78 280465 38 1.51752e+08 4.6769e+07 2.40314e+07 5047.55 201.27 45.7702 37.9151 599066 6522637 -1 262949 17 86466 116965 11441653 2162489 4.92975 4.92975 -21271.4 -4.92975 0 0 3.01399e+07 6330.58 12.77 5.93 5.15 -1 -1 12.77 3.01721 2.57504 25690 2050 -1 -1 -1 -1 - k6_frac_ripple_N8_22nm.xml cordic.v common 6.89 vpr 64.07 MiB -1 -1 0.89 25656 4 0.16 -1 -1 33436 -1 -1 31 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65612 54 51 503 502 1 304 136 9 9 81 clb auto 25.2 MiB 2.05 1922 8163 1239 6107 817 64.1 MiB 0.12 0.01 4.46634 -227.611 -4.46634 4.46634 0.15 0.00138637 0.00127855 0.0380722 0.0352824 -1 -1 -1 -1 58 4010 35 1.43308e+06 433189 237595. 2933.27 2.17 0.473652 0.409252 7864 57025 -1 3504 19 1914 6815 355293 91574 4.00986 4.00986 -203.926 -4.00986 0 0 298762. 3688.42 0.06 0.14 0.06 -1 -1 0.06 0.0573607 0.0506837 231 281 -1 -1 -1 -1 - k6_frac_uripple_N8_22nm.xml Md5Core.v common 725.64 vpr 847.35 MiB -1 -1 21.61 218272 1 3.62 -1 -1 145224 -1 -1 3391 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 867688 641 128 55563 47815 1 19453 4160 70 70 4900 clb auto 257.6 MiB 242.61 229476 4786509 1811673 2839137 135699 847.4 MiB 144.98 1.15 8.45033 -26255.9 -8.45033 8.45033 44.55 0.0706407 0.0605663 9.85709 8.24084 -1 -1 -1 -1 74 309564 47 1.56988e+08 4.77907e+07 2.37944e+07 4855.99 205.74 40.3572 33.4092 603630 6360748 -1 281191 24 82458 102666 12068393 2210419 5.62486 5.62486 -22699.9 -5.62486 0 0 2.96071e+07 6042.26 11.42 6.73 5.01 -1 -1 11.42 3.76274 3.16053 25717 2050 -1 -1 -1 -1 - k6_frac_uripple_N8_22nm.xml cordic.v common 5.09 vpr 64.27 MiB -1 -1 0.90 25612 4 0.16 -1 -1 33360 -1 -1 33 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65812 54 51 503 502 1 307 138 9 9 81 clb auto 25.3 MiB 0.70 2035 12242 2410 8614 1218 64.3 MiB 0.15 0.00 4.64981 -235.444 -4.64981 4.64981 0.15 0.00138199 0.00127842 0.0546169 0.0504723 -1 -1 -1 -1 54 4324 35 1.43728e+06 465097 226270. 2793.45 1.66 0.427278 0.370182 7624 52756 -1 3604 19 1920 6934 318277 82324 3.81736 3.81736 -208.354 -3.81736 0 0 280165. 3458.82 0.06 0.13 0.05 -1 -1 0.06 0.0571091 0.0505347 247 281 -1 -1 -1 -1 + k6_frac_2ripple_N8_22nm.xml Md5Core.v common 541.33 vpr 770.48 MiB -1 -1 21.57 219052 1 3.94 -1 -1 145160 -1 -1 2904 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 788976 641 128 55563 47815 1 17837 3673 65 65 4225 clb auto 278.4 MiB 280.64 186842 4139415 1628153 2426823 84439 770.5 MiB 80.11 0.65 6.85172 -24425.5 -6.85172 6.85172 17.37 0.0707807 0.0606116 10.8556 9.00171 -1 -1 -1 -1 86 266896 42 1.34217e+08 4.20381e+07 2.31978e+07 5490.61 95.85 37.0767 30.5473 551762 6310377 -1 239670 19 85960 107325 12022295 2121435 5.37037 5.37037 -22498.9 -5.37037 0 0 2.90884e+07 6884.83 1.53 5.92 5.28 -1 -1 1.53 3.24584 2.77988 21038 2050 -1 -1 -1 -1 + k6_frac_2ripple_N8_22nm.xml cordic.v common 7.58 vpr 65.10 MiB -1 -1 0.88 26100 4 0.16 -1 -1 33024 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66664 54 51 503 502 1 316 138 9 9 81 clb auto 26.1 MiB 3.78 1956 11174 2060 8307 807 65.1 MiB 0.13 0.00 4.40854 -233.833 -4.40854 4.40854 0.09 0.00139097 0.00128641 0.0504025 0.0467374 -1 -1 -1 -1 56 4041 27 1.45065e+06 477698 231774. 2861.41 1.17 0.353028 0.308187 7704 54090 -1 3517 18 1771 6187 313268 82102 4.02896 4.02896 -216.237 -4.02896 0 0 286113. 3532.26 0.01 0.13 0.05 -1 -1 0.01 0.0573414 0.0511544 225 281 -1 -1 -1 -1 + k6_frac_2uripple_N8_22nm.xml Md5Core.v common 445.49 vpr 768.55 MiB -1 -1 21.93 218372 1 4.17 -1 -1 145216 -1 -1 2904 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 787000 641 128 55563 47815 1 17906 3673 65 65 4225 clb auto 273.5 MiB 187.96 185308 3941126 1565098 2300167 75861 768.6 MiB 89.53 0.80 6.8947 -23916.3 -6.8947 6.8947 17.72 0.0715102 0.0611769 10.6329 8.87437 -1 -1 -1 -1 86 262207 37 1.34928e+08 4.2735e+07 2.31978e+07 5490.61 81.66 34.9922 28.9773 551762 6310377 -1 236506 17 80887 101963 10950479 1939027 5.59715 5.59715 -21989.7 -5.59715 0 0 2.90884e+07 6884.83 1.64 5.62 5.31 -1 -1 1.64 3.04009 2.59505 20989 2050 -1 -1 -1 -1 + k6_frac_2uripple_N8_22nm.xml cordic.v common 5.96 vpr 64.87 MiB -1 -1 0.87 26208 4 0.16 -1 -1 33076 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66424 54 51 503 502 1 318 138 9 9 81 clb auto 25.9 MiB 0.40 1964 10462 1843 7559 1060 64.9 MiB 0.13 0.00 4.28518 -225.617 -4.28518 4.28518 0.09 0.00139646 0.00129195 0.0476616 0.0441834 -1 -1 -1 -1 56 4128 31 1.45905e+06 485618 231774. 2861.41 2.57 0.547183 0.474234 7704 54090 -1 3583 18 1731 6262 331465 85566 3.8968 3.8968 -212.026 -3.8968 0 0 286113. 3532.26 0.01 0.14 0.05 -1 -1 0.01 0.058103 0.0518196 225 281 -1 -1 -1 -1 + k6_frac_N8_22nm.xml Md5Core.v common 523.72 vpr 809.32 MiB -1 -1 35.88 328152 27 14.52 -1 -1 138636 -1 -1 3446 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 828744 641 128 52026 52154 1 22420 4215 70 70 4900 clb auto 269.8 MiB 211.66 265423 4326406 1648229 2614689 63488 809.3 MiB 79.80 0.65 14.952 -39387.3 -14.952 14.952 20.28 0.0925834 0.0810563 12.6496 10.7217 -1 -1 -1 -1 84 394620 43 1.54829e+08 4.64245e+07 2.64571e+07 5399.40 108.95 44.8309 37.5465 624050 7235563 -1 356794 20 108067 230531 16879775 3154299 13.0725 13.0725 -36269.1 -13.0725 0 0 3.34846e+07 6833.59 1.94 9.36 5.72 -1 -1 1.94 4.65498 4.01829 24663 14777 -1 -1 -1 -1 + k6_frac_N8_22nm.xml cordic.v common 4.95 vpr 64.28 MiB -1 -1 0.95 26424 11 0.25 -1 -1 33660 -1 -1 34 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65824 54 51 461 512 1 317 139 9 9 81 clb auto 25.0 MiB 0.23 2204 9473 1828 7093 552 64.3 MiB 0.12 0.00 6.42199 -256.014 -6.42199 6.42199 0.09 0.00144714 0.00133734 0.0443724 0.0410787 -1 -1 -1 -1 62 4693 48 1.41552e+06 458048 249781. 3083.72 1.55 0.41392 0.360399 7884 59488 -1 3923 19 2092 8192 403186 97926 5.39904 5.39904 -231.32 -5.39904 0 0 310465. 3832.90 0.01 0.10 0.04 -1 -1 0.01 0.0365187 0.0331706 252 351 -1 -1 -1 -1 + k6_frac_ripple_N8_22nm.xml Md5Core.v common 968.02 vpr 871.61 MiB -1 -1 22.34 218328 1 3.90 -1 -1 145312 -1 -1 3580 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 892524 641 128 55563 47815 1 19465 4349 71 71 5041 clb auto 262.5 MiB 670.29 210279 5114045 1917429 3043210 153406 871.6 MiB 143.83 0.80 7.61884 -24559.3 -7.61884 7.61884 21.38 0.0719772 0.0594682 10.7407 8.89088 -1 -1 -1 -1 72 286581 46 1.58244e+08 5.00245e+07 2.39867e+07 4758.32 62.14 31.0052 25.5746 615390 6416121 -1 266321 24 92304 125385 12396060 2405052 4.93927 4.93927 -21502.9 -4.93927 0 0 3.00078e+07 5952.75 1.71 7.10 5.50 -1 -1 1.71 3.83741 3.21004 25723 2050 -1 -1 -1 -1 + k6_frac_ripple_N8_22nm.xml cordic.v common 5.83 vpr 64.57 MiB -1 -1 0.88 26136 4 0.16 -1 -1 33044 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66124 54 51 503 502 1 304 138 9 9 81 clb auto 25.3 MiB 2.08 2002 12954 2480 9062 1412 64.6 MiB 0.20 0.01 4.43013 -227.708 -4.43013 4.43013 0.09 0.001451 0.0013363 0.0685664 0.0632597 -1 -1 -1 -1 56 4228 32 1.43308e+06 461137 231774. 2861.41 1.26 0.391145 0.341818 7704 54090 -1 3725 17 1917 7166 373067 93632 3.65072 3.65072 -196.427 -3.65072 0 0 286113. 3532.26 0.01 0.09 0.03 -1 -1 0.01 0.0324143 0.0294926 234 281 -1 -1 -1 -1 + k6_frac_uripple_N8_22nm.xml Md5Core.v common 472.40 vpr 866.96 MiB -1 -1 22.33 218376 1 4.13 -1 -1 145204 -1 -1 3485 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 887772 641 128 55563 47815 1 18425 4254 71 71 5041 clb auto 256.6 MiB 191.79 205408 4896722 1844424 2914068 138230 867.0 MiB 129.30 1.04 8.03131 -25587.9 -8.03131 8.03131 21.08 0.0733517 0.0590529 10.6832 8.73949 -1 -1 -1 -1 64 273108 50 1.5868e+08 4.91153e+07 2.16513e+07 4295.04 61.30 30.7872 25.3336 590190 5755241 -1 250871 18 71120 89065 8566793 1619750 5.5524 5.5524 -21928.1 -5.5524 0 0 2.72404e+07 5403.77 1.82 6.19 4.71 -1 -1 1.82 3.42355 2.88442 25749 2050 -1 -1 -1 -1 + k6_frac_uripple_N8_22nm.xml cordic.v common 4.49 vpr 64.21 MiB -1 -1 0.92 26136 4 0.16 -1 -1 33152 -1 -1 35 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65752 54 51 503 502 1 303 140 9 9 81 clb auto 25.4 MiB 0.68 1940 13934 2921 9841 1172 64.2 MiB 0.17 0.00 4.47128 -234.847 -4.47128 4.47128 0.09 0.00140285 0.00129011 0.0597002 0.0551005 -1 -1 -1 -1 56 3999 30 1.43728e+06 493284 231774. 2861.41 1.11 0.375638 0.327858 7704 54090 -1 3545 17 1758 6326 315468 81095 3.68106 3.68106 -203.624 -3.68106 0 0 286113. 3532.26 0.01 0.13 0.05 -1 -1 0.01 0.0539124 0.0479125 251 281 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt index f58fc23a7d9..bc4a9702b59 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt @@ -1,31 +1,31 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.76 vpr 64.06 MiB -1 -1 0.45 18428 3 0.09 -1 -1 33228 -1 53036 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65596 99 130 344 474 1 226 298 12 12 144 clb auto 24.8 MiB 0.08 690 66963 18463 34948 13552 64.1 MiB 0.23 0.00 1.84453 -119.387 -1.84453 1.84453 0.26 0.00128301 0.00121619 0.0902368 0.085465 -1 -1 -1 -1 48 1235 27 5.66058e+06 4.21279e+06 394078. 2736.65 0.88 0.373857 0.343183 13382 75762 -1 1211 8 384 646 27249 8414 1.92052 1.92052 -141.203 -1.92052 -0.22504 -0.106568 503207. 3494.49 0.11 0.04 0.07 -1 -1 0.11 0.027115 0.0250754 0.01051 0.26 0.08082 0.6592 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 14.27 vpr 67.39 MiB -1 -1 0.71 23632 15 0.35 -1 -1 34492 -1 54792 39 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69008 162 96 1009 950 1 711 302 16 16 256 mult_36 auto 28.2 MiB 0.26 5690 95430 30621 57523 7286 67.4 MiB 0.71 0.01 21.0118 -1578.46 -21.0118 21.0118 0.51 0.00329249 0.00309405 0.327743 0.307697 -1 -1 -1 -1 48 13017 37 1.21132e+07 4.08187e+06 756778. 2956.16 7.85 1.49988 1.37661 25228 149258 -1 10215 19 3466 7106 912370 260096 21.8757 21.8757 -1697.9 -21.8757 0 0 968034. 3781.38 0.22 0.33 0.13 -1 -1 0.22 0.146899 0.13583 0.007773 0.3631 0.01709 0.6198 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 401.39 vpr 460.05 MiB -1 -1 83.22 343248 123 58.49 -1 -1 79500 -1 117196 1366 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 471088 114 102 21994 21904 1 11836 1635 50 50 2500 memory auto 154.8 MiB 20.21 157807 1070343 385976 662554 21813 460.0 MiB 25.59 0.21 79.4041 -53458.1 -79.4041 79.4041 19.31 0.0604453 0.0527448 7.45004 6.20215 -1 -1 -1 -1 94 240754 50 1.47946e+08 1.0145e+08 1.55181e+07 6207.23 114.06 27.7995 22.9975 341268 3271592 -1 215929 21 44770 168610 10181079 1913380 79.6681 79.6681 -67309 -79.6681 -34.1184 -0.295467 1.95446e+07 7817.85 7.00 6.34 2.88 -1 -1 7.00 3.52242 3.0254 0.08167 0.4293 0.0115 0.5592 - k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.68 vpr 64.21 MiB -1 -1 0.49 18412 3 0.09 -1 -1 33192 -1 53180 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65752 99 130 344 474 1 226 298 12 12 144 clb auto 25.2 MiB 0.10 819 72933 24290 33841 14802 64.2 MiB 0.24 0.00 1.91347 -122.834 -1.91347 1.91347 0.26 0.00128041 0.00121074 0.0975158 0.0923199 -1 -1 -1 -1 46 1427 13 5.66058e+06 4.21279e+06 378970. 2631.74 1.69 0.37035 0.339938 13238 73581 -1 1364 9 400 647 30525 8792 1.87624 1.87624 -136.601 -1.87624 -1.17589 -0.322548 486261. 3376.82 0.10 0.05 0.07 -1 -1 0.10 0.029177 0.0269441 0.01251 0.2572 0.06872 0.6741 - k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml diffeq1.v common 13.20 vpr 67.45 MiB -1 -1 0.72 23304 15 0.35 -1 -1 34404 -1 54880 39 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69064 162 96 1009 950 1 711 302 16 16 256 mult_36 auto 28.2 MiB 0.33 5690 95430 30623 57523 7284 67.4 MiB 0.72 0.01 21.0118 -1578.35 -21.0118 21.0118 0.52 0.00334815 0.00314845 0.334671 0.314364 -1 -1 -1 -1 48 13572 38 1.21132e+07 4.08187e+06 756778. 2956.16 6.63 1.3536 1.2446 25228 149258 -1 10088 17 3403 6982 882550 253315 21.8901 21.8901 -1680.47 -21.8901 0 0 968034. 3781.38 0.22 0.31 0.13 -1 -1 0.22 0.135825 0.125866 0.008049 0.3475 0.01649 0.636 - k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml LU8PEEng.v common 408.55 vpr 462.37 MiB -1 -1 83.91 346936 123 56.59 -1 -1 79516 -1 117232 1283 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 473464 114 102 21994 21904 1 11396 1552 50 50 2500 memory auto 158.9 MiB 48.19 155931 971608 341857 610635 19116 462.4 MiB 25.21 0.21 80.3837 -53565.2 -80.3837 80.3837 20.66 0.0618498 0.0542286 7.48256 6.24492 -1 -1 -1 -1 96 229667 22 1.47946e+08 9.69764e+07 1.58254e+07 6330.17 92.97 25.1374 20.8491 343768 3324272 -1 208496 21 41726 161181 9376663 1766124 80.5561 80.5561 -67304.6 -80.5561 -13.3147 -0.295467 1.97871e+07 7914.84 6.32 5.96 2.94 -1 -1 6.32 3.48565 2.98525 0.08322 0.4235 0.01132 0.5652 - k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.77 vpr 64.30 MiB -1 -1 0.47 18588 3 0.09 -1 -1 33172 -1 53072 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65844 99 130 344 474 1 226 298 12 12 144 clb auto 25.1 MiB 0.15 699 66963 17966 34693 14304 64.3 MiB 0.23 0.00 1.84343 -124.37 -1.84343 1.84343 0.27 0.00123085 0.00116207 0.0901875 0.0853725 -1 -1 -1 -1 34 1396 8 5.66058e+06 4.21279e+06 307677. 2136.65 1.83 0.530992 0.483083 12584 59343 -1 1233 10 404 639 23079 7765 1.94353 1.94353 -145.674 -1.94353 -0.336499 -0.167028 377431. 2621.05 0.09 0.05 0.05 -1 -1 0.09 0.0313345 0.0289285 0.01001 0.231 0.07204 0.697 - k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml diffeq1.v common 13.25 vpr 67.53 MiB -1 -1 0.72 23416 15 0.35 -1 -1 34272 -1 54808 39 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69152 162 96 1009 950 1 705 302 16 16 256 mult_36 auto 28.3 MiB 0.84 5916 86322 26942 52489 6891 67.5 MiB 0.65 0.01 21.2591 -1580.87 -21.2591 21.2591 0.54 0.00333899 0.00313775 0.30219 0.283938 -1 -1 -1 -1 48 12788 29 1.21132e+07 4.08187e+06 791884. 3093.30 6.16 1.45115 1.33083 26208 159478 -1 10226 17 3178 6770 896758 257736 22.1828 22.1828 -1735.12 -22.1828 0 0 1.01413e+06 3961.44 0.24 0.32 0.13 -1 -1 0.24 0.137182 0.127174 0.008014 0.3561 0.01656 0.6273 - k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml LU8PEEng.v common 680.75 vpr 490.74 MiB -1 -1 81.98 346216 123 60.04 -1 -1 79272 -1 117192 1288 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 502520 114 102 21994 21904 1 12045 1557 50 50 2500 memory auto 155.5 MiB 213.60 164488 1011797 361199 628216 22382 490.7 MiB 26.52 0.22 79.4472 -51530.1 -79.4472 79.4472 22.32 0.060741 0.0533068 7.58406 6.36451 -1 -1 -1 -1 96 243545 47 1.47946e+08 9.72458e+07 1.65526e+07 6621.02 194.25 27.7583 23.1223 355864 3561008 -1 217786 21 41299 157335 9832993 1863421 80.3477 80.3477 -63213.1 -80.3477 -9.95257 -0.29436 2.06346e+07 8253.84 6.55 6.06 3.05 -1 -1 6.55 3.47074 2.99437 0.08657 0.4192 0.01142 0.5694 - k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.40 vpr 64.41 MiB -1 -1 0.46 18612 3 0.09 -1 -1 33252 -1 52968 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65952 99 130 344 474 1 226 298 12 12 144 clb auto 25.4 MiB 0.13 692 72933 23276 35223 14434 64.4 MiB 0.24 0.00 1.86464 -118.633 -1.86464 1.86464 0.27 0.00127857 0.00121127 0.0978445 0.0926191 -1 -1 -1 -1 38 1411 12 5.66058e+06 4.21279e+06 334530. 2323.13 1.40 0.417201 0.382648 13012 66834 -1 1212 7 400 636 24860 8313 1.99361 1.99361 -136.339 -1.99361 -0.924755 -0.320482 424691. 2949.24 0.10 0.04 0.06 -1 -1 0.10 0.0250475 0.0232193 0.0114 0.2245 0.06531 0.7102 - k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml diffeq1.v common 10.29 vpr 67.59 MiB -1 -1 0.73 23388 15 0.35 -1 -1 34328 -1 54912 38 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69208 162 96 1009 950 1 706 301 16 16 256 mult_36 auto 28.4 MiB 0.95 5815 73885 21988 46599 5298 67.6 MiB 0.58 0.01 20.9884 -1505.17 -20.9884 20.9884 0.54 0.00334172 0.00313673 0.25816 0.242412 -1 -1 -1 -1 46 13107 32 1.21132e+07 4.02797e+06 761464. 2974.47 3.14 0.910149 0.838444 25952 154797 -1 10036 18 3102 6455 835144 242123 22.1364 22.1364 -1610.51 -22.1364 0 0 979054. 3824.43 0.23 0.31 0.13 -1 -1 0.23 0.142565 0.132103 0.008278 0.3388 0.01582 0.6453 - k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml LU8PEEng.v common 590.93 vpr 489.86 MiB -1 -1 82.75 346848 123 58.04 -1 -1 79280 -1 117184 1193 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 501620 114 102 21994 21904 1 11319 1462 50 50 2500 memory auto 156.6 MiB 191.22 150803 905508 321541 566075 17892 489.9 MiB 22.88 0.19 78.1077 -50345.2 -78.1077 78.1077 21.98 0.0591849 0.0516876 7.17008 5.99965 -1 -1 -1 -1 92 228120 37 1.47946e+08 9.21257e+07 1.59225e+07 6369.02 133.10 26.7258 22.1743 350868 3451476 -1 203270 20 41572 162541 9562123 1847272 78.237 78.237 -64005.6 -78.237 -38.6467 -0.293253 2.01686e+07 8067.44 6.81 6.03 2.89 -1 -1 6.81 3.4232 2.94021 0.08721 0.4013 0.01147 0.5872 - k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.75 vpr 64.53 MiB -1 -1 0.47 18468 3 0.09 -1 -1 33276 -1 53036 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66076 99 130 344 474 1 224 298 12 12 144 clb auto 25.3 MiB 0.15 684 73928 22492 35269 16167 64.5 MiB 0.25 0.00 1.84564 -120.454 -1.84564 1.84564 0.28 0.00128312 0.00121622 0.099544 0.0942601 -1 -1 -1 -1 32 1444 14 5.66058e+06 4.21279e+06 307825. 2137.67 0.69 0.279002 0.257511 12860 59602 -1 1374 12 375 565 30620 10341 2.02431 2.02431 -141.661 -2.02431 -0.372022 -0.169903 375846. 2610.04 0.09 0.05 0.05 -1 -1 0.09 0.0357317 0.0329107 0.009994 0.2606 0.06791 0.6715 - k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 11.09 vpr 67.76 MiB -1 -1 0.72 23484 15 0.35 -1 -1 34496 -1 54884 36 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69384 162 96 1009 950 1 712 299 16 16 256 mult_36 auto 28.5 MiB 0.82 5783 78221 22549 49384 6288 67.8 MiB 0.60 0.01 21.2118 -1583.01 -21.2118 21.2118 0.56 0.00335661 0.00314936 0.275732 0.259044 -1 -1 -1 -1 46 13220 42 1.21132e+07 3.92018e+06 791147. 3090.42 4.06 0.996512 0.917657 26792 163197 -1 10183 19 3349 7152 989589 281475 22.2653 22.2653 -1681.46 -22.2653 0 0 1.01637e+06 3970.19 0.23 0.34 0.13 -1 -1 0.23 0.146642 0.135717 0.008056 0.352 0.01624 0.6318 - k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 685.71 vpr 541.36 MiB -1 -1 82.72 346304 123 60.41 -1 -1 79620 -1 117176 1274 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 554352 114 102 21994 21904 1 11815 1543 50 50 2500 memory auto 156.5 MiB 261.00 166633 946215 318795 604305 23115 541.4 MiB 23.62 0.21 80.1279 -54074.7 -80.1279 80.1279 26.36 0.0593802 0.0519284 6.93138 5.84084 -1 -1 -1 -1 94 248407 44 1.47946e+08 9.64913e+07 1.68500e+07 6739.98 149.04 27.7074 23.0826 363732 3705320 -1 218597 20 39669 154060 10430670 2004897 80.2496 80.2496 -66632.5 -80.2496 -14.4798 -0.29436 2.11127e+07 8445.07 6.74 6.02 3.27 -1 -1 6.74 3.35396 2.8887 0.08961 0.4087 0.01166 0.5796 - k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.69 vpr 64.59 MiB -1 -1 0.47 18536 3 0.09 -1 -1 33168 -1 53016 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66140 99 130 344 474 1 224 298 12 12 144 clb auto 25.6 MiB 0.14 723 72933 21131 35508 16294 64.6 MiB 0.24 0.00 1.84896 -122.984 -1.84896 1.84896 0.28 0.00129708 0.00123013 0.0982963 0.0931302 -1 -1 -1 -1 32 1546 9 5.66058e+06 4.21279e+06 307825. 2137.67 1.66 0.461106 0.422085 12860 59602 -1 1430 7 347 561 25878 8702 1.97804 1.97804 -145.694 -1.97804 -0.24122 -0.0950605 375846. 2610.04 0.09 0.04 0.06 -1 -1 0.09 0.0254919 0.0236226 0.01153 0.2343 0.06023 0.7055 - k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml diffeq1.v common 11.76 vpr 68.03 MiB -1 -1 0.73 23656 15 0.35 -1 -1 34312 -1 54840 36 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69664 162 96 1009 950 1 712 299 16 16 256 mult_36 auto 28.7 MiB 1.03 5783 78221 22554 49384 6283 68.0 MiB 0.61 0.01 21.2118 -1582.92 -21.2118 21.2118 0.59 0.00341236 0.003205 0.281532 0.264594 -1 -1 -1 -1 46 13227 46 1.21132e+07 3.92018e+06 791147. 3090.42 4.29 1.02224 0.94124 26792 163197 -1 10289 19 3183 6723 927239 263450 22.3978 22.3978 -1754.57 -22.3978 0 0 1.01637e+06 3970.19 0.24 0.35 0.13 -1 -1 0.24 0.152499 0.14121 0.008319 0.3396 0.01564 0.6448 - k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 710.23 vpr 546.39 MiB -1 -1 84.01 346708 123 57.00 -1 -1 79472 -1 117204 1175 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 559508 114 102 21994 21904 1 10942 1444 50 50 2500 memory auto 156.6 MiB 247.45 149383 890666 315853 555376 19437 546.4 MiB 24.29 0.22 78.9433 -49861.2 -78.9433 78.9433 26.06 0.0637968 0.0519727 7.43281 6.14665 -1 -1 -1 -1 92 224977 28 1.47946e+08 9.11556e+07 1.65231e+07 6609.23 189.49 27.8764 23.0735 361236 3648468 -1 197674 21 36197 148054 8655924 1696159 79.8587 79.8587 -61942.5 -79.8587 -11.4535 -0.29436 2.08892e+07 8355.67 6.76 5.76 3.02 -1 -1 6.76 3.44382 2.97064 0.08992 0.3929 0.01157 0.5955 - k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.83 vpr 64.24 MiB -1 -1 0.46 18588 3 0.09 -1 -1 33268 -1 53060 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65780 99 130 344 474 1 226 298 12 12 144 clb auto 25.0 MiB 0.14 690 66963 18463 34948 13552 64.2 MiB 0.23 0.00 1.84453 -119.387 -1.84453 1.84453 0.26 0.00128966 0.00122151 0.0906009 0.0857911 -1 -1 -1 -1 48 1219 27 5.66058e+06 4.21279e+06 394078. 2736.65 0.88 0.374327 0.343576 13382 75762 -1 1213 10 380 620 26636 8291 1.92052 1.92052 -132.564 -1.92052 -0.22504 -0.106568 503207. 3494.49 0.11 0.05 0.07 -1 -1 0.11 0.031463 0.0290047 0.01061 0.2612 0.08008 0.6587 - k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml diffeq1.v common 13.92 vpr 67.27 MiB -1 -1 0.74 23740 15 0.35 -1 -1 34420 -1 54776 37 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 68880 162 96 1009 950 1 705 300 16 16 256 mult_36 auto 28.1 MiB 0.78 5822 99597 35964 57057 6576 67.3 MiB 0.75 0.01 20.9826 -1581.32 -20.9826 20.9826 0.51 0.00340159 0.00318809 0.352654 0.330998 -1 -1 -1 -1 46 13288 46 1.21132e+07 3.97408e+06 727248. 2840.81 6.84 1.58393 1.45671 24972 144857 -1 10547 19 3468 7301 1024533 298496 22.4428 22.4428 -1807.38 -22.4428 0 0 934704. 3651.19 0.21 0.34 0.12 -1 -1 0.21 0.144733 0.133839 0.00776 0.3586 0.01653 0.6249 - k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml LU8PEEng.v common 530.63 vpr 452.32 MiB -1 -1 84.49 343012 123 57.56 -1 -1 79496 -1 117260 1312 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 463172 114 102 21994 21904 1 12069 1581 50 50 2500 memory auto 155.7 MiB 153.23 156855 1014241 368235 623960 22046 452.3 MiB 24.95 0.21 79.7937 -51339.3 -79.7937 79.7937 19.16 0.0602961 0.0527292 7.34313 6.15426 -1 -1 -1 -1 96 234956 41 1.47946e+08 9.85393e+07 1.58254e+07 6330.17 110.51 24.5347 20.3374 343768 3324272 -1 213019 20 45703 171940 10043077 1887993 79.5447 79.5447 -64945.1 -79.5447 -27.0382 -0.295467 1.97871e+07 7914.84 6.68 5.96 2.93 -1 -1 6.68 3.33648 2.88206 0.08305 0.4251 0.01164 0.5633 - k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.60 vpr 64.32 MiB -1 -1 0.46 18460 3 0.09 -1 -1 33116 -1 52940 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65868 99 130 344 474 1 226 298 12 12 144 clb auto 25.3 MiB 0.13 819 72933 24290 33841 14802 64.3 MiB 0.24 0.00 1.91347 -122.834 -1.91347 1.91347 0.26 0.00127684 0.00120774 0.0977163 0.092509 -1 -1 -1 -1 46 1423 13 5.66058e+06 4.21279e+06 378970. 2631.74 1.68 0.370142 0.339907 13238 73581 -1 1376 9 406 664 31725 9062 1.87624 1.87624 -136.482 -1.87624 -1.17589 -0.322548 486261. 3376.82 0.10 0.05 0.07 -1 -1 0.10 0.0294731 0.0272283 0.01259 0.2575 0.06826 0.6742 - k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml diffeq1.v common 11.88 vpr 67.57 MiB -1 -1 0.71 23172 15 0.35 -1 -1 34336 -1 55020 38 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69196 162 96 1009 950 1 712 301 16 16 256 mult_36 auto 28.4 MiB 0.90 5650 82957 25249 50207 7501 67.6 MiB 0.63 0.01 21.0836 -1553.51 -21.0836 21.0836 0.52 0.00341845 0.00321054 0.295101 0.277311 -1 -1 -1 -1 52 12449 43 1.21132e+07 4.02797e+06 805949. 3148.24 4.82 1.2104 1.11453 25992 162577 -1 9670 14 3083 6221 808658 230419 22.2502 22.2502 -1680.34 -22.2502 0 0 1.06067e+06 4143.25 0.23 0.28 0.14 -1 -1 0.23 0.11935 0.1109 0.008212 0.3529 0.01664 0.6305 - k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml LU8PEEng.v common 567.80 vpr 459.82 MiB -1 -1 83.88 346828 123 56.93 -1 -1 79404 -1 117236 1232 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 470852 114 102 21994 21904 1 11410 1501 50 50 2500 memory auto 157.1 MiB 153.85 152566 937811 338282 579692 19837 459.8 MiB 23.16 0.20 79.5093 -52803.3 -79.5093 79.5093 19.01 0.0589847 0.0516048 7.12415 5.9667 -1 -1 -1 -1 94 230017 31 1.47946e+08 9.42277e+07 1.55181e+07 6207.23 151.42 27.1606 22.5407 341268 3271592 -1 206976 21 43395 164909 10164437 1931987 79.3467 79.3467 -64718.7 -79.3467 -7.07382 -0.296573 1.95446e+07 7817.85 6.05 6.03 2.95 -1 -1 6.05 3.41938 2.93997 0.08398 0.4124 0.01155 0.5761 - k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.79 vpr 64.62 MiB -1 -1 0.46 18580 3 0.09 -1 -1 33112 -1 53044 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66176 99 130 344 474 1 224 298 12 12 144 clb auto 25.4 MiB 0.15 678 73928 21255 36531 16142 64.6 MiB 0.25 0.00 1.84343 -119.532 -1.84343 1.84343 0.27 0.00127236 0.00120574 0.0989421 0.0936831 -1 -1 -1 -1 50 1296 14 5.66058e+06 4.21279e+06 406292. 2821.48 1.82 0.448976 0.411503 13526 77840 -1 1195 11 357 532 29874 9121 1.99509 1.99509 -135.514 -1.99509 -0.544742 -0.178238 520805. 3616.70 0.11 0.05 0.07 -1 -1 0.11 0.0334864 0.0308874 0.01027 0.2615 0.07863 0.6599 - k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 10.02 vpr 67.49 MiB -1 -1 0.73 23636 15 0.35 -1 -1 34472 -1 54844 36 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69108 162 96 1009 950 1 713 299 16 16 256 mult_36 auto 28.3 MiB 0.75 5721 86213 28592 52244 5377 67.5 MiB 0.66 0.01 20.8058 -1501.7 -20.8058 20.8058 0.51 0.00342119 0.00321645 0.305002 0.28669 -1 -1 -1 -1 48 13175 30 1.21132e+07 3.92018e+06 756778. 2956.16 3.01 0.967828 0.892591 25228 149258 -1 10301 18 3425 6878 942155 258318 22.3533 22.3533 -1697.63 -22.3533 0 0 968034. 3781.38 0.22 0.33 0.14 -1 -1 0.22 0.143607 0.132965 0.007929 0.3557 0.01643 0.6279 - k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 625.06 vpr 452.82 MiB -1 -1 84.98 342824 123 57.69 -1 -1 79376 -1 117200 1303 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 463692 114 102 21994 21904 1 11945 1572 50 50 2500 memory auto 156.6 MiB 165.49 160111 988260 342703 624333 21224 452.8 MiB 23.88 0.23 79.9872 -53373.2 -79.9872 79.9872 18.91 0.0587079 0.0512977 7.09493 5.97271 -1 -1 -1 -1 98 240200 31 1.47946e+08 9.80543e+07 1.60641e+07 6425.63 192.41 27.0374 22.491 348768 3430976 -1 216847 21 44681 169424 9942056 1841988 81.5457 81.5457 -64488 -81.5457 -39.6896 -0.29436 2.03677e+07 8147.07 6.25 5.93 3.10 -1 -1 6.25 3.40108 2.93127 0.08479 0.4269 0.01147 0.5616 - k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 3.82 vpr 64.68 MiB -1 -1 0.48 18524 3 0.09 -1 -1 33252 -1 53000 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66236 99 130 344 474 1 224 298 12 12 144 clb auto 25.7 MiB 0.13 698 72933 20188 36234 16511 64.7 MiB 0.24 0.00 1.84564 -121.191 -1.84564 1.84564 0.26 0.00128124 0.00121391 0.0977819 0.0926146 -1 -1 -1 -1 48 1220 12 5.66058e+06 4.21279e+06 394078. 2736.65 0.84 0.349739 0.321525 13382 75762 -1 1200 11 356 571 27848 8427 1.97152 1.97152 -138.744 -1.97152 -0.366576 -0.220625 503207. 3494.49 0.11 0.05 0.07 -1 -1 0.11 0.0335359 0.030924 0.01177 0.2373 0.07035 0.6923 - k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml diffeq1.v common 12.60 vpr 67.55 MiB -1 -1 0.73 23468 15 0.35 -1 -1 34400 -1 54856 36 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69172 162 96 1009 950 1 713 299 16 16 256 mult_36 auto 28.4 MiB 0.93 5721 86213 28592 52244 5377 67.6 MiB 0.66 0.01 20.8058 -1501.7 -20.8058 20.8058 0.51 0.00335344 0.00314925 0.303909 0.285307 -1 -1 -1 -1 50 11869 21 1.21132e+07 3.92018e+06 780512. 3048.87 5.52 1.32663 1.21819 25484 153448 -1 10126 17 3362 6747 918313 252436 22.3405 22.3405 -1650.85 -22.3405 0 0 1.00276e+06 3917.05 0.22 0.31 0.13 -1 -1 0.22 0.137518 0.127577 0.008272 0.3466 0.01554 0.6378 - k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 598.55 vpr 491.77 MiB -1 -1 84.05 346908 123 53.64 -1 -1 79372 -1 117228 1201 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 503568 114 102 21994 21904 1 11170 1470 50 50 2500 memory auto 156.4 MiB 166.03 150651 903810 320390 563000 20420 459.0 MiB 22.23 0.19 78.4561 -52150.3 -78.4561 78.4561 18.73 0.058846 0.0512813 7.13124 5.98955 -1 -1 -1 -1 96 226476 38 1.47946e+08 9.25569e+07 1.58254e+07 6330.17 173.31 36.0661 29.773 343768 3324272 -1 204225 21 42293 163966 10269335 1942383 79.7709 79.7709 -64638.4 -79.7709 -5.0051 -0.29436 1.97871e+07 7914.84 6.66 6.08 2.93 -1 -1 6.66 3.42255 2.94526 0.08545 0.4092 0.0116 0.5791 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.41 vpr 66.85 MiB -1 -1 0.34 22268 3 0.10 -1 -1 37000 -1 54240 68 99 1 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68452 99 130 344 474 1 226 298 12 12 144 clb auto 27.2 MiB 0.07 661 69948 21317 34488 14143 66.8 MiB 0.19 0.00 1.84343 -120.716 -1.84343 1.84343 0.15 0.000836305 0.000777868 0.0624432 0.0579886 -1 -1 -1 -1 48 1234 11 5.66058e+06 4.21279e+06 394078. 2736.65 1.13 0.388411 0.354166 13382 75762 -1 1152 12 449 726 34037 10619 1.91136 1.91136 -134.16 -1.91136 -1.28997 -0.320482 503207. 3494.49 0.02 0.04 0.08 -1 -1 0.02 0.0268156 0.0249636 0.01041 0.2485 0.08202 0.6695 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 11.54 vpr 70.42 MiB -1 -1 0.52 27052 15 0.44 -1 -1 37612 -1 56036 39 162 0 5 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 72112 162 96 1009 950 1 709 302 16 16 256 mult_36 auto 30.4 MiB 0.30 5587 92394 30880 53838 7676 70.4 MiB 0.63 0.01 21.0975 -1536.06 -21.0975 21.0975 0.31 0.00264219 0.0024523 0.255431 0.237213 -1 -1 -1 -1 54 12491 42 1.21132e+07 4.08187e+06 835850. 3265.04 5.79 1.11973 1.03745 26248 167850 -1 9804 18 3129 6329 829951 256686 22.2714 22.2714 -1674.4 -22.2714 0 0 1.08614e+06 4242.72 0.05 0.30 0.16 -1 -1 0.05 0.123137 0.115878 0.007816 0.3726 0.01778 0.6096 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 445.10 vpr 422.13 MiB -1 -1 69.38 368528 123 78.20 -1 -1 82692 -1 118888 1375 114 45 8 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 432260 114 102 21994 21904 1 11802 1644 50 50 2500 memory auto 156.2 MiB 22.97 160790 1049136 374899 655277 18960 422.1 MiB 26.05 0.23 78.4871 -53143.2 -78.4871 78.4871 11.24 0.052813 0.0462077 6.2757 5.24155 -1 -1 -1 -1 94 237421 37 1.47946e+08 1.01935e+08 1.55181e+07 6207.23 158.08 25.6908 21.7243 341268 3271592 -1 217663 19 44811 172250 10215733 1905978 81.238 81.238 -63088.5 -81.238 -14.6885 -0.29436 1.95446e+07 7817.85 1.30 6.17 3.55 -1 -1 1.30 3.3903 2.9824 0.08135 0.4303 0.01138 0.5584 +k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 3.52 vpr 67.00 MiB -1 -1 0.34 22060 3 0.09 -1 -1 37120 -1 54184 68 99 1 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68612 99 130 344 474 1 226 298 12 12 144 clb auto 27.4 MiB 0.11 716 68953 19729 34143 15081 67.0 MiB 0.20 0.00 1.84343 -118.985 -1.84343 1.84343 0.16 0.000884793 0.00082197 0.0659105 0.0611015 -1 -1 -1 -1 50 1307 17 5.66058e+06 4.21279e+06 406292. 2821.48 1.16 0.290646 0.265392 13526 77840 -1 1223 12 430 705 34827 10711 2.03591 2.03591 -135.117 -2.03591 -0.536858 -0.172926 520805. 3616.70 0.02 0.04 0.08 -1 -1 0.02 0.0279279 0.0259917 0.01127 0.2362 0.07017 0.6936 +k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml diffeq1.v common 11.30 vpr 70.10 MiB -1 -1 0.54 27172 15 0.44 -1 -1 38168 -1 56116 39 162 0 5 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 71784 162 96 1009 950 1 709 302 16 16 256 mult_36 auto 30.1 MiB 0.39 5587 92394 30879 53839 7676 70.1 MiB 0.66 0.01 21.0975 -1536.12 -21.0975 21.0975 0.31 0.00286543 0.00265289 0.276055 0.256826 -1 -1 -1 -1 56 11626 33 1.21132e+07 4.08187e+06 870502. 3400.40 5.32 1.27718 1.18421 26504 172068 -1 9678 21 2911 5904 758117 233537 22.3178 22.3178 -1651.57 -22.3178 0 0 1.11200e+06 4343.75 0.05 0.32 0.17 -1 -1 0.05 0.141995 0.133696 0.008142 0.3626 0.01671 0.6207 +k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml LU8PEEng.v common 454.81 vpr 426.46 MiB -1 -1 71.31 367564 123 81.62 -1 -1 82248 -1 118536 1291 114 45 8 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 436700 114 102 21994 21904 1 11352 1560 50 50 2500 memory auto 158.3 MiB 61.05 152483 987356 362069 607612 17675 426.5 MiB 26.52 0.22 79.1367 -50547.3 -79.1367 79.1367 11.72 0.0513453 0.0448586 6.66942 5.5865 -1 -1 -1 -1 92 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2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68676 99 130 344 474 1 226 298 12 12 144 clb auto 27.2 MiB 0.15 708 68953 19077 35256 14620 67.1 MiB 0.19 0.00 1.84675 -120.418 -1.84675 1.84675 0.16 0.000896212 0.000833184 0.0639544 0.0592867 -1 -1 -1 -1 32 1546 17 5.66058e+06 4.21279e+06 295695. 2053.44 0.32 0.170676 0.156606 12440 56522 -1 1380 11 395 551 27778 8974 2.00702 2.00702 -146.809 -2.00702 -0.360519 -0.100806 361905. 2513.23 0.02 0.04 0.05 -1 -1 0.02 0.0259164 0.0241103 0.01128 0.2266 0.06022 0.7132 +k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml diffeq1.v common 10.36 vpr 70.66 MiB -1 -1 0.53 27052 15 0.44 -1 -1 37896 -1 56252 38 162 0 5 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 72360 162 96 1009 950 1 695 301 16 16 256 mult_36 auto 30.6 MiB 0.96 5610 94045 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VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 423676 114 102 21994 21904 1 11865 1590 50 50 2500 memory auto 157.0 MiB 234.23 159962 1012674 360995 632974 18705 413.7 MiB 28.65 0.24 80.0347 -53799.9 -80.0347 80.0347 11.56 0.0584029 0.048305 6.87553 5.75603 -1 -1 -1 -1 98 236251 50 1.47946e+08 9.90244e+07 1.60641e+07 6425.63 236.89 27.583 23.3765 348768 3430976 -1 213518 19 44437 171946 9945264 1846943 82.1489 82.1489 -66738.4 -82.1489 -32.5879 -0.295467 2.03677e+07 8147.07 1.31 6.03 3.88 -1 -1 1.31 3.45254 3.05529 0.0845 0.427 0.01145 0.5616 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 2.93 vpr 67.35 MiB -1 -1 0.33 22060 3 0.09 -1 -1 36884 -1 54528 68 99 1 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68968 99 130 344 474 1 224 298 12 12 144 clb auto 27.6 MiB 0.15 687 68953 19356 33866 15731 67.4 MiB 0.19 0.00 1.84343 -121.129 -1.84343 1.84343 0.16 0.00085163 0.000776737 0.0614238 0.0570225 -1 -1 -1 -1 50 1252 13 5.66058e+06 4.21279e+06 406292. 2821.48 0.55 0.231719 0.212206 13526 77840 -1 1181 11 369 581 25228 7706 1.92695 1.92695 -132.699 -1.92695 -0.484167 -0.178238 520805. 3616.70 0.02 0.04 0.08 -1 -1 0.02 0.0260129 0.0241858 0.01196 0.2348 0.06986 0.6954 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml diffeq1.v common 10.78 vpr 70.93 MiB -1 -1 0.50 27244 15 0.44 -1 -1 37616 -1 56252 39 162 0 5 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 72628 162 96 1009 950 1 696 302 16 16 256 mult_36 auto 30.6 MiB 0.82 5628 84298 25487 51591 7220 70.9 MiB 0.61 0.01 20.5614 -1538.13 -20.5614 20.5614 0.31 0.00277962 0.00258393 0.2467 0.229461 -1 -1 -1 -1 48 11900 27 1.21132e+07 4.08187e+06 756778. 2956.16 4.46 1.13654 1.0514 25228 149258 -1 9893 20 3407 7154 882105 254608 22.0311 22.0311 -1692.99 -22.0311 0 0 968034. 3781.38 0.05 0.34 0.14 -1 -1 0.05 0.137752 0.129626 0.008223 0.3385 0.01605 0.6455 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 690.94 vpr 425.08 MiB -1 -1 65.25 367856 123 79.72 -1 -1 82696 -1 118676 1206 114 45 8 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 435280 114 102 21994 21904 1 11136 1475 50 50 2500 memory auto 157.9 MiB 235.02 149552 916312 318253 574633 23426 425.1 MiB 26.64 0.23 79.6388 -49613.8 -79.6388 79.6388 11.39 0.057808 0.048017 6.8334 5.67923 -1 -1 -1 -1 96 228699 35 1.47946e+08 9.28264e+07 1.58254e+07 6330.17 187.06 28.054 23.6791 343768 3324272 -1 203782 21 43588 169952 10265906 1938967 79.9409 79.9409 -62955.8 -79.9409 -22.6241 -0.295467 1.97871e+07 7914.84 1.28 6.23 3.62 -1 -1 1.28 3.53958 3.11283 0.08518 0.4086 0.01162 0.5798 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt index cc62481848e..8d6884970eb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt @@ -1,15 +1,15 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 101.34 parmys 236.79 MiB -1 -1 60.71 242472 13 8.21 -1 -1 47864 -1 49620 321 257 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 95300 257 32 5008 5040 1 2969 610 23 23 529 clb auto 50.4 MiB 3.82 20279 215248 66110 139947 9191 93.1 MiB 3.04 0.04 8.70616 -3949.99 -8.70616 8.70616 1.18 0.0125771 0.0113805 1.0992 0.970008 -1 -1 -1 -1 56 34377 21 2.70004e+07 1.73e+07 1.92373e+06 3636.54 8.22 3.45323 3.01988 56706 387443 -1 30578 16 11916 36297 982790 202359 9.34373 9.34373 -4057.11 -9.34373 0 0 2.45466e+06 4640.18 0.60 0.82 0.32 -1 -1 0.60 0.512599 0.462114 0.01666 0.4299 0.03362 0.5365 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml blob_merge.v common 107.46 parmys 306.12 MiB -1 -1 20.79 313468 7 12.29 -1 -1 61008 -1 50612 547 36 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 159172 36 100 6778 6878 1 3152 683 30 30 900 clb auto 67.4 MiB 3.53 43003 265211 75875 171128 18208 113.8 MiB 5.03 0.06 5.7259 -2235.23 -5.7259 5.7259 2.15 0.0185179 0.0154456 1.73258 1.47032 -1 -1 -1 -1 70 65187 20 4.8774e+07 2.948e+07 4.18297e+06 4647.75 38.88 8.89422 7.5224 106732 854442 -1 61867 16 14594 66731 2752238 371387 6.2856 6.2856 -2335.12 -6.2856 0 0 5.26086e+06 5845.40 1.29 1.60 0.70 -1 -1 1.29 0.836319 0.749628 0.02599 0.3676 0.06197 0.5704 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml boundtop.v common 24.16 vpr 67.42 MiB -1 -1 17.13 32316 4 0.24 -1 -1 34324 -1 55220 50 195 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69040 195 193 1087 1280 1 611 439 15 15 225 io auto 28.5 MiB 0.29 3380 103793 26292 68639 8862 67.4 MiB 0.54 0.01 2.49928 -1085.58 -2.49928 2.49928 0.45 0.00353825 0.00330455 0.231878 0.216292 -1 -1 -1 -1 38 6431 21 1.03862e+07 3.2427e+06 544128. 2418.35 1.99 1.01597 0.930332 21038 109288 -1 5638 14 1680 2547 165707 45554 2.61737 2.61737 -1202.07 -2.61737 -0.383541 -0.179345 690492. 3068.85 0.16 0.17 0.09 -1 -1 0.16 0.118647 0.10973 0.01444 0.3894 0.05366 0.5569 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.90 vpr 64.11 MiB -1 -1 0.46 18576 3 0.09 -1 -1 33260 -1 53084 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65652 99 130 344 474 1 226 298 12 12 144 clb auto 24.9 MiB 0.08 690 66963 18463 34948 13552 64.1 MiB 0.23 0.00 1.84453 -119.387 -1.84453 1.84453 0.26 0.00128062 0.00121358 0.0901314 0.0853406 -1 -1 -1 -1 48 1235 27 5.66058e+06 4.21279e+06 394078. 2736.65 0.89 0.376068 0.345073 13382 75762 -1 1211 8 384 646 27249 8414 1.92052 1.92052 -141.203 -1.92052 -0.22504 -0.106568 503207. 3494.49 0.11 0.04 0.07 -1 -1 0.11 0.0270219 0.0250048 0.01051 0.26 0.08082 0.6592 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 10.77 vpr 67.23 MiB -1 -1 0.74 23536 15 0.37 -1 -1 34412 -1 54864 39 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 68840 162 96 1009 950 1 711 302 16 16 256 mult_36 auto 28.0 MiB 0.26 5690 95430 30621 57523 7286 67.2 MiB 0.71 0.01 21.0118 -1578.46 -21.0118 21.0118 0.51 0.00332849 0.00313083 0.328391 0.308461 -1 -1 -1 -1 48 13017 37 1.21132e+07 4.08187e+06 756778. 2956.16 4.22 1.0699 0.986615 25228 149258 -1 10215 19 3466 7106 912370 260096 21.8757 21.8757 -1697.9 -21.8757 0 0 968034. 3781.38 0.22 0.33 0.13 -1 -1 0.22 0.149551 0.138422 0.007773 0.3631 0.01709 0.6198 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq2.v common 11.72 vpr 65.73 MiB -1 -1 0.58 22544 16 0.25 -1 -1 33408 -1 53836 25 66 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 67312 66 96 616 557 1 415 192 16 16 256 mult_36 auto 26.2 MiB 0.24 3582 35584 8711 22727 4146 65.7 MiB 0.31 0.01 17.0763 -933.216 -17.0763 17.0763 0.51 0.00238059 0.00225121 0.161867 0.152888 -1 -1 -1 -1 38 9038 38 1.21132e+07 3.32735e+06 614590. 2400.74 6.60 0.921446 0.844635 23696 123034 -1 7156 21 2451 5027 1039467 341839 18.1068 18.1068 -1021.94 -18.1068 0 0 780512. 3048.87 0.18 0.32 0.11 -1 -1 0.18 0.111255 0.102688 0.007306 0.3288 0.0194 0.6518 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 412.25 vpr 459.94 MiB -1 -1 83.91 345680 123 55.18 -1 -1 79452 -1 117364 1366 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 470976 114 102 21994 21904 1 11836 1635 50 50 2500 memory auto 154.7 MiB 20.14 157807 1070343 385976 662554 21813 459.9 MiB 27.15 0.21 79.4041 -53458.1 -79.4041 79.4041 20.21 0.0604698 0.0528011 7.69778 6.42684 -1 -1 -1 -1 94 240754 50 1.47946e+08 1.0145e+08 1.55181e+07 6207.23 125.92 26.5625 22.0155 341268 3271592 -1 215929 21 44770 168610 10181079 1913380 79.6681 79.6681 -67309 -79.6681 -34.1184 -0.295467 1.95446e+07 7817.85 5.86 5.76 2.89 -1 -1 5.86 3.26586 2.8046 0.08167 0.4293 0.0115 0.5592 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkDelayWorker32B.v common 90.48 vpr 331.86 MiB -1 -1 18.16 125044 5 3.21 -1 -1 56032 -1 73368 460 506 47 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 339828 506 553 3055 3608 1 2790 1566 50 50 2500 memory auto 46.0 MiB 4.79 16153 1137816 548528 407688 181600 331.9 MiB 5.44 0.07 6.67096 -2020.14 -6.67096 6.67096 19.12 0.0225934 0.0204156 2.93437 2.63134 -1 -1 -1 -1 38 23317 18 1.47946e+08 5.05479e+07 6.86584e+06 2746.33 16.87 8.18989 7.41168 251304 1421084 -1 22431 17 3841 4967 1023796 259831 7.09403 7.09403 -2394.32 -7.09403 -1.60806 -0.199574 8.69095e+06 3476.38 2.76 1.13 1.19 -1 -1 2.76 0.934502 0.861192 0.1726 0.1419 0.03943 0.8187 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkPktMerge.v common 21.17 vpr 71.31 MiB -1 -1 1.27 25292 2 0.14 -1 -1 33632 -1 60032 26 311 15 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 73020 311 156 972 1128 1 953 508 28 28 784 memory auto 28.8 MiB 0.46 9244 197030 68488 118013 10529 71.3 MiB 1.14 0.02 4.08264 -4469.06 -4.08264 4.08264 1.88 0.00555662 0.00492709 0.564647 0.499581 -1 -1 -1 -1 36 15359 25 4.25198e+07 9.62124e+06 1.94918e+06 2486.20 9.68 2.58077 2.28028 74338 387760 -1 14127 14 3001 3471 707329 200421 4.39536 4.39536 -4930.06 -4.39536 -23.3965 -0.340786 2.40571e+06 3068.51 0.65 0.37 0.32 -1 -1 0.65 0.203975 0.183729 0.08358 0.1547 0.01721 0.828 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkSMAdapter4B.v common 25.81 vpr 75.85 MiB -1 -1 8.75 54500 7 2.29 -1 -1 39580 -1 59092 155 193 5 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 77668 193 205 2234 2439 1 1177 558 20 20 400 memory auto 35.7 MiB 1.09 9343 230158 76067 129187 24904 75.8 MiB 1.66 0.02 4.77105 -2950.24 -4.77105 4.77105 0.85 0.00679034 0.00613812 0.712263 0.639828 -1 -1 -1 -1 48 16951 19 2.07112e+07 1.10936e+07 1.23055e+06 3076.38 4.06 1.80116 1.60396 40448 245963 -1 14947 15 4199 10676 555153 128354 5.33264 5.33264 -3131.09 -5.33264 -6.85654 -0.29768 1.57502e+06 3937.55 0.37 0.39 0.21 -1 -1 0.37 0.26107 0.236959 0.029 0.2155 0.0258 0.7587 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml or1200.v common 59.82 vpr 99.94 MiB -1 -1 7.76 67916 27 4.04 -1 -1 38688 -1 61160 230 385 2 1 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 102336 385 394 3906 4237 1 2371 1012 27 27 729 io auto 45.8 MiB 2.74 31818 549436 207916 318095 23425 88.1 MiB 5.14 0.06 13.6891 -13601.7 -13.6891 13.6891 1.80 0.015847 0.01475 2.00047 1.83115 -1 -1 -1 -1 74 52043 45 3.93038e+07 1.38876e+07 3.51708e+06 4824.52 23.64 7.06874 6.48735 88217 717307 -1 45806 15 11143 38956 2327403 423270 13.7426 13.7426 -14238.9 -13.7426 0 0 4.41327e+06 6053.86 1.15 1.18 0.59 -1 -1 1.15 0.620583 0.577856 0.02262 0.455 0.02732 0.5177 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml raygentop.v common 26.77 vpr 77.02 MiB -1 -1 6.02 45696 8 1.03 -1 -1 37700 -1 60816 132 235 1 6 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 78872 235 305 2600 2761 1 1513 679 19 19 361 io auto 36.9 MiB 2.30 12446 257217 87938 156711 12568 77.0 MiB 2.00 0.03 5.21052 -2695.25 -5.21052 5.21052 0.78 0.00833798 0.00759325 0.784503 0.720451 -1 -1 -1 -1 56 23724 29 1.72706e+07 1.0038e+07 1.27879e+06 3542.35 6.44 2.59347 2.36584 38159 255829 -1 21061 16 6083 16778 1518471 388985 5.74403 5.74403 -2918.04 -5.74403 -0.678968 -0.063748 1.63234e+06 4521.70 0.37 0.64 0.21 -1 -1 0.37 0.322829 0.298228 0.02425 0.4068 0.02614 0.567 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml sha.v common 19.90 vpr 78.46 MiB -1 -1 4.15 47060 21 2.26 -1 -1 40792 -1 45652 149 38 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 80344 38 36 2570 2606 1 1067 223 17 17 289 clb auto 37.6 MiB 1.11 9186 42135 10514 28822 2799 78.5 MiB 0.87 0.01 14.489 -2637.24 -14.489 14.489 0.59 0.00570235 0.00505996 0.410899 0.362544 -1 -1 -1 -1 48 15409 28 1.34605e+07 8.03021e+06 864508. 2991.38 3.30 1.52379 1.3128 28519 171069 -1 13295 15 4245 12043 362530 70167 15.0234 15.0234 -2942.08 -15.0234 0 0 1.10659e+06 3829.03 0.25 0.37 0.14 -1 -1 0.25 0.250361 0.222953 0.006573 0.364 0.03019 0.6058 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mcml.v common 5120.01 vpr 1.66 GiB -1 -1 669.92 1429688 64 3238.48 -1 -1 348532 -1 316988 6755 36 159 27 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 1745216 36 356 125423 124208 1 35759 7333 98 98 9604 clb auto 669.3 MiB 69.08 472751 9976873 4211332 5688117 77424 1704.3 MiB 166.62 1.28 62.922 -266875 -62.922 62.922 79.42 0.238495 0.197947 34.8953 29.1342 -1 -1 -1 -1 84 619524 38 5.9175e+08 4.61843e+08 5.50586e+07 5732.88 291.80 112.255 92.7458 1265060 11766760 -1 588054 18 120512 381178 21916553 4319201 63.8888 63.8888 -334021 -63.8888 0 0 6.99411e+07 7282.50 23.74 17.67 10.44 -1 -1 23.74 11.6929 10.0211 0.2761 0.3715 0.01425 0.6143 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 98.48 parmys 238.48 MiB -1 -1 62.65 244200 13 8.25 -1 -1 47788 -1 49624 326 257 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 95576 257 32 5008 5040 1 2954 615 23 23 529 clb auto 50.5 MiB 2.76 20267 220191 65143 146065 8983 93.3 MiB 2.97 0.04 8.82032 -3904.7 -8.82032 8.82032 0.54 0.0109643 0.0098333 1.02884 0.902188 -1 -1 -1 -1 56 33645 24 2.70004e+07 1.75694e+07 1.92373e+06 3636.54 6.22 3.27588 2.85668 56706 387443 -1 30010 16 11550 36095 972511 199422 9.40635 9.40635 -3964.62 -9.40635 0 0 2.45466e+06 4640.18 0.09 0.82 0.33 -1 -1 0.09 0.508209 0.459137 0.01648 0.4272 0.03377 0.5391 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml blob_merge.v common 94.21 parmys 306.69 MiB -1 -1 21.16 314052 7 13.24 -1 -1 60844 -1 50612 549 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 136868 36 100 6778 6878 1 3144 685 30 30 900 clb auto 67.3 MiB 3.50 42466 287395 83633 184471 19291 113.8 MiB 5.19 0.06 5.74861 -2247.23 -5.74861 5.74861 1.03 0.0222208 0.0200972 1.955 1.66503 -1 -1 -1 -1 66 68658 45 4.8774e+07 2.95878e+07 3.99156e+06 4435.07 27.65 7.52931 6.32406 104036 803752 -1 60922 16 14883 67597 2789200 373708 5.76735 5.76735 -2377.78 -5.76735 0 0 4.95347e+06 5503.86 0.20 1.71 0.69 -1 -1 0.20 0.908064 0.803825 0.02605 0.351 0.06511 0.5839 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml boundtop.v common 24.14 vpr 68.57 MiB -1 -1 17.73 31664 4 0.24 -1 -1 34328 -1 55248 53 195 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70220 195 193 1087 1280 1 610 442 15 15 225 io auto 28.4 MiB 0.31 3111 131716 33861 86359 11496 68.6 MiB 0.67 0.01 2.49928 -1087.72 -2.49928 2.49928 0.23 0.00362287 0.00338275 0.298018 0.277768 -1 -1 -1 -1 40 5849 18 1.03862e+07 3.40438e+06 568276. 2525.67 1.78 1.09849 1.00863 21262 112936 -1 5416 11 1616 2529 155491 45590 2.72859 2.72859 -1209.59 -2.72859 -0.959406 -0.246 712852. 3168.23 0.02 0.09 0.07 -1 -1 0.02 0.0607763 0.057325 0.01365 0.3769 0.05606 0.567 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.23 vpr 63.89 MiB -1 -1 0.49 18176 3 0.10 -1 -1 33044 -1 53092 68 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65428 99 130 344 474 1 226 298 12 12 144 clb auto 24.1 MiB 0.08 678 66963 19395 33485 14083 63.9 MiB 0.23 0.00 1.86362 -122.41 -1.86362 1.86362 0.14 0.00130445 0.00123497 0.0907109 0.085881 -1 -1 -1 -1 52 1254 11 5.66058e+06 4.21279e+06 419432. 2912.72 0.65 0.338628 0.310581 13810 82561 -1 1175 7 368 599 29659 8862 1.9806 1.9806 -135.825 -1.9806 -0.309826 -0.0782318 551878. 3832.49 0.02 0.04 0.08 -1 -1 0.02 0.0250196 0.0231993 0.01031 0.263 0.08354 0.6535 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 10.16 vpr 68.16 MiB -1 -1 0.74 23332 15 0.35 -1 -1 34092 -1 54824 39 162 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69796 162 96 1009 950 1 709 302 16 16 256 mult_36 auto 28.2 MiB 0.19 5587 92394 30880 53838 7676 68.2 MiB 0.69 0.01 21.0975 -1536.06 -21.0975 21.0975 0.26 0.00337966 0.00317219 0.323022 0.303359 -1 -1 -1 -1 56 11812 30 1.21132e+07 4.08187e+06 870502. 3400.40 4.17 1.16452 1.07293 26504 172068 -1 9609 16 2935 5927 775463 239759 22.3005 22.3005 -1636.88 -22.3005 0 0 1.11200e+06 4343.75 0.04 0.29 0.15 -1 -1 0.04 0.13141 0.122082 0.007854 0.3765 0.01734 0.6061 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq2.v common 7.88 vpr 65.00 MiB -1 -1 0.61 21868 16 0.27 -1 -1 33428 -1 53744 25 66 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66560 66 96 616 557 1 415 192 16 16 256 mult_36 auto 25.5 MiB 0.17 3625 36690 9459 22826 4405 65.0 MiB 0.32 0.01 17.203 -935.064 -17.203 17.203 0.26 0.00236496 0.0022302 0.166486 0.157037 -1 -1 -1 -1 40 8373 37 1.21132e+07 3.32735e+06 642278. 2508.90 3.53 0.766237 0.703647 23952 127161 -1 7217 17 2534 5167 951988 292757 18.0101 18.0101 -1019.64 -18.0101 0 0 805949. 3148.24 0.02 0.19 0.08 -1 -1 0.02 0.05209 0.0486566 0.007411 0.3353 0.01978 0.6449 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 440.60 vpr 461.59 MiB -1 -1 84.00 349248 123 64.46 -1 -1 78572 -1 117272 1375 114 45 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 472672 114 102 21994 21904 1 11802 1644 50 50 2500 memory auto 155.4 MiB 20.55 160790 1049136 374899 655277 18960 461.6 MiB 26.29 0.22 78.4871 -53143.2 -78.4871 78.4871 9.75 0.0621978 0.0545143 7.35439 6.13837 -1 -1 -1 -1 94 240662 29 1.47946e+08 1.01935e+08 1.55181e+07 6207.23 162.29 28.9908 23.8912 341268 3271592 -1 217509 21 44132 167614 9994098 1867129 81.2261 81.2261 -64082.4 -81.2261 -12.841 -0.29436 1.95446e+07 7817.85 0.86 6.13 3.06 -1 -1 0.86 3.42933 2.93557 0.08134 0.4302 0.01139 0.5585 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkDelayWorker32B.v common 70.13 vpr 332.00 MiB -1 -1 18.29 128412 5 3.25 -1 -1 56812 -1 73340 470 506 47 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 339964 506 553 3055 3608 1 2790 1576 50 50 2500 memory auto 45.7 MiB 4.81 15429 1147451 561958 401565 183928 332.0 MiB 5.51 0.07 7.14518 -1819.3 -7.14518 7.14518 9.87 0.0227758 0.020582 2.93349 2.63053 -1 -1 -1 -1 38 22365 17 1.47946e+08 5.10868e+07 6.86584e+06 2746.33 11.85 8.32526 7.54939 251304 1421084 -1 21433 18 3916 5150 995348 263030 7.69019 7.69019 -2049.85 -7.69019 -5.04137 -0.293253 8.69095e+06 3476.38 0.41 1.18 1.23 -1 -1 0.41 0.985049 0.907039 0.1604 0.1419 0.03923 0.8189 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkPktMerge.v common 13.31 vpr 71.36 MiB -1 -1 1.63 25356 2 0.13 -1 -1 33796 -1 60140 29 311 15 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73068 311 156 972 1128 1 953 511 28 28 784 memory auto 29.5 MiB 0.51 9032 192459 70202 112997 9260 71.4 MiB 1.14 0.02 4.00429 -4585.85 -4.00429 4.00429 0.90 0.00569369 0.00505114 0.564395 0.499447 -1 -1 -1 -1 36 14754 13 4.25198e+07 9.78293e+06 1.94918e+06 2486.20 3.93 1.82677 1.61944 74338 387760 -1 13894 15 2784 3327 698932 209763 4.39426 4.39426 -5070.29 -4.39426 -12.8598 -0.360359 2.40571e+06 3068.51 0.10 0.36 0.33 -1 -1 0.10 0.20904 0.188673 0.0833 0.1522 0.01727 0.8306 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkSMAdapter4B.v common 28.03 vpr 76.09 MiB -1 -1 9.24 55960 7 2.30 -1 -1 37416 -1 59040 157 193 5 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77920 193 205 2234 2439 1 1179 560 20 20 400 memory auto 35.6 MiB 1.10 9842 228953 80249 124571 24133 76.1 MiB 1.72 0.02 5.08439 -2926.08 -5.08439 5.08439 0.43 0.00685575 0.00620383 0.738776 0.665656 -1 -1 -1 -1 48 17744 33 2.07112e+07 1.12014e+07 1.23055e+06 3076.38 6.37 2.5483 2.26983 40448 245963 -1 15329 16 4566 11562 627458 139494 5.47739 5.47739 -3135.16 -5.47739 -11.584 -0.360359 1.57502e+06 3937.55 0.06 0.44 0.22 -1 -1 0.06 0.280677 0.254763 0.02856 0.2221 0.02552 0.7523 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml or1200.v common 63.07 vpr 106.00 MiB -1 -1 7.93 68908 27 4.13 -1 -1 38580 -1 61144 234 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 108548 385 394 3906 4237 1 2373 1016 27 27 729 io auto 46.0 MiB 2.92 31525 572776 227317 322407 23052 88.3 MiB 5.07 0.06 14.4133 -13461.7 -14.4133 14.4133 0.83 0.0160926 0.0150256 1.89286 1.74364 -1 -1 -1 -1 78 51645 44 3.93038e+07 1.41032e+07 3.65949e+06 5019.88 29.17 7.69214 7.06424 90401 760319 -1 44396 14 10279 35511 1944665 349659 14.8103 14.8103 -13960.4 -14.8103 0 0 4.63207e+06 6354.00 0.16 1.07 0.66 -1 -1 0.16 0.591618 0.549921 0.02224 0.4637 0.02666 0.5097 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml raygentop.v common 25.27 vpr 77.84 MiB -1 -1 6.25 46808 8 0.90 -1 -1 37872 -1 60796 133 235 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79708 235 305 2600 2761 1 1501 680 19 19 361 io auto 36.8 MiB 2.09 12500 263712 91208 158948 13556 77.8 MiB 1.99 0.03 5.38636 -2731.89 -5.38636 5.38636 0.39 0.00825643 0.00765916 0.774605 0.712384 -1 -1 -1 -1 56 23995 47 1.72706e+07 1.00919e+07 1.27879e+06 3542.35 6.04 2.65451 2.42437 38159 255829 -1 20300 15 5879 16147 1393547 361528 5.87661 5.87661 -3009.11 -5.87661 -1.26427 -0.201639 1.63234e+06 4521.70 0.07 0.66 0.22 -1 -1 0.07 0.333764 0.30935 0.02386 0.4083 0.02598 0.5657 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml sha.v common 19.44 vpr 78.34 MiB -1 -1 4.20 47476 21 2.24 -1 -1 40644 -1 45784 147 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80220 38 36 2570 2606 1 1050 221 17 17 289 clb auto 37.3 MiB 1.10 9478 36239 7889 25786 2564 78.3 MiB 0.76 0.01 14.6977 -2591.44 -14.6977 14.6977 0.30 0.00627054 0.00560905 0.378906 0.335347 -1 -1 -1 -1 46 16543 25 1.34605e+07 7.92242e+06 830882. 2875.03 3.43 1.51759 1.31374 28231 166010 -1 13884 15 4024 11917 367875 68444 15.3347 15.3347 -2866.69 -15.3347 0 0 1.06831e+06 3696.59 0.04 0.39 0.14 -1 -1 0.04 0.261218 0.233045 0.006476 0.3635 0.02972 0.6068 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mcml.v common 5304.23 vpr 1.66 GiB -1 -1 692.05 1442556 64 3350.31 -1 -1 347144 -1 317188 6851 36 159 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1741944 36 356 125423 124208 1 34881 7429 98 98 9604 clb auto 660.2 MiB 73.61 461903 10223866 4318975 5823833 81058 1701.1 MiB 186.47 1.32 63.3139 -299631 -63.3139 63.3139 39.62 0.235404 0.202231 35.8753 30.2278 -1 -1 -1 -1 80 612389 32 5.9175e+08 4.67016e+08 5.28775e+07 5505.77 350.18 119.658 98.779 1236252 11146124 -1 575490 18 116226 373166 21552241 4233065 64.9427 64.9427 -370561 -64.9427 0 0 6.66202e+07 6936.71 3.07 14.93 8.56 -1 -1 3.07 9.99565 8.64031 0.27 0.3629 0.01392 0.6231 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt index 829c3da90f8..afc7702ee1c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt @@ -1,21 +1,21 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 4.75 vpr 64.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66040 14 8 926 934 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6815 89.2 MiB 2.28 0.03 7.83344 -342.752 -7.83344 7.83344 0.92 0.0100177 0.00886659 0.857361 0.741308 92 46721 44 1.74617e+07 1.65455e+07 2.37849e+06 5946.23 18.28 3.97352 3.38216 54288 506964 -1 42503 16 14653 63396 2356990 367690 8.12752 8.12752 -355.073 -8.12752 0 0 3.01539e+06 7538.48 0.69 1.19 0.43 -1 -1 0.69 0.511744 0.462774 -k6_frac_N10_40nm.xml des.pre-vpr.blif common 7.12 vpr 62.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 51 256 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64448 256 245 954 1199 0 578 552 18 18 324 io auto 23.8 MiB 0.33 4966 131806 34568 89483 7755 62.9 MiB 0.48 0.01 3.70962 -712.314 -3.70962 nan 0.74 0.00414551 0.00395387 0.186169 0.176197 36 9086 34 1.37969e+07 2.74859e+06 824466. 2544.65 3.31 1.24102 1.16598 31748 166456 -1 8145 16 2076 4578 247499 55677 4.28288 nan -799.816 -4.28288 0 0 1.01518e+06 3133.28 0.26 0.23 0.13 -1 -1 0.26 0.156872 0.14849 -k6_frac_N10_40nm.xml diffeq.pre-vpr.blif common 3.87 vpr 64.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 65 64 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65904 64 39 1371 1410 1 542 168 11 11 121 clb auto 25.2 MiB 0.48 3387 16373 2957 12425 991 64.4 MiB 0.23 0.01 5.33717 -1012.06 -5.33717 5.33717 0.22 0.00291587 0.00263997 0.121115 0.109984 46 5978 20 4.36541e+06 3.50311e+06 343362. 2837.71 1.41 0.597762 0.523358 12051 69045 -1 5146 15 1964 5478 158754 33013 5.81148 5.81148 -1104.11 -5.81148 0 0 440296. 3638.81 0.09 0.18 0.06 -1 -1 0.09 0.122268 0.110374 -k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 10.46 vpr 65.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70 229 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on 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0.356682 -k6_frac_N10_40nm.xml s298.pre-vpr.blif common 4.12 vpr 62.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 4 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63740 4 6 726 732 1 398 73 10 10 100 clb auto 23.2 MiB 0.75 3666 3417 417 2860 140 62.2 MiB 0.11 0.00 6.02354 -48.3456 -6.02354 6.02354 0.18 0.00201694 0.00183365 0.0626085 0.0572741 50 5820 31 3.44922e+06 3.39532e+06 295697. 2956.97 1.63 0.53661 0.462064 10016 58256 -1 5144 15 2315 9199 280618 50632 6.26562 6.26562 -52.0008 -6.26562 0 0 379824. 3798.24 0.08 0.17 0.05 -1 -1 0.08 0.0972111 0.0881692 -k6_frac_N10_40nm.xml s38417.pre-vpr.blif common 15.85 vpr 87.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 249 29 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89280 29 106 4782 4888 1 2019 384 18 18 324 clb auto 44.7 MiB 2.35 13216 107799 27485 70375 9939 87.2 MiB 1.53 0.02 5.18654 -3584.37 -5.18654 5.18654 0.72 0.00820093 0.00716198 0.7235 0.630423 52 21960 50 1.37969e+07 1.34196e+07 1.12378e+06 3468.47 6.68 2.99225 2.56134 35300 236012 -1 19626 15 6767 19136 685005 132226 5.32162 5.32162 -3691.42 -5.32162 0 0 1.48031e+06 4568.86 0.34 0.58 0.19 -1 -1 0.34 0.406682 0.365814 -k6_frac_N10_40nm.xml s38584.1.pre-vpr.blif common 16.40 vpr 86.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 226 38 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88452 38 304 4422 4726 1 2052 568 18 18 324 clb auto 43.6 MiB 2.25 13975 176893 52423 113746 10724 86.4 MiB 1.91 0.03 4.9343 -2945.33 -4.9343 4.9343 0.73 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-k6_frac_N10_40nm.xml spla.pre-vpr.blif common 16.32 vpr 76.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 216 16 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78668 16 46 2232 2278 0 1170 278 17 17 289 clb auto 35.3 MiB 2.69 15884 45628 10574 32142 2912 76.8 MiB 0.90 0.02 5.95671 -204.452 -5.95671 nan 0.66 0.00655055 0.00559031 0.393901 0.343227 74 25546 32 1.21262e+07 1.16411e+07 1.39325e+06 4820.95 7.80 2.00641 1.71174 35379 286977 -1 24647 19 7675 42760 1737904 249467 6.14143 nan -217.643 -6.14143 0 0 1.74421e+06 6035.33 0.38 0.81 0.26 -1 -1 0.38 0.340644 0.303738 -k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 3.98 vpr 65.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 61 52 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66596 52 122 1461 1583 1 474 235 10 10 100 clb auto 26.0 MiB 0.54 2490 35711 8852 25144 1715 65.0 MiB 0.32 0.01 4.73051 -1125.66 -4.73051 4.73051 0.18 0.00299119 0.00271471 0.1633 0.148553 46 4691 25 3.44922e+06 3.28753e+06 276332. 2763.32 1.35 0.707889 0.622607 9816 55112 -1 4036 15 1411 3526 118896 27892 5.08546 5.08546 -1209.63 -5.08546 0 0 354105. 3541.05 0.07 0.15 0.04 -1 -1 0.07 0.117472 0.106373 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 4.59 vpr 64.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65868 14 8 926 934 0 490 100 11 11 121 clb auto 24.6 MiB 0.91 4639 5668 847 4419 402 64.3 MiB 0.16 0.01 4.54815 -31.8355 -4.54815 nan 0.11 0.00249412 0.00221472 0.083083 0.0754962 -1 -1 -1 -1 48 7214 49 4.36541e+06 4.20373e+06 357017. 2950.55 2.04 0.729015 0.623693 12171 71069 -1 6577 19 3324 15359 408061 81134 4.87162 nan -34.7178 -4.87162 0 0 455885. 3767.64 0.01 0.26 0.06 -1 -1 0.01 0.140142 0.125126 + k6_frac_N10_40nm.xml apex2.pre-vpr.blif common 6.95 vpr 65.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 103 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67448 38 3 1113 1116 0 662 144 13 13 169 clb auto 26.3 MiB 1.53 7442 11831 1926 8689 1216 65.9 MiB 0.29 0.01 5.59822 -16.3249 -5.59822 nan 0.16 0.00306728 0.00270237 0.126883 0.113876 -1 -1 -1 -1 64 12841 39 6.52117e+06 5.55108e+06 687872. 4070.25 3.20 0.976549 0.840439 19211 138678 -1 11425 17 4712 23613 728373 121323 5.82519 nan -16.8677 -5.82519 0 0 856291. 5066.81 0.03 0.36 0.11 -1 -1 0.03 0.160453 0.144609 + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.91 vpr 64.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65892 9 19 897 916 0 556 110 12 12 144 clb auto 24.8 MiB 1.46 6252 7474 1266 5720 488 64.3 MiB 0.20 0.01 4.74237 -77.8307 -4.74237 nan 0.14 0.00271417 0.00242922 0.0925149 0.0843887 -1 -1 -1 -1 62 10739 47 5.3894e+06 4.41931e+06 554770. 3852.57 2.59 0.760237 0.654515 15940 110000 -1 9728 17 4391 21118 675575 120995 5.20821 nan -84.4166 -5.20821 0 0 687181. 4772.09 0.02 0.31 0.09 -1 -1 0.02 0.1315 0.118528 + k6_frac_N10_40nm.xml bigkey.pre-vpr.blif common 6.12 vpr 65.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67388 229 197 1364 1561 1 539 497 16 16 256 io auto 26.1 MiB 0.83 4504 148022 42306 97632 8084 65.8 MiB 0.82 0.01 2.97254 -656.061 -2.97254 2.97254 0.27 0.00439332 0.00408702 0.35847 0.333653 -1 -1 -1 -1 36 7822 26 1.05632e+07 3.82647e+06 638738. 2495.07 2.60 1.40665 1.28851 24820 128426 -1 7098 11 1611 3987 187232 44731 3.15649 3.15649 -738.429 -3.15649 0 0 786978. 3074.13 0.03 0.19 0.08 -1 -1 0.03 0.132772 0.123936 + k6_frac_N10_40nm.xml clma.pre-vpr.blif common 28.51 vpr 89.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 316 62 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 91500 62 82 3672 3754 1 2348 460 20 20 400 clb auto 45.2 MiB 3.83 29602 121160 32274 82250 6636 89.4 MiB 2.46 0.04 7.97523 -360.045 -7.97523 7.97523 0.44 0.0115817 0.00968577 0.858962 0.732885 -1 -1 -1 -1 92 48575 45 1.74617e+07 1.70305e+07 2.37849e+06 5946.23 16.44 4.93267 4.15445 54288 506964 -1 43403 17 15069 65645 2357098 375873 8.16272 8.16272 -366.296 -8.16272 0 0 3.01539e+06 7538.48 0.10 1.28 0.42 -1 -1 0.10 0.57067 0.510695 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 5.68 vpr 62.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 51 256 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64476 256 245 954 1199 0 578 552 18 18 324 io auto 23.6 MiB 0.23 5523 134069 36344 90454 7271 63.0 MiB 0.66 0.01 3.66288 -710.092 -3.66288 nan 0.35 0.00435575 0.00415707 0.270866 0.258189 -1 -1 -1 -1 36 9376 41 1.37969e+07 2.74859e+06 824466. 2544.65 2.93 1.43298 1.34768 31748 166456 -1 8164 13 2250 4803 238712 56339 4.07339 nan -791.038 -4.07339 0 0 1.01518e+06 3133.28 0.04 0.21 0.14 -1 -1 0.04 0.139599 0.132291 + k6_frac_N10_40nm.xml diffeq.pre-vpr.blif common 3.71 vpr 64.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66072 64 39 1371 1410 1 541 167 10 10 100 clb auto 25.0 MiB 0.50 3623 18986 4100 13819 1067 64.5 MiB 0.29 0.01 5.32461 -1004.72 -5.32461 5.32461 0.09 0.00297013 0.00265425 0.142744 0.129291 -1 -1 -1 -1 50 5495 30 3.44922e+06 3.44922e+06 295697. 2956.97 1.53 0.822979 0.71402 10016 58256 -1 4877 17 1881 5375 141590 30815 5.49357 5.49357 -1059.83 -5.49357 0 0 379824. 3798.24 0.01 0.18 0.05 -1 -1 0.01 0.130986 0.117787 + k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 6.57 vpr 65.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66956 229 197 1362 1559 1 570 496 16 16 256 io auto 25.8 MiB 0.92 5066 137836 36889 92766 8181 65.4 MiB 0.78 0.01 2.91431 -671.379 -2.91431 2.91431 0.27 0.00438808 0.00409538 0.327876 0.305574 -1 -1 -1 -1 36 8862 27 1.05632e+07 3.77258e+06 638738. 2495.07 2.96 1.41434 1.29776 24820 128426 -1 7675 13 1986 5211 265646 63312 3.18697 3.18697 -739.19 -3.18697 0 0 786978. 3074.13 0.03 0.23 0.10 -1 -1 0.03 0.155656 0.14507 + k6_frac_N10_40nm.xml elliptic.pre-vpr.blif common 12.40 vpr 77.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 171 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79424 131 114 3421 3535 1 1164 416 16 16 256 clb auto 36.2 MiB 3.40 10474 95088 26501 63930 4657 77.6 MiB 1.19 0.02 7.51043 -4391.12 -7.51043 7.51043 0.26 0.00746347 0.00670247 0.527413 0.462699 -1 -1 -1 -1 56 18313 31 1.05632e+07 9.21587e+06 942187. 3680.42 4.59 2.05209 1.78067 28136 192436 -1 15484 16 5183 22017 710369 128360 7.51944 7.51944 -4543.65 -7.51944 0 0 1.20185e+06 4694.72 0.04 0.55 0.15 -1 -1 0.04 0.349204 0.315387 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 24.75 vpr 82.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 285 10 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83992 10 10 2659 2669 0 1401 305 19 19 361 clb auto 39.3 MiB 4.57 26220 51605 13492 36245 1868 82.0 MiB 1.25 0.02 6.59302 -61.9652 -6.59302 nan 0.39 0.00827542 0.00731978 0.484089 0.41329 -1 -1 -1 -1 90 42829 31 1.55754e+07 1.53598e+07 2.09179e+06 5794.43 14.00 3.32602 2.79995 48131 439069 -1 39158 17 9518 58062 2365838 328796 6.83753 nan -64.8858 -6.83753 0 0 2.60973e+06 7229.16 0.08 1.03 0.29 -1 -1 0.08 0.41705 0.373851 + k6_frac_N10_40nm.xml ex5p.pre-vpr.blif common 3.76 vpr 63.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 8 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64588 8 63 761 824 0 435 134 10 10 100 clb auto 23.7 MiB 0.68 3999 11420 2063 8488 869 63.1 MiB 0.20 0.01 3.77984 -169.82 -3.77984 nan 0.09 0.00233479 0.00210219 0.0905659 0.0824737 -1 -1 -1 -1 58 6565 28 3.44922e+06 3.39532e+06 342720. 3427.20 1.56 0.557203 0.48462 10608 68480 -1 5918 16 2541 10577 323005 63220 4.22288 nan -188.35 -4.22288 0 0 435638. 4356.38 0.01 0.19 0.05 -1 -1 0.01 0.102623 0.0927145 + k6_frac_N10_40nm.xml frisc.pre-vpr.blif common 13.58 vpr 77.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 167 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79220 20 116 3175 3291 1 1338 303 15 15 225 clb auto 36.1 MiB 3.06 14602 62340 15718 42273 4349 77.4 MiB 1.17 0.02 8.56273 -4519.63 -8.56273 8.56273 0.22 0.00757247 0.0068348 0.522644 0.463063 -1 -1 -1 -1 80 24018 43 9.10809e+06 9.0003e+06 1.12687e+06 5008.33 6.06 2.41987 2.10801 28171 234221 -1 21050 15 6703 26493 1041429 176822 9.09101 9.09101 -4756.62 -9.09101 0 0 1.41774e+06 6301.08 0.04 0.63 0.19 -1 -1 0.04 0.342199 0.310175 + k6_frac_N10_40nm.xml misex3.pre-vpr.blif common 4.84 vpr 63.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65224 14 14 828 842 0 475 99 11 11 121 clb auto 24.1 MiB 0.91 4532 5343 748 4219 376 63.7 MiB 0.15 0.01 4.39029 -57.6027 -4.39029 nan 0.11 0.00227799 0.00202987 0.0718845 0.0655562 -1 -1 -1 -1 52 7728 41 4.36541e+06 3.82647e+06 379421. 3135.71 2.05 0.703343 0.603899 12531 77429 -1 6634 16 3040 13763 383785 71279 4.69105 nan -60.7462 -4.69105 0 0 499620. 4129.09 0.01 0.15 0.04 -1 -1 0.01 0.0814211 0.0751261 + k6_frac_N10_40nm.xml pdc.pre-vpr.blif common 26.16 vpr 82.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 272 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84416 16 40 2839 2879 0 1511 328 19 19 361 clb auto 39.8 MiB 3.52 23598 55698 13292 40268 2138 82.4 MiB 1.28 0.02 6.48626 -238.484 -6.48626 nan 0.44 0.00886302 0.00735171 0.491212 0.417579 -1 -1 -1 -1 82 38584 40 1.55754e+07 1.46592e+07 1.91630e+06 5308.30 16.27 3.50905 2.95866 46331 403357 -1 35281 17 9680 52085 1891572 294823 6.8403 nan -243.508 -6.8403 0 0 2.40187e+06 6653.38 0.08 1.01 0.33 -1 -1 0.08 0.437668 0.392311 + k6_frac_N10_40nm.xml s298.pre-vpr.blif common 3.15 vpr 62.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 4 6 726 732 1 395 74 10 10 100 clb auto 23.4 MiB 0.73 3639 2709 340 2252 117 62.8 MiB 0.10 0.00 6.02711 -48.0055 -6.02711 6.02711 0.09 0.00207648 0.0018638 0.0538424 0.0494959 -1 -1 -1 -1 50 5470 24 3.44922e+06 3.44922e+06 295697. 2956.97 1.28 0.507359 0.443613 10016 58256 -1 4992 17 2195 9283 271197 50082 6.42868 6.42868 -51.2874 -6.42868 0 0 379824. 3798.24 0.01 0.12 0.03 -1 -1 0.01 0.0746748 0.0694149 + k6_frac_N10_40nm.xml s38417.pre-vpr.blif common 13.59 vpr 87.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 250 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 89136 29 106 4782 4888 1 1993 385 18 18 324 clb auto 44.4 MiB 2.46 13385 89985 21640 60579 7766 87.0 MiB 1.52 0.02 5.22969 -3570.14 -5.22969 5.22969 0.34 0.00938818 0.00831247 0.681949 0.588191 -1 -1 -1 -1 50 21612 42 1.37969e+07 1.34735e+07 1.08879e+06 3360.46 5.45 2.95573 2.52337 34656 222912 -1 19075 14 7130 20879 621675 127526 5.31212 5.31212 -3691.5 -5.31212 0 0 1.40279e+06 4329.61 0.05 0.59 0.17 -1 -1 0.05 0.416139 0.374046 + k6_frac_N10_40nm.xml s38584.1.pre-vpr.blif common 13.45 vpr 85.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 228 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 87964 38 304 4422 4726 1 1994 570 18 18 324 clb auto 43.2 MiB 2.50 13819 172996 49998 111442 11556 85.9 MiB 2.01 0.03 4.76683 -2916.88 -4.76683 4.76683 0.35 0.00939228 0.00841165 0.819185 0.712738 -1 -1 -1 -1 58 23055 36 1.37969e+07 1.22878e+07 1.26150e+06 3893.53 4.75 2.90623 2.51915 36592 261672 -1 20398 14 6469 17425 591858 126037 4.97859 4.97859 -3048.53 -4.97859 0 0 1.60510e+06 4954.00 0.05 0.63 0.21 -1 -1 0.05 0.450883 0.410575 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.73 vpr 65.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66644 41 35 1006 1041 0 604 160 12 12 144 clb auto 25.4 MiB 1.22 6515 13180 2173 9685 1322 65.1 MiB 0.26 0.01 4.58553 -134.055 -4.58553 nan 0.14 0.00299227 0.00267516 0.112623 0.102342 -1 -1 -1 -1 64 10841 30 5.3894e+06 4.5271e+06 575115. 3993.85 2.53 0.863068 0.745904 16224 115365 -1 9534 17 3641 17204 511035 92223 4.88481 nan -140.076 -4.88481 0 0 716128. 4973.11 0.02 0.28 0.09 -1 -1 0.02 0.142307 0.128311 + k6_frac_N10_40nm.xml spla.pre-vpr.blif common 15.03 vpr 76.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 216 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78680 16 46 2232 2278 0 1170 278 17 17 289 clb auto 35.0 MiB 2.88 16089 42000 9359 30203 2438 76.8 MiB 0.95 0.02 5.95204 -207.143 -5.95204 nan 0.30 0.00775355 0.00661099 0.401796 0.349405 -1 -1 -1 -1 68 27700 45 1.21262e+07 1.16411e+07 1.30851e+06 4527.71 7.55 2.17634 1.8524 34227 265321 -1 23554 19 8023 43603 1540936 228530 6.17174 nan -217.21 -6.17174 0 0 1.61843e+06 5600.10 0.05 0.82 0.21 -1 -1 0.05 0.356964 0.321301 + k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 3.30 vpr 65.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66732 52 122 1461 1583 1 472 237 10 10 100 clb auto 25.8 MiB 0.55 2690 30290 6635 22073 1582 65.2 MiB 0.30 0.01 4.95966 -1122.48 -4.95966 4.95966 0.09 0.00309899 0.0028239 0.143089 0.130468 -1 -1 -1 -1 46 4786 25 3.44922e+06 3.39532e+06 276332. 2763.32 1.07 0.637438 0.562157 9816 55112 -1 4250 13 1489 3922 122560 29939 5.00101 5.00101 -1209.26 -5.00101 0 0 354105. 3541.05 0.01 0.16 0.04 -1 -1 0.01 0.119116 0.108599 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt index 694b1b03602..cc7b62c6a7e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt @@ -1,20 +1,20 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_40nm.xml alu4.pre-vpr.blif common 7.79 vpr 64.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 97 14 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65584 14 8 926 934 0 517 119 12 12 144 clb auto 24.9 MiB 0.59 4978 9171 1462 7157 552 64.0 MiB 0.27 0.01 4.85854 -36.6925 -4.85854 nan 0.40 0.00229013 0.0019463 0.126381 0.111748 -1 -1 -1 -1 52 6841 26 1.8e+06 1.746e+06 452692. 3143.70 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-1 -1 95 9 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65968 9 19 897 916 0 568 123 12 12 144 clb auto 25.0 MiB 0.57 6616 8358 1251 6625 482 64.4 MiB 0.22 0.01 5.18808 -85.4879 -5.18808 nan 0.39 0.00281312 0.0023275 0.0756863 0.0650474 -1 -1 -1 -1 64 10344 32 1.8e+06 1.71e+06 562980. 3909.58 6.98 1.02613 0.882001 13324 112085 -1 9823 21 5176 24280 1089893 157064 5.18521 nan -85.6966 -5.18521 0 0 705288. 4897.83 0.22 0.47 0.11 -1 -1 0.22 0.162583 0.148293 -k6_N10_40nm.xml bigkey.pre-vpr.blif common 12.60 vpr 65.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 94 229 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66928 263 197 1372 1603 1 490 554 17 17 289 io auto 26.0 MiB 0.36 4312 159734 46622 103443 9669 65.4 MiB 1.19 0.03 3.07033 -729.814 -3.07033 3.07033 1.14 0.00415099 0.00372162 0.308823 0.273056 -1 -1 -1 -1 34 7551 23 4.05e+06 1.692e+06 688919. 2383.80 5.72 1.29646 1.16606 21366 134962 -1 7110 17 2315 10686 592079 112425 3.1266 3.1266 -779.621 -3.1266 0 0 845950. 2927.16 0.34 0.43 0.19 -1 -1 0.34 0.207796 0.19268 -k6_N10_40nm.xml clma.pre-vpr.blif common 61.67 vpr 99.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 378 62 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 101448 383 82 3674 4077 1 2351 843 22 22 484 clb auto 44.5 MiB 2.29 30234 398843 147564 198233 53046 88.7 MiB 6.67 0.10 8.68878 -384.052 -8.68878 8.68878 2.69 0.0155276 0.0133229 1.26339 1.07925 -1 -1 -1 -1 82 49771 43 7.2e+06 6.804e+06 2.55950e+06 5288.23 35.48 6.79195 5.74354 51036 532374 -1 43646 25 18197 79309 3810614 487367 8.62407 8.62407 -396.956 -8.62407 0 0 3.19792e+06 6607.28 1.25 2.00 0.51 -1 -1 1.25 0.806388 0.742409 -k6_N10_40nm.xml des.pre-vpr.blif common 9.87 vpr 63.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 256 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64664 256 245 954 1199 0 613 602 18 18 324 io auto 24.3 MiB 0.27 4828 140357 37125 96029 7203 63.1 MiB 0.58 0.01 4.31026 -789.244 -4.31026 nan 1.18 0.00268887 0.00247718 0.14833 0.135634 -1 -1 -1 -1 34 7705 26 4.608e+06 1.818e+06 779010. 2404.35 3.68 0.891807 0.829501 24000 152888 -1 7130 18 2525 6134 402061 81348 4.49788 nan -806.729 -4.49788 0 0 956463. 2952.05 0.41 0.38 0.14 -1 -1 0.41 0.171429 0.161993 -k6_N10_40nm.xml diffeq.pre-vpr.blif common 9.77 vpr 64.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 95 64 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65996 64 39 1371 1410 1 554 198 12 12 144 clb auto 25.4 MiB 0.38 3823 22662 4704 16452 1506 64.4 MiB 0.27 0.01 6.25641 -1164.67 -6.25641 6.25641 0.39 0.00226113 0.00194038 0.0990354 0.0845147 -1 -1 -1 -1 38 5271 25 1.8e+06 1.71e+06 347776. 2415.11 4.33 1.28566 1.11201 10892 69136 -1 4772 22 2865 8580 311452 52776 5.99996 5.99996 -1159.16 -5.99996 0 0 439064. 3049.06 0.16 0.26 0.06 -1 -1 0.16 0.1526 0.138145 -k6_N10_40nm.xml dsip.pre-vpr.blif common 12.42 vpr 65.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 97 229 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66712 229 197 1370 1567 1 538 523 16 16 256 io auto 25.8 MiB 0.56 4639 156367 46237 102482 7648 65.1 MiB 1.00 0.02 3.20322 -726.151 -3.20322 3.20322 0.86 0.00418747 0.00365041 0.259732 0.22846 -1 -1 -1 -1 34 8368 47 3.528e+06 1.746e+06 604079. 2359.69 5.60 1.32024 1.1892 18880 118149 -1 7459 13 2689 9149 571229 113616 3.28489 3.28489 -779.779 -3.28489 0 0 742044. 2898.61 0.30 0.35 0.11 -1 -1 0.30 0.147385 0.138151 -k6_N10_40nm.xml elliptic.pre-vpr.blif common 39.05 vpr 76.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 235 131 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 78472 131 114 3421 3535 1 1210 480 18 18 324 clb auto 35.7 MiB 1.64 11363 120672 33837 81431 5404 76.6 MiB 2.18 0.04 8.05414 -4631.43 -8.05414 8.05414 1.22 0.00849488 0.00726103 0.692001 0.597428 -1 -1 -1 -1 52 19720 37 4.608e+06 4.23e+06 1.09957e+06 3393.73 16.77 4.25257 3.62962 27876 225772 -1 17122 28 8126 36582 1833716 257901 7.83312 7.83312 -4681.92 -7.83312 0 0 1.44575e+06 4462.18 0.53 1.09 0.27 -1 -1 0.53 0.553107 0.496597 -k6_N10_40nm.xml ex1010.pre-vpr.blif common 41.78 vpr 79.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 299 10 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 81784 10 10 2659 2669 0 1414 319 20 20 400 clb auto 37.5 MiB 2.01 26899 59125 16225 41006 1894 79.9 MiB 1.87 0.03 6.8153 -65.2788 -6.8153 nan 1.86 0.0068608 0.00562071 0.52978 0.455904 -1 -1 -1 -1 90 45378 49 5.832e+06 5.382e+06 2.27845e+06 5696.13 25.05 3.88225 3.29354 44092 472493 -1 41285 21 11495 69687 3807936 447062 6.84579 nan -65.1254 -6.84579 0 0 2.84047e+06 7101.17 1.28 2.16 0.54 -1 -1 1.28 0.780219 0.707484 -k6_N10_40nm.xml ex5p.pre-vpr.blif common 9.00 vpr 62.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 8 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 63808 8 63 761 824 0 451 153 12 12 144 clb auto 23.3 MiB 0.57 4564 13650 2467 10070 1113 62.3 MiB 0.33 0.01 4.36001 -198.144 -4.36001 nan 0.63 0.00250332 0.00205267 0.106769 0.0912641 -1 -1 -1 -1 46 8116 47 1.8e+06 1.476e+06 409728. 2845.33 4.32 0.911486 0.793647 11608 81817 -1 7004 30 4945 21003 896494 141905 4.47246 nan -203.996 -4.47246 0 0 527971. 3666.47 0.17 0.60 0.08 -1 -1 0.17 0.234913 0.213184 -k6_N10_40nm.xml frisc.pre-vpr.blif common 40.55 vpr 75.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 242 20 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 77756 20 116 3175 3291 1 1258 378 18 18 324 clb auto 34.9 MiB 1.71 15482 83704 21369 56709 5626 75.9 MiB 1.70 0.02 10.0612 -5141.26 -10.0612 10.0612 1.16 0.00491127 0.00417088 0.4835 0.410195 -1 -1 -1 -1 64 24533 32 4.608e+06 4.356e+06 1.36711e+06 4219.48 18.07 3.52561 2.98385 30460 277092 -1 22374 28 8629 36312 2096962 284266 10.1175 10.1175 -5118.01 -10.1175 0 0 1.70889e+06 5274.36 1.01 0.98 0.44 -1 -1 1.01 0.438117 0.387003 -k6_N10_40nm.xml misex3.pre-vpr.blif common 7.41 vpr 62.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 86 14 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64336 14 14 828 842 0 506 114 12 12 144 clb auto 23.7 MiB 0.43 4946 8118 1259 6320 539 62.8 MiB 0.19 0.00 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-1 -1 -1 -1 -1 -1 -1 -1 100 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 14 14 828 842 0 489 128 12 12 144 clb auto 23.4 MiB 0.39 5175 7856 1075 6307 474 63.2 MiB 0.17 0.01 4.84801 -64.1454 -4.84801 nan 0.13 0.00237316 0.00211186 0.0763038 0.069521 -1 -1 -1 -1 46 7690 36 1.8e+06 1.8e+06 409728. 2845.33 1.90 0.68048 0.582561 11608 81817 -1 6920 20 4140 18396 605767 102501 4.82071 nan -63.1482 -4.82071 0 0 527971. 3666.47 0.02 0.29 0.06 -1 -1 0.02 0.12603 0.112062 + k6_N10_40nm.xml pdc.pre-vpr.blif common 21.86 vpr 80.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 332 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82088 16 40 2839 2879 0 1508 388 21 21 441 clb auto 37.7 MiB 1.17 25399 76744 19217 54467 3060 80.2 MiB 1.51 0.03 6.92036 -251.161 -6.92036 nan 0.47 0.00885769 0.00740089 0.531173 0.448728 -1 -1 -1 -1 72 40612 31 6.498e+06 5.976e+06 2.09950e+06 4760.78 11.04 2.90977 2.44288 43822 429389 -1 36688 22 12583 72460 3185853 429873 7.06044 nan -257.312 -7.06044 0 0 2.62494e+06 5952.24 0.09 1.30 0.27 -1 -1 0.09 0.47556 0.41731 + k6_N10_40nm.xml s298.pre-vpr.blif common 3.96 vpr 61.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62952 4 6 726 732 1 389 94 12 12 144 clb auto 22.2 MiB 0.25 4089 5206 723 4335 148 61.5 MiB 0.09 0.00 7.44269 -59.1085 -7.44269 7.44269 0.10 0.00104361 0.000914441 0.0377587 0.0345446 -1 -1 -1 -1 40 6786 29 1.8e+06 1.512e+06 360446. 2503.10 1.34 0.413858 0.360142 11036 71301 -1 5886 21 3075 15208 517485 86492 7.26292 7.26292 -60.1433 -7.26292 0 0 452692. 3143.70 0.01 0.25 0.06 -1 -1 0.01 0.116222 0.103786 + k6_N10_40nm.xml s38584.1.pre-vpr.blif common 25.20 vpr 84.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 404 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 86316 39 304 4677 4982 1 2030 747 23 23 529 clb auto 42.7 MiB 1.01 14904 261623 79531 168959 13133 84.3 MiB 2.43 0.03 5.31651 -3386.99 -5.31651 5.31651 0.57 0.010079 0.00906179 0.841925 0.734315 -1 -1 -1 -1 38 21753 42 7.938e+06 7.272e+06 1.42597e+06 2695.60 6.41 3.52156 3.02715 41046 290405 -1 19677 23 11025 32342 1182586 226448 5.01574 5.01574 -3392.1 -5.01574 0 0 1.79789e+06 3398.65 0.07 0.91 0.22 -1 -1 0.07 0.560332 0.490747 + k6_N10_40nm.xml seq.pre-vpr.blif common 6.68 vpr 63.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 112 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65376 41 35 1006 1041 0 592 188 13 13 169 clb auto 24.2 MiB 0.53 7217 15790 2751 11594 1445 63.8 MiB 0.29 0.01 4.98507 -144.608 -4.98507 nan 0.16 0.00308253 0.00273928 0.120489 0.109161 -1 -1 -1 -1 54 11911 44 2.178e+06 2.016e+06 560467. 3316.37 3.24 0.979146 0.844173 14526 113769 -1 10428 30 5280 24638 903866 142828 4.87201 nan -144.017 -4.87201 0 0 730287. 4321.22 0.02 0.46 0.10 -1 -1 0.02 0.199563 0.175824 + k6_N10_40nm.xml spla.pre-vpr.blif common 17.67 vpr 74.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 265 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76688 16 46 2232 2278 0 1137 327 19 19 361 clb auto 33.2 MiB 0.92 17307 56627 13789 39736 3102 74.9 MiB 1.05 0.02 6.63208 -224.84 -6.63208 nan 0.37 0.00697821 0.0058582 0.391341 0.336325 -1 -1 -1 -1 60 30174 42 5.202e+06 4.77e+06 1.43744e+06 3981.82 8.84 2.3335 1.98111 32910 290117 -1 25425 24 9835 57132 2445755 336723 6.52939 nan -226.972 -6.52939 0 0 1.79849e+06 4981.96 0.06 1.13 0.23 -1 -1 0.06 0.404897 0.357661 + k6_N10_40nm.xml tseng.pre-vpr.blif common 3.61 vpr 64.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 112 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65656 52 122 1461 1583 1 500 286 13 13 169 clb auto 24.5 MiB 0.22 3158 39808 8713 28658 2437 64.1 MiB 0.20 0.00 6.15771 -1276.75 -6.15771 6.15771 0.12 0.00151949 0.00138677 0.0725931 0.0655934 -1 -1 -1 -1 26 4848 34 2.178e+06 2.016e+06 310759. 1838.81 0.73 0.389324 0.342948 11502 59218 -1 4210 17 2436 6640 243507 54081 5.71256 5.71256 -1266.26 -5.71256 0 0 383419. 2268.75 0.01 0.20 0.05 -1 -1 0.01 0.123184 0.110004 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt index f2ab28c8ba9..9c78b87cb9f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt @@ -1,17 +1,9 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time num_fpu -hard_fpu_arch_timing.xml bfly.v common -1 -1 -1 -1 -1 0.16 18224 1 0.05 -1 -1 31068 -1 -1 12 193 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63432 193 64 833 649 1 555 273 30 30 900 block_FPU auto 23.1 MiB 12.87 6972 77268 29980 43623 3665 61.9 MiB 0.64 0.01 2.985 -1452.65 -2.985 2.985 0.00 0.00345903 0.00320898 0.310157 0.288034 9758 17.6137 2596 4.68592 934 1040 481302 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-1 -1 0 129 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63392 129 64 769 585 1 513 197 30 30 900 block_FPU auto 22.9 MiB 12.31 6958 48902 21245 27359 298 61.9 MiB 0.54 0.01 2.985 -1455.98 -2.985 2.985 0.00 0.00319221 0.00294586 0.282301 0.261055 10003 19.5371 2642 5.16016 779 897 439553 99390 1.6779e+06 137533 2.03108e+06 2256.75 4 48532 406344 -1 2.985 2.985 -1548.45 -2.985 -21.7856 -0.0851 0.51 -1 -1 61.9 MiB 0.13 0.339114 0.31525 61.9 MiB -1 0.74 4 -hard_fpu_arch_timing.xml fir.v common -1 -1 -1 -1 -1 0.23 18448 1 0.06 -1 -1 31448 -1 -1 0 161 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63824 161 32 993 808 1 589 198 32 32 1024 block_FPU auto 23.5 MiB 19.33 8696 52614 20036 29788 2790 62.3 MiB 0.52 0.00 2.985 -1388.15 -2.985 2.985 0.00 0.00236183 0.0021016 0.238946 0.215583 12400 21.0884 3199 5.44048 931 1030 627581 134171 2.063e+06 171916 2.37490e+06 2319.23 4 57140 479124 -1 2.985 2.985 -1481.02 -2.985 -38.21 -0.0851 0.58 -1 -1 62.3 MiB 0.17 0.292004 0.266051 62.3 MiB -1 1.10 5 -hard_fpu_arch_timing.xml mm3.v common -1 -1 -1 -1 -1 0.13 17448 1 0.04 -1 -1 30584 -1 -1 0 193 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 61708 193 32 545 422 1 406 228 22 22 484 block_FPU auto 21.7 MiB 5.89 4776 55212 23773 31167 272 60.3 MiB 0.43 0.00 2.985 -859.622 -2.985 2.985 0.00 0.00227966 0.00213157 0.192562 0.180241 6302 15.5605 1716 4.23704 575 575 247743 57500 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -879.413 -2.985 -11.8289 -0.0851 0.31 -1 -1 60.3 MiB 0.08 0.230754 0.216735 60.3 MiB -1 0.40 3 -hard_fpu_arch_timing.xml ode.v common -1 -1 -1 -1 -1 0.27 18856 1 0.10 -1 -1 34124 -1 -1 139 130 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 65828 130 72 1194 1103 1 572 343 19 19 361 io auto 25.3 MiB 63.68 4565 96343 31862 60407 4074 64.3 MiB 0.65 0.02 2.985 -1406.8 -2.985 2.985 0.00 0.00310122 0.00280178 0.267549 0.240869 6648 11.6427 1747 3.05954 1275 1369 363986 74305 653279 387384 795482. 2203.55 9 19802 160939 -1 2.985 2.985 -1405.3 -2.985 -52.6773 -0.0851 0.23 -1 -1 64.3 MiB 0.15 0.350981 0.317977 64.3 MiB -1 0.27 2 -hard_fpu_arch_timing.xml syn2.v common -1 -1 -1 -1 -1 0.18 17704 1 0.03 -1 -1 30688 -1 -1 0 161 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63032 161 128 641 490 1 475 293 30 30 900 block_FPU auto 22.9 MiB 2.22 7841 79997 33960 45061 976 61.6 MiB 0.67 0.01 2.985 -1572.64 -2.985 2.985 0.00 0.00371321 0.00348406 0.319763 0.300473 10437 22.0190 2753 5.80802 792 997 433379 92547 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1589.34 -2.985 -16.4581 -0.0851 0.53 -1 -1 61.6 MiB 0.15 0.385642 0.363691 61.6 MiB -1 0.84 4 -hard_fpu_arch_timing.xml syn7.v common -1 -1 -1 -1 -1 0.42 20548 1 0.08 -1 -1 32460 -1 -1 0 161 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 114764 161 128 1921 499 1 1761 309 54 54 2916 block_FPU auto 36.7 MiB 0.90 51330 112017 54453 57290 274 112.1 MiB 3.15 0.04 2.985 -8362.4 -2.985 2.985 0.00 0.0141291 0.0132401 1.6054 1.50698 67889 38.5733 17189 9.76648 4622 7614 5369001 1071099 6.08571e+06 687663 6.89978e+06 2366.18 7 161598 1383069 -1 2.985 2.985 -8813.08 -2.985 -46.2947 -0.0851 1.66 -1 -1 112.1 MiB 1.35 1.95104 1.84046 112.1 MiB -1 3.28 20 - hard_fpu_arch_timing.xml bfly.v common -1 -1 -1 -1 -1 0.16 18224 1 0.05 -1 -1 31068 -1 -1 12 193 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63432 193 64 833 649 1 555 273 30 30 900 block_FPU auto 23.1 MiB 12.87 6972 77268 29980 43623 3665 61.9 MiB 0.64 0.01 2.985 -1452.65 -2.985 2.985 0.00 0.00345903 0.00320898 0.310157 0.288034 9758 17.6137 2596 4.68592 934 1040 481302 105916 1.6779e+06 165039 2.03108e+06 2256.75 7 48532 406344 -1 2.985 2.985 -1496.45 -2.985 -23.8163 -0.0851 0.54 -1 -1 61.9 MiB 0.16 0.388266 0.362244 61.9 MiB -1 0.74 4 - hard_fpu_arch_timing.xml bgm.v common -1 -1 -1 -1 -1 0.29 19040 1 0.06 -1 -1 31632 -1 -1 0 257 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 67800 257 32 1281 693 1 1054 299 38 38 1444 block_FPU auto 26.9 MiB 1.08 18110 101198 46140 54513 545 66.2 MiB 1.42 0.01 2.985 -3229.01 -2.985 2.985 0.00 0.00654702 0.00610351 0.685687 0.639812 25207 23.9383 6546 6.21652 1846 2287 1380850 300883 2.90196e+06 343832 3.35777e+06 2325.33 6 79768 674274 -1 2.985 2.985 -3437.76 -2.985 -32.8428 -0.0851 0.80 -1 -1 66.2 MiB 0.40 0.828712 0.776824 66.2 MiB -1 1.59 10 - hard_fpu_arch_timing.xml dscg.v common -1 -1 -1 -1 -1 0.18 17724 1 0.05 -1 -1 31092 -1 -1 0 129 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63392 129 64 769 585 1 513 197 30 30 900 block_FPU auto 22.9 MiB 12.31 6958 48902 21245 27359 298 61.9 MiB 0.54 0.01 2.985 -1455.98 -2.985 2.985 0.00 0.00319221 0.00294586 0.282301 0.261055 10003 19.5371 2642 5.16016 779 897 439553 99390 1.6779e+06 137533 2.03108e+06 2256.75 4 48532 406344 -1 2.985 2.985 -1548.45 -2.985 -21.7856 -0.0851 0.51 -1 -1 61.9 MiB 0.13 0.339114 0.31525 61.9 MiB -1 0.74 4 - hard_fpu_arch_timing.xml fir.v common -1 -1 -1 -1 -1 0.23 18448 1 0.06 -1 -1 31448 -1 -1 0 161 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63824 161 32 993 808 1 589 198 32 32 1024 block_FPU auto 23.5 MiB 19.33 8696 52614 20036 29788 2790 62.3 MiB 0.52 0.00 2.985 -1388.15 -2.985 2.985 0.00 0.00236183 0.0021016 0.238946 0.215583 12400 21.0884 3199 5.44048 931 1030 627581 134171 2.063e+06 171916 2.37490e+06 2319.23 4 57140 479124 -1 2.985 2.985 -1481.02 -2.985 -38.21 -0.0851 0.58 -1 -1 62.3 MiB 0.17 0.292004 0.266051 62.3 MiB -1 1.10 5 - hard_fpu_arch_timing.xml mm3.v common -1 -1 -1 -1 -1 0.13 17448 1 0.04 -1 -1 30584 -1 -1 0 193 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 61708 193 32 545 422 1 406 228 22 22 484 block_FPU auto 21.7 MiB 5.89 4776 55212 23773 31167 272 60.3 MiB 0.43 0.00 2.985 -859.622 -2.985 2.985 0.00 0.00227966 0.00213157 0.192562 0.180241 6302 15.5605 1716 4.23704 575 575 247743 57500 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -879.413 -2.985 -11.8289 -0.0851 0.31 -1 -1 60.3 MiB 0.08 0.230754 0.216735 60.3 MiB -1 0.40 3 - hard_fpu_arch_timing.xml ode.v common -1 -1 -1 -1 -1 0.27 18856 1 0.10 -1 -1 34124 -1 -1 139 130 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 65828 130 72 1194 1103 1 572 343 19 19 361 io auto 25.3 MiB 63.68 4565 96343 31862 60407 4074 64.3 MiB 0.65 0.02 2.985 -1406.8 -2.985 2.985 0.00 0.00310122 0.00280178 0.267549 0.240869 6648 11.6427 1747 3.05954 1275 1369 363986 74305 653279 387384 795482. 2203.55 9 19802 160939 -1 2.985 2.985 -1405.3 -2.985 -52.6773 -0.0851 0.23 -1 -1 64.3 MiB 0.15 0.350981 0.317977 64.3 MiB -1 0.27 2 - hard_fpu_arch_timing.xml syn2.v common -1 -1 -1 -1 -1 0.18 17704 1 0.03 -1 -1 30688 -1 -1 0 161 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63032 161 128 641 490 1 475 293 30 30 900 block_FPU auto 22.9 MiB 2.22 7841 79997 33960 45061 976 61.6 MiB 0.67 0.01 2.985 -1572.64 -2.985 2.985 0.00 0.00371321 0.00348406 0.319763 0.300473 10437 22.0190 2753 5.80802 792 997 433379 92547 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1589.34 -2.985 -16.4581 -0.0851 0.53 -1 -1 61.6 MiB 0.15 0.385642 0.363691 61.6 MiB -1 0.84 4 - hard_fpu_arch_timing.xml syn7.v common -1 -1 -1 -1 -1 0.42 20548 1 0.08 -1 -1 32460 -1 -1 0 161 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 114764 161 128 1921 499 1 1761 309 54 54 2916 block_FPU auto 36.7 MiB 0.90 51330 112017 54453 57290 274 112.1 MiB 3.15 0.04 2.985 -8362.4 -2.985 2.985 0.00 0.0141291 0.0132401 1.6054 1.50698 67889 38.5733 17189 9.76648 4622 7614 5369001 1071099 6.08571e+06 687663 6.89978e+06 2366.18 7 161598 1383069 -1 2.985 2.985 -8813.08 -2.985 -46.2947 -0.0851 1.66 -1 -1 112.1 MiB 1.35 1.95104 1.84046 112.1 MiB -1 3.28 20 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time num_fpu + hard_fpu_arch_timing.xml bfly.v common 10.66 vpr 62.66 MiB -1 -1 0.29 18880 1 0.04 -1 -1 31060 -1 -1 14 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64160 193 64 833 649 1 555 275 30 30 900 block_FPU auto 22.9 MiB 9.06 7227 73501 28110 42559 2832 62.7 MiB 0.24 0.00 2.985 -1449.57 -2.985 2.985 0.00 0.00129076 0.0012041 0.111382 0.10419 -1 -1 -1 -1 10011 18.0704 2627 4.74188 921 1045 352645 96816 1.6779e+06 169623 2.03108e+06 2256.75 6 48532 406344 -1 2.985 2.985 -1492.92 -2.985 -24.3711 -0.0851 0.33 -1 -1 62.7 MiB 0.08 0.141917 0.133178 62.7 MiB -1 0.09 4 + hard_fpu_arch_timing.xml bgm.v common 4.38 vpr 66.29 MiB -1 -1 0.37 19684 1 0.06 -1 -1 31568 -1 -1 0 257 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67880 257 32 1281 693 1 1048 299 38 38 1444 block_FPU auto 27.1 MiB 1.15 17732 96203 37615 55516 3072 66.3 MiB 0.97 0.01 2.985 -3196.19 -2.985 2.985 0.00 0.0058053 0.00549326 0.572424 0.541944 -1 -1 -1 -1 24861 23.7450 6446 6.15664 1897 2343 998279 268232 2.90196e+06 343832 3.35777e+06 2325.33 6 79768 674274 -1 2.985 2.985 -3400.32 -2.985 -32.9279 -0.0851 0.72 -1 -1 66.3 MiB 0.27 0.668829 0.633922 66.3 MiB -1 0.18 10 + hard_fpu_arch_timing.xml dscg.v common 11.83 vpr 63.13 MiB -1 -1 0.27 18916 1 0.05 -1 -1 30476 -1 -1 0 129 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 129 64 769 585 1 513 197 30 30 900 block_FPU auto 23.0 MiB 9.85 7095 47183 20094 26781 308 63.1 MiB 0.42 0.00 2.985 -1443.24 -2.985 2.985 0.00 0.00302745 0.00284785 0.254581 0.239617 -1 -1 -1 -1 9979 19.4902 2627 5.13086 790 910 348267 96422 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1537.32 -2.985 -21.8648 -0.0851 0.44 -1 -1 63.1 MiB 0.11 0.304162 0.286319 63.1 MiB -1 0.10 4 + hard_fpu_arch_timing.xml fir.v common 19.03 vpr 63.21 MiB -1 -1 0.34 19016 1 0.05 -1 -1 32588 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64724 161 32 993 808 1 587 198 32 32 1024 block_FPU auto 23.3 MiB 16.72 9692 44550 18401 25778 371 63.2 MiB 0.41 0.00 2.985 -1407.96 -2.985 2.985 0.00 0.00297922 0.00277214 0.239029 0.222609 -1 -1 -1 -1 12905 22.0222 3330 5.68259 990 1086 448603 120061 2.063e+06 171916 2.37490e+06 2319.23 5 57140 479124 -1 2.985 2.985 -1491.67 -2.985 -38.4653 -0.0851 0.53 -1 -1 63.2 MiB 0.13 0.291694 0.271864 63.2 MiB -1 0.12 5 + hard_fpu_arch_timing.xml mm3.v common 6.50 vpr 61.19 MiB -1 -1 0.23 18328 1 0.04 -1 -1 30736 -1 -1 0 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62656 193 32 545 422 1 386 228 22 22 484 block_FPU auto 21.8 MiB 4.95 4984 53124 22938 29850 336 61.2 MiB 0.32 0.00 2.985 -851.626 -2.985 2.985 0.00 0.00217515 0.00206622 0.171111 0.1626 -1 -1 -1 -1 6454 16.7636 1714 4.45195 565 565 194103 53991 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -877.472 -2.985 -13.5705 -0.0851 0.24 -1 -1 61.2 MiB 0.07 0.203477 0.193246 61.2 MiB -1 0.05 3 + hard_fpu_arch_timing.xml ode.v common 53.14 vpr 64.66 MiB -1 -1 0.41 19816 1 0.10 -1 -1 34200 -1 -1 141 130 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66208 130 72 1194 1103 1 571 345 19 19 361 io auto 24.6 MiB 50.95 5001 98274 32566 61072 4636 64.7 MiB 0.54 0.01 2.985 -1384.17 -2.985 2.985 0.00 0.00308436 0.00282904 0.260751 0.239819 -1 -1 -1 -1 6737 11.8193 1762 3.09123 1249 1362 304558 77526 653279 391968 795482. 2203.55 8 19802 160939 -1 2.985 2.985 -1385.47 -2.985 -52.8417 -0.0851 0.18 -1 -1 64.7 MiB 0.13 0.330036 0.303434 64.7 MiB -1 0.04 2 + hard_fpu_arch_timing.xml syn2.v common 3.85 vpr 62.39 MiB -1 -1 0.16 18524 1 0.04 -1 -1 30832 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63892 161 128 641 490 1 475 293 30 30 900 block_FPU auto 23.1 MiB 1.75 8105 81941 35762 45750 429 62.4 MiB 0.54 0.01 2.985 -1571.9 -2.985 2.985 0.00 0.00342016 0.0032503 0.298242 0.283689 -1 -1 -1 -1 10335 21.8038 2743 5.78692 780 976 327494 85675 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1595.62 -2.985 -16.3392 -0.0851 0.44 -1 -1 62.4 MiB 0.11 0.355509 0.338332 62.4 MiB -1 0.10 4 + hard_fpu_arch_timing.xml syn7.v common 7.45 vpr 112.47 MiB -1 -1 0.45 21564 1 0.08 -1 -1 32500 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 115168 161 128 1921 499 1 1760 309 54 54 2916 block_FPU auto 37.0 MiB 0.62 44624 112017 52264 59181 572 112.5 MiB 2.20 0.02 2.985 -8100.96 -2.985 2.985 0.00 0.0120269 0.0114133 1.31427 1.24716 -1 -1 -1 -1 60108 34.1717 15324 8.71177 4214 6760 3339753 839694 6.08571e+06 687663 6.89978e+06 2366.18 9 161598 1383069 -1 2.985 2.985 -8533.86 -2.985 -46.3798 -0.0851 1.55 -1 -1 112.5 MiB 0.90 1.61708 1.53715 112.5 MiB -1 0.39 20 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt index 39285b5f6fd..985745ce71c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt @@ -1,8 +1,8 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - soft_fpu_arch_timing.xml bfly.v common 40.57 yosys 122.16 MiB -1 -1 22.13 125096 23 5.62 -1 -1 41692 -1 -1 1040 193 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 85328 193 64 4025 4089 1 2736 1297 35 35 1225 clb auto 46.0 MiB 0.97 24357 83.3 MiB 3.80 0.05 12.6863 -3133.42 -12.6863 12.6863 0.19 0.00678317 0.00575525 0.583526 0.494286 43509 23481 79464 7440725 993539 2.49624e+06 2.38392e+06 2.83731e+06 2316.17 25 14.5389 14.5389 -3399.68 -14.5389 -30.6915 -0.0851 83.3 MiB 2.29 1.09901 0.94705 83.3 MiB 1.83 - soft_fpu_arch_timing.xml bgm.v common 85.62 yosys 262.74 MiB -1 -1 55.10 269048 18 13.31 -1 -1 50340 -1 -1 1412 257 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 98592 257 32 6050 6082 1 4052 1701 40 40 1600 clb auto 59.8 MiB 1.28 32465 96.3 MiB 5.79 0.04 10.1721 -4834.31 -10.1721 10.1721 0.25 0.00614799 0.00540653 0.86422 0.729823 55833 29024 89852 8145011 1111561 3.30999e+06 3.23663e+06 3.73324e+06 2333.28 24 11.3843 11.3843 -5207.55 -11.3843 -27.431 -0.0851 96.3 MiB 1.71 1.32139 1.13159 96.3 MiB 2.43 - soft_fpu_arch_timing.xml dscg.v common 33.83 yosys 120.67 MiB -1 -1 24.80 123568 25 2.07 -1 -1 41792 -1 -1 565 129 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 71128 129 64 2143 2207 1 1543 758 26 26 676 clb auto 31.6 MiB 0.51 12874 69.5 MiB 1.58 0.02 14.3664 -1690.33 -14.3664 14.3664 0.09 0.00354728 0.00307928 0.273789 0.235084 23119 13167 44172 4130151 562348 1.32031e+06 1.2951e+06 1.53374e+06 2268.84 24 15.799 15.799 -1841.77 -15.799 -8.6998 -0.0851 69.5 MiB 1.27 0.551637 0.482491 69.5 MiB 0.94 - soft_fpu_arch_timing.xml fir.v common 26.03 yosys 107.03 MiB -1 -1 20.01 109600 16 1.08 -1 -1 39144 -1 -1 470 161 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 68304 161 32 2031 2063 1 1225 663 24 24 576 clb auto 29.0 MiB 0.34 6818 66.7 MiB 0.96 0.02 8.78105 -1407.83 -8.78105 8.78105 0.07 0.00263578 0.00221588 0.190077 0.16097 11091 6628 16931 1530770 210173 1.10943e+06 1.07733e+06 1.29802e+06 2253.51 29 10.2137 10.2137 -1490.23 -10.2137 -36.4317 -0.0851 66.7 MiB 0.58 0.402875 0.349509 66.7 MiB 0.78 - soft_fpu_arch_timing.xml mm3.v common 16.83 yosys 77.55 MiB -1 -1 14.00 79408 11 0.34 -1 -1 37140 -1 -1 188 193 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 60760 193 32 904 936 1 583 413 21 21 441 io auto 21.3 MiB 0.13 2803 59.3 MiB 0.33 0.01 5.82017 -484.835 -5.82017 5.82017 0.05 0.00130186 0.00114881 0.0741617 0.0644725 4633 2312 4580 414875 58859 827486 430936 981244. 2225.04 18 6.59157 6.59157 -518.556 -6.59157 -6.90646 -0.0851 59.3 MiB 0.16 0.13609 0.120573 59.3 MiB 0.51 - soft_fpu_arch_timing.xml ode.v common 41.23 yosys 125.50 MiB -1 -1 17.72 128508 24 6.58 -1 -1 47476 -1 -1 1376 130 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 95068 130 72 5235 5307 1 3591 1578 40 40 1600 clb auto 55.9 MiB 1.26 35397 92.8 MiB 5.68 0.07 13.7468 -4422.98 -13.7468 13.7468 0.24 0.00918165 0.00803446 0.859672 0.732311 61467 27802 90970 8572516 1132437 3.30999e+06 3.15411e+06 3.73324e+06 2333.28 22 15.1794 15.1794 -4765.97 -15.1794 -53.7766 -0.0851 92.8 MiB 2.72 1.52323 1.31474 92.8 MiB 2.44 - soft_fpu_arch_timing.xml syn2.v common 70.87 yosys 151.36 MiB -1 -1 23.13 154996 23 13.96 -1 -1 51820 -1 -1 2290 161 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 131092 161 128 8356 8484 1 6201 2579 50 50 2500 clb auto 82.9 MiB 2.30 63583 126.4 MiB 14.58 0.16 13.437 -6901.96 -13.437 13.437 0.46 0.0187672 0.016783 1.78112 1.47957 112990 51030 168594 15868739 2084984 5.2812e+06 5.24911e+06 5.89298e+06 2357.19 25 14.6283 14.6283 -7454.97 -14.6283 -24.4737 -0.0851 126.4 MiB 5.44 3.18795 2.70077 126.4 MiB 4.09 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + soft_fpu_arch_timing.xml bfly.v common 41.34 parmys 121.35 MiB -1 -1 28.71 124260 23 3.25 -1 -1 39816 -1 -1 1065 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84540 193 64 3908 3972 1 2590 1322 35 35 1225 clb auto 40.9 MiB 0.92 23821 566978 183866 374301 8811 82.6 MiB 3.62 0.05 15.2252 -3632.45 -15.2252 15.2252 0.00 0.00893832 0.00809078 0.765101 0.674928 -1 -1 -1 -1 41554 16.0502 10620 4.10197 16398 55146 3818752 563046 2.49624e+06 2.44122e+06 2.83731e+06 2316.17 20 66042 566079 -1 14.3186 14.3186 -3387.7 -14.3186 -31.8712 -0.0851 0.59 -1 -1 82.6 MiB 1.30 1.1781 1.04452 82.6 MiB -1 0.14 + soft_fpu_arch_timing.xml bgm.v common 91.63 parmys 261.79 MiB -1 -1 68.05 268076 18 8.02 -1 -1 47316 -1 -1 1490 257 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 98376 257 32 6040 6072 1 3862 1779 41 41 1681 clb auto 52.4 MiB 1.35 32284 896104 308252 576620 11232 96.1 MiB 5.96 0.07 12.7604 -5544.74 -12.7604 12.7604 0.00 0.0121239 0.0108644 1.11649 0.963883 -1 -1 -1 -1 53705 13.9132 13764 3.56580 24580 81256 5307364 800086 3.48649e+06 3.41543e+06 3.92715e+06 2336.20 24 90666 782499 -1 12.0246 12.0246 -5156.11 -12.0246 -31.3502 -0.0851 0.78 -1 -1 96.1 MiB 1.91 1.78217 1.54405 96.1 MiB -1 0.19 + soft_fpu_arch_timing.xml dscg.v common 37.96 parmys 121.48 MiB -1 -1 31.02 124396 24 1.46 -1 -1 38668 -1 -1 602 129 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72036 129 64 2192 2256 1 1525 795 27 27 729 clb auto 30.2 MiB 0.54 13360 240060 66463 162314 11283 70.3 MiB 1.50 0.02 16.4736 -1891.5 -16.4736 16.4736 0.00 0.00522672 0.00478088 0.373681 0.337968 -1 -1 -1 -1 23389 15.7821 5992 4.04318 10665 36046 2530253 367157 1.43263e+06 1.37991e+06 1.65895e+06 2275.65 21 39258 331839 -1 14.938 14.938 -1781.33 -14.938 -9.29425 -0.0851 0.32 -1 -1 70.3 MiB 0.86 0.642834 0.579879 70.3 MiB -1 0.07 + soft_fpu_arch_timing.xml fir.v common 30.01 parmys 107.04 MiB -1 -1 25.31 109604 16 0.75 -1 -1 35824 -1 -1 480 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69144 161 32 2044 2076 1 1154 673 24 24 576 clb auto 27.8 MiB 0.33 7067 186397 50839 130117 5441 67.5 MiB 1.00 0.02 10.7496 -1623.35 -10.7496 10.7496 0.00 0.00400883 0.00360476 0.266889 0.238205 -1 -1 -1 -1 11039 9.58247 2844 2.46875 5647 15675 1030099 156890 1.10943e+06 1.10026e+06 1.29802e+06 2253.51 23 30996 260004 -1 10.1243 10.1243 -1523.31 -10.1243 -41.6788 -0.0851 0.25 -1 -1 67.5 MiB 0.42 0.454829 0.403412 67.5 MiB -1 0.06 + soft_fpu_arch_timing.xml mm3.v common 19.71 parmys 76.30 MiB -1 -1 17.40 78128 11 0.25 -1 -1 34080 -1 -1 188 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62248 193 32 892 924 1 553 413 21 21 441 io auto 21.0 MiB 0.15 2944 81874 21125 56255 4494 60.8 MiB 0.37 0.01 7.4944 -557.676 -7.4944 7.4944 0.00 0.00203025 0.00187301 0.114304 0.105094 -1 -1 -1 -1 4300 7.78986 1136 2.05797 2073 4078 247328 39648 827486 430936 981244. 2225.04 17 23706 196899 -1 6.6809 6.6809 -514.232 -6.6809 -6.91814 -0.0851 0.19 -1 -1 60.8 MiB 0.13 0.187463 0.170377 60.8 MiB -1 0.04 + soft_fpu_arch_timing.xml ode.v common 40.64 parmys 125.57 MiB -1 -1 23.10 128584 24 4.17 -1 -1 44228 -1 -1 1412 130 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 94024 130 72 5151 5223 1 3426 1614 40 40 1600 clb auto 48.4 MiB 1.33 35991 777580 261625 505362 10593 91.8 MiB 5.34 0.06 15.9431 -5264.37 -15.9431 15.9431 0.00 0.0117408 0.0100826 1.01252 0.875255 -1 -1 -1 -1 60460 17.6732 15462 4.51973 24242 84687 5987586 871715 3.30999e+06 3.23663e+06 3.73324e+06 2333.28 21 86292 744004 -1 14.8488 14.8488 -4929.15 -14.8488 -50.5031 -0.0851 0.74 -1 -1 91.8 MiB 1.94 1.5713 1.36676 91.8 MiB -1 0.19 + soft_fpu_arch_timing.xml syn2.v common 62.84 parmys 154.08 MiB -1 -1 29.55 157776 24 7.67 -1 -1 48164 -1 -1 2381 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 146376 161 128 8330 8458 1 5909 2670 51 51 2601 clb auto 69.8 MiB 2.37 66146 1576445 571349 976282 28814 142.9 MiB 12.22 0.13 17.1016 -8352.63 -17.1016 17.1016 0.00 0.0199685 0.0180821 1.87397 1.60664 -1 -1 -1 -1 113775 19.4487 28920 4.94359 45588 170928 12281742 1779631 5.50353e+06 5.45769e+06 6.13592e+06 2359.06 21 140346 1220799 -1 15.9299 15.9299 -7817.18 -15.9299 -29.0971 -0.0851 1.30 -1 -1 142.9 MiB 4.07 2.89569 2.48638 142.9 MiB -1 0.35 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt index 6e30998de45..dbe5e369b17 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt @@ -1,235 +1,235 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_14.v common 10.54 vpr 70.70 MiB 0.08 10424 -1 -1 8 0.47 -1 -1 34568 -1 -1 129 22 0 4 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72392 22 19 1764 1664 1 986 174 16 16 256 mult_36 auto 32.5 MiB 0.23 6911 23454 4494 16949 2011 70.7 MiB 0.38 0.01 4.33936 -1301.29 -4.33936 4.33936 0.56 0.00365899 0.00326498 0.195213 0.174646 56 12579 33 6.2557e+06 3.1391e+06 803869. 3140.11 6.06 1.35873 1.18031 23564 190428 -1 11422 16 3998 8028 649808 152476 4.21916 4.21916 -1356.04 -4.21916 0 0 987003. 3855.48 0.24 0.27 0.17 -1 -1 0.24 0.135479 0.1203 966 966 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_15.v common 18.70 vpr 71.25 MiB 0.12 10744 -1 -1 8 0.49 -1 -1 36248 -1 -1 139 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72960 22 19 1918 1801 1 1083 185 16 16 256 clb mult_36 auto 33.3 MiB 0.31 7452 24381 4617 17851 1913 71.2 MiB 0.40 0.01 4.2726 -1449.28 -4.2726 4.2726 0.57 0.00379266 0.0033986 0.199621 0.178244 58 13092 31 6.2557e+06 3.65564e+06 820238. 3204.05 13.97 1.94719 1.68393 24072 200857 -1 11442 15 3878 7716 550889 129867 4.33936 4.33936 -1521.98 -4.33936 0 0 1.02849e+06 4017.54 0.26 0.28 0.18 -1 -1 0.26 0.149226 0.132931 1047 1047 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_16.v common 20.82 vpr 71.85 MiB 0.08 10924 -1 -1 8 0.49 -1 -1 37424 -1 -1 143 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73572 22 19 1976 1859 1 1114 189 17 17 289 clb auto 33.9 MiB 0.32 7264 24037 4291 17788 1958 71.8 MiB 0.41 0.01 4.21916 -1486.51 -4.21916 4.21916 0.63 0.00489752 0.00431003 0.201025 0.178991 50 13894 29 6.55708e+06 3.70386e+06 851065. 2944.86 15.84 1.99817 1.72454 25342 195625 -1 12284 15 4638 9503 717159 167904 4.21916 4.21916 -1550.01 -4.21916 0 0 1.01866e+06 3524.77 0.26 0.29 0.17 -1 -1 0.26 0.142612 0.126662 1086 1086 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_17.v common 9.92 vpr 72.78 MiB 0.12 11700 -1 -1 8 0.62 -1 -1 36784 -1 -1 163 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74524 22 19 2278 2144 1 1240 209 17 17 289 clb auto 35.2 MiB 0.36 8060 29969 5695 21748 2526 72.8 MiB 0.47 0.01 4.45956 -1684.95 -4.45956 4.45956 0.63 0.00463111 0.0041369 0.23625 0.210005 54 15140 22 6.55708e+06 3.94496e+06 896083. 3100.63 4.55 1.53975 1.33532 26206 212621 -1 12577 16 4569 8799 640836 153828 4.21916 4.21916 -1745.34 -4.21916 0 0 1.10294e+06 3816.40 0.28 0.32 0.18 -1 -1 0.28 0.176032 0.155889 1242 1242 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_18.v common 11.28 vpr 73.71 MiB 0.09 11836 -1 -1 8 0.64 -1 -1 37796 -1 -1 168 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75484 22 19 2336 2202 1 1265 214 18 18 324 clb auto 35.8 MiB 0.40 8290 36637 7934 26298 2405 73.7 MiB 0.57 0.01 4.21916 -1744.34 -4.21916 4.21916 0.73 0.00444452 0.00396062 0.286115 0.253518 50 16367 48 7.67456e+06 4.00524e+06 975281. 3010.13 5.32 1.59346 1.38595 28904 225404 -1 13788 16 5109 10482 831833 193930 4.33936 4.33936 -1820.48 -4.33936 0 0 1.16663e+06 3600.72 0.32 0.37 0.20 -1 -1 0.32 0.182922 0.161524 1281 1281 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_19.v common 27.64 vpr 73.89 MiB 0.14 12416 -1 -1 8 0.73 -1 -1 37396 -1 -1 175 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75668 22 19 2488 2337 1 1372 222 18 18 324 clb auto 36.6 MiB 0.40 9596 39140 8295 28140 2705 73.9 MiB 0.68 0.01 4.33936 -1880.13 -4.33936 4.33936 0.80 0.0047139 0.00418558 0.324637 0.286821 54 18562 42 7.67456e+06 4.48562e+06 1.02660e+06 3168.53 21.36 2.68022 2.31611 29872 244976 -1 14749 13 5049 10006 745695 175397 4.33936 4.33936 -1903.22 -4.33936 0 0 1.26286e+06 3897.71 0.32 0.31 0.21 -1 -1 0.32 0.161915 0.144401 1360 1360 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_20.v common 12.23 vpr 74.60 MiB 0.14 12340 -1 -1 8 0.79 -1 -1 37540 -1 -1 182 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76388 22 19 2546 2395 1 1407 229 18 18 324 clb auto 37.3 MiB 0.40 9852 41529 9029 29722 2778 74.6 MiB 0.66 0.01 4.23263 -1906.98 -4.23263 4.23263 0.73 0.00510993 0.00455479 0.311577 0.274832 56 17400 27 7.67456e+06 4.57001e+06 1.05222e+06 3247.61 5.92 1.81762 1.58422 30196 251424 -1 15852 16 5369 10891 854362 201858 4.33936 4.33936 -2002.14 -4.33936 0 0 1.29075e+06 3983.80 0.34 0.40 0.22 -1 -1 0.34 0.201322 0.179277 1399 1399 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_21.v common 16.26 vpr 75.50 MiB 0.15 12828 -1 -1 8 0.89 -1 -1 37744 -1 -1 193 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77308 22 19 2735 2567 1 1516 240 19 19 361 clb auto 38.2 MiB 0.47 11409 38235 7770 28551 1914 75.5 MiB 0.63 0.01 4.57976 -2047.16 -4.57976 4.57976 0.84 0.00577536 0.00518636 0.3054 0.270886 60 19097 20 8.02416e+06 4.70262e+06 1.23460e+06 3419.94 9.34 2.14776 1.86265 34598 305437 -1 17021 13 5592 11571 878461 200428 4.45956 4.45956 -2093.27 -4.45956 0 0 1.54069e+06 4267.84 0.41 0.36 0.27 -1 -1 0.41 0.181661 0.162213 1497 1497 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_22.v common 12.01 vpr 75.86 MiB 0.14 12916 -1 -1 8 0.92 -1 -1 38120 -1 -1 200 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77680 22 19 2793 2625 1 1545 247 19 19 361 clb auto 38.7 MiB 0.43 10819 43591 9468 32068 2055 75.9 MiB 0.69 0.01 4.33936 -2094.5 -4.33936 4.33936 0.83 0.00528357 0.00468913 0.332009 0.293678 58 18949 22 8.02416e+06 4.787e+06 1.20750e+06 3344.89 5.03 1.59876 1.39152 34238 298765 -1 17036 18 6019 12139 929813 221385 4.33936 4.33936 -2185.66 -4.33936 0 0 1.51231e+06 4189.22 0.41 0.44 0.25 -1 -1 0.41 0.233865 0.207296 1536 1536 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_23.v common 12.86 vpr 76.60 MiB 0.11 13404 -1 -1 8 0.92 -1 -1 38712 -1 -1 211 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78440 22 19 2947 2762 1 1644 259 19 19 361 clb auto 39.4 MiB 0.49 11020 43159 9038 31489 2632 76.6 MiB 0.75 0.01 4.2726 -2221.58 -4.2726 4.2726 0.87 0.0059107 0.00523601 0.358623 0.318099 58 19050 20 8.02416e+06 5.3156e+06 1.20750e+06 3344.89 5.62 1.82998 1.60216 34238 298765 -1 17111 13 5734 11444 793982 193134 4.45956 4.45956 -2263.88 -4.45956 0 0 1.51231e+06 4189.22 0.41 0.40 0.26 -1 -1 0.41 0.205585 0.184619 1617 1617 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_24.v common 13.53 vpr 76.93 MiB 0.18 13496 -1 -1 8 0.95 -1 -1 38724 -1 -1 216 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78780 22 19 3005 2820 1 1676 264 19 19 361 clb auto 39.9 MiB 0.51 11788 45102 9582 33144 2376 76.9 MiB 0.77 0.01 4.33936 -2265.94 -4.33936 4.33936 0.89 0.0060117 0.00535217 0.367787 0.325894 58 20359 33 8.02416e+06 5.37588e+06 1.20750e+06 3344.89 5.91 1.94923 1.70406 34238 298765 -1 17938 13 6106 12521 945470 221782 4.33936 4.33936 -2379.04 -4.33936 0 0 1.51231e+06 4189.22 0.42 0.42 0.26 -1 -1 0.42 0.207164 0.185275 1656 1656 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_25.v common 16.78 vpr 79.07 MiB 0.16 13996 -1 -1 8 1.12 -1 -1 40320 -1 -1 231 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80972 22 19 3229 3027 1 1787 279 20 20 400 clb auto 41.1 MiB 0.55 13104 50384 10538 36503 3343 79.1 MiB 0.86 0.01 4.33936 -2497.75 -4.33936 4.33936 1.01 0.00631594 0.00563073 0.407978 0.360229 56 24126 48 1.09209e+07 5.5567e+06 1.31097e+06 3277.42 8.53 2.56516 2.25629 37530 313959 -1 21480 15 7283 15143 1320591 298085 4.33936 4.33936 -2564.15 -4.33936 0 0 1.60880e+06 4022.00 0.42 0.54 0.27 -1 -1 0.42 0.247739 0.220975 1771 1771 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_26.v common 19.25 vpr 79.34 MiB 0.18 14372 -1 -1 8 1.08 -1 -1 40560 -1 -1 237 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81244 22 19 3287 3085 1 1821 285 21 21 441 clb auto 41.4 MiB 0.56 13136 57442 13523 40914 3005 79.3 MiB 0.90 0.01 4.33936 -2504.53 -4.33936 4.33936 1.08 0.00606643 0.00535482 0.414242 0.364529 58 22683 37 1.13066e+07 5.62904e+06 1.48593e+06 3369.47 10.49 2.35823 2.04792 42062 368216 -1 20548 13 6990 14309 1055541 245303 4.21916 4.21916 -2554.32 -4.21916 0 0 1.86135e+06 4220.76 0.51 0.49 0.31 -1 -1 0.51 0.232733 0.208547 1810 1810 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_27.v common 19.01 vpr 79.30 MiB 0.15 14548 -1 -1 8 1.04 -1 -1 39364 -1 -1 251 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81208 22 19 3453 3234 1 1931 300 21 21 441 clb auto 42.4 MiB 0.57 14985 60480 13891 43297 3292 79.3 MiB 0.96 0.02 4.35283 -2683.1 -4.35283 4.35283 1.06 0.006508 0.00577071 0.447304 0.394235 58 26866 32 1.13066e+07 6.1938e+06 1.48593e+06 3369.47 10.12 2.22103 1.93376 42062 368216 -1 23239 14 7816 16183 1303787 291924 4.33936 4.33936 -2773.32 -4.33936 0 0 1.86135e+06 4220.76 0.54 0.60 0.32 -1 -1 0.54 0.286199 0.260459 1903 1903 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_28.v common 21.07 vpr 80.57 MiB 0.14 14696 -1 -1 8 1.34 -1 -1 41092 -1 -1 256 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82504 22 19 3511 3292 1 1964 305 21 21 441 clb auto 42.9 MiB 0.62 13949 56735 12285 41462 2988 80.6 MiB 0.96 0.02 4.33936 -2735.23 -4.33936 4.33936 1.10 0.00704446 0.00619059 0.437073 0.384685 64 23032 20 1.13066e+07 6.25408e+06 1.61476e+06 3661.58 11.73 2.81808 2.45166 43822 404518 -1 20960 15 6761 13901 1029805 236692 4.33936 4.33936 -2868.81 -4.33936 0 0 2.02607e+06 4594.27 0.59 0.55 0.37 -1 -1 0.59 0.291523 0.261599 1942 1942 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_29.v common 43.72 vpr 81.68 MiB 0.11 15144 -1 -1 8 1.20 -1 -1 40048 -1 -1 268 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83640 22 19 3709 3473 1 2078 318 22 22 484 clb mult_36 auto 44.3 MiB 0.60 16039 68673 16015 49006 3652 81.7 MiB 1.06 0.02 4.45956 -2880.87 -4.45956 4.45956 1.15 0.00686048 0.00606524 0.489167 0.431798 58 28453 49 1.25085e+07 6.79474e+06 1.65337e+06 3416.05 34.20 3.77322 3.27923 46570 411141 -1 24738 15 8089 16692 1363351 299594 4.45956 4.45956 -2907.33 -4.45956 0 0 2.07026e+06 4277.39 0.57 0.58 0.34 -1 -1 0.57 0.269084 0.238866 2049 2049 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_30.v common 19.05 vpr 82.44 MiB 0.15 15328 -1 -1 8 1.43 -1 -1 40280 -1 -1 274 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84420 22 19 3767 3531 1 2107 324 22 22 484 clb mult_36 auto 45.1 MiB 0.63 15345 71492 17040 50634 3818 82.4 MiB 1.15 0.02 4.33936 -2892.9 -4.33936 4.33936 1.15 0.00691652 0.00611562 0.518098 0.456256 58 27413 39 1.25085e+07 6.86707e+06 1.65337e+06 3416.05 8.83 2.77404 2.41177 46570 411141 -1 23887 38 8479 18001 1648879 434292 4.21916 4.21916 -3000.49 -4.21916 0 0 2.07026e+06 4277.39 0.57 0.99 0.35 -1 -1 0.57 0.558583 0.489165 2088 2088 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_31.v common 23.10 vpr 85.05 MiB 0.22 15676 -1 -1 8 1.39 -1 -1 41812 -1 -1 288 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87096 22 19 3928 3675 1 2213 338 22 22 484 clb mult_36 auto 45.3 MiB 0.65 16438 72074 17115 51144 3815 82.8 MiB 1.12 0.02 4.45956 -3035.76 -4.45956 4.45956 1.16 0.00842428 0.00738986 0.509085 0.449211 66 26913 16 1.25085e+07 7.03584e+06 1.84972e+06 3821.73 12.87 3.03126 2.63675 48986 463441 -1 24448 13 7560 15563 1140627 256835 4.33936 4.33936 -3082.3 -4.33936 0 0 2.30827e+06 4769.15 0.68 0.58 0.41 -1 -1 0.68 0.287148 0.25805 2176 2176 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_32.v common 41.95 vpr 83.27 MiB 0.21 15936 -1 -1 8 1.45 -1 -1 41916 -1 -1 292 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85272 22 19 3986 3733 1 2248 342 22 22 484 clb mult_36 auto 45.9 MiB 0.69 16132 74432 17571 52958 3903 83.3 MiB 1.25 0.02 4.33936 -3099.4 -4.33936 4.33936 1.20 0.00832441 0.00746229 0.553013 0.486788 56 31857 46 1.25085e+07 7.08406e+06 1.62053e+06 3348.21 31.65 4.71659 4.10469 45606 389969 -1 26896 15 9433 19525 1638672 375328 4.33936 4.33936 -3259.61 -4.33936 0 0 1.98725e+06 4105.89 0.58 0.70 0.31 -1 -1 0.58 0.308955 0.276833 2215 2215 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_33.v common 27.12 vpr 84.87 MiB 0.20 16892 -1 -1 8 1.52 -1 -1 40940 -1 -1 314 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86904 22 19 4329 4059 1 2377 365 23 23 529 clb auto 47.6 MiB 0.71 17638 86363 21629 61030 3704 84.9 MiB 1.40 0.02 4.33936 -3329.38 -4.33936 4.33936 1.33 0.00842929 0.00749515 0.624815 0.549057 56 32553 43 1.29425e+07 7.74527e+06 1.78215e+06 3368.90 15.79 3.43193 2.97782 49650 429369 -1 28679 14 9750 20297 1623196 372067 4.33936 4.33936 -3511.98 -4.33936 0 0 2.18505e+06 4130.54 0.64 0.72 0.38 -1 -1 0.64 0.329797 0.295474 2394 2394 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_34.v common 39.21 vpr 85.64 MiB 0.20 17024 -1 -1 8 1.64 -1 -1 42864 -1 -1 320 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87692 22 19 4387 4117 1 2404 371 23 23 529 clb auto 48.3 MiB 0.69 17853 80291 18434 57983 3874 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100540 22 19 4860 4556 1 2713 407 25 25 625 clb auto 51.0 MiB 0.83 21029 104390 26805 72904 4681 87.5 MiB 1.68 0.02 4.513 -3868.35 -4.513 4.513 1.70 0.00965273 0.008604 0.734399 0.645727 64 35977 33 1.55855e+07 8.63552e+06 2.32897e+06 3726.35 18.72 4.63084 4.04052 62084 585869 -1 31942 15 9860 20631 1603833 349642 4.45956 4.45956 -4006.24 -4.45956 0 0 2.92220e+06 4675.52 0.82 0.72 0.47 -1 -1 0.82 0.357199 0.317705 2704 2704 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_39.v common 24.48 vpr 92.17 MiB 0.23 18476 -1 -1 8 1.83 -1 -1 43728 -1 -1 370 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94384 22 19 5019 4698 1 2814 422 25 25 625 clb auto 51.8 MiB 0.93 21376 107998 26675 75558 5765 90.1 MiB 1.77 0.02 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0.24 19348 -1 -1 8 2.09 -1 -1 44368 -1 -1 397 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 97564 22 19 5366 5028 1 2986 450 26 26 676 clb auto 53.8 MiB 0.86 22251 119337 30576 83966 4795 90.3 MiB 1.80 0.02 4.23263 -4198.35 -4.23263 4.23263 1.74 0.0101791 0.00901582 0.76676 0.671252 56 40623 46 1.89118e+07 9.53784e+06 2.31971e+06 3431.53 12.60 4.2101 3.65301 64740 561756 -1 35526 16 11590 24438 1963681 445204 4.45956 4.45956 -4499.81 -4.45956 0 0 2.84390e+06 4206.95 1.08 0.94 0.59 -1 -1 1.08 0.462596 0.415325 2990 2990 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_43.v common 36.63 vpr 106.50 MiB 0.22 19876 -1 -1 8 2.33 -1 -1 44700 -1 -1 404 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 109060 22 19 5524 5169 1 3090 457 26 26 676 clb auto 54.9 MiB 0.90 23398 130623 34411 91228 4984 92.7 MiB 2.06 0.03 4.45956 -4342.14 -4.45956 4.45956 1.83 0.0108931 0.00969226 0.874489 0.767625 60 39582 39 1.89118e+07 9.62222e+06 2.42032e+06 3580.36 21.57 5.52395 4.85172 66764 605600 -1 35437 14 11429 23247 1712213 389393 4.45956 4.45956 -4737.53 -4.45956 0 0 3.01907e+06 4466.08 0.95 0.86 0.52 -1 -1 0.95 0.4245 0.38237 3075 3075 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_44.v common 27.82 vpr 97.39 MiB 0.30 20044 -1 -1 8 2.22 -1 -1 45288 -1 -1 410 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 99732 22 19 5582 5227 1 3122 463 26 26 676 clb auto 55.3 MiB 0.91 23363 127553 31863 89801 5889 93.0 MiB 2.05 0.03 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0.37 22404 -1 -1 8 3.18 -1 -1 47348 -1 -1 485 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 132504 22 19 6600 6177 1 3704 540 28 28 784 clb auto 61.2 MiB 1.11 29887 163192 43894 113647 5651 98.5 MiB 2.51 0.03 4.45956 -5273.35 -4.45956 4.45956 2.19 0.0131739 0.0114938 1.01498 0.889057 68 47406 27 2.18512e+07 1.13907e+07 3.12359e+06 3984.17 26.82 7.31251 6.40015 80408 782754 -1 43526 15 12631 27337 1955079 425942 4.45956 4.45956 -5862.66 -4.45956 0 0 3.88747e+06 4958.51 1.25 1.01 0.66 -1 -1 1.25 0.518284 0.464813 3692 3692 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_14.v common 12.28 vpr 67.25 MiB 0.06 9112 -1 -1 10 0.50 -1 -1 35248 -1 -1 93 22 0 4 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68864 22 19 1149 1049 1 787 138 16 16 256 mult_36 auto 29.3 MiB 0.23 5353 14734 2612 11022 1100 67.2 MiB 0.27 0.01 12.8728 -438.233 -12.8728 12.8728 0.60 0.00301233 0.0027457 0.141779 0.129371 58 10212 29 6.2557e+06 2.70512e+06 820238. 3204.05 8.07 1.40181 1.23568 24072 200857 -1 9272 20 4271 8887 665232 152260 12.1591 12.1591 -509.624 -12.1591 0 0 1.02849e+06 4017.54 0.27 0.28 0.18 -1 -1 0.27 0.129279 0.115798 715 715 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_15.v common 9.05 vpr 67.98 MiB 0.11 9572 -1 -1 11 0.61 -1 -1 36132 -1 -1 106 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69616 22 19 1261 1144 1 879 152 16 16 256 mult_36 auto 30.0 MiB 0.26 6117 19592 3623 14422 1547 68.0 MiB 0.32 0.01 14.5477 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-1 128 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71072 22 19 1507 1373 1 1035 174 16 16 256 mult_36 auto 32.0 MiB 0.28 7464 21029 3707 15454 1868 69.4 MiB 0.36 0.01 14.9867 -537.872 -14.9867 14.9867 0.59 0.00395163 0.00358045 0.179772 0.163435 58 13697 35 6.2557e+06 3.52304e+06 820238. 3204.05 5.18 1.10905 0.982387 24072 200857 -1 12092 18 5182 10900 801705 187365 13.6413 13.6413 -622.575 -13.6413 0 0 1.02849e+06 4017.54 0.26 0.36 0.18 -1 -1 0.26 0.160493 0.144356 961 961 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_19.v common 9.66 vpr 70.07 MiB 0.10 10332 -1 -1 11 0.71 -1 -1 36144 -1 -1 135 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71748 22 19 1596 1445 1 1100 182 16 16 256 clb mult_36 auto 32.6 MiB 0.28 7815 21297 3392 16393 1512 70.1 MiB 0.38 0.01 14.7981 -567.745 -14.7981 14.7981 0.57 0.00384762 0.00349311 0.187979 0.171004 56 15000 37 6.2557e+06 4.00342e+06 803869. 3140.11 4.70 1.20261 1.06324 23564 190428 -1 13198 19 5867 12427 977161 232477 13.6952 13.6952 -693.57 -13.6952 0 0 987003. 3855.48 0.26 0.43 0.18 -1 -1 0.26 0.177795 0.160712 1013 1013 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_20.v common 11.89 vpr 70.29 MiB 0.14 10576 -1 -1 11 0.68 -1 -1 36936 -1 -1 137 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71980 22 19 1656 1505 1 1146 184 16 16 256 clb mult_36 auto 32.7 MiB 0.30 8226 19535 3061 14927 1547 70.3 MiB 0.35 0.01 14.4967 -584.138 -14.4967 14.4967 0.57 0.00393457 0.00358032 0.168607 0.15344 58 15564 50 6.2557e+06 4.02754e+06 820238. 3204.05 6.98 1.3782 1.22146 24072 200857 -1 13060 20 5925 12416 924193 221803 13.4156 13.4156 -768.957 -13.4156 0 0 1.02849e+06 4017.54 0.28 0.34 0.19 -1 -1 0.28 0.16696 0.149639 1054 1054 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_21.v common 15.54 vpr 70.82 MiB 0.09 10748 -1 -1 12 0.81 -1 -1 37008 -1 -1 145 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72520 22 19 1754 1586 1 1213 192 17 17 289 clb auto 33.6 MiB 0.30 9436 23971 4257 18177 1537 70.8 MiB 0.45 0.01 15.1206 -613.533 -15.1206 15.1206 0.65 0.00447903 0.00407881 0.226797 0.206229 60 17512 49 6.55708e+06 4.12398e+06 958460. 3316.47 10.01 1.45888 1.29374 27358 235245 -1 14560 18 6447 13271 1064829 240334 14.1746 14.1746 -764.795 -14.1746 0 0 1.19711e+06 4142.24 0.31 0.42 0.20 -1 -1 0.31 0.173969 0.156345 1115 1115 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_22.v common 11.30 vpr 71.59 MiB 0.15 10996 -1 -1 11 0.85 -1 -1 37792 -1 -1 154 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73308 22 19 1827 1659 1 1262 201 17 17 289 clb auto 34.2 MiB 0.33 9095 29013 5239 21338 2436 71.6 MiB 0.47 0.01 14.6828 -638.764 -14.6828 14.6828 0.64 0.00429262 0.00389892 0.233123 0.211587 64 16634 32 6.55708e+06 4.23247e+06 1.01866e+06 3524.77 5.32 1.32124 1.16817 28222 252754 -1 14512 23 6357 13024 1029780 236641 13.8083 13.8083 -765.715 -13.8083 0 0 1.27888e+06 4425.19 0.33 0.57 0.25 -1 -1 0.33 0.267912 0.242576 1169 1169 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_23.v common 15.76 vpr 71.86 MiB 0.14 11232 -1 -1 12 0.87 -1 -1 38128 -1 -1 157 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73580 22 19 1905 1720 1 1323 205 18 18 324 mult_36 auto 34.4 MiB 0.34 9808 34633 7458 24783 2392 71.9 MiB 0.59 0.01 14.9939 -659.479 -14.9939 14.9939 0.75 0.00453045 0.00412462 0.291424 0.264208 58 19445 41 7.67456e+06 4.66464e+06 1.07356e+06 3313.45 9.40 1.57466 1.39573 30840 265148 -1 16122 22 7808 16540 1310721 294165 14.0003 14.0003 -877.662 -14.0003 0 0 1.34501e+06 4151.27 0.37 0.54 0.24 -1 -1 0.37 0.228984 0.204045 1210 1210 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_24.v common 16.84 vpr 72.42 MiB 0.13 11360 -1 -1 12 0.93 -1 -1 36812 -1 -1 163 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74156 22 19 1979 1794 1 1362 211 18 18 324 mult_36 auto 35.0 MiB 0.36 10247 30307 5737 22712 1858 72.4 MiB 0.53 0.01 15.5582 -672.236 -15.5582 15.5582 0.77 0.00485803 0.00441306 0.256813 0.232741 64 18408 28 7.67456e+06 4.73696e+06 1.16663e+06 3600.72 10.39 2.12101 1.87481 32132 291232 -1 16259 20 7082 14613 1290097 280950 14.0222 14.0222 -882.314 -14.0222 0 0 1.46385e+06 4518.05 0.40 0.54 0.27 -1 -1 0.40 0.22467 0.202927 1265 1265 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_25.v common 15.82 vpr 73.32 MiB 0.17 11668 -1 -1 12 0.98 -1 -1 37456 -1 -1 174 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75084 22 19 2073 1871 1 1415 222 18 18 324 clb mult_36 auto 35.8 MiB 0.36 10262 31759 5655 24329 1775 73.3 MiB 0.54 0.01 15.2851 -698.101 -15.2851 15.2851 0.74 0.00493404 0.00448269 0.2635 0.238323 62 19471 45 7.67456e+06 4.86957e+06 1.13028e+06 3488.51 9.42 2.10207 1.85772 31488 277500 -1 15897 19 7242 15053 992914 233872 13.8751 13.8751 -842.351 -13.8751 0 0 1.39838e+06 4315.99 0.40 0.38 0.24 -1 -1 0.40 0.19889 0.1808 1322 1322 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_26.v common 17.70 vpr 73.64 MiB 0.16 11832 -1 -1 12 1.09 -1 -1 37448 -1 -1 180 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75408 22 19 2130 1928 1 1466 228 18 18 324 clb mult_36 auto 36.0 MiB 0.39 10652 35724 6736 26248 2740 73.6 MiB 0.62 0.01 15.3608 -721.142 -15.3608 15.3608 0.75 0.00597821 0.00546213 0.299863 0.271939 64 19028 28 7.67456e+06 4.9419e+06 1.16663e+06 3600.72 10.86 2.2653 1.99637 32132 291232 -1 16939 19 7400 15347 1200851 276434 14.0936 14.0936 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77720 22 19 2400 2164 1 1689 248 22 22 484 mult_36 auto 37.7 MiB 0.40 12158 39926 7813 29522 2591 75.0 MiB 0.70 0.01 14.8648 -767.523 -14.8648 14.8648 1.17 0.00572308 0.00520244 0.335179 0.302059 60 23104 32 1.25085e+07 5.95089e+06 1.69059e+06 3492.95 14.33 2.65821 2.35306 47054 420411 -1 20299 21 9082 18938 1454657 337588 13.6423 13.6423 -1032.35 -13.6423 0 0 2.10969e+06 4358.87 0.58 0.59 0.35 -1 -1 0.58 0.261257 0.233815 1537 1537 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_30.v common 21.29 vpr 75.84 MiB 0.13 12620 -1 -1 12 1.25 -1 -1 38124 -1 -1 209 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77656 22 19 2474 2238 1 1711 259 22 22 484 mult_36 auto 38.5 MiB 0.44 12757 40684 7873 30286 2525 75.8 MiB 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2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79624 22 19 2834 2564 1 1962 291 22 22 484 mult_36 auto 40.8 MiB 0.49 13536 57167 12483 41925 2759 77.8 MiB 0.93 0.01 16.4686 -958.47 -16.4686 16.4686 1.19 0.00655799 0.00594363 0.434681 0.391476 56 26290 37 1.25085e+07 6.8532e+06 1.62053e+06 3348.21 9.69 2.424 2.14289 45606 389969 -1 23558 19 10115 20843 1765620 396726 15.2737 15.2737 -1309.09 -15.2737 0 0 1.98725e+06 4105.89 0.55 0.71 0.33 -1 -1 0.55 0.295054 0.264891 1840 1840 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_35.v common 21.81 vpr 78.48 MiB 0.21 14128 -1 -1 13 1.46 -1 -1 40480 -1 -1 248 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80368 22 19 2941 2654 1 2054 299 22 22 484 mult_36 auto 41.8 MiB 0.51 15246 57242 12170 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85196 22 19 3689 3334 1 2572 370 24 24 576 mult_36 auto 46.4 MiB 0.65 18865 83971 19794 59912 4265 83.2 MiB 1.39 0.02 15.5441 -1198.02 -15.5441 15.5441 1.44 0.00874975 0.00795207 0.616877 0.549789 64 34373 50 1.51154e+07 8.57344e+06 2.13454e+06 3705.80 12.90 2.98074 2.63968 57414 536310 -1 30131 18 12902 26588 2258286 492592 14.6142 14.6142 -1654.43 -14.6142 0 0 2.67880e+06 4650.70 0.79 0.87 0.46 -1 -1 0.79 0.358025 0.321617 2415 2415 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_45.v common 32.60 vpr 91.75 MiB 0.28 16060 -1 -1 13 2.25 -1 -1 38912 -1 -1 321 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93956 22 19 3763 3391 1 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9.04176e+06 1.96475e+06 3411.02 50.72 4.39914 3.86705 55114 488114 -1 31826 21 13682 28559 2181283 495303 14.7048 14.7048 -1619.73 -14.7048 0 0 2.46106e+06 4272.68 0.71 0.97 0.39 -1 -1 0.71 0.432828 0.388718 2515 2515 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_47.v common 34.19 vpr 95.70 MiB 0.30 16696 -1 -1 13 2.35 -1 -1 42724 -1 -1 337 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 98000 22 19 3983 3594 1 2790 391 24 24 576 clb mult_36 auto 48.3 MiB 0.70 20826 97563 23505 69067 4991 85.4 MiB 1.57 0.02 16.1383 -1250.84 -16.1383 16.1383 1.41 0.00962343 0.00858643 0.672502 0.597474 68 35894 26 1.51154e+07 9.21054e+06 2.25030e+06 3906.77 21.08 4.40596 3.90419 58566 560801 -1 32368 22 13885 29969 2157797 487394 14.8224 14.8224 -1676.6 -14.8224 0 0 2.80126e+06 4863.30 0.78 0.98 0.47 -1 -1 0.78 0.459592 0.412945 2616 2616 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_48.v common 24.05 vpr 87.84 MiB 0.15 16744 -1 -1 13 2.49 -1 -1 38852 -1 -1 341 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89944 22 19 4025 3636 1 2807 395 24 24 576 clb mult_36 auto 49.0 MiB 0.65 20555 85827 18761 62689 4377 85.9 MiB 1.41 0.02 15.9366 -1257.71 -15.9366 15.9366 1.41 0.00929673 0.00841654 0.600275 0.534894 66 36074 31 1.51154e+07 9.25876e+06 2.19797e+06 3815.93 11.41 3.11841 2.75444 57990 550195 -1 32231 18 13521 28658 2093839 472895 14.6727 14.6727 -1673.74 -14.6727 0 0 2.74415e+06 4764.15 0.78 0.72 0.50 -1 -1 0.78 0.332776 0.301428 2639 2639 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_49.v common 37.25 vpr 99.59 MiB 0.28 17008 -1 -1 13 2.57 -1 -1 39368 -1 -1 355 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 101976 22 19 4164 3758 1 2908 410 25 25 625 clb auto 49.9 MiB 0.78 24013 87164 19079 63957 4128 86.7 MiB 1.53 0.03 16.6034 -1378.21 -16.6034 16.6034 1.65 0.0113847 0.0102893 0.659189 0.587169 74 38864 29 1.55855e+07 9.82352e+06 2.63203e+06 4211.25 23.48 4.53826 4.00027 65828 666824 -1 36038 21 13775 28917 2595162 541555 15.5436 15.5436 -1942.02 -15.5436 0 0 3.27126e+06 5234.01 0.97 1.01 0.54 -1 -1 0.97 0.381898 0.347421 2741 2741 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_50.v common 27.11 vpr 87.12 MiB 0.21 17160 -1 -1 13 2.59 -1 -1 39248 -1 -1 356 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89212 22 19 4190 3784 1 2926 411 25 25 625 clb auto 49.7 MiB 0.76 22437 93558 20689 67553 5316 86.7 MiB 1.50 0.02 16.4936 -1315.59 -16.4936 16.4936 1.59 0.00547894 0.00498528 0.640403 0.568865 66 39166 37 1.55855e+07 9.83558e+06 2.39749e+06 3835.99 12.82 3.14878 2.7644 62708 601000 -1 34785 23 14166 29888 2365680 520343 15.4749 15.4749 -1830.59 -15.4749 0 0 2.99279e+06 4788.46 0.94 1.16 0.55 -1 -1 0.94 0.542515 0.485758 2748 2748 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_51.v common 25.89 vpr 88.01 MiB 0.30 17380 -1 -1 13 2.75 -1 -1 43640 -1 -1 366 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90120 22 19 4305 3882 1 2980 421 25 25 625 clb auto 50.8 MiB 0.74 22535 99772 22908 71362 5502 87.8 MiB 1.63 0.03 16.3966 -1337.54 -16.3966 16.3966 1.58 0.0106801 0.00931618 0.693838 0.614797 66 38966 35 1.55855e+07 9.95613e+06 2.39749e+06 3835.99 11.41 3.27514 2.88885 62708 601000 -1 34679 18 14178 29765 2227761 499078 15.1266 15.1266 -2035.35 -15.1266 0 0 2.99279e+06 4788.46 0.89 0.97 0.52 -1 -1 0.89 0.436174 0.392121 2826 2826 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_52.v common 27.64 vpr 92.35 MiB 0.20 17548 -1 -1 13 2.75 -1 -1 39780 -1 -1 370 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94564 22 19 4363 3940 1 3039 425 25 25 625 clb auto 50.9 MiB 0.79 23857 97842 22331 71351 4160 87.9 MiB 1.71 0.02 16.7981 -1392.86 -16.7981 16.7981 1.62 0.00937252 0.0084418 0.734853 0.652986 70 40949 38 1.55855e+07 1.00044e+07 2.52006e+06 4032.10 12.89 3.29691 2.90817 64580 638411 -1 36845 20 14992 31313 2738027 581899 15.2222 15.2222 -1993.63 -15.2222 0 0 3.16512e+06 5064.19 0.94 1.13 0.54 -1 -1 0.94 0.475349 0.426546 2865 2865 -1 -1 -1 -1 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_14.v common 7.17 vpr 71.81 MiB 0.07 10472 -1 -1 1 0.25 -1 -1 35508 -1 -1 125 22 0 4 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73532 22 19 1974 1653 1 1039 170 16 16 256 mult_36 auto 34.2 MiB 0.37 6283 25550 5428 17285 2837 71.8 MiB 0.45 0.01 4.18011 -1206.26 -4.18011 4.18011 0.57 0.00350846 0.00313293 0.213571 0.191347 44 12375 36 6.32612e+06 3.15375e+06 649498. 2537.10 2.89 0.908391 0.79608 22336 155612 -1 8982 15 3271 4074 387555 98826 4.36136 4.36136 -1211.82 -4.36136 0 0 820238. 3204.05 0.21 0.22 0.14 -1 -1 0.21 0.128601 0.11497 955 708 247 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_15.v common 9.37 vpr 72.36 MiB 0.08 10772 -1 -1 1 0.26 -1 -1 36860 -1 -1 134 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74096 22 19 2144 1789 1 1138 180 16 16 256 clb mult_36 auto 35.1 MiB 0.36 6909 28120 5467 19449 3204 72.4 MiB 0.33 0.01 4.19358 -1335.76 -4.19358 4.19358 0.57 0.0037113 0.00333884 0.133605 0.11961 46 11544 32 6.32612e+06 3.66277e+06 684529. 2673.94 5.06 1.22954 1.06767 22592 160355 -1 9200 15 3275 3934 333576 89258 4.24116 4.24116 -1301.9 -4.24116 0 0 838722. 3276.26 0.23 0.23 0.14 -1 -1 0.23 0.139646 0.124395 1035 769 266 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_16.v common 10.35 vpr 73.17 MiB 0.07 10912 -1 -1 1 0.23 -1 -1 36864 -1 -1 139 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74924 22 19 2218 1846 1 1177 185 16 16 256 clb mult_36 auto 35.7 MiB 0.41 6963 25959 4805 17669 3485 73.2 MiB 0.45 0.01 4.07338 -1365.88 -4.07338 4.07338 0.56 0.00388045 0.00348674 0.208146 0.187017 46 13890 41 6.32612e+06 3.72556e+06 684529. 2673.94 5.69 1.29537 1.13495 22592 160355 -1 10116 19 3779 4592 448481 113412 4.24116 4.24116 -1370.82 -4.24116 0 0 838722. 3276.26 0.23 0.27 0.15 -1 -1 0.23 0.169377 0.15002 1073 788 285 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_17.v common 8.34 vpr 74.82 MiB 0.14 11732 -1 -1 1 0.25 -1 -1 36588 -1 -1 159 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76620 22 19 2536 2130 1 1298 205 17 17 289 clb auto 37.6 MiB 0.46 7620 37049 7684 25247 4118 74.8 MiB 0.62 0.01 4.42051 -1540.01 -4.42051 4.42051 0.65 0.00423609 0.00378899 0.282318 0.252374 46 13764 27 6.64007e+06 3.97672e+06 782063. 2706.10 3.04 1.04231 0.91148 25426 183746 -1 11043 17 4001 4900 453425 123152 4.24116 4.24116 -1541.83 -4.24116 0 0 958460. 3316.47 0.26 0.29 0.16 -1 -1 0.26 0.177466 0.157705 1228 924 304 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_18.v common 8.78 vpr 75.02 MiB 0.10 11952 -1 -1 1 0.31 -1 -1 37072 -1 -1 165 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76816 22 19 2610 2187 1 1336 211 17 17 289 clb auto 37.7 MiB 0.48 8349 34696 7275 23014 4407 75.0 MiB 0.58 0.01 4.13813 -1586.39 -4.13813 4.13813 0.66 0.00439442 0.00392502 0.267351 0.239362 48 14562 33 6.64007e+06 4.05207e+06 816265. 2824.45 3.48 1.13466 0.990693 25714 189529 -1 11938 15 4344 5163 568179 146907 4.36136 4.36136 -1641.57 -4.36136 0 0 986792. 3414.50 0.26 0.33 0.17 -1 -1 0.26 0.173087 0.154333 1266 943 323 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_19.v common 9.22 vpr 76.04 MiB 0.12 12208 -1 -1 1 0.32 -1 -1 36792 -1 -1 174 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77860 22 19 2778 2321 1 1434 221 18 18 324 clb auto 38.8 MiB 0.56 8435 36906 7335 26151 3420 76.0 MiB 0.62 0.01 4.18011 -1706.23 -4.18011 4.18011 0.77 0.00463437 0.00415387 0.27846 0.249498 44 15275 31 7.77114e+06 4.56109e+06 850563. 2625.19 3.39 1.13425 0.990832 28700 205432 -1 11863 18 4157 5289 458211 127186 4.36136 4.36136 -1720.9 -4.36136 0 0 1.07356e+06 3313.45 0.29 0.31 0.17 -1 -1 0.29 0.197713 0.175468 1344 1002 342 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_20.v common 10.57 vpr 76.70 MiB 0.11 12456 -1 -1 1 0.33 -1 -1 36984 -1 -1 178 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78536 22 19 2852 2378 1 1479 225 18 18 324 clb auto 39.2 MiB 0.58 8723 40581 8381 28372 3828 76.7 MiB 0.68 0.01 4.13813 -1771.41 -4.13813 4.13813 0.77 0.00494821 0.00443889 0.30125 0.269261 46 14626 20 7.77114e+06 4.61132e+06 895831. 2764.91 4.55 1.42369 1.24659 29024 211752 -1 12101 15 4346 5256 526214 143468 4.24116 4.24116 -1780.8 -4.24116 0 0 1.09776e+06 3388.15 0.30 0.31 0.19 -1 -1 0.30 0.17954 0.16092 1382 1021 361 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_21.v common 10.05 vpr 77.91 MiB 0.15 12852 -1 -1 1 0.36 -1 -1 37596 -1 -1 190 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79784 22 19 3057 2549 1 1586 237 18 18 324 clb auto 40.7 MiB 0.63 10000 39086 7340 28690 3056 77.9 MiB 0.81 0.01 4.36136 -1893.99 -4.36136 4.36136 0.82 0.005902 0.00531029 0.341896 0.304488 46 17097 24 7.77114e+06 4.76202e+06 895831. 2764.91 3.74 1.26578 1.10779 29024 211752 -1 13601 15 4515 5613 518271 136937 4.36136 4.36136 -1963.24 -4.36136 0 0 1.09776e+06 3388.15 0.29 0.31 0.18 -1 -1 0.29 0.186915 0.166708 1479 1099 380 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_22.v common 13.34 vpr 77.94 MiB 0.11 13080 -1 -1 1 0.25 -1 -1 38084 -1 -1 196 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79812 22 19 3131 2606 1 1626 243 19 19 361 clb auto 40.8 MiB 0.63 10581 47239 9889 33869 3481 77.9 MiB 0.87 0.01 4.48156 -1979.61 -4.48156 4.48156 0.90 0.00552736 0.00497025 0.378449 0.337682 48 18758 47 8.13532e+06 4.83737e+06 1.05176e+06 2913.46 6.65 1.84109 1.60475 32602 246183 -1 15477 18 5270 6461 700019 166552 4.36136 4.36136 -2014.15 -4.36136 0 0 1.27108e+06 3521.00 0.35 0.38 0.21 -1 -1 0.35 0.216509 0.191988 1517 1118 399 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_23.v common 11.22 vpr 79.36 MiB 0.16 13248 -1 -1 1 0.36 -1 -1 37868 -1 -1 206 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81260 22 19 3301 2742 1 1720 254 19 19 361 clb auto 42.2 MiB 0.60 10777 53318 12123 37751 3444 79.4 MiB 0.92 0.01 4.30038 -2073.95 -4.30038 4.30038 0.85 0.00592401 0.00523054 0.407801 0.364218 54 17563 25 8.13532e+06 5.35895e+06 1.15452e+06 3198.10 4.34 1.72645 1.50918 34042 276675 -1 14742 16 4950 6056 567418 143713 4.36136 4.36136 -2093.48 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-1 1 0.30 -1 -1 38104 -1 -1 225 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82628 22 19 3615 3005 1 1878 273 20 20 400 clb auto 43.8 MiB 0.73 12783 60453 13305 42245 4903 80.7 MiB 1.08 0.01 4.29513 -2284.67 -4.29513 4.29513 0.94 0.00615409 0.00550465 0.468509 0.418359 50 22427 38 1.10386e+07 5.59755e+06 1.21483e+06 3037.08 6.84 2.14736 1.8751 36870 282114 -1 18002 16 6329 7668 826615 201907 4.48156 4.48156 -2405 -4.48156 0 0 1.45344e+06 3633.59 0.46 0.44 0.26 -1 -1 0.46 0.240524 0.214471 1749 1293 456 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_26.v common 27.65 vpr 81.20 MiB 0.21 14084 -1 -1 1 0.44 -1 -1 38468 -1 -1 230 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83144 22 19 3689 3062 1 1918 278 20 20 400 clb auto 44.4 MiB 0.67 12259 59233 12310 41511 5412 81.2 MiB 1.01 0.01 4.13813 -2292.86 -4.13813 4.13813 0.97 0.0059514 0.00531072 0.419469 0.371454 46 22560 47 1.10386e+07 5.66034e+06 1.11552e+06 2788.80 19.94 2.92269 2.53164 36070 264401 -1 16932 14 5898 7281 710408 180437 4.36136 4.36136 -2399.27 -4.36136 0 0 1.36764e+06 3419.10 0.38 0.46 0.24 -1 -1 0.38 0.266686 0.241179 1787 1312 475 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_27.v common 38.14 vpr 82.61 MiB 0.14 14440 -1 -1 1 0.47 -1 -1 38408 -1 -1 242 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84596 22 19 3871 3210 1 2023 291 21 21 441 clb auto 45.6 MiB 0.77 12969 62951 13572 44045 5334 82.6 MiB 1.11 0.01 4.36136 -2529.89 -4.36136 4.36136 1.08 0.00661824 0.0059161 0.478655 0.426406 48 24732 39 1.14404e+07 6.20704e+06 1.29409e+06 2934.45 29.79 3.13754 2.72999 40046 303487 -1 19419 15 6942 8722 1093050 248022 4.48156 4.48156 -2651.69 -4.48156 0 0 1.56480e+06 3548.29 0.44 0.48 0.21 -1 -1 0.44 0.242647 0.21615 1879 1385 494 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_28.v common 14.38 vpr 82.73 MiB 0.19 14620 -1 -1 1 0.54 -1 -1 38548 -1 -1 247 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84716 22 19 3945 3267 1 2070 296 21 21 441 clb auto 45.8 MiB 0.77 13605 63400 13597 45154 4649 82.7 MiB 1.18 0.02 4.24116 -2495.55 -4.24116 4.24116 1.09 0.00697535 0.00626872 0.499185 0.445723 52 23436 41 1.14404e+07 6.26983e+06 1.38344e+06 3137.06 5.84 2.26323 1.98047 41366 331634 -1 18697 14 6169 7747 801288 198953 4.36136 4.36136 -2569.18 -4.36136 0 0 1.70223e+06 3859.94 0.46 0.38 0.28 -1 -1 0.46 0.213995 0.190374 1917 1404 513 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_29.v common 18.09 vpr 84.27 MiB 0.15 14936 -1 -1 1 0.52 -1 -1 39648 -1 -1 260 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86288 22 19 4159 3447 1 2186 310 22 22 484 mult_36 auto 47.3 MiB 0.79 14251 75766 16916 53468 5382 84.3 MiB 1.32 0.02 4.30038 -2650.53 -4.30038 4.30038 1.21 0.006988 0.00623253 0.5503 0.488282 48 24770 32 1.26594e+07 6.82908e+06 1.44011e+06 2975.42 9.09 2.32987 2.03802 44390 338934 -1 20456 14 6939 8707 972163 230644 4.48156 4.48156 -2836.1 -4.48156 0 0 1.74100e+06 3597.11 0.51 0.46 0.24 -1 -1 0.51 0.2421 0.216208 2023 1491 532 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_30.v common 21.30 vpr 84.31 MiB 0.19 15188 -1 -1 1 0.53 -1 -1 40780 -1 -1 265 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86336 22 19 4233 3504 1 2225 315 22 22 484 mult_36 auto 47.5 MiB 0.83 14490 83853 20335 56854 6664 84.3 MiB 1.46 0.02 4.24116 -2618.51 -4.24116 4.24116 1.24 0.00714772 0.00637711 0.605622 0.537951 50 25164 32 1.26594e+07 6.89187e+06 1.50222e+06 3103.76 11.74 2.89467 2.5294 44874 350400 -1 20610 14 7194 8993 921636 226843 4.36136 4.36136 -2766.51 -4.36136 0 0 1.79645e+06 3711.66 0.50 0.49 0.28 -1 -1 0.50 0.274395 0.24729 2061 1510 551 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_31.v common 19.45 vpr 85.30 MiB 0.14 15440 -1 -1 1 0.52 -1 -1 40928 -1 -1 276 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87344 22 19 4410 3647 1 2335 326 22 22 484 clb mult_36 auto 48.5 MiB 0.78 16122 77675 17613 54161 5901 85.3 MiB 1.36 0.02 4.36136 -2880.63 -4.36136 4.36136 1.23 0.0075266 0.00673816 0.559591 0.497527 50 27001 29 1.26594e+07 7.03001e+06 1.50222e+06 3103.76 9.88 2.41232 2.1093 44874 350400 -1 22573 15 7610 9869 1093468 253767 4.48156 4.48156 -2966.78 -4.48156 0 0 1.79645e+06 3711.66 0.58 0.52 0.31 -1 -1 0.58 0.262899 0.235664 2148 1578 570 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_32.v common 30.33 vpr 85.77 MiB 0.20 15712 -1 -1 1 0.44 -1 -1 40580 -1 -1 280 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87824 22 19 4484 3704 1 2374 330 22 22 484 clb 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1.65241e+06 3123.66 33.77 3.95648 3.4406 48882 385791 -1 23998 15 7697 10016 1012708 239734 4.48156 4.48156 -3211.65 -4.48156 0 0 1.97533e+06 3734.07 0.57 0.54 0.32 -1 -1 0.57 0.296085 0.263436 2364 1756 608 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_34.v common 16.82 vpr 88.21 MiB 0.18 16652 -1 -1 1 0.72 -1 -1 41604 -1 -1 309 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90328 22 19 4917 4086 1 2542 360 23 23 529 clb auto 51.3 MiB 0.85 16883 87400 19509 61991 5900 88.2 MiB 1.45 0.02 4.2946 -3132.19 -4.2946 4.2946 1.29 0.00788218 0.006887 0.570903 0.502905 48 29983 34 1.31115e+07 7.84042e+06 1.58369e+06 2993.75 6.73 2.19272 1.90211 48354 373213 -1 24232 15 8519 10539 1178068 279978 4.36136 4.36136 -3239.06 -4.36136 0 0 1.91452e+06 3619.14 0.54 0.55 0.30 -1 -1 0.54 0.289307 0.25688 2402 1775 627 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_35.v common 18.89 vpr 88.98 MiB 0.23 17056 -1 -1 1 0.65 -1 -1 41752 -1 -1 320 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91120 22 19 5093 4228 1 2643 371 23 23 529 clb auto 52.3 MiB 0.97 16361 88283 19281 62146 6856 89.0 MiB 1.56 0.02 4.18011 -3243.72 -4.18011 4.18011 1.43 0.0101303 0.009037 0.622098 0.552535 54 27381 34 1.31115e+07 7.97856e+06 1.73850e+06 3286.39 8.20 2.81154 2.4584 50466 419205 -1 22379 15 7580 9662 963966 246031 4.36136 4.36136 -3289.45 -4.36136 0 0 2.13727e+06 4040.20 0.64 0.58 0.34 -1 -1 0.64 0.341484 0.306495 2488 1842 646 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_36.v common 29.16 vpr 89.19 MiB 0.26 17120 -1 -1 1 0.71 -1 -1 41720 -1 -1 324 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91328 22 19 5167 4285 1 2691 375 23 23 529 clb auto 52.7 MiB 0.95 18019 98998 23016 68009 7973 89.2 MiB 1.69 0.02 4.25463 -3294.79 -4.25463 4.25463 1.31 0.00840097 0.00747584 0.671425 0.595096 56 29248 46 1.31115e+07 8.02879e+06 1.78215e+06 3368.90 18.21 4.18849 3.64695 50994 430361 -1 25192 17 8520 10780 1168967 288965 4.24116 4.24116 -3384.13 -4.24116 0 0 2.18505e+06 4130.54 0.60 0.66 0.38 -1 -1 0.60 0.36118 0.320109 2526 1861 665 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_37.v common 26.20 vpr 91.57 MiB 0.23 17756 -1 -1 1 0.69 -1 -1 40880 -1 -1 337 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93768 22 19 5380 4464 1 2808 389 24 24 576 clb mult_36 auto 53.9 MiB 1.06 18769 112490 27337 77347 7806 90.5 MiB 2.04 0.02 4.24116 -3467.58 -4.24116 4.24116 1.46 0.00907631 0.00809949 0.782821 0.686432 50 31438 37 1.52924e+07 8.58805e+06 1.78400e+06 3097.22 14.29 3.93921 3.43732 53074 415989 -1 26089 15 8677 10964 1154625 282675 4.36136 4.36136 -3530.32 -4.36136 0 0 2.13454e+06 3705.80 0.73 0.62 0.36 -1 -1 0.73 0.345649 0.311132 2631 1947 684 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_38.v common 22.31 vpr 91.45 MiB 0.17 17708 -1 -1 1 0.73 -1 -1 42384 -1 -1 343 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93644 22 19 5454 4521 1 2849 395 24 24 576 clb mult_36 auto 55.0 MiB 0.90 19940 116235 27981 79411 8843 91.4 MiB 2.02 0.02 4.36136 -3489.43 -4.36136 4.36136 1.56 0.00865726 0.0076673 0.789594 0.698073 50 33618 45 1.52924e+07 8.66339e+06 1.78400e+06 3097.22 10.80 3.19398 2.7774 53074 415989 -1 27632 15 9105 11562 1231630 291884 4.48156 4.48156 -3625.47 -4.48156 0 0 2.13454e+06 3705.80 0.60 0.62 0.28 -1 -1 0.60 0.337085 0.300387 2669 1966 703 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_39.v common 25.88 vpr 91.90 MiB 0.28 18160 -1 -1 1 0.76 -1 -1 40224 -1 -1 353 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94108 22 19 5629 4662 1 2951 405 25 25 625 clb auto 55.4 MiB 1.14 19953 114177 27339 77982 8856 91.9 MiB 1.99 0.02 4.36136 -3656.12 -4.36136 4.36136 1.69 0.0096819 0.00860995 0.788368 0.696843 50 35626 42 1.57822e+07 8.78897e+06 1.94653e+06 3114.45 13.53 3.34528 2.91404 57408 454416 -1 28298 13 9542 11975 1300975 310972 4.48156 4.48156 -3801.9 -4.48156 0 0 2.32897e+06 3726.35 0.78 0.61 0.33 -1 -1 0.78 0.323378 0.290166 2754 2032 722 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_40.v common 26.67 vpr 92.66 MiB 0.30 18280 -1 -1 1 0.77 -1 -1 42276 -1 -1 358 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94880 22 19 5703 4719 1 2994 410 25 25 625 clb auto 56.3 MiB 1.08 21027 114560 27826 78845 7889 92.7 MiB 2.12 0.02 4.24116 -3663.98 -4.24116 4.24116 1.63 0.00961592 0.0085823 0.754727 0.666265 54 36082 37 1.57822e+07 8.85176e+06 2.04878e+06 3278.05 13.97 3.29258 2.87627 59280 493784 -1 28451 13 8976 11375 1210126 295638 4.60176 4.60176 -3737.01 -4.60176 0 0 2.52006e+06 4032.10 0.74 0.60 0.40 -1 -1 0.74 0.322934 0.288973 2792 2051 741 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_41.v common 20.61 vpr 94.05 MiB 0.26 18812 -1 -1 1 0.79 -1 -1 41700 -1 -1 374 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 96312 22 19 5950 4932 1 3111 427 25 25 625 clb auto 57.5 MiB 1.20 20818 125773 30837 85286 9650 94.1 MiB 2.17 0.03 4.42051 -3821.28 -4.42051 4.42051 1.63 0.00988404 0.0088336 0.857002 0.754623 52 33687 24 1.57822e+07 9.44869e+06 1.99531e+06 3192.49 6.87 2.69468 2.36476 58656 480125 -1 27916 13 8776 11804 1123040 278330 4.60176 4.60176 -3900.78 -4.60176 0 0 2.45448e+06 3927.17 0.96 0.67 0.44 -1 -1 0.96 0.380177 0.346074 2913 2153 760 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_42.v common 21.94 vpr 94.25 MiB 0.28 18964 -1 -1 1 0.87 -1 -1 42876 -1 -1 377 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 96512 22 19 6024 4989 1 3151 430 25 25 625 clb auto 57.6 MiB 1.16 21903 126946 30063 87199 9684 94.2 MiB 2.26 0.03 4.36136 -3905.46 -4.36136 4.36136 1.66 0.0103375 0.00920788 0.868049 0.767092 54 34451 19 1.57822e+07 9.48637e+06 2.04878e+06 3278.05 8.66 3.34036 2.92748 59280 493784 -1 29343 13 9076 11896 1099829 264107 4.48156 4.48156 -4076.71 -4.48156 0 0 2.52006e+06 4032.10 0.77 0.60 0.42 -1 -1 0.77 0.340296 0.305387 2951 2172 779 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_43.v common 23.19 vpr 95.80 MiB 0.31 19404 -1 -1 1 0.89 -1 -1 43328 -1 -1 389 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 98104 22 19 6198 5129 1 3252 442 25 25 625 clb auto 59.1 MiB 1.21 22747 131716 31686 89081 10949 95.8 MiB 2.33 0.03 4.37853 -4053.38 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4.48156 4.48156 -4398.9 -4.48156 0 0 2.70930e+06 4007.84 0.83 0.64 0.45 -1 -1 0.83 0.357413 0.31977 3073 2256 817 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_45.v common 28.04 vpr 96.83 MiB 0.32 19964 -1 -1 1 0.91 -1 -1 43712 -1 -1 407 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 99156 22 19 6485 5365 1 3415 461 26 26 676 clb auto 60.4 MiB 1.17 21937 142861 34619 98677 9565 96.8 MiB 2.51 0.03 4.37853 -4161.26 -4.37853 4.37853 1.72 0.0108605 0.00967532 0.949021 0.832038 54 35587 27 1.91291e+07 1.02591e+07 2.26288e+06 3347.46 13.68 3.78755 3.32727 65792 548382 -1 29674 14 9521 12541 1199994 291317 4.60176 4.60176 -4732.88 -4.60176 0 0 2.78165e+06 4114.86 0.80 0.67 0.46 -1 -1 0.80 0.40794 0.367144 3178 2342 836 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_46.v common 50.52 vpr 97.72 MiB 0.22 20072 -1 -1 1 0.91 -1 -1 44016 -1 -1 412 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100068 22 19 6559 5422 1 3449 466 26 26 676 clb auto 60.7 MiB 1.21 23538 148558 36858 101207 10493 97.3 MiB 2.54 0.03 4.36136 -4211.81 -4.36136 4.36136 1.74 0.012603 0.01142 0.948557 0.83767 50 37784 24 1.91291e+07 1.03219e+07 2.15046e+06 3181.16 36.51 5.75007 5.01756 63768 504694 -1 31931 15 10220 12587 1272284 312759 4.48156 4.48156 -4493.44 -4.48156 0 0 2.57128e+06 3803.68 0.75 0.74 0.39 -1 -1 0.75 0.42784 0.384383 3216 2361 855 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_47.v common 23.60 vpr 99.03 MiB 0.22 20368 -1 -1 1 0.93 -1 -1 44564 -1 -1 422 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 101408 22 19 6735 5564 1 3561 476 26 26 676 clb auto 62.5 MiB 1.21 24114 145322 35443 99736 10143 99.0 MiB 2.73 0.03 4.36136 -4363.73 -4.36136 4.36136 1.76 0.0129397 0.011653 1.1003 0.97872 52 40909 29 1.91291e+07 1.04475e+07 2.20423e+06 3260.69 8.77 3.41046 3.00851 65116 533202 -1 32715 14 10296 12618 1300621 315598 4.60176 4.60176 -4478.39 -4.60176 0 0 2.70930e+06 4007.84 0.98 0.71 0.46 -1 -1 0.98 0.408648 0.366685 3302 2428 874 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_48.v common 27.73 vpr 100.63 MiB 0.30 20524 -1 -1 1 0.97 -1 -1 44032 -1 -1 428 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 103044 22 19 6809 5621 1 3598 482 26 26 676 clb auto 63.0 MiB 1.28 25457 151602 37795 102913 10894 98.7 MiB 2.57 0.03 4.36136 -4421.6 -4.36136 4.36136 1.76 0.0110835 0.0098763 0.963183 0.849135 54 40678 40 1.91291e+07 1.05228e+07 2.26288e+06 3347.46 13.20 4.51534 3.96596 65792 548382 -1 33773 15 10421 12979 1342589 331991 4.48156 4.48156 -4589.32 -4.48156 0 0 2.78165e+06 4114.86 0.79 0.71 0.44 -1 -1 0.79 0.406414 0.361218 3340 2447 893 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_49.v common 28.81 vpr 101.54 MiB 0.32 21104 -1 -1 1 1.05 -1 -1 44376 -1 -1 444 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 103976 22 19 7094 5872 1 3718 499 27 27 729 clb auto 64.4 MiB 1.35 27242 166651 41903 114568 10180 100.2 MiB 3.09 0.03 4.48156 -4645.19 -4.48156 4.48156 1.93 0.0137483 0.0124058 1.21856 1.07489 54 44469 28 1.9669e+07 1.11198e+07 2.44988e+06 3360.60 12.93 4.26154 3.72779 70678 594165 -1 36864 15 11534 14523 1551802 366884 4.60176 4.60176 -5029.95 -4.60176 0 0 3.01106e+06 4130.40 0.86 0.80 0.49 -1 -1 0.86 0.436947 0.390212 3481 2569 912 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_50.v common 38.24 vpr 104.04 MiB 0.22 21184 -1 -1 1 0.99 -1 -1 44140 -1 -1 449 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 106532 22 19 7168 5929 1 3755 504 27 27 729 clb auto 65.1 MiB 1.38 27900 166919 41558 115070 10291 101.0 MiB 3.07 0.03 4.42058 -4700.51 -4.42058 4.42058 1.95 0.0133138 0.0119708 1.19493 1.0588 54 46623 41 1.9669e+07 1.11825e+07 2.44988e+06 3360.60 22.19 5.22553 4.55891 70678 594165 -1 37253 16 11580 14881 1507663 361077 4.48156 4.48156 -4833.63 -4.48156 0 0 3.01106e+06 4130.40 0.95 0.82 0.47 -1 -1 0.95 0.462516 0.412714 3519 2588 931 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_51.v common 59.87 vpr 106.14 MiB 0.31 21572 -1 -1 1 1.08 -1 -1 44824 -1 -1 460 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 108688 22 19 7344 6071 1 3863 515 27 27 729 clb auto 65.7 MiB 1.37 26191 173807 44357 119669 9781 101.5 MiB 3.15 0.04 4.4148 -4780.65 -4.4148 4.4148 1.97 0.0143687 0.0128847 1.21421 1.07263 54 42070 24 1.9669e+07 1.13207e+07 2.44988e+06 3360.60 43.33 5.82771 5.07827 70678 594165 -1 35404 13 11033 14165 1456223 354857 4.72196 4.72196 -5030.57 -4.72196 0 0 3.01106e+06 4130.40 0.98 0.78 0.49 -1 -1 0.98 0.425101 0.38117 3605 2655 950 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_52.v common 28.61 vpr 106.45 MiB 0.25 21884 -1 -1 1 1.15 -1 -1 45220 -1 -1 465 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 109004 22 19 7418 6128 1 3909 520 27 27 729 clb auto 66.5 MiB 1.34 28280 178170 45981 119497 12692 102.4 MiB 3.22 0.04 4.37853 -4830.08 -4.37853 4.37853 1.95 0.0141499 0.0123272 1.23818 1.08169 54 45707 28 1.9669e+07 1.13835e+07 2.44988e+06 3360.60 12.27 4.30066 3.76467 70678 594165 -1 38034 16 11980 15124 1623681 386703 4.48156 4.48156 -5051.95 -4.48156 0 0 3.01106e+06 4130.40 0.84 0.80 0.46 -1 -1 0.84 0.496756 0.440935 3643 2674 969 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_14.v common 9.41 vpr 67.30 MiB 0.06 9328 -1 -1 1 0.16 -1 -1 34656 -1 -1 81 22 0 4 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68916 22 19 1246 925 1 736 126 16 16 256 mult_36 auto 29.6 MiB 0.40 4254 18396 4205 11555 2636 67.3 MiB 0.34 0.01 8.36318 -383.367 -8.36318 8.36318 0.56 0.00278544 0.00258491 0.159571 0.146202 38 8861 34 6.32612e+06 2.6012e+06 558663. 2182.28 5.53 1.07474 0.945186 21316 135884 -1 6561 22 4832 5445 582149 154526 7.80999 7.80999 -388.43 -7.80999 0 0 744679. 2908.90 0.19 0.26 0.12 -1 -1 0.19 0.118783 0.105935 591 344 247 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_15.v common 7.62 vpr 67.93 MiB 0.07 9716 -1 -1 1 0.16 -1 -1 35136 -1 -1 86 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69556 22 19 1344 989 1 796 132 16 16 256 mult_36 auto 30.3 MiB 0.37 4680 18892 4302 11939 2651 67.9 MiB 0.37 0.01 8.43996 -390.118 -8.43996 8.43996 0.57 0.00280472 0.00258568 0.168314 0.15441 40 9059 33 6.32612e+06 3.05999e+06 583096. 2277.72 3.69 0.787018 0.698129 21572 140635 -1 7624 21 5398 6282 743093 192604 7.99439 7.99439 -467.887 -7.99439 0 0 763333. 2981.77 0.19 0.28 0.13 -1 -1 0.19 0.117461 0.104846 635 369 266 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_16.v common 22.21 vpr 68.30 MiB 0.07 9588 -1 -1 1 0.20 -1 -1 35172 -1 -1 91 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69944 22 19 1418 1046 1 833 137 16 16 256 mult_36 auto 30.8 MiB 0.46 5124 23788 5451 15273 3064 68.3 MiB 0.47 0.01 8.48338 -427.318 -8.48338 8.48338 0.59 0.00324841 0.00298687 0.205054 0.187831 40 9542 34 6.32612e+06 3.12278e+06 583096. 2277.72 17.80 1.58883 1.40324 21572 140635 -1 7989 24 5937 6919 778879 198407 8.18279 8.18279 -520.319 -8.18279 0 0 763333. 2981.77 0.19 0.33 0.13 -1 -1 0.19 0.146991 0.131238 673 388 285 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_17.v common 11.74 vpr 69.05 MiB 0.12 10252 -1 -1 1 0.22 -1 -1 35376 -1 -1 97 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70708 22 19 1518 1112 1 899 143 16 16 256 mult_36 auto 31.4 MiB 0.43 5605 24761 5724 15848 3189 69.1 MiB 0.50 0.01 9.23404 -471.583 -9.23404 9.23404 0.57 0.00299432 0.00271579 0.215328 0.196431 42 12302 48 6.32612e+06 3.19813e+06 613404. 2396.11 7.17 1.52838 1.35187 21828 146600 -1 8704 23 6699 7694 985071 246811 9.15065 9.15065 -572.903 -9.15065 0 0 784202. 3063.29 0.27 0.40 0.13 -1 -1 0.27 0.157069 0.140898 719 415 304 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_18.v common 14.27 vpr 69.80 MiB 0.10 10300 -1 -1 1 0.23 -1 -1 34916 -1 -1 102 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71472 22 19 1592 1169 1 937 148 16 16 256 mult_36 auto 32.0 MiB 0.48 5411 25954 5761 17040 3153 69.8 MiB 0.50 0.01 9.11384 -492.872 -9.11384 9.11384 0.57 0.00308504 0.00279575 0.215571 0.196214 40 10608 35 6.32612e+06 3.26092e+06 583096. 2277.72 9.65 1.42462 1.25955 21572 140635 -1 9003 23 6783 7936 948207 245104 8.48265 8.48265 -629.25 -8.48265 0 0 763333. 2981.77 0.22 0.37 0.14 -1 -1 0.22 0.155053 0.138515 757 434 323 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_19.v common 11.00 vpr 70.22 MiB 0.11 10544 -1 -1 1 0.21 -1 -1 35336 -1 -1 107 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71904 22 19 1688 1231 1 998 154 16 16 256 mult_36 auto 32.6 MiB 0.51 5851 22814 4729 13760 4325 70.2 MiB 0.46 0.01 9.12484 -496.487 -9.12484 9.12484 0.56 0.00337278 0.00308981 0.204978 0.187705 46 11198 40 6.32612e+06 3.71971e+06 684529. 2673.94 6.64 1.44049 1.27621 22592 160355 -1 8482 21 5296 6099 654272 170198 8.26205 8.26205 -572.735 -8.26205 0 0 838722. 3276.26 0.21 0.29 0.11 -1 -1 0.21 0.143728 0.128598 799 457 342 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_20.v common 12.00 vpr 70.56 MiB 0.08 10640 -1 -1 1 0.25 -1 -1 35548 -1 -1 112 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72256 22 19 1762 1288 1 1033 159 16 16 256 mult_36 auto 32.8 MiB 0.48 6825 22089 4646 13915 3528 70.6 MiB 0.47 0.01 9.16401 -519.117 -9.16401 9.16401 0.56 0.00360731 0.00330817 0.190943 0.174072 50 11241 25 6.32612e+06 3.7825e+06 744679. 2908.90 7.42 1.37001 1.20992 23104 171162 -1 9261 21 5709 6587 736555 189282 8.39745 8.39745 -613.624 -8.39745 0 0 891356. 3481.86 0.24 0.34 0.17 -1 -1 0.24 0.158795 0.142393 837 476 361 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_21.v common 10.24 vpr 70.94 MiB 0.09 10924 -1 -1 1 0.23 -1 -1 35780 -1 -1 119 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72640 22 19 1859 1351 1 1097 166 16 16 256 mult_36 auto 33.3 MiB 0.47 6666 26158 5203 16523 4432 70.9 MiB 0.50 0.01 9.03763 -508.506 -9.03763 9.03763 0.56 0.00365336 0.00334877 0.220005 0.200745 48 12141 45 6.32612e+06 3.8704e+06 714410. 2790.66 5.70 1.21186 1.07324 22848 165380 -1 9960 23 6766 7896 953019 239000 8.21605 8.21605 -705.722 -8.21605 0 0 863353. 3372.47 0.22 0.38 0.16 -1 -1 0.22 0.175403 0.156387 880 500 380 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_22.v common 8.72 vpr 71.55 MiB 0.14 11048 -1 -1 1 0.26 -1 -1 35832 -1 -1 123 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73272 22 19 1933 1408 1 1134 170 16 16 256 mult_36 auto 33.8 MiB 0.52 7313 28370 5828 17736 4806 71.6 MiB 0.56 0.01 9.17501 -549.932 -9.17501 9.17501 0.56 0.00368249 0.0033307 0.236244 0.214884 48 12035 28 6.32612e+06 3.92063e+06 714410. 2790.66 3.90 0.984652 0.872973 22848 165380 -1 10062 23 6419 7390 836835 213069 8.51065 8.51065 -667.103 -8.51065 0 0 863353. 3372.47 0.23 0.38 0.16 -1 -1 0.23 0.181923 0.162592 918 519 399 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_23.v common 13.10 vpr 71.78 MiB 0.12 11476 -1 -1 1 0.26 -1 -1 36084 -1 -1 131 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73504 22 19 2031 1472 1 1198 179 18 18 324 mult_36 auto 34.2 MiB 0.61 7550 30419 6455 19369 4595 71.8 MiB 0.62 0.01 9.12001 -583.855 -9.12001 9.12001 0.73 0.00393783 0.00359825 0.259055 0.235968 48 12630 26 7.77114e+06 4.4171e+06 935225. 2886.50 7.41 1.66175 1.4664 29348 218440 -1 10831 21 6820 7945 915173 231648 8.49665 8.49665 -783.026 -8.49665 0 0 1.13028e+06 3488.51 0.31 0.42 0.21 -1 -1 0.31 0.196924 0.173911 962 544 418 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_24.v common 14.69 vpr 72.13 MiB 0.09 11404 -1 -1 1 0.26 -1 -1 36260 -1 -1 136 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73860 22 19 2105 1529 1 1235 184 18 18 324 mult_36 auto 34.9 MiB 0.58 7661 37317 8501 24959 3857 72.1 MiB 0.69 0.01 9.10913 -586.392 -9.10913 9.10913 0.75 0.00385424 0.00348189 0.294439 0.266977 48 13133 26 7.77114e+06 4.47989e+06 935225. 2886.50 8.93 1.94041 1.70952 29348 218440 -1 10908 23 7434 8576 948645 234568 8.58465 8.58465 -791.233 -8.58465 0 0 1.13028e+06 3488.51 0.30 0.42 0.19 -1 -1 0.30 0.198405 0.177356 1000 563 437 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_25.v common 10.98 vpr 72.92 MiB 0.13 11880 -1 -1 1 0.24 -1 -1 36524 -1 -1 141 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74672 22 19 2201 1591 1 1295 189 18 18 324 mult_36 auto 35.6 MiB 0.65 7882 35419 7795 23110 4514 72.9 MiB 0.75 0.01 9.0476 -626.573 -9.0476 9.0476 0.76 0.00401564 0.00365488 0.307124 0.279188 46 14895 28 7.77114e+06 4.54268e+06 895831. 2764.91 5.23 1.29314 1.14623 29024 211752 -1 11428 21 6952 8164 847241 222680 8.28945 8.28945 -792.599 -8.28945 0 0 1.09776e+06 3388.15 0.29 0.38 0.19 -1 -1 0.29 0.187225 0.167354 1042 586 456 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_26.v common 14.27 vpr 73.07 MiB 0.16 11928 -1 -1 1 0.33 -1 -1 37424 -1 -1 145 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74820 22 19 2275 1648 1 1331 193 18 18 324 mult_36 auto 35.9 MiB 0.64 8270 37512 8174 25127 4211 73.1 MiB 0.74 0.01 9.15301 -640.754 -9.15301 9.15301 0.75 0.00418134 0.00380681 0.302948 0.275287 48 14431 26 7.77114e+06 4.59291e+06 935225. 2886.50 8.14 1.80477 1.59081 29348 218440 -1 12124 23 9127 10596 1176912 285820 8.54065 8.54065 -814.155 -8.54065 0 0 1.13028e+06 3488.51 0.34 0.52 0.20 -1 -1 0.34 0.226656 0.202872 1080 605 475 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_27.v common 16.96 vpr 73.94 MiB 0.16 12168 -1 -1 1 0.33 -1 -1 36860 -1 -1 153 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75712 22 19 2385 1724 1 1408 202 18 18 324 mult_36 auto 36.6 MiB 0.62 9475 39274 8633 24027 6614 73.9 MiB 0.80 0.01 9.16401 -680.51 -9.16401 9.16401 0.79 0.00432941 0.00393962 0.337033 0.306189 54 16614 36 7.77114e+06 5.08937e+06 1.02660e+06 3168.53 10.75 2.19661 1.93908 30640 245540 -1 13208 20 7860 9445 1117978 264377 8.41125 8.41125 -880.793 -8.41125 0 0 1.26286e+06 3897.71 0.33 0.42 0.21 -1 -1 0.33 0.191053 0.170746 1136 642 494 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_28.v common 11.57 vpr 74.54 MiB 0.18 12280 -1 -1 1 0.26 -1 -1 36736 -1 -1 158 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76324 22 19 2459 1781 1 1444 207 18 18 324 mult_36 auto 37.0 MiB 0.76 8909 41211 9001 25741 6469 74.5 MiB 0.81 0.01 9.14684 -663.352 -9.14684 9.14684 0.79 0.00460207 0.00411187 0.323378 0.293345 46 16563 50 7.77114e+06 5.15216e+06 895831. 2764.91 5.19 1.42025 1.25683 29024 211752 -1 12815 21 8674 9947 1180543 313346 8.80125 8.80125 -858.702 -8.80125 0 0 1.09776e+06 3388.15 0.29 0.48 0.18 -1 -1 0.29 0.209869 0.187449 1174 661 513 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_29.v common 19.37 vpr 74.96 MiB 0.18 12660 -1 -1 1 0.34 -1 -1 37108 -1 -1 165 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76756 22 19 2565 1853 1 1517 215 22 22 484 mult_36 auto 37.6 MiB 0.76 9695 50369 11832 33775 4762 75.0 MiB 1.05 0.01 9.39824 -758.644 -9.39824 9.39824 1.22 0.0048153 0.00437802 0.403953 0.3667 44 19021 30 1.26594e+07 5.63607e+06 1.30964e+06 2705.88 11.40 2.24831 1.98778 43422 318546 -1 14146 23 8551 9980 1131104 280459 8.63965 8.63965 -1048.26 -8.63965 0 0 1.65337e+06 3416.05 0.47 0.53 0.27 -1 -1 0.47 0.25129 0.224571 1226 694 532 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_30.v common 46.46 vpr 75.68 MiB 0.13 12644 -1 -1 1 0.25 -1 -1 37348 -1 -1 170 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77492 22 19 2639 1910 1 1554 220 22 22 484 mult_36 auto 38.2 MiB 0.83 9525 45967 10375 31456 4136 75.7 MiB 0.98 0.01 9.332 -761.848 -9.332 9.332 1.27 0.00495473 0.00451634 0.392015 0.355908 40 18870 42 1.26594e+07 5.69886e+06 1.17677e+06 2431.33 38.65 2.72081 2.40169 41974 287914 -1 15646 19 10618 12587 1630390 401109 8.82305 8.82305 -1060.29 -8.82305 0 0 1.53957e+06 3180.94 0.43 0.56 0.18 -1 -1 0.43 0.20758 0.185629 1264 713 551 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_31.v common 14.59 vpr 75.85 MiB 0.10 12888 -1 -1 1 0.39 -1 -1 37480 -1 -1 177 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77668 22 19 2744 1981 1 1626 227 22 22 484 mult_36 auto 38.5 MiB 0.79 10029 50743 11223 34192 5328 75.8 MiB 1.02 0.01 9.332 -743.867 -9.332 9.332 1.29 0.00285428 0.00261476 0.411716 0.373589 44 19607 46 1.26594e+07 5.78677e+06 1.30964e+06 2705.88 6.46 1.62768 1.44317 43422 318546 -1 14760 21 8812 10635 1193110 306240 8.51565 8.51565 -997.056 -8.51565 0 0 1.65337e+06 3416.05 0.47 0.51 0.28 -1 -1 0.47 0.239315 0.214108 1315 745 570 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_32.v common 20.57 vpr 76.41 MiB 0.20 13016 -1 -1 1 0.37 -1 -1 37008 -1 -1 181 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78240 22 19 2818 2038 1 1662 231 22 22 484 mult_36 auto 39.1 MiB 0.84 10896 62535 16168 40587 5780 76.4 MiB 1.32 0.02 9.51844 -833.689 -9.51844 9.51844 1.17 0.00567558 0.0051011 0.507219 0.459742 46 19729 33 1.26594e+07 5.837e+06 1.37878e+06 2848.72 12.02 2.45886 2.17829 43906 328446 -1 15857 23 10062 11624 1282729 313572 8.31125 8.31125 -1223.57 -8.31125 0 0 1.69059e+06 3492.95 0.48 0.55 0.30 -1 -1 0.48 0.256887 0.228971 1353 764 589 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_33.v common 42.72 vpr 76.81 MiB 0.20 13632 -1 -1 1 0.28 -1 -1 37428 -1 -1 189 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78656 22 19 2923 2109 1 1730 240 22 22 484 mult_36 auto 39.7 MiB 0.84 11006 63565 15479 41766 6320 76.8 MiB 1.25 0.01 10.0899 -813.568 -10.0899 10.0899 1.21 0.00518259 0.00469824 0.489613 0.442392 44 22012 50 1.26594e+07 6.33346e+06 1.30964e+06 2705.88 34.19 2.93242 2.58393 43422 318546 -1 16383 23 12263 14060 1788436 435492 9.31331 9.31331 -1098.11 -9.31331 0 0 1.65337e+06 3416.05 0.48 0.67 0.28 -1 -1 0.48 0.271858 0.242511 1404 796 608 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_34.v common 23.80 vpr 77.41 MiB 0.20 13712 -1 -1 1 0.40 -1 -1 37740 -1 -1 194 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79264 22 19 2997 2166 1 1769 245 22 22 484 mult_36 auto 40.1 MiB 1.12 11467 56929 13204 37063 6662 77.4 MiB 1.16 0.01 9.84947 -801.897 -9.84947 9.84947 1.23 0.00550201 0.00500599 0.449134 0.405926 46 23369 48 1.26594e+07 6.39625e+06 1.37878e+06 2848.72 14.79 2.70665 2.3907 43906 328446 -1 16588 23 11553 13716 1515832 373082 9.23591 9.23591 -1123.07 -9.23591 0 0 1.69059e+06 3492.95 0.48 0.73 0.29 -1 -1 0.48 0.297688 0.267246 1442 815 627 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_35.v common 18.97 vpr 78.42 MiB 0.19 14032 -1 -1 1 0.42 -1 -1 37924 -1 -1 200 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80300 22 19 3101 2236 1 1838 251 22 22 484 mult_36 auto 41.0 MiB 1.06 11980 57994 13001 38956 6037 78.4 MiB 1.22 0.02 10.4246 -898.797 -10.4246 10.4246 1.48 0.0061833 0.00566496 0.467701 0.424377 46 22305 40 1.26594e+07 6.4716e+06 1.37878e+06 2848.72 9.73 1.90829 1.69402 43906 328446 -1 17462 19 9824 11939 1348912 334590 9.59651 9.59651 -1262.04 -9.59651 0 0 1.69059e+06 3492.95 0.46 0.53 0.29 -1 -1 0.46 0.230592 0.206289 1492 846 646 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_36.v common 17.38 vpr 78.79 MiB 0.22 14132 -1 -1 1 0.41 -1 -1 37988 -1 -1 204 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80684 22 19 3175 2293 1 1872 255 22 22 484 mult_36 auto 41.3 MiB 1.17 11366 60855 13639 40637 6579 78.8 MiB 1.21 0.02 10.2398 -852.171 -10.2398 10.2398 1.18 0.00553478 0.00500054 0.457669 0.413833 48 20735 33 1.26594e+07 6.52183e+06 1.44011e+06 2975.42 8.52 2.04069 1.81415 44390 338934 -1 16863 23 10639 12310 1484249 366742 9.42731 9.42731 -1124.46 -9.42731 0 0 1.74100e+06 3597.11 0.48 0.58 0.29 -1 -1 0.48 0.268926 0.2395 1530 865 665 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_37.v common 25.75 vpr 79.31 MiB 0.25 14440 -1 -1 1 0.47 -1 -1 37420 -1 -1 211 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81216 22 19 3280 2364 1 1945 263 24 24 576 mult_36 auto 42.3 MiB 1.15 12736 63413 14509 42506 6398 79.3 MiB 1.40 0.02 10.3609 -909.644 -10.3609 10.3609 1.63 0.00777899 0.00697982 0.548709 0.497288 48 22784 34 1.52924e+07 7.00574e+06 1.71014e+06 2969.00 15.49 2.97976 2.63549 52498 402441 -1 18388 22 10953 12996 1615157 387443 9.53551 9.53551 -1204.08 -9.53551 0 0 2.06880e+06 3591.66 0.62 0.65 0.35 -1 -1 0.62 0.284875 0.25441 1581 897 684 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_38.v common 21.35 vpr 79.64 MiB 0.16 14468 -1 -1 1 0.48 -1 -1 37924 -1 -1 216 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81556 22 19 3354 2421 1 1981 268 24 24 576 mult_36 auto 42.8 MiB 1.30 13069 66719 15235 45868 5616 79.6 MiB 1.39 0.02 9.9525 -910.496 -9.9525 9.9525 1.46 0.00636589 0.00580294 0.514272 0.463865 44 26849 47 1.52924e+07 7.06853e+06 1.55518e+06 2699.97 11.22 2.20563 1.95256 51346 378163 -1 19312 24 12866 15131 1925109 470482 9.60091 9.60091 -1238.65 -9.60091 0 0 1.96475e+06 3411.02 0.55 0.70 0.30 -1 -1 0.55 0.295828 0.263378 1619 916 703 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_39.v common 16.77 vpr 80.21 MiB 0.21 14716 -1 -1 1 0.49 -1 -1 38280 -1 -1 223 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82140 22 19 3457 2490 1 2052 275 24 24 576 mult_36 auto 43.2 MiB 1.22 13656 73501 17416 50143 5942 80.2 MiB 1.62 0.02 10.0727 -966.849 -10.0727 10.0727 1.44 0.00654031 0.00595441 0.621855 0.561075 46 23538 32 1.52924e+07 7.15643e+06 1.63708e+06 2842.15 6.70 1.88873 1.67432 51922 389946 -1 18838 23 10601 12759 1435807 370600 8.95151 8.95151 -1160.49 -8.95151 0 0 2.00908e+06 3487.99 0.57 0.69 0.23 -1 -1 0.57 0.331688 0.297995 1668 946 722 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_40.v common 21.71 vpr 80.70 MiB 0.17 14852 -1 -1 1 0.46 -1 -1 38748 -1 -1 228 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82636 22 19 3531 2547 1 2089 280 24 24 576 mult_36 auto 43.6 MiB 1.40 13045 78055 20225 49115 8715 80.7 MiB 1.53 0.02 9.95249 -1011.72 -9.95249 9.95249 1.45 0.0065844 0.00598886 0.59874 0.538194 46 24015 38 1.52924e+07 7.21922e+06 1.63708e+06 2842.15 11.30 2.16095 1.91139 51922 389946 -1 18582 26 11805 14295 1481227 365944 8.90771 8.90771 -1456.6 -8.90771 0 0 2.00908e+06 3487.99 0.59 0.71 0.29 -1 -1 0.59 0.349879 0.311755 1706 965 741 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_41.v common 22.34 vpr 81.34 MiB 0.25 15324 -1 -1 1 0.59 -1 -1 37992 -1 -1 234 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83292 22 19 3634 2616 1 2155 287 24 24 576 mult_36 auto 44.4 MiB 1.34 13626 81643 18980 54154 8509 81.3 MiB 1.76 0.02 10.2807 -1100.54 -10.2807 10.2807 1.64 0.00589193 0.00531161 0.641657 0.582472 48 24099 30 1.52924e+07 7.69057e+06 1.71014e+06 2969.00 11.28 2.30878 2.05025 52498 402441 -1 19745 21 10698 12698 1556800 373550 9.35911 9.35911 -1273.87 -9.35911 0 0 2.06880e+06 3591.66 0.58 0.64 0.34 -1 -1 0.58 0.296748 0.265201 1755 995 760 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_42.v common 26.53 vpr 81.88 MiB 0.19 15376 -1 -1 1 0.51 -1 -1 38272 -1 -1 239 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83848 22 19 3708 2673 1 2193 292 24 24 576 mult_36 auto 44.8 MiB 1.41 14431 72892 16198 51073 5621 81.9 MiB 1.77 0.02 10.1929 -992.819 -10.1929 10.1929 1.57 0.00635968 0.00581533 0.574831 0.514396 48 25902 39 1.52924e+07 7.75336e+06 1.71014e+06 2969.00 15.17 3.18975 2.81988 52498 402441 -1 20831 21 12944 15314 1869342 457103 9.58971 9.58971 -1252.11 -9.58971 0 0 2.06880e+06 3591.66 0.64 0.79 0.37 -1 -1 0.64 0.333755 0.299406 1793 1014 779 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_43.v common 20.91 vpr 82.54 MiB 0.14 15612 -1 -1 1 0.53 -1 -1 38816 -1 -1 245 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84520 22 19 3810 2741 1 2260 298 24 24 576 mult_36 auto 45.3 MiB 1.35 14165 81888 20044 54601 7243 82.5 MiB 1.81 0.03 10.1328 -1049.12 -10.1328 10.1328 1.56 0.00741441 0.00659365 0.662329 0.59364 46 27674 49 1.52924e+07 7.82871e+06 1.63708e+06 2842.15 9.61 2.43495 2.15978 51922 389946 -1 20484 24 13292 15374 1707658 435292 9.19011 9.19011 -1651.37 -9.19011 0 0 2.00908e+06 3487.99 0.58 0.79 0.29 -1 -1 0.58 0.365312 0.326451 1841 1043 798 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_44.v common 71.92 vpr 82.65 MiB 0.22 15704 -1 -1 1 0.56 -1 -1 38420 -1 -1 250 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84636 22 19 3884 2798 1 2296 303 24 24 576 mult_36 auto 45.4 MiB 1.53 14946 80646 18903 52810 8933 82.7 MiB 1.73 0.02 9.99493 -1033.19 -9.99493 9.99493 1.55 0.00737401 0.00661175 0.630908 0.568308 48 27278 40 1.52924e+07 7.8915e+06 1.71014e+06 2969.00 60.53 4.224 3.7203 52498 402441 -1 22061 23 14612 17263 2051107 497730 9.31511 9.31511 -1517.68 -9.31511 0 0 2.06880e+06 3591.66 0.60 0.83 0.34 -1 -1 0.60 0.353811 0.314744 1879 1062 817 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_45.v common 19.49 vpr 83.04 MiB 0.26 15944 -1 -1 1 0.60 -1 -1 40472 -1 -1 257 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85032 22 19 3989 2869 1 2368 311 24 24 576 mult_36 auto 46.0 MiB 1.40 16964 75074 16987 50636 7451 83.0 MiB 1.59 0.02 10.3131 -1048.02 -10.3131 10.3131 1.52 0.00784933 0.00716328 0.580129 0.52297 48 28860 31 1.52924e+07 8.37541e+06 1.71014e+06 2969.00 8.09 2.10725 1.8649 52498 402441 -1 23894 23 12966 15711 2070445 493094 9.73871 9.73871 -1579.52 -9.73871 0 0 2.06880e+06 3591.66 0.58 0.76 0.37 -1 -1 0.58 0.33325 0.296675 1930 1094 836 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_46.v common 22.02 vpr 83.42 MiB 0.27 16056 -1 -1 1 0.58 -1 -1 40536 -1 -1 261 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85424 22 19 4063 2926 1 2404 315 24 24 576 mult_36 auto 46.3 MiB 1.67 15692 88137 21521 56647 9969 83.4 MiB 1.75 0.02 9.95249 -1107.23 -9.95249 9.95249 1.49 0.00859715 0.00777619 0.658305 0.593526 54 26619 49 1.52924e+07 8.42564e+06 1.87785e+06 3260.16 10.01 2.74176 2.43271 54798 452027 -1 21115 25 12793 15079 1570956 397175 9.08891 9.08891 -1436.28 -9.08891 0 0 2.31032e+06 4010.97 0.65 0.77 0.42 -1 -1 0.65 0.388572 0.345487 1968 1113 855 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_47.v common 24.10 vpr 84.30 MiB 0.26 16620 -1 -1 1 0.44 -1 -1 40800 -1 -1 268 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86324 22 19 4167 2996 1 2473 322 24 24 576 mult_36 auto 47.3 MiB 1.15 15910 88562 20878 57457 10227 84.3 MiB 1.83 0.02 10.0899 -1142.01 -10.0899 10.0899 1.50 0.00778185 0.0070779 0.652391 0.587128 50 27180 34 1.52924e+07 8.51354e+06 1.78400e+06 3097.22 12.92 2.60385 2.30211 53074 415989 -1 22519 23 12297 14952 1649666 414573 9.24691 9.24691 -1519.04 -9.24691 0 0 2.13454e+06 3705.80 0.61 0.78 0.35 -1 -1 0.61 0.379489 0.338212 2018 1144 874 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_48.v common 19.62 vpr 84.32 MiB 0.24 16492 -1 -1 1 0.62 -1 -1 40916 -1 -1 273 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86348 22 19 4241 3053 1 2509 327 24 24 576 mult_36 auto 47.4 MiB 1.38 16487 93785 22388 64524 6873 84.3 MiB 1.86 0.02 10.5535 -1144.3 -10.5535 10.5535 1.46 0.00701064 0.0063265 0.618906 0.556033 48 28818 32 1.52924e+07 8.57633e+06 1.71014e+06 2969.00 8.35 2.29073 2.04076 52498 402441 -1 24059 23 12093 14580 1751508 427964 10.3207 10.3207 -1752.01 -10.3207 0 0 2.06880e+06 3591.66 0.70 0.70 0.33 -1 -1 0.70 0.318799 0.289487 2056 1163 893 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_49.v common 23.58 vpr 84.68 MiB 0.33 16980 -1 -1 1 0.61 -1 -1 41100 -1 -1 279 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86712 22 19 4346 3124 1 2580 334 24 24 576 mult_36 auto 47.9 MiB 1.53 16418 98764 23499 65407 9858 84.7 MiB 2.11 0.02 10.0121 -1103.23 -10.0121 10.0121 1.51 0.00801433 0.0072699 0.739201 0.661626 48 28351 48 1.52924e+07 9.04768e+06 1.71014e+06 2969.00 11.34 2.93392 2.59947 52498 402441 -1 24128 20 15119 18240 2121135 532072 9.54451 9.54451 -1898.86 -9.54451 0 0 2.06880e+06 3591.66 0.62 0.85 0.34 -1 -1 0.62 0.358724 0.321338 2107 1195 912 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_50.v common 21.90 vpr 85.40 MiB 0.17 17136 -1 -1 1 0.64 -1 -1 40976 -1 -1 284 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87452 22 19 4420 3181 1 2615 339 24 24 576 mult_36 auto 48.5 MiB 1.60 17962 88914 19616 60588 8710 85.4 MiB 1.92 0.03 10.2463 -1217.9 -10.2463 10.2463 1.43 0.00802952 0.00727944 0.649197 0.583734 52 30590 30 1.52924e+07 9.11047e+06 1.82869e+06 3174.81 9.79 2.66483 2.36444 54222 439550 -1 24692 22 14714 17386 2038106 506700 9.42751 9.42751 -1884.23 -9.42751 0 0 2.25030e+06 3906.77 0.74 0.91 0.41 -1 -1 0.74 0.403763 0.368433 2145 1214 931 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_51.v common 30.19 vpr 85.87 MiB 0.20 17368 -1 -1 1 0.65 -1 -1 41140 -1 -1 292 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87932 22 19 4524 3251 1 2687 347 24 24 576 mult_36 auto 48.9 MiB 1.71 17584 90479 20112 60343 10024 85.9 MiB 1.88 0.03 10.1323 -1257.51 -10.1323 10.1323 1.41 0.00828558 0.00749981 0.650201 0.58338 54 30742 41 1.52924e+07 9.21094e+06 1.87785e+06 3260.16 17.90 3.45437 3.05274 54798 452027 -1 24323 24 12811 15116 1754918 426147 9.61671 9.61671 -2019.82 -9.61671 0 0 2.31032e+06 4010.97 0.76 0.86 0.38 -1 -1 0.76 0.434004 0.388012 2195 1245 950 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_52.v common 24.08 vpr 86.49 MiB 0.29 17524 -1 -1 1 0.59 -1 -1 39328 -1 -1 296 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88564 22 19 4598 3308 1 2721 351 24 24 576 mult_36 auto 49.6 MiB 1.38 17233 94363 21503 64446 8414 86.5 MiB 1.99 0.03 10.4246 -1286.45 -10.4246 10.4246 1.46 0.00842922 0.00765206 0.674663 0.606068 50 29595 50 1.52924e+07 9.26117e+06 1.78400e+06 3097.22 11.90 3.04331 2.69276 53074 415989 -1 24350 23 14468 16947 2000437 496448 9.61971 9.61971 -1721.97 -9.61971 0 0 2.13454e+06 3705.80 0.89 0.81 0.41 -1 -1 0.89 0.393047 0.353185 2233 1264 969 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_14.v common 13.99 vpr 71.68 MiB 0.06 10360 -1 -1 1 0.26 -1 -1 35432 -1 -1 123 22 0 4 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73404 22 19 1974 1653 1 1039 168 16 16 256 mult_36 auto 34.2 MiB 1.71 6084 26559 5485 17904 3170 71.7 MiB 0.45 0.01 4.07137 -1184.46 -4.07137 4.07137 0.56 0.00386419 0.0035194 0.214571 0.193058 40 11804 49 6.34292e+06 3.14339e+06 583096. 2277.72 8.15 1.68742 1.4728 21572 140635 -1 9984 21 4134 4929 581328 151853 4.48156 4.48156 -1220.21 -4.48156 0 0 763333. 2981.77 0.21 0.33 0.14 -1 -1 0.21 0.188958 0.168721 953 708 247 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_15.v common 13.35 vpr 72.60 MiB 0.08 10804 -1 -1 1 0.24 -1 -1 36924 -1 -1 132 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74340 22 19 2144 1789 1 1138 178 16 16 256 clb mult_36 auto 35.2 MiB 1.79 6845 29178 5734 19784 3660 72.6 MiB 0.50 0.01 4.13443 -1312.79 -4.13443 4.13443 0.56 0.00395181 0.00358259 0.243092 0.21955 44 12842 28 6.34292e+06 3.6535e+06 649498. 2537.10 7.35 1.51796 1.33002 22336 155612 -1 9870 14 3634 4364 464801 122306 4.24116 4.24116 -1341.45 -4.24116 0 0 820238. 3204.05 0.22 0.25 0.12 -1 -1 0.22 0.143265 0.129136 1033 769 266 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_16.v common 8.94 vpr 72.88 MiB 0.12 10984 -1 -1 1 0.25 -1 -1 36852 -1 -1 137 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74632 22 19 2218 1846 1 1177 183 16 16 256 clb mult_36 auto 35.6 MiB 2.08 7131 32361 6636 21461 4264 72.9 MiB 0.55 0.01 4.24116 -1381.33 -4.24116 4.24116 0.58 0.00386192 0.00347919 0.254067 0.228151 46 12387 24 6.34292e+06 3.71689e+06 684529. 2673.94 2.56 0.873502 0.767796 22592 160355 -1 9850 14 3563 4257 399452 105344 4.24116 4.24116 -1382.06 -4.24116 0 0 838722. 3276.26 0.21 0.23 0.15 -1 -1 0.21 0.133813 0.119563 1071 788 285 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_17.v common 10.12 vpr 75.05 MiB 0.10 11836 -1 -1 1 0.30 -1 -1 36744 -1 -1 157 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76848 22 19 2536 2130 1 1298 203 17 17 289 clb auto 37.7 MiB 2.30 7990 29407 5457 21306 2644 75.0 MiB 0.50 0.01 4.48156 -1537.29 -4.48156 4.48156 0.64 0.00430613 0.00385143 0.230555 0.20626 46 15105 26 6.65987e+06 3.97045e+06 782063. 2706.10 3.11 1.02124 0.89176 25426 183746 -1 11140 13 4183 5041 445642 117624 4.36136 4.36136 -1531.19 -4.36136 0 0 958460. 3316.47 0.25 0.31 0.16 -1 -1 0.25 0.181249 0.165655 1226 924 304 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_18.v common 10.00 vpr 75.36 MiB 0.12 11868 -1 -1 1 0.31 -1 -1 37216 -1 -1 163 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77172 22 19 2610 2187 1 1336 209 17 17 289 clb auto 37.9 MiB 2.21 8155 36789 7305 26033 3451 75.4 MiB 0.50 0.01 4.05473 -1593.4 -4.05473 4.05473 0.64 0.00204187 0.00181336 0.205703 0.183114 48 15307 35 6.65987e+06 4.04651e+06 816265. 2824.45 3.10 0.995261 0.867823 25714 189529 -1 12228 16 4558 5382 598643 148707 4.24116 4.24116 -1683.87 -4.24116 0 0 986792. 3414.50 0.26 0.30 0.17 -1 -1 0.26 0.169811 0.15093 1264 943 323 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_19.v common 19.99 vpr 76.09 MiB 0.10 12172 -1 -1 1 0.34 -1 -1 36796 -1 -1 172 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77916 22 19 2778 2321 1 1434 219 18 18 324 clb auto 39.2 MiB 2.49 8731 36464 7395 26087 2982 76.1 MiB 0.61 0.01 4.24116 -1720.94 -4.24116 4.24116 0.73 0.00509493 0.00450297 0.279768 0.250014 44 16662 42 7.79418e+06 4.55662e+06 850563. 2625.19 12.37 2.27729 1.98592 28700 205432 -1 12706 14 4544 5587 531680 141034 4.24116 4.24116 -1760.33 -4.24116 0 0 1.07356e+06 3313.45 0.30 0.31 0.18 -1 -1 0.30 0.173921 0.155689 1342 1002 342 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_20.v common 12.38 vpr 76.71 MiB 0.17 12368 -1 -1 1 0.34 -1 -1 36952 -1 -1 176 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78552 22 19 2852 2378 1 1479 223 18 18 324 clb auto 39.8 MiB 2.45 9149 36727 6960 26660 3107 76.7 MiB 0.64 0.01 4.17493 -1790.89 -4.17493 4.17493 0.77 0.00476988 0.00427466 0.281251 0.25121 46 15963 21 7.79418e+06 4.60733e+06 895831. 2764.91 4.53 1.36531 1.18775 29024 211752 -1 13130 14 4664 5572 585274 152661 4.36136 4.36136 -1839.76 -4.36136 0 0 1.09776e+06 3388.15 0.29 0.31 0.18 -1 -1 0.29 0.16464 0.147225 1380 1021 361 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_21.v common 13.46 vpr 77.67 MiB 0.13 12896 -1 -1 1 0.35 -1 -1 38016 -1 -1 188 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79536 22 19 3057 2549 1 1586 235 18 18 324 clb auto 40.8 MiB 2.76 9903 45123 9529 32094 3500 77.7 MiB 0.76 0.01 4.25463 -1905.93 -4.25463 4.25463 0.75 0.00498986 0.0044505 0.338263 0.301731 46 17948 30 7.79418e+06 4.75946e+06 895831. 2764.91 5.01 1.49883 1.31763 29024 211752 -1 13855 14 5092 6144 628537 161536 4.36136 4.36136 -2028.43 -4.36136 0 0 1.09776e+06 3388.15 0.29 0.32 0.17 -1 -1 0.29 0.179308 0.160203 1477 1099 380 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_22.v common 18.07 vpr 78.16 MiB 0.13 12828 -1 -1 1 0.35 -1 -1 37944 -1 -1 194 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80032 22 19 3131 2606 1 1626 241 19 19 361 clb auto 41.4 MiB 2.84 10286 47428 9839 33939 3650 78.2 MiB 0.84 0.01 4.24116 -1964.7 -4.24116 4.24116 0.84 0.00515519 0.00460612 0.374874 0.334519 48 18602 34 8.16184e+06 4.83553e+06 1.05176e+06 2913.46 9.15 2.16239 1.89086 32602 246183 -1 15049 16 5468 6655 767404 181797 4.24116 4.24116 -1987.18 -4.24116 0 0 1.27108e+06 3521.00 0.34 0.37 0.21 -1 -1 0.34 0.197316 0.175297 1515 1118 399 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_23.v common 14.48 vpr 79.21 MiB 0.16 13236 -1 -1 1 0.36 -1 -1 37880 -1 -1 204 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81112 22 19 3301 2742 1 1720 252 19 19 361 clb auto 42.1 MiB 2.94 11043 52722 11417 37077 4228 79.2 MiB 0.96 0.01 4.12096 -2024.58 -4.12096 4.12096 0.84 0.00592097 0.00532352 0.426861 0.380863 50 18333 39 8.16184e+06 5.35831e+06 1.09718e+06 3039.29 5.13 1.91612 1.67794 32962 254619 -1 15633 15 5503 6537 715495 175652 4.36136 4.36136 -2095.67 -4.36136 0 0 1.31179e+06 3633.76 0.43 0.44 0.21 -1 -1 0.43 0.258958 0.236943 1595 1179 418 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_24.v common 17.69 vpr 79.93 MiB 0.18 13436 -1 -1 1 0.38 -1 -1 38112 -1 -1 209 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81848 22 19 3375 2799 1 1765 257 19 19 361 clb auto 42.7 MiB 3.14 10750 45953 8990 33234 3729 79.9 MiB 0.78 0.01 4.17493 -2082.77 -4.17493 4.17493 0.83 0.00572618 0.00512497 0.333878 0.297631 50 19942 42 8.16184e+06 5.4217e+06 1.09718e+06 3039.29 8.20 1.98948 1.74691 32962 254619 -1 15531 18 5893 7110 826640 196272 4.48156 4.48156 -2097.91 -4.48156 0 0 1.31179e+06 3633.76 0.35 0.41 0.23 -1 -1 0.35 0.232604 0.206131 1633 1198 437 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_25.v common 19.32 vpr 80.93 MiB 0.09 13904 -1 -1 1 0.41 -1 -1 38040 -1 -1 223 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82876 22 19 3615 3005 1 1878 271 20 20 400 clb auto 43.8 MiB 3.29 11843 54583 11378 38149 5056 80.9 MiB 0.91 0.01 4.18011 -2275.57 -4.18011 4.18011 0.99 0.0059378 0.00528452 0.392642 0.348871 50 19676 18 1.10667e+07 5.59919e+06 1.21483e+06 3037.08 9.37 2.3373 2.05364 36870 282114 -1 16952 16 6065 7149 736369 184136 4.36136 4.36136 -2393.56 -4.36136 0 0 1.45344e+06 3633.59 0.39 0.38 0.24 -1 -1 0.39 0.221589 0.196726 1747 1293 456 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_26.v common 15.55 vpr 81.50 MiB 0.10 14064 -1 -1 1 0.42 -1 -1 38312 -1 -1 228 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83456 22 19 3689 3062 1 1918 276 20 20 400 clb auto 44.8 MiB 3.39 12415 59544 13159 41333 5052 81.5 MiB 1.03 0.02 4.13813 -2248.17 -4.13813 4.13813 0.94 0.00636596 0.00571336 0.441584 0.393961 48 22522 44 1.10667e+07 5.66258e+06 1.16517e+06 2912.92 5.28 1.89176 1.66089 36470 272802 -1 17889 14 6502 7743 857384 212074 4.36136 4.36136 -2389.08 -4.36136 0 0 1.40818e+06 3520.44 0.42 0.40 0.25 -1 -1 0.42 0.215312 0.194032 1785 1312 475 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_27.v common 22.10 vpr 82.62 MiB 0.14 14320 -1 -1 1 0.43 -1 -1 38328 -1 -1 240 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84604 22 19 3871 3210 1 2023 289 21 21 441 clb auto 45.5 MiB 3.59 13091 69049 15421 48905 4723 82.6 MiB 1.17 0.02 4.25833 -2439.76 -4.25833 4.25833 1.04 0.00662048 0.00586304 0.484025 0.429075 50 22955 23 1.14723e+07 6.21072e+06 1.34972e+06 3060.59 10.90 2.78183 2.45578 40486 313801 -1 19085 17 6693 8122 872684 214863 4.36136 4.36136 -2497.47 -4.36136 0 0 1.61476e+06 3661.58 0.44 0.45 0.25 -1 -1 0.44 0.256917 0.228658 1877 1385 494 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_28.v common 18.55 vpr 83.02 MiB 0.18 14580 -1 -1 1 0.52 -1 -1 38388 -1 -1 245 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85016 22 19 3945 3267 1 2070 294 21 21 441 clb auto 46.1 MiB 3.68 13787 70638 15611 48908 6119 83.0 MiB 1.24 0.02 4.18011 -2457.52 -4.18011 4.18011 1.06 0.0074756 0.006569 0.530694 0.471761 50 23792 26 1.14723e+07 6.27411e+06 1.34972e+06 3060.59 7.01 2.15928 1.89132 40486 313801 -1 19707 15 6833 8556 909227 220592 4.36136 4.36136 -2566.1 -4.36136 0 0 1.61476e+06 3661.58 0.45 0.42 0.25 -1 -1 0.45 0.231815 0.206025 1915 1404 513 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_29.v common 31.29 vpr 84.27 MiB 0.19 15128 -1 -1 1 0.54 -1 -1 39544 -1 -1 258 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86292 22 19 4159 3447 1 2186 308 22 22 484 mult_36 auto 47.4 MiB 3.84 14540 75116 16849 52375 5892 84.3 MiB 1.25 0.02 4.48156 -2570.01 -4.48156 4.48156 1.17 0.00688567 0.00616168 0.52709 0.468722 50 23434 22 1.26954e+07 6.83492e+06 1.50222e+06 3103.76 19.22 3.03941 2.64267 44874 350400 -1 20303 14 6789 8219 816835 204141 4.48156 4.48156 -2692.11 -4.48156 0 0 1.79645e+06 3711.66 0.51 0.43 0.30 -1 -1 0.51 0.249086 0.222942 2021 1491 532 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_30.v common 19.90 vpr 84.84 MiB 0.20 15240 -1 -1 1 0.52 -1 -1 40812 -1 -1 263 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86880 22 19 4233 3504 1 2225 313 22 22 484 mult_36 auto 48.0 MiB 3.96 14345 72529 15646 51039 5844 84.8 MiB 1.22 0.02 4.29513 -2641.58 -4.29513 4.29513 1.15 0.00705696 0.00626798 0.507139 0.45077 48 25057 33 1.26954e+07 6.89831e+06 1.44011e+06 2975.42 7.55 2.3246 2.02616 44390 338934 -1 20617 16 7249 9020 909338 222155 4.48156 4.48156 -2910.31 -4.48156 0 0 1.74100e+06 3597.11 0.56 0.49 0.29 -1 -1 0.56 0.277592 0.247925 2059 1510 551 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_31.v common 26.91 vpr 85.89 MiB 0.17 15576 -1 -1 1 0.57 -1 -1 40948 -1 -1 274 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87948 22 19 4410 3647 1 2335 324 22 22 484 clb mult_36 auto 49.0 MiB 4.10 14627 81500 18211 56732 6557 85.9 MiB 1.36 0.02 4.48156 -2763.28 -4.48156 4.48156 1.17 0.00738142 0.0064759 0.546542 0.485598 54 24724 32 1.26954e+07 7.03777e+06 1.58090e+06 3266.32 13.87 3.49276 3.07371 46322 380746 -1 20211 16 6937 8304 881095 215583 4.48156 4.48156 -2824.86 -4.48156 0 0 1.94386e+06 4016.24 0.75 0.50 0.38 -1 -1 0.75 0.291696 0.260883 2146 1578 570 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_32.v common 18.88 vpr 86.39 MiB 0.21 15748 -1 -1 1 0.57 -1 -1 40676 -1 -1 278 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88460 22 19 4484 3704 1 2374 328 22 22 484 clb mult_36 auto 49.4 MiB 4.21 15540 78298 18108 54278 5912 86.4 MiB 1.37 0.02 4.24116 -2782.8 -4.24116 4.24116 1.18 0.00850778 0.00767123 0.580402 0.51799 48 26921 28 1.26954e+07 7.08848e+06 1.44011e+06 2975.42 6.06 2.09126 1.83654 44390 338934 -1 22311 13 7902 9623 980518 241405 4.48156 4.48156 -2896.93 -4.48156 0 0 1.74100e+06 3597.11 0.50 0.47 0.31 -1 -1 0.50 0.244366 0.218501 2184 1597 589 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_33.v common 20.43 vpr 87.84 MiB 0.18 16488 -1 -1 1 0.61 -1 -1 41520 -1 -1 302 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89948 22 19 4843 4029 1 2501 353 23 23 529 clb auto 51.3 MiB 4.44 17435 87643 19607 61599 6437 87.8 MiB 1.47 0.01 4.24116 -3073.8 -4.24116 4.24116 1.40 0.00437909 0.00392859 0.602393 0.533154 50 29482 39 1.31518e+07 7.78876e+06 1.65241e+06 3123.66 6.51 2.45162 2.13701 48882 385791 -1 24265 14 8069 9691 993548 240146 4.36136 4.36136 -3116.31 -4.36136 0 0 1.97533e+06 3734.07 0.60 0.53 0.37 -1 -1 0.60 0.293733 0.261277 2362 1756 608 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_34.v common 23.61 vpr 88.46 MiB 0.12 16748 -1 -1 1 0.62 -1 -1 41616 -1 -1 308 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90580 22 19 4917 4086 1 2542 359 23 23 529 clb auto 51.8 MiB 4.42 16896 87059 18935 61744 6380 88.5 MiB 1.56 0.02 4.48156 -3114.12 -4.48156 4.48156 1.32 0.00762155 0.00676444 0.636308 0.56748 50 30043 27 1.31518e+07 7.86482e+06 1.65241e+06 3123.66 9.44 2.60169 2.26752 48882 385791 -1 24344 14 8758 10802 1224972 286268 4.60176 4.60176 -3387.39 -4.60176 0 0 1.97533e+06 3734.07 0.56 0.56 0.37 -1 -1 0.56 0.286044 0.255012 2401 1775 627 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_35.v common 42.49 vpr 89.30 MiB 0.25 17244 -1 -1 1 0.65 -1 -1 41768 -1 -1 319 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91440 22 19 5093 4228 1 2643 370 23 23 529 clb auto 52.6 MiB 4.59 18051 89279 20131 63728 5420 89.3 MiB 1.53 0.03 4.37483 -3218.94 -4.37483 4.37483 1.28 0.0115723 0.0106977 0.611601 0.540946 50 30668 35 1.31518e+07 8.00428e+06 1.65241e+06 3123.66 28.07 3.81148 3.33209 48882 385791 -1 25188 17 8575 10282 1105084 272137 4.48156 4.48156 -3354.12 -4.48156 0 0 1.97533e+06 3734.07 0.57 0.64 0.31 -1 -1 0.57 0.36502 0.32385 2487 1842 646 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_36.v common 42.13 vpr 89.86 MiB 0.24 17224 -1 -1 1 0.58 -1 -1 41708 -1 -1 323 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92020 22 19 5167 4285 1 2691 374 23 23 529 clb auto 53.3 MiB 4.79 17780 96011 21980 67780 6251 89.9 MiB 1.63 0.02 4.48156 -3272.89 -4.48156 4.48156 1.27 0.00902501 0.00810883 0.636019 0.564686 50 31361 46 1.31518e+07 8.05499e+06 1.65241e+06 3123.66 27.54 4.02566 3.48344 48882 385791 -1 25174 17 9093 11307 1257811 296331 4.36136 4.36136 -3536.95 -4.36136 0 0 1.97533e+06 3734.07 0.65 0.70 0.32 -1 -1 0.65 0.394101 0.352154 2525 1861 665 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_37.v common 22.69 vpr 91.00 MiB 0.28 17624 -1 -1 1 0.67 -1 -1 40876 -1 -1 336 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93188 22 19 5380 4464 1 2808 388 24 24 576 mult_36 auto 54.4 MiB 4.95 18000 106438 25977 73150 7311 91.0 MiB 1.93 0.02 4.36136 -3470.71 -4.36136 4.36136 1.62 0.00921082 0.00823912 0.767144 0.678016 48 30066 22 1.53347e+07 8.61581e+06 1.71014e+06 2969.00 6.75 2.50437 2.1985 52498 402441 -1 25768 15 8689 10479 1086200 257350 4.60176 4.60176 -3539.87 -4.60176 0 0 2.06880e+06 3591.66 0.59 0.57 0.34 -1 -1 0.59 0.325227 0.290089 2630 1947 684 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_38.v common 29.23 vpr 91.32 MiB 0.27 17876 -1 -1 1 0.76 -1 -1 42228 -1 -1 342 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93512 22 19 5454 4521 1 2849 394 24 24 576 clb mult_36 auto 55.5 MiB 4.99 18144 115834 28131 77060 10643 91.3 MiB 1.97 0.02 4.24116 -3379.88 -4.24116 4.24116 1.45 0.00923439 0.00823115 0.799143 0.708981 50 29652 34 1.53347e+07 8.69188e+06 1.78400e+06 3097.22 13.48 3.83727 3.35876 53074 415989 -1 25288 17 8636 10670 1032084 260041 4.36136 4.36136 -3563.7 -4.36136 0 0 2.13454e+06 3705.80 0.60 0.62 0.34 -1 -1 0.60 0.370192 0.325926 2668 1966 703 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_39.v common 23.74 vpr 92.36 MiB 0.22 18152 -1 -1 1 0.66 -1 -1 40208 -1 -1 352 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94576 22 19 5629 4662 1 2951 404 24 24 576 clb mult_36 auto 56.4 MiB 5.14 21626 118272 28657 79200 10415 92.4 MiB 2.06 0.02 4.48156 -3617.12 -4.48156 4.48156 1.45 0.0096086 0.00860047 0.824292 0.731809 52 37764 38 1.53347e+07 8.81866e+06 1.82869e+06 3174.81 7.59 2.73664 2.40506 54222 439550 -1 29338 14 9216 11739 1241818 290722 4.72196 4.72196 -3919.7 -4.72196 0 0 2.25030e+06 3906.77 0.67 0.65 0.37 -1 -1 0.67 0.353944 0.318368 2753 2032 722 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_40.v common 26.05 vpr 92.76 MiB 0.19 18376 -1 -1 1 0.67 -1 -1 42312 -1 -1 357 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94988 22 19 5703 4719 1 2994 409 25 25 625 clb auto 57.0 MiB 5.29 20955 115701 27338 79764 8599 92.8 MiB 1.92 0.02 4.30038 -3680.46 -4.30038 4.30038 1.49 0.00891788 0.00790718 0.732142 0.646044 52 36068 32 1.58291e+07 8.88205e+06 1.99531e+06 3192.49 9.71 2.88506 2.51628 58656 480125 -1 28247 15 9057 11231 1191506 271016 4.48156 4.48156 -3899.12 -4.48156 0 0 2.45448e+06 3927.17 0.73 0.61 0.38 -1 -1 0.73 0.343601 0.306286 2791 2051 741 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_41.v common 35.27 vpr 101.03 MiB 0.26 18820 -1 -1 1 0.88 -1 -1 41464 -1 -1 373 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 103456 22 19 5950 4932 1 3111 426 25 25 625 clb auto 58.4 MiB 5.35 22868 125382 30342 84914 10126 94.5 MiB 2.17 0.03 4.36136 -3900.3 -4.36136 4.36136 1.74 0.010111 0.00896462 0.855855 0.758941 58 35761 44 1.58291e+07 9.48089e+06 2.14341e+06 3429.45 17.71 4.20562 3.67432 61152 534357 -1 30542 13 9396 11438 1360367 304092 4.36136 4.36136 -4147.24 -4.36136 0 0 2.68463e+06 4295.40 0.82 0.64 0.38 -1 -1 0.82 0.334472 0.299137 2912 2153 760 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_42.v common 28.04 vpr 94.77 MiB 0.19 18916 -1 -1 1 0.81 -1 -1 42788 -1 -1 376 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 97040 22 19 6024 4989 1 3151 429 25 25 625 clb auto 58.8 MiB 5.61 22338 129789 31817 87521 10451 94.8 MiB 2.26 0.02 4.48156 -3879.56 -4.48156 4.48156 1.62 0.0100564 0.00897238 0.888357 0.786949 52 37600 39 1.58291e+07 9.51893e+06 1.99531e+06 3192.49 10.69 3.58221 3.12509 58656 480125 -1 30047 14 9557 11787 1160075 277147 4.60176 4.60176 -3969.48 -4.60176 0 0 2.45448e+06 3927.17 0.72 0.63 0.28 -1 -1 0.72 0.364161 0.324891 2950 2172 779 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_43.v common 52.56 vpr 95.76 MiB 0.17 19248 -1 -1 1 0.84 -1 -1 43268 -1 -1 388 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 98060 22 19 6198 5129 1 3252 441 25 25 625 clb auto 59.7 MiB 5.69 22292 124613 28130 84188 12295 95.8 MiB 2.25 0.03 4.48156 -3906.86 -4.48156 4.48156 1.57 0.0119826 0.0108248 0.915972 0.811748 52 39721 49 1.58291e+07 9.67106e+06 1.99531e+06 3192.49 35.29 5.54653 4.84612 58656 480125 -1 30201 14 9788 12101 1217348 300045 4.48156 4.48156 -4076.88 -4.48156 0 0 2.45448e+06 3927.17 0.72 0.64 0.45 -1 -1 0.72 0.362311 0.324278 3034 2237 798 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_44.v common 38.21 vpr 104.12 MiB 0.23 19452 -1 -1 1 0.85 -1 -1 43464 -1 -1 393 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 106616 22 19 6272 5186 1 3297 446 26 26 676 clb auto 60.2 MiB 5.83 21355 129874 31660 89304 8910 96.5 MiB 2.36 0.03 4.29513 -3951.34 -4.29513 4.29513 1.81 0.0122421 0.0106007 0.908054 0.794565 52 38819 39 1.91809e+07 9.73445e+06 2.20423e+06 3260.69 19.62 4.72492 4.12636 65116 533202 -1 29530 15 9717 12154 1180163 283797 4.60176 4.60176 -4317.78 -4.60176 0 0 2.70930e+06 4007.84 0.83 0.68 0.45 -1 -1 0.83 0.396535 0.354423 3072 2256 817 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_45.v common 54.27 vpr 97.45 MiB 0.29 19848 -1 -1 1 0.86 -1 -1 43752 -1 -1 406 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 99784 22 19 6485 5365 1 3415 460 26 26 676 clb auto 61.4 MiB 5.72 22624 140685 34814 96882 8989 97.4 MiB 2.38 0.03 4.48156 -4103.24 -4.48156 4.48156 1.75 0.0108887 0.00973389 0.910155 0.806291 50 36300 23 1.91809e+07 1.02953e+07 2.15046e+06 3181.16 35.78 4.8435 4.21885 63768 504694 -1 31167 13 10359 13165 1307358 324247 4.60176 4.60176 -4375.92 -4.60176 0 0 2.57128e+06 3803.68 0.81 0.74 0.42 -1 -1 0.81 0.405213 0.364765 3177 2342 836 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_46.v common 32.21 vpr 97.84 MiB 0.19 20024 -1 -1 1 0.91 -1 -1 43916 -1 -1 411 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100184 22 19 6559 5422 1 3449 465 26 26 676 clb auto 61.9 MiB 6.60 25506 149865 38664 101092 10109 97.8 MiB 2.67 0.03 4.48156 -4212.37 -4.48156 4.48156 1.84 0.01155 0.0100428 0.99278 0.873518 54 41203 26 1.91809e+07 1.03587e+07 2.26288e+06 3347.46 12.00 3.68277 3.22084 65792 548382 -1 34168 15 10921 13370 1528099 357175 4.60176 4.60176 -4476.26 -4.60176 0 0 2.78165e+06 4114.86 0.79 0.72 0.45 -1 -1 0.79 0.406959 0.362956 3215 2361 855 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_47.v common 31.14 vpr 99.51 MiB 0.29 20428 -1 -1 1 0.95 -1 -1 44560 -1 -1 421 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 101896 22 19 6735 5564 1 3561 475 26 26 676 clb auto 63.1 MiB 6.24 25310 154191 38459 104957 10775 99.0 MiB 2.64 0.03 4.42058 -4395.65 -4.42058 4.42058 1.77 0.0114443 0.0102196 0.993177 0.874618 54 40333 20 1.91809e+07 1.04854e+07 2.26288e+06 3347.46 11.75 3.82 3.32185 65792 548382 -1 34143 14 10999 13415 1399252 324545 4.48156 4.48156 -4534.97 -4.48156 0 0 2.78165e+06 4114.86 0.84 0.73 0.44 -1 -1 0.84 0.402783 0.361236 3301 2428 874 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_48.v common 31.29 vpr 99.37 MiB 0.17 20476 -1 -1 1 1.03 -1 -1 44148 -1 -1 427 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 101756 22 19 6809 5621 1 3598 481 26 26 676 clb auto 63.5 MiB 6.29 25005 160536 40351 110386 9799 99.4 MiB 2.77 0.03 4.48156 -4491.6 -4.48156 4.48156 1.74 0.0111671 0.00995686 1.02469 0.906026 56 38290 31 1.91809e+07 1.05615e+07 2.31971e+06 3431.53 11.86 3.84741 3.37679 66468 563034 -1 34042 15 10589 12939 1484526 349460 4.60176 4.60176 -4789.55 -4.60176 0 0 2.84390e+06 4206.95 0.80 0.72 0.46 -1 -1 0.80 0.40184 0.356501 3339 2447 893 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_49.v common 31.00 vpr 102.99 MiB 0.31 21084 -1 -1 1 0.94 -1 -1 44412 -1 -1 443 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 105464 22 19 7094 5872 1 3718 498 27 27 729 clb auto 65.0 MiB 6.56 24179 152419 37669 105372 9378 101.0 MiB 2.65 0.03 4.19728 -4586.35 -4.19728 4.19728 1.87 0.0111429 0.00990221 0.979898 0.856498 52 42399 36 1.9726e+07 1.11604e+07 2.38665e+06 3273.86 10.51 3.42089 2.98719 69950 577685 -1 33223 16 11342 13977 1432247 338328 4.48156 4.48156 -4941.55 -4.48156 0 0 2.93284e+06 4023.09 0.88 0.90 0.47 -1 -1 0.88 0.524157 0.472249 3480 2569 912 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_50.v common 36.75 vpr 105.16 MiB 0.33 21384 -1 -1 1 1.16 -1 -1 44104 -1 -1 448 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 107684 22 19 7168 5929 1 3755 503 27 27 729 clb auto 65.2 MiB 6.69 28000 166420 40751 114741 10928 101.5 MiB 2.94 0.03 4.48156 -4578.26 -4.48156 4.48156 1.90 0.0129669 0.0115651 1.12572 0.993242 56 43916 39 1.9726e+07 1.12237e+07 2.51142e+06 3445.02 15.40 4.33648 3.78899 71406 610069 -1 38950 16 12222 15384 1884834 440341 4.60176 4.60176 -4998.93 -4.60176 0 0 3.07846e+06 4222.85 0.95 0.92 0.50 -1 -1 0.95 0.483905 0.433524 3518 2588 931 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_51.v common 40.38 vpr 105.87 MiB 0.36 21596 -1 -1 1 1.05 -1 -1 44764 -1 -1 459 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 108412 22 19 7344 6071 1 3863 514 27 27 729 clb auto 66.9 MiB 6.64 28678 169270 42388 115337 11545 102.6 MiB 2.80 0.03 4.41533 -4778.21 -4.41533 4.41533 1.83 0.0117034 0.0103951 1.02012 0.897826 54 46382 43 1.9726e+07 1.13632e+07 2.44988e+06 3360.60 19.23 4.86679 4.23664 70678 594165 -1 38295 15 12029 14450 1626312 380742 4.48156 4.48156 -5141.25 -4.48156 0 0 3.01106e+06 4130.40 1.00 0.82 0.46 -1 -1 1.00 0.446907 0.396647 3604 2655 950 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_52.v common 37.70 vpr 104.27 MiB 0.36 21756 -1 -1 1 1.12 -1 -1 45316 -1 -1 464 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 106772 22 19 7418 6128 1 3909 519 27 27 729 clb auto 67.1 MiB 6.88 26143 167239 39832 117509 9898 102.7 MiB 2.94 0.03 4.30031 -4799.25 -4.30031 4.30031 1.86 0.0122554 0.0109024 1.03923 0.915693 54 43532 47 1.9726e+07 1.14266e+07 2.44988e+06 3360.60 16.00 4.83717 4.20334 70678 594165 -1 35636 17 11690 14277 1452572 355720 4.36136 4.36136 -5218.21 -4.36136 0 0 3.01106e+06 4130.40 0.94 0.86 0.53 -1 -1 0.94 0.509977 0.45505 3642 2674 969 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_14.v common 11.24 vpr 67.37 MiB 0.06 9432 -1 -1 1 0.12 -1 -1 34808 -1 -1 79 22 0 4 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68984 22 19 1246 925 1 736 124 16 16 256 mult_36 auto 29.5 MiB 1.24 4241 18355 4196 11625 2534 67.4 MiB 0.38 0.01 8.07311 -393.21 -8.07311 8.07311 0.57 0.00311988 0.00285625 0.168593 0.154108 38 9033 43 6.34292e+06 2.58556e+06 558663. 2182.28 6.60 0.809765 0.716733 21316 135884 -1 6718 20 5024 5685 595728 162068 8.13448 8.13448 -417.392 -8.13448 0 0 744679. 2908.90 0.19 0.24 0.09 -1 -1 0.19 0.106176 0.0947645 589 344 247 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_15.v common 20.61 vpr 68.05 MiB 0.07 9540 -1 -1 1 0.15 -1 -1 35248 -1 -1 84 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69684 22 19 1344 989 1 796 130 16 16 256 mult_36 auto 30.6 MiB 1.51 4753 18225 3749 10940 3536 68.1 MiB 0.34 0.01 8.46137 -399.963 -8.46137 8.46137 0.59 0.00267077 0.00244665 0.164538 0.150832 40 9325 41 6.34292e+06 3.04495e+06 583096. 2277.72 15.54 1.45096 1.27986 21572 140635 -1 7587 24 6351 7155 819730 219125 8.06128 8.06128 -488.017 -8.06128 0 0 763333. 2981.77 0.20 0.33 0.13 -1 -1 0.20 0.137446 0.122756 633 369 266 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_16.v common 10.49 vpr 68.47 MiB 0.10 9628 -1 -1 1 0.17 -1 -1 35048 -1 -1 89 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70116 22 19 1418 1046 1 833 135 16 16 256 mult_36 auto 30.9 MiB 1.59 4903 22971 5326 13381 4264 68.5 MiB 0.42 0.01 8.1423 -435.818 -8.1423 8.1423 0.58 0.00275106 0.00252177 0.197817 0.181108 44 8716 37 6.34292e+06 3.10834e+06 649498. 2537.10 5.33 1.17548 1.03474 22336 155612 -1 7030 22 4906 5497 598759 157899 7.39308 7.39308 -479.139 -7.39308 0 0 820238. 3204.05 0.21 0.25 0.09 -1 -1 0.21 0.124865 0.111257 671 388 285 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_17.v common 8.65 vpr 69.00 MiB 0.08 10204 -1 -1 1 0.19 -1 -1 35396 -1 -1 95 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70660 22 19 1518 1112 1 899 141 16 16 256 mult_36 auto 31.5 MiB 1.46 5556 17709 3644 11642 2423 69.0 MiB 0.35 0.01 8.90161 -437.56 -8.90161 8.90161 0.55 0.00293275 0.00267956 0.158421 0.144964 46 9741 26 6.34292e+06 3.18441e+06 684529. 2673.94 3.47 0.839932 0.745992 22592 160355 -1 7950 22 5670 6223 725059 195443 8.13305 8.13305 -481.209 -8.13305 0 0 838722. 3276.26 0.21 0.30 0.15 -1 -1 0.21 0.14019 0.125408 717 415 304 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_18.v common 13.78 vpr 69.55 MiB 0.07 10252 -1 -1 1 0.15 -1 -1 34892 -1 -1 100 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71216 22 19 1592 1169 1 937 146 16 16 256 mult_36 auto 31.9 MiB 1.64 5565 22034 5042 13956 3036 69.5 MiB 0.42 0.01 8.87973 -457.467 -8.87973 8.87973 0.62 0.00310544 0.00284191 0.193774 0.177316 42 11318 39 6.34292e+06 3.2478e+06 613404. 2396.11 8.14 1.38438 1.21964 21828 146600 -1 8699 22 6205 6918 797479 216264 8.34213 8.34213 -594.881 -8.34213 0 0 784202. 3063.29 0.25 0.33 0.12 -1 -1 0.25 0.146706 0.131004 755 434 323 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_19.v common 11.33 vpr 69.94 MiB 0.11 10548 -1 -1 1 0.22 -1 -1 35336 -1 -1 105 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71616 22 19 1688 1231 1 998 152 16 16 256 mult_36 auto 32.5 MiB 1.86 5757 22427 4578 13882 3967 69.9 MiB 0.44 0.01 8.92361 -471.887 -8.92361 8.92361 0.56 0.00324852 0.00295972 0.195619 0.178395 48 9652 27 6.34292e+06 3.70719e+06 714410. 2790.66 5.63 1.35638 1.19582 22848 165380 -1 8651 22 5351 6026 732157 188713 8.18805 8.18805 -546.947 -8.18805 0 0 863353. 3372.47 0.22 0.30 0.10 -1 -1 0.22 0.147667 0.131721 797 457 342 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_20.v common 12.61 vpr 70.42 MiB 0.13 10708 -1 -1 1 0.22 -1 -1 35620 -1 -1 110 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72112 22 19 1762 1288 1 1033 157 16 16 256 mult_36 auto 32.8 MiB 1.88 5909 26383 5594 16039 4750 70.4 MiB 0.51 0.01 8.83537 -533.405 -8.83537 8.83537 0.56 0.00334843 0.00305355 0.229503 0.208935 46 10553 28 6.34292e+06 3.77058e+06 684529. 2673.94 6.59 1.4927 1.31724 22592 160355 -1 8432 21 5501 6184 629963 165433 8.19799 8.19799 -535.068 -8.19799 0 0 838722. 3276.26 0.21 0.29 0.14 -1 -1 0.21 0.14789 0.13221 835 476 361 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_21.v common 19.27 vpr 71.07 MiB 0.14 11088 -1 -1 1 0.26 -1 -1 35780 -1 -1 117 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72772 22 19 1859 1351 1 1097 164 16 16 256 mult_36 auto 33.3 MiB 2.10 6877 26148 4845 17989 3314 71.1 MiB 0.52 0.01 9.10283 -530.329 -9.10283 9.10283 0.55 0.00350904 0.00319379 0.219292 0.199579 46 12941 28 6.34292e+06 3.85933e+06 684529. 2673.94 12.86 1.68486 1.48673 22592 160355 -1 9640 20 5382 6297 642924 169839 8.50765 8.50765 -651.006 -8.50765 0 0 838722. 3276.26 0.24 0.30 0.14 -1 -1 0.24 0.158102 0.141691 878 500 380 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_22.v common 12.47 vpr 71.47 MiB 0.09 11048 -1 -1 1 0.24 -1 -1 35836 -1 -1 121 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73184 22 19 1933 1408 1 1134 168 16 16 256 mult_36 auto 33.9 MiB 2.14 7422 25170 4911 15658 4601 71.5 MiB 0.48 0.01 9.01458 -573.662 -9.01458 9.01458 0.57 0.00366039 0.00333703 0.217225 0.1982 48 13367 46 6.34292e+06 3.91004e+06 714410. 2790.66 5.95 1.20201 1.06296 22848 165380 -1 10834 24 6813 8030 1002292 248924 8.32694 8.32694 -795.331 -8.32694 0 0 863353. 3372.47 0.22 0.40 0.15 -1 -1 0.22 0.183735 0.163565 916 519 399 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_23.v common 11.86 vpr 72.08 MiB 0.09 11388 -1 -1 1 0.27 -1 -1 36152 -1 -1 129 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73808 22 19 2031 1472 1 1198 177 18 18 324 mult_36 auto 34.6 MiB 2.24 7275 31425 6625 21832 2968 72.1 MiB 0.66 0.01 9.00463 -548.336 -9.00463 9.00463 0.74 0.00390493 0.00356234 0.258931 0.235866 46 14196 45 7.79418e+06 4.40746e+06 895831. 2764.91 4.56 1.12575 0.997804 29024 211752 -1 10934 25 6882 7848 880826 223229 8.43839 8.43839 -703.752 -8.43839 0 0 1.09776e+06 3388.15 0.29 0.39 0.17 -1 -1 0.29 0.19905 0.177408 960 544 418 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_24.v common 12.36 vpr 72.46 MiB 0.09 11464 -1 -1 1 0.25 -1 -1 36348 -1 -1 134 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74196 22 19 2105 1529 1 1235 182 18 18 324 mult_36 auto 35.0 MiB 2.48 7801 30567 6031 22002 2534 72.5 MiB 0.61 0.01 8.93461 -590.946 -8.93461 8.93461 0.74 0.00432734 0.00392692 0.248296 0.225855 44 15786 47 7.79418e+06 4.47085e+06 850563. 2625.19 4.97 1.26592 1.11687 28700 205432 -1 11441 21 7563 8584 1010699 259800 8.45525 8.45525 -751.332 -8.45525 0 0 1.07356e+06 3313.45 0.29 0.41 0.17 -1 -1 0.29 0.184476 0.164299 998 563 437 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_25.v common 15.88 vpr 73.18 MiB 0.16 11912 -1 -1 1 0.26 -1 -1 36644 -1 -1 139 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74940 22 19 2201 1591 1 1295 187 18 18 324 mult_36 auto 35.6 MiB 2.58 7794 35431 8008 24050 3373 73.2 MiB 0.75 0.01 8.99805 -627.204 -8.99805 8.99805 0.76 0.00409877 0.00373479 0.29492 0.268298 48 14419 25 7.79418e+06 4.53424e+06 935225. 2886.50 7.93 1.6909 1.49346 29348 218440 -1 11847 24 9376 10639 1260323 308837 8.19914 8.19914 -859.595 -8.19914 0 0 1.13028e+06 3488.51 0.31 0.46 0.19 -1 -1 0.31 0.202649 0.180363 1040 586 456 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_26.v common 15.96 vpr 73.44 MiB 0.16 11904 -1 -1 1 0.27 -1 -1 37360 -1 -1 143 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75200 22 19 2275 1648 1 1331 191 18 18 324 mult_36 auto 36.1 MiB 2.25 8212 29837 6030 19775 4032 73.4 MiB 0.58 0.01 9.02558 -646.811 -9.02558 9.02558 0.75 0.00428548 0.00390516 0.253584 0.230771 46 15122 38 7.79418e+06 4.58495e+06 895831. 2764.91 8.59 1.9133 1.68997 29024 211752 -1 11958 22 7098 8090 861622 220837 8.17599 8.17599 -727.5 -8.17599 0 0 1.09776e+06 3388.15 0.29 0.38 0.19 -1 -1 0.29 0.193184 0.173255 1078 605 475 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_27.v common 17.03 vpr 74.23 MiB 0.11 12160 -1 -1 1 0.30 -1 -1 36788 -1 -1 151 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76008 22 19 2385 1724 1 1408 200 18 18 324 mult_36 auto 36.7 MiB 2.60 8727 36992 8286 24092 4614 74.2 MiB 0.76 0.01 8.93461 -662.978 -8.93461 8.93461 0.76 0.00472339 0.00425073 0.301533 0.274021 48 15283 36 7.79418e+06 5.08238e+06 935225. 2886.50 8.89 2.08068 1.8344 29348 218440 -1 12726 23 9179 10508 1335353 324369 8.28419 8.28419 -946.068 -8.28419 0 0 1.13028e+06 3488.51 0.30 0.49 0.19 -1 -1 0.30 0.205865 0.184459 1134 642 494 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_28.v common 16.72 vpr 74.45 MiB 0.17 12356 -1 -1 1 0.31 -1 -1 36712 -1 -1 156 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76232 22 19 2459 1781 1 1444 205 18 18 324 mult_36 auto 37.1 MiB 2.68 8451 39465 8337 25107 6021 74.4 MiB 0.76 0.01 9.16641 -691.339 -9.16641 9.16641 0.74 0.00462481 0.00422355 0.316536 0.287465 48 14904 25 7.79418e+06 5.14577e+06 935225. 2886.50 8.55 2.04169 1.80553 29348 218440 -1 12614 21 8926 10211 1159620 293360 8.50739 8.50739 -823.07 -8.50739 0 0 1.13028e+06 3488.51 0.30 0.45 0.19 -1 -1 0.30 0.203297 0.181535 1172 661 513 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_29.v common 47.46 vpr 75.10 MiB 0.11 12536 -1 -1 1 0.33 -1 -1 37136 -1 -1 163 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76900 22 19 2565 1853 1 1517 213 22 22 484 mult_36 auto 37.8 MiB 2.97 9736 37678 8527 25986 3165 75.1 MiB 0.75 0.01 8.92046 -697.22 -8.92046 8.92046 1.15 0.00455768 0.00415114 0.297373 0.26977 44 19381 44 1.26954e+07 5.63051e+06 1.30964e+06 2705.88 37.68 2.69823 2.37585 43422 318546 -1 14570 23 9535 10931 1293369 324951 8.36113 8.36113 -893.601 -8.36113 0 0 1.65337e+06 3416.05 0.47 0.54 0.29 -1 -1 0.47 0.243977 0.218617 1224 694 532 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_30.v common 21.61 vpr 75.55 MiB 0.15 12620 -1 -1 1 0.35 -1 -1 37288 -1 -1 168 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77368 22 19 2639 1910 1 1554 218 22 22 484 mult_36 auto 38.7 MiB 2.93 9704 46068 10050 31278 4740 75.6 MiB 0.90 0.01 9.05578 -707.338 -9.05578 9.05578 1.22 0.00505393 0.00458653 0.362219 0.32803 46 18565 36 1.26954e+07 5.6939e+06 1.37878e+06 2848.72 11.65 2.2504 1.98663 43906 328446 -1 14231 21 9207 10549 1182524 287358 8.44828 8.44828 -1021.22 -8.44828 0 0 1.69059e+06 3492.95 0.48 0.49 0.29 -1 -1 0.48 0.22278 0.199444 1262 713 551 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_31.v common 18.40 vpr 76.16 MiB 0.19 12948 -1 -1 1 0.36 -1 -1 37572 -1 -1 175 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77984 22 19 2744 1981 1 1626 225 22 22 484 mult_36 auto 39.1 MiB 3.06 10429 54261 13323 35940 4998 76.2 MiB 1.06 0.01 9.21706 -731.706 -9.21706 9.21706 1.19 0.00506592 0.00460699 0.417543 0.377769 46 19383 40 1.26954e+07 5.78265e+06 1.37878e+06 2848.72 7.99 1.79479 1.59544 43906 328446 -1 15283 22 9077 10419 1338103 316338 8.27705 8.27705 -922.434 -8.27705 0 0 1.69059e+06 3492.95 0.47 0.57 0.28 -1 -1 0.47 0.263815 0.237002 1313 745 570 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_32.v common 22.02 vpr 76.43 MiB 0.11 13016 -1 -1 1 0.39 -1 -1 36920 -1 -1 179 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78268 22 19 2818 2038 1 1662 229 22 22 484 mult_36 auto 39.4 MiB 3.20 10391 57629 14299 38067 5263 76.4 MiB 1.16 0.01 8.90432 -796.741 -8.90432 8.90432 1.23 0.00509439 0.00460665 0.45302 0.409964 50 17124 25 1.26954e+07 5.83336e+06 1.50222e+06 3103.76 11.39 2.40958 2.13136 44874 350400 -1 15076 25 10335 11812 1322909 330631 8.19693 8.19693 -1070.7 -8.19693 0 0 1.79645e+06 3711.66 0.51 0.57 0.25 -1 -1 0.51 0.26958 0.240498 1351 764 589 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_33.v common 16.88 vpr 77.11 MiB 0.21 13780 -1 -1 1 0.39 -1 -1 37408 -1 -1 187 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78956 22 19 2923 2109 1 1730 238 22 22 484 mult_36 auto 40.1 MiB 3.20 10842 55513 13255 35231 7027 77.1 MiB 1.05 0.01 9.95249 -834.822 -9.95249 9.95249 1.18 0.00253764 0.00230185 0.418184 0.377872 46 19712 40 1.26954e+07 6.33079e+06 1.37878e+06 2848.72 6.36 1.65683 1.4737 43906 328446 -1 15703 22 9397 10976 1237626 310640 9.04671 9.04671 -1200.39 -9.04671 0 0 1.69059e+06 3492.95 0.48 0.56 0.28 -1 -1 0.48 0.263107 0.234827 1402 796 608 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_34.v common 18.96 vpr 77.73 MiB 0.20 13840 -1 -1 1 0.39 -1 -1 37884 -1 -1 193 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79600 22 19 2997 2166 1 1769 244 22 22 484 mult_36 auto 40.5 MiB 3.32 11512 55870 12803 38332 4735 77.7 MiB 1.10 0.01 9.71104 -846.569 -9.71104 9.71104 1.18 0.00548715 0.00499123 0.421909 0.382237 44 24353 49 1.26954e+07 6.40685e+06 1.30964e+06 2705.88 8.01 1.83971 1.62943 43422 318546 -1 17171 26 12960 14652 1853547 452272 9.15799 9.15799 -1105.75 -9.15799 0 0 1.65337e+06 3416.05 0.48 0.73 0.27 -1 -1 0.48 0.310143 0.276139 1441 815 627 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_35.v common 23.39 vpr 78.45 MiB 0.21 14108 -1 -1 1 0.41 -1 -1 37808 -1 -1 199 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80332 22 19 3101 2236 1 1838 250 22 22 484 mult_36 auto 41.3 MiB 3.53 11883 59275 13898 40462 4915 78.4 MiB 1.24 0.02 10.0716 -839.08 -10.0716 10.0716 1.19 0.00572678 0.00520149 0.474643 0.430492 46 21331 31 1.26954e+07 6.48292e+06 1.37878e+06 2848.72 12.12 2.66162 2.35294 43906 328446 -1 17287 21 10101 11468 1346054 329306 9.20985 9.20985 -1049.74 -9.20985 0 0 1.69059e+06 3492.95 0.47 0.54 0.27 -1 -1 0.47 0.254172 0.227458 1491 846 646 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_36.v common 25.66 vpr 78.64 MiB 0.13 14164 -1 -1 1 0.42 -1 -1 38088 -1 -1 203 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80532 22 19 3175 2293 1 1872 254 22 22 484 mult_36 auto 41.7 MiB 3.56 11856 67790 16050 43614 8126 78.6 MiB 1.29 0.02 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v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82676 22 19 3531 2547 1 2089 279 24 24 576 mult_36 auto 43.9 MiB 4.04 13649 81358 20240 53084 8034 80.7 MiB 1.55 0.02 9.76447 -1012.02 -9.76447 9.76447 1.44 0.00627344 0.00568308 0.596184 0.538567 46 24498 47 1.53347e+07 7.23391e+06 1.63708e+06 2842.15 10.31 2.32309 2.0508 51922 389946 -1 19547 23 11831 13375 1622364 412860 8.89731 8.89731 -1325.41 -8.89731 0 0 2.00908e+06 3487.99 0.56 0.69 0.34 -1 -1 0.56 0.32088 0.286395 1705 965 741 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_41.v common 23.80 vpr 81.44 MiB 0.24 15120 -1 -1 1 0.63 -1 -1 38080 -1 -1 233 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83396 22 19 3634 2616 1 2155 286 24 24 576 mult_36 auto 44.5 MiB 5.19 13461 71802 17518 48500 5784 81.4 MiB 1.44 0.02 9.84473 -990.415 -9.84473 9.84473 1.49 0.00682155 0.00620547 0.551807 0.496406 46 24068 31 1.53347e+07 7.70597e+06 1.63708e+06 2842.15 9.20 2.20878 1.9572 51922 389946 -1 19383 21 10783 12491 1296656 334801 9.01371 9.01371 -1397.76 -9.01371 0 0 2.00908e+06 3487.99 0.56 0.58 0.31 -1 -1 0.56 0.291691 0.25952 1754 995 760 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_42.v common 26.35 vpr 81.95 MiB 0.23 15460 -1 -1 1 0.54 -1 -1 38248 -1 -1 238 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83920 22 19 3708 2673 1 2193 291 24 24 576 mult_36 auto 45.0 MiB 4.33 13774 73555 16192 46647 10716 82.0 MiB 1.46 0.02 9.6448 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-k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_45.v common 22.00 vpr 83.36 MiB 0.27 16076 -1 -1 1 0.66 -1 -1 40428 -1 -1 256 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85360 22 19 3989 2869 1 2368 310 24 24 576 mult_36 auto 46.3 MiB 4.47 16170 76814 16744 54012 6058 83.4 MiB 1.63 0.02 9.69686 -1053.48 -9.69686 9.69686 1.51 0.00733892 0.00667215 0.584672 0.525516 48 27771 33 1.53347e+07 8.39357e+06 1.71014e+06 2969.00 7.65 2.13518 1.89576 52498 402441 -1 23267 23 14444 16589 2052278 495094 9.46445 9.46445 -1673.39 -9.46445 0 0 2.06880e+06 3591.66 0.60 0.85 0.29 -1 -1 0.60 0.365172 0.325707 1929 1094 836 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_46.v common 23.54 vpr 84.10 MiB 0.26 16096 -1 -1 1 0.61 -1 -1 40696 -1 -1 260 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86116 22 19 4063 2926 1 2404 314 24 24 576 mult_36 auto 47.2 MiB 4.78 15339 80264 18599 54196 7469 84.1 MiB 1.70 0.02 10.1503 -1097.92 -10.1503 10.1503 1.37 0.0080052 0.0071957 0.606251 0.544168 48 26539 34 1.53347e+07 8.44428e+06 1.71014e+06 2969.00 8.51 2.26702 2.00623 52498 402441 -1 22415 22 12869 14913 1883761 456417 9.18285 9.18285 -1669.24 -9.18285 0 0 2.06880e+06 3591.66 0.59 0.79 0.34 -1 -1 0.59 0.345793 0.309364 1967 1113 855 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_47.v common 26.53 vpr 84.31 MiB 0.29 16492 -1 -1 1 0.68 -1 -1 40776 -1 -1 267 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86336 22 19 4167 2996 1 2473 321 24 24 576 mult_36 auto 47.5 MiB 5.05 15911 94749 24093 55772 14884 84.3 MiB 1.98 0.02 9.84328 -1100.98 -9.84328 9.84328 1.68 0.00765987 0.00694488 0.760369 0.680609 52 27975 40 1.53347e+07 8.53303e+06 1.82869e+06 3174.81 10.22 2.77005 2.44505 54222 439550 -1 21924 24 13845 15738 1880408 458130 8.78434 8.78434 -1662.3 -8.78434 0 0 2.25030e+06 3906.77 0.65 0.81 0.38 -1 -1 0.65 0.378633 0.337232 2017 1144 874 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_48.v common 25.99 vpr 84.62 MiB 0.29 16564 -1 -1 1 0.63 -1 -1 40944 -1 -1 272 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86648 22 19 4241 3053 1 2509 326 24 24 576 mult_36 auto 47.7 MiB 6.23 15944 93369 22969 60571 9829 84.6 MiB 1.86 0.02 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crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_14.v common 13.36 vpr 70.26 MiB 0.09 10424 -1 -1 8 0.47 -1 -1 34572 -1 -1 167 22 0 4 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 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9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76224 22 19 2488 2337 1 1296 281 20 20 400 clb auto 34.2 MiB 0.79 10108 52721 12182 37607 2932 74.4 MiB 0.72 0.01 4.33936 -1893.53 -4.33936 4.33936 0.44 0.00513677 0.00460665 0.29455 0.260628 -1 -1 -1 -1 42 20702 48 1.09209e+07 5.19687e+06 1.00142e+06 2503.56 5.54 1.53183 1.3355 33938 240731 -1 16690 15 5263 11971 845516 215430 4.57976 4.57976 -1989.21 -4.57976 0 0 1.27864e+06 3196.60 0.05 0.37 0.19 -1 -1 0.05 0.185413 0.164913 1360 1360 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_20.v common 20.34 vpr 74.65 MiB 0.15 12440 -1 -1 8 0.72 -1 -1 37452 -1 -1 242 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76440 22 19 2546 2395 1 1327 289 21 21 441 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78972 22 19 3005 2820 1 1580 334 22 22 484 clb auto 36.4 MiB 0.59 12197 69814 16429 49622 3763 77.1 MiB 0.61 0.01 4.39565 -2299.56 -4.39565 4.39565 0.44 0.00315432 0.00282751 0.205453 0.180694 -1 -1 -1 -1 44 23896 48 1.25085e+07 6.21973e+06 1.30964e+06 2705.88 21.51 2.81539 2.41828 42222 317661 -1 20018 14 6355 14283 1038692 270318 4.45956 4.45956 -2489.25 -4.45956 0 0 1.65337e+06 3416.05 0.07 0.44 0.25 -1 -1 0.07 0.215637 0.192196 1656 1656 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_25.v common 33.50 vpr 78.28 MiB 0.10 14148 -1 -1 8 1.00 -1 -1 40376 -1 -1 301 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80160 22 19 3229 3027 1 1681 349 23 23 529 clb auto 37.5 MiB 1.06 12977 75257 18358 53198 3701 78.3 MiB 1.08 0.02 4.20914 -2487.72 -4.20914 4.20914 0.61 0.00633471 0.00564081 0.435315 0.383338 -1 -1 -1 -1 46 25322 26 1.29425e+07 6.40056e+06 1.51613e+06 2866.03 25.87 3.15091 2.706 46482 360645 -1 20392 15 6168 14237 875172 225052 4.33936 4.33936 -2618 -4.33936 0 0 1.85922e+06 3514.59 0.08 0.43 0.28 -1 -1 0.08 0.235902 0.211186 1771 1771 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_26.v common 31.57 vpr 78.65 MiB 0.19 14376 -1 -1 8 1.08 -1 -1 40752 -1 -1 310 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80536 22 19 3287 3085 1 1716 358 23 23 529 clb auto 37.6 MiB 1.10 13044 77828 19200 55176 3452 78.6 MiB 1.09 0.02 4.33936 -2551.51 -4.33936 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/home/elgamma8/research/release/vtr-verilog-to-routing 121012 22 19 6600 6177 1 3516 701 32 32 1024 clb auto 54.0 MiB 2.25 28670 252773 74309 169713 8751 111.3 MiB 3.47 0.04 4.49301 -5297.83 -4.49301 4.49301 1.27 0.0139262 0.0124467 1.19941 1.0457 -1 -1 -1 -1 48 51786 44 3.00046e+07 1.33315e+07 3.15722e+06 3083.23 66.78 7.45152 6.3921 92896 748174 -1 44132 14 12610 29612 1930272 478078 4.45956 4.45956 -5598.89 -4.45956 0 0 3.82033e+06 3730.79 0.18 0.91 0.58 -1 -1 0.18 0.463107 0.411713 3692 3692 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_14.v common 10.85 vpr 68.50 MiB 0.10 9364 -1 -1 10 0.49 -1 -1 35168 -1 -1 129 22 0 4 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70148 22 19 1149 1049 1 759 174 16 16 256 mult_36 auto 28.0 MiB 0.39 5184 23939 4710 17099 2130 68.5 MiB 0.33 0.01 13.5198 -443.456 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71320 22 19 1507 1373 1 991 218 18 18 324 clb auto 30.4 MiB 0.53 7362 30348 5713 22491 2144 69.6 MiB 0.43 0.01 14.8725 -555.907 -14.8725 14.8725 0.36 0.00359591 0.00327891 0.185193 0.16836 -1 -1 -1 -1 54 13406 22 7.67456e+06 4.05346e+06 1.02660e+06 3168.53 2.82 0.944802 0.832068 29872 244976 -1 12074 19 4649 10391 624229 159812 13.4966 13.4966 -696.578 -13.4966 0 0 1.26286e+06 3897.71 0.05 0.29 0.19 -1 -1 0.05 0.150286 0.133957 961 961 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_19.v common 12.51 vpr 70.14 MiB 0.12 10404 -1 -1 11 0.66 -1 -1 36104 -1 -1 183 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71828 22 19 1596 1445 1 1066 230 18 18 324 clb auto 30.6 MiB 0.40 7944 35430 6947 26296 2187 70.1 MiB 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 101752 22 19 4305 3882 1 2862 558 29 29 841 clb auto 45.5 MiB 1.42 22691 158982 41824 110259 6899 91.0 MiB 2.07 0.03 16.6868 -1410.23 -16.6868 16.6868 1.00 0.0098307 0.008898 0.737926 0.654456 -1 -1 -1 -1 54 40794 35 2.24058e+07 1.16077e+07 2.80981e+06 3341.03 61.81 5.74602 5.00323 78400 678428 -1 35834 21 13983 32924 2124657 520135 15.259 15.259 -1939.91 -15.259 0 0 3.45506e+06 4108.28 0.15 0.97 0.53 -1 -1 0.15 0.456186 0.407309 2826 2826 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_52.v common 64.09 vpr 97.14 MiB 0.31 17592 -1 -1 13 2.71 -1 -1 39888 -1 -1 507 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 99468 22 19 4363 3940 1 2893 562 29 29 841 clb auto 45.6 MiB 1.45 22976 167458 43444 116381 7633 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77224 22 19 2536 2130 1 1284 256 19 19 361 clb auto 35.5 MiB 0.73 7943 48976 10568 34606 3802 75.4 MiB 0.71 0.01 4.19769 -1575.78 -4.19769 4.19769 0.40 0.00421759 0.00376835 0.28038 0.250024 -1 -1 -1 -1 38 14826 29 8.13532e+06 4.61718e+06 822740. 2279.06 9.82 1.90607 1.64658 30442 202059 -1 11445 15 3911 5068 425584 124345 4.24116 4.24116 -1631.53 -4.24116 0 0 1.09718e+06 3039.29 0.04 0.25 0.16 -1 -1 0.04 0.152868 0.135649 1228 924 304 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_18.v common 11.05 vpr 75.65 MiB 0.13 12000 -1 -1 1 0.28 -1 -1 37152 -1 -1 220 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77468 22 19 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 117908 22 19 7418 6128 1 3906 690 31 31 961 clb auto 60.8 MiB 2.21 31171 274920 76802 183853 14265 110.9 MiB 4.03 0.05 4.48156 -5029.46 -4.48156 4.48156 1.18 0.0129033 0.0115628 1.21606 1.07363 -1 -1 -1 -1 44 50421 42 2.5096e+07 1.35183e+07 2.69324e+06 2802.54 31.82 4.99006 4.31204 86716 660222 -1 41712 15 11398 14424 1540122 390484 4.72196 4.72196 -5077.4 -4.72196 0 0 3.40179e+06 3539.84 0.16 0.77 0.51 -1 -1 0.16 0.433546 0.384238 3643 2674 969 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_14.v common 5.54 vpr 67.75 MiB 0.09 9396 -1 -1 1 0.16 -1 -1 34652 -1 -1 105 22 0 4 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69380 22 19 1246 925 1 729 150 16 16 256 mult_36 auto 28.8 MiB 0.42 4287 20050 4045 13932 2073 67.8 MiB 0.35 0.01 8.44555 -394.864 -8.44555 8.44555 0.28 0.00252268 0.00231193 0.137422 0.125997 -1 -1 -1 -1 36 9045 37 6.32612e+06 2.90259e+06 535569. 2092.07 2.37 0.631072 0.557954 20808 126872 -1 6872 24 5057 6129 675254 196211 7.96139 7.96139 -477.109 -7.96139 0 0 684529. 2673.94 0.03 0.26 0.11 -1 -1 0.03 0.121495 0.108107 591 344 247 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_15.v common 6.19 vpr 68.48 MiB 0.11 9612 -1 -1 1 0.19 -1 -1 35192 -1 -1 112 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70120 22 19 1344 989 1 789 158 16 16 256 mult_36 auto 29.2 MiB 0.41 4918 25778 5718 17517 2543 68.5 MiB 0.48 0.01 8.50055 -422.339 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vpr 69.84 MiB 0.12 10372 -1 -1 1 0.19 -1 -1 35108 -1 -1 134 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71520 22 19 1592 1169 1 928 180 16 16 256 clb mult_36 auto 30.8 MiB 0.54 5466 32184 7384 21670 3130 69.8 MiB 0.62 0.01 9.07695 -498.175 -9.07695 9.07695 0.28 0.00305233 0.00278916 0.206264 0.188236 -1 -1 -1 -1 38 11809 43 6.32612e+06 3.66277e+06 558663. 2182.28 3.10 0.890721 0.7875 21316 135884 -1 8788 23 6839 8006 836324 249518 8.68285 8.68285 -652.045 -8.68285 0 0 744679. 2908.90 0.03 0.32 0.11 -1 -1 0.03 0.143925 0.127913 757 434 323 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_19.v common 18.37 vpr 70.55 MiB 0.13 10476 -1 -1 1 0.20 -1 -1 35300 -1 -1 141 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72240 22 19 1688 1231 1 988 188 17 17 289 clb auto 31.2 MiB 0.56 6040 29778 6467 18590 4721 70.5 MiB 0.54 0.01 9.14683 -510.28 -9.14683 9.14683 0.32 0.00337204 0.00307949 0.207074 0.188891 -1 -1 -1 -1 40 11750 40 6.64007e+06 4.14668e+06 666494. 2306.21 14.32 1.64128 1.44358 24274 161130 -1 9396 22 6413 7782 829846 236284 8.85905 8.85905 -666.243 -8.85905 0 0 872365. 3018.56 0.03 0.32 0.13 -1 -1 0.03 0.148784 0.132358 799 457 342 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_20.v common 17.96 vpr 70.89 MiB 0.13 10752 -1 -1 1 0.22 -1 -1 35712 -1 -1 147 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72596 22 19 1762 1288 1 1026 194 17 17 289 clb auto 31.6 MiB 0.58 6727 40025 9604 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74468 22 19 2105 1529 1 1224 223 18 18 324 clb mult_36 auto 33.2 MiB 0.69 7747 44163 10132 30236 3795 72.7 MiB 0.80 0.01 9.18099 -606.294 -9.18099 9.18099 0.36 0.00398144 0.00363267 0.286395 0.26078 -1 -1 -1 -1 44 14619 39 7.77114e+06 4.96965e+06 850563. 2625.19 8.75 1.79914 1.57976 28700 205432 -1 11577 23 7286 8761 953169 268335 8.47065 8.47065 -820.552 -8.47065 0 0 1.07356e+06 3313.45 0.04 0.39 0.16 -1 -1 0.04 0.18896 0.167499 1000 563 437 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_25.v common 8.60 vpr 73.39 MiB 0.15 12020 -1 -1 1 0.28 -1 -1 36580 -1 -1 182 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75152 22 19 2201 1591 1 1284 230 18 18 324 clb mult_36 auto 33.9 MiB 0.69 7961 49510 11662 33160 4688 73.4 MiB 0.86 0.01 8.98857 -675.612 -8.98857 8.98857 0.36 0.00418069 0.00380642 0.286762 0.259732 -1 -1 -1 -1 46 14105 33 7.77114e+06 5.05756e+06 895831. 2764.91 3.63 1.28515 1.13409 29024 211752 -1 11360 22 7134 8496 846648 235548 8.25405 8.25405 -875.377 -8.25405 0 0 1.09776e+06 3388.15 0.04 0.34 0.17 -1 -1 0.04 0.182138 0.161881 1042 586 456 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_26.v common 15.03 vpr 73.68 MiB 0.16 11956 -1 -1 1 0.28 -1 -1 37400 -1 -1 189 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75444 22 19 2275 1648 1 1320 237 18 18 324 clb mult_36 auto 34.2 MiB 0.69 8332 51547 11837 33261 6449 73.7 MiB 0.93 0.01 9.20998 -667.689 -9.20998 9.20998 0.36 0.00430745 0.00392566 0.319063 0.289801 -1 -1 -1 -1 44 15572 31 7.77114e+06 5.14546e+06 850563. 2625.19 9.86 1.88471 1.65398 28700 205432 -1 12379 22 7578 9224 954809 269452 8.67185 8.67185 -830.678 -8.67185 0 0 1.07356e+06 3313.45 0.04 0.38 0.16 -1 -1 0.04 0.192164 0.170765 1080 605 475 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_27.v common 17.59 vpr 74.30 MiB 0.16 12248 -1 -1 1 0.30 -1 -1 36696 -1 -1 199 22 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76088 22 19 2385 1724 1 1395 248 19 19 361 clb auto 34.5 MiB 0.72 8712 55486 13505 36286 5695 74.3 MiB 0.93 0.01 9.14633 -671.93 -9.14633 9.14633 0.40 0.00429562 0.00386782 0.322657 0.292637 -1 -1 -1 -1 40 16572 36 8.13532e+06 5.66704e+06 859013. 2379.54 12.11 2.20879 1.93876 30802 209215 -1 13671 23 9626 11438 1195167 335637 8.64865 8.64865 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x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77884 22 19 2639 1910 1 1539 271 22 22 484 mult_36 auto 36.2 MiB 0.86 9909 65971 16907 43504 5560 76.1 MiB 1.22 0.02 9.0891 -763.527 -9.0891 9.0891 0.55 0.00494907 0.0044795 0.389735 0.352486 -1 -1 -1 -1 40 19268 27 1.26594e+07 6.33932e+06 1.17677e+06 2431.33 6.46 1.51266 1.33443 41974 287914 -1 15915 25 12141 14260 1611823 432096 8.74585 8.74585 -895.223 -8.74585 0 0 1.53957e+06 3180.94 0.07 0.55 0.23 -1 -1 0.07 0.23933 0.211973 1264 713 551 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_31.v common 28.21 vpr 76.57 MiB 0.18 13024 -1 -1 1 0.34 -1 -1 37476 -1 -1 231 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78408 22 19 2744 1981 1 1609 281 22 22 484 mult_36 auto 36.7 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6.52769e+06 1.12685e+06 2328.21 22.62 2.69708 2.36845 41490 277996 -1 16087 22 12319 14701 1525128 421166 8.84825 8.84825 -1096.2 -8.84825 0 0 1.50222e+06 3103.76 0.06 0.57 0.22 -1 -1 0.06 0.243455 0.216177 1353 764 589 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_33.v common 12.97 vpr 77.75 MiB 0.20 13700 -1 -1 1 0.37 -1 -1 37496 -1 -1 247 22 0 10 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79612 22 19 2923 2109 1 1714 298 22 22 484 mult_36 auto 37.6 MiB 0.89 10805 77908 19804 48941 9163 77.7 MiB 1.33 0.02 10.0946 -829.447 -10.0946 10.0946 0.55 0.00549627 0.00497002 0.446976 0.403289 -1 -1 -1 -1 44 20199 34 1.26594e+07 7.06183e+06 1.30964e+06 2705.88 5.99 1.7989 1.59048 43422 318546 -1 16375 21 10645 12669 1455180 374595 9.65391 9.65391 -1117.92 -9.65391 0 0 1.65337e+06 3416.05 0.07 0.51 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81000 22 19 3175 2293 1 1856 318 22 22 484 clb mult_36 auto 39.0 MiB 1.01 13199 78438 19409 50137 8892 79.1 MiB 1.42 0.02 10.2693 -910.248 -10.2693 10.2693 0.55 0.00593774 0.00534405 0.444722 0.401248 -1 -1 -1 -1 44 25416 43 1.26594e+07 7.31299e+06 1.30964e+06 2705.88 21.94 2.74676 2.40989 43422 318546 -1 19234 24 10254 12494 1584808 397779 9.57071 9.57071 -1208.42 -9.57071 0 0 1.65337e+06 3416.05 0.07 0.59 0.25 -1 -1 0.07 0.276211 0.24504 1530 865 665 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_37.v common 46.16 vpr 79.78 MiB 0.22 14476 -1 -1 1 0.42 -1 -1 37556 -1 -1 277 22 0 11 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81692 22 19 3280 2364 1 1927 329 24 24 576 mult_36 auto 39.6 MiB 1.02 12290 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84868 22 19 3708 2673 1 2172 365 24 24 576 mult_36 auto 41.6 MiB 1.22 14462 120241 32438 75438 12365 82.2 MiB 2.17 0.02 9.96967 -1067.82 -9.96967 9.96967 0.65 0.00646698 0.00585808 0.660337 0.594419 -1 -1 -1 -1 52 24462 42 1.52924e+07 8.6701e+06 1.82869e+06 3174.81 13.80 3.56459 3.12873 54222 439550 -1 20698 22 10976 13483 1592120 415353 9.00471 9.00471 -1584.16 -9.00471 0 0 2.25030e+06 3906.77 0.09 0.64 0.35 -1 -1 0.09 0.304663 0.270699 1793 1014 779 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_43.v common 14.31 vpr 82.55 MiB 0.25 15636 -1 -1 1 0.51 -1 -1 38876 -1 -1 321 22 0 12 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84528 22 19 3810 2741 1 2238 374 24 24 576 mult_36 auto 42.1 MiB 1.22 14596 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 87024 22 19 4241 3053 1 2487 411 25 25 625 clb auto 44.3 MiB 1.43 16851 128679 33580 81852 13247 85.0 MiB 2.19 0.03 10.4333 -1182.17 -10.4333 10.4333 0.71 0.00727078 0.00656308 0.651011 0.584255 -1 -1 -1 -1 46 30316 49 1.57822e+07 9.63121e+06 1.78602e+06 2857.63 7.65 2.46871 2.17452 56160 425985 -1 23399 19 11576 14177 1412366 389061 9.45851 9.45851 -1530.31 -9.45851 0 0 2.19200e+06 3507.21 0.09 0.61 0.33 -1 -1 0.09 0.307777 0.274473 2056 1163 893 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_49.v common 30.41 vpr 85.53 MiB 0.30 17148 -1 -1 1 0.61 -1 -1 41080 -1 -1 367 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 87584 22 19 4346 3124 1 2556 422 25 25 625 clb auto 44.7 MiB 1.42 16534 145966 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-1 -1 168 22 0 4 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73836 22 19 1974 1653 1 1034 213 18 18 324 clb auto 32.4 MiB 1.57 6437 36408 8464 25361 2583 72.1 MiB 0.53 0.01 4.17493 -1221.02 -4.17493 4.17493 0.35 0.00353135 0.00317482 0.212 0.190543 -1 -1 -1 -1 38 11873 29 7.79418e+06 3.7139e+06 731621. 2258.09 2.13 0.865345 0.753807 27408 179348 -1 9578 16 3293 4036 387848 110929 4.36136 4.36136 -1291.74 -4.36136 0 0 975281. 3010.13 0.04 0.21 0.14 -1 -1 0.04 0.123114 0.108894 955 708 247 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_15.v common 10.08 vpr 73.14 MiB 0.11 11004 -1 -1 1 0.23 -1 -1 36888 -1 -1 182 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74896 22 19 2144 1789 1 1129 228 18 18 324 clb auto 33.3 MiB 1.78 6855 41292 9386 28690 3216 73.1 MiB 0.59 0.01 4.12096 -1335.05 -4.12096 4.12096 0.35 0.00392815 0.00353498 0.234729 0.21031 -1 -1 -1 -1 36 12852 27 7.79418e+06 4.2874e+06 701445. 2164.95 4.64 1.31645 1.14368 26764 167360 -1 10878 15 3781 4648 441066 132051 4.36136 4.36136 -1397.94 -4.36136 0 0 895831. 2764.91 0.04 0.22 0.13 -1 -1 0.04 0.127815 0.113299 1035 769 266 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_16.v common 11.76 vpr 73.54 MiB 0.12 10880 -1 -1 1 0.25 -1 -1 36860 -1 -1 190 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75308 22 19 2218 1846 1 1177 236 18 18 324 clb auto 34.0 MiB 1.84 7711 49079 11493 33399 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x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 107268 22 19 6485 5365 1 3397 606 30 30 900 clb auto 56.4 MiB 5.35 22826 236402 66664 157987 11751 102.1 MiB 3.35 0.04 4.30031 -4327.06 -4.30031 4.30031 1.07 0.0103941 0.00921231 1.01692 0.892236 -1 -1 -1 -1 42 39063 32 2.45387e+07 1.21463e+07 2.38040e+06 2644.88 40.63 5.17453 4.4485 79656 579061 -1 32498 17 10688 13571 1349892 354774 4.36136 4.36136 -4464.7 -4.36136 0 0 3.03473e+06 3371.92 0.13 0.72 0.44 -1 -1 0.13 0.414525 0.366798 3178 2342 836 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_46.v common 79.18 vpr 109.56 MiB 0.31 20060 -1 -1 1 0.90 -1 -1 43976 -1 -1 561 22 0 13 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 112192 22 19 6559 5422 1 3448 615 30 30 900 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0.11 10272 -1 -1 1 0.18 -1 -1 35368 -1 -1 127 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71256 22 19 1518 1112 1 892 173 16 16 256 mult_36 auto 30.3 MiB 0.65 5503 28071 5933 18743 3395 69.6 MiB 0.49 0.01 8.91743 -462.46 -8.91743 8.91743 0.29 0.00295234 0.00270461 0.189539 0.173372 -1 -1 -1 -1 38 11258 42 6.34292e+06 3.59011e+06 558663. 2182.28 5.29 1.1709 1.0309 21316 135884 -1 8513 21 6222 7437 682588 201755 8.48434 8.48434 -576.047 -8.48434 0 0 744679. 2908.90 0.03 0.27 0.11 -1 -1 0.03 0.128485 0.114432 719 415 304 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_18.v common 6.42 vpr 69.94 MiB 0.10 10248 -1 -1 1 0.21 -1 -1 34952 -1 -1 134 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71616 22 19 1592 1169 1 928 180 16 16 256 clb mult_36 auto 30.7 MiB 0.64 5724 31676 7309 20857 3510 69.9 MiB 0.57 0.01 8.93251 -473.848 -8.93251 8.93251 0.28 0.00321904 0.00295322 0.2123 0.193994 -1 -1 -1 -1 40 10073 47 6.34292e+06 3.67885e+06 583096. 2277.72 2.38 0.879715 0.778536 21572 140635 -1 8764 24 5909 7048 709438 207670 8.43039 8.43039 -586.215 -8.43039 0 0 763333. 2981.77 0.03 0.30 0.11 -1 -1 0.03 0.1475 0.13093 757 434 323 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_19.v common 16.88 vpr 70.49 MiB 0.12 10616 -1 -1 1 0.20 -1 -1 35336 -1 -1 141 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72184 22 19 1688 1231 1 988 188 17 17 289 clb auto 31.2 MiB 0.71 6258 37848 9148 22741 5959 70.5 MiB 0.63 0.01 9.05754 -504.418 -9.05754 9.05754 0.31 0.00319327 0.00290678 0.237097 0.216084 -1 -1 -1 -1 44 11257 33 6.65987e+06 4.1636e+06 742403. 2568.87 12.65 1.70433 1.49671 25138 178286 -1 9123 22 5698 6671 729354 204335 8.54048 8.54048 -561.246 -8.54048 0 0 937218. 3242.97 0.04 0.30 0.14 -1 -1 0.04 0.14804 0.131823 799 457 342 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_20.v common 14.65 vpr 70.83 MiB 0.13 10704 -1 -1 1 0.21 -1 -1 35564 -1 -1 147 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72528 22 19 1762 1288 1 1026 194 17 17 289 clb auto 31.6 MiB 0.69 6372 41708 10894 25393 5421 70.8 MiB 0.72 0.01 8.88444 -508.436 -8.88444 8.88444 0.31 0.00339803 0.00310403 0.264787 0.240982 -1 -1 -1 -1 40 12323 50 6.65987e+06 4.23967e+06 666494. 2306.21 10.22 1.61063 1.418 24274 161130 -1 9898 23 7805 9172 952233 263407 8.50239 8.50239 -652.802 -8.50239 0 0 872365. 3018.56 0.03 0.37 0.13 -1 -1 0.03 0.16399 0.145904 837 476 361 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_21.v common 9.41 vpr 71.57 MiB 0.14 11128 -1 -1 1 0.22 -1 -1 35816 -1 -1 153 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73284 22 19 1859 1351 1 1087 200 17 17 289 clb auto 32.1 MiB 0.71 7135 41080 9703 25137 6240 71.6 MiB 0.74 0.01 9.05481 -571.674 -9.05481 9.05481 0.32 0.00355987 0.00325093 0.260262 0.23706 -1 -1 -1 -1 48 12634 30 6.65987e+06 4.31573e+06 816265. 2824.45 4.94 1.51572 1.33563 25714 189529 -1 10421 20 5528 6749 743939 205293 8.25194 8.25194 -695.98 -8.25194 0 0 986792. 3414.50 0.04 0.30 0.15 -1 -1 0.04 0.14708 0.131047 880 500 380 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_22.v common 6.87 vpr 71.99 MiB 0.14 11160 -1 -1 1 0.23 -1 -1 35832 -1 -1 160 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73716 22 19 1933 1408 1 1125 207 17 17 289 clb auto 32.5 MiB 0.72 7164 37539 8536 23747 5256 72.0 MiB 0.67 0.01 8.99572 -564.854 -8.99572 8.99572 0.31 0.00365369 0.00332109 0.239411 0.217447 -1 -1 -1 -1 46 12071 28 6.65987e+06 4.40448e+06 782063. 2706.10 2.34 0.897038 0.793261 25426 183746 -1 9756 23 5544 6782 656975 182769 8.12179 8.12179 -677.438 -8.12179 0 0 958460. 3316.47 0.04 0.33 0.15 -1 -1 0.04 0.181285 0.161567 918 519 399 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_23.v common 12.72 vpr 72.27 MiB 0.14 11396 -1 -1 1 0.24 -1 -1 36052 -1 -1 169 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74008 22 19 2031 1472 1 1187 217 18 18 324 clb mult_36 auto 32.8 MiB 0.78 7269 45136 10448 29894 4794 72.3 MiB 0.84 0.01 8.94717 -568.771 -8.94717 8.94717 0.36 0.00385211 0.00351229 0.273839 0.249158 -1 -1 -1 -1 40 14012 42 7.79418e+06 4.91458e+06 763742. 2357.23 7.80 1.66763 1.46752 27732 185676 -1 11431 21 7670 9036 921671 269036 8.55559 8.55559 -694.235 -8.55559 0 0 999570. 3085.09 0.04 0.36 0.15 -1 -1 0.04 0.166579 0.14786 962 544 418 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_24.v common 10.07 vpr 73.32 MiB 0.15 11604 -1 -1 1 0.26 -1 -1 36112 -1 -1 175 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75084 22 19 2105 1529 1 1224 223 18 18 324 clb mult_36 auto 33.8 MiB 0.82 7856 45515 10622 31014 3879 73.3 MiB 0.82 0.01 8.93681 -595.083 -8.93681 8.93681 0.35 0.00381823 0.00346963 0.275426 0.250002 -1 -1 -1 -1 46 14077 24 7.79418e+06 4.99065e+06 895831. 2764.91 5.04 1.60029 1.40502 29024 211752 -1 11512 22 7514 8893 918553 261407 8.35219 8.35219 -631.356 -8.35219 0 0 1.09776e+06 3388.15 0.04 0.37 0.17 -1 -1 0.04 0.180825 0.160726 1000 563 437 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_25.v common 10.13 vpr 73.51 MiB 0.16 11912 -1 -1 1 0.28 -1 -1 36424 -1 -1 182 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75272 22 19 2201 1591 1 1284 230 18 18 324 clb mult_36 auto 33.8 MiB 0.85 8224 50918 12167 30031 8720 73.5 MiB 0.83 0.01 8.99737 -625.34 -8.99737 8.99737 0.36 0.00397983 0.00362109 0.314202 0.285111 -1 -1 -1 -1 48 14542 36 7.79418e+06 5.0794e+06 935225. 2886.50 4.88 1.31157 1.15852 29348 218440 -1 11961 24 7008 8736 915317 241367 8.56039 8.56039 -704.083 -8.56039 0 0 1.13028e+06 3488.51 0.04 0.40 0.17 -1 -1 0.04 0.204017 0.181375 1042 586 456 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_26.v common 8.53 vpr 73.86 MiB 0.16 11876 -1 -1 1 0.27 -1 -1 37400 -1 -1 189 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75628 22 19 2275 1648 1 1320 237 18 18 324 clb mult_36 auto 34.1 MiB 0.81 8346 50814 11462 34501 4851 73.9 MiB 0.96 0.01 9.09558 -657.157 -9.09558 9.09558 0.36 0.00436876 0.00398285 0.319295 0.290452 -1 -1 -1 -1 44 15339 45 7.79418e+06 5.16814e+06 850563. 2625.19 3.22 1.21177 1.07151 28700 205432 -1 12115 22 7823 9299 982087 267789 8.25188 8.25188 -856.357 -8.25188 0 0 1.07356e+06 3313.45 0.04 0.38 0.16 -1 -1 0.04 0.191349 0.170229 1080 605 475 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_27.v common 15.88 vpr 74.38 MiB 0.17 12296 -1 -1 1 0.32 -1 -1 36844 -1 -1 199 22 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76168 22 19 2385 1724 1 1395 248 19 19 361 clb auto 34.5 MiB 0.87 8353 59376 14664 39126 5586 74.4 MiB 1.05 0.01 9.03062 -667.978 -9.03062 9.03062 0.40 0.00460919 0.00421162 0.363484 0.330023 -1 -1 -1 -1 42 16704 48 8.16184e+06 5.69092e+06 904410. 2505.29 10.08 2.07236 1.82372 31162 217923 -1 12970 23 9018 10799 1228060 332168 8.43914 8.43914 -824.709 -8.43914 0 0 1.15452e+06 3198.10 0.05 0.46 0.17 -1 -1 0.05 0.21151 0.188231 1136 642 494 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77352 22 19 2565 1853 1 1503 265 22 22 484 mult_36 auto 36.2 MiB 0.97 9808 64015 16460 42593 4962 75.5 MiB 1.13 0.02 9.05375 -732.273 -9.05375 9.05375 0.55 0.00470731 0.00428202 0.384556 0.348512 -1 -1 -1 -1 40 18429 28 1.26954e+07 6.28977e+06 1.17677e+06 2431.33 24.28 2.52808 2.22106 41974 287914 -1 15451 24 9834 11638 1274098 332704 8.80894 8.80894 -983.307 -8.80894 0 0 1.53957e+06 3180.94 0.06 0.49 0.23 -1 -1 0.06 0.230917 0.205166 1226 694 532 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_30.v common 30.96 vpr 76.09 MiB 0.18 12684 -1 -1 1 0.33 -1 -1 37320 -1 -1 221 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77912 22 19 2639 1910 1 1539 271 22 22 484 mult_36 auto 36.4 MiB 0.97 10302 64219 16193 42182 5844 76.1 MiB 1.11 0.02 9.22277 -769.765 -9.22277 9.22277 0.55 0.00470315 0.00427788 0.370428 0.335355 -1 -1 -1 -1 40 19440 32 1.26954e+07 6.36584e+06 1.17677e+06 2431.33 24.43 2.31453 2.03196 41974 287914 -1 16183 23 10677 12986 1545071 400344 8.83708 8.83708 -956.651 -8.83708 0 0 1.53957e+06 3180.94 0.06 0.53 0.23 -1 -1 0.06 0.225759 0.200111 1264 713 551 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_31.v common 36.68 vpr 76.55 MiB 0.19 13056 -1 -1 1 0.34 -1 -1 37400 -1 -1 231 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78384 22 19 2744 1981 1 1609 281 22 22 484 mult_36 auto 36.9 MiB 0.98 10126 69281 17690 45544 6047 76.5 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 87468 22 19 4241 3053 1 2487 411 25 25 625 clb auto 44.6 MiB 1.46 17117 127152 34394 82360 10398 85.4 MiB 2.38 0.03 9.74538 -1337.51 -9.74538 9.74538 0.72 0.00741054 0.00670671 0.661797 0.592729 -1 -1 -1 -1 48 30943 45 1.58291e+07 9.67405e+06 1.86575e+06 2985.21 7.70 2.31897 2.0396 56784 439662 -1 24260 24 15548 18942 2246437 579527 9.03454 9.03454 -1610.92 -9.03454 0 0 2.25743e+06 3611.89 0.10 0.80 0.34 -1 -1 0.10 0.366347 0.324821 2056 1163 893 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_49.v common 33.98 vpr 85.96 MiB 0.29 17048 -1 -1 1 0.62 -1 -1 41120 -1 -1 367 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 88028 22 19 4346 3124 1 2556 422 25 25 625 clb auto 45.0 MiB 1.54 17917 164950 43977 106885 14088 86.0 MiB 2.98 0.03 9.72864 -1222.9 -9.72864 9.72864 0.72 0.00748269 0.00676769 0.832977 0.745272 -1 -1 -1 -1 48 29936 46 1.58291e+07 1.01968e+07 1.86575e+06 2985.21 22.95 4.21972 3.69785 56784 439662 -1 25226 23 13398 16104 1760306 465428 9.24793 9.24793 -1703.69 -9.24793 0 0 2.25743e+06 3611.89 0.10 0.73 0.35 -1 -1 0.10 0.364782 0.323472 2107 1195 912 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_50.v common 18.62 vpr 86.75 MiB 0.29 17068 -1 -1 1 0.62 -1 -1 41008 -1 -1 373 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 88828 22 19 4420 3181 1 2593 428 25 25 625 clb auto 45.7 MiB 1.51 18261 148732 41199 95280 12253 86.7 MiB 2.57 0.03 9.79718 -1289.48 -9.79718 9.79718 0.71 0.00764436 0.00689871 0.720103 0.645993 -1 -1 -1 -1 48 31646 38 1.58291e+07 1.02729e+07 1.86575e+06 2985.21 7.90 2.54634 2.24429 56784 439662 -1 25317 22 14234 17411 1948373 506791 9.01254 9.01254 -2044.95 -9.01254 0 0 2.25743e+06 3611.89 0.10 0.86 0.34 -1 -1 0.10 0.407263 0.362966 2145 1214 931 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_51.v common 18.28 vpr 86.97 MiB 0.30 17412 -1 -1 1 0.66 -1 -1 41160 -1 -1 383 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 89060 22 19 4524 3251 1 2660 438 25 25 625 clb auto 46.0 MiB 1.53 18966 148356 39141 96657 12558 87.0 MiB 2.65 0.03 9.8742 -1310.12 -9.8742 9.8742 0.71 0.00878717 0.00798343 0.709788 0.637808 -1 -1 -1 -1 48 32817 33 1.58291e+07 1.03997e+07 1.86575e+06 2985.21 8.24 2.45853 2.17254 56784 439662 -1 26245 22 13943 16929 1864054 492094 9.52339 9.52339 -1741.57 -9.52339 0 0 2.25743e+06 3611.89 0.09 0.51 0.25 -1 -1 0.09 0.217762 0.195363 2195 1245 950 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_52.v common 18.19 vpr 87.73 MiB 0.30 17516 -1 -1 1 0.64 -1 -1 39364 -1 -1 389 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 89836 22 19 4598 3308 1 2699 444 25 25 625 clb auto 46.4 MiB 1.56 16791 164665 43738 102572 18355 87.7 MiB 2.77 0.03 9.57983 -1323.89 -9.57983 9.57983 0.71 0.00892576 0.00791173 0.83102 0.74501 -1 -1 -1 -1 50 26877 25 1.58291e+07 1.04757e+07 1.94653e+06 3114.45 7.18 2.79481 2.46273 57408 454416 -1 23850 23 15192 18227 1836466 484557 8.86851 8.86851 -1778.99 -8.86851 0 0 2.32897e+06 3726.35 0.10 0.81 0.36 -1 -1 0.10 0.4043 0.358163 2233 1264 969 19 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt index 3b5b7fa0f97..5e8d0a1b566 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt @@ -1,391 +1,391 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_2ripple_N8_22nm.xml fir_pipe_14.v common 8.50 vpr 71.57 MiB 0.11 10472 -1 -1 1 0.27 -1 -1 35440 -1 -1 65 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73284 22 19 1974 1653 1 1013 110 16 16 256 mult_36 auto 34.0 MiB 0.69 5272 15101 3393 9968 1740 71.6 MiB 0.37 0.01 4.0831 -1115.98 -4.0831 4.0831 0.58 0.0034759 0.00313328 0.217026 0.195977 64 9828 23 6.59459e+06 2.52492e+06 943753. 3686.54 3.60 0.988199 0.864659 27892 240595 -1 8477 16 3926 4549 486168 112677 4.27196 4.27196 -1212.54 -4.27196 0 0 1.19033e+06 4649.74 0.30 0.24 0.21 -1 -1 0.30 0.136181 0.121699 481 708 247 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_15.v common 9.16 vpr 72.44 MiB 0.06 10800 -1 -1 1 0.24 -1 -1 36992 -1 -1 72 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74180 22 19 2144 1789 1 1110 118 16 16 256 mult_36 auto 34.8 MiB 0.98 6136 19192 4400 11965 2827 72.4 MiB 0.47 0.01 4.07762 -1246.61 -4.07762 4.07762 0.53 0.00377881 0.00340845 0.27241 0.245631 68 11309 29 6.59459e+06 3.02225e+06 1.00038e+06 3907.74 3.77 1.15784 1.01647 28404 252462 -1 9516 17 4344 4959 564949 131023 4.27196 4.27196 -1329.64 -4.27196 0 0 1.24648e+06 4869.04 0.30 0.28 0.24 -1 -1 0.30 0.159052 0.141737 521 769 266 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_16.v common 10.44 vpr 72.95 MiB 0.08 10940 -1 -1 1 0.23 -1 -1 36856 -1 -1 74 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74700 22 19 2218 1846 1 1154 120 16 16 256 mult_36 auto 35.3 MiB 0.88 6159 16935 3952 11063 1920 72.9 MiB 0.44 0.01 4.14666 -1298.68 -4.14666 4.14666 0.59 0.00394912 0.00355481 0.245771 0.221636 64 13073 22 6.59459e+06 3.0512e+06 943753. 3686.54 5.23 1.15014 1.00888 27892 240595 -1 10191 20 4784 5574 648344 144961 4.39726 4.39726 -1411.91 -4.39726 0 0 1.19033e+06 4649.74 0.29 0.30 0.21 -1 -1 0.29 0.170515 0.151369 540 788 285 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_17.v common 28.01 vpr 74.32 MiB 0.10 11684 -1 -1 1 0.28 -1 -1 36576 -1 -1 83 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76104 22 19 2536 2130 1 1256 129 16 16 256 mult_36 auto 36.9 MiB 1.18 6865 15729 3064 11003 1662 74.3 MiB 0.42 0.01 4.27196 -1448.46 -4.27196 4.27196 0.58 0.00465454 0.00412377 0.234476 0.211013 62 14881 44 6.59459e+06 3.18149e+06 916467. 3579.95 22.37 2.23199 1.9324 27384 229598 -1 10624 18 4845 5517 591644 141708 4.27196 4.27196 -1513.48 -4.27196 0 0 1.13630e+06 4438.68 0.26 0.30 0.19 -1 -1 0.26 0.179178 0.159375 617 924 304 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_18.v common 9.57 vpr 74.83 MiB 0.10 11884 -1 -1 1 0.31 -1 -1 37200 -1 -1 86 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76624 22 19 2610 2187 1 1305 132 16 16 256 mult_36 auto 37.5 MiB 0.99 6869 16212 3205 10695 2312 74.8 MiB 0.42 0.01 4.03926 -1468.2 -4.03926 4.03926 0.58 0.00449043 0.00402742 0.234775 0.2109 70 12353 27 6.59459e+06 3.22491e+06 1.02522e+06 4004.78 3.93 1.22954 1.06835 28912 262511 -1 10716 20 5011 5723 704649 159235 4.27196 4.27196 -1543.19 -4.27196 0 0 1.29210e+06 5047.26 0.31 0.34 0.25 -1 -1 0.31 0.199818 0.1773 636 943 323 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_19.v common 10.50 vpr 75.61 MiB 0.11 12332 -1 -1 1 0.23 -1 -1 36868 -1 -1 91 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77428 22 19 2778 2321 1 1401 138 16 16 256 mult_36 auto 38.4 MiB 0.98 7751 20074 4172 13462 2440 75.6 MiB 0.50 0.01 4.20832 -1614.09 -4.20832 4.20832 0.59 0.00455987 0.00407148 0.282142 0.252858 70 14091 32 6.59459e+06 3.69329e+06 1.02522e+06 4004.78 4.69 1.46178 1.27549 28912 262511 -1 11597 19 5221 6080 670296 155538 4.27196 4.27196 -1747.26 -4.27196 0 0 1.29210e+06 5047.26 0.31 0.34 0.25 -1 -1 0.31 0.20489 0.182093 676 1002 342 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_20.v common 11.55 vpr 76.22 MiB 0.14 12328 -1 -1 1 0.36 -1 -1 36916 -1 -1 93 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78052 22 19 2852 2378 1 1441 140 16 16 256 mult_36 auto 39.0 MiB 1.20 7701 24098 5487 15382 3229 76.2 MiB 0.69 0.01 4.14666 -1615.69 -4.14666 4.14666 0.59 0.00482598 0.00432145 0.385718 0.345251 68 15216 40 6.59459e+06 3.72224e+06 1.00038e+06 3907.74 5.20 1.61757 1.41891 28404 252462 -1 12039 17 5419 6476 661435 153008 4.27196 4.27196 -1732.55 -4.27196 0 0 1.24648e+06 4869.04 0.32 0.34 0.23 -1 -1 0.32 0.201544 0.180315 695 1021 361 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_21.v common 13.54 vpr 77.15 MiB 0.15 12796 -1 -1 1 0.34 -1 -1 37844 -1 -1 97 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79000 22 19 3057 2549 1 1544 144 16 16 256 mult_36 auto 40.0 MiB 1.31 9367 24272 5008 16124 3140 77.1 MiB 0.68 0.01 4.39726 -1835.45 -4.39726 4.39726 0.58 0.00532694 0.00478054 0.376655 0.338089 74 16942 47 6.59459e+06 3.78015e+06 1.07073e+06 4182.55 6.89 2.11826 1.85409 29424 273870 -1 13957 14 5924 6833 901877 190814 4.52256 4.52256 -1968.88 -4.52256 0 0 1.33358e+06 5209.30 0.32 0.36 0.25 -1 -1 0.32 0.186047 0.16608 742 1099 380 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_22.v common 12.36 vpr 77.33 MiB 0.11 13000 -1 -1 1 0.38 -1 -1 37952 -1 -1 100 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79184 22 19 3131 2606 1 1587 147 16 16 256 mult_36 auto 40.3 MiB 1.11 8900 25689 5397 16690 3602 77.3 MiB 0.70 0.01 4.27196 -1832.45 -4.27196 4.27196 0.56 0.00564151 0.00505803 0.391706 0.351179 74 16546 36 6.59459e+06 3.82357e+06 1.07073e+06 4182.55 5.80 1.71816 1.50682 29424 273870 -1 13593 21 6218 7124 883830 200504 4.27196 4.27196 -1953.42 -4.27196 0 0 1.33358e+06 5209.30 0.32 0.45 0.24 -1 -1 0.32 0.256768 0.228242 762 1118 399 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_23.v common 14.10 vpr 78.45 MiB 0.13 13308 -1 -1 1 0.37 -1 -1 38060 -1 -1 107 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80332 22 19 3301 2742 1 1685 155 18 18 324 mult_36 auto 41.3 MiB 1.00 9550 28859 6368 19463 3028 78.4 MiB 0.57 0.01 4.27196 -1973.15 -4.27196 4.27196 0.66 0.00634227 0.00573287 0.287066 0.258115 68 18693 46 8.13932e+06 4.3209e+06 1.31159e+06 4048.11 7.26 1.84939 1.62041 36620 334356 -1 14822 18 6572 7617 914655 195234 4.39726 4.39726 -2060.9 -4.39726 0 0 1.63345e+06 5041.52 0.42 0.44 0.31 -1 -1 0.42 0.239853 0.214582 802 1179 418 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_24.v common 12.49 vpr 78.90 MiB 0.14 13444 -1 -1 1 0.29 -1 -1 38112 -1 -1 109 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80796 22 19 3375 2799 1 1732 157 18 18 324 mult_36 auto 41.8 MiB 0.75 10056 25960 5726 17532 2702 78.9 MiB 0.71 0.01 4.27196 -2004.23 -4.27196 4.27196 0.77 0.00625433 0.00566837 0.392726 0.352573 76 17719 30 8.13932e+06 4.34985e+06 1.43297e+06 4422.75 5.70 1.77721 1.56248 38232 369828 -1 14833 17 6600 7437 899992 195667 4.39726 4.39726 -2169.68 -4.39726 0 0 1.77541e+06 5479.65 0.46 0.43 0.33 -1 -1 0.46 0.242617 0.21773 821 1198 437 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_25.v common 13.23 vpr 79.76 MiB 0.14 14020 -1 -1 1 0.37 -1 -1 38096 -1 -1 116 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81676 22 19 3615 3005 1 1836 164 18 18 324 mult_36 auto 42.7 MiB 1.03 10729 33764 7877 22457 3430 79.8 MiB 0.90 0.01 4.39726 -2180.78 -4.39726 4.39726 0.78 0.00623701 0.00557538 0.503163 0.449551 76 19342 24 8.13932e+06 4.45118e+06 1.43297e+06 4422.75 5.58 1.93758 1.70715 38232 369828 -1 16315 17 6932 7862 1003575 222232 4.39726 4.39726 -2258.25 -4.39726 0 0 1.77541e+06 5479.65 0.46 0.52 0.33 -1 -1 0.46 0.27578 0.248193 877 1293 456 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_26.v common 15.22 vpr 80.33 MiB 0.15 14088 -1 -1 1 0.44 -1 -1 38552 -1 -1 118 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82260 22 19 3689 3062 1 1874 166 18 18 324 mult_36 auto 43.3 MiB 1.16 10442 30262 6705 20097 3460 80.3 MiB 0.77 0.01 4.27196 -2184.83 -4.27196 4.27196 0.79 0.00652778 0.00585374 0.404966 0.361867 72 20476 50 8.13932e+06 4.48013e+06 1.37338e+06 4238.83 7.42 2.18124 1.91119 37588 355536 -1 16153 20 7464 8416 998033 217072 4.14666 4.14666 -2311.78 -4.14666 0 0 1.72054e+06 5310.31 0.47 0.50 0.39 -1 -1 0.47 0.292601 0.260921 896 1312 475 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_27.v common 14.26 vpr 81.57 MiB 0.21 14520 -1 -1 1 0.45 -1 -1 38396 -1 -1 126 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83528 22 19 3871 3210 1 1982 175 18 18 324 mult_36 auto 44.4 MiB 1.24 11174 29515 6552 19982 2981 81.6 MiB 0.80 0.01 4.27196 -2274.04 -4.27196 4.27196 0.78 0.00630671 0.00561642 0.439461 0.393044 68 21260 31 8.13932e+06 4.99193e+06 1.31159e+06 4048.11 6.40 2.09377 1.83035 36620 334356 -1 17367 17 7795 9201 990857 222794 4.39726 4.39726 -2515.29 -4.39726 0 0 1.63345e+06 5041.52 0.42 0.49 0.30 -1 -1 0.42 0.282366 0.253531 944 1385 494 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_28.v common 13.93 vpr 81.64 MiB 0.14 14688 -1 -1 1 0.47 -1 -1 38576 -1 -1 128 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83604 22 19 3945 3267 1 2025 177 18 18 324 mult_36 auto 44.7 MiB 1.09 11734 34897 7640 23359 3898 81.6 MiB 0.90 0.01 4.27196 -2285.03 -4.27196 4.27196 0.77 0.00668871 0.00599553 0.483753 0.431257 72 22190 34 8.13932e+06 5.02088e+06 1.37338e+06 4238.83 5.98 2.12639 1.84804 37588 355536 -1 17870 17 7943 9223 1126928 247605 4.39726 4.39726 -2508.33 -4.39726 0 0 1.72054e+06 5310.31 0.45 0.56 0.30 -1 -1 0.45 0.304202 0.272596 962 1404 513 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_29.v common 18.58 vpr 82.79 MiB 0.19 14976 -1 -1 1 0.49 -1 -1 39616 -1 -1 135 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84780 22 19 4159 3447 1 2141 185 22 22 484 mult_36 auto 45.8 MiB 1.44 13174 35953 8427 24187 3339 82.8 MiB 1.04 0.02 4.22237 -2488.49 -4.22237 4.22237 1.18 0.00856951 0.00780558 0.564857 0.507552 72 25377 43 1.32347e+07 5.5182e+06 2.11301e+06 4365.72 8.73 2.57868 2.27583 56918 551676 -1 20346 15 8444 9848 1257155 262005 4.39726 4.39726 -2750.66 -4.39726 0 0 2.64603e+06 5467.00 0.75 0.46 0.50 -1 -1 0.75 0.2482 0.223951 1015 1491 532 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_30.v common 18.97 vpr 84.25 MiB 0.19 15232 -1 -1 1 0.52 -1 -1 40872 -1 -1 137 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86276 22 19 4233 3504 1 2181 187 22 22 484 mult_36 auto 46.4 MiB 1.32 13110 38635 8392 26373 3870 84.3 MiB 1.00 0.01 4.08302 -2563.57 -4.08302 4.08302 1.21 0.00716477 0.00630509 0.530592 0.472881 68 25874 37 1.32347e+07 5.54715e+06 2.01763e+06 4168.66 9.32 2.41307 2.11127 55470 518816 -1 20145 22 8858 10316 1212837 260181 4.14666 4.14666 -2787.95 -4.14666 0 0 2.51205e+06 5190.18 0.65 0.59 0.44 -1 -1 0.65 0.338688 0.299762 1034 1510 551 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_31.v common 18.06 vpr 85.23 MiB 0.23 15608 -1 -1 1 0.54 -1 -1 40796 -1 -1 143 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87276 22 19 4410 3647 1 2284 193 22 22 484 mult_36 auto 47.4 MiB 1.13 14030 46981 10944 31495 4542 85.2 MiB 1.28 0.02 4.39726 -2691.53 -4.39726 4.39726 1.26 0.00865791 0.00769648 0.685382 0.611844 76 25587 29 1.32347e+07 5.63401e+06 2.20457e+06 4554.90 8.03 2.41776 2.11977 57882 574062 -1 21637 17 8701 9904 1360390 269571 4.64786 4.64786 -2958.16 -4.64786 0 0 2.73077e+06 5642.09 0.76 0.63 0.37 -1 -1 0.76 0.339392 0.307222 1077 1578 570 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_32.v common 21.69 vpr 84.51 MiB 0.21 15728 -1 -1 1 0.55 -1 -1 40596 -1 -1 145 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86536 22 19 4484 3704 1 2331 195 22 22 484 mult_36 auto 47.4 MiB 1.32 14336 39180 9212 26344 3624 84.5 MiB 1.07 0.02 4.27196 -2750.64 -4.27196 4.27196 1.30 0.00779802 0.00686165 0.574051 0.513729 74 27846 43 1.32347e+07 5.66296e+06 2.15943e+06 4461.62 11.13 2.7468 2.41532 57402 562966 -1 21950 17 9362 10872 1422997 286951 4.52256 4.52256 -3005.56 -4.52256 0 0 2.68771e+06 5553.12 0.74 0.66 0.53 -1 -1 0.74 0.333597 0.299696 1096 1597 589 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_33.v common 22.52 vpr 86.98 MiB 0.26 16636 -1 -1 1 0.59 -1 -1 41576 -1 -1 157 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89064 22 19 4843 4029 1 2441 208 22 22 484 mult_36 auto 49.7 MiB 1.74 14676 47024 10400 32136 4488 87.0 MiB 1.30 0.02 4.39726 -2845.68 -4.39726 4.39726 1.30 0.00826196 0.00738647 0.697696 0.62331 78 24684 29 1.32347e+07 6.23266e+06 2.25108e+06 4650.99 10.99 3.39692 2.97879 58850 595650 -1 21723 14 8860 10340 1224784 254736 4.39726 4.39726 -3004.01 -4.39726 0 0 2.82299e+06 5832.63 0.74 0.56 0.53 -1 -1 0.74 0.31281 0.283115 1185 1756 608 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_34.v common 23.60 vpr 86.76 MiB 0.29 16752 -1 -1 1 0.62 -1 -1 41480 -1 -1 160 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88844 22 19 4917 4086 1 2486 211 22 22 484 mult_36 auto 50.2 MiB 1.67 14916 46609 10188 31704 4717 86.8 MiB 1.24 0.02 4.27196 -2997.24 -4.27196 4.27196 1.27 0.00858556 0.00770115 0.67088 0.597459 80 25429 32 1.32347e+07 6.27609e+06 2.29262e+06 4736.82 12.34 3.4883 3.04762 59334 607116 -1 22295 17 9208 10622 1372836 273552 4.27196 4.27196 -3123.26 -4.27196 0 0 2.87723e+06 5944.70 0.75 0.61 0.49 -1 -1 0.75 0.336562 0.300767 1205 1775 627 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_35.v common 20.24 vpr 87.50 MiB 0.25 17108 -1 -1 1 0.68 -1 -1 41776 -1 -1 163 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89604 22 19 5093 4228 1 2588 214 22 22 484 mult_36 auto 50.9 MiB 1.67 15536 45583 9917 31556 4110 87.5 MiB 1.27 0.02 4.27196 -3005.45 -4.27196 4.27196 1.31 0.00869664 0.00777674 0.669261 0.594241 76 28352 31 1.32347e+07 6.31951e+06 2.20457e+06 4554.90 9.25 2.8244 2.47362 57882 574062 -1 23607 17 9965 11831 1457758 304984 4.39726 4.39726 -3480.44 -4.39726 0 0 2.73077e+06 5642.09 0.74 0.67 0.43 -1 -1 0.74 0.353488 0.321039 1248 1842 646 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_36.v common 22.73 vpr 87.92 MiB 0.25 17160 -1 -1 1 0.67 -1 -1 41868 -1 -1 165 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90028 22 19 5167 4285 1 2632 216 22 22 484 mult_36 auto 51.4 MiB 1.63 15667 41624 8267 29885 3472 87.9 MiB 1.23 0.02 4.33362 -3152.9 -4.33362 4.33362 1.28 0.00850204 0.00759229 0.636531 0.565249 74 29785 34 1.32347e+07 6.34846e+06 2.15943e+06 4461.62 11.37 3.30946 2.8967 57402 562966 -1 24080 19 10244 12040 1518165 313102 4.52256 4.52256 -3590.71 -4.52256 0 0 2.68771e+06 5553.12 0.75 0.71 0.49 -1 -1 0.75 0.40039 0.357387 1267 1861 665 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_37.v common 23.77 vpr 89.23 MiB 0.26 17788 -1 -1 1 0.66 -1 -1 40800 -1 -1 173 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91368 22 19 5380 4464 1 2743 225 24 24 576 mult_36 auto 52.8 MiB 1.91 17323 51525 11897 34432 5196 89.2 MiB 1.39 0.02 4.28601 -3284.49 -4.28601 4.28601 1.54 0.00857551 0.00763061 0.733055 0.64925 74 30303 40 1.59675e+07 6.86027e+06 2.56259e+06 4448.94 10.91 3.19892 2.80024 67906 667765 -1 25244 18 10317 12089 1522453 322878 4.39726 4.39726 -3731.23 -4.39726 0 0 3.19068e+06 5539.38 0.95 0.75 0.60 -1 -1 0.95 0.40953 0.366886 1321 1947 684 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_38.v common 22.68 vpr 89.94 MiB 0.17 17808 -1 -1 1 0.71 -1 -1 42296 -1 -1 176 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92100 22 19 5454 4521 1 2787 228 24 24 576 mult_36 auto 52.9 MiB 2.02 17173 57996 13827 39781 4388 89.4 MiB 1.61 0.02 4.52256 -3242.13 -4.52256 4.52256 1.46 0.00925643 0.00828699 0.842234 0.748468 74 29865 34 1.59675e+07 6.90369e+06 2.56259e+06 4448.94 9.75 3.22568 2.83864 67906 667765 -1 25656 15 10421 12099 1547300 316808 4.64786 4.64786 -3606.77 -4.64786 0 0 3.19068e+06 5539.38 0.98 0.68 0.62 -1 -1 0.98 0.359616 0.32315 1340 1966 703 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_39.v common 25.20 vpr 90.11 MiB 0.21 18144 -1 -1 1 0.71 -1 -1 40084 -1 -1 180 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92272 22 19 5629 4662 1 2884 232 24 24 576 mult_36 auto 53.8 MiB 2.03 18624 55768 13035 37822 4911 90.1 MiB 1.61 0.02 4.39726 -3391.54 -4.39726 4.39726 1.50 0.0104887 0.00942536 0.862312 0.77126 76 33253 33 1.59675e+07 6.9616e+06 2.61600e+06 4541.67 11.98 3.38951 2.98079 68478 680951 -1 27050 17 10922 12570 1623278 339627 4.52256 4.52256 -3618.17 -4.52256 0 0 3.24203e+06 5628.53 0.93 0.73 0.59 -1 -1 0.93 0.390966 0.349857 1381 2032 722 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_40.v common 106.73 vpr 91.25 MiB 0.15 18340 -1 -1 1 0.75 -1 -1 42292 -1 -1 182 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93440 22 19 5703 4719 1 2932 234 24 24 576 mult_36 auto 54.2 MiB 2.06 17761 53514 12161 36873 4480 90.6 MiB 1.51 0.02 4.3337 -3472.19 -4.3337 4.3337 1.47 0.0105528 0.00951556 0.779612 0.694323 70 33764 46 1.59675e+07 6.99055e+06 2.45377e+06 4260.01 93.93 6.55011 5.67694 66754 640332 -1 27180 18 11294 13295 1660649 350009 4.39726 4.39726 -3935.92 -4.39726 0 0 3.09179e+06 5367.68 0.84 0.73 0.53 -1 -1 0.84 0.400462 0.355338 1400 2051 741 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_41.v common 28.65 vpr 92.59 MiB 0.22 18828 -1 -1 1 0.74 -1 -1 41616 -1 -1 190 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94816 22 19 5950 4932 1 3040 243 24 24 576 mult_36 auto 55.3 MiB 2.19 19478 54819 12176 38018 4625 91.5 MiB 1.41 0.02 4.41131 -3650.22 -4.41131 4.41131 1.44 0.00941679 0.00837831 0.711187 0.628289 80 31276 23 1.59675e+07 7.50235e+06 2.72095e+06 4723.87 15.35 3.98026 3.46891 70206 720185 -1 27478 16 10740 12213 1485213 299160 4.52256 4.52256 -3708.57 -4.52256 0 0 3.41546e+06 5929.62 0.96 0.70 0.62 -1 -1 0.96 0.397874 0.356582 1461 2153 760 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_42.v common 24.36 vpr 92.43 MiB 0.21 19056 -1 -1 1 0.62 -1 -1 42764 -1 -1 193 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94644 22 19 6024 4989 1 3083 246 24 24 576 mult_36 auto 56.0 MiB 2.07 19232 63386 14561 42862 5963 92.0 MiB 1.77 0.02 4.64786 -3641.46 -4.64786 4.64786 1.43 0.0112474 0.010131 0.930823 0.832762 76 33762 25 1.59675e+07 7.54578e+06 2.61600e+06 4541.67 10.82 3.38503 2.97948 68478 680951 -1 28522 16 11374 13382 1767274 362795 4.77316 4.77316 -3938.14 -4.77316 0 0 3.24203e+06 5628.53 0.92 0.78 0.55 -1 -1 0.92 0.417719 0.37574 1480 2172 779 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_43.v common 35.71 vpr 93.63 MiB 0.30 19448 -1 -1 1 0.89 -1 -1 43352 -1 -1 199 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 95880 22 19 6198 5129 1 3182 252 24 24 576 mult_36 auto 56.7 MiB 2.19 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100084 22 19 6735 5564 1 3478 270 24 24 576 mult_36 auto 59.6 MiB 2.33 22209 70030 15451 47782 6797 95.9 MiB 2.09 0.02 4.41516 -4128.21 -4.41516 4.41516 1.47 0.0129228 0.0116882 1.09035 0.970827 84 37671 32 1.59675e+07 8.27472e+06 2.84938e+06 4946.85 19.62 5.16013 4.52241 71930 760447 -1 31070 17 12543 14162 1836210 367421 4.52256 4.52256 -4366.36 -4.52256 0 0 3.60864e+06 6265.01 1.06 0.86 0.55 -1 -1 1.06 0.485985 0.435523 1656 2428 874 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_48.v common 33.45 vpr 97.87 MiB 0.32 20468 -1 -1 1 0.97 -1 -1 44052 -1 -1 218 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100220 22 19 6809 5621 1 3528 272 24 24 576 mult_36 auto 60.2 MiB 2.27 22399 68109 15563 46856 5690 96.2 MiB 1.89 0.02 4.28601 -4165.16 -4.28601 4.28601 1.51 0.0106728 0.00949716 0.930706 0.824444 84 37990 31 1.59675e+07 8.30367e+06 2.84938e+06 4946.85 18.68 4.78227 4.17358 71930 760447 -1 31425 16 12475 14355 1676213 339117 4.64786 4.64786 -4427.09 -4.64786 0 0 3.60864e+06 6265.01 1.05 0.83 0.62 -1 -1 1.05 0.476709 0.428619 1674 2447 893 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_49.v common 30.74 vpr 104.11 MiB 0.26 21080 -1 -1 1 1.14 -1 -1 44408 -1 -1 228 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 106608 22 19 7094 5872 1 3643 283 24 24 576 mult_36 auto 61.6 MiB 2.42 22044 72667 16155 50381 6131 97.9 MiB 2.20 0.03 4.16456 -4302.53 -4.16456 4.16456 1.47 0.0132913 0.0117975 1.12979 0.99479 78 36952 26 1.59675e+07 8.84444e+06 2.67122e+06 4637.53 15.11 5.14497 4.49556 69630 706637 -1 31678 15 13251 15339 1784571 373556 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1 1.11 -1 -1 44760 -1 -1 235 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 106064 22 19 7344 6071 1 3784 290 24 24 576 mult_36 auto 62.9 MiB 2.61 23160 75092 17160 51061 6871 99.0 MiB 2.23 0.03 4.28601 -4423.35 -4.28601 4.28601 1.55 0.0133859 0.0120886 1.16131 1.03723 80 39279 28 1.59675e+07 8.94577e+06 2.72095e+06 4723.87 20.13 5.30123 4.63659 70206 720185 -1 33312 15 13811 15847 1871805 392568 4.52256 4.52256 -4830.06 -4.52256 0 0 3.41546e+06 5929.62 1.07 0.89 0.58 -1 -1 1.07 0.477973 0.430588 1808 2655 950 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_52.v common 33.54 vpr 106.84 MiB 0.21 21728 -1 -1 1 0.94 -1 -1 45300 -1 -1 237 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 109400 22 19 7418 6128 1 3829 292 24 24 576 mult_36 auto 63.4 MiB 2.53 24388 75796 17173 51253 7370 99.4 MiB 1.97 0.02 4.39726 -4541.6 -4.39726 4.39726 1.42 0.0121864 0.0108831 0.960739 0.84753 82 40166 40 1.59675e+07 8.97472e+06 2.78508e+06 4835.20 18.23 5.40215 4.7012 70778 734779 -1 34142 16 13821 15840 1861707 392582 4.52256 4.52256 -4916.53 -4.52256 0 0 3.48632e+06 6052.64 0.92 0.89 0.59 -1 -1 0.92 0.502002 0.449718 1827 2674 969 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_14.v common 9.57 vpr 67.63 MiB 0.09 9420 -1 -1 1 0.13 -1 -1 34724 -1 -1 43 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69256 22 19 1246 925 1 719 88 16 16 256 mult_36 auto 29.9 MiB 1.06 3708 12178 3140 7111 1927 67.6 MiB 0.29 0.00 7.85627 -369.053 -7.85627 7.85627 0.56 0.00247974 0.00227123 0.164562 0.151153 56 7704 42 6.59459e+06 2.20645e+06 849745. 3319.32 4.60 0.792333 0.701862 26364 208198 -1 6616 32 8380 9269 1473487 377056 8.18784 8.18784 -442.129 -8.18784 0 0 1.04740e+06 4091.43 0.25 0.51 0.24 -1 -1 0.25 0.174145 0.155285 299 344 247 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_15.v common 8.47 vpr 68.37 MiB 0.10 9592 -1 -1 1 0.16 -1 -1 35180 -1 -1 46 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70012 22 19 1344 989 1 778 92 16 16 256 mult_36 auto 30.5 MiB 0.89 4253 11891 2718 7916 1257 68.4 MiB 0.29 0.00 8.06786 -397.609 -8.06786 8.06786 0.58 0.00265339 0.00243857 0.163296 0.149912 54 9006 35 6.59459e+06 2.64588e+06 829453. 3240.05 3.79 0.796672 0.706837 26108 202796 -1 7077 27 6857 7815 969928 231501 8.88753 8.88753 -500.255 -8.88753 0 0 1.02522e+06 4004.78 0.24 0.35 0.17 -1 -1 0.24 0.148959 0.132915 321 369 266 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_16.v common 9.84 vpr 68.77 MiB 0.11 9752 -1 -1 1 0.17 -1 -1 35168 -1 -1 48 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70424 22 19 1418 1046 1 822 94 16 16 256 mult_36 auto 30.9 MiB 1.08 4528 13087 3331 8118 1638 68.8 MiB 0.34 0.01 7.80064 -415.87 -7.80064 7.80064 0.58 0.00301012 0.00277729 0.190385 0.174644 60 8307 44 6.59459e+06 2.67484e+06 890343. 3477.90 4.96 0.900933 0.799135 27128 224764 -1 7269 23 7299 8032 994162 223606 8.50533 8.50533 -467.681 -8.50533 0 0 1.11577e+06 4358.47 0.27 0.34 0.18 -1 -1 0.27 0.136378 0.121633 340 388 285 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_17.v common 10.49 vpr 69.04 MiB 0.11 10164 -1 -1 1 0.18 -1 -1 35384 -1 -1 52 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70692 22 19 1518 1112 1 879 98 16 16 256 mult_36 auto 31.3 MiB 1.02 4723 16523 4141 9979 2403 69.0 MiB 0.48 0.01 8.49449 -420.557 -8.49449 8.49449 0.66 0.00306434 0.00276878 0.261531 0.239561 56 9780 47 6.59459e+06 2.73274e+06 849745. 3319.32 5.12 1.05673 0.940382 26364 208198 -1 8101 27 9367 10451 1358860 310210 9.29868 9.29868 -518.713 -9.29868 0 0 1.04740e+06 4091.43 0.25 0.45 0.19 -1 -1 0.25 0.168453 0.150261 365 415 304 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_18.v common 11.55 vpr 69.42 MiB 0.08 10380 -1 -1 1 0.19 -1 -1 34960 -1 -1 55 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71088 22 19 1592 1169 1 918 101 16 16 256 mult_36 auto 31.5 MiB 1.29 5255 15846 3816 10145 1885 69.4 MiB 0.43 0.01 8.73075 -474.97 -8.73075 8.73075 0.54 0.00363037 0.00333098 0.234126 0.214278 58 9951 50 6.59459e+06 2.77617e+06 871168. 3403.00 6.13 1.0597 0.940004 26872 219187 -1 8328 26 8188 9162 1100395 244875 8.96668 8.96668 -544.981 -8.96668 0 0 1.09288e+06 4269.05 0.31 0.41 0.20 -1 -1 0.31 0.174447 0.155683 383 434 323 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_19.v common 11.58 vpr 69.89 MiB 0.05 10540 -1 -1 1 0.22 -1 -1 35332 -1 -1 58 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71564 22 19 1688 1231 1 975 105 16 16 256 mult_36 auto 32.2 MiB 1.26 5522 18136 4926 9933 3277 69.9 MiB 0.33 0.00 8.61576 -458.576 -8.61576 8.61576 0.58 0.00158923 0.00144049 0.173046 0.158003 58 11561 41 6.59459e+06 3.21559e+06 871168. 3403.00 6.32 1.01078 0.895587 26872 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10.09 vpr 70.92 MiB 0.13 11064 -1 -1 1 0.22 -1 -1 35788 -1 -1 62 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72620 22 19 1859 1351 1 1072 109 16 16 256 mult_36 auto 33.2 MiB 1.38 6071 17789 4553 10762 2474 70.9 MiB 0.47 0.01 8.64699 -503.256 -8.64699 8.64699 0.57 0.00350866 0.00321066 0.255118 0.233082 70 10334 32 6.59459e+06 3.2735e+06 1.02522e+06 4004.78 4.12 1.1358 1.00634 28912 262511 -1 9048 24 8163 9276 1068033 251456 8.68598 8.68598 -630.827 -8.68598 0 0 1.29210e+06 5047.26 0.33 0.45 0.26 -1 -1 0.33 0.190795 0.170811 445 500 380 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_22.v common 11.76 vpr 71.06 MiB 0.14 11192 -1 -1 1 0.23 -1 -1 35848 -1 -1 66 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72768 22 19 1933 1408 1 1112 113 16 16 256 mult_36 auto 33.5 MiB 1.56 6284 16766 3772 10688 2306 71.1 MiB 0.44 0.01 8.66433 -531.367 -8.66433 8.66433 0.57 0.00358871 0.00327439 0.235653 0.214767 64 12202 40 6.59459e+06 3.3314e+06 943753. 3686.54 5.63 1.18362 1.04832 27892 240595 -1 9937 26 8773 9855 1261410 275837 8.85048 8.85048 -653.969 -8.85048 0 0 1.19033e+06 4649.74 0.29 0.49 0.23 -1 -1 0.29 0.220799 0.198239 464 519 399 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_23.v common 13.12 vpr 71.43 MiB 0.14 11392 -1 -1 1 0.24 -1 -1 36044 -1 -1 68 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73144 22 19 2031 1472 1 1172 116 18 18 324 mult_36 auto 34.0 MiB 1.74 6825 18164 4253 11642 2269 71.4 MiB 0.49 0.01 8.63545 -565.294 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75180 22 19 2385 1724 1 1377 131 18 18 324 mult_36 auto 36.2 MiB 1.78 8472 26027 6274 16532 3221 73.4 MiB 0.69 0.01 8.72365 -592.733 -8.72365 8.72365 0.75 0.00437438 0.00398433 0.368738 0.33545 58 17784 50 8.13932e+06 4.35501e+06 1.14310e+06 3528.09 11.45 1.60024 1.4182 34680 290288 -1 14148 29 14549 16458 2410411 525176 9.27518 9.27518 -913.009 -9.27518 0 0 1.43297e+06 4422.75 0.35 0.73 0.25 -1 -1 0.35 0.258717 0.230231 575 642 494 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_28.v common 13.73 vpr 73.90 MiB 0.18 12284 -1 -1 1 0.33 -1 -1 36780 -1 -1 83 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75676 22 19 2459 1781 1 1418 132 18 18 324 mult_36 auto 36.6 MiB 2.05 8415 20232 4376 13738 2118 73.9 MiB 0.55 0.01 8.74245 -615.172 -8.74245 8.74245 0.76 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v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77420 22 19 2744 1981 1 1589 143 22 22 484 mult_36 auto 38.3 MiB 2.25 10398 27745 6556 18229 2960 75.6 MiB 0.79 0.01 8.84777 -733.653 -8.84777 8.84777 1.21 0.0050278 0.00457911 0.39794 0.361066 60 21030 47 1.32347e+07 4.91023e+06 1.79840e+06 3715.71 62.39 3.13351 2.7603 53054 462096 -1 16299 28 16051 18584 2592891 539995 9.38798 9.38798 -984.877 -9.38798 0 0 2.25108e+06 4650.99 0.59 0.83 0.38 -1 -1 0.59 0.297336 0.264934 665 745 570 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_32.v common 18.89 vpr 75.58 MiB 0.14 12912 -1 -1 1 0.34 -1 -1 36856 -1 -1 96 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77392 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79456 22 19 3175 2293 1 1835 158 22 22 484 mult_36 auto 40.4 MiB 3.51 11333 30475 6946 20367 3162 77.6 MiB 0.87 0.01 9.75629 -817.637 -9.75629 9.75629 1.21 0.00575594 0.00522535 0.444008 0.402507 66 21761 48 1.32347e+07 5.50888e+06 1.96511e+06 4060.15 57.53 4.0587 3.55958 54986 507526 -1 17539 27 16171 18953 2330366 501744 9.95932 9.95932 -1222.31 -9.95932 0 0 2.45963e+06 5081.88 0.66 0.86 0.43 -1 -1 0.66 0.347439 0.310801 773 865 665 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_37.v common 26.60 vpr 78.42 MiB 0.24 14392 -1 -1 1 0.43 -1 -1 37452 -1 -1 111 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80304 22 19 3280 2364 1 1905 163 24 24 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fir_nopipe_45.v common 26.06 vpr 81.98 MiB 0.25 15932 -1 -1 1 0.55 -1 -1 40488 -1 -1 135 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83944 22 19 3989 2869 1 2317 189 24 24 576 mult_36 auto 45.0 MiB 4.61 14618 41381 9719 27735 3927 82.0 MiB 1.20 0.02 9.77027 -1011.74 -9.77027 9.77027 1.47 0.00736802 0.00668993 0.588856 0.531874 72 25523 37 1.59675e+07 7.1022e+06 2.50747e+06 4353.24 11.47 2.51799 2.2285 67330 654343 -1 21225 23 16401 19162 2396371 518493 9.82682 9.82682 -1397.87 -9.82682 0 0 3.14081e+06 5452.80 0.91 0.90 0.55 -1 -1 0.91 0.37998 0.340237 975 1094 836 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_46.v common 29.93 vpr 82.05 MiB 0.14 16060 -1 -1 1 0.54 -1 -1 40688 -1 -1 136 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84020 22 19 4063 2926 1 2354 190 24 24 576 mult_36 auto 44.9 MiB 4.94 16350 37864 7792 26746 3326 82.1 MiB 1.14 0.02 9.83665 -1114.77 -9.83665 9.83665 1.50 0.00740843 0.00663842 0.54478 0.488634 82 25929 47 1.59675e+07 7.11667e+06 2.78508e+06 4835.20 15.04 3.2069 2.82375 70778 734779 -1 22200 23 15637 18321 2342525 476667 9.76082 9.76082 -1542.32 -9.76082 0 0 3.48632e+06 6052.64 0.98 0.78 0.64 -1 -1 0.98 0.322008 0.287989 993 1113 855 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_47.v common 25.24 vpr 82.53 MiB 0.26 16636 -1 -1 1 0.53 -1 -1 40820 -1 -1 141 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84508 22 19 4167 2996 1 2420 195 24 24 576 mult_36 auto 45.3 MiB 4.57 16260 49350 11375 33104 4871 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83.79 MiB 0.16 17144 -1 -1 1 0.67 -1 -1 41040 -1 -1 148 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85796 22 19 4420 3181 1 2563 203 24 24 576 mult_36 auto 47.2 MiB 5.26 17398 44307 10226 29911 4170 83.8 MiB 1.37 0.02 9.9037 -1079.02 -9.9037 9.9037 1.52 0.00831944 0.00739092 0.668411 0.598925 74 29993 39 1.59675e+07 7.68637e+06 2.56259e+06 4448.94 13.19 2.72523 2.40927 67906 667765 -1 25064 27 22957 25885 3706669 745505 9.89712 9.89712 -1512.67 -9.89712 0 0 3.19068e+06 5539.38 0.92 1.25 0.54 -1 -1 0.92 0.468746 0.417267 1082 1214 931 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_51.v common 29.07 vpr 84.34 MiB 0.27 17280 -1 -1 1 0.73 -1 -1 41072 -1 -1 152 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86360 22 19 4524 3251 1 2633 207 24 24 576 mult_36 auto 47.4 MiB 5.06 17274 43047 9353 29279 4415 84.3 MiB 1.13 0.02 9.72425 -1170.65 -9.72425 9.72425 1.50 0.00836409 0.00742991 0.5227 0.466561 76 29407 46 1.59675e+07 7.74428e+06 2.61600e+06 4541.67 13.39 2.72234 2.40206 68478 680951 -1 24555 25 19224 22166 3043731 614947 10.2548 10.2548 -1642.4 -10.2548 0 0 3.24203e+06 5628.53 0.89 1.10 0.55 -1 -1 0.89 0.452964 0.405044 1107 1245 950 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_52.v common 28.26 vpr 84.80 MiB 0.30 17348 -1 -1 1 0.67 -1 -1 39500 -1 -1 155 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86832 22 19 4598 3308 1 2667 210 24 24 576 mult_36 auto 48.0 MiB 5.62 17604 46386 10173 32285 3928 84.8 MiB 1.48 0.02 9.68009 -1080.95 -9.68009 9.68009 1.59 0.00915384 0.0082116 0.70414 0.632133 72 30917 38 1.59675e+07 7.7877e+06 2.50747e+06 4353.24 11.45 2.81989 2.49644 67330 654343 -1 25360 25 21418 25117 3240485 694413 10.206 10.206 -1662.84 -10.206 0 0 3.14081e+06 5452.80 0.89 1.15 0.56 -1 -1 0.89 0.452531 0.404064 1127 1264 969 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_14.v common 9.62 vpr 71.29 MiB 0.11 10476 -1 -1 1 0.25 -1 -1 35508 -1 -1 65 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73000 22 19 1974 1653 1 1013 110 16 16 256 mult_36 auto 33.6 MiB 0.45 5297 17205 4342 10377 2486 71.3 MiB 0.42 0.01 4.14666 -1129.87 -4.14666 4.14666 0.58 0.00339471 0.00305405 0.248201 0.223626 56 11347 43 6.62819e+06 2.54052e+06 849745. 3319.32 4.90 1.11777 0.974098 26364 208198 -1 9317 19 4256 4818 612410 141530 4.39726 4.39726 -1244.22 -4.39726 0 0 1.04740e+06 4091.43 0.25 0.29 0.18 -1 -1 0.25 0.154654 0.137773 481 708 247 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_15.v common 9.84 vpr 72.22 MiB 0.08 10828 -1 -1 1 0.28 -1 -1 36908 -1 -1 72 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73952 22 19 2144 1789 1 1107 118 16 16 256 mult_36 auto 34.4 MiB 0.65 5790 18036 4123 11366 2547 72.2 MiB 0.41 0.00 4.11968 -1267.13 -4.11968 4.11968 0.60 0.00166501 0.00149431 0.220697 0.197374 58 11809 27 6.62819e+06 3.03953e+06 871168. 3403.00 4.87 1.10123 0.960951 26872 219187 -1 9868 19 4677 5264 620916 144337 4.14666 4.14666 -1356.44 -4.14666 0 0 1.09288e+06 4269.05 0.26 0.31 0.20 -1 -1 0.26 0.181583 0.162619 521 769 266 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_16.v common 32.82 vpr 72.61 MiB 0.09 10936 -1 -1 1 0.29 -1 -1 37020 -1 -1 74 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74348 22 19 2218 1846 1 1153 120 16 16 256 mult_36 auto 34.8 MiB 0.65 5931 16640 3652 10868 2120 72.6 MiB 0.41 0.01 4.14666 -1288.47 -4.14666 4.14666 0.57 0.00377805 0.00339693 0.234481 0.211024 60 12726 33 6.62819e+06 3.06896e+06 890343. 3477.90 27.70 2.238 1.94709 27128 224764 -1 10016 27 4853 5474 1043418 337630 4.27196 4.27196 -1404.7 -4.27196 0 0 1.11577e+06 4358.47 0.27 0.46 0.19 -1 -1 0.27 0.218022 0.192869 540 788 285 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_17.v common 30.59 vpr 74.12 MiB 0.14 11752 -1 -1 1 0.27 -1 -1 36588 -1 -1 83 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 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-k6_frac_2uripple_N8_22nm.xml fir_pipe_20.v common 12.79 vpr 75.91 MiB 0.15 12328 -1 -1 1 0.31 -1 -1 37000 -1 -1 93 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77736 22 19 2852 2378 1 1440 140 16 16 256 mult_36 auto 38.6 MiB 0.79 8294 22646 5123 14901 2622 75.9 MiB 0.60 0.01 4.2084 -1649.58 -4.2084 4.2084 0.59 0.00519432 0.00459622 0.330436 0.295579 68 16097 38 6.62819e+06 3.74456e+06 1.00038e+06 3907.74 6.65 1.6338 1.43308 28404 252462 -1 12428 32 5526 6490 1025857 306320 4.39726 4.39726 -1796.73 -4.39726 0 0 1.24648e+06 4869.04 0.32 0.59 0.24 -1 -1 0.32 0.329705 0.29122 695 1021 361 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_21.v common 11.23 vpr 76.87 MiB 0.13 12808 -1 -1 1 0.34 -1 -1 37736 -1 -1 97 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78712 22 19 3057 2549 1 1542 144 16 16 256 mult_36 auto 39.6 MiB 0.88 8673 23895 5161 15228 3506 76.9 MiB 0.64 0.01 4.52256 -1743.09 -4.52256 4.52256 0.59 0.00509947 0.00455544 0.355011 0.31784 74 15361 35 6.62819e+06 3.80343e+06 1.07073e+06 4182.55 5.08 1.69428 1.48117 29424 273870 -1 12772 16 5516 6283 721984 162116 4.39726 4.39726 -1867.34 -4.39726 0 0 1.33358e+06 5209.30 0.37 0.37 0.23 -1 -1 0.37 0.219266 0.196635 742 1099 380 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_22.v common 11.01 vpr 77.04 MiB 0.14 13056 -1 -1 1 0.35 -1 -1 38004 -1 -1 100 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78884 22 19 3131 2606 1 1585 147 16 16 256 mult_36 auto 39.8 MiB 0.80 8566 16401 3002 11439 1960 77.0 MiB 0.46 0.01 4.20292 -1804.73 -4.20292 4.20292 0.58 0.00505943 0.00451654 0.250613 0.224921 70 15569 27 6.62819e+06 3.84757e+06 1.02522e+06 4004.78 5.00 1.57019 1.37496 28912 262511 -1 12915 18 5834 6628 735961 170375 4.27196 4.27196 -1954.66 -4.27196 0 0 1.29210e+06 5047.26 0.31 0.39 0.23 -1 -1 0.31 0.237635 0.212022 762 1118 399 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_23.v common 12.69 vpr 78.08 MiB 0.23 13264 -1 -1 1 0.36 -1 -1 37940 -1 -1 107 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79956 22 19 3301 2742 1 1683 155 18 18 324 mult_36 auto 40.7 MiB 0.77 9538 29691 6508 19815 3368 78.1 MiB 0.78 0.01 4.16456 -1929.44 -4.16456 4.16456 0.77 0.00543034 0.00486181 0.427346 0.382197 74 17207 25 8.18539e+06 4.34658e+06 1.40368e+06 4332.34 5.68 1.81502 1.59881 37912 362744 -1 14522 15 6182 7157 877389 187757 4.39726 4.39726 -2097.58 -4.39726 0 0 1.74764e+06 5393.95 0.44 0.39 0.32 -1 -1 0.44 0.220923 0.197744 802 1179 418 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_24.v common 14.98 vpr 78.37 MiB 0.16 13344 -1 -1 1 0.39 -1 -1 38272 -1 -1 109 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80252 22 19 3375 2799 1 1730 157 18 18 324 mult_36 auto 41.1 MiB 0.72 9993 25960 5685 17809 2466 78.4 MiB 0.69 0.01 4.14666 -1987.87 -4.14666 4.14666 0.78 0.00654875 0.00596535 0.380892 0.340812 66 20196 47 8.18539e+06 4.37601e+06 1.27759e+06 3943.17 8.17 2.00995 1.75922 36296 327148 -1 15425 16 6577 7667 933401 201564 4.27196 4.27196 -2140.03 -4.27196 0 0 1.59950e+06 4936.74 0.40 0.40 0.29 -1 -1 0.40 0.219115 0.195599 821 1198 437 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_25.v common 15.04 vpr 79.46 MiB 0.12 13996 -1 -1 1 0.41 -1 -1 38108 -1 -1 116 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81364 22 19 3615 3005 1 1835 164 18 18 324 mult_36 auto 42.2 MiB 0.80 11154 29284 6310 19654 3320 79.5 MiB 0.80 0.01 4.14666 -2148.01 -4.14666 4.14666 0.79 0.00586019 0.00523374 0.423027 0.375862 74 20993 41 8.18539e+06 4.47902e+06 1.40368e+06 4332.34 7.70 2.07686 1.81166 37912 362744 -1 16756 18 7134 8004 1128968 235536 4.39726 4.39726 -2385.21 -4.39726 0 0 1.74764e+06 5393.95 0.46 0.53 0.37 -1 -1 0.46 0.278899 0.249426 877 1293 456 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_26.v common 13.31 vpr 79.98 MiB 0.19 14172 -1 -1 1 0.42 -1 -1 38464 -1 -1 118 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81896 22 19 3689 3062 1 1872 166 18 18 324 mult_36 auto 42.9 MiB 0.73 10890 31630 7268 20957 3405 80.0 MiB 0.87 0.01 4.27196 -2181.76 -4.27196 4.27196 0.76 0.00606494 0.00540887 0.467527 0.418559 70 19335 31 8.18539e+06 4.50845e+06 1.34436e+06 4149.26 5.95 2.19285 1.93908 37264 347768 -1 16326 14 6732 7802 873866 193746 4.64786 4.64786 -2351.91 -4.64786 0 0 1.69344e+06 5226.66 0.44 0.45 0.31 -1 -1 0.44 0.250603 0.228761 896 1312 475 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_27.v common 14.41 vpr 80.97 MiB 0.24 14340 -1 -1 1 0.46 -1 -1 38332 -1 -1 126 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82916 22 19 3871 3210 1 1979 175 18 18 324 mult_36 auto 43.9 MiB 0.98 11935 36361 8458 24158 3745 81.0 MiB 0.94 0.01 4.27196 -2285.74 -4.27196 4.27196 0.75 0.00613784 0.00547274 0.503502 0.449047 74 21341 43 8.18539e+06 5.02217e+06 1.40368e+06 4332.34 6.40 2.23969 1.95842 37912 362744 -1 17442 28 7329 8264 1322461 328195 4.39726 4.39726 -2440.95 -4.39726 0 0 1.74764e+06 5393.95 0.44 0.76 0.34 -1 -1 0.44 0.424379 0.377177 944 1385 494 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_28.v common 14.60 vpr 81.27 MiB 0.18 14592 -1 -1 1 0.47 -1 -1 38396 -1 -1 128 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83216 22 19 3945 3267 1 2024 177 18 18 324 mult_36 auto 44.3 MiB 0.90 12138 33905 7358 22743 3804 81.3 MiB 0.87 0.01 4.2084 -2321.46 -4.2084 4.2084 0.75 0.00632408 0.00564454 0.466734 0.414007 70 21577 28 8.18539e+06 5.0516e+06 1.34436e+06 4149.26 7.04 2.21927 1.94826 37264 347768 -1 17740 16 7557 8666 1010701 226948 4.39726 4.39726 -2498.89 -4.39726 0 0 1.69344e+06 5226.66 0.44 0.51 0.32 -1 -1 0.44 0.287858 0.262005 962 1404 513 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_29.v common 17.47 vpr 82.56 MiB 0.20 14908 -1 -1 1 0.53 -1 -1 39728 -1 -1 135 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84544 22 19 4159 3447 1 2140 185 22 22 484 mult_36 auto 45.6 MiB 0.82 12922 36479 8016 24715 3748 82.6 MiB 0.96 0.01 4.27196 -2537.11 -4.27196 4.27196 1.19 0.00683899 0.00611129 0.513952 0.458181 72 24568 26 1.33067e+07 5.5506e+06 2.11301e+06 4365.72 7.99 2.21268 1.9378 56918 551676 -1 19622 18 7762 9120 1147231 234160 4.52256 4.52256 -2684.21 -4.52256 0 0 2.64603e+06 5467.00 0.81 0.59 0.50 -1 -1 0.81 0.327241 0.293336 1015 1491 532 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_30.v common 17.71 vpr 82.84 MiB 0.22 15256 -1 -1 1 0.50 -1 -1 40852 -1 -1 137 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84824 22 19 4233 3504 1 2179 187 22 22 484 mult_36 auto 45.8 MiB 1.00 12963 38101 8862 25522 3717 82.8 MiB 1.03 0.01 4.16456 -2491.22 -4.16456 4.16456 1.21 0.00728231 0.00641715 0.549748 0.485614 68 24170 26 1.33067e+07 5.58003e+06 2.01763e+06 4168.66 8.33 2.19929 1.91941 55470 518816 -1 19865 19 8475 9594 1119874 244580 4.27196 4.27196 -2605.99 -4.27196 0 0 2.51205e+06 5190.18 0.79 0.62 0.32 -1 -1 0.79 0.347772 0.311818 1034 1510 551 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_31.v common 19.21 vpr 84.78 MiB 0.19 15500 -1 -1 1 0.53 -1 -1 40888 -1 -1 143 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86816 22 19 4410 3647 1 2283 193 22 22 484 mult_36 auto 46.6 MiB 1.09 13261 42525 9859 28389 4277 84.8 MiB 1.12 0.01 4.20292 -2606.72 -4.20292 4.20292 1.23 0.00792387 0.00715548 0.607786 0.542467 68 26796 45 1.33067e+07 5.66832e+06 2.01763e+06 4168.66 9.59 2.60643 2.28092 55470 518816 -1 20620 18 9122 10596 1262791 274069 4.27196 4.27196 -2850.79 -4.27196 0 0 2.51205e+06 5190.18 0.66 0.58 0.41 -1 -1 0.66 0.313357 0.279844 1077 1578 570 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_32.v common 17.78 vpr 83.86 MiB 0.24 15564 -1 -1 1 0.65 -1 -1 40628 -1 -1 145 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85876 22 19 4484 3704 1 2328 195 22 22 484 mult_36 auto 46.7 MiB 1.10 14086 42570 10140 28365 4065 83.9 MiB 1.19 0.01 4.27196 -2656.53 -4.27196 4.27196 1.26 0.0074867 0.00669018 0.632666 0.566104 76 25174 22 1.33067e+07 5.69776e+06 2.20457e+06 4554.90 7.48 2.3411 2.05657 57882 574062 -1 21201 17 8736 10203 1208112 256654 4.52256 4.52256 -2899.81 -4.52256 0 0 2.73077e+06 5642.09 0.76 0.56 0.47 -1 -1 0.76 0.308971 0.276204 1096 1597 589 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_33.v common 19.59 vpr 86.55 MiB 0.18 16668 -1 -1 1 0.72 -1 -1 41584 -1 -1 157 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88624 22 19 4843 4029 1 2439 208 22 22 484 mult_36 auto 48.9 MiB 0.97 14930 47640 11114 32188 4338 86.5 MiB 1.36 0.02 4.39726 -2986.1 -4.39726 4.39726 1.21 0.00807193 0.00721129 0.720009 0.641175 72 28519 46 1.33067e+07 6.27034e+06 2.11301e+06 4365.72 9.31 2.92459 2.56125 56918 551676 -1 22603 18 8941 10278 1322426 274519 4.52256 4.52256 -3196.98 -4.52256 0 0 2.64603e+06 5467.00 0.69 0.62 0.44 -1 -1 0.69 0.344955 0.307973 1185 1756 608 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_34.v common 19.92 vpr 86.19 MiB 0.21 16844 -1 -1 1 0.66 -1 -1 41520 -1 -1 160 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88260 22 19 4917 4086 1 2483 211 22 22 484 mult_36 auto 49.5 MiB 1.07 15547 44101 10019 30168 3914 86.2 MiB 1.19 0.02 4.52256 -2910.9 -4.52256 4.52256 1.29 0.00850993 0.00765958 0.628457 0.56061 72 28972 45 1.33067e+07 6.31449e+06 2.11301e+06 4365.72 9.40 3.01041 2.65124 56918 551676 -1 23425 15 9029 10536 1317654 275619 4.77316 4.77316 -3227.02 -4.77316 0 0 2.64603e+06 5467.00 0.72 0.59 0.48 -1 -1 0.72 0.310447 0.278067 1205 1775 627 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_35.v common 19.61 vpr 86.97 MiB 0.19 17008 -1 -1 1 0.61 -1 -1 41780 -1 -1 163 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89056 22 19 5093 4228 1 2586 214 22 22 484 mult_36 auto 50.4 MiB 1.15 14368 50056 10737 34290 5029 87.0 MiB 1.36 0.02 4.0831 -3007.04 -4.0831 4.0831 1.30 0.00833478 0.00743564 0.68954 0.611847 70 26841 32 1.33067e+07 6.35863e+06 2.06816e+06 4273.05 8.76 2.96404 2.60102 56434 539830 -1 22266 17 9508 10903 1285918 285062 4.27196 4.27196 -3253.37 -4.27196 0 0 2.60483e+06 5381.88 0.75 0.66 0.47 -1 -1 0.75 0.377564 0.341646 1248 1842 646 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_36.v common 28.12 vpr 87.36 MiB 0.27 17256 -1 -1 1 0.66 -1 -1 42020 -1 -1 165 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89452 22 19 5167 4285 1 2630 216 22 22 484 mult_36 auto 50.8 MiB 1.17 17033 50682 11615 34548 4519 87.4 MiB 1.48 0.02 4.41516 -3107.93 -4.41516 4.41516 1.32 0.0095028 0.00838872 0.767027 0.68235 78 30105 32 1.33067e+07 6.38806e+06 2.25108e+06 4650.99 16.67 3.91497 3.43174 58850 595650 -1 24920 16 9692 11251 1483545 305489 4.52256 4.52256 -3425.17 -4.52256 0 0 2.82299e+06 5832.63 0.79 0.67 0.52 -1 -1 0.79 0.358575 0.322125 1267 1861 665 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_37.v common 22.25 vpr 88.59 MiB 0.24 17688 -1 -1 1 0.71 -1 -1 40812 -1 -1 173 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90716 22 19 5380 4464 1 2739 225 24 24 576 mult_36 auto 52.1 MiB 1.21 16600 56313 12680 38864 4769 88.6 MiB 1.57 0.02 4.39726 -3260.8 -4.39726 4.39726 1.56 0.00877338 0.00782934 0.818708 0.726201 70 30941 28 1.60519e+07 6.90179e+06 2.45377e+06 4260.01 9.63 2.98262 2.61057 66754 640332 -1 25189 16 10124 11953 1441066 304403 4.52256 4.52256 -3510.18 -4.52256 0 0 3.09179e+06 5367.68 0.86 0.69 0.63 -1 -1 0.86 0.381342 0.340062 1321 1947 684 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_38.v common 23.40 vpr 90.68 MiB 0.27 17864 -1 -1 1 0.70 -1 -1 42304 -1 -1 176 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92852 22 19 5454 4521 1 2784 228 24 24 576 mult_36 auto 52.1 MiB 1.20 17686 58692 14006 39560 5126 88.5 MiB 1.63 0.02 4.20237 -3287.95 -4.20237 4.20237 1.47 0.00905596 0.00808648 0.861451 0.765781 80 27661 18 1.60519e+07 6.94594e+06 2.72095e+06 4723.87 11.25 3.6755 3.21596 70206 720185 -1 25044 17 9392 10797 1238597 262408 4.39726 4.39726 -3387.93 -4.39726 0 0 3.41546e+06 5929.62 0.92 0.62 0.58 -1 -1 0.92 0.365106 0.326009 1340 1966 703 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_39.v common 21.01 vpr 92.66 MiB 0.31 18068 -1 -1 1 0.60 -1 -1 40220 -1 -1 180 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94884 22 19 5629 4662 1 2882 232 24 24 576 mult_36 auto 52.9 MiB 1.16 17139 55056 12561 37747 4748 89.5 MiB 1.32 0.01 4.39726 -3372.5 -4.39726 4.39726 1.43 0.00421205 0.00376248 0.673509 0.595022 72 32360 40 1.60519e+07 7.0048e+06 2.50747e+06 4353.24 9.53 3.12732 2.7338 67330 654343 -1 26063 15 10213 11721 1450566 306425 4.52256 4.52256 -3562.16 -4.52256 0 0 3.14081e+06 5452.80 0.88 0.66 0.52 -1 -1 0.88 0.362696 0.325953 1381 2032 722 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_40.v common 23.71 vpr 95.62 MiB 0.17 18332 -1 -1 1 0.64 -1 -1 42224 -1 -1 182 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 97920 22 19 5703 4719 1 2929 234 24 24 576 mult_36 auto 53.8 MiB 1.19 17730 54234 12385 37329 4520 90.3 MiB 1.44 0.02 4.27196 -3426.27 -4.27196 4.27196 1.45 0.0096553 0.00863034 0.736039 0.655051 74 32857 35 1.60519e+07 7.03423e+06 2.56259e+06 4448.94 11.86 3.74322 3.27327 67906 667765 -1 27007 17 10660 11973 1577287 328402 4.39726 4.39726 -3639.92 -4.39726 0 0 3.19068e+06 5539.38 0.88 0.72 0.53 -1 -1 0.88 0.399574 0.357659 1400 2051 741 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_41.v common 25.04 vpr 92.39 MiB 0.19 18932 -1 -1 1 0.84 -1 -1 41616 -1 -1 190 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94612 22 19 5950 4932 1 3039 243 24 24 576 mult_36 auto 54.5 MiB 1.28 18494 48755 10232 33831 4692 90.9 MiB 1.31 0.02 4.14666 -3593.15 -4.14666 4.14666 1.49 0.00924519 0.00822018 0.675753 0.598199 78 30524 25 1.60519e+07 7.54795e+06 2.67122e+06 4637.53 12.89 4.04171 3.53277 69630 706637 -1 26409 17 10464 12149 1422734 303195 4.27196 4.27196 -3758.11 -4.27196 0 0 3.35110e+06 5817.88 0.92 0.70 0.57 -1 -1 0.92 0.40952 0.366635 1461 2153 760 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_42.v common 27.13 vpr 92.70 MiB 0.23 18872 -1 -1 1 0.94 -1 -1 42772 -1 -1 193 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94928 22 19 6024 4989 1 3082 246 24 24 576 mult_36 auto 55.2 MiB 1.24 20030 64926 14885 44112 5929 91.5 MiB 1.76 0.02 4.39726 -3645.71 -4.39726 4.39726 1.56 0.00996243 0.008898 0.910422 0.8106 76 36054 42 1.60519e+07 7.5921e+06 2.61600e+06 4541.67 13.78 4.1362 3.61629 68478 680951 -1 29459 18 11439 13299 1697383 348587 4.39726 4.39726 -3948.23 -4.39726 0 0 3.24203e+06 5628.53 1.06 0.83 0.60 -1 -1 1.06 0.459419 0.411692 1480 2172 779 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_43.v common 23.59 vpr 92.35 MiB 0.25 19360 -1 -1 1 1.09 -1 -1 43276 -1 -1 199 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94568 22 19 6198 5129 1 3181 252 24 24 576 mult_36 auto 56.1 MiB 1.30 20168 59082 13911 39065 6106 92.4 MiB 1.54 0.02 4.64786 -3811.84 -4.64786 4.64786 1.45 0.00965356 0.0085898 0.791746 0.702729 74 34701 31 1.60519e+07 7.68039e+06 2.56259e+06 4448.94 10.77 3.6847 3.24442 67906 667765 -1 29515 15 11276 13062 1613817 335267 4.64786 4.64786 -4088.62 -4.64786 0 0 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success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 97556 22 19 6485 5365 1 3338 262 24 24 576 mult_36 auto 57.5 MiB 1.43 21050 68140 15742 46206 6192 93.8 MiB 1.96 0.02 4.3337 -3866.62 -4.3337 4.3337 1.72 0.0110034 0.00985175 1.00708 0.895221 76 37388 40 1.60519e+07 8.20883e+06 2.61600e+06 4541.67 12.17 3.96882 3.48336 68478 680951 -1 29833 26 12212 14243 1891537 439336 4.39726 4.39726 -4071.65 -4.39726 0 0 3.24203e+06 5628.53 0.94 1.11 0.57 -1 -1 0.94 0.649219 0.577456 1593 2342 836 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_46.v common 24.25 vpr 95.32 MiB 0.31 20044 -1 -1 1 1.01 -1 -1 43836 -1 -1 210 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 97604 22 19 6559 5422 1 3380 264 24 24 576 mult_36 auto 57.9 MiB 1.44 20986 65406 14272 45368 5766 94.0 MiB 1.89 0.02 4.41516 -3851.32 -4.41516 4.41516 1.75 0.0104864 0.00925677 0.951179 0.844485 76 35918 33 1.60519e+07 8.23826e+06 2.61600e+06 4541.67 9.96 3.65068 3.18914 68478 680951 -1 30049 16 12176 14229 1658356 357526 4.39726 4.39726 -4137.94 -4.39726 0 0 3.24203e+06 5628.53 0.96 0.81 0.56 -1 -1 0.96 0.45034 0.404231 1613 2361 855 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_47.v common 30.26 vpr 100.97 MiB 0.23 20468 -1 -1 1 0.98 -1 -1 44512 -1 -1 216 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 103392 22 19 6735 5564 1 3477 270 24 24 576 mult_36 auto 59.1 MiB 1.55 24055 64798 13570 44576 6652 95.1 MiB 1.71 0.02 4.39726 -4157.74 -4.39726 4.39726 1.78 0.0113045 0.0101147 0.845251 0.755155 86 40233 49 1.60519e+07 8.32656e+06 2.91907e+06 5067.82 15.99 4.313 3.78276 72506 773887 -1 33084 16 12748 14764 2101422 413693 4.64786 4.64786 -4356.52 -4.64786 0 0 3.65856e+06 6351.67 1.02 0.87 0.65 -1 -1 1.02 0.458208 0.411484 1656 2428 874 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_48.v common 35.47 vpr 96.93 MiB 0.32 20664 -1 -1 1 0.95 -1 -1 44236 -1 -1 218 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 99252 22 19 6809 5621 1 3526 272 24 24 576 mult_36 auto 59.3 MiB 1.50 22900 73395 16707 49770 6918 95.2 MiB 2.15 0.02 4.39726 -4153.76 -4.39726 4.39726 1.67 0.011406 0.0101958 1.08523 0.969545 80 37824 42 1.60519e+07 8.35599e+06 2.72095e+06 4723.87 20.80 5.22399 4.56195 70206 720185 -1 31870 17 12170 14127 1643072 340205 4.52256 4.52256 -4448.16 -4.52256 0 0 3.41546e+06 5929.62 0.98 0.91 0.60 -1 -1 0.98 0.514534 0.462797 1674 2447 893 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_49.v common 31.44 vpr 97.77 MiB 0.33 21116 -1 -1 1 1.20 -1 -1 44496 -1 -1 228 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100120 22 19 7094 5872 1 3640 283 24 24 576 mult_36 auto 60.8 MiB 1.61 22621 68027 14330 47033 6664 96.8 MiB 1.93 0.02 4.32767 -4362.09 -4.32767 4.32767 1.64 0.0119534 0.0107154 0.980804 0.872047 78 38472 32 1.60519e+07 8.89916e+06 2.67122e+06 4637.53 16.89 5.12848 4.48135 69630 706637 -1 32337 18 12793 14786 1774390 369345 4.39726 4.39726 -4662.48 -4.39726 0 0 3.35110e+06 5817.88 0.96 0.89 0.59 -1 -1 0.96 0.506522 0.451565 1745 2569 912 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_50.v common 42.89 vpr 104.99 MiB 0.34 21260 -1 -1 1 1.07 -1 -1 44300 -1 -1 230 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 107512 22 19 7168 5929 1 3676 285 24 24 576 mult_36 auto 61.3 MiB 1.54 23567 73371 16206 50485 6680 97.6 MiB 2.07 0.02 4.52256 -4404.95 -4.52256 4.52256 1.61 0.0121815 0.0108962 1.01563 0.902893 80 39688 35 1.60519e+07 8.92859e+06 2.72095e+06 4723.87 28.13 5.30125 4.63165 70206 720185 -1 33305 16 12887 14936 1843889 377237 4.64786 4.64786 -4684.92 -4.64786 0 0 3.41546e+06 5929.62 0.97 0.88 0.58 -1 -1 0.97 0.48546 0.433223 1764 2588 931 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_51.v common 35.12 vpr 100.53 MiB 0.29 21748 -1 -1 1 1.16 -1 -1 44852 -1 -1 235 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 102940 22 19 7344 6071 1 3782 290 24 24 576 mult_36 auto 61.8 MiB 1.53 23722 73174 15715 50579 6880 97.9 MiB 2.23 0.02 4.459 -4442.21 -4.459 4.459 1.71 0.0129397 0.0114853 1.13602 1.00367 78 40381 49 1.60519e+07 9.00217e+06 2.67122e+06 4637.53 19.81 5.82881 5.09426 69630 706637 -1 33812 17 13492 15556 1913676 402938 4.39726 4.39726 -4781.62 -4.39726 0 0 3.35110e+06 5817.88 0.99 0.96 0.60 -1 -1 0.99 0.553941 0.498992 1808 2655 950 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_52.v common 29.93 vpr 103.93 MiB 0.35 21712 -1 -1 1 1.06 -1 -1 45144 -1 -1 237 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 106420 22 19 7418 6128 1 3828 292 24 24 576 mult_36 auto 63.0 MiB 1.65 25005 78700 18301 52935 7464 99.2 MiB 2.24 0.03 4.3337 -4441.83 -4.3337 4.3337 1.62 0.0141833 0.0126136 1.11433 0.987066 82 41723 40 1.60519e+07 9.0316e+06 2.78508e+06 4835.20 14.40 5.09586 4.46474 70778 734779 -1 34399 17 13048 14909 1766649 364634 4.64786 4.64786 -4948.18 -4.64786 0 0 3.48632e+06 6052.64 1.03 0.91 0.62 -1 -1 1.03 0.529155 0.472554 1827 2674 969 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_14.v common 8.30 vpr 67.70 MiB 0.06 9236 -1 -1 1 0.16 -1 -1 34796 -1 -1 43 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69320 22 19 1246 925 1 718 88 16 16 256 mult_36 auto 29.6 MiB 0.40 3890 12373 3373 7466 1534 67.7 MiB 0.29 0.00 7.60941 -361.611 -7.60941 7.60941 0.58 0.00248719 0.00227377 0.168746 0.154814 48 8671 44 6.62819e+06 2.21677e+06 755748. 2952.14 4.19 0.782373 0.696842 25088 180500 -1 6645 23 6937 7779 935577 227413 8.26573 8.26573 -437.931 -8.26573 0 0 916467. 3579.95 0.32 0.34 0.18 -1 -1 0.32 0.131416 0.117582 299 344 247 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_15.v common 7.86 vpr 67.93 MiB 0.10 9568 -1 -1 1 0.16 -1 -1 35164 -1 -1 46 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69560 22 19 1344 989 1 778 92 16 16 256 mult_36 auto 30.1 MiB 0.35 4185 14168 4013 8552 1603 67.9 MiB 0.34 0.00 7.6175 -392.139 -7.6175 7.6175 0.57 0.00268393 0.00245944 0.195077 0.179222 60 7437 28 6.62819e+06 2.65692e+06 890343. 3477.90 3.66 0.798125 0.713421 27128 224764 -1 6562 26 6006 6790 825899 214119 7.65538 7.65538 -446.805 -7.65538 0 0 1.11577e+06 4358.47 0.27 0.34 0.20 -1 -1 0.27 0.146346 0.13072 321 369 266 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_16.v common 7.58 vpr 68.24 MiB 0.11 9564 -1 -1 1 0.17 -1 -1 35172 -1 -1 48 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69880 22 19 1418 1046 1 821 94 16 16 256 mult_36 auto 30.5 MiB 0.39 4487 13513 3432 8383 1698 68.2 MiB 0.33 0.00 7.60494 -393.597 -7.60494 7.60494 0.58 0.0027842 0.00255165 0.187731 0.172143 56 8390 28 6.62819e+06 2.68636e+06 849745. 3319.32 3.33 0.831016 0.737597 26364 208198 -1 7216 25 7078 7963 962371 230897 7.99013 7.99013 -460.438 -7.99013 0 0 1.04740e+06 4091.43 0.25 0.36 0.25 -1 -1 0.25 0.150063 0.134273 340 388 285 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_17.v common 9.38 vpr 68.71 MiB 0.11 10216 -1 -1 1 0.15 -1 -1 35368 -1 -1 52 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70356 22 19 1518 1112 1 879 98 16 16 256 mult_36 auto 31.0 MiB 0.39 4625 16298 4224 8851 3223 68.7 MiB 0.40 0.01 8.32683 -417.873 -8.32683 8.32683 0.58 0.00298677 0.00271368 0.228688 0.209212 58 9112 39 6.62819e+06 2.74522e+06 871168. 3403.00 5.05 0.9919 0.882394 26872 219187 -1 7252 25 7366 7878 922895 225342 9.12512 9.12512 -480.323 -9.12512 0 0 1.09288e+06 4269.05 0.27 0.39 0.19 -1 -1 0.27 0.167818 0.150821 365 415 304 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_18.v common 11.18 vpr 69.09 MiB 0.12 10396 -1 -1 1 0.19 -1 -1 34952 -1 -1 55 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70752 22 19 1592 1169 1 918 101 16 16 256 mult_36 auto 31.2 MiB 0.42 5347 16316 4097 10275 1944 69.1 MiB 0.41 0.01 8.4422 -469.823 -8.4422 8.4422 0.57 0.00307543 0.00281496 0.225945 0.206695 56 10897 47 6.62819e+06 2.78937e+06 849745. 3319.32 6.50 1.05998 0.941705 26364 208198 -1 9026 32 9275 10182 1519161 349464 9.30818 9.30818 -562.145 -9.30818 0 0 1.04740e+06 4091.43 0.25 0.55 0.18 -1 -1 0.25 0.20576 0.183578 383 434 323 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_19.v common 10.03 vpr 69.58 MiB 0.08 10668 -1 -1 1 0.20 -1 -1 35488 -1 -1 58 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71252 22 19 1688 1231 1 976 105 16 16 256 mult_36 auto 31.8 MiB 0.46 5523 17642 4653 10328 2661 69.6 MiB 0.43 0.01 8.2901 -468.025 -8.2901 8.2901 0.57 0.00321502 0.00294453 0.244246 0.223338 58 10958 42 6.62819e+06 3.22951e+06 871168. 3403.00 5.27 1.08965 0.971784 26872 219187 -1 8881 23 8148 9336 1045786 240112 9.19702 9.19702 -670.638 -9.19702 0 0 1.09288e+06 4269.05 0.36 0.44 0.21 -1 -1 0.36 0.170417 0.152624 404 457 342 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_20.v common 9.80 vpr 70.05 MiB 0.08 10652 -1 -1 1 0.22 -1 -1 35588 -1 -1 59 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71732 22 19 1762 1288 1 1014 106 16 16 256 mult_36 auto 32.2 MiB 0.47 5650 16606 4202 10324 2080 70.1 MiB 0.45 0.01 8.4978 -488.18 -8.4978 8.4978 0.57 0.00334718 0.00305518 0.244371 0.222607 56 11507 38 6.62819e+06 3.24423e+06 849745. 3319.32 4.85 1.09951 0.975231 26364 208198 -1 9516 27 10307 11396 1607507 371242 9.22112 9.22112 -579.067 -9.22112 0 0 1.04740e+06 4091.43 0.27 0.59 0.21 -1 -1 0.27 0.202265 0.180619 423 476 361 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_21.v common 10.37 vpr 70.59 MiB 0.13 10924 -1 -1 1 0.23 -1 -1 35984 -1 -1 62 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72284 22 19 1859 1351 1 1072 109 16 16 256 mult_36 auto 32.8 MiB 0.52 6035 17789 4471 10978 2340 70.6 MiB 0.50 0.01 8.38109 -487.093 -8.38109 8.38109 0.58 0.00353177 0.00322401 0.258398 0.235679 60 12117 48 6.62819e+06 3.28838e+06 890343. 3477.90 5.30 1.15998 1.0304 27128 224764 -1 9393 23 8484 9643 1075611 255217 9.04658 9.04658 -638.837 -9.04658 0 0 1.11577e+06 4358.47 0.34 0.43 0.20 -1 -1 0.34 0.187693 0.169332 445 500 380 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_22.v common 9.75 vpr 71.11 MiB 0.15 11060 -1 -1 1 0.23 -1 -1 35992 -1 -1 66 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72816 22 19 1933 1408 1 1111 113 16 16 256 mult_36 auto 33.4 MiB 0.55 6447 14582 3335 9243 2004 71.1 MiB 0.40 0.01 8.38225 -539.049 -8.38225 8.38225 0.52 0.00372084 0.00340025 0.211763 0.193395 66 12032 36 6.62819e+06 3.34724e+06 974584. 3806.97 4.64 1.11576 0.989347 28148 247068 -1 9826 24 8221 9433 1042848 236369 8.80852 8.80852 -690.661 -8.80852 0 0 1.22072e+06 4768.46 0.29 0.44 0.23 -1 -1 0.29 0.195304 0.175492 464 519 399 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_23.v common 12.26 vpr 71.07 MiB 0.15 11404 -1 -1 1 0.25 -1 -1 36004 -1 -1 68 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72780 22 19 2031 1472 1 1174 116 18 18 324 mult_36 auto 33.5 MiB 0.60 6930 17882 4089 11335 2458 71.1 MiB 0.47 0.01 8.41364 -547.214 -8.41364 8.41364 0.75 0.00373301 0.0033942 0.252968 0.230155 60 13146 46 8.18539e+06 3.77267e+06 1.16833e+06 3605.96 6.44 1.26858 1.12367 35004 297736 -1 10629 25 9789 11037 1322884 293485 8.79022 8.79022 -667.882 -8.79022 0 0 1.46313e+06 4515.82 0.37 0.55 0.26 -1 -1 0.37 0.222269 0.199302 486 544 418 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_24.v common 28.06 vpr 71.67 MiB 0.15 11572 -1 -1 1 0.26 -1 -1 36336 -1 -1 71 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73388 22 19 2105 1529 1 1210 119 18 18 324 mult_36 auto 34.0 MiB 0.57 6947 19099 4545 12489 2065 71.7 MiB 0.50 0.01 8.54591 -592.304 -8.54591 8.54591 0.76 0.00387295 0.00353344 0.268825 0.244429 58 13826 37 8.18539e+06 3.81682e+06 1.14310e+06 3528.09 22.14 2.16612 1.90652 34680 290288 -1 11315 25 10013 11336 1455403 323969 9.26762 9.26762 -836.784 -9.26762 0 0 1.43297e+06 4422.75 0.38 0.51 0.26 -1 -1 0.38 0.191148 0.172557 505 563 437 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_25.v common 12.18 vpr 72.28 MiB 0.10 11840 -1 -1 1 0.28 -1 -1 36436 -1 -1 73 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74016 22 19 2201 1591 1 1268 121 18 18 324 mult_36 auto 34.8 MiB 0.59 7634 22247 5441 14246 2560 72.3 MiB 0.59 0.01 8.41835 -567.959 -8.41835 8.41835 0.75 0.00403852 0.00366175 0.317042 0.288294 64 14202 44 8.18539e+06 3.84625e+06 1.23838e+06 3822.15 6.20 1.44631 1.28376 35972 318676 -1 11820 29 12088 13740 1940094 442042 8.68898 8.68898 -781.144 -8.68898 0 0 1.56068e+06 4816.91 0.38 0.65 0.28 -1 -1 0.38 0.246613 0.219596 526 586 456 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_26.v common 11.94 vpr 72.46 MiB 0.10 11936 -1 -1 1 0.28 -1 -1 37420 -1 -1 76 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74204 22 19 2275 1648 1 1306 124 18 18 324 mult_36 auto 35.1 MiB 0.81 7751 20827 4662 13516 2649 72.5 MiB 0.57 0.01 8.56929 -568.623 -8.56929 8.56929 0.77 0.00413781 0.00376541 0.298181 0.271274 60 14701 32 8.18539e+06 3.8904e+06 1.16833e+06 3605.96 5.72 1.33007 1.17753 35004 297736 -1 12032 25 10795 12330 1483067 336752 8.81798 8.81798 -886.816 -8.81798 0 0 1.46313e+06 4515.82 0.37 0.55 0.25 -1 -1 0.37 0.224402 0.199898 546 605 475 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_27.v common 12.20 vpr 73.11 MiB 0.16 12176 -1 -1 1 0.31 -1 -1 36624 -1 -1 82 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74864 22 19 2385 1724 1 1378 131 18 18 324 mult_36 auto 35.7 MiB 0.67 8283 20383 4936 13018 2429 73.1 MiB 0.56 0.01 8.5461 -628.049 -8.5461 8.5461 0.75 0.00441244 0.00400671 0.289094 0.262967 68 14535 41 8.18539e+06 4.37469e+06 1.31159e+06 4048.11 5.93 1.42908 1.26783 36620 334356 -1 12409 26 10631 12441 1427422 320553 8.58227 8.58227 -875.158 -8.58227 0 0 1.63345e+06 5041.52 0.41 0.56 0.28 -1 -1 0.41 0.247584 0.221266 575 642 494 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_28.v common 16.70 vpr 73.46 MiB 0.17 12280 -1 -1 1 0.31 -1 -1 36788 -1 -1 83 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75224 22 19 2459 1781 1 1417 132 18 18 324 mult_36 auto 36.1 MiB 0.64 8787 24252 5813 15988 2451 73.5 MiB 0.63 0.01 8.59036 -640.13 -8.59036 8.59036 0.74 0.00438785 0.00398589 0.335875 0.305032 58 18144 50 8.18539e+06 4.3894e+06 1.14310e+06 3528.09 10.39 1.61231 1.42708 34680 290288 -1 13981 22 13072 15000 1915715 426043 9.02382 9.02382 -822.024 -9.02382 0 0 1.43297e+06 4422.75 0.36 0.64 0.24 -1 -1 0.36 0.241009 0.217144 594 661 513 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_29.v common 17.70 vpr 73.96 MiB 0.18 12728 -1 -1 1 0.32 -1 -1 37292 -1 -1 85 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75732 22 19 2565 1853 1 1485 135 22 22 484 mult_36 auto 36.7 MiB 0.71 9693 25047 5824 16462 2761 74.0 MiB 0.71 0.01 8.56824 -658.817 -8.56824 8.56824 1.22 0.00474006 0.0043231 0.362784 0.329646 64 18425 33 1.33067e+07 4.81483e+06 1.90554e+06 3937.06 9.45 1.53093 1.35853 54502 494576 -1 15063 28 14458 16832 2340289 516030 8.76628 8.76628 -928.497 -8.76628 0 0 2.40101e+06 4960.76 0.62 0.77 0.40 -1 -1 0.62 0.280264 0.250411 619 694 532 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_30.v common 15.00 vpr 74.31 MiB 0.08 12824 -1 -1 1 0.34 -1 -1 37428 -1 -1 89 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76096 22 19 2639 1910 1 1523 139 22 22 484 mult_36 auto 37.1 MiB 0.74 9384 25628 5988 16697 2943 74.3 MiB 0.72 0.01 8.44238 -674.317 -8.44238 8.44238 1.23 0.00474821 0.00431628 0.368392 0.334281 70 15871 29 1.33067e+07 4.87369e+06 2.06816e+06 4273.05 6.97 1.51562 1.34444 56434 539830 -1 14145 24 11726 13596 1807233 398151 9.10687 9.10687 -826.57 -9.10687 0 0 2.60483e+06 5381.88 0.69 0.64 0.44 -1 -1 0.69 0.255512 0.228396 639 713 551 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_31.v common 17.31 vpr 74.87 MiB 0.19 12964 -1 -1 1 0.39 -1 -1 37424 -1 -1 93 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76664 22 19 2744 1981 1 1590 143 22 22 484 mult_36 auto 37.7 MiB 0.74 9784 30356 7187 19530 3639 74.9 MiB 0.86 0.01 8.38567 -675.978 -8.38567 8.38567 1.22 0.00507411 0.00456402 0.440825 0.399147 64 18972 47 1.33067e+07 4.93255e+06 1.90554e+06 3937.06 9.03 1.81872 1.61299 54502 494576 -1 15109 27 13335 15415 2075489 440624 9.05667 9.05667 -930.353 -9.05667 0 0 2.40101e+06 4960.76 0.63 0.71 0.40 -1 -1 0.63 0.28603 0.255035 665 745 570 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_32.v common 59.78 vpr 75.20 MiB 0.13 13060 -1 -1 1 0.42 -1 -1 36820 -1 -1 96 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77008 22 19 2818 2038 1 1627 146 22 22 484 mult_36 auto 37.9 MiB 0.81 9765 27794 6626 18138 3030 75.2 MiB 0.78 0.01 8.43423 -706.833 -8.43423 8.43423 1.24 0.00503391 0.00455887 0.393484 0.356822 68 17281 43 1.33067e+07 4.9767e+06 2.01763e+06 4168.66 51.47 3.45154 3.04118 55470 518816 -1 14549 26 13387 15791 1843918 396984 8.48238 8.48238 -1019.62 -8.48238 0 0 2.51205e+06 5190.18 0.66 0.73 0.35 -1 -1 0.66 0.32025 0.287688 684 764 589 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_33.v common 18.67 vpr 75.77 MiB 0.20 13728 -1 -1 1 0.40 -1 -1 37556 -1 -1 100 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77588 22 19 2923 2109 1 1695 151 22 22 484 mult_36 auto 38.4 MiB 0.73 10394 32632 7799 20384 4449 75.8 MiB 0.93 0.01 9.15948 -780.094 -9.15948 9.15948 1.23 0.00550841 0.00496395 0.466464 0.422627 68 19006 40 1.33067e+07 5.43155e+06 2.01763e+06 4168.66 10.13 1.85464 1.64421 55470 518816 -1 15474 24 12536 14090 1741858 383228 9.73142 9.73142 -1174.71 -9.73142 0 0 2.51205e+06 5190.18 0.66 0.64 0.41 -1 -1 0.66 0.274146 0.24518 710 796 608 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_34.v common 17.07 vpr 76.12 MiB 0.15 13748 -1 -1 1 0.44 -1 -1 37840 -1 -1 101 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77944 22 19 2997 2166 1 1734 152 22 22 484 mult_36 auto 38.9 MiB 1.01 10711 29717 6877 19660 3180 76.1 MiB 0.85 0.01 9.29828 -782.067 -9.29828 9.29828 1.27 0.00537933 0.00488556 0.439577 0.398766 68 19336 39 1.33067e+07 5.44627e+06 2.01763e+06 4168.66 8.09 1.80439 1.59957 55470 518816 -1 15822 25 13222 15017 1923830 410698 9.61867 9.61867 -1083.26 -9.61867 0 0 2.51205e+06 5190.18 0.67 0.74 0.44 -1 -1 0.67 0.31043 0.277578 729 815 627 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_35.v common 18.30 vpr 76.68 MiB 0.23 14092 -1 -1 1 0.43 -1 -1 37608 -1 -1 106 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78520 22 19 3101 2236 1 1801 157 22 22 484 mult_36 auto 39.4 MiB 1.05 11402 28075 6295 18501 3279 76.7 MiB 0.81 0.01 9.47066 -829.471 -9.47066 9.47066 1.22 0.00609179 0.00558557 0.405266 0.367879 70 19800 47 1.33067e+07 5.51985e+06 2.06816e+06 4273.05 9.21 1.86486 1.65176 56434 539830 -1 16867 24 13697 15802 2138431 452706 9.74781 9.74781 -1050.32 -9.74781 0 0 2.60483e+06 5381.88 0.70 0.76 0.44 -1 -1 0.70 0.299055 0.26771 755 846 646 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_36.v common 21.97 vpr 77.04 MiB 0.21 14088 -1 -1 1 0.44 -1 -1 38016 -1 -1 107 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78888 22 19 3175 2293 1 1836 158 22 22 484 mult_36 auto 39.8 MiB 1.13 11170 30902 7166 20385 3351 77.0 MiB 0.94 0.01 9.18378 -834.69 -9.18378 9.18378 1.25 0.00580597 0.00527978 0.477711 0.431692 60 23060 49 1.33067e+07 5.53456e+06 1.79840e+06 3715.71 12.89 2.11193 1.86795 53054 462096 -1 17670 24 14840 17527 2134269 458631 9.53001 9.53001 -1214.3 -9.53001 0 0 2.25108e+06 4650.99 0.61 0.77 0.38 -1 -1 0.61 0.306378 0.273847 773 865 665 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_37.v common 21.82 vpr 77.66 MiB 0.22 14376 -1 -1 1 0.43 -1 -1 37340 -1 -1 111 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79520 22 19 3280 2364 1 1904 163 24 24 576 mult_36 auto 40.5 MiB 1.15 11916 36653 8512 22659 5482 77.7 MiB 1.10 0.01 9.503 -813.596 -9.503 9.503 1.55 0.00616994 0.00541883 0.561311 0.506567 68 21847 36 1.60519e+07 5.98942e+06 2.39371e+06 4155.74 11.44 2.14252 1.89965 65606 615345 -1 17297 31 13826 16479 2281397 551091 9.31947 9.31947 -1215.55 -9.31947 0 0 2.98162e+06 5176.42 0.78 0.89 0.49 -1 -1 0.78 0.378325 0.337347 798 897 684 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_38.v common 19.36 vpr 78.34 MiB 0.28 14508 -1 -1 1 0.44 -1 -1 37968 -1 -1 113 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80220 22 19 3354 2421 1 1941 165 24 24 576 mult_36 auto 41.1 MiB 1.27 13091 35421 8629 23184 3608 78.3 MiB 1.06 0.01 9.56954 -911.791 -9.56954 9.56954 1.50 0.0060493 0.00549289 0.531047 0.479941 70 22176 36 1.60519e+07 6.01886e+06 2.45377e+06 4260.01 8.83 2.08523 1.84725 66754 640332 -1 18678 23 12610 14627 1802919 388775 9.66152 9.66152 -1189.17 -9.66152 0 0 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success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80760 22 19 3531 2547 1 2046 172 24 24 576 mult_36 auto 41.7 MiB 1.34 13416 38890 9004 25965 3921 78.9 MiB 1.13 0.01 9.43624 -981.01 -9.43624 9.43624 1.43 0.00625586 0.00565441 0.543303 0.489943 70 23523 44 1.60519e+07 6.12186e+06 2.45377e+06 4260.01 11.31 2.23268 1.9759 66754 640332 -1 19563 25 14474 17290 2278221 477004 9.83772 9.83772 -1353.33 -9.83772 0 0 3.09179e+06 5367.68 0.86 0.84 0.51 -1 -1 0.86 0.367156 0.327513 862 965 741 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_41.v common 21.92 vpr 79.35 MiB 0.22 15180 -1 -1 1 0.52 -1 -1 38096 -1 -1 122 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81256 22 19 3634 2616 1 2113 175 24 24 576 mult_36 auto 42.3 MiB 1.31 14260 37339 8299 25744 3296 79.4 MiB 1.14 0.01 9.48942 -936.304 -9.48942 9.48942 1.49 0.00675422 0.00614536 0.558513 0.504178 76 24101 46 1.60519e+07 6.5473e+06 2.61600e+06 4541.67 11.02 2.44748 2.17082 68478 680951 -1 20450 26 13980 16375 2275565 472356 10.0482 10.0482 -1255.71 -10.0482 0 0 3.24203e+06 5628.53 0.92 0.87 0.54 -1 -1 0.92 0.371853 0.332549 886 995 760 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_42.v common 22.42 vpr 80.11 MiB 0.12 15260 -1 -1 1 0.45 -1 -1 38348 -1 -1 125 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82028 22 19 3708 2673 1 2147 178 24 24 576 mult_36 auto 42.9 MiB 1.36 13247 38178 8698 26287 3193 80.1 MiB 1.07 0.01 9.34555 -911.748 -9.34555 9.34555 1.44 0.0064956 0.00588021 0.52583 0.474314 68 24266 46 1.60519e+07 6.59144e+06 2.39371e+06 4155.74 12.11 2.37149 2.09472 65606 615345 -1 19305 25 14215 16917 2027268 431068 9.41247 9.41247 -1370.03 -9.41247 0 0 2.98162e+06 5176.42 0.76 0.76 0.48 -1 -1 0.76 0.345503 0.307881 906 1014 779 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_43.v common 23.50 vpr 80.20 MiB 0.16 15604 -1 -1 1 0.54 -1 -1 38872 -1 -1 129 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82124 22 19 3810 2741 1 2214 182 24 24 576 mult_36 auto 43.1 MiB 1.40 14854 39322 8760 27092 3470 80.2 MiB 1.18 0.01 9.43515 -973.044 -9.43515 9.43515 1.50 0.00665249 0.00603299 0.564376 0.511736 70 26179 39 1.60519e+07 6.6503e+06 2.45377e+06 4260.01 12.41 2.38973 2.11663 66754 640332 -1 21790 27 16236 19013 2690277 570799 10.0622 10.0622 -1353.82 -10.0622 0 0 3.09179e+06 5367.68 0.89 1.00 0.52 -1 -1 0.89 0.406695 0.362835 930 1043 798 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_44.v common 21.15 vpr 80.74 MiB 0.15 15680 -1 -1 1 0.55 -1 -1 38396 -1 -1 132 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82680 22 19 3884 2798 1 2251 185 24 24 576 mult_36 auto 43.6 MiB 1.51 14264 43317 10157 28920 4240 80.7 MiB 1.14 0.01 9.54931 -1049.89 -9.54931 9.54931 1.45 0.00442549 0.0040212 0.566381 0.512217 70 23866 43 1.60519e+07 6.69445e+06 2.45377e+06 4260.01 10.14 2.47136 2.1912 66754 640332 -1 20739 24 16345 18902 2422633 514103 9.94026 9.94026 -1346.73 -9.94026 0 0 3.09179e+06 5367.68 0.84 0.90 0.53 -1 -1 0.84 0.372298 0.33204 949 1062 817 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_45.v common 21.13 vpr 81.10 MiB 0.14 15976 -1 -1 1 0.58 -1 -1 40524 -1 -1 135 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83048 22 19 3989 2869 1 2318 189 24 24 576 mult_36 auto 43.9 MiB 1.45 15002 45717 10664 29972 5081 81.1 MiB 1.34 0.02 9.30374 -1001.57 -9.30374 9.30374 1.52 0.00746911 0.00679006 0.668085 0.604004 74 24106 34 1.60519e+07 7.1346e+06 2.56259e+06 4448.94 9.60 2.47418 2.18875 67906 667765 -1 21115 26 15678 18406 2326491 502931 9.44027 9.44027 -1425.49 -9.44027 0 0 3.19068e+06 5539.38 0.86 0.92 0.59 -1 -1 0.86 0.405328 0.361259 975 1094 836 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_46.v common 24.34 vpr 81.14 MiB 0.24 16108 -1 -1 1 0.56 -1 -1 40476 -1 -1 136 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83088 22 19 4063 2926 1 2357 190 24 24 576 mult_36 auto 44.1 MiB 1.54 15384 39502 8716 27417 3369 81.1 MiB 1.20 0.02 9.25444 -1065.06 -9.25444 9.25444 1.46 0.00819881 0.00737383 0.591398 0.531649 68 28280 44 1.60519e+07 7.14931e+06 2.39371e+06 4155.74 13.33 2.59794 2.29721 65606 615345 -1 22363 25 16582 19483 2454716 510839 9.51877 9.51877 -1579.55 -9.51877 0 0 2.98162e+06 5176.42 0.80 0.77 0.50 -1 -1 0.80 0.295053 0.265261 993 1113 855 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_47.v common 22.95 vpr 81.84 MiB 0.28 16676 -1 -1 1 0.57 -1 -1 40860 -1 -1 141 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83800 22 19 4167 2996 1 2421 195 24 24 576 mult_36 auto 44.9 MiB 1.52 15434 47655 11175 32212 4268 81.8 MiB 1.45 0.02 9.32624 -1067.91 -9.32624 9.32624 1.46 0.00866741 0.00766169 0.705291 0.6329 68 26939 44 1.60519e+07 7.22289e+06 2.39371e+06 4155.74 11.15 2.73486 2.41721 65606 615345 -1 22408 22 17205 20128 2344851 525433 9.69172 9.69172 -1531.77 -9.69172 0 0 2.98162e+06 5176.42 0.89 0.86 0.54 -1 -1 0.89 0.360779 0.3226 1019 1144 874 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_48.v common 26.04 vpr 84.46 MiB 0.28 16560 -1 -1 1 0.62 -1 -1 40944 -1 -1 144 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86488 22 19 4241 3053 1 2459 198 24 24 576 mult_36 auto 45.1 MiB 1.63 16101 43398 9885 28969 4544 82.2 MiB 1.32 0.02 9.15276 -1137.39 -9.15276 9.15276 1.41 0.00812705 0.00725182 0.602704 0.540065 74 28016 46 1.60519e+07 7.26704e+06 2.56259e+06 4448.94 14.11 3.02835 2.67053 67906 667765 -1 23184 26 19200 22279 3097523 635988 10.1736 10.1736 -1421.35 -10.1736 0 0 3.19068e+06 5539.38 0.89 1.12 0.55 -1 -1 0.89 0.441622 0.39392 1038 1163 893 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_49.v common 22.70 vpr 82.50 MiB 0.30 17020 -1 -1 1 0.63 -1 -1 41164 -1 -1 145 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84476 22 19 4346 3124 1 2527 200 24 24 576 mult_36 auto 45.8 MiB 1.58 16303 42248 9563 28218 4467 82.5 MiB 1.25 0.02 9.38798 -1053.9 -9.38798 9.38798 1.45 0.00782229 0.00708899 0.606041 0.545412 76 26459 35 1.60519e+07 7.67775e+06 2.61600e+06 4541.67 10.77 2.5998 2.30202 68478 680951 -1 22900 23 17127 19789 2450260 525170 9.49071 9.49071 -1363.71 -9.49071 0 0 3.24203e+06 5628.53 0.88 0.95 0.57 -1 -1 0.88 0.408657 0.365417 1062 1195 912 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_50.v common 24.93 vpr 84.88 MiB 0.30 16992 -1 -1 1 0.62 -1 -1 40960 -1 -1 148 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86916 22 19 4420 3181 1 2564 203 24 24 576 mult_36 auto 46.2 MiB 1.72 16495 43711 9469 30201 4041 82.7 MiB 1.31 0.02 9.43609 -1064.71 -9.43609 9.43609 1.44 0.0088878 0.00796896 0.634709 0.572282 74 29023 44 1.60519e+07 7.72189e+06 2.56259e+06 4448.94 12.97 2.85564 2.52665 67906 667765 -1 23678 25 18523 22416 2877968 597216 9.48707 9.48707 -1821.24 -9.48707 0 0 3.19068e+06 5539.38 0.86 1.01 0.55 -1 -1 0.86 0.421101 0.376085 1082 1214 931 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_51.v common 23.60 vpr 83.62 MiB 0.31 17388 -1 -1 1 0.50 -1 -1 41132 -1 -1 152 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85628 22 19 4524 3251 1 2634 207 24 24 576 mult_36 auto 46.9 MiB 1.47 16985 41823 9101 28954 3768 83.6 MiB 1.27 0.02 9.734 -1168.67 -9.734 9.734 1.49 0.00828626 0.00752653 0.605156 0.543297 72 29204 35 1.60519e+07 7.78076e+06 2.50747e+06 4353.24 11.88 2.7076 2.39559 67330 654343 -1 24180 25 18625 21935 2835680 592310 9.95301 9.95301 -1799.32 -9.95301 0 0 3.14081e+06 5452.80 0.84 1.10 0.55 -1 -1 0.84 0.463942 0.414065 1107 1245 950 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_52.v common 23.86 vpr 86.70 MiB 0.30 17404 -1 -1 1 0.68 -1 -1 39356 -1 -1 155 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88776 22 19 4598 3308 1 2668 210 24 24 576 mult_36 auto 47.2 MiB 1.76 17259 43266 9678 28409 5179 84.2 MiB 1.25 0.02 9.7565 -1135.89 -9.7565 9.7565 1.46 0.00829854 0.00752642 0.618965 0.557544 72 30374 50 1.60519e+07 7.8249e+06 2.50747e+06 4353.24 11.75 2.94605 2.60428 67330 654343 -1 24994 25 20197 24076 3112218 653789 9.59001 9.59001 -1667.66 -9.59001 0 0 3.14081e+06 5452.80 0.89 1.12 0.53 -1 -1 0.89 0.451547 0.402446 1127 1264 969 19 0 0 -k6_frac_N8_22nm.xml fir_pipe_14.v common 35.06 vpr 70.03 MiB 0.07 10400 -1 -1 8 0.52 -1 -1 34576 -1 -1 79 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71708 22 19 1764 1664 1 1014 124 16 16 256 mult_36 auto 32.0 MiB 0.61 6309 13720 2598 9792 1330 70.0 MiB 0.31 0.01 4.27196 -1341.5 -4.27196 4.27196 0.57 0.00354648 0.00317141 0.178158 0.159799 62 13731 45 6.45408e+06 2.64829e+06 916467. 3579.95 30.10 2.06286 1.78614 26824 229188 -1 9858 17 4242 7313 542219 128340 4.27196 4.27196 -1342.23 -4.27196 0 0 1.13630e+06 4438.68 0.29 0.31 0.20 -1 -1 0.29 0.168254 0.151358 599 966 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_15.v common 9.44 vpr 71.33 MiB 0.12 10904 -1 -1 8 0.42 -1 -1 36132 -1 -1 85 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73044 22 19 1918 1801 1 1104 131 16 16 256 mult_36 auto 32.9 MiB 0.59 6626 16731 3359 11755 1617 71.3 MiB 0.41 0.01 4.52256 -1452.91 -4.52256 4.52256 0.59 0.00446844 0.00396271 0.2364 0.211929 64 12736 29 6.45408e+06 3.12512e+06 943753. 3686.54 4.24 1.25278 1.0975 27332 240185 -1 10846 16 4390 7653 589954 137377 4.39726 4.39726 -1545.05 -4.39726 0 0 1.19033e+06 4649.74 0.30 0.34 0.22 -1 -1 0.30 0.187048 0.169073 651 1047 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_16.v common 9.35 vpr 71.73 MiB 0.10 10872 -1 -1 8 0.52 -1 -1 37432 -1 -1 87 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73448 22 19 1976 1859 1 1141 133 16 16 256 mult_36 auto 33.4 MiB 0.64 7164 16066 3216 11368 1482 71.7 MiB 0.37 0.01 4.28601 -1479.04 -4.28601 4.28601 0.58 0.00387816 0.00346619 0.213837 0.190981 66 14097 31 6.45408e+06 3.15206e+06 974584. 3806.97 4.07 1.22789 1.07012 27588 246658 -1 11314 14 4644 8048 628529 143762 4.39726 4.39726 -1506.32 -4.39726 0 0 1.22072e+06 4768.46 0.30 0.29 0.24 -1 -1 0.30 0.152509 0.136574 679 1086 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_17.v common 10.64 vpr 72.72 MiB 0.19 11888 -1 -1 8 0.54 -1 -1 36740 -1 -1 102 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74464 22 19 2278 2144 1 1269 148 16 16 256 mult_36 auto 34.9 MiB 0.67 8095 16961 3169 12034 1758 72.7 MiB 0.39 0.01 4.27196 -1685.47 -4.27196 4.27196 0.61 0.00431669 0.00384312 0.216345 0.192777 66 15895 38 6.45408e+06 3.35414e+06 974584. 3806.97 4.97 1.40484 1.2203 27588 246658 -1 12871 17 5512 9156 773452 182436 4.14666 4.14666 -1714.79 -4.14666 0 0 1.22072e+06 4768.46 0.29 0.35 0.23 -1 -1 0.29 0.187032 0.166489 768 1242 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_18.v common 10.64 vpr 73.61 MiB 0.13 11900 -1 -1 8 0.64 -1 -1 37788 -1 -1 105 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75380 22 19 2336 2202 1 1299 151 16 16 256 mult_36 auto 35.2 MiB 0.49 8142 19800 3855 14118 1827 73.6 MiB 0.45 0.01 4.27196 -1743.36 -4.27196 4.27196 0.57 0.00455664 0.00406375 0.2538 0.22658 66 16357 31 6.45408e+06 3.39456e+06 974584. 3806.97 5.10 1.41202 1.23044 27588 246658 -1 13041 16 5315 9387 790244 175589 4.27196 4.27196 -1778.91 -4.27196 0 0 1.22072e+06 4768.46 0.29 0.38 0.23 -1 -1 0.29 0.193318 0.172161 794 1281 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_19.v common 24.75 vpr 74.32 MiB 0.14 12416 -1 -1 8 0.68 -1 -1 37468 -1 -1 111 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76104 22 19 2488 2337 1 1399 158 16 16 256 mult_36 auto 36.3 MiB 0.69 9188 20654 3849 14830 1975 74.3 MiB 0.46 0.01 4.52256 -1895.49 -4.52256 4.52256 0.57 0.00473762 0.00422106 0.259355 0.231093 68 18182 48 6.45408e+06 3.87139e+06 1.00038e+06 3907.74 18.65 2.74248 2.3778 27844 252052 -1 14297 34 5758 10179 1038312 262783 4.52256 4.52256 -1955.57 -4.52256 0 0 1.24648e+06 4869.04 0.30 0.58 0.21 -1 -1 0.30 0.341379 0.298117 837 1360 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_20.v common 11.64 vpr 74.53 MiB 0.15 12376 -1 -1 8 0.72 -1 -1 37532 -1 -1 114 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76316 22 19 2546 2395 1 1440 161 16 16 256 mult_36 auto 36.6 MiB 0.76 9425 20700 4100 14535 2065 74.5 MiB 0.49 0.01 4.32767 -1936.05 -4.32767 4.32767 0.60 0.00479328 0.00425549 0.262515 0.233316 70 17071 27 6.45408e+06 3.91181e+06 1.02522e+06 4004.78 5.44 1.50404 1.31263 28352 262101 -1 14775 14 5841 10666 895010 199961 4.39726 4.39726 -1935.26 -4.39726 0 0 1.29210e+06 5047.26 0.33 0.40 0.24 -1 -1 0.33 0.202434 0.182515 867 1399 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_21.v common 13.89 vpr 75.57 MiB 0.08 12880 -1 -1 8 0.83 -1 -1 37748 -1 -1 122 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77380 22 19 2735 2567 1 1547 169 16 16 256 mult_36 auto 37.5 MiB 0.80 10400 22118 4046 16008 2064 75.6 MiB 0.53 0.01 4.52256 -2137.28 -4.52256 4.52256 0.58 0.00516143 0.00458229 0.287244 0.254668 70 19515 48 6.45408e+06 4.01958e+06 1.02522e+06 4004.78 7.48 1.81902 1.57916 28352 262101 -1 15796 16 6443 11250 987187 224359 4.39726 4.39726 -2218.61 -4.39726 0 0 1.29210e+06 5047.26 0.31 0.44 0.24 -1 -1 0.31 0.220885 0.198288 931 1497 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_22.v common 13.34 vpr 75.62 MiB 0.30 13172 -1 -1 8 0.95 -1 -1 38144 -1 -1 126 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77440 22 19 2793 2625 1 1580 173 16 16 256 mult_36 auto 38.0 MiB 0.83 10482 25185 5093 17461 2631 75.6 MiB 0.56 0.01 4.39726 -2104.19 -4.39726 4.39726 0.57 0.00537934 0.0047865 0.308563 0.273921 72 20575 41 6.45408e+06 4.07347e+06 1.04740e+06 4091.43 6.34 1.82921 1.59368 28608 268066 -1 16169 16 6398 11556 979161 224597 4.39726 4.39726 -2198.12 -4.39726 0 0 1.31294e+06 5128.69 0.35 0.45 0.25 -1 -1 0.35 0.226758 0.202105 962 1536 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_23.v common 16.01 vpr 76.38 MiB 0.16 13296 -1 -1 8 0.89 -1 -1 38448 -1 -1 131 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78216 22 19 2947 2762 1 1693 179 18 18 324 mult_36 auto 39.0 MiB 0.93 10552 29411 6189 20863 2359 76.4 MiB 0.70 0.01 4.33362 -2228.91 -4.33362 4.33362 0.66 0.00580614 0.00516197 0.384101 0.340643 68 20948 46 7.94662e+06 4.53683e+06 1.31159e+06 4048.11 8.55 2.05696 1.79391 35852 333792 -1 17072 17 7143 12403 1006005 225429 4.27196 4.27196 -2354.78 -4.27196 0 0 1.63345e+06 5041.52 0.41 0.48 0.29 -1 -1 0.41 0.256808 0.22909 1008 1617 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_24.v common 14.93 vpr 76.59 MiB 0.17 13576 -1 -1 8 1.00 -1 -1 38700 -1 -1 135 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78424 22 19 3005 2820 1 1720 183 18 18 324 mult_36 auto 39.2 MiB 0.91 11450 28728 5932 20637 2159 76.6 MiB 0.66 0.01 4.52256 -2356.78 -4.52256 4.52256 0.75 0.00574229 0.00510157 0.358146 0.317759 72 21726 43 7.94662e+06 4.59072e+06 1.37338e+06 4238.83 7.31 1.99763 1.74589 36820 354972 -1 17934 15 7047 12424 1077888 233656 4.52256 4.52256 -2526.88 -4.52256 0 0 1.72054e+06 5310.31 0.42 0.49 0.31 -1 -1 0.42 0.23615 0.211458 1039 1656 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_25.v common 16.53 vpr 77.66 MiB 0.18 13972 -1 -1 8 1.00 -1 -1 40404 -1 -1 145 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79524 22 19 3229 3027 1 1824 193 18 18 324 mult_36 auto 40.2 MiB 0.96 12352 31385 6347 23011 2027 77.7 MiB 0.71 0.01 4.39726 -2511.96 -4.39726 4.39726 0.75 0.0065231 0.00581076 0.383994 0.340359 70 22936 50 7.94662e+06 4.72544e+06 1.34436e+06 4149.26 8.72 2.23382 1.94605 36496 347204 -1 19370 16 7698 13674 1225432 265565 4.39726 4.39726 -2525.78 -4.39726 0 0 1.69344e+06 5226.66 0.45 0.57 0.25 -1 -1 0.45 0.288571 0.258231 1106 1771 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_26.v common 33.53 vpr 78.91 MiB 0.16 14212 -1 -1 8 1.12 -1 -1 40760 -1 -1 151 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80804 22 19 3287 3085 1 1862 199 18 18 324 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2.29136 2.00107 37144 362180 -1 20914 15 8108 14439 1272992 270691 4.39726 4.39726 -2705.27 -4.39726 0 0 1.74764e+06 5393.95 0.42 0.54 0.30 -1 -1 0.42 0.270946 0.242901 1189 1903 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_28.v common 16.27 vpr 80.38 MiB 0.19 14924 -1 -1 8 1.34 -1 -1 41120 -1 -1 160 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82308 22 19 3511 3292 1 2001 209 18 18 324 mult_36 auto 42.2 MiB 1.16 13533 36169 7851 25670 2648 80.4 MiB 0.81 0.01 4.27196 -2716.32 -4.27196 4.27196 0.77 0.00311184 0.00273883 0.42534 0.377914 76 24958 37 7.94662e+06 5.32352e+06 1.43297e+06 4422.75 7.46 2.14707 1.86573 37464 369264 -1 20464 15 8254 14560 1239406 267344 4.27196 4.27196 -2808.92 -4.27196 0 0 1.77541e+06 5479.65 0.44 0.56 0.31 -1 -1 0.44 0.280802 0.252252 1221 1942 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_29.v common 18.06 vpr 81.39 MiB 0.22 15232 -1 -1 8 1.30 -1 -1 39884 -1 -1 168 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83348 22 19 3709 3473 1 2127 218 22 22 484 mult_36 auto 43.1 MiB 1.13 14602 39518 9141 27857 2520 81.4 MiB 0.88 0.01 4.64786 -2935.24 -4.64786 4.64786 1.18 0.00704858 0.00623722 0.475426 0.419795 72 26438 32 1.29336e+07 5.8273e+06 2.11301e+06 4365.72 7.81 2.31239 2.02149 55718 550791 -1 22616 14 8048 14017 1235710 262139 4.64786 4.64786 -3093.81 -4.64786 0 0 2.64603e+06 5467.00 0.71 0.56 0.43 -1 -1 0.71 0.282288 0.253979 1281 2049 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_30.v common 19.14 vpr 81.88 MiB 0.15 15520 -1 -1 8 1.29 -1 -1 40308 -1 -1 170 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83848 22 19 3767 3531 1 2168 220 22 22 484 mult_36 auto 43.8 MiB 1.21 14136 38674 7872 27997 2805 81.9 MiB 0.88 0.01 4.27196 -2917.4 -4.27196 4.27196 1.12 0.00731678 0.00647748 0.47014 0.414099 70 26124 28 1.29336e+07 5.85424e+06 2.06816e+06 4273.05 8.74 2.28486 1.99526 55234 538945 -1 23007 16 8701 15898 1397998 301821 4.52256 4.52256 -3212.81 -4.52256 0 0 2.60483e+06 5381.88 0.72 0.59 0.43 -1 -1 0.72 0.284851 0.256579 1309 2088 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_31.v common 22.22 vpr 82.26 MiB 0.23 15852 -1 -1 8 1.37 -1 -1 41832 -1 -1 177 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84232 22 19 3928 3675 1 2252 227 22 22 484 mult_36 auto 44.1 MiB 1.26 15955 41055 8830 29506 2719 82.3 MiB 0.91 0.01 4.64786 -3128.05 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success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87116 22 19 4387 4117 1 2459 249 22 22 484 mult_36 auto 47.0 MiB 1.40 17068 44097 9577 31491 3029 85.1 MiB 1.06 0.02 4.39726 -3405.93 -4.39726 4.39726 1.28 0.00891162 0.00796796 0.552844 0.487065 72 32512 35 1.29336e+07 6.62746e+06 2.11301e+06 4365.72 9.24 2.76456 2.41224 55718 550791 -1 26613 16 9838 17813 1459212 312343 4.39726 4.39726 -3610.82 -4.39726 0 0 2.64603e+06 5467.00 0.72 0.69 0.44 -1 -1 0.72 0.357191 0.320219 1521 2433 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_35.v common 25.69 vpr 85.73 MiB 0.22 17368 -1 -1 8 1.74 -1 -1 41464 -1 -1 208 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71656 22 19 1596 1445 1 1103 127 16 16 256 mult_36 auto 32.0 MiB 0.46 7348 16715 3403 11508 1804 70.0 MiB 0.39 0.01 14.8867 -546.505 -14.8867 14.8867 0.61 0.00383748 0.00350071 0.219016 0.199495 74 14383 47 6.45408e+06 3.45376e+06 1.07073e+06 4182.55 5.89 1.36261 1.21569 28864 273460 -1 12301 23 6003 11963 1225113 345124 13.7425 13.7425 -634.512 -13.7425 0 0 1.33358e+06 5209.30 0.32 0.48 0.25 -1 -1 0.32 0.195495 0.174987 615 1013 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_nopipe_20.v common 11.43 vpr 70.18 MiB 0.12 10476 -1 -1 11 0.71 -1 -1 37016 -1 -1 86 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71864 22 19 1656 1505 1 1131 133 16 16 256 mult_36 auto 32.3 MiB 0.50 7846 15049 2924 10833 1292 70.2 MiB 0.36 0.01 15.2396 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32313 17 14152 27191 2278999 483397 15.8336 15.8336 -1741.68 -15.8336 0 0 3.48632e+06 6052.64 0.95 0.91 0.59 -1 -1 0.95 0.399336 0.360201 1622 2741 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_nopipe_50.v common 36.12 vpr 86.42 MiB 0.20 17156 -1 -1 13 2.58 -1 -1 39324 -1 -1 212 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88496 22 19 4190 3784 1 2864 267 24 24 576 mult_36 auto 48.0 MiB 1.19 20719 47512 9780 35035 2697 84.8 MiB 1.16 0.02 16.5956 -1264.91 -16.5956 16.5956 1.47 0.0091073 0.00821237 0.577449 0.516343 80 37198 33 1.56141e+07 8.40006e+06 2.72095e+06 4723.87 22.19 4.055 3.58594 68798 719145 -1 32760 21 15413 30452 2837390 559448 15.403 15.403 -1780.07 -15.403 0 0 3.41546e+06 5929.62 0.95 1.10 0.58 -1 -1 0.95 0.474642 0.42666 1618 2748 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_nopipe_51.v common 30.24 vpr 89.34 MiB 0.32 17612 -1 -1 13 2.71 -1 -1 43504 -1 -1 216 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91480 22 19 4305 3882 1 2950 271 24 24 576 mult_36 auto 49.1 MiB 0.93 21440 51079 10257 37415 3407 86.6 MiB 1.27 0.02 16.714 -1309.99 -16.714 16.714 1.64 0.0119022 0.0109917 0.641407 0.572951 84 38763 39 1.56141e+07 8.45395e+06 2.84938e+06 4946.85 15.79 4.22066 3.74218 70522 759407 -1 32428 20 15429 30918 2308593 493125 15.4073 15.4073 -1971.83 -15.4073 0 0 3.60864e+06 6265.01 0.98 1.05 0.61 -1 -1 0.98 0.497871 0.448507 1666 2826 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_nopipe_52.v common 152.77 vpr 89.94 MiB 0.33 17640 -1 -1 13 2.82 -1 -1 39776 -1 -1 227 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92096 22 19 4363 3940 1 3005 282 24 24 576 mult_36 auto 49.3 MiB 1.21 21730 54798 11168 40568 3062 87.0 MiB 1.32 0.02 17.192 -1314.04 -17.192 17.192 1.52 0.0101418 0.00918253 0.66549 0.59325 76 43596 50 1.56141e+07 8.60214e+06 2.61600e+06 4541.67 137.76 7.36468 6.43712 67070 679911 -1 35261 20 17755 34183 2873298 612759 15.6501 15.6501 -1976.75 -15.6501 0 0 3.24203e+06 5628.53 0.91 1.24 0.60 -1 -1 0.91 0.56194 0.502549 1697 2865 -1 -1 -1 -1 -k6_frac_ripple_N8_22nm.xml fir_pipe_14.v common 7.16 vpr 70.80 MiB 0.07 10496 -1 -1 1 0.24 -1 -1 35480 -1 -1 81 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72496 22 19 1974 1653 1 1020 126 16 16 256 mult_36 auto 32.8 MiB 0.41 5707 14616 2612 9996 2008 70.8 MiB 0.35 0.01 4.27196 -1191.29 -4.27196 4.27196 0.57 0.00340592 0.00306896 0.179803 0.162328 60 9610 24 6.52434e+06 2.71588e+06 890343. 3477.90 2.78 0.899076 0.784711 27128 224764 -1 8185 17 3699 4190 423433 108714 4.39726 4.39726 -1140.75 -4.39726 0 0 1.11577e+06 4358.47 0.29 0.23 0.19 -1 -1 0.29 0.130495 0.117487 605 708 247 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_15.v common 20.60 vpr 71.64 MiB 0.08 10912 -1 -1 1 0.25 -1 -1 36976 -1 -1 88 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73356 22 19 2144 1789 1 1119 134 16 16 256 mult_36 auto 33.5 MiB 0.42 6078 18944 3753 12931 2260 71.6 MiB 0.44 0.01 4.22492 -1354.66 -4.22492 4.22492 0.67 0.0037036 0.00333617 0.21501 0.193696 52 14873 50 6.52434e+06 3.20969e+06 808720. 3159.06 15.69 1.74398 1.5257 25852 197779 -1 10045 20 4558 5394 572033 144141 4.52256 4.52256 -1396.34 -4.52256 0 0 1.00038e+06 3907.74 0.24 0.29 0.17 -1 -1 0.24 0.162087 0.143071 654 769 266 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_16.v common 8.25 vpr 71.93 MiB 0.11 10952 -1 -1 1 0.26 -1 -1 36912 -1 -1 91 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73652 22 19 2218 1846 1 1161 137 16 16 256 mult_36 auto 33.8 MiB 0.46 6793 19199 3651 12642 2906 71.9 MiB 0.46 0.01 4.29396 -1376.37 -4.29396 4.29396 0.55 0.00392286 0.00353131 0.222154 0.199557 56 12610 23 6.52434e+06 3.25161e+06 849745. 3319.32 3.35 1.08385 0.946389 26364 208198 -1 10765 21 4657 5400 648059 162428 4.52256 4.52256 -1436.25 -4.52256 0 0 1.04740e+06 4091.43 0.27 0.35 0.21 -1 -1 0.27 0.193181 0.170747 683 788 285 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_17.v common 9.50 vpr 73.33 MiB 0.13 11704 -1 -1 1 0.27 -1 -1 36580 -1 -1 103 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75088 22 19 2536 2130 1 1274 149 16 16 256 mult_36 auto 35.3 MiB 0.52 7563 19849 3721 13396 2732 73.3 MiB 0.51 0.01 4.29396 -1555.03 -4.29396 4.29396 0.60 0.00452081 0.00408155 0.252577 0.22717 54 14934 45 6.52434e+06 3.4193e+06 829453. 3240.05 4.40 1.45664 1.27771 26108 202796 -1 11220 19 5009 5929 575456 150599 4.29396 4.29396 -1585.29 -4.29396 0 0 1.02522e+06 4004.78 0.25 0.34 0.17 -1 -1 0.25 0.199787 0.177848 770 924 304 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_18.v common 10.95 vpr 74.29 MiB 0.12 11884 -1 -1 1 0.31 -1 -1 37120 -1 -1 107 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76068 22 19 2610 2187 1 1316 153 16 16 256 mult_36 auto 35.8 MiB 0.55 7580 22648 4139 15538 2971 74.3 MiB 0.55 0.01 4.22437 -1603.12 -4.22437 4.22437 0.58 0.00443525 0.00398183 0.273319 0.245768 56 14991 32 6.52434e+06 3.47519e+06 849745. 3319.32 5.86 1.41031 1.23076 26364 208198 -1 12118 24 5442 6385 763550 186400 5.14906 5.14906 -1681.4 -5.14906 0 0 1.04740e+06 4091.43 0.27 0.41 0.13 -1 -1 0.27 0.230417 0.203033 798 943 323 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_19.v common 10.76 vpr 75.11 MiB 0.17 12184 -1 -1 1 0.33 -1 -1 36724 -1 -1 113 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76916 22 19 2778 2321 1 1410 160 16 16 256 mult_36 auto 36.8 MiB 0.57 8169 22294 4065 14927 3302 75.1 MiB 0.53 0.01 4.2304 -1681.23 -4.2304 4.2304 0.58 0.0045314 0.00405318 0.256982 0.22945 58 14770 47 6.52434e+06 3.95503e+06 871168. 3403.00 5.40 1.56264 1.36024 26872 219187 -1 12035 18 5167 5841 646056 165802 4.29396 4.29396 -1705.82 -4.29396 0 0 1.09288e+06 4269.05 0.26 0.34 0.19 -1 -1 0.26 0.194726 0.171914 846 1002 342 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_20.v common 9.91 vpr 75.12 MiB 0.13 12376 -1 -1 1 0.35 -1 -1 37004 -1 -1 118 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76928 22 19 2852 2378 1 1454 165 16 16 256 mult_36 auto 37.3 MiB 0.56 8808 21861 3843 15034 2984 75.1 MiB 0.55 0.01 4.28986 -1739.48 -4.28986 4.28986 0.61 0.00497001 0.00446513 0.264268 0.23753 60 14824 27 6.52434e+06 4.0249e+06 890343. 3477.90 4.57 1.45122 1.26718 27128 224764 -1 12480 16 5276 6100 595745 151457 4.41926 4.41926 -1762.84 -4.41926 0 0 1.11577e+06 4358.47 0.28 0.34 0.20 -1 -1 0.28 0.194343 0.172377 875 1021 361 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_21.v common 11.49 vpr 76.05 MiB 0.15 12808 -1 -1 1 0.34 -1 -1 37824 -1 -1 122 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77880 22 19 3057 2549 1 1559 169 16 16 256 mult_36 auto 38.3 MiB 0.64 9015 24920 4571 15619 4730 76.1 MiB 0.64 0.01 4.20237 -1905.04 -4.20237 4.20237 0.58 0.00554434 0.00500669 0.309355 0.276796 60 16024 44 6.52434e+06 4.0808e+06 890343. 3477.90 5.69 1.73434 1.51865 27128 224764 -1 13134 16 5600 6594 636756 160290 4.29396 4.29396 -1928.97 -4.29396 0 0 1.11577e+06 4358.47 0.28 0.36 0.19 -1 -1 0.28 0.207694 0.184735 932 1099 380 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_22.v common 12.10 vpr 76.48 MiB 0.10 12960 -1 -1 1 0.35 -1 -1 37920 -1 -1 125 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78316 22 19 3131 2606 1 1599 172 16 16 256 mult_36 auto 38.8 MiB 0.53 9644 27896 4964 18195 4737 76.5 MiB 0.74 0.01 4.09962 -1964.96 -4.09962 4.09962 0.57 0.00549947 0.00489115 0.342589 0.303885 66 17711 35 6.52434e+06 4.12272e+06 974584. 3806.97 6.45 1.71183 1.49596 28148 247068 -1 13707 17 5831 6659 781116 185151 4.29396 4.29396 -1959.31 -4.29396 0 0 1.22072e+06 4768.46 0.31 0.39 0.19 -1 -1 0.31 0.215751 0.191625 961 1118 399 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_23.v common 13.73 vpr 77.29 MiB 0.17 13308 -1 -1 1 0.39 -1 -1 37936 -1 -1 133 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79140 22 19 3301 2742 1 1700 181 18 18 324 mult_36 auto 39.5 MiB 0.72 10087 30330 5799 21301 3230 77.3 MiB 0.74 0.01 4.29396 -2075.2 -4.29396 4.29396 0.77 0.00650178 0.00598133 0.346423 0.313697 60 18320 28 8.04299e+06 4.63052e+06 1.16833e+06 3605.96 7.06 1.72603 1.51148 35004 297736 -1 15010 17 6849 7695 873963 206522 4.29396 4.29396 -2095.97 -4.29396 0 0 1.46313e+06 4515.82 0.40 0.41 0.25 -1 -1 0.40 0.220321 0.195312 1012 1179 418 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_24.v common 13.85 vpr 77.54 MiB 0.13 13392 -1 -1 1 0.41 -1 -1 38108 -1 -1 137 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79396 22 19 3375 2799 1 1743 185 18 18 324 mult_36 auto 39.8 MiB 0.70 10300 29115 5219 20674 3222 77.5 MiB 0.80 0.01 4.22437 -2073.88 -4.22437 4.22437 0.77 0.006131 0.00553331 0.354774 0.317073 58 18565 31 8.04299e+06 4.68641e+06 1.14310e+06 3528.09 7.15 1.79694 1.56807 34680 290288 -1 15595 17 6816 7782 901255 220455 4.29396 4.29396 -2160.36 -4.29396 0 0 1.43297e+06 4422.75 0.36 0.44 0.26 -1 -1 0.36 0.237466 0.211355 1041 1198 437 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_25.v common 13.85 vpr 78.52 MiB 0.13 13888 -1 -1 1 0.40 -1 -1 38236 -1 -1 146 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80404 22 19 3615 3005 1 1847 194 18 18 324 mult_36 auto 40.8 MiB 0.67 10975 29927 5204 21640 3083 78.5 MiB 0.78 0.01 4.29396 -2273.15 -4.29396 4.29396 0.76 0.006101 0.00546094 0.361338 0.323248 58 20078 36 8.04299e+06 4.81218e+06 1.14310e+06 3528.09 7.25 1.94915 1.69787 34680 290288 -1 16168 17 7089 8219 904291 224983 4.41926 4.41926 -2410.63 -4.41926 0 0 1.43297e+06 4422.75 0.36 0.46 0.24 -1 -1 0.36 0.258436 0.230808 1107 1293 456 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_26.v common 14.51 vpr 79.02 MiB 0.09 14076 -1 -1 1 0.34 -1 -1 38412 -1 -1 148 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80916 22 19 3689 3062 1 1888 196 18 18 324 mult_36 auto 41.4 MiB 0.77 10816 33767 6403 23789 3575 79.0 MiB 0.90 0.01 4.09962 -2289.16 -4.09962 4.09962 0.77 0.00666653 0.00592456 0.405095 0.359897 60 19765 47 8.04299e+06 4.84013e+06 1.16833e+06 3605.96 7.57 2.1649 1.88473 35004 297736 -1 15783 16 6853 7919 833754 202360 4.41926 4.41926 -2402.93 -4.41926 0 0 1.46313e+06 4515.82 0.37 0.43 0.25 -1 -1 0.37 0.24325 0.216254 1135 1312 475 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_27.v common 12.41 vpr 80.23 MiB 0.18 14388 -1 -1 1 0.41 -1 -1 38456 -1 -1 156 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82160 22 19 3871 3210 1 1998 205 18 18 324 mult_36 auto 42.4 MiB 0.80 12132 28593 4296 20787 3510 80.2 MiB 0.74 0.01 4.41926 -2393.12 -4.41926 4.41926 0.77 0.006481 0.00579771 0.338432 0.302298 64 20586 19 8.04299e+06 5.34793e+06 1.23838e+06 3822.15 5.24 1.78906 1.56837 35972 318676 -1 17280 19 7116 8295 869286 210992 4.41926 4.41926 -2474.76 -4.41926 0 0 1.56068e+06 4816.91 0.44 0.51 0.30 -1 -1 0.44 0.295813 0.263743 1191 1385 494 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_28.v common 15.94 vpr 80.36 MiB 0.28 14584 -1 -1 1 0.47 -1 -1 38476 -1 -1 160 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82292 22 19 3945 3267 1 2043 209 18 18 324 mult_36 auto 42.6 MiB 0.83 12721 34929 5952 24376 4601 80.4 MiB 0.89 0.01 4.26697 -2429.16 -4.26697 4.26697 0.78 0.00701006 0.00631112 0.406399 0.363637 60 21797 48 8.04299e+06 5.40382e+06 1.16833e+06 3605.96 8.27 2.30836 2.01074 35004 297736 -1 18182 20 8118 9346 1020381 253908 4.41926 4.41926 -2516.38 -4.41926 0 0 1.46313e+06 4515.82 0.38 0.63 0.27 -1 -1 0.38 0.375108 0.337767 1219 1404 513 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_29.v common 17.64 vpr 81.52 MiB 0.12 15092 -1 -1 1 0.48 -1 -1 39648 -1 -1 170 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83480 22 19 4159 3447 1 2157 220 22 22 484 mult_36 auto 43.7 MiB 0.84 13597 41989 8196 30469 3324 81.5 MiB 1.05 0.02 4.16866 -2687.48 -4.16866 4.16866 1.22 0.00719836 0.00646222 0.481623 0.429453 56 27289 30 1.30842e+07 5.93957e+06 1.71605e+06 3545.56 8.95 2.22671 1.94498 51606 428054 -1 21919 20 9434 11001 1516906 343088 4.52256 4.52256 -2855.36 -4.52256 0 0 2.11301e+06 4365.72 0.56 0.39 0.34 -1 -1 0.56 0.187846 0.168815 1283 1491 532 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_30.v common 20.20 vpr 82.89 MiB 0.20 15032 -1 -1 1 0.60 -1 -1 40776 -1 -1 173 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84880 22 19 4233 3504 1 2198 223 22 22 484 mult_36 auto 44.3 MiB 0.85 14316 43487 8493 30718 4276 82.9 MiB 1.12 0.02 4.41926 -2750.54 -4.41926 4.41926 1.22 0.00742763 0.00666077 0.497987 0.444103 58 27441 46 1.30842e+07 5.98149e+06 1.75961e+06 3635.55 10.85 2.43679 2.13088 52570 450426 -1 21701 17 9112 10561 1278143 292476 4.54456 4.54456 -2870.39 -4.54456 0 0 2.20457e+06 4554.90 0.61 0.57 0.36 -1 -1 0.61 0.303403 0.26981 1311 1510 551 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_31.v common 16.67 vpr 83.57 MiB 0.23 15640 -1 -1 1 0.53 -1 -1 41024 -1 -1 179 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85576 22 19 4410 3647 1 2304 229 22 22 484 mult_36 auto 44.9 MiB 0.88 14559 42929 8301 31079 3549 83.6 MiB 1.12 0.02 4.54456 -2849.05 -4.54456 4.54456 1.21 0.00745103 0.00666239 0.502234 0.448841 60 26138 29 1.30842e+07 6.06533e+06 1.79840e+06 3715.71 7.35 2.34135 2.05057 53054 462096 -1 21367 18 8865 10303 1128192 264808 4.54456 4.54456 -2991.12 -4.54456 0 0 2.25108e+06 4650.99 0.62 0.59 0.39 -1 -1 0.62 0.318889 0.285441 1363 1578 570 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_32.v common 20.69 vpr 82.85 MiB 0.19 15572 -1 -1 1 0.54 -1 -1 40572 -1 -1 183 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84836 22 19 4484 3704 1 2346 233 22 22 484 mult_36 auto 45.1 MiB 0.91 14169 51069 10204 36498 4367 82.8 MiB 1.24 0.02 4.35562 -2870.14 -4.35562 4.35562 1.18 0.00727166 0.00648461 0.540705 0.481056 58 28562 42 1.30842e+07 6.12123e+06 1.75961e+06 3635.55 10.86 2.61612 2.28074 52570 450426 -1 21935 18 9198 10981 1225293 282955 4.41926 4.41926 -3046.59 -4.41926 0 0 2.20457e+06 4554.90 0.62 0.59 0.32 -1 -1 0.62 0.310706 0.275736 1393 1597 589 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_33.v common 24.20 vpr 85.52 MiB 0.23 16688 -1 -1 1 0.56 -1 -1 41628 -1 -1 196 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87572 22 19 4843 4029 1 2462 247 22 22 484 mult_36 auto 47.0 MiB 1.13 15624 49783 9117 36437 4229 85.5 MiB 1.21 0.02 4.64786 -3017.99 -4.64786 4.64786 1.24 0.00761602 0.00676614 0.533935 0.474376 60 29459 48 1.30842e+07 6.6989e+06 1.79840e+06 3715.71 14.26 2.84822 2.48391 53054 462096 -1 23118 17 9322 10866 1279018 283870 4.54456 4.54456 -3177.97 -4.54456 0 0 2.25108e+06 4650.99 0.61 0.62 0.46 -1 -1 0.61 0.353908 0.31735 1490 1756 608 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_34.v common 20.31 vpr 84.88 MiB 0.26 16896 -1 -1 1 0.63 -1 -1 41516 -1 -1 199 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86916 22 19 4917 4086 1 2503 250 22 22 484 mult_36 auto 47.4 MiB 0.95 16182 52192 10276 36322 5594 84.9 MiB 1.28 0.02 4.41926 -3092.45 -4.41926 4.41926 1.23 0.00760482 0.00676556 0.564061 0.500769 64 28538 36 1.30842e+07 6.74082e+06 1.90554e+06 3937.06 10.13 3.04467 2.68442 54502 494576 -1 22667 18 8811 10602 1146289 263961 4.54456 4.54456 -3188.99 -4.54456 0 0 2.40101e+06 4960.76 0.65 0.62 0.41 -1 -1 0.65 0.351193 0.312295 1519 1775 627 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_35.v common 21.36 vpr 85.83 MiB 0.32 17128 -1 -1 1 0.63 -1 -1 41764 -1 -1 207 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87888 22 19 5093 4228 1 2606 258 22 22 484 mult_36 auto 48.2 MiB 0.95 15281 55265 10444 39810 5011 85.8 MiB 1.34 0.02 4.16866 -3231.81 -4.16866 4.16866 1.23 0.00806113 0.00717252 0.590696 0.524331 60 28985 37 1.30842e+07 6.85261e+06 1.79840e+06 3715.71 11.05 2.9251 2.55373 53054 462096 -1 22720 20 9865 11925 1244020 294578 4.41926 4.41926 -3325.32 -4.41926 0 0 2.25108e+06 4650.99 0.64 0.69 0.37 -1 -1 0.64 0.399047 0.354548 1572 1842 646 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_36.v common 18.14 vpr 86.34 MiB 0.17 17204 -1 -1 1 0.65 -1 -1 41776 -1 -1 209 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88416 22 19 5167 4285 1 2653 260 22 22 484 mult_36 auto 48.8 MiB 0.98 16606 54145 10648 38527 4970 86.3 MiB 1.36 0.02 4.16866 -3259.63 -4.16866 4.16866 1.19 0.00868234 0.00775776 0.586893 0.521739 64 29957 28 1.30842e+07 6.88056e+06 1.90554e+06 3937.06 8.19 2.67123 2.33119 54502 494576 -1 23683 18 9902 11325 1259385 289004 4.41926 4.41926 -3287.54 -4.41926 0 0 2.40101e+06 4960.76 0.61 0.58 0.39 -1 -1 0.61 0.331583 0.292623 1600 1861 665 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_37.v common 21.09 vpr 88.22 MiB 0.26 17588 -1 -1 1 0.67 -1 -1 40772 -1 -1 218 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90340 22 19 5380 4464 1 2755 270 24 24 576 mult_36 auto 49.9 MiB 1.06 18567 56078 10962 40406 4710 88.2 MiB 1.45 0.02 4.41926 -3517.74 -4.41926 4.41926 1.46 0.011845 0.0108667 0.625669 0.556627 62 34089 42 1.57908e+07 7.40233e+06 2.19658e+06 3813.51 10.12 3.24992 2.85968 63306 560109 -1 25982 17 10013 11925 1290386 299725 4.54456 4.54456 -3709.06 -4.54456 0 0 2.72095e+06 4723.87 0.70 0.60 0.43 -1 -1 0.70 0.335585 0.296844 1662 1947 684 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_38.v common 23.46 vpr 87.28 MiB 0.18 17932 -1 -1 1 0.70 -1 -1 42356 -1 -1 220 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89372 22 19 5454 4521 1 2802 272 24 24 576 mult_36 auto 49.6 MiB 1.08 18582 51370 9929 37950 3491 87.3 MiB 1.41 0.02 4.41926 -3447.93 -4.41926 4.41926 1.47 0.00885871 0.00790343 0.606093 0.53869 64 34209 36 1.57908e+07 7.43028e+06 2.26035e+06 3924.22 12.06 2.88108 2.51729 64454 586630 -1 26870 18 10485 12283 1454697 328137 4.54456 4.54456 -3636.25 -4.54456 0 0 2.84938e+06 4946.85 0.81 0.72 0.48 -1 -1 0.81 0.391969 0.349886 1690 1966 703 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_39.v common 23.62 vpr 88.21 MiB 0.29 18256 -1 -1 1 0.71 -1 -1 40212 -1 -1 228 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90324 22 19 5629 4662 1 2909 280 24 24 576 mult_36 auto 50.9 MiB 1.08 18512 58840 11287 42675 4878 88.2 MiB 1.50 0.02 4.53661 -3591.01 -4.53661 4.53661 1.51 0.0104965 0.0094672 0.651336 0.579977 64 33376 33 1.57908e+07 7.54207e+06 2.26035e+06 3924.22 11.88 3.18095 2.78182 64454 586630 -1 26570 18 10607 12773 1398491 323531 4.52256 4.52256 -3729.32 -4.52256 0 0 2.84938e+06 4946.85 0.82 0.72 0.47 -1 -1 0.82 0.405198 0.361638 1742 2032 722 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_40.v common 24.07 vpr 89.79 MiB 0.34 18348 -1 -1 1 0.68 -1 -1 42284 -1 -1 232 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91944 22 19 5703 4719 1 2951 284 24 24 576 mult_36 auto 51.8 MiB 1.09 19527 61862 12354 44168 5340 89.8 MiB 1.55 0.02 4.51758 -3660.42 -4.51758 4.51758 1.41 0.00911902 0.00811392 0.654527 0.579497 64 35385 33 1.57908e+07 7.59797e+06 2.26035e+06 3924.22 11.97 3.12936 2.74636 64454 586630 -1 27678 18 10750 12796 1471921 331561 4.64786 4.64786 -3839.37 -4.64786 0 0 2.84938e+06 4946.85 0.83 0.79 0.55 -1 -1 0.83 0.438235 0.393209 1771 2051 741 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_41.v common 24.48 vpr 89.66 MiB 0.21 18724 -1 -1 1 0.84 -1 -1 41504 -1 -1 240 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91816 22 19 5950 4932 1 3065 293 24 24 576 mult_36 auto 52.4 MiB 1.12 20313 68333 13912 49003 5418 89.7 MiB 1.76 0.02 4.35562 -3781.12 -4.35562 4.35562 1.49 0.0100927 0.00897853 0.748474 0.663187 64 37437 47 1.57908e+07 8.10576e+06 2.26035e+06 3924.22 12.19 3.44676 2.99524 64454 586630 -1 29393 20 11515 13868 1578948 357275 4.54456 4.54456 -4027.56 -4.54456 0 0 2.84938e+06 4946.85 0.77 0.81 0.47 -1 -1 0.77 0.448202 0.39727 1841 2153 760 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_42.v common 25.47 vpr 92.35 MiB 0.23 18988 -1 -1 1 0.86 -1 -1 42916 -1 -1 242 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94564 22 19 6024 4989 1 3106 295 24 24 576 mult_36 auto 53.2 MiB 1.15 21018 65041 12819 46780 5442 90.3 MiB 1.67 0.02 4.54456 -3823.47 -4.54456 4.54456 1.51 0.0101508 0.00906076 0.715915 0.636736 64 36534 49 1.57908e+07 8.13371e+06 2.26035e+06 3924.22 13.19 3.56747 3.11957 64454 586630 -1 29646 18 11267 13244 1541469 352337 4.66986 4.66986 -3955.02 -4.66986 0 0 2.84938e+06 4946.85 0.75 0.75 0.46 -1 -1 0.75 0.430993 0.383901 1869 2172 779 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_43.v common 25.12 vpr 91.39 MiB 0.31 19256 -1 -1 1 0.89 -1 -1 43264 -1 -1 250 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93588 22 19 6198 5129 1 3209 303 24 24 576 mult_36 auto 54.3 MiB 1.22 22338 66408 13114 47625 5669 91.4 MiB 1.76 0.03 4.47497 -4072.8 -4.47497 4.47497 1.50 0.0104487 0.00936437 0.738522 0.655007 68 37694 34 1.57908e+07 8.2455e+06 2.39371e+06 4155.74 12.43 3.35506 2.92455 65606 615345 -1 30383 15 11489 13385 1484469 334786 4.66986 4.66986 -4189.73 -4.66986 0 0 2.98162e+06 5176.42 1.02 0.78 0.49 -1 -1 1.02 0.421175 0.378984 1921 2237 798 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_44.v common 25.17 vpr 94.43 MiB 0.17 19552 -1 -1 1 0.85 -1 -1 43196 -1 -1 253 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 96696 22 19 6272 5186 1 3253 306 24 24 576 mult_36 auto 54.2 MiB 1.23 22629 67256 12828 47647 6781 91.3 MiB 1.75 0.03 4.41926 -4066.4 -4.41926 4.41926 1.56 0.0105256 0.0093916 0.741281 0.658657 70 37350 43 1.57908e+07 8.28742e+06 2.45377e+06 4260.01 12.42 3.6164 3.15387 66754 640332 -1 30782 20 11655 13506 1570135 362351 4.41926 4.41926 -4119.98 -4.41926 0 0 3.09179e+06 5367.68 0.82 0.82 0.51 -1 -1 0.82 0.468682 0.416096 1949 2256 817 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_45.v common 23.85 vpr 92.27 MiB 0.33 20028 -1 -1 1 0.90 -1 -1 43716 -1 -1 262 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94488 22 19 6485 5365 1 3362 316 24 24 576 mult_36 auto 55.3 MiB 1.26 21577 68041 12652 49574 5815 92.3 MiB 1.82 0.03 4.34967 -4219.28 -4.34967 4.34967 1.55 0.010752 0.00961779 0.738639 0.650742 72 36507 46 1.57908e+07 8.80919e+06 2.50747e+06 4353.24 10.81 3.77641 3.29091 67330 654343 -1 29810 22 11462 13137 1601544 361852 4.39726 4.39726 -4238.31 -4.39726 0 0 3.14081e+06 5452.80 0.85 0.91 0.52 -1 -1 0.85 0.527897 0.467341 2011 2342 836 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_46.v common 26.61 vpr 98.11 MiB 0.34 20028 -1 -1 1 0.87 -1 -1 43880 -1 -1 266 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100468 22 19 6559 5422 1 3404 320 24 24 576 mult_36 auto 55.5 MiB 1.28 24101 72524 13138 53102 6284 92.7 MiB 2.08 0.03 4.66986 -4291.45 -4.66986 4.66986 1.46 0.0119672 0.0107794 0.83727 0.749668 68 40255 40 1.57908e+07 8.86508e+06 2.39371e+06 4155.74 13.34 3.88625 3.40879 65606 615345 -1 32521 18 12015 14089 1546690 340905 4.66986 4.66986 -4364.43 -4.66986 0 0 2.98162e+06 5176.42 0.79 0.84 0.52 -1 -1 0.79 0.471209 0.420824 2040 2361 855 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_47.v common 25.66 vpr 96.38 MiB 0.26 20328 -1 -1 1 0.98 -1 -1 44612 -1 -1 273 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 98692 22 19 6735 5564 1 3511 327 24 24 576 mult_36 auto 56.6 MiB 1.32 22785 72391 13683 52096 6612 93.7 MiB 2.12 0.03 4.36967 -4379.74 -4.36967 4.36967 1.44 0.0126992 0.011479 0.885818 0.786761 66 39572 35 1.57908e+07 8.9629e+06 2.33135e+06 4047.49 12.30 3.95827 3.45851 65030 601923 -1 31611 19 12384 14268 1564989 359786 4.54456 4.54456 -4464.94 -4.54456 0 0 2.91907e+06 5067.82 0.82 0.86 0.50 -1 -1 0.82 0.496205 0.441897 2092 2428 874 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_48.v common 27.56 vpr 98.24 MiB 0.39 20536 -1 -1 1 1.04 -1 -1 44100 -1 -1 276 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100596 22 19 6809 5621 1 3555 330 24 24 576 mult_36 auto 57.0 MiB 1.36 23066 80060 16107 55507 8446 94.0 MiB 2.24 0.03 4.29396 -4332.56 -4.29396 4.29396 1.49 0.010321 0.00913554 0.900016 0.796321 70 39582 34 1.57908e+07 9.00482e+06 2.45377e+06 4260.01 13.48 3.67756 3.19309 66754 640332 -1 32506 18 12951 15266 1774464 412111 4.41926 4.41926 -4460.37 -4.41926 0 0 3.09179e+06 5367.68 0.84 0.87 0.54 -1 -1 0.84 0.478592 0.424893 2121 2447 893 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_49.v common 27.16 vpr 97.51 MiB 0.18 21252 -1 -1 1 1.04 -1 -1 44416 -1 -1 287 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 99852 22 19 7094 5872 1 3669 342 24 24 576 mult_36 auto 58.0 MiB 1.42 24245 82797 16885 57326 8586 95.1 MiB 2.25 0.03 4.52256 -4714.45 -4.52256 4.52256 1.44 0.0118561 0.0106259 0.900369 0.79678 72 41230 32 1.57908e+07 9.55454e+06 2.50747e+06 4353.24 13.37 3.97004 3.4626 67330 654343 -1 33608 16 12552 14465 1746432 385070 4.64786 4.64786 -4951.91 -4.64786 0 0 3.14081e+06 5452.80 0.85 0.85 0.53 -1 -1 0.85 0.455975 0.406164 2200 2569 912 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_50.v common 26.03 vpr 100.95 MiB 0.21 21304 -1 -1 1 1.04 -1 -1 44288 -1 -1 290 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 103372 22 19 7168 5929 1 3710 345 24 24 576 mult_36 auto 58.4 MiB 1.47 24589 80139 15697 56982 7460 95.4 MiB 2.13 0.03 4.41926 -4634.65 -4.41926 4.41926 1.48 0.0119433 0.010454 0.836358 0.737133 70 40446 44 1.57908e+07 9.59646e+06 2.45377e+06 4260.01 12.09 4.00842 3.47817 66754 640332 -1 34146 18 13413 15667 1907396 427492 4.54456 4.54456 -4822.29 -4.54456 0 0 3.09179e+06 5367.68 0.89 1.01 0.52 -1 -1 0.89 0.535964 0.47839 2229 2588 931 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_51.v common 28.63 vpr 99.47 MiB 0.37 21664 -1 -1 1 1.11 -1 -1 44756 -1 -1 297 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 101856 22 19 7344 6071 1 3814 352 24 24 576 mult_36 auto 59.4 MiB 1.64 25956 86050 17957 59580 8513 96.4 MiB 2.35 0.04 4.54456 -4790.18 -4.54456 4.54456 1.49 0.0162424 0.0148599 0.946895 0.838694 72 43615 28 1.57908e+07 9.69428e+06 2.50747e+06 4353.24 13.90 3.95891 3.45177 67330 654343 -1 35657 17 13386 15768 1879694 426603 4.64786 4.64786 -4925.15 -4.64786 0 0 3.14081e+06 5452.80 0.86 0.89 0.52 -1 -1 0.86 0.48718 0.433407 2282 2655 950 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_52.v common 25.95 vpr 99.39 MiB 0.28 21732 -1 -1 1 1.01 -1 -1 45068 -1 -1 301 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 101776 22 19 7418 6128 1 3859 356 24 24 576 mult_36 auto 60.1 MiB 1.47 27555 81060 16090 57104 7866 99.1 MiB 2.14 0.03 4.54456 -4802.82 -4.54456 4.54456 1.43 0.0120698 0.0107753 0.842413 0.740695 76 44587 45 1.57908e+07 9.75017e+06 2.61600e+06 4541.67 12.08 4.15845 3.61183 68478 680951 -1 37419 17 14263 16730 1964169 440460 4.52256 4.52256 -5062.61 -4.52256 0 0 3.24203e+06 5628.53 0.95 0.95 0.52 -1 -1 0.95 0.502544 0.447268 2310 2674 969 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_14.v common 8.81 vpr 67.31 MiB 0.13 9440 -1 -1 1 0.12 -1 -1 34712 -1 -1 58 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68924 22 19 1246 925 1 732 103 16 16 256 mult_36 auto 28.9 MiB 2.74 3886 14081 3199 8271 2611 67.3 MiB 0.31 0.01 8.43746 -386.648 -8.43746 8.43746 0.59 0.00249884 0.0022961 0.153735 0.141049 44 8107 32 6.52434e+06 2.39448e+06 686998. 2683.59 2.43 0.551985 0.492102 24576 170172 -1 6188 24 5707 6417 667481 172985 7.87084 7.87084 -462.711 -7.87084 0 0 871168. 3403.00 0.21 0.29 0.15 -1 -1 0.21 0.128358 0.11408 421 344 247 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_15.v common 9.80 vpr 67.93 MiB 0.10 9540 -1 -1 1 0.17 -1 -1 35144 -1 -1 61 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69560 22 19 1344 989 1 793 107 16 16 256 mult_36 auto 29.6 MiB 2.03 4415 16299 3732 8915 3652 67.9 MiB 0.37 0.01 8.61109 -402.505 -8.61109 8.61109 0.58 0.00265723 0.00243955 0.189356 0.173645 44 9925 41 6.52434e+06 2.8324e+06 686998. 2683.59 3.88 0.892944 0.7947 24576 170172 -1 7024 25 6220 7095 698142 184212 8.45004 8.45004 -463.679 -8.45004 0 0 871168. 3403.00 0.22 0.34 0.15 -1 -1 0.22 0.155405 0.14074 453 369 266 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_16.v common 11.29 vpr 68.10 MiB 0.10 9672 -1 -1 1 0.19 -1 -1 35136 -1 -1 65 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69736 22 19 1418 1046 1 832 111 16 16 256 mult_36 auto 30.1 MiB 2.96 4724 16869 4045 10706 2118 68.1 MiB 0.44 0.01 8.43651 -410.772 -8.43651 8.43651 0.62 0.0028132 0.00257563 0.200536 0.183658 48 9176 31 6.52434e+06 2.88829e+06 755748. 2952.14 4.31 0.897273 0.796679 25088 180500 -1 7305 24 6692 7397 851322 211567 7.80584 7.80584 -467.143 -7.80584 0 0 916467. 3579.95 0.22 0.34 0.17 -1 -1 0.22 0.143449 0.127696 481 388 285 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_17.v common 10.58 vpr 68.59 MiB 0.10 10212 -1 -1 1 0.15 -1 -1 35340 -1 -1 71 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70240 22 19 1518 1112 1 896 117 16 16 256 mult_36 auto 30.6 MiB 2.67 5238 17563 3887 11404 2272 68.6 MiB 0.46 0.01 9.04171 -433.063 -9.04171 9.04171 0.56 0.00413444 0.00385519 0.205719 0.187964 48 10177 28 6.52434e+06 2.97214e+06 755748. 2952.14 3.95 0.881042 0.782615 25088 180500 -1 8176 22 6890 7606 917926 237751 8.68028 8.68028 -493.626 -8.68028 0 0 916467. 3579.95 0.22 0.32 0.18 -1 -1 0.22 0.135487 0.121653 514 415 304 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_18.v common 13.14 vpr 68.97 MiB 0.12 10304 -1 -1 1 0.21 -1 -1 34948 -1 -1 74 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70628 22 19 1592 1169 1 934 120 16 16 256 mult_36 auto 30.9 MiB 3.32 5243 15755 3475 9888 2392 69.0 MiB 0.39 0.01 9.04775 -490.252 -9.04775 9.04775 0.55 0.00310114 0.00281456 0.183321 0.167683 48 11232 37 6.52434e+06 3.01406e+06 755748. 2952.14 5.98 0.941072 0.833617 25088 180500 -1 8633 23 7736 8750 1034775 249786 8.80158 8.80158 -540.639 -8.80158 0 0 916467. 3579.95 0.23 0.39 0.17 -1 -1 0.23 0.152496 0.136913 542 434 323 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_19.v common 11.51 vpr 69.29 MiB 0.11 10692 -1 -1 1 0.20 -1 -1 35236 -1 -1 79 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70956 22 19 1688 1231 1 994 126 16 16 256 mult_36 auto 31.4 MiB 2.90 5618 18711 3986 11280 3445 69.3 MiB 0.48 0.01 9.18492 -482.658 -9.18492 9.18492 0.58 0.00325551 0.00298378 0.223503 0.20475 52 10842 44 6.52434e+06 3.47993e+06 808720. 3159.06 4.48 1.093 0.971846 25852 197779 -1 8271 22 6752 7535 845938 215127 8.23108 8.23108 -551.85 -8.23108 0 0 1.00038e+06 3907.74 0.25 0.33 0.17 -1 -1 0.25 0.150906 0.134461 573 457 342 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_20.v common 12.15 vpr 69.87 MiB 0.12 10752 -1 -1 1 0.22 -1 -1 35508 -1 -1 81 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71544 22 19 1762 1288 1 1031 128 16 16 256 mult_36 auto 31.8 MiB 3.48 6535 19770 4199 12093 3478 69.9 MiB 0.50 0.01 9.33493 -488.07 -9.33493 9.33493 0.58 0.00393902 0.00361618 0.226774 0.206643 48 12219 33 6.52434e+06 3.50787e+06 755748. 2952.14 4.48 1.04501 0.925176 25088 180500 -1 9898 22 7504 8327 1040791 265119 8.96258 8.96258 -581.233 -8.96258 0 0 916467. 3579.95 0.23 0.39 0.16 -1 -1 0.23 0.156731 0.139761 601 476 361 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_21.v common 12.92 vpr 70.16 MiB 0.14 10972 -1 -1 1 0.23 -1 -1 35944 -1 -1 85 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71844 22 19 1859 1351 1 1093 132 16 16 256 mult_36 auto 32.1 MiB 3.48 6792 15542 2589 10760 2193 70.2 MiB 0.41 0.01 9.32007 -525.351 -9.32007 9.32007 0.61 0.00348662 0.00319064 0.180881 0.165392 52 13770 38 6.52434e+06 3.56377e+06 808720. 3159.06 5.06 1.13318 1.00524 25852 197779 -1 10144 26 8345 9522 1119762 274391 8.76698 8.76698 -629.803 -8.76698 0 0 1.00038e+06 3907.74 0.25 0.48 0.17 -1 -1 0.25 0.200326 0.179147 632 500 380 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_22.v common 12.79 vpr 70.51 MiB 0.09 11036 -1 -1 1 0.25 -1 -1 35780 -1 -1 90 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72200 22 19 1933 1408 1 1131 137 16 16 256 mult_36 auto 32.7 MiB 4.09 7153 18846 3425 12209 3212 70.5 MiB 0.49 0.01 9.31293 -505.408 -9.31293 9.31293 0.60 0.00360585 0.00328582 0.209128 0.190526 56 11937 28 6.52434e+06 3.63364e+06 849745. 3319.32 4.42 1.06006 0.938823 26364 208198 -1 10148 23 7351 8481 910874 235258 8.45968 8.45968 -707.138 -8.45968 0 0 1.04740e+06 4091.43 0.26 0.39 0.18 -1 -1 0.26 0.181491 0.161447 661 519 399 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_23.v common 16.10 vpr 71.06 MiB 0.18 11408 -1 -1 1 0.25 -1 -1 36016 -1 -1 94 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72768 22 19 2031 1472 1 1193 142 18 18 324 mult_36 auto 33.2 MiB 3.90 7470 21602 4449 14485 2668 71.1 MiB 0.53 0.01 9.36191 -552.695 -9.36191 9.36191 0.79 0.00376507 0.00343241 0.238367 0.217452 50 14673 42 8.04299e+06 4.08553e+06 1.03391e+06 3191.07 7.13 1.27319 1.12709 32744 246704 -1 11207 23 8954 10315 1227188 301096 8.80128 8.80128 -805.076 -8.80128 0 0 1.23838e+06 3822.15 0.31 0.48 0.22 -1 -1 0.31 0.19755 0.176261 693 544 418 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_24.v common 15.40 vpr 71.33 MiB 0.11 11492 -1 -1 1 0.23 -1 -1 36264 -1 -1 97 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73040 22 19 2105 1529 1 1232 145 18 18 324 mult_36 auto 33.3 MiB 4.14 7507 21425 4200 14405 2820 71.3 MiB 0.55 0.01 9.44155 -614.321 -9.44155 9.44155 0.78 0.0038934 0.00354525 0.238346 0.21681 50 14797 40 8.04299e+06 4.12745e+06 1.03391e+06 3191.07 6.30 1.24287 1.0989 32744 246704 -1 11508 23 9004 10353 1255675 301759 8.51938 8.51938 -832.526 -8.51938 0 0 1.23838e+06 3822.15 0.31 0.44 0.21 -1 -1 0.31 0.185596 0.165494 721 563 437 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_25.v common 14.99 vpr 71.78 MiB 0.08 11932 -1 -1 1 0.27 -1 -1 36564 -1 -1 101 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73500 22 19 2201 1591 1 1290 149 18 18 324 mult_36 auto 33.9 MiB 3.96 8738 27335 5810 17606 3919 71.8 MiB 0.75 0.01 9.29835 -606.15 -9.29835 9.29835 0.78 0.00474546 0.00429979 0.319794 0.290255 54 16607 42 8.04299e+06 4.18335e+06 1.08842e+06 3359.33 5.60 1.37437 1.21416 33712 268580 -1 12763 24 9307 10561 1197981 287506 8.67428 8.67428 -895.049 -8.67428 0 0 1.34436e+06 4149.26 0.34 0.51 0.24 -1 -1 0.34 0.215604 0.192549 751 586 456 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_26.v common 15.07 vpr 72.17 MiB 0.11 11824 -1 -1 1 0.27 -1 -1 37384 -1 -1 105 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73900 22 19 2275 1648 1 1330 153 18 18 324 mult_36 auto 34.3 MiB 4.64 8508 22239 4415 15566 2258 72.2 MiB 0.62 0.01 9.42265 -590.577 -9.42265 9.42265 0.80 0.00445864 0.00401596 0.257362 0.233603 58 14084 47 8.04299e+06 4.23924e+06 1.14310e+06 3528.09 5.07 1.33825 1.18192 34680 290288 -1 11882 25 8955 10040 1155840 295020 8.75428 8.75428 -771.843 -8.75428 0 0 1.43297e+06 4422.75 0.37 0.49 0.24 -1 -1 0.37 0.224963 0.200306 779 605 475 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_27.v common 15.95 vpr 72.68 MiB 0.12 12180 -1 -1 1 0.31 -1 -1 36636 -1 -1 111 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74420 22 19 2385 1724 1 1404 160 18 18 324 mult_36 auto 34.8 MiB 4.54 8706 29238 6495 17225 5518 72.7 MiB 0.73 0.01 9.5032 -657.318 -9.5032 9.5032 0.82 0.00494662 0.00454829 0.328609 0.29886 54 15872 37 8.04299e+06 4.7191e+06 1.08842e+06 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-k6_frac_ripple_N8_22nm.xml fir_nopipe_29.v common 21.18 vpr 73.47 MiB 0.18 12728 -1 -1 1 0.34 -1 -1 37124 -1 -1 118 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75236 22 19 2565 1853 1 1511 168 22 22 484 mult_36 auto 35.8 MiB 5.07 9474 28874 6138 19875 2861 73.5 MiB 0.84 0.01 9.50133 -723.607 -9.50133 9.50133 1.27 0.00561174 0.0050836 0.359574 0.328413 48 19694 45 1.30842e+07 5.21292e+06 1.52614e+06 3153.19 8.93 1.66619 1.47757 49190 371334 -1 15172 26 14085 16168 2028455 476792 9.32778 9.32778 -1106.44 -9.32778 0 0 1.85176e+06 3825.95 0.50 0.70 0.33 -1 -1 0.50 0.26154 0.232522 881 694 532 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_30.v common 23.43 vpr 73.83 MiB 0.18 12628 -1 -1 1 0.34 -1 -1 37408 -1 -1 123 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75604 22 19 2639 1910 1 1549 173 22 22 484 mult_36 auto 36.1 MiB 5.43 9440 36248 7919 24781 3548 73.8 MiB 0.99 0.01 9.36191 -670.158 -9.36191 9.36191 1.30 0.00494298 0.00448404 0.423993 0.384622 48 20360 50 1.30842e+07 5.28279e+06 1.52614e+06 3153.19 10.37 1.80964 1.60233 49190 371334 -1 15247 24 13469 15202 1910838 455736 8.95958 8.95958 -928.137 -8.95958 0 0 1.85176e+06 3825.95 0.50 0.72 0.32 -1 -1 0.50 0.254704 0.227272 910 713 551 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_31.v common 20.52 vpr 75.10 MiB 0.11 12956 -1 -1 1 0.35 -1 -1 37316 -1 -1 128 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76900 22 19 2744 1981 1 1618 178 22 22 484 mult_36 auto 37.0 MiB 5.38 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-1 16006 25 13662 15590 1847779 424015 8.83758 8.83758 -1053.02 -8.83758 0 0 2.06816e+06 4273.05 0.59 0.75 0.35 -1 -1 0.59 0.284515 0.253659 974 764 589 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_33.v common 20.81 vpr 75.45 MiB 0.19 13676 -1 -1 1 0.29 -1 -1 37356 -1 -1 137 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77256 22 19 2923 2109 1 1726 188 22 22 484 mult_36 auto 37.9 MiB 5.35 10997 40538 8465 27874 4199 75.4 MiB 1.12 0.01 10.2864 -775.869 -10.2864 10.2864 1.27 0.00603775 0.00548455 0.463266 0.419405 52 22517 47 1.30842e+07 5.87443e+06 1.63434e+06 3376.74 8.03 1.96653 1.74365 50638 406276 -1 16574 24 12868 14850 1713334 417624 9.69202 9.69202 -1312.41 -9.69202 0 0 2.01763e+06 4168.66 0.52 0.60 0.36 -1 -1 0.52 0.259428 0.231175 1009 796 608 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_34.v common 23.72 vpr 75.49 MiB 0.15 13668 -1 -1 1 0.46 -1 -1 37768 -1 -1 140 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77304 22 19 2997 2166 1 1764 191 22 22 484 mult_36 auto 38.1 MiB 8.36 11197 34229 7090 23850 3289 75.5 MiB 0.93 0.01 10.179 -781.353 -10.179 10.179 1.24 0.0059064 0.00538226 0.383252 0.348114 54 21293 29 1.30842e+07 5.91636e+06 1.67518e+06 3461.11 7.73 1.7254 1.52965 51122 416746 -1 16721 23 13120 14891 1633684 395631 9.53142 9.53142 -1224.14 -9.53142 0 0 2.06816e+06 4273.05 0.54 0.66 0.38 -1 -1 0.54 0.27638 0.245962 1037 815 627 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_35.v common 23.83 vpr 76.11 MiB 0.25 14040 -1 -1 1 0.49 -1 -1 37616 -1 -1 145 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77940 22 19 3101 2236 1 1831 196 22 22 484 mult_36 auto 38.7 MiB 7.24 12065 39457 7984 27451 4022 76.1 MiB 1.09 0.02 10.526 -851.981 -10.526 10.526 1.24 0.00586591 0.00534859 0.436328 0.396044 56 22258 29 1.30842e+07 5.98623e+06 1.71605e+06 3545.56 8.54 1.85952 1.64959 51606 428054 -1 18193 24 12714 14593 1871341 439910 10.0876 10.0876 -1238.72 -10.0876 0 0 2.11301e+06 4365.72 0.61 0.73 0.36 -1 -1 0.61 0.297247 0.265421 1072 846 646 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_36.v common 24.33 vpr 76.50 MiB 0.20 14132 -1 -1 1 0.44 -1 -1 38020 -1 -1 148 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78332 22 19 3175 2293 1 1871 199 22 22 484 mult_36 auto 39.2 MiB 9.10 12207 40799 8234 28761 3804 76.5 MiB 1.07 0.02 10.1611 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-1 38268 -1 -1 161 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79784 22 19 3457 2490 1 2044 213 24 24 576 mult_36 auto 40.5 MiB 8.89 13552 45933 9854 31922 4157 77.9 MiB 1.23 0.02 10.2548 -903.58 -10.2548 10.2548 1.43 0.0061585 0.00559162 0.50214 0.4543 56 23176 27 1.57908e+07 6.60581e+06 2.03561e+06 3534.04 7.69 2.02374 1.79471 61006 507707 -1 19371 24 12670 14651 1649493 401965 9.71472 9.71472 -1420.41 -9.71472 0 0 2.50747e+06 4353.24 0.70 0.73 0.46 -1 -1 0.70 0.328048 0.292553 1198 946 722 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_40.v common 29.98 vpr 78.39 MiB 0.21 14836 -1 -1 1 0.55 -1 -1 38816 -1 -1 164 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80272 22 19 3531 2547 1 2082 216 24 24 576 mult_36 auto 41.0 MiB 10.45 14377 40977 8198 29796 2983 78.4 MiB 1.20 0.04 10.1711 -960.277 -10.1711 10.1711 1.48 0.0143787 0.0127714 0.458028 0.414102 54 25953 34 1.57908e+07 6.64774e+06 1.98675e+06 3449.22 10.60 2.07487 1.83836 60430 494267 -1 20022 24 14385 16625 1937405 463879 9.81632 9.81632 -1428.6 -9.81632 0 0 2.45377e+06 4260.01 0.64 0.73 0.39 -1 -1 0.64 0.314374 0.279746 1226 965 741 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_41.v common 35.16 vpr 78.74 MiB 0.28 15280 -1 -1 1 0.49 -1 -1 38148 -1 -1 170 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80628 22 19 3634 2616 1 2147 223 24 24 576 mult_36 auto 41.5 MiB 9.41 15712 55655 12202 38909 4544 78.7 MiB 1.47 0.02 10.3763 -978.657 -10.3763 10.3763 1.47 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2.61600e+06 4541.67 0.71 0.81 0.45 -1 -1 0.71 0.329232 0.292614 1289 1014 779 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_43.v common 36.71 vpr 79.58 MiB 0.18 15700 -1 -1 1 0.52 -1 -1 39024 -1 -1 178 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81492 22 19 3810 2741 1 2253 231 24 24 576 mult_36 auto 42.4 MiB 10.00 15931 45543 9198 31101 5244 79.6 MiB 1.19 0.02 10.2488 -1034.23 -10.2488 10.2488 1.39 0.00703787 0.00638807 0.446452 0.40357 58 28790 31 1.57908e+07 7.23937e+06 2.08734e+06 3623.85 17.51 2.14457 1.89576 62154 534210 -1 22784 25 17469 20003 2871017 629000 9.78802 9.78802 -1425.18 -9.78802 0 0 2.61600e+06 4541.67 0.70 0.99 0.44 -1 -1 0.70 0.367709 0.327023 1323 1043 798 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_44.v common 31.84 vpr 79.89 MiB 0.19 15672 -1 -1 1 0.62 -1 -1 38428 -1 -1 181 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81804 22 19 3884 2798 1 2294 234 24 24 576 mult_36 auto 42.5 MiB 11.63 15026 47034 9339 32867 4828 79.9 MiB 1.26 0.02 10.6634 -975.806 -10.6634 10.6634 1.49 0.00718101 0.00652364 0.497842 0.448355 56 25505 43 1.57908e+07 7.28129e+06 2.03561e+06 3534.04 10.72 2.34961 2.07315 61006 507707 -1 21177 24 13604 15932 1830861 450606 10.1266 10.1266 -1497.53 -10.1266 0 0 2.50747e+06 4353.24 0.75 0.86 0.45 -1 -1 0.75 0.39966 0.357524 1351 1062 817 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_45.v common 34.45 vpr 80.38 MiB 0.20 15976 -1 -1 1 0.56 -1 -1 40620 -1 -1 186 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82304 22 19 3989 2869 1 2359 240 24 24 576 mult_36 auto 43.1 MiB 10.86 16504 49410 9364 35589 4457 80.4 MiB 1.34 0.02 10.4128 -1039.57 -10.4128 10.4128 1.47 0.00736411 0.00667934 0.524551 0.472825 58 28065 31 1.57908e+07 7.74716e+06 2.08734e+06 3623.85 14.02 2.31055 2.04279 62154 534210 -1 23178 24 14780 17083 2031719 479355 10.0216 10.0216 -1620.1 -10.0216 0 0 2.61600e+06 4541.67 0.76 0.85 0.46 -1 -1 0.76 0.380055 0.340905 1387 1094 836 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_46.v common 34.08 vpr 80.50 MiB 0.16 16112 -1 -1 1 0.51 -1 -1 40524 -1 -1 189 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82428 22 19 4063 2926 1 2398 243 24 24 576 mult_36 auto 43.3 MiB 12.69 15456 49513 9815 35157 4541 80.5 MiB 1.38 0.02 10.3988 -1055.79 -10.3988 10.3988 1.48 0.00738406 0.00670027 0.527894 0.477333 54 30376 49 1.57908e+07 7.78909e+06 1.98675e+06 3449.22 11.93 2.5705 2.26971 60430 494267 -1 22258 25 14010 16246 1792980 437746 10.0703 10.0703 -1496.13 -10.0703 0 0 2.45377e+06 4260.01 0.71 0.83 0.42 -1 -1 0.71 0.407104 0.363229 1414 1113 855 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_47.v common 31.04 vpr 80.99 MiB 0.29 16436 -1 -1 1 0.50 -1 -1 40912 -1 -1 194 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82936 22 19 4167 2996 1 2466 248 24 24 576 mult_36 auto 43.9 MiB 11.29 16457 49262 9642 34224 5396 81.0 MiB 1.33 0.02 10.2964 -1023.88 -10.2964 10.2964 1.45 0.00767253 0.00696798 0.528201 0.475734 62 27413 41 1.57908e+07 7.85896e+06 2.19658e+06 3813.51 10.15 2.47844 2.18562 63306 560109 -1 22126 24 15880 18201 1967159 487181 9.26852 9.26852 -1515.46 -9.26852 0 0 2.72095e+06 4723.87 0.80 0.85 0.42 -1 -1 0.80 0.382417 0.341094 1449 1144 874 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_48.v common 37.43 vpr 81.34 MiB 0.29 16504 -1 -1 1 0.60 -1 -1 40704 -1 -1 197 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83288 22 19 4241 3053 1 2505 251 24 24 576 mult_36 auto 44.2 MiB 13.09 16971 46920 8877 33152 4891 81.3 MiB 1.26 0.02 10.3426 -1105.68 -10.3426 10.3426 1.41 0.00707168 0.00637172 0.454538 0.408531 58 28357 39 1.57908e+07 7.90088e+06 2.08734e+06 3623.85 14.75 2.52654 2.23221 62154 534210 -1 23109 25 14819 17069 1985321 468184 9.32312 9.32312 -1714.79 -9.32312 0 0 2.61600e+06 4541.67 0.71 0.84 0.45 -1 -1 0.71 0.394003 0.351585 1477 1163 893 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_49.v common 31.77 vpr 81.89 MiB 0.24 16968 -1 -1 1 0.63 -1 -1 41060 -1 -1 204 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83852 22 19 4346 3124 1 2572 259 24 24 576 mult_36 auto 44.8 MiB 12.23 17818 58009 12065 38423 7521 81.9 MiB 1.51 0.02 10.4215 -1066.19 -10.4215 10.4215 1.46 0.0080745 0.00733701 0.604224 0.544123 64 27669 29 1.57908e+07 8.3947e+06 2.26035e+06 3924.22 9.46 2.45546 2.1712 64454 586630 -1 23761 23 15470 17571 1974721 480976 10.0026 10.0026 -1667.25 -10.0026 0 0 2.84938e+06 4946.85 0.77 0.83 0.50 -1 -1 0.77 0.375436 0.332674 1512 1195 912 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_50.v common 38.16 vpr 82.15 MiB 0.29 17100 -1 -1 1 0.66 -1 -1 41020 -1 -1 206 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84120 22 19 4420 3181 1 2611 261 24 24 576 mult_36 auto 44.8 MiB 13.82 18113 59404 12055 41197 6152 82.1 MiB 1.17 0.02 10.7633 -1102.87 -10.7633 10.7633 1.43 0.00500541 0.00457353 0.399298 0.359786 58 30827 50 1.57908e+07 8.42264e+06 2.08734e+06 3623.85 14.62 2.65311 2.33328 62154 534210 -1 25105 24 17430 20166 2474881 582739 9.91802 9.91802 -1434.59 -9.91802 0 0 2.61600e+06 4541.67 0.83 0.99 0.44 -1 -1 0.83 0.413443 0.368887 1541 1214 931 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_51.v common 35.76 vpr 82.72 MiB 0.36 17424 -1 -1 1 0.69 -1 -1 41064 -1 -1 211 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84708 22 19 4524 3251 1 2681 266 24 24 576 mult_36 auto 45.6 MiB 12.68 17903 58406 11821 39335 7250 82.7 MiB 1.54 0.02 10.1189 -1113.35 -10.1189 10.1189 1.47 0.00840097 0.00762828 0.598606 0.537073 66 28650 46 1.57908e+07 8.49251e+06 2.33135e+06 4047.49 12.41 2.79535 2.46899 65030 601923 -1 23838 22 15662 18095 2053216 483046 9.32782 9.32782 -1570.64 -9.32782 0 0 2.91907e+06 5067.82 0.88 0.90 0.53 -1 -1 0.88 0.406862 0.363976 1576 1245 950 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_52.v common 38.64 vpr 83.15 MiB 0.31 17420 -1 -1 1 0.66 -1 -1 39328 -1 -1 215 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85148 22 19 4598 3308 1 2718 270 24 24 576 mult_36 auto 46.1 MiB 14.46 18499 60438 12754 41701 5983 83.2 MiB 1.60 0.02 10.3652 -1274.39 -10.3652 10.3652 1.47 0.00856926 0.00761627 0.633263 0.568286 60 30704 47 1.57908e+07 8.54841e+06 2.13333e+06 3703.69 13.56 2.91685 2.57247 62730 548095 -1 24767 24 17273 19354 2179586 520270 9.64242 9.64242 -1770.68 -9.64242 0 0 2.67122e+06 4637.53 0.72 1.11 0.45 -1 -1 0.72 0.496032 0.445053 1605 1264 969 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_14.v common 7.87 vpr 70.55 MiB 0.07 10524 -1 -1 1 0.24 -1 -1 35484 -1 -1 81 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72248 22 19 1974 1653 1 1020 126 16 16 256 mult_36 auto 32.4 MiB 0.34 5566 18081 3979 11568 2534 70.6 MiB 0.43 0.01 4.18656 -1184 -4.18656 4.18656 0.67 0.00356539 0.00320963 0.220467 0.198858 50 12015 26 6.54114e+06 2.7256e+06 787708. 3076.99 3.45 1.01169 0.882887 25344 186282 -1 9252 17 4107 4636 547995 139041 4.41926 4.41926 -1238.23 -4.41926 0 0 943753. 3686.54 0.24 0.26 0.16 -1 -1 0.24 0.141423 0.125975 605 708 247 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_15.v common 8.30 vpr 71.43 MiB 0.11 10904 -1 -1 1 0.26 -1 -1 36900 -1 -1 88 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73144 22 19 2144 1789 1 1120 134 16 16 256 mult_36 auto 33.2 MiB 0.36 6319 20654 4053 14159 2442 71.4 MiB 0.51 0.01 4.29396 -1347.48 -4.29396 4.29396 0.58 0.00372143 0.00335451 0.253783 0.22888 50 12838 32 6.54114e+06 3.22025e+06 787708. 3076.99 3.77 1.17955 1.03156 25344 186282 -1 10194 15 4381 5331 543271 135603 4.41926 4.41926 -1427.22 -4.41926 0 0 943753. 3686.54 0.23 0.24 0.17 -1 -1 0.23 0.128701 0.114324 654 769 266 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_16.v common 8.39 vpr 71.61 MiB 0.10 10948 -1 -1 1 0.28 -1 -1 36840 -1 -1 91 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73332 22 19 2218 1846 1 1162 137 16 16 256 mult_36 auto 33.5 MiB 0.37 6746 20611 4243 13930 2438 71.6 MiB 0.50 0.01 4.27196 -1343.11 -4.27196 4.27196 0.59 0.0032663 0.00291636 0.239428 0.215294 56 12205 20 6.54114e+06 3.26253e+06 849745. 3319.32 3.49 1.14162 1.001 26364 208198 -1 10886 18 4466 5238 632605 153751 4.54456 4.54456 -1414.59 -4.54456 0 0 1.04740e+06 4091.43 0.29 0.30 0.19 -1 -1 0.29 0.15905 0.140984 683 788 285 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_17.v common 9.73 vpr 72.91 MiB 0.08 11792 -1 -1 1 0.32 -1 -1 36508 -1 -1 103 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74660 22 19 2536 2130 1 1275 149 16 16 256 mult_36 auto 34.6 MiB 0.47 7309 25759 5410 16752 3597 72.9 MiB 0.59 0.01 4.22437 -1538.56 -4.22437 4.22437 0.57 0.00421061 0.00376811 0.292735 0.261633 54 15370 50 6.54114e+06 3.43166e+06 829453. 3240.05 4.63 1.49103 1.29857 26108 202796 -1 11251 20 4866 5650 591941 150326 4.41926 4.41926 -1554.25 -4.41926 0 0 1.02522e+06 4004.78 0.27 0.32 0.18 -1 -1 0.27 0.191262 0.168408 770 924 304 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_18.v common 10.30 vpr 73.96 MiB 0.11 11880 -1 -1 1 0.29 -1 -1 37264 -1 -1 107 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75732 22 19 2610 2187 1 1316 153 16 16 256 mult_36 auto 35.4 MiB 0.45 7489 21012 3652 14420 2940 74.0 MiB 0.52 0.01 4.05741 -1594.66 -4.05741 4.05741 0.59 0.00442383 0.00397394 0.261885 0.235686 58 14224 36 6.54114e+06 3.48803e+06 871168. 3403.00 5.23 1.41298 1.23272 26872 219187 -1 11540 19 4929 5820 646042 159250 4.41926 4.41926 -1618.92 -4.41926 0 0 1.09288e+06 4269.05 0.26 0.39 0.19 -1 -1 0.26 0.204211 0.18126 798 943 323 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_19.v common 10.55 vpr 74.75 MiB 0.14 12128 -1 -1 1 0.25 -1 -1 36804 -1 -1 113 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76548 22 19 2778 2321 1 1412 160 16 16 256 mult_36 auto 36.3 MiB 0.47 8590 28804 5795 19118 3891 74.8 MiB 0.72 0.01 4.16866 -1754.96 -4.16866 4.16866 0.60 0.00457112 0.00408692 0.351306 0.314519 60 14551 41 6.54114e+06 3.96859e+06 890343. 3477.90 5.43 1.68264 1.47097 27128 224764 -1 12108 19 5195 6165 612347 148881 4.29396 4.29396 -1780.33 -4.29396 0 0 1.11577e+06 4358.47 0.27 0.35 0.17 -1 -1 0.27 0.205204 0.181382 846 1002 342 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_20.v common 11.37 vpr 74.61 MiB 0.10 12396 -1 -1 1 0.31 -1 -1 37000 -1 -1 118 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76400 22 19 2852 2378 1 1455 165 16 16 256 mult_36 auto 36.7 MiB 0.47 8719 21409 3812 14750 2847 74.6 MiB 0.53 0.01 4.23032 -1751.68 -4.23032 4.23032 0.57 0.00497053 0.00445561 0.253389 0.227057 58 15488 34 6.54114e+06 4.03906e+06 871168. 3403.00 6.21 1.50021 1.30756 26872 219187 -1 12591 16 5346 6342 671911 168571 4.29396 4.29396 -1828.31 -4.29396 0 0 1.09288e+06 4269.05 0.30 0.33 0.19 -1 -1 0.30 0.183129 0.162478 875 1021 361 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_21.v common 11.40 vpr 75.77 MiB 0.14 12892 -1 -1 1 0.38 -1 -1 37876 -1 -1 122 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77592 22 19 3057 2549 1 1560 169 16 16 256 mult_36 auto 37.8 MiB 0.52 9662 28189 5474 18473 4242 75.8 MiB 0.72 0.01 4.27196 -1924.27 -4.27196 4.27196 0.56 0.00527906 0.00471781 0.33261 0.296421 60 16376 39 6.54114e+06 4.09544e+06 890343. 3477.90 5.78 1.68732 1.4696 27128 224764 -1 13229 17 5417 6865 651246 161214 4.52256 4.52256 -1946.8 -4.52256 0 0 1.11577e+06 4358.47 0.29 0.37 0.20 -1 -1 0.29 0.214974 0.191547 932 1099 380 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_22.v common 11.22 vpr 75.77 MiB 0.15 13000 -1 -1 1 0.36 -1 -1 38084 -1 -1 125 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77584 22 19 3131 2606 1 1600 172 16 16 256 mult_36 auto 37.8 MiB 0.50 9746 26940 4762 17615 4563 75.8 MiB 0.74 0.01 4.1051 -1925.37 -4.1051 4.1051 0.60 0.00611816 0.00544144 0.356751 0.319711 64 17025 40 6.54114e+06 4.13772e+06 943753. 3686.54 5.32 1.70879 1.49331 27892 240595 -1 13419 19 5604 6604 696533 174227 4.41926 4.41926 -1888.34 -4.41926 0 0 1.19033e+06 4649.74 0.30 0.40 0.23 -1 -1 0.30 0.237528 0.209958 961 1118 399 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_23.v common 16.07 vpr 76.61 MiB 0.17 13432 -1 -1 1 0.37 -1 -1 37772 -1 -1 133 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78444 22 19 3301 2742 1 1700 181 18 18 324 mult_36 auto 38.7 MiB 0.59 10073 29819 5770 20700 3349 76.6 MiB 0.78 0.01 4.29396 -2072.96 -4.29396 4.29396 0.94 0.00542746 0.00490157 0.375376 0.33652 58 20039 44 8.06603e+06 4.64648e+06 1.14310e+06 3528.09 9.23 1.91764 1.67586 34680 290288 -1 15296 19 6397 7351 896472 206109 4.52256 4.52256 -2107.99 -4.52256 0 0 1.43297e+06 4422.75 0.40 0.44 0.25 -1 -1 0.40 0.240683 0.213451 1012 1179 418 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_24.v common 14.61 vpr 77.01 MiB 0.16 13444 -1 -1 1 0.37 -1 -1 38100 -1 -1 137 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78856 22 19 3375 2799 1 1744 185 18 18 324 mult_36 auto 39.0 MiB 0.53 10242 28589 5033 20765 2791 77.0 MiB 0.77 0.01 4.16866 -2095.84 -4.16866 4.16866 0.89 0.00584888 0.00521185 0.358826 0.320166 56 19239 34 8.06603e+06 4.70285e+06 1.11497e+06 3441.27 8.07 1.89179 1.65394 34036 275796 -1 15430 18 6668 8155 902923 218175 4.66986 4.66986 -2283.29 -4.66986 0 0 1.37338e+06 4238.83 0.34 0.45 0.23 -1 -1 0.34 0.243287 0.216124 1041 1198 437 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_25.v common 12.96 vpr 77.87 MiB 0.14 13944 -1 -1 1 0.45 -1 -1 38164 -1 -1 146 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79740 22 19 3615 3005 1 1848 194 18 18 324 mult_36 auto 39.9 MiB 0.63 11381 30488 5169 21849 3470 77.9 MiB 0.84 0.01 4.29396 -2317.79 -4.29396 4.29396 0.96 0.00648239 0.00577959 0.389275 0.347872 60 19735 24 8.06603e+06 4.8297e+06 1.16833e+06 3605.96 5.76 1.97602 1.73231 35004 297736 -1 15899 18 6600 7758 807688 195562 4.41926 4.41926 -2334.44 -4.41926 0 0 1.46313e+06 4515.82 0.41 0.46 0.27 -1 -1 0.41 0.266483 0.237429 1107 1293 456 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_26.v common 15.61 vpr 78.54 MiB 0.13 14192 -1 -1 1 0.42 -1 -1 38520 -1 -1 148 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80428 22 19 3689 3062 1 1888 196 18 18 324 mult_36 auto 40.5 MiB 0.63 11433 29784 5199 21859 2726 78.5 MiB 0.82 0.02 4.24437 -2303.41 -4.24437 4.24437 0.85 0.00711705 0.00628036 0.378532 0.339296 58 20982 37 8.06603e+06 4.85789e+06 1.14310e+06 3528.09 8.60 2.11816 1.84746 34680 290288 -1 16695 16 7063 8326 925400 221942 4.41926 4.41926 -2385.92 -4.41926 0 0 1.43297e+06 4422.75 0.36 0.47 0.24 -1 -1 0.36 0.260815 0.235816 1135 1312 475 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_27.v common 14.19 vpr 79.47 MiB 0.19 14444 -1 -1 1 0.48 -1 -1 38456 -1 -1 156 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81380 22 19 3871 3210 1 2002 205 18 18 324 mult_36 auto 41.4 MiB 0.56 12765 36445 6420 26320 3705 79.5 MiB 0.96 0.02 4.54456 -2408.49 -4.54456 4.54456 0.82 0.00685927 0.00612775 0.437842 0.392218 64 23264 38 8.06603e+06 5.36665e+06 1.23838e+06 3822.15 6.95 2.19503 1.91755 35972 318676 -1 18200 18 7220 8450 972098 233171 4.52256 4.52256 -2487.12 -4.52256 0 0 1.56068e+06 4816.91 0.48 0.50 0.28 -1 -1 0.48 0.289327 0.259022 1191 1385 494 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_28.v common 14.33 vpr 79.86 MiB 0.11 14480 -1 -1 1 0.47 -1 -1 38392 -1 -1 160 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81780 22 19 3945 3267 1 2045 209 18 18 324 mult_36 auto 41.9 MiB 0.70 12597 35549 6371 25304 3874 79.9 MiB 0.91 0.02 4.26697 -2505.98 -4.26697 4.26697 0.79 0.00592329 0.00528273 0.412317 0.367578 68 21534 29 8.06603e+06 5.42302e+06 1.31159e+06 4048.11 7.05 2.09847 1.8353 36620 334356 -1 17403 19 7212 8305 866718 201384 4.29396 4.29396 -2504.3 -4.29396 0 0 1.63345e+06 5041.52 0.41 0.50 0.28 -1 -1 0.41 0.292126 0.259432 1219 1404 513 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_29.v common 17.90 vpr 80.95 MiB 0.17 14996 -1 -1 1 0.48 -1 -1 39736 -1 -1 170 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82888 22 19 4159 3447 1 2159 220 22 22 484 mult_36 auto 42.9 MiB 0.66 13941 43978 8874 31271 3833 80.9 MiB 1.17 0.02 4.35022 -2631.97 -4.35022 4.35022 1.25 0.00774696 0.00697861 0.556098 0.499879 58 24926 40 1.31202e+07 5.95997e+06 1.75961e+06 3635.55 9.01 2.41905 2.11286 52570 450426 -1 20690 17 8007 9443 1068841 244740 4.54456 4.54456 -2664.53 -4.54456 0 0 2.20457e+06 4554.90 0.59 0.56 0.38 -1 -1 0.59 0.298787 0.265732 1283 1491 532 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_30.v common 17.61 vpr 81.04 MiB 0.31 15108 -1 -1 1 0.50 -1 -1 40796 -1 -1 173 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82984 22 19 4233 3504 1 2198 223 22 22 484 mult_36 auto 43.1 MiB 0.70 14275 43487 8406 30788 4293 81.0 MiB 1.13 0.02 4.29396 -2676.94 -4.29396 4.29396 1.20 0.00692972 0.00618355 0.508408 0.45329 62 26940 39 1.31202e+07 6.00225e+06 1.85176e+06 3825.95 8.47 2.36766 2.06397 53538 472186 -1 20137 19 7963 9293 978277 226339 4.39726 4.39726 -2703.02 -4.39726 0 0 2.29262e+06 4736.82 0.66 0.56 0.41 -1 -1 0.66 0.316801 0.28135 1311 1510 551 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_31.v common 20.11 vpr 82.97 MiB 0.24 15504 -1 -1 1 0.53 -1 -1 41024 -1 -1 179 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84960 22 19 4410 3647 1 2305 229 22 22 484 mult_36 auto 44.0 MiB 0.73 14328 48529 9744 34610 4175 83.0 MiB 1.21 0.02 4.31186 -2776.62 -4.31186 4.31186 1.19 0.00763571 0.00681491 0.544669 0.484896 60 26322 48 1.31202e+07 6.08682e+06 1.79840e+06 3715.71 10.61 2.63139 2.29142 53054 462096 -1 20969 18 8442 9887 1082581 257139 4.39726 4.39726 -2815.55 -4.39726 0 0 2.25108e+06 4650.99 0.71 0.59 0.38 -1 -1 0.71 0.326546 0.291041 1363 1578 570 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_32.v common 15.71 vpr 82.19 MiB 0.19 15580 -1 -1 1 0.53 -1 -1 40672 -1 -1 183 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84164 22 19 4484 3704 1 2348 233 22 22 484 mult_36 auto 44.2 MiB 0.73 14525 45341 8355 32699 4287 82.2 MiB 1.16 0.02 4.41926 -2881.16 -4.41926 4.41926 1.21 0.00766067 0.00686394 0.513788 0.459417 60 25283 24 1.31202e+07 6.14319e+06 1.79840e+06 3715.71 6.97 2.2262 1.94485 53054 462096 -1 21198 18 8307 9417 1043367 244738 4.41926 4.41926 -2865.53 -4.41926 0 0 2.25108e+06 4650.99 0.61 0.56 0.32 -1 -1 0.61 0.315484 0.280564 1393 1597 589 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_33.v common 18.91 vpr 84.66 MiB 0.22 16620 -1 -1 1 0.59 -1 -1 41660 -1 -1 196 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86688 22 19 4843 4029 1 2463 247 22 22 484 mult_36 auto 46.0 MiB 0.78 15998 49783 9671 35687 4425 84.7 MiB 1.28 0.02 4.54456 -3078.09 -4.54456 4.54456 1.19 0.00747416 0.00663489 0.560167 0.499174 62 30039 29 1.31202e+07 6.72242e+06 1.85176e+06 3825.95 9.26 2.48747 2.16446 53538 472186 -1 22471 18 8965 10546 1092220 257195 4.41926 4.41926 -3312.48 -4.41926 0 0 2.29262e+06 4736.82 0.59 0.58 0.41 -1 -1 0.59 0.352441 0.314917 1490 1756 608 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_34.v common 19.55 vpr 84.04 MiB 0.25 16760 -1 -1 1 0.57 -1 -1 41600 -1 -1 199 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86060 22 19 4917 4086 1 2505 250 22 22 484 mult_36 auto 46.4 MiB 0.77 15240 53766 10631 37846 5289 84.0 MiB 1.33 0.02 4.29396 -3047.21 -4.29396 4.29396 1.18 0.00808591 0.00721489 0.588263 0.523476 60 28229 35 1.31202e+07 6.7647e+06 1.79840e+06 3715.71 9.97 2.63886 2.29656 53054 462096 -1 22321 17 8852 10511 1134513 265850 4.52256 4.52256 -3384.85 -4.52256 0 0 2.25108e+06 4650.99 0.63 0.60 0.40 -1 -1 0.63 0.335676 0.2989 1519 1775 627 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_35.v common 23.64 vpr 85.00 MiB 0.24 17068 -1 -1 1 0.68 -1 -1 41824 -1 -1 207 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87040 22 19 5093 4228 1 2607 258 22 22 484 mult_36 auto 47.3 MiB 0.79 16561 53623 9690 39001 4932 85.0 MiB 1.34 0.02 4.27196 -3266.59 -4.27196 4.27196 1.24 0.00830998 0.0075757 0.581879 0.518075 60 31544 47 1.31202e+07 6.87745e+06 1.79840e+06 3715.71 13.58 3.07471 2.68119 53054 462096 -1 24567 20 9974 11801 1384303 319840 4.64786 4.64786 -3518.09 -4.64786 0 0 2.25108e+06 4650.99 0.64 0.77 0.37 -1 -1 0.64 0.428809 0.381439 1572 1842 646 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_36.v common 17.81 vpr 85.26 MiB 0.14 17200 -1 -1 1 0.65 -1 -1 41692 -1 -1 209 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87308 22 19 5167 4285 1 2655 260 22 22 484 mult_36 auto 47.4 MiB 0.83 17463 54974 10444 39030 5500 85.3 MiB 1.42 0.02 4.35562 -3241.22 -4.35562 4.35562 1.19 0.00860278 0.00767459 0.617579 0.546968 66 29932 33 1.31202e+07 6.90564e+06 1.96511e+06 4060.15 7.92 2.75677 2.40228 54986 507526 -1 24310 15 9330 10872 1221412 282633 4.41926 4.41926 -3341.91 -4.41926 0 0 2.45963e+06 5081.88 0.65 0.58 0.40 -1 -1 0.65 0.312635 0.278695 1600 1861 665 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_37.v common 27.73 vpr 87.54 MiB 0.26 17768 -1 -1 1 0.54 -1 -1 40916 -1 -1 218 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89640 22 19 5380 4464 1 2756 270 24 24 576 mult_36 auto 48.8 MiB 0.86 18706 56950 10603 41531 4816 87.5 MiB 1.41 0.02 4.35562 -3473.4 -4.35562 4.35562 1.50 0.00838022 0.00746015 0.610354 0.542795 60 36033 48 1.58331e+07 7.42849e+06 2.13333e+06 3703.69 16.72 3.22557 2.81696 62730 548095 -1 27276 19 10671 12691 1595594 352262 4.54456 4.54456 -3667.6 -4.54456 0 0 2.67122e+06 4637.53 0.72 0.73 0.46 -1 -1 0.72 0.392459 0.34775 1662 1947 684 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_38.v common 22.21 vpr 86.79 MiB 0.26 17700 -1 -1 1 0.70 -1 -1 42288 -1 -1 220 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88868 22 19 5454 4521 1 2804 272 24 24 576 mult_36 auto 49.1 MiB 0.86 18631 58418 11427 42785 4206 86.8 MiB 1.49 0.02 4.29396 -3507.9 -4.29396 4.29396 1.45 0.00871041 0.00776012 0.630769 0.558119 62 35211 42 1.58331e+07 7.45668e+06 2.19658e+06 3813.51 11.05 3.14164 2.73658 63306 560109 -1 26641 17 10663 12453 1388485 323603 4.39726 4.39726 -3646.05 -4.39726 0 0 2.72095e+06 4723.87 0.74 0.69 0.45 -1 -1 0.74 0.371924 0.331025 1690 1966 703 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_39.v common 25.05 vpr 87.38 MiB 0.29 18144 -1 -1 1 0.73 -1 -1 40268 -1 -1 228 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89472 22 19 5629 4662 1 2910 280 24 24 576 mult_36 auto 49.9 MiB 0.89 20090 64330 13333 46393 4604 87.4 MiB 1.77 0.02 4.55861 -3641.68 -4.55861 4.55861 1.58 0.0105706 0.00923672 0.76296 0.67492 66 38359 44 1.58331e+07 7.56943e+06 2.33135e+06 4047.49 13.56 3.38858 2.95709 65030 601923 -1 28690 16 10858 13238 1585011 358083 4.54456 4.54456 -3858.1 -4.54456 0 0 2.91907e+06 5067.82 0.82 0.68 0.42 -1 -1 0.82 0.309942 0.278263 1742 2032 722 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_40.v common 26.03 vpr 88.15 MiB 0.16 18344 -1 -1 1 0.75 -1 -1 42292 -1 -1 232 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90268 22 19 5703 4719 1 2952 284 24 24 576 mult_36 auto 50.3 MiB 0.97 18947 59996 11849 42843 5304 87.7 MiB 1.58 0.02 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1 0.89 -1 -1 43280 -1 -1 250 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92720 22 19 6198 5129 1 3209 303 24 24 576 mult_36 auto 52.8 MiB 1.03 22784 60306 10847 44895 4564 90.0 MiB 1.63 0.03 4.66986 -4092.44 -4.66986 4.66986 1.56 0.010458 0.00933727 0.683433 0.609507 68 38832 41 1.58331e+07 8.2755e+06 2.39371e+06 4155.74 15.82 3.42817 2.98344 65606 615345 -1 31135 17 11588 13651 1552306 353970 4.54456 4.54456 -4162.55 -4.54456 0 0 2.98162e+06 5176.42 0.80 0.76 0.49 -1 -1 0.80 0.414118 0.368413 1921 2237 798 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_44.v common 24.51 vpr 90.27 MiB 0.24 19576 -1 -1 1 0.89 -1 -1 43548 -1 -1 253 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92432 22 19 6272 5186 1 3255 306 24 24 576 mult_36 auto 52.8 MiB 1.02 21212 62106 11016 45638 5452 90.3 MiB 1.89 0.03 4.29396 -3963.31 -4.29396 4.29396 1.50 0.0118959 0.0107204 0.811675 0.728958 66 38086 47 1.58331e+07 8.31778e+06 2.33135e+06 4047.49 12.08 3.96345 3.47157 65030 601923 -1 29668 16 11714 13642 1536421 356784 4.52256 4.52256 -4103.45 -4.52256 0 0 2.91907e+06 5067.82 0.82 0.73 0.50 -1 -1 0.82 0.396822 0.353156 1949 2256 817 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_45.v common 23.95 vpr 93.04 MiB 0.29 19992 -1 -1 1 0.99 -1 -1 43872 -1 -1 262 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 95268 22 19 6485 5365 1 3364 316 24 24 576 mult_36 auto 53.9 MiB 1.06 21665 63741 11956 46622 5163 91.4 MiB 1.69 0.03 4.41926 -4168.43 -4.41926 4.41926 1.43 0.0109101 0.00976255 0.702499 0.622845 64 37095 22 1.58331e+07 8.84063e+06 2.26035e+06 3924.22 11.56 3.25556 2.83432 64454 586630 -1 31001 18 12007 14131 1617183 372391 4.54456 4.54456 -4244.66 -4.54456 0 0 2.84938e+06 4946.85 0.84 0.83 0.47 -1 -1 0.84 0.455739 0.405333 2011 2342 836 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_46.v common 28.82 vpr 94.72 MiB 0.17 20176 -1 -1 1 0.95 -1 -1 44120 -1 -1 266 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 96992 22 19 6559 5422 1 3406 320 24 24 576 mult_36 auto 54.3 MiB 1.11 22395 70336 13410 49504 7422 91.7 MiB 1.88 0.03 4.29396 -4167.58 -4.29396 4.29396 1.55 0.0104906 0.00933311 0.751473 0.664137 68 38012 39 1.58331e+07 8.897e+06 2.39371e+06 4155.74 15.77 3.61694 3.13945 65606 615345 -1 30883 18 11581 13686 1504829 345509 4.41926 4.41926 -4245.28 -4.41926 0 0 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v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 99552 22 19 6809 5621 1 3556 330 24 24 576 mult_36 auto 55.5 MiB 1.24 24443 75504 14693 54581 6230 92.9 MiB 2.12 0.03 4.54456 -4333.82 -4.54456 4.54456 1.61 0.0130596 0.0117811 0.89344 0.798428 68 41304 32 1.58331e+07 9.03794e+06 2.39371e+06 4155.74 14.16 4.00794 3.5132 65606 615345 -1 32992 16 12193 14996 1577116 364367 4.66986 4.66986 -4785.3 -4.66986 0 0 2.98162e+06 5176.42 0.83 0.79 0.49 -1 -1 0.83 0.434988 0.387791 2121 2447 893 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_49.v common 25.51 vpr 96.57 MiB 0.23 21104 -1 -1 1 1.09 -1 -1 44384 -1 -1 287 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 98888 22 19 7094 5872 1 3671 342 24 24 576 mult_36 auto 56.6 MiB 1.18 24412 81602 15797 59095 6710 94.3 MiB 2.29 0.03 4.66986 -4735 -4.66986 4.66986 1.59 0.0116342 0.0102507 0.880052 0.775715 76 38504 31 1.58331e+07 9.58898e+06 2.61600e+06 4541.67 11.47 3.75695 3.26879 68478 680951 -1 32830 17 11929 13673 1640992 357972 4.92046 4.92046 -4741.32 -4.92046 0 0 3.24203e+06 5628.53 0.93 0.87 0.55 -1 -1 0.93 0.489288 0.436653 2200 2569 912 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_50.v common 27.54 vpr 98.38 MiB 0.35 21340 -1 -1 1 1.16 -1 -1 44232 -1 -1 290 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100736 22 19 7168 5929 1 3712 345 24 24 576 mult_36 auto 57.1 MiB 1.25 25160 76512 14255 54563 7694 94.7 MiB 1.93 0.03 4.47552 -4598.48 -4.47552 4.47552 1.61 0.013865 0.0125473 0.804796 0.724721 70 41615 40 1.58331e+07 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2655 950 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_52.v common 32.37 vpr 102.40 MiB 0.37 21760 -1 -1 1 1.14 -1 -1 45136 -1 -1 301 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 104856 22 19 7418 6128 1 3860 356 24 24 576 mult_36 auto 58.7 MiB 1.26 25970 87365 17770 61046 8549 96.3 MiB 2.54 0.03 4.34967 -4804.09 -4.34967 4.34967 1.60 0.0145542 0.0131418 1.06436 0.932564 72 44233 45 1.58331e+07 9.78629e+06 2.50747e+06 4353.24 17.54 4.64956 4.04739 67330 654343 -1 35405 17 12953 15244 1834273 401238 4.54456 4.54456 -4810.48 -4.54456 0 0 3.14081e+06 5452.80 0.85 0.91 0.53 -1 -1 0.85 0.514887 0.459964 2310 2674 969 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_14.v common 18.72 vpr 66.80 MiB 0.10 9440 -1 -1 1 0.19 -1 -1 34640 -1 -1 58 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68404 22 19 1246 925 1 732 103 16 16 256 mult_36 auto 28.4 MiB 1.17 4023 13117 2985 8070 2062 66.8 MiB 0.34 0.01 8.30942 -383.734 -8.30942 8.30942 0.59 0.00262001 0.00241154 0.150191 0.137092 40 8052 31 6.54114e+06 2.40144e+06 616420. 2407.89 13.83 1.33095 1.17365 23812 153515 -1 6887 25 6377 7252 840667 207113 7.83898 7.83898 -465.002 -7.83898 0 0 808720. 3159.06 0.20 0.35 0.14 -1 -1 0.20 0.139969 0.124794 421 344 247 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_15.v common 8.49 vpr 67.56 MiB 0.07 9596 -1 -1 1 0.18 -1 -1 35084 -1 -1 61 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69180 22 19 1344 989 1 791 107 16 16 256 mult_36 auto 29.3 MiB 0.96 4575 14022 3062 9140 1820 67.6 MiB 0.35 0.01 8.46467 -389.974 -8.46467 8.46467 0.59 0.00303809 0.00280853 0.166695 0.152832 42 9875 50 6.54114e+06 2.83972e+06 649763. 2538.14 3.81 0.88637 0.786788 24068 159480 -1 7244 23 6090 6933 810054 211687 7.95378 7.95378 -494.958 -7.95378 0 0 829453. 3240.05 0.22 0.34 0.14 -1 -1 0.22 0.139388 0.124672 453 369 266 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_16.v common 8.88 vpr 67.79 MiB 0.11 9644 -1 -1 1 0.18 -1 -1 35228 -1 -1 65 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69416 22 19 1418 1046 1 832 111 16 16 256 mult_36 auto 29.5 MiB 1.30 4773 16071 3747 10021 2303 67.8 MiB 0.39 0.01 8.40964 -409.362 -8.40964 8.40964 0.58 0.00292238 0.0026757 0.181568 0.165822 46 9093 31 6.54114e+06 2.89609e+06 723233. 2825.13 3.79 0.816121 0.72172 24832 174915 -1 7344 26 5474 6088 675835 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35032 -1 -1 74 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70372 22 19 1592 1169 1 934 120 16 16 256 mult_36 auto 30.6 MiB 1.48 5562 18410 4023 12076 2311 68.7 MiB 0.50 0.01 9.11545 -462.729 -9.11545 9.11545 0.58 0.00313992 0.00286707 0.219509 0.20039 50 10839 29 6.54114e+06 3.02294e+06 787708. 3076.99 3.65 0.960923 0.851871 25344 186282 -1 8621 24 6644 7427 822442 205516 8.84223 8.84223 -564.118 -8.84223 0 0 943753. 3686.54 0.24 0.34 0.19 -1 -1 0.24 0.155445 0.138298 542 434 323 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_19.v common 9.72 vpr 68.82 MiB 0.11 10560 -1 -1 1 0.27 -1 -1 35344 -1 -1 79 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70468 22 19 1688 1231 1 993 126 16 16 256 mult_36 auto 30.8 MiB 1.32 5905 19656 4339 11653 3664 68.8 MiB 0.49 0.01 9.37523 -468.383 -9.37523 9.37523 0.58 0.00351254 0.00323258 0.232479 0.212033 48 11452 47 6.54114e+06 3.48941e+06 755748. 2952.14 4.24 1.13956 1.0091 25088 180500 -1 8957 23 5555 6342 718459 187069 8.83268 8.83268 -558.947 -8.83268 0 0 916467. 3579.95 0.23 0.33 0.16 -1 -1 0.23 0.163001 0.145746 573 457 342 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_20.v common 10.98 vpr 69.38 MiB 0.09 10784 -1 -1 1 0.23 -1 -1 35528 -1 -1 81 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71044 22 19 1762 1288 1 1031 128 16 16 256 mult_36 auto 31.4 MiB 1.59 6159 20092 4300 10622 5170 69.4 MiB 0.47 0.01 9.0553 -504.795 -9.0553 9.0553 0.58 0.00336194 0.003079 0.223133 0.20372 48 12002 45 6.54114e+06 3.51759e+06 755748. 2952.14 5.14 1.09027 0.964321 25088 180500 -1 9426 26 8013 9013 1087933 263252 8.51952 8.51952 -758.559 -8.51952 0 0 916467. 3579.95 0.27 0.43 0.18 -1 -1 0.27 0.182262 0.162271 601 476 361 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_21.v common 10.02 vpr 69.73 MiB 0.11 10904 -1 -1 1 0.24 -1 -1 35776 -1 -1 85 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71404 22 19 1859 1351 1 1092 132 16 16 256 mult_36 auto 31.6 MiB 1.57 6816 20232 4108 12738 3386 69.7 MiB 0.54 0.01 9.21366 -510.538 -9.21366 9.21366 0.59 0.00370234 0.00339557 0.232676 0.21175 54 12156 29 6.54114e+06 3.57397e+06 829453. 3240.05 4.16 1.10107 0.97694 26108 202796 -1 9502 23 6442 7334 699332 184639 8.23497 8.23497 -611.204 -8.23497 0 0 1.02522e+06 4004.78 0.24 0.34 0.18 -1 -1 0.24 0.17102 0.152253 632 500 380 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_22.v common 11.05 vpr 69.93 MiB 0.14 11016 -1 -1 1 0.26 -1 -1 35912 -1 -1 90 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71604 22 19 1933 1408 1 1130 137 16 16 256 mult_36 auto 31.8 MiB 1.89 6953 18846 3874 11726 3246 69.9 MiB 0.51 0.01 9.25639 -524.337 -9.25639 9.25639 0.60 0.00633064 0.00579152 0.229754 0.209796 54 12678 28 6.54114e+06 3.64444e+06 829453. 3240.05 4.77 1.12815 0.998589 26108 202796 -1 10018 23 7514 8545 880687 221653 8.27422 8.27422 -608.588 -8.27422 0 0 1.02522e+06 4004.78 0.26 0.42 0.19 -1 -1 0.26 0.195465 0.17486 661 519 399 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_23.v common 12.05 vpr 70.30 MiB 0.14 11296 -1 -1 1 0.24 -1 -1 35984 -1 -1 94 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71988 22 19 2031 1472 1 1193 142 18 18 324 mult_36 auto 32.4 MiB 1.88 7735 24562 5200 16532 2830 70.3 MiB 0.65 0.01 9.45758 -535.83 -9.45758 9.45758 0.78 0.00385623 0.00351616 0.276218 0.251396 50 14484 31 8.06603e+06 4.09681e+06 1.03391e+06 3191.07 5.08 1.22106 1.08246 32744 246704 -1 11690 23 7230 8414 1076073 253853 8.46493 8.46493 -695.821 -8.46493 0 0 1.23838e+06 3822.15 0.31 0.47 0.23 -1 -1 0.31 0.198031 0.176796 693 544 418 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_24.v common 15.78 vpr 70.71 MiB 0.17 11480 -1 -1 1 0.22 -1 -1 36208 -1 -1 97 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72404 22 19 2105 1529 1 1230 145 18 18 324 mult_36 auto 32.6 MiB 1.82 7180 26745 5794 17769 3182 70.7 MiB 0.44 0.01 9.12646 -589.17 -9.12646 9.12646 0.72 0.00174114 0.00155803 0.141052 0.12686 46 15589 39 8.06603e+06 4.13909e+06 948677. 2928.01 9.22 1.18426 1.04138 32096 231720 -1 11052 22 7422 8604 958262 236388 8.28608 8.28608 -757.327 -8.28608 0 0 1.16833e+06 3605.96 0.35 0.43 0.17 -1 -1 0.35 0.198698 0.177394 721 563 437 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_25.v common 13.08 vpr 71.23 MiB 0.19 11976 -1 -1 1 0.32 -1 -1 36508 -1 -1 101 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72944 22 19 2201 1591 1 1290 149 18 18 324 mult_36 auto 33.3 MiB 1.80 8299 21425 4201 14721 2503 71.2 MiB 0.63 0.01 9.40561 -605.89 -9.40561 9.40561 0.82 0.0049407 0.00448797 0.265454 0.241336 50 15707 32 8.06603e+06 4.19547e+06 1.03391e+06 3191.07 5.84 1.31782 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fir_nopipe_27.v common 13.18 vpr 72.21 MiB 0.12 12088 -1 -1 1 0.32 -1 -1 36688 -1 -1 111 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73948 22 19 2385 1724 1 1404 160 18 18 324 mult_36 auto 34.4 MiB 1.94 9241 28370 5807 18956 3607 72.2 MiB 0.83 0.01 9.27331 -683.845 -9.27331 9.27331 0.78 0.00442823 0.00404133 0.325043 0.29516 54 17136 39 8.06603e+06 4.73242e+06 1.08842e+06 3359.33 5.64 1.46239 1.29485 33712 268580 -1 13437 24 10877 12354 1477729 344669 8.64193 8.64193 -919.251 -8.64193 0 0 1.34436e+06 4149.26 0.36 0.59 0.22 -1 -1 0.36 0.252438 0.226581 817 642 494 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_28.v common 14.41 vpr 72.31 MiB 0.16 12296 -1 -1 1 0.32 -1 -1 36784 -1 -1 114 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74048 22 19 2459 1781 1 1443 163 18 18 324 mult_36 auto 34.3 MiB 2.32 9764 21523 4098 13503 3922 72.3 MiB 0.62 0.01 9.32934 -687.124 -9.32934 9.32934 0.78 0.00551631 0.00500842 0.259632 0.236424 56 16775 37 8.06603e+06 4.7747e+06 1.11497e+06 3441.27 6.63 1.46602 1.29663 34036 275796 -1 13980 23 9350 10755 1348955 317758 8.77023 8.77023 -898.217 -8.77023 0 0 1.37338e+06 4238.83 0.34 0.53 0.24 -1 -1 0.34 0.233752 0.208772 845 661 513 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_29.v common 16.69 vpr 73.07 MiB 0.19 12476 -1 -1 1 0.36 -1 -1 37116 -1 -1 118 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74828 22 19 2565 1853 1 1511 168 22 22 484 mult_36 auto 35.2 MiB 2.60 9948 31652 6879 21519 3254 73.1 MiB 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0.35 -1 -1 36972 -1 -1 131 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75492 22 19 2818 2038 1 1656 181 22 22 484 mult_36 auto 36.0 MiB 2.74 10985 33396 7014 22006 4376 73.7 MiB 0.94 0.01 9.18872 -729.727 -9.18872 9.18872 1.22 0.00555682 0.00501678 0.391822 0.354063 52 21147 46 1.31202e+07 5.4103e+06 1.63434e+06 3376.74 7.78 1.89748 1.68336 50638 406276 -1 15805 26 12963 14588 1925572 461503 8.66113 8.66113 -888.638 -8.66113 0 0 2.01763e+06 4168.66 0.56 0.76 0.37 -1 -1 0.56 0.298184 0.266224 974 764 589 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_33.v common 18.09 vpr 74.57 MiB 0.18 13792 -1 -1 1 0.37 -1 -1 37332 -1 -1 137 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76356 22 19 2923 2109 1 1725 188 22 22 484 mult_36 auto 36.9 MiB 2.39 11534 41076 8921 25709 6446 74.6 MiB 1.05 0.01 10.2924 -835.387 -10.2924 10.2924 1.27 0.00546535 0.00497593 0.44184 0.40093 54 21231 38 1.31202e+07 5.89087e+06 1.67518e+06 3461.11 8.17 1.90087 1.69027 51122 416746 -1 16854 24 11734 13578 1615248 384384 9.39377 9.39377 -1134.87 -9.39377 0 0 2.06816e+06 4273.05 0.54 0.62 0.34 -1 -1 0.54 0.267121 0.2382 1009 796 608 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_34.v common 21.65 vpr 74.83 MiB 0.21 13772 -1 -1 1 0.38 -1 -1 37876 -1 -1 140 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76624 22 19 2997 2166 1 1764 191 22 22 484 mult_36 auto 37.2 MiB 3.66 12266 39170 8245 26892 4033 74.8 MiB 1.07 0.01 9.97834 -770.817 -9.97834 9.97834 1.21 0.00571216 0.0052044 0.426004 0.386425 56 21922 39 1.31202e+07 5.93316e+06 1.71605e+06 3545.56 10.32 1.86387 1.65418 51606 428054 -1 18215 24 13841 15896 2255928 507616 9.94227 9.94227 -1246.47 -9.94227 0 0 2.11301e+06 4365.72 0.54 0.76 0.35 -1 -1 0.54 0.281343 0.250097 1037 815 627 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_35.v common 19.19 vpr 75.42 MiB 0.15 13984 -1 -1 1 0.39 -1 -1 37592 -1 -1 145 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77228 22 19 3101 2236 1 1830 196 22 22 484 mult_36 auto 37.6 MiB 3.22 11422 38319 7965 26269 4085 75.4 MiB 1.02 0.01 9.90229 -825.692 -9.90229 9.90229 1.23 0.00568749 0.00517513 0.40807 0.368882 54 21987 30 1.31202e+07 6.00363e+06 1.67518e+06 3461.11 8.36 1.90347 1.6945 51122 416746 -1 17198 23 12943 14962 1754919 421016 9.26291 9.26291 -1135.22 -9.26291 0 0 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success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78116 22 19 3280 2364 1 1940 204 24 24 576 mult_36 auto 38.6 MiB 3.56 12413 41604 8759 29253 3592 76.3 MiB 1.07 0.02 10.1414 -859.737 -10.1414 10.1414 1.64 0.00602109 0.00548311 0.412304 0.372312 50 25735 44 1.58331e+07 6.49829e+06 1.88759e+06 3277.06 11.57 2.03071 1.79344 58706 454005 -1 18389 25 12459 14636 1793419 425436 9.27766 9.27766 -1319.74 -9.27766 0 0 2.26035e+06 3924.22 0.60 0.75 0.36 -1 -1 0.60 0.334717 0.30042 1135 897 684 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_38.v common 21.64 vpr 76.78 MiB 0.24 14576 -1 -1 1 0.46 -1 -1 37976 -1 -1 157 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78620 22 19 3354 2421 1 1977 209 24 24 576 mult_36 auto 39.0 MiB 4.17 12700 43609 9545 30570 3494 76.8 MiB 1.19 0.02 10.0282 -917.593 -10.0282 10.0282 1.49 0.00602725 0.00545141 0.471712 0.425047 56 21119 26 1.58331e+07 6.56876e+06 2.03561e+06 3534.04 8.64 1.92611 1.70534 61006 507707 -1 18139 27 11695 13188 1690980 410021 9.18442 9.18442 -1340.55 -9.18442 0 0 2.50747e+06 4353.24 0.70 0.76 0.43 -1 -1 0.70 0.348213 0.310179 1164 916 703 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_39.v common 22.11 vpr 77.25 MiB 0.12 14688 -1 -1 1 0.46 -1 -1 38264 -1 -1 161 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79100 22 19 3457 2490 1 2042 213 24 24 576 mult_36 auto 39.5 MiB 3.72 12894 46568 10474 28732 7362 77.2 MiB 1.22 0.02 10.1583 -949.474 -10.1583 10.1583 1.43 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success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79964 22 19 3708 2673 1 2186 226 24 24 576 mult_36 auto 40.3 MiB 4.74 16104 42194 8322 28032 5840 78.1 MiB 1.14 0.02 10.4136 -1012.01 -10.4136 10.4136 1.46 0.00636253 0.00575312 0.426379 0.385045 62 27815 40 1.58331e+07 7.19026e+06 2.19658e+06 3813.51 14.85 2.26474 2.0088 63306 560109 -1 21638 25 14219 16394 2291368 490734 9.41877 9.41877 -1577.24 -9.41877 0 0 2.72095e+06 4723.87 0.71 0.81 0.46 -1 -1 0.71 0.336207 0.29879 1289 1014 779 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_43.v common 27.74 vpr 78.05 MiB 0.25 15604 -1 -1 1 0.65 -1 -1 38608 -1 -1 178 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79920 22 19 3810 2741 1 2253 231 24 24 576 mult_36 auto 40.4 MiB 4.30 15296 41295 8139 29365 3791 78.0 MiB 1.20 0.02 10.16 -1063.97 -10.16 10.16 1.54 0.0070497 0.00641468 0.455071 0.409328 56 28472 50 1.58331e+07 7.26073e+06 2.03561e+06 3534.04 13.96 2.40374 2.12442 61006 507707 -1 22090 23 15206 17473 2444394 558097 9.42572 9.42572 -1494.13 -9.42572 0 0 2.50747e+06 4353.24 0.67 0.80 0.47 -1 -1 0.67 0.286418 0.257228 1323 1043 798 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_44.v common 24.56 vpr 78.46 MiB 0.26 15644 -1 -1 1 0.65 -1 -1 38452 -1 -1 181 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80348 22 19 3884 2798 1 2294 234 24 24 576 mult_36 auto 40.8 MiB 4.95 15489 47034 9365 34232 3437 78.5 MiB 1.31 0.02 10.121 -975.462 -10.121 10.121 1.62 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success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81580 22 19 4167 2996 1 2465 248 24 24 576 mult_36 auto 42.2 MiB 4.83 16473 59376 11937 40248 7191 79.7 MiB 1.55 0.02 10.4408 -1061.77 -10.4408 10.4408 1.55 0.00789307 0.00718347 0.613169 0.553732 60 26903 48 1.58331e+07 7.88224e+06 2.13333e+06 3703.69 11.83 2.78199 2.45451 62730 548095 -1 21754 23 12304 14126 1550289 380177 9.28402 9.28402 -1464.85 -9.28402 0 0 2.67122e+06 4637.53 0.76 0.75 0.47 -1 -1 0.76 0.374453 0.33403 1449 1144 874 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_48.v common 23.87 vpr 79.73 MiB 0.23 16660 -1 -1 1 0.66 -1 -1 40516 -1 -1 197 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81648 22 19 4241 3053 1 2504 251 24 24 576 mult_36 auto 42.1 MiB 5.61 16474 57994 11394 40219 6381 79.7 MiB 1.47 0.02 10.5013 -1047.39 -10.5013 10.5013 1.43 0.00738982 0.00668981 0.570981 0.514404 64 25175 29 1.58331e+07 7.92452e+06 2.26035e+06 3924.22 8.19 2.34248 2.06535 64454 586630 -1 22200 23 12490 14529 1711643 410861 9.39387 9.39387 -1359.3 -9.39387 0 0 2.84938e+06 4946.85 0.85 0.79 0.56 -1 -1 0.85 0.382435 0.340426 1477 1163 893 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_49.v common 27.24 vpr 80.15 MiB 0.31 17092 -1 -1 1 0.64 -1 -1 40920 -1 -1 204 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82076 22 19 4346 3124 1 2572 259 24 24 576 mult_36 auto 42.5 MiB 5.24 17944 60484 12294 40037 8153 80.2 MiB 1.62 0.02 10.2711 -1057.18 -10.2711 10.2711 1.51 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14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83244 22 19 4598 3308 1 2717 270 24 24 576 mult_36 auto 43.9 MiB 6.37 18189 61310 12677 40484 8149 81.3 MiB 1.72 0.03 10.1072 -1112.57 -10.1072 10.1072 1.50 0.0101785 0.00922809 0.672075 0.603798 58 33606 48 1.58331e+07 8.57421e+06 2.08734e+06 3623.85 22.48 2.99387 2.64132 62154 534210 -1 25197 24 15147 17510 2264940 516528 9.45177 9.45177 -1662.09 -9.45177 0 0 2.61600e+06 4541.67 0.75 0.98 0.38 -1 -1 0.75 0.434057 0.386885 1605 1264 969 19 0 0 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler 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min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_frac_2ripple_N8_22nm.xml fir_pipe_14.v common 16.72 vpr 72.14 MiB 0.07 10524 -1 -1 1 0.22 -1 -1 35652 -1 -1 84 22 0 4 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73868 22 19 1974 1653 1 1008 129 16 16 256 mult_36 auto 32.4 MiB 1.05 5469 18004 3993 12227 1784 72.1 MiB 0.40 0.01 4.14666 -1156.94 -4.14666 4.14666 0.24 0.00342963 0.00309238 0.20424 0.184059 -1 -1 -1 -1 56 11505 39 6.59459e+06 2.79996e+06 849745. 3319.32 12.41 2.02021 1.75562 26364 208198 -1 8946 18 3982 4651 528508 140814 4.27196 4.27196 -1272.08 -4.27196 0 0 1.04740e+06 4091.43 0.04 0.25 0.16 -1 -1 0.04 0.141457 0.12562 484 708 247 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_pipe_15.v common 19.14 vpr 72.98 MiB 0.12 11000 -1 -1 1 0.23 -1 -1 36912 -1 -1 91 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74728 22 19 2144 1789 1 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78104 22 19 2778 2321 1 1389 163 16 16 256 mult_36 auto 36.0 MiB 1.36 8349 28643 6138 19307 3198 76.3 MiB 0.67 0.01 4.32767 -1701.92 -4.32767 4.32767 0.29 0.00489133 0.00440702 0.328294 0.294928 -1 -1 -1 -1 64 15175 30 6.59459e+06 4.05519e+06 943753. 3686.54 22.89 2.88759 2.49841 27892 240595 -1 11744 16 4803 5611 621335 143640 4.27196 4.27196 -1714.96 -4.27196 0 0 1.19033e+06 4649.74 0.04 0.31 0.20 -1 -1 0.04 0.186567 0.166709 682 1002 342 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_pipe_20.v common 11.70 vpr 76.78 MiB 0.13 12496 -1 -1 1 0.31 -1 -1 37004 -1 -1 120 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78624 22 19 2852 2378 1 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81316 22 19 3375 2799 1 1720 192 18 18 324 mult_36 auto 38.5 MiB 1.64 9997 35031 7324 24280 3427 79.4 MiB 0.78 0.01 4.2263 -2010.98 -4.2263 4.2263 0.37 0.00551458 0.00492416 0.367684 0.328149 -1 -1 -1 -1 60 17113 25 8.13932e+06 4.8565e+06 1.16833e+06 3605.96 13.83 3.1404 2.72282 35004 297736 -1 14817 17 6221 7512 731941 182840 4.27196 4.27196 -2101.85 -4.27196 0 0 1.46313e+06 4515.82 0.06 0.40 0.24 -1 -1 0.06 0.241793 0.217237 826 1198 437 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_pipe_25.v common 24.17 vpr 80.90 MiB 0.18 14024 -1 -1 1 0.41 -1 -1 38176 -1 -1 150 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82840 22 19 3615 3005 1 1813 198 18 18 324 mult_36 auto 39.9 MiB 1.74 10048 37638 8260 25340 4038 80.9 MiB 0.85 0.01 4.14666 -2190.25 -4.14666 4.14666 0.37 0.00573555 0.00511089 0.403337 0.358296 -1 -1 -1 -1 66 17382 33 8.13932e+06 4.94335e+06 1.27759e+06 3943.17 17.16 3.41995 2.95671 36296 327148 -1 14915 14 5955 7259 740555 175354 4.27196 4.27196 -2315.28 -4.27196 0 0 1.59950e+06 4936.74 0.06 0.36 0.26 -1 -1 0.06 0.218664 0.195875 891 1293 456 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_pipe_26.v common 12.13 vpr 81.18 MiB 0.18 14036 -1 -1 1 0.42 -1 -1 38344 -1 -1 155 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83124 22 19 3689 3062 1 1866 203 18 18 324 mult_36 auto 40.2 MiB 1.83 11664 39539 8297 27644 3598 81.2 MiB 0.94 0.01 4.32822 -2193.84 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 86016 22 19 4233 3504 1 2174 229 22 22 484 mult_36 auto 42.6 MiB 2.19 12823 49929 11428 34943 3558 84.0 MiB 1.10 0.02 4.27196 -2525.34 -4.27196 4.27196 0.58 0.0065951 0.00586339 0.503897 0.447818 -1 -1 -1 -1 62 22961 40 1.32347e+07 6.15512e+06 1.85176e+06 3825.95 31.78 3.98361 3.44449 53538 472186 -1 18850 14 7518 9345 917099 214842 4.39726 4.39726 -2598.37 -4.39726 0 0 2.29262e+06 4736.82 0.11 0.45 0.41 -1 -1 0.11 0.262052 0.234969 1041 1510 551 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_pipe_31.v common 41.01 vpr 85.09 MiB 0.21 15580 -1 -1 1 0.52 -1 -1 40960 -1 -1 186 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 87128 22 19 4410 3647 1 2271 236 22 22 484 mult_36 auto 43.6 MiB 2.20 14018 52724 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71228 22 19 1518 1112 1 874 114 16 16 256 mult_36 auto 30.3 MiB 1.44 5245 24402 6450 15009 2943 69.6 MiB 0.54 0.01 8.71055 -438.026 -8.71055 8.71055 0.29 0.00292705 0.00267783 0.270838 0.247842 -1 -1 -1 -1 54 10377 43 6.59459e+06 2.96435e+06 829453. 3240.05 4.94 1.17091 1.04076 26108 202796 -1 8188 26 8292 9448 963929 243570 9.34558 9.34558 -558.37 -9.34558 0 0 1.02522e+06 4004.78 0.04 0.34 0.16 -1 -1 0.04 0.156995 0.139831 366 415 304 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_nopipe_18.v common 8.03 vpr 69.85 MiB 0.12 10260 -1 -1 1 0.19 -1 -1 34968 -1 -1 71 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71524 22 19 1592 1169 1 911 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3.46168e+06 916467. 3579.95 6.63 1.71576 1.51305 27384 229598 -1 8531 27 8100 9147 1007274 238049 8.54388 8.54388 -576.436 -8.54388 0 0 1.13630e+06 4438.68 0.04 0.36 0.18 -1 -1 0.04 0.178144 0.15859 407 457 342 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_nopipe_20.v common 19.24 vpr 70.88 MiB 0.13 10668 -1 -1 1 0.21 -1 -1 35540 -1 -1 77 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72576 22 19 1762 1288 1 1008 124 16 16 256 mult_36 auto 31.2 MiB 1.58 5696 19900 4820 12143 2937 70.9 MiB 0.47 0.01 8.72494 -497.85 -8.72494 8.72494 0.29 0.00333636 0.00304322 0.232955 0.21242 -1 -1 -1 -1 62 10220 48 6.59459e+06 3.49063e+06 916467. 3579.95 14.15 1.93836 1.69903 27384 229598 -1 8514 24 7371 8214 846629 211248 8.69588 8.69588 -542.413 -8.69588 0 0 1.13630e+06 4438.68 0.04 0.34 0.19 -1 -1 0.04 0.173473 0.154762 425 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73132 22 19 1933 1408 1 1105 131 16 16 256 mult_36 auto 31.8 MiB 1.69 6613 19387 4426 12555 2406 71.4 MiB 0.49 0.01 8.68371 -576.607 -8.68371 8.68371 0.29 0.00361745 0.00330276 0.231014 0.210384 -1 -1 -1 -1 64 11510 32 6.59459e+06 3.59196e+06 943753. 3686.54 3.57 1.09921 0.971727 27892 240595 -1 9867 25 8936 10054 1161617 270205 8.73628 8.73628 -648.894 -8.73628 0 0 1.19033e+06 4649.74 0.04 0.42 0.20 -1 -1 0.04 0.194085 0.17289 467 519 399 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_nopipe_23.v common 10.20 vpr 72.12 MiB 0.15 11536 -1 -1 1 0.25 -1 -1 36192 -1 -1 89 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73852 22 19 2031 1472 1 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8.13932e+06 4.10377e+06 1.16833e+06 3605.96 4.12 1.13211 0.999115 35004 297736 -1 10624 23 8524 9667 1084700 263305 8.64568 8.64568 -770.611 -8.64568 0 0 1.46313e+06 4515.82 0.06 0.39 0.24 -1 -1 0.06 0.190269 0.169691 508 563 437 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_nopipe_25.v common 13.99 vpr 73.21 MiB 0.12 11768 -1 -1 1 0.22 -1 -1 36520 -1 -1 95 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74964 22 19 2201 1591 1 1260 143 18 18 324 mult_36 auto 33.2 MiB 1.76 8194 27745 7100 17403 3242 73.2 MiB 0.69 0.01 8.73499 -572.467 -8.73499 8.73499 0.38 0.0042082 0.00384116 0.33006 0.299895 -1 -1 -1 -1 66 14299 30 8.13932e+06 4.1472e+06 1.27759e+06 3943.17 7.86 1.99307 1.75537 36296 327148 -1 12283 23 11448 12868 1680012 391916 9.04958 9.04958 -692.805 -9.04958 0 0 1.59950e+06 4936.74 0.06 0.52 0.26 -1 -1 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75884 22 19 2385 1724 1 1372 153 18 18 324 mult_36 auto 34.2 MiB 2.02 8777 30419 7799 19239 3381 74.1 MiB 0.75 0.01 8.86475 -625.413 -8.86475 8.86475 0.37 0.00429284 0.00389463 0.34172 0.309996 -1 -1 -1 -1 76 13707 24 8.13932e+06 4.67347e+06 1.43297e+06 4422.75 7.73 2.18313 1.92481 38232 369828 -1 12614 23 9422 10787 1205229 288478 8.68188 8.68188 -858.473 -8.68188 0 0 1.77541e+06 5479.65 0.07 0.45 0.30 -1 -1 0.07 0.220245 0.196444 577 642 494 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_nopipe_28.v common 12.54 vpr 74.55 MiB 0.17 12360 -1 -1 1 0.31 -1 -1 36800 -1 -1 108 22 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76336 22 19 2459 1781 1 1407 157 18 18 324 mult_36 auto 34.7 MiB 2.09 8925 30190 7619 18347 4224 74.5 MiB 0.72 0.01 8.65855 -666.267 -8.65855 8.65855 0.37 0.00438766 0.0039739 0.340069 0.308012 -1 -1 -1 -1 66 15195 32 8.13932e+06 4.73137e+06 1.27759e+06 3943.17 5.83 1.66023 1.46255 36296 327148 -1 13273 22 10080 11530 1391089 314694 9.17008 9.17008 -831.006 -9.17008 0 0 1.59950e+06 4936.74 0.06 0.47 0.26 -1 -1 0.06 0.217458 0.194342 597 661 513 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_nopipe_29.v common 14.48 vpr 75.21 MiB 0.17 12648 -1 -1 1 0.32 -1 -1 37264 -1 -1 113 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77016 22 19 2565 1853 1 1476 163 22 22 484 mult_36 auto 35.3 MiB 2.43 8788 31313 8132 20016 3165 75.2 MiB 0.75 0.01 8.77133 -653.597 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9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74616 22 19 2144 1789 1 1096 137 16 16 256 mult_36 auto 32.8 MiB 0.83 6252 23082 5311 14826 2945 72.9 MiB 0.51 0.01 4.27196 -1278.5 -4.27196 4.27196 0.29 0.00368719 0.00331551 0.260562 0.234651 -1 -1 -1 -1 56 12471 39 6.62819e+06 3.31913e+06 849745. 3319.32 4.71 1.38491 1.20834 26364 208198 -1 9905 17 4015 4904 579812 151105 4.39726 4.39726 -1386.98 -4.39726 0 0 1.04740e+06 4091.43 0.04 0.27 0.17 -1 -1 0.04 0.152253 0.13572 530 769 266 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_pipe_16.v common 6.62 vpr 73.04 MiB 0.12 11024 -1 -1 1 0.25 -1 -1 36876 -1 -1 95 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74796 22 19 2218 1846 1 1145 141 16 16 256 mult_36 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9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78140 22 19 2852 2378 1 1431 167 16 16 256 mult_36 auto 36.0 MiB 1.08 9109 29543 6251 19805 3487 76.3 MiB 0.71 0.01 4.33405 -1719.45 -4.33405 4.33405 0.31 0.00480446 0.00430083 0.339688 0.304336 -1 -1 -1 -1 72 15149 30 6.62819e+06 4.14189e+06 1.04740e+06 4091.43 7.24 2.26964 1.97187 29168 268476 -1 12761 14 4845 5724 641063 148686 4.39726 4.39726 -1772.51 -4.39726 0 0 1.31294e+06 5128.69 0.05 0.29 0.22 -1 -1 0.05 0.172114 0.154045 698 1021 361 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_pipe_21.v common 15.79 vpr 77.49 MiB 0.16 12836 -1 -1 1 0.34 -1 -1 37928 -1 -1 127 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79352 22 19 3057 2549 1 1525 174 16 16 256 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82504 22 19 3615 3005 1 1807 198 18 18 324 mult_36 auto 39.4 MiB 1.38 10242 38214 8215 26103 3896 80.6 MiB 0.86 0.01 4.22665 -2157.26 -4.22665 4.22665 0.42 0.00581616 0.00517666 0.409019 0.363853 -1 -1 -1 -1 62 18218 46 8.18539e+06 4.97935e+06 1.20291e+06 3712.69 15.15 3.33537 2.87876 35328 304176 -1 14927 16 6073 7295 716490 176824 4.27196 4.27196 -2232.43 -4.27196 0 0 1.49010e+06 4599.06 0.06 0.36 0.24 -1 -1 0.06 0.22827 0.202908 891 1293 456 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_pipe_26.v common 17.26 vpr 80.83 MiB 0.18 14164 -1 -1 1 0.42 -1 -1 38460 -1 -1 155 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82772 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k6_frac_2uripple_N8_22nm.xml fir_nopipe_17.v common 22.16 vpr 69.66 MiB 0.12 10296 -1 -1 1 0.19 -1 -1 35392 -1 -1 68 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71332 22 19 1518 1112 1 874 114 16 16 256 mult_36 auto 30.3 MiB 0.63 5196 19710 5445 11819 2446 69.7 MiB 0.47 0.01 8.45239 -453.637 -8.45239 8.45239 0.29 0.00302513 0.00277978 0.229393 0.209995 -1 -1 -1 -1 52 11585 50 6.62819e+06 2.98067e+06 808720. 3159.06 18.20 1.69619 1.49381 25852 197779 -1 8467 26 7939 9134 1049694 260543 9.07812 9.07812 -543.726 -9.07812 0 0 1.00038e+06 3907.74 0.04 0.35 0.16 -1 -1 0.04 0.155655 0.138475 366 415 304 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_nopipe_18.v common 6.76 vpr 69.75 MiB 0.12 10348 -1 -1 1 0.19 -1 -1 34968 -1 -1 71 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 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on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73576 22 19 2031 1472 1 1164 137 18 18 324 mult_36 auto 32.2 MiB 0.79 6746 28730 7542 17338 3850 71.9 MiB 0.68 0.01 8.54591 -533.672 -8.54591 8.54591 0.38 0.0037745 0.00344253 0.325506 0.296594 -1 -1 -1 -1 56 12955 47 8.18539e+06 4.0817e+06 1.11497e+06 3441.27 4.18 1.39605 1.23432 34036 275796 -1 10923 24 9524 10733 1204326 316235 9.44578 9.44578 -667.58 -9.44578 0 0 1.37338e+06 4238.83 0.05 0.44 0.22 -1 -1 0.05 0.197167 0.175668 489 544 418 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_nopipe_24.v common 10.17 vpr 72.61 MiB 0.15 11564 -1 -1 1 0.26 -1 -1 36176 -1 -1 92 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74348 22 19 2105 1529 1 1203 140 18 18 324 mult_36 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475 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_nopipe_27.v common 22.51 vpr 73.62 MiB 0.18 12268 -1 -1 1 0.30 -1 -1 36652 -1 -1 104 22 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75384 22 19 2385 1724 1 1370 153 18 18 324 mult_36 auto 33.7 MiB 0.88 8092 32055 7887 20603 3565 73.6 MiB 0.73 0.01 8.64809 -651.306 -8.64809 8.64809 0.38 0.00428401 0.00390161 0.353171 0.320778 -1 -1 -1 -1 58 14837 29 8.18539e+06 4.69843e+06 1.14310e+06 3528.09 17.13 2.39591 2.1037 34680 290288 -1 12470 25 10099 11558 1309249 328905 9.16302 9.16302 -843.909 -9.16302 0 0 1.43297e+06 4422.75 0.06 0.49 0.23 -1 -1 0.06 0.233777 0.208169 577 642 494 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_nopipe_28.v common 14.78 vpr 74.25 MiB 0.17 12316 -1 -1 1 0.32 -1 -1 36856 -1 -1 108 22 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84256 22 19 4233 3504 1 2196 265 22 22 484 mult_36 auto 40.6 MiB 1.57 14001 52965 10141 38785 4039 82.3 MiB 1.21 0.02 4.18656 -2766.6 -4.18656 4.18656 0.59 0.00689166 0.00615924 0.46357 0.411804 -1 -1 -1 -1 52 25400 33 1.30842e+07 6.5684e+06 1.63434e+06 3376.74 18.23 3.12246 2.69814 50638 406276 -1 20255 18 7377 9042 871750 226668 4.54456 4.54456 -2785.97 -4.54456 0 0 2.01763e+06 4168.66 0.08 0.47 0.31 -1 -1 0.08 0.281012 0.247997 1312 1510 551 19 0 0 + k6_frac_ripple_N8_22nm.xml fir_pipe_31.v common 15.10 vpr 83.01 MiB 0.21 15516 -1 -1 1 0.53 -1 -1 40880 -1 -1 223 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85004 22 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 88736 22 19 5093 4228 1 2600 306 22 22 484 mult_36 auto 44.4 MiB 1.76 17113 70346 15205 49642 5499 86.7 MiB 1.64 0.02 4.39726 -3301.07 -4.39726 4.39726 0.61 0.00818413 0.00730255 0.619958 0.550445 -1 -1 -1 -1 58 27385 20 1.30842e+07 7.52337e+06 1.75961e+06 3635.55 5.81 2.71154 2.35254 52570 450426 -1 23967 17 8704 10692 1062475 277561 4.41926 4.41926 -3287.64 -4.41926 0 0 2.20457e+06 4554.90 0.09 0.54 0.35 -1 -1 0.09 0.321183 0.283601 1579 1842 646 19 0 0 + k6_frac_ripple_N8_22nm.xml fir_pipe_36.v common 31.41 vpr 86.95 MiB 0.25 17312 -1 -1 1 0.65 -1 -1 41708 -1 -1 261 22 0 10 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 89032 22 19 5167 4285 1 2654 312 22 22 484 mult_36 auto 44.6 MiB 1.80 17908 66903 12538 49558 4807 86.9 MiB 1.61 0.03 4.32323 -3308.18 -4.32323 4.32323 0.60 0.00860958 0.00769352 0.588541 0.520875 -1 -1 -1 -1 56 31375 42 1.30842e+07 7.60721e+06 1.71605e+06 3545.56 21.96 4.30623 3.71055 51606 428054 -1 25747 16 9282 11133 1163492 307557 4.54456 4.54456 -3414.57 -4.54456 0 0 2.11301e+06 4365.72 0.09 0.57 0.33 -1 -1 0.09 0.322486 0.286254 1601 1861 665 19 0 0 + k6_frac_ripple_N8_22nm.xml fir_pipe_37.v common 30.76 vpr 88.01 MiB 0.26 17764 -1 -1 1 0.67 -1 -1 40792 -1 -1 270 22 0 11 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 90120 22 19 5380 4464 1 2753 322 24 24 576 mult_36 auto 45.4 MiB 1.83 17930 72017 15146 51896 4975 88.0 MiB 1.67 0.02 4.39726 -3485.12 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/home/elgamma8/research/release/vtr-verilog-to-routing 73044 22 19 2031 1472 1 1189 159 18 18 324 mult_36 auto 31.5 MiB 4.48 7061 27679 5917 18965 2797 71.3 MiB 0.68 0.01 9.36191 -582.736 -9.36191 9.36191 0.38 0.00371606 0.00338429 0.254265 0.231417 -1 -1 -1 -1 48 12912 27 8.04299e+06 4.32309e+06 991730. 3060.90 2.90 0.953397 0.843166 32420 239176 -1 10546 23 7436 8617 945615 250974 8.93758 8.93758 -717.803 -8.93758 0 0 1.20291e+06 3712.69 0.05 0.36 0.19 -1 -1 0.05 0.176264 0.156554 700 544 418 19 0 0 + k6_frac_ripple_N8_22nm.xml fir_nopipe_24.v common 13.09 vpr 71.78 MiB 0.07 11528 -1 -1 1 0.25 -1 -1 36188 -1 -1 115 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73504 22 19 2105 1529 1 1226 163 18 18 324 mult_36 auto 32.0 MiB 4.85 7614 27308 5726 18896 2686 71.8 MiB 0.74 0.01 9.27241 -589.706 -9.27241 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75116 22 19 2459 1781 1 1435 184 18 18 324 mult_36 auto 33.6 MiB 5.87 9664 34179 7288 22627 4264 73.4 MiB 0.90 0.01 9.47211 -709.303 -9.47211 9.47211 0.37 0.00453022 0.0040763 0.308968 0.280239 -1 -1 -1 -1 52 17978 43 8.04299e+06 5.05447e+06 1.06151e+06 3276.26 5.52 1.52642 1.34525 33388 261900 -1 13899 25 10339 11870 1318603 341192 8.71498 8.71498 -893.429 -8.71498 0 0 1.31159e+06 4048.11 0.05 0.49 0.20 -1 -1 0.05 0.228226 0.20229 856 661 513 19 0 0 + k6_frac_ripple_N8_22nm.xml fir_nopipe_29.v common 19.43 vpr 73.88 MiB 0.17 12676 -1 -1 1 0.32 -1 -1 37268 -1 -1 142 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75656 22 19 2565 1853 1 1504 192 22 22 484 mult_36 auto 33.9 MiB 5.89 9917 38902 8764 24624 5514 73.9 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/home/elgamma8/research/release/vtr-verilog-to-routing 77708 22 19 3057 2549 1 1549 198 17 17 289 clb auto 35.4 MiB 1.03 9250 34182 6503 23460 4219 75.9 MiB 0.75 0.01 4.16866 -1902.33 -4.16866 4.16866 0.33 0.00498017 0.00445532 0.314048 0.279386 -1 -1 -1 -1 52 16499 45 6.89349e+06 4.50416e+06 926341. 3205.33 8.02 2.62694 2.26391 29218 227130 -1 13459 15 4935 6172 588490 160646 4.54456 4.54456 -1954.17 -4.54456 0 0 1.14541e+06 3963.36 0.04 0.30 0.18 -1 -1 0.04 0.181183 0.160647 939 1099 380 19 0 0 + k6_frac_uripple_N8_22nm.xml fir_pipe_22.v common 16.80 vpr 76.08 MiB 0.16 12964 -1 -1 1 0.34 -1 -1 37912 -1 -1 157 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77908 22 19 3131 2606 1 1600 204 17 17 289 clb auto 35.7 MiB 1.03 10391 36204 6804 25063 4337 76.1 MiB 0.83 0.01 4.29396 -2010.61 -4.29396 4.29396 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81024 22 19 3689 3062 1 1888 233 18 18 324 clb mult_36 auto 37.8 MiB 1.20 12084 41761 7839 29331 4591 79.1 MiB 0.99 0.02 4.41926 -2391.24 -4.41926 4.41926 0.38 0.00615276 0.00550654 0.38751 0.346378 -1 -1 -1 -1 56 19374 25 8.06603e+06 5.37936e+06 1.11497e+06 3441.27 4.53 2.02335 1.75425 34036 275796 -1 16924 17 6149 7462 703147 193689 4.54456 4.54456 -2408.11 -4.54456 0 0 1.37338e+06 4238.83 0.05 0.46 0.26 -1 -1 0.05 0.27169 0.242225 1136 1312 475 19 0 0 + k6_frac_uripple_N8_22nm.xml fir_pipe_27.v common 23.80 vpr 79.91 MiB 0.19 14560 -1 -1 1 0.45 -1 -1 38468 -1 -1 194 22 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81828 22 19 3871 3210 1 1992 243 19 19 361 clb auto 38.6 MiB 1.26 11315 46481 8979 32879 4623 79.9 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Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84424 22 19 4410 3647 1 2297 273 22 22 484 mult_36 auto 40.7 MiB 1.53 15086 56028 10921 40849 4258 82.4 MiB 1.31 0.02 4.39726 -2835.95 -4.39726 4.39726 0.58 0.00723747 0.00646969 0.487651 0.433891 -1 -1 -1 -1 54 28995 49 1.31202e+07 6.70695e+06 1.67518e+06 3461.11 21.06 3.52671 3.04296 51122 416746 -1 21612 13 7756 9275 951243 242088 4.66986 4.66986 -2900.03 -4.66986 0 0 2.06816e+06 4273.05 0.08 0.44 0.32 -1 -1 0.08 0.236748 0.210606 1370 1578 570 19 0 0 + k6_frac_uripple_N8_22nm.xml fir_pipe_32.v common 13.50 vpr 82.77 MiB 0.22 15816 -1 -1 1 0.53 -1 -1 40564 -1 -1 229 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84760 22 19 4484 3704 1 2346 279 22 22 484 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75056 22 19 2565 1853 1 1504 192 22 22 484 mult_36 auto 33.4 MiB 2.66 9980 38902 8510 27060 3332 73.3 MiB 0.94 0.01 9.55956 -734.936 -9.55956 9.55956 0.58 0.00467819 0.00424899 0.341342 0.309318 -1 -1 -1 -1 46 19528 31 1.31202e+07 5.56534e+06 1.45945e+06 3015.39 29.18 2.55349 2.24323 48706 359646 -1 14955 23 9799 11721 1367754 344286 8.92648 8.92648 -1046.74 -8.92648 0 0 1.79840e+06 3715.71 0.08 0.53 0.32 -1 -1 0.08 0.233165 0.207613 891 694 532 19 0 0 + k6_frac_uripple_N8_22nm.xml fir_nopipe_30.v common 40.51 vpr 73.54 MiB 0.18 12696 -1 -1 1 0.26 -1 -1 37316 -1 -1 145 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75304 22 19 2639 1910 1 1540 195 22 22 484 mult_36 auto 33.7 MiB 2.84 9425 47655 11240 31065 5350 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4524 3251 1 2671 308 24 24 576 mult_36 auto 41.0 MiB 5.18 18561 77194 16474 53362 7358 82.8 MiB 2.10 0.03 10.2353 -1249.02 -10.2353 10.2353 0.71 0.00813623 0.00736483 0.636713 0.568738 -1 -1 -1 -1 56 31415 47 1.58331e+07 9.10978e+06 2.03561e+06 3534.04 40.83 4.73954 4.14534 61006 507707 -1 25944 24 15278 18150 2062037 537506 9.39491 9.39491 -1834.69 -9.39491 0 0 2.50747e+06 4353.24 0.11 0.90 0.39 -1 -1 0.11 0.419484 0.372632 1594 1245 950 19 0 0 + k6_frac_uripple_N8_22nm.xml fir_nopipe_52.v common 26.53 vpr 89.48 MiB 0.32 17472 -1 -1 1 0.69 -1 -1 39304 -1 -1 258 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 91628 22 19 4598 3308 1 2708 313 24 24 576 mult_36 auto 41.2 MiB 5.63 17989 78901 17073 53371 8457 82.8 MiB 2.11 0.03 10.0544 -1205.38 -10.0544 10.0544 0.69 0.00923478 0.00812452 0.667561 0.594533 -1 -1 -1 -1 60 26627 33 1.58331e+07 9.18025e+06 2.13333e+06 3703.69 12.39 3.91661 3.44487 62730 548095 -1 24090 24 13892 16967 1757096 435601 9.21877 9.21877 -1665.44 -9.21877 0 0 2.67122e+06 4637.53 0.12 0.81 0.43 -1 -1 0.12 0.419028 0.37223 1624 1264 969 19 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt index 7754909e7b4..23d74d84fd3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt @@ -1,201 +1,201 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 3.50 vpr 61.01 MiB 0.01 5816 -1 -1 2 0.05 -1 -1 31892 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62472 11 6 34 40 1 24 19 17 17 289 -1 unnamed_device 22.4 MiB 0.01 72 444 121 288 35 61.0 MiB 0.01 0.00 0.900447 -12.0151 -0.900447 0.900447 0.95 0.000147916 0.000134485 0.00301238 0.00273498 22 213 10 6.55708e+06 24110 420624. 1455.45 0.64 0.0194369 0.0168614 20158 92377 -1 158 12 95 98 5293 1758 0.83871 0.83871 -12.913 -0.83871 0 0 500653. 1732.36 0.17 0.01 0.13 -1 -1 0.17 0.0048254 0.00430326 16 7 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 3.60 vpr 61.00 MiB 0.02 6064 -1 -1 3 0.06 -1 -1 31956 -1 -1 3 13 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62468 13 7 41 48 1 32 23 17 17 289 -1 unnamed_device 22.4 MiB 0.01 91 855 163 648 44 61.0 MiB 0.01 0.00 1.58811 -16.2873 -1.58811 1.58811 0.95 0.000177402 0.000162269 0.00519947 0.00475699 24 295 11 6.55708e+06 36165 448715. 1552.65 0.71 0.0249257 0.0217293 20734 103517 -1 254 10 116 129 6964 2198 1.50711 1.50711 -17.293 -1.50711 0 0 554710. 1919.41 0.18 0.01 0.15 -1 -1 0.18 0.00501074 0.00449096 19 9 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 3.69 vpr 60.88 MiB 0.01 5880 -1 -1 3 0.06 -1 -1 32376 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62336 15 8 47 55 1 38 26 17 17 289 -1 unnamed_device 22.2 MiB 0.01 99 1014 271 604 139 60.9 MiB 0.01 0.00 1.23151 -17.4525 -1.23151 1.23151 0.96 0.000203904 0.000186784 0.0059962 0.00548251 26 398 20 6.55708e+06 36165 477104. 1650.88 0.77 0.0318265 0.027733 21022 109990 -1 272 8 150 171 7737 2724 1.14085 1.14085 -18.4888 -1.14085 0 0 585099. 2024.56 0.19 0.01 0.16 -1 -1 0.19 0.00489735 0.00439557 23 10 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 4.85 vpr 61.05 MiB 0.01 5884 -1 -1 3 0.07 -1 -1 32092 -1 -1 4 17 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62512 17 9 56 65 1 42 30 17 17 289 -1 unnamed_device 22.2 MiB 0.06 120 628 136 477 15 61.0 MiB 0.01 0.00 1.70831 -21.0872 -1.70831 1.70831 0.96 0.000251482 0.000230868 0.00407859 0.00374317 28 337 17 6.55708e+06 48220 500653. 1732.36 1.89 0.0668127 0.057696 21310 115450 -1 293 12 147 164 8042 2499 1.58811 1.58811 -21.8318 -1.58811 0 0 612192. 2118.31 0.21 0.02 0.16 -1 -1 0.21 0.00738294 0.00656787 25 14 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 3.70 vpr 61.07 MiB 0.02 5956 -1 -1 4 0.06 -1 -1 31980 -1 -1 4 19 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62532 19 10 60 70 1 48 33 17 17 289 -1 unnamed_device 22.3 MiB 0.02 142 1229 224 959 46 61.1 MiB 0.02 0.00 1.58811 -24.8435 -1.58811 1.58811 0.95 0.000261776 0.000240893 0.00688308 0.00632377 26 425 11 6.55708e+06 48220 477104. 1650.88 0.77 0.0357697 0.0312968 21022 109990 -1 380 16 211 268 12350 3922 1.59011 1.59011 -25.4098 -1.59011 0 0 585099. 2024.56 0.19 0.02 0.16 -1 -1 0.19 0.00945114 0.00833258 29 13 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 5.45 vpr 61.21 MiB 0.03 5844 -1 -1 4 0.06 -1 -1 31764 -1 -1 5 21 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62676 21 11 69 80 1 54 37 17 17 289 -1 unnamed_device 22.7 MiB 0.05 255 1379 224 1089 66 61.2 MiB 0.02 0.00 1.74751 -29.3828 -1.74751 1.74751 0.98 0.000301732 0.000278383 0.00759182 0.0070033 26 631 16 6.55708e+06 60275 477104. 1650.88 2.35 0.0681668 0.0593772 21022 109990 -1 573 15 226 325 21349 5594 1.59211 1.59211 -31.6197 -1.59211 0 0 585099. 2024.56 0.19 0.02 0.16 -1 -1 0.19 0.0101978 0.00903499 33 17 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 3.82 vpr 60.99 MiB 0.01 5896 -1 -1 5 0.04 -1 -1 32356 -1 -1 5 23 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62452 23 12 73 85 1 58 40 17 17 289 -1 unnamed_device 22.3 MiB 0.02 278 3032 1045 1570 417 61.0 MiB 0.03 0.00 2.03736 -35.0243 -2.03736 2.03736 0.99 0.000313724 0.000288155 0.0147363 0.0135526 26 630 14 6.55708e+06 60275 477104. 1650.88 0.80 0.05062 0.044825 21022 109990 -1 591 12 246 332 19803 5342 2.03736 2.03736 -37.4544 -2.03736 0 0 585099. 2024.56 0.20 0.02 0.16 -1 -1 0.20 0.00906154 0.00809068 35 16 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.90 vpr 61.21 MiB 0.01 6096 -1 -1 5 0.06 -1 -1 31996 -1 -1 6 25 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62684 25 13 82 95 1 66 44 17 17 289 -1 unnamed_device 22.5 MiB 0.02 261 1738 345 1379 14 61.2 MiB 0.02 0.00 2.11777 -37.2459 -2.11777 2.11777 0.96 0.000351899 0.000323529 0.00882293 0.00811274 28 700 13 6.55708e+06 72330 500653. 1732.36 0.90 0.0481305 0.0424594 21310 115450 -1 582 11 253 352 21177 5630 1.7847 1.7847 -38.388 -1.7847 0 0 612192. 2118.31 0.20 0.02 0.17 -1 -1 0.20 0.00821106 0.00733367 40 20 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.91 vpr 61.17 MiB 0.03 6144 -1 -1 5 0.06 -1 -1 32156 -1 -1 7 27 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62636 27 14 91 105 1 70 48 17 17 289 -1 unnamed_device 22.5 MiB 0.02 359 1875 334 1509 32 61.2 MiB 0.02 0.00 1.74751 -38.0286 -1.74751 1.74751 0.95 0.000399123 0.000368654 0.00960368 0.00887756 26 782 16 6.55708e+06 84385 477104. 1650.88 0.88 0.055629 0.0490976 21022 109990 -1 739 13 288 437 26332 6701 1.61564 1.61564 -41.0607 -1.61564 0 0 585099. 2024.56 0.19 0.03 0.16 -1 -1 0.19 0.0114245 0.0101843 42 24 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 3.89 vpr 61.09 MiB 0.01 6012 -1 -1 6 0.08 -1 -1 31864 -1 -1 7 29 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62560 29 15 95 110 1 74 51 17 17 289 -1 unnamed_device 22.6 MiB 0.04 393 3811 1258 2017 536 61.1 MiB 0.04 0.00 2.47436 -47.7903 -2.47436 2.47436 0.95 0.000410482 0.000378211 0.0175403 0.0161537 26 836 30 6.55708e+06 84385 477104. 1650.88 0.89 0.0766164 0.0677414 21022 109990 -1 781 10 297 399 27292 6696 2.23396 2.23396 -48.1296 -2.23396 0 0 585099. 2024.56 0.20 0.03 0.12 -1 -1 0.20 0.0100811 0.00903196 45 23 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_015bits.v common 4.17 vpr 61.22 MiB 0.02 5976 -1 -1 6 0.06 -1 -1 31852 -1 -1 9 31 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62688 31 16 104 120 1 80 56 17 17 289 -1 unnamed_device 22.7 MiB 0.14 318 5620 1687 2850 1083 61.2 MiB 0.04 0.00 2.31696 -46.1298 -2.31696 2.31696 0.95 0.000322878 0.000295631 0.0181944 0.0166554 28 899 16 6.55708e+06 108495 500653. 1732.36 1.00 0.0708566 0.0627012 21310 115450 -1 747 12 319 467 28038 7282 2.07656 2.07656 -46.8018 -2.07656 0 0 612192. 2118.31 0.20 0.03 0.17 -1 -1 0.20 0.0125221 0.0111438 50 27 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_016bits.v common 3.94 vpr 61.47 MiB 0.01 6004 -1 -1 7 0.06 -1 -1 31832 -1 -1 7 33 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62948 33 17 108 125 1 86 57 17 17 289 -1 unnamed_device 23.0 MiB 0.03 550 4526 1045 3142 339 61.5 MiB 0.04 0.00 3.16202 -64.7432 -3.16202 3.16202 0.95 0.000463838 0.000428431 0.0203095 0.0187574 30 1080 27 6.55708e+06 84385 526063. 1820.29 0.90 0.08197 0.0728203 21886 126133 -1 971 12 307 433 28025 6683 2.92162 2.92162 -64.2421 -2.92162 0 0 666494. 2306.21 0.22 0.03 0.18 -1 -1 0.22 0.0128013 0.011434 51 26 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_018bits.v common 6.02 vpr 61.43 MiB 0.01 5940 -1 -1 7 0.07 -1 -1 32640 -1 -1 8 37 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62904 37 19 127 146 1 101 64 17 17 289 -1 unnamed_device 22.7 MiB 0.20 514 6795 1522 4730 543 61.4 MiB 0.06 0.00 3.00462 -67.1078 -3.00462 3.00462 0.96 0.000542022 0.000497119 0.0304047 0.0280285 30 1090 15 6.55708e+06 96440 526063. 1820.29 2.69 0.171612 0.152175 21886 126133 -1 946 13 343 485 26736 6931 2.76422 2.76422 -66.3273 -2.76422 0 0 666494. 2306.21 0.22 0.03 0.18 -1 -1 0.22 0.0157454 0.0141273 59 35 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 4.43 vpr 61.74 MiB 0.02 6248 -1 -1 8 0.07 -1 -1 32048 -1 -1 10 41 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63220 41 21 139 160 1 109 72 17 17 289 -1 unnamed_device 23.1 MiB 0.15 466 7224 1587 4756 881 61.7 MiB 0.06 0.00 3.12482 -72.4463 -3.12482 3.12482 0.94 0.000585941 0.000537805 0.0296336 0.0273828 26 1176 14 6.55708e+06 120550 477104. 1650.88 1.03 0.0959116 0.0860609 21022 109990 -1 992 60 521 751 349760 277715 2.88442 2.88442 -73.8868 -2.88442 0 0 585099. 2024.56 0.20 0.22 0.16 -1 -1 0.20 0.0605657 0.0536567 67 37 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 5.97 vpr 61.59 MiB 0.03 6236 -1 -1 9 0.07 -1 -1 32300 -1 -1 11 45 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63068 45 23 152 175 1 124 79 17 17 289 -1 unnamed_device 22.9 MiB 0.06 700 10219 3011 5707 1501 61.6 MiB 0.08 0.00 3.23076 -85.7251 -3.23076 3.23076 0.96 0.000636299 0.000587737 0.040168 0.0371027 30 1350 16 6.55708e+06 132605 526063. 1820.29 2.73 0.217915 0.194235 21886 126133 -1 1250 15 429 583 35763 8490 2.9787 2.9787 -84.954 -2.9787 0 0 666494. 2306.21 0.21 0.04 0.18 -1 -1 0.21 0.0202543 0.018224 74 40 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 6.42 vpr 61.94 MiB 0.01 6140 -1 -1 10 0.07 -1 -1 32668 -1 -1 11 49 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63428 49 25 165 190 1 131 85 17 17 289 -1 unnamed_device 23.3 MiB 0.23 510 10687 3828 4882 1977 61.9 MiB 0.08 0.00 3.62716 -93.9579 -3.62716 3.62716 0.95 0.000577829 0.000539911 0.0408866 0.0377321 34 1348 13 6.55708e+06 132605 585099. 2024.56 3.01 0.222018 0.198376 22462 138074 -1 1076 12 464 619 34731 9575 3.50696 3.50696 -93.1779 -3.50696 0 0 742403. 2568.87 0.24 0.04 0.20 -1 -1 0.24 0.0188192 0.0170145 79 43 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 4.65 vpr 61.80 MiB 0.01 6420 -1 -1 11 0.08 -1 -1 32568 -1 -1 14 57 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63280 57 29 199 228 1 157 100 17 17 289 -1 unnamed_device 23.0 MiB 0.23 782 9380 2186 6081 1113 61.8 MiB 0.07 0.00 4.46034 -123.44 -4.46034 4.46034 0.96 0.000605841 0.000559835 0.0339911 0.0314438 30 1804 48 6.55708e+06 168770 526063. 1820.29 1.19 0.174767 0.156836 21886 126133 -1 1460 13 570 852 45024 11444 3.85934 3.85934 -118.77 -3.85934 0 0 666494. 2306.21 0.22 0.05 0.18 -1 -1 0.22 0.0236573 0.0213575 93 57 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 4.68 vpr 62.28 MiB 0.01 6352 -1 -1 13 0.08 -1 -1 32060 -1 -1 15 65 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63776 65 33 224 257 1 179 113 17 17 289 -1 unnamed_device 23.4 MiB 0.44 1034 16493 4993 9000 2500 62.3 MiB 0.11 0.00 4.49339 -150.828 -4.49339 4.49339 0.96 0.000937882 0.00086809 0.0590234 0.0546171 28 2094 24 6.55708e+06 180825 500653. 1732.36 1.03 0.179539 0.162231 21310 115450 -1 1921 12 695 915 63028 15444 4.26336 4.26336 -151.13 -4.26336 0 0 612192. 2118.31 0.20 0.06 0.16 -1 -1 0.20 0.0249062 0.0225707 107 62 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 7.38 vpr 62.89 MiB 0.02 6432 -1 -1 19 0.11 -1 -1 32496 -1 -1 24 97 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64400 97 49 340 389 1 265 170 17 17 289 -1 unnamed_device 23.9 MiB 0.28 1415 34950 10191 20929 3830 62.9 MiB 0.22 0.00 6.91256 -283.047 -6.91256 6.91256 0.96 0.00143473 0.00132934 0.110179 0.102108 34 2902 25 6.55708e+06 289320 585099. 2024.56 3.54 0.507859 0.460642 22462 138074 -1 2593 11 922 1294 92517 23588 6.61819 6.61819 -278.129 -6.61819 0 0 742403. 2568.87 0.23 0.08 0.20 -1 -1 0.23 0.0358744 0.0328197 160 98 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 12.55 vpr 63.77 MiB 0.03 6688 -1 -1 26 0.11 -1 -1 32544 -1 -1 31 129 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65300 129 65 454 519 1 354 225 17 17 289 -1 unnamed_device 24.3 MiB 0.20 1738 52893 17102 30066 5725 63.8 MiB 0.32 0.00 9.58349 -458.959 -9.58349 9.58349 0.95 0.00192435 0.00178641 0.153331 0.142328 34 3942 23 6.55708e+06 373705 585099. 2024.56 8.61 0.838476 0.764406 22462 138074 -1 3385 12 1244 1747 115011 28796 9.09424 9.09424 -446.392 -9.09424 0 0 742403. 2568.87 0.23 0.10 0.20 -1 -1 0.23 0.0511318 0.0469612 213 132 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.39 abc 29.26 MiB 0.02 6300 -1 -1 1 0.03 -1 -1 29964 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23020 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.38 abc 29.34 MiB 0.03 6396 -1 -1 1 0.02 -1 -1 30044 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23352 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.46 abc 29.38 MiB 0.03 6136 -1 -1 1 0.02 -1 -1 30084 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23228 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.39 abc 29.30 MiB 0.01 6252 -1 -1 1 0.03 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23204 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.40 abc 29.33 MiB 0.01 6264 -1 -1 1 0.03 -1 -1 30036 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23244 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.40 abc 29.36 MiB 0.02 6296 -1 -1 1 0.03 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23272 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.40 abc 29.45 MiB 0.03 6332 -1 -1 1 0.02 -1 -1 30156 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23344 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.40 abc 29.30 MiB 0.01 6436 -1 -1 1 0.02 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23364 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.38 abc 29.47 MiB 0.01 6184 -1 -1 1 0.03 -1 -1 30176 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23392 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.41 abc 29.29 MiB 0.01 6316 -1 -1 1 0.02 -1 -1 29996 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23304 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.37 abc 29.25 MiB 0.01 6484 -1 -1 1 0.03 -1 -1 29956 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23404 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.41 abc 29.58 MiB 0.01 6388 -1 -1 1 0.02 -1 -1 30292 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23776 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.38 abc 29.61 MiB 0.01 6344 -1 -1 1 0.03 -1 -1 30324 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23540 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.42 abc 29.65 MiB 0.03 6444 -1 -1 1 0.02 -1 -1 30360 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23832 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.41 abc 29.82 MiB 0.01 6280 -1 -1 1 0.03 -1 -1 30536 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23516 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.40 abc 29.66 MiB 0.01 6356 -1 -1 1 0.02 -1 -1 30376 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23880 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 7 7 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.36 abc 29.73 MiB 0.02 6616 -1 -1 1 0.03 -1 -1 30448 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23668 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 8 8 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.39 abc 29.64 MiB 0.02 6516 -1 -1 1 0.03 -1 -1 30348 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23616 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 9 9 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.47 abc 29.82 MiB 0.03 6716 -1 -1 1 0.03 -1 -1 30532 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23984 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 13 13 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.45 abc 29.70 MiB 0.02 6940 -1 -1 1 0.04 -1 -1 30412 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 24276 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 17 17 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.39 abc 29.38 MiB 0.03 6260 -1 -1 1 0.02 -1 -1 30088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22928 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.41 abc 29.36 MiB 0.01 6260 -1 -1 1 0.02 -1 -1 30064 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22928 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.41 abc 29.32 MiB 0.01 6304 -1 -1 1 0.03 -1 -1 30020 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23048 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.35 abc 29.46 MiB 0.01 6256 -1 -1 1 0.02 -1 -1 30172 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23044 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.43 abc 29.31 MiB 0.03 6260 -1 -1 1 0.02 -1 -1 30012 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22900 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.40 abc 29.30 MiB 0.03 6412 -1 -1 1 0.02 -1 -1 30004 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22968 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.40 abc 29.30 MiB 0.02 6284 -1 -1 1 0.02 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23068 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.42 abc 29.35 MiB 0.01 6224 -1 -1 1 0.02 -1 -1 30056 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22976 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.37 abc 29.36 MiB 0.02 6360 -1 -1 1 0.03 -1 -1 30064 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23120 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.36 abc 29.46 MiB 0.01 6348 -1 -1 1 0.03 -1 -1 30164 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22964 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.41 abc 29.36 MiB 0.01 6316 -1 -1 1 0.03 -1 -1 30064 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23180 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.36 abc 29.51 MiB 0.01 6396 -1 -1 1 0.02 -1 -1 30216 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23232 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.37 abc 29.62 MiB 0.01 6408 -1 -1 1 0.02 -1 -1 30336 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23256 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.35 abc 29.62 MiB 0.01 6452 -1 -1 1 0.03 -1 -1 30332 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23508 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.43 abc 29.68 MiB 0.02 6344 -1 -1 1 0.02 -1 -1 30388 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23152 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.36 abc 29.77 MiB 0.02 6460 -1 -1 1 0.03 -1 -1 30488 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23392 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 7 7 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.38 abc 29.66 MiB 0.02 6356 -1 -1 1 0.03 -1 -1 30376 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23252 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 8 8 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.39 abc 29.69 MiB 0.01 6520 -1 -1 1 0.03 -1 -1 30404 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23656 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 9 9 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.40 abc 29.68 MiB 0.02 6880 -1 -1 1 0.03 -1 -1 30392 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23700 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 13 13 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.41 abc 29.86 MiB 0.02 6776 -1 -1 1 0.04 -1 -1 30572 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 24068 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 17 17 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 3.63 vpr 61.31 MiB 0.01 6316 -1 -1 1 0.02 -1 -1 30196 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62780 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 22.6 MiB 0.02 63 419 85 325 9 61.3 MiB 0.01 0.00 0.803048 -11.7113 -0.803048 0.803048 1.01 0.000115703 0.000104219 0.00248269 0.00222935 22 232 10 6.64007e+06 25116 420624. 1455.45 0.70 0.0188354 0.0162609 20818 92861 -1 196 8 97 97 4416 1451 0.912248 0.912248 -13.152 -0.912248 0 0 500653. 1732.36 0.17 0.01 0.13 -1 -1 0.17 0.00390172 0.0035265 16 2 7 7 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 3.58 vpr 61.36 MiB 0.03 6392 -1 -1 1 0.02 -1 -1 30016 -1 -1 3 13 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62836 13 7 48 49 1 32 23 17 17 289 -1 unnamed_device 22.7 MiB 0.02 113 727 127 584 16 61.4 MiB 0.01 0.00 0.825048 -14.4294 -0.825048 0.825048 0.99 0.000125571 0.00011309 0.00358775 0.00322947 26 247 6 6.64007e+06 37674 477104. 1650.88 0.67 0.0135043 0.0116866 21682 110474 -1 253 10 96 96 5814 1694 0.825048 0.825048 -15.7267 -0.825048 0 0 585099. 2024.56 0.20 0.01 0.16 -1 -1 0.20 0.00487818 0.00437432 19 2 8 8 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 3.71 vpr 61.23 MiB 0.01 6108 -1 -1 1 0.02 -1 -1 30120 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62700 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 22.5 MiB 0.02 103 938 201 719 18 61.2 MiB 0.01 0.00 1.18536 -16.7279 -1.18536 1.18536 0.98 0.000194182 0.000177814 0.00531568 0.0048707 26 296 14 6.64007e+06 37674 477104. 1650.88 0.78 0.027702 0.0241689 21682 110474 -1 255 12 171 171 7592 2494 0.954248 0.954248 -18.6358 -0.954248 0 0 585099. 2024.56 0.23 0.02 0.16 -1 -1 0.23 0.00640486 0.00575347 22 2 9 9 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 3.77 vpr 61.42 MiB 0.01 6304 -1 -1 1 0.03 -1 -1 30016 -1 -1 4 17 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62892 17 9 62 63 1 41 30 17 17 289 -1 unnamed_device 22.7 MiB 0.03 174 858 170 673 15 61.4 MiB 0.01 0.00 1.19636 -20.4292 -1.19636 1.19636 0.98 0.000158989 0.000143916 0.00348312 0.00316506 26 351 9 6.64007e+06 50232 477104. 1650.88 0.76 0.0272919 0.0237987 21682 110474 -1 343 15 138 138 7704 2264 0.921248 0.921248 -21.734 -0.921248 0 0 585099. 2024.56 0.22 0.02 0.16 -1 -1 0.22 0.00679754 0.00601394 25 2 10 10 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 3.84 vpr 61.36 MiB 0.01 6232 -1 -1 1 0.02 -1 -1 30048 -1 -1 4 19 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62836 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 22.8 MiB 0.03 216 1021 207 713 101 61.4 MiB 0.01 0.00 1.20736 -23.977 -1.20736 1.20736 0.99 0.000243033 0.000223112 0.00533354 0.00490576 26 442 13 6.64007e+06 50232 477104. 1650.88 0.85 0.0281258 0.0244045 21682 110474 -1 419 12 187 187 12739 3257 0.987248 0.987248 -25.9698 -0.987248 0 0 585099. 2024.56 0.23 0.02 0.16 -1 -1 0.23 0.00723711 0.0064074 28 2 11 11 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 3.88 vpr 61.54 MiB 0.01 6412 -1 -1 1 0.02 -1 -1 30048 -1 -1 5 21 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63016 21 11 76 77 1 49 37 17 17 289 -1 unnamed_device 23.1 MiB 0.03 214 1623 338 1262 23 61.5 MiB 0.02 0.00 1.21836 -25.661 -1.21836 1.21836 0.98 0.000272138 0.000250413 0.00831597 0.00767986 28 467 13 6.64007e+06 62790 500653. 1732.36 0.86 0.038732 0.0339266 21970 115934 -1 429 12 134 134 7869 2282 0.943248 0.943248 -27.0018 -0.943248 0 0 612192. 2118.31 0.21 0.02 0.16 -1 -1 0.21 0.00746885 0.00664669 31 2 12 12 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 3.67 vpr 61.50 MiB 0.01 6276 -1 -1 1 0.03 -1 -1 30260 -1 -1 5 23 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62980 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 22.8 MiB 0.04 261 1536 299 1189 48 61.5 MiB 0.02 0.00 1.22936 -29.0547 -1.22936 1.22936 0.92 0.000295184 0.000271395 0.00731757 0.00672944 22 568 14 6.64007e+06 62790 420624. 1455.45 0.75 0.0410044 0.0359424 20818 92861 -1 506 11 199 199 13088 3699 1.10745 1.10745 -32.0351 -1.10745 0 0 500653. 1732.36 0.20 0.03 0.13 -1 -1 0.20 0.0151575 0.0133105 34 2 13 13 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.80 vpr 61.47 MiB 0.01 6260 -1 -1 1 0.03 -1 -1 30052 -1 -1 5 25 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62944 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 22.8 MiB 0.03 303 1618 294 1276 48 61.5 MiB 0.02 0.00 1.24036 -31.9481 -1.24036 1.24036 0.96 0.000316354 0.000291154 0.00757555 0.00697705 26 656 12 6.64007e+06 62790 477104. 1650.88 0.81 0.0424619 0.0373186 21682 110474 -1 635 11 267 267 20790 5144 1.10745 1.10745 -34.9991 -1.10745 0 0 585099. 2024.56 0.19 0.02 0.16 -1 -1 0.19 0.00835673 0.00743413 37 2 14 14 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.82 vpr 61.52 MiB 0.01 6324 -1 -1 1 0.02 -1 -1 30064 -1 -1 6 27 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62996 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 23.1 MiB 0.03 324 2231 466 1582 183 61.5 MiB 0.02 0.00 1.25136 -34.9134 -1.25136 1.25136 0.95 0.000328185 0.000301419 0.0096156 0.00882967 26 657 19 6.64007e+06 75348 477104. 1650.88 0.80 0.0487004 0.0427251 21682 110474 -1 642 12 177 177 12847 3231 1.04225 1.04225 -37.0687 -1.04225 0 0 585099. 2024.56 0.26 0.02 0.14 -1 -1 0.26 0.00776323 0.00696115 40 2 15 15 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 4.01 vpr 61.71 MiB 0.03 6292 -1 -1 1 0.02 -1 -1 30268 -1 -1 6 29 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63196 29 15 104 105 1 73 50 17 17 289 -1 unnamed_device 23.2 MiB 0.03 332 2626 448 2137 41 61.7 MiB 0.03 0.00 1.26236 -36.933 -1.26236 1.26236 0.95 0.000354517 0.000326698 0.0110615 0.0101922 32 715 15 6.64007e+06 75348 554710. 1919.41 0.91 0.0518265 0.0457882 22834 132086 -1 665 9 264 264 19013 4931 0.956248 0.956248 -38.329 -0.956248 0 0 701300. 2426.64 0.25 0.02 0.20 -1 -1 0.25 0.00834853 0.00750376 43 2 16 16 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 3.85 vpr 61.70 MiB 0.02 6236 -1 -1 1 0.02 -1 -1 30304 -1 -1 7 31 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63184 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 23.2 MiB 0.03 430 4134 883 2967 284 61.7 MiB 0.04 0.00 1.62267 -42.2033 -1.62267 1.62267 0.96 0.000381488 0.000351602 0.0165045 0.0152134 26 840 9 6.64007e+06 87906 477104. 1650.88 0.80 0.0565092 0.0501826 21682 110474 -1 803 16 354 354 25144 6064 1.07325 1.07325 -43.1628 -1.07325 0 0 585099. 2024.56 0.24 0.03 0.16 -1 -1 0.24 0.0129664 0.0115094 46 2 17 17 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 3.97 vpr 61.71 MiB 0.03 6336 -1 -1 1 0.03 -1 -1 30528 -1 -1 7 33 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63192 33 17 118 119 1 82 57 17 17 289 -1 unnamed_device 23.2 MiB 0.03 400 5507 1293 3991 223 61.7 MiB 0.05 0.00 1.63367 -44.5064 -1.63367 1.63367 1.06 0.000408945 0.000377519 0.0214126 0.0197253 26 883 13 6.64007e+06 87906 477104. 1650.88 0.84 0.0663624 0.0590511 21682 110474 -1 791 19 389 389 30948 7774 1.06345 1.06345 -44.7308 -1.06345 0 0 585099. 2024.56 0.19 0.04 0.15 -1 -1 0.19 0.0147011 0.0129749 49 2 18 18 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 3.83 vpr 61.86 MiB 0.02 6216 -1 -1 1 0.03 -1 -1 30340 -1 -1 8 37 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63344 37 19 132 133 1 90 64 17 17 289 -1 unnamed_device 23.3 MiB 0.04 467 4001 820 3044 137 61.9 MiB 0.04 0.00 1.65567 -51.2944 -1.65567 1.65567 0.97 0.000459785 0.000424853 0.015202 0.0140269 26 1042 14 6.64007e+06 100464 477104. 1650.88 0.81 0.0658689 0.0583462 21682 110474 -1 917 13 352 352 28690 6808 1.17145 1.17145 -51.8759 -1.17145 0 0 585099. 2024.56 0.19 0.03 0.16 -1 -1 0.19 0.0124416 0.0110161 55 2 20 20 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 4.02 vpr 61.92 MiB 0.02 6408 -1 -1 1 0.02 -1 -1 30420 -1 -1 8 41 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63404 41 21 146 147 1 102 70 17 17 289 -1 unnamed_device 23.3 MiB 0.04 551 4966 1056 3737 173 61.9 MiB 0.05 0.00 1.67767 -59.443 -1.67767 1.67767 0.93 0.000500905 0.000462299 0.0184939 0.0170705 32 1095 12 6.64007e+06 100464 554710. 1919.41 0.94 0.0734061 0.0652999 22834 132086 -1 968 14 416 416 31553 7556 1.07325 1.07325 -55.2431 -1.07325 0 0 701300. 2426.64 0.23 0.04 0.19 -1 -1 0.23 0.0152335 0.0135691 61 2 22 22 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 4.21 vpr 62.12 MiB 0.03 6456 -1 -1 1 0.02 -1 -1 30496 -1 -1 9 45 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63608 45 23 160 161 1 114 77 17 17 289 -1 unnamed_device 23.5 MiB 0.04 584 6760 1544 5011 205 62.1 MiB 0.05 0.00 1.69967 -63.9386 -1.69967 1.69967 1.14 0.000553185 0.0005114 0.0216194 0.0199584 28 1213 14 6.64007e+06 113022 500653. 1732.36 0.91 0.0826337 0.0737112 21970 115934 -1 1091 11 457 457 39339 9371 1.11845 1.11845 -61.1772 -1.11845 0 0 612192. 2118.31 0.20 0.04 0.17 -1 -1 0.20 0.0134772 0.0121033 67 2 24 24 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 4.11 vpr 61.82 MiB 0.02 6576 -1 -1 1 0.02 -1 -1 30284 -1 -1 10 49 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63300 49 25 174 175 1 123 84 17 17 289 -1 unnamed_device 23.1 MiB 0.04 754 12711 4339 7261 1111 61.8 MiB 0.09 0.00 2.07098 -75.5183 -2.07098 2.07098 0.97 0.000599035 0.000553004 0.0428346 0.0395009 30 1330 13 6.64007e+06 125580 526063. 1820.29 0.93 0.108506 0.097651 22546 126617 -1 1194 13 486 486 33990 8082 1.18125 1.18125 -69.8231 -1.18125 0 0 666494. 2306.21 0.22 0.04 0.18 -1 -1 0.22 0.0166537 0.0149633 73 2 26 26 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 4.10 vpr 62.04 MiB 0.01 6400 -1 -1 1 0.03 -1 -1 29960 -1 -1 11 57 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63532 57 29 202 203 1 143 97 17 17 289 -1 unnamed_device 23.4 MiB 0.04 781 12973 3128 9205 640 62.0 MiB 0.10 0.00 2.11498 -88.6474 -2.11498 2.11498 0.96 0.000688368 0.000636098 0.0448878 0.0414394 28 1578 16 6.64007e+06 138138 500653. 1732.36 0.93 0.124055 0.111839 21970 115934 -1 1448 16 714 714 62305 14306 1.22525 1.22525 -82.5246 -1.22525 0 0 612192. 2118.31 0.20 0.06 0.17 -1 -1 0.20 0.0225172 0.0202093 85 2 30 30 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 4.48 vpr 62.51 MiB 0.02 6396 -1 -1 1 0.02 -1 -1 30360 -1 -1 13 65 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64008 65 33 230 231 1 164 111 17 17 289 -1 unnamed_device 23.7 MiB 0.07 1016 17401 7183 10118 100 62.5 MiB 0.15 0.00 2.50829 -106.175 -2.50829 2.50829 1.04 0.00111944 0.00103172 0.0660215 0.0610914 32 1822 12 6.64007e+06 163254 554710. 1919.41 1.05 0.153471 0.139055 22834 132086 -1 1725 13 707 707 61118 14144 1.31125 1.31125 -94.7939 -1.31125 0 0 701300. 2426.64 0.23 0.06 0.19 -1 -1 0.23 0.0222217 0.0200178 97 2 34 34 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 4.68 vpr 63.29 MiB 0.03 6728 -1 -1 1 0.03 -1 -1 30476 -1 -1 19 97 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64812 97 49 342 343 1 246 165 17 17 289 -1 unnamed_device 24.3 MiB 0.06 1599 34969 13035 19621 2313 63.3 MiB 0.24 0.00 3.38291 -183.275 -3.38291 3.38291 0.95 0.000963566 0.000889534 0.0970877 0.0900944 30 2918 27 6.64007e+06 238602 526063. 1820.29 1.24 0.242446 0.220945 22546 126617 -1 2584 20 1013 1013 84748 19026 1.51625 1.51625 -149.177 -1.51625 0 0 666494. 2306.21 0.23 0.09 0.18 -1 -1 0.23 0.0338627 0.030536 145 2 50 50 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 5.00 vpr 63.69 MiB 0.02 6864 -1 -1 1 0.03 -1 -1 30296 -1 -1 25 129 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65216 129 65 454 455 1 328 219 17 17 289 -1 unnamed_device 24.6 MiB 0.08 1778 56234 21152 30749 4333 63.7 MiB 0.40 0.01 4.25753 -263.048 -4.25753 4.25753 0.96 0.00166468 0.00155049 0.144367 0.134295 32 3642 14 6.64007e+06 313950 554710. 1919.41 1.24 0.332515 0.305368 22834 132086 -1 3143 13 1268 1268 107582 25490 1.71025 1.71025 -195.441 -1.71025 0 0 701300. 2426.64 0.23 0.11 0.19 -1 -1 0.23 0.0456319 0.0418789 193 2 66 66 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 3.50 vpr 61.26 MiB 0.01 6352 -1 -1 1 0.03 -1 -1 30152 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62732 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 22.6 MiB 0.01 67 419 80 331 8 61.3 MiB 0.01 0.00 0.803048 -11.78 -0.803048 0.803048 0.96 0.000100883 8.92e-05 0.00277665 0.00250861 22 251 10 6.65987e+06 25356 420624. 1455.45 0.65 0.0192068 0.0166272 20818 92861 -1 198 8 93 93 4666 1476 1.04345 1.04345 -14.1496 -1.04345 0 0 500653. 1732.36 0.18 0.01 0.12 -1 -1 0.18 0.00386653 0.00348934 16 2 7 7 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 3.35 vpr 61.01 MiB 0.01 6268 -1 -1 1 0.02 -1 -1 30016 -1 -1 3 13 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62476 13 7 48 49 1 32 23 17 17 289 -1 unnamed_device 22.3 MiB 0.01 108 791 160 615 16 61.0 MiB 0.01 0.00 0.825048 -14.3383 -0.825048 0.825048 0.95 0.000169095 0.000154616 0.00465786 0.00425356 20 310 11 6.65987e+06 38034 394039. 1363.46 0.60 0.0103609 0.00931345 20530 87850 -1 273 13 145 145 8632 2391 1.01045 1.01045 -16.4625 -1.01045 0 0 477104. 1650.88 0.16 0.01 0.12 -1 -1 0.16 0.005724 0.00508009 19 2 8 8 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 3.79 vpr 61.41 MiB 0.02 6244 -1 -1 1 0.02 -1 -1 30088 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62880 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 22.7 MiB 0.01 103 938 195 725 18 61.4 MiB 0.02 0.00 1.18536 -16.8309 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62996 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 22.8 MiB 0.02 256 1536 305 1173 58 61.5 MiB 0.03 0.00 1.22936 -28.8616 -1.22936 1.22936 0.94 0.000904834 0.000833633 0.00784941 0.00717263 22 582 9 6.65987e+06 63390 420624. 1455.45 0.71 0.0387895 0.0339824 20818 92861 -1 499 15 192 192 11326 3279 1.12945 1.12945 -32.4515 -1.12945 0 0 500653. 1732.36 0.17 0.02 0.13 -1 -1 0.17 0.00865158 0.00766782 34 2 13 13 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.78 vpr 61.39 MiB 0.01 6200 -1 -1 1 0.02 -1 -1 30192 -1 -1 5 25 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62868 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 22.7 MiB 0.02 293 2293 540 1476 277 61.4 MiB 0.02 0.00 1.24036 -31.9104 -1.24036 1.24036 0.96 0.000313177 0.000288035 0.010364 0.00953574 26 636 12 6.65987e+06 63390 477104. 1650.88 0.79 0.0451094 0.039711 21682 110474 -1 608 15 296 296 22531 5808 1.02025 1.02025 -34.0861 -1.02025 0 0 585099. 2024.56 0.20 0.03 0.16 -1 -1 0.20 0.0106445 0.00943593 37 2 14 14 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.83 vpr 61.36 MiB 0.01 6236 -1 -1 1 0.03 -1 -1 30124 -1 -1 6 27 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62832 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 22.9 MiB 0.02 378 2231 478 1580 173 61.4 MiB 0.02 0.00 1.25136 -36.02 -1.25136 1.25136 0.96 0.000339532 0.000312504 0.0097423 0.00897193 30 668 13 6.65987e+06 76068 526063. 1820.29 0.86 0.0468599 0.0413419 22546 126617 -1 622 11 216 216 15522 3800 0.856048 0.856048 -34.1489 -0.856048 0 0 666494. 2306.21 0.22 0.02 0.18 -1 -1 0.22 0.00895817 0.00799451 40 2 15 15 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 3.68 vpr 61.53 MiB 0.01 6456 -1 -1 1 0.03 -1 -1 30324 -1 -1 6 29 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63004 29 15 104 105 1 73 50 17 17 289 -1 unnamed_device 23.0 MiB 0.02 331 2442 412 1993 37 61.5 MiB 0.03 0.00 1.26236 -36.7774 -1.26236 1.26236 0.96 0.00035608 0.00032823 0.0103726 0.0095505 26 789 11 6.65987e+06 76068 477104. 1650.88 0.76 0.0486244 0.0429782 21682 110474 -1 724 15 378 378 28843 7348 1.06545 1.06545 -39.427 -1.06545 0 0 585099. 2024.56 0.20 0.03 0.16 -1 -1 0.20 0.0118046 0.010488 43 2 16 16 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 3.78 vpr 61.38 MiB 0.03 6324 -1 -1 1 0.03 -1 -1 30284 -1 -1 7 31 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62848 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 22.9 MiB 0.02 435 3216 703 2283 230 61.4 MiB 0.03 0.00 1.62267 -42.4629 -1.62267 1.62267 0.96 0.000387867 0.000357866 0.0129899 0.0119562 26 863 15 6.65987e+06 88746 477104. 1650.88 0.80 0.0548182 0.0484952 21682 110474 -1 825 14 376 376 28737 7038 1.05019 1.05019 -43.3518 -1.05019 0 0 585099. 2024.56 0.19 0.03 0.16 -1 -1 0.19 0.0118349 0.0105148 46 2 17 17 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 3.85 vpr 61.43 MiB 0.01 6336 -1 -1 1 0.03 -1 -1 30284 -1 -1 7 33 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62900 33 17 118 119 1 82 57 17 17 289 -1 unnamed_device 22.9 MiB 0.02 427 6052 1399 4413 240 61.4 MiB 0.05 0.00 1.63367 -46.0647 -1.63367 1.63367 0.88 0.000406209 0.000374769 0.0236579 0.0218125 26 862 21 6.65987e+06 88746 477104. 1650.88 0.87 0.0742398 0.0660048 21682 110474 -1 837 14 393 393 28781 7241 1.11845 1.11845 -46.125 -1.11845 0 0 585099. 2024.56 0.19 0.03 0.16 -1 -1 0.19 0.0126558 0.0112639 49 2 18 18 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 3.82 vpr 61.51 MiB 0.01 6388 -1 -1 1 0.02 -1 -1 30428 -1 -1 8 37 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62984 37 19 132 133 1 90 64 17 17 289 -1 unnamed_device 22.9 MiB 0.03 445 3874 792 2975 107 61.5 MiB 0.04 0.00 1.65567 -51.2172 -1.65567 1.65567 0.95 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63592 57 29 202 203 1 143 97 17 17 289 -1 unnamed_device 23.4 MiB 0.03 728 12751 3280 8876 595 62.1 MiB 0.09 0.00 2.11498 -85.6644 -2.11498 2.11498 0.97 0.000693276 0.000640716 0.041245 0.0381323 32 1538 17 6.65987e+06 139458 554710. 1919.41 1.01 0.133302 0.120096 22834 132086 -1 1375 14 555 555 43916 11014 1.23625 1.23625 -78.4834 -1.23625 0 0 701300. 2426.64 0.23 0.05 0.19 -1 -1 0.23 0.0202577 0.0181988 85 2 30 30 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 4.19 vpr 62.18 MiB 0.02 6540 -1 -1 1 0.03 -1 -1 30536 -1 -1 13 65 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63676 65 33 230 231 1 164 111 17 17 289 -1 unnamed_device 23.3 MiB 0.03 1003 17401 6715 9666 1020 62.2 MiB 0.10 0.00 2.50829 -107.27 -2.50829 2.50829 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49 1 25 22 17 17 289 -1 unnamed_device 23.4 MiB 0.04 58 562 122 423 17 61.9 MiB 0.01 0.00 0.802432 -14.4781 -0.802432 0.802432 1.00 0.000169573 0.000154834 0.00365235 0.00333138 22 206 13 6.95648e+06 28951.4 443629. 1535.05 1.96 0.0318908 0.0275353 23458 102101 -1 189 12 79 79 5519 1756 0.87204 0.87204 -15.9569 -0.87204 0 0 531479. 1839.03 0.17 0.01 0.14 -1 -1 0.17 0.00546236 0.00487674 10 2 8 8 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 3.92 vpr 62.06 MiB 0.01 6240 -1 -1 1 0.02 -1 -1 30112 -1 -1 2 15 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63548 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 23.4 MiB 0.04 82 673 149 507 17 62.1 MiB 0.01 0.00 0.830632 -16.8934 -0.830632 0.830632 1.01 0.000189877 0.000173438 0.00408628 0.00373528 26 255 11 6.95648e+06 28951.4 503264. 1741.40 0.79 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63788 21 11 76 77 1 49 34 17 17 289 -1 unnamed_device 23.7 MiB 0.04 238 914 193 707 14 62.3 MiB 0.01 0.00 0.896632 -26.6731 -0.896632 0.896632 1.01 0.000270266 0.000248424 0.00535576 0.00493972 26 545 15 6.95648e+06 28951.4 503264. 1741.40 2.07 0.074246 0.0639801 24322 120374 -1 481 16 290 290 21220 5201 1.14723 1.14723 -30.8531 -1.14723 0 0 618332. 2139.56 0.20 0.02 0.17 -1 -1 0.20 0.00956601 0.00844827 16 2 12 12 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml adder_011bits.v common 6.07 vpr 62.29 MiB 0.03 6216 -1 -1 1 0.03 -1 -1 30016 -1 -1 3 23 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63784 23 12 83 84 1 55 38 17 17 289 -1 unnamed_device 23.8 MiB 0.04 198 1298 273 1012 13 62.3 MiB 0.02 0.00 0.907632 -28.5647 -0.907632 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0.03 0.22 -1 -1 0.24 0.0109102 0.00967308 19 2 14 14 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 4.99 vpr 62.43 MiB 0.02 6340 -1 -1 1 0.03 -1 -1 30156 -1 -1 3 27 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63924 27 14 97 98 1 66 44 17 17 289 -1 unnamed_device 23.9 MiB 0.04 180 3971 1477 2086 408 62.4 MiB 0.04 0.00 0.951632 -32.5735 -0.951632 0.951632 1.00 0.000331553 0.000304909 0.0184768 0.0170144 36 677 34 6.95648e+06 43427 648988. 2245.63 1.69 0.0808537 0.0710269 26050 158493 -1 479 36 638 638 44030 11892 1.21133 1.21133 -34.4716 -1.21133 0 0 828058. 2865.25 0.26 0.05 0.22 -1 -1 0.26 0.0226096 0.0198257 20 2 15 15 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml adder_014bits.v common 5.22 vpr 62.30 MiB 0.03 6472 -1 -1 1 0.03 -1 -1 30268 -1 -1 3 29 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63796 29 15 104 105 1 72 47 17 17 289 -1 unnamed_device 23.7 MiB 0.05 227 4331 1745 2561 25 62.3 MiB 0.04 0.00 0.962632 -36.3287 -0.962632 0.962632 1.02 0.00035448 0.000325727 0.0193523 0.0177854 36 789 39 6.95648e+06 43427 648988. 2245.63 1.96 0.102472 0.0898472 26050 158493 -1 644 21 474 474 83491 31666 1.26153 1.26153 -42.9574 -1.26153 0 0 828058. 2865.25 0.25 0.05 0.23 -1 -1 0.25 0.0153445 0.0135655 22 2 16 16 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml adder_015bits.v common 6.42 vpr 62.38 MiB 0.01 6456 -1 -1 1 0.03 -1 -1 30276 -1 -1 3 31 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63872 31 16 111 112 1 78 50 17 17 289 -1 unnamed_device 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on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65192 97 49 342 343 1 243 156 17 17 289 -1 unnamed_device 24.7 MiB 0.10 1600 30324 11596 17665 1063 63.7 MiB 0.20 0.00 2.41762 -168.85 -2.41762 2.41762 0.99 0.0012189 0.00113346 0.0914509 0.0849961 52 2765 24 6.95648e+06 144757 926341. 3205.33 5.79 0.458578 0.416464 29218 227130 -1 2519 17 1068 1068 118761 24238 1.49993 1.49993 -156.625 -1.49993 0 0 1.14541e+06 3963.36 0.35 0.10 0.35 -1 -1 0.35 0.0416608 0.0379877 73 2 50 50 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml adder_064bits.v common 12.07 vpr 64.49 MiB 0.03 6956 -1 -1 1 0.04 -1 -1 30328 -1 -1 13 129 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66040 129 65 454 455 1 324 207 17 17 289 -1 unnamed_device 25.4 MiB 0.08 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63608 25 13 90 91 1 60 41 17 17 289 -1 unnamed_device 23.6 MiB 0.02 340 1441 266 1110 65 62.1 MiB 0.02 0.00 0.901432 -33.1271 -0.901432 0.901432 0.99 0.000312456 0.000287804 0.00724621 0.00668238 34 752 16 6.99608e+06 44147 618332. 2139.56 1.48 0.0691239 0.060081 25762 151098 -1 707 15 318 318 34339 7519 1.17833 1.17833 -38.8894 -1.17833 0 0 787024. 2723.27 0.24 0.03 0.22 -1 -1 0.24 0.010303 0.00911183 19 2 14 14 0 0 -fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 4.92 vpr 62.22 MiB 0.01 6328 -1 -1 1 0.03 -1 -1 30080 -1 -1 3 27 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63716 27 14 97 98 1 66 44 17 17 289 -1 unnamed_device 23.7 MiB 0.02 178 3971 1404 1915 652 62.2 MiB 0.04 0.00 0.912432 -32.1713 -0.912432 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62792 11 6 34 40 1 23 19 17 17 289 -1 unnamed_device 22.6 MiB 0.01 171 94 40 54 0 61.3 MiB 0.01 0.00 1.02368 -16.6264 -1.02368 1.02368 0.96 0.000150084 0.000136484 0.00132734 0.00125 20 289 7 6.79088e+06 26944 414966. 1435.87 1.90 0.0145334 0.0126342 22510 95286 -1 266 5 64 74 4817 1223 1.02368 1.02368 -16.8849 -1.02368 0 0 503264. 1741.40 0.16 0.01 0.15 -1 -1 0.16 0.00329059 0.00301525 10 7 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_006bits.v common 3.63 vpr 61.30 MiB 0.02 5944 -1 -1 3 0.05 -1 -1 32032 -1 -1 2 13 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62776 13 7 41 48 1 30 22 17 17 289 -1 unnamed_device 22.7 MiB 0.01 78 532 122 389 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65484 129 65 454 455 1 329 211 17 17 289 -1 unnamed_device 25.0 MiB 0.13 1688 49117 18704 27900 2513 63.9 MiB 0.39 0.01 4.35372 -274.791 -4.35372 4.35372 0.99 0.0016391 0.00152441 0.138557 0.129324 36 3981 28 6.87369e+06 237555 648988. 2245.63 2.31 0.431598 0.395411 26050 158493 -1 3348 17 1626 1626 161860 37131 1.87697 1.87697 -215.085 -1.87697 0 0 828058. 2865.25 0.25 0.13 0.23 -1 -1 0.25 0.0558962 0.051049 130 2 66 66 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_005bits.v common 5.09 vpr 61.48 MiB 0.01 6404 -1 -1 1 0.02 -1 -1 30040 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62960 11 6 41 42 1 27 19 17 17 289 -1 unnamed_device 22.8 MiB 0.04 64 444 102 328 14 61.5 MiB 0.01 0.00 0.850273 -12.9291 -0.850273 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63048 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 22.9 MiB 0.05 144 1041 203 767 71 61.6 MiB 0.01 0.00 1.2326 -21.8949 -1.2326 1.2326 1.00 0.000218316 0.000200418 0.00572431 0.00525213 24 415 18 6.89349e+06 42281.5 470940. 1629.55 2.00 0.0431018 0.0372535 24034 113901 -1 396 8 135 135 15448 4273 1.12264 1.12264 -24.7204 -1.12264 0 0 586450. 2029.24 0.18 0.02 0.16 -1 -1 0.18 0.00519604 0.00465696 18 2 10 10 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_009bits.v common 4.81 vpr 61.85 MiB 0.02 6300 -1 -1 1 0.02 -1 -1 30240 -1 -1 3 19 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63332 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 23.1 MiB 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63584 37 19 132 133 1 89 61 17 17 289 -1 unnamed_device 23.6 MiB 0.07 389 3541 674 2740 127 62.1 MiB 0.03 0.00 1.70293 -53.0421 -1.70293 1.70293 1.01 0.000461074 0.000425981 0.0145987 0.013486 30 873 17 6.89349e+06 70469.2 556674. 1926.21 2.04 0.11842 0.103829 25186 138497 -1 796 13 362 362 22124 5809 1.12567 1.12567 -52.3224 -1.12567 0 0 706193. 2443.58 0.22 0.03 0.20 -1 -1 0.22 0.0131863 0.0116944 38 2 20 20 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 4.90 vpr 62.24 MiB 0.03 6368 -1 -1 1 0.03 -1 -1 30496 -1 -1 6 41 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63732 41 21 146 147 1 101 68 17 17 289 -1 unnamed_device 23.7 MiB 0.07 518 8624 2120 6023 481 62.2 MiB 0.07 0.00 1.72493 -63.2115 -1.72493 1.72493 1.01 0.000502665 0.00046437 0.032912 0.03043 34 1201 12 6.89349e+06 84563 618332. 2139.56 1.47 0.128077 0.113684 25762 151098 -1 1092 19 486 486 44758 10102 1.05732 1.05732 -60.475 -1.05732 0 0 787024. 2723.27 0.24 0.05 0.22 -1 -1 0.24 0.0191615 0.0169569 42 2 22 22 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 4.89 vpr 62.16 MiB 0.07 6400 -1 -1 1 0.03 -1 -1 30320 -1 -1 6 45 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63656 45 23 160 161 1 115 74 17 17 289 -1 unnamed_device 23.6 MiB 0.07 723 8754 3062 4670 1022 62.2 MiB 0.07 0.00 1.74693 -75.1597 -1.74693 1.74693 1.00 0.000548145 0.000506193 0.0322829 0.0297954 34 1449 13 6.89349e+06 84563 618332. 2139.56 1.51 0.136395 0.121126 25762 151098 -1 1323 17 566 566 61281 12665 1.18067 1.18067 -69.4326 -1.18067 0 0 787024. 2723.27 0.24 0.05 0.22 -1 -1 0.24 0.0192756 0.0171967 47 2 24 24 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_024bits.v common 4.97 vpr 62.20 MiB 0.03 6460 -1 -1 1 0.02 -1 -1 30324 -1 -1 7 49 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63696 49 25 174 175 1 124 81 17 17 289 -1 unnamed_device 23.6 MiB 0.10 626 7431 1738 5510 183 62.2 MiB 0.07 0.00 2.12926 -77.4465 -2.12926 2.12926 0.99 0.000597739 0.000552859 0.0265395 0.0245343 34 1418 16 6.89349e+06 98656.9 618332. 2139.56 1.51 0.143182 0.1274 25762 151098 -1 1247 15 537 537 47107 10808 1.35887 1.35887 -77.4553 -1.35887 0 0 787024. 2723.27 0.24 0.05 0.22 -1 -1 0.24 0.0186467 0.0166572 50 2 26 26 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 5.16 vpr 62.36 MiB 0.02 6424 -1 -1 1 0.03 -1 -1 30160 -1 -1 8 57 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63852 57 29 202 203 1 142 94 17 17 289 -1 unnamed_device 23.8 MiB 0.12 744 15004 6297 8531 176 62.4 MiB 0.11 0.00 2.17326 -95.1695 -2.17326 2.17326 1.00 0.00068394 0.000631618 0.0499335 0.0461505 34 1591 25 6.89349e+06 112751 618332. 2139.56 1.64 0.195702 0.175187 25762 151098 -1 1347 18 763 763 72750 17001 1.27767 1.27767 -84.9346 -1.27767 0 0 787024. 2723.27 0.24 0.06 0.22 -1 -1 0.24 0.0246571 0.0220987 58 2 30 30 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 5.09 vpr 62.41 MiB 0.02 6416 -1 -1 1 0.03 -1 -1 30360 -1 -1 9 65 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63908 65 33 230 231 1 165 107 17 17 289 -1 unnamed_device 23.7 MiB 0.09 917 16046 5086 9451 1509 62.4 MiB 0.12 0.00 2.57759 -114.077 -2.57759 2.57759 1.01 0.000794256 0.00073469 0.0524572 0.0485583 34 1955 15 6.89349e+06 126845 618332. 2139.56 1.64 0.207582 0.186274 25762 151098 -1 1772 11 686 686 59886 13353 1.43387 1.43387 -105.391 -1.43387 0 0 787024. 2723.27 0.24 0.05 0.22 -1 -1 0.24 0.0193739 0.0174416 66 2 34 34 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 5.87 vpr 63.18 MiB 0.03 6764 -1 -1 1 0.04 -1 -1 30372 -1 -1 13 97 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64700 97 49 342 343 1 247 159 17 17 289 -1 unnamed_device 24.3 MiB 0.13 1233 31119 11476 17865 1778 63.2 MiB 0.22 0.01 3.47425 -185.498 -3.47425 3.47425 1.01 0.00120524 0.00111939 0.0901849 0.0837306 34 2983 38 6.89349e+06 183220 618332. 2139.56 2.13 0.373536 0.33893 25762 151098 -1 2521 14 1152 1152 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odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 2.26 vpr 61.58 MiB 0.03 6444 -1 -1 2 0.05 -1 -1 31768 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63060 11 6 34 40 1 20 19 17 17 289 -1 unnamed_device 22.9 MiB 0.01 130 394 82 301 11 61.6 MiB 0.01 0.00 1.13885 -14.0146 -1.13885 1.13885 0.32 0.000122715 0.000111905 0.00236611 0.00216193 -1 -1 -1 -1 26 218 5 6.55708e+06 24110 477104. 1650.88 0.84 0.0245212 0.0201793 21022 109990 -1 206 5 43 48 4257 1028 1.13885 1.13885 -14.7223 -1.13885 0 0 585099. 2024.56 0.02 0.01 0.09 -1 -1 0.02 0.00260643 0.00236173 16 7 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.94 vpr 61.66 MiB 0.03 6308 -1 -1 3 0.06 -1 -1 32080 -1 -1 3 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63136 13 7 41 48 1 27 23 17 17 289 -1 unnamed_device 22.9 MiB 0.01 89 887 227 554 106 61.7 MiB 0.01 0.00 1.37725 -15.4804 -1.37725 1.37725 0.33 0.000148682 0.000136138 0.00420888 0.00384431 -1 -1 -1 -1 20 157 8 6.55708e+06 36165 394039. 1363.46 0.52 0.0125893 0.0108682 19870 87366 -1 153 6 78 88 3997 1739 1.25705 1.25705 -15.7895 -1.25705 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00296234 0.00265101 19 9 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.79 vpr 61.64 MiB 0.02 6372 -1 -1 3 0.05 -1 -1 32476 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63116 15 8 47 55 1 35 27 17 17 289 -1 unnamed_device 23.2 MiB 0.01 130 1227 294 745 188 61.6 MiB 0.04 0.00 1.23151 -17.8131 -1.23151 1.23151 0.31 0.000251661 0.000232432 0.00907333 0.00831964 -1 -1 -1 -1 26 323 11 6.55708e+06 48220 477104. 1650.88 0.33 0.0245422 0.0211268 21022 109990 -1 248 9 79 100 4761 1525 1.13885 1.13885 -18.5343 -1.13885 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.0039751 0.00350554 23 10 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.97 vpr 61.75 MiB 0.02 6292 -1 -1 3 0.06 -1 -1 32132 -1 -1 6 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63236 17 9 56 65 1 37 32 17 17 289 -1 unnamed_device 23.3 MiB 0.02 178 932 169 687 76 61.8 MiB 0.01 0.00 1.77705 -23.0458 -1.77705 1.77705 0.31 0.000174397 0.000161035 0.00373922 0.00346015 -1 -1 -1 -1 20 342 11 6.55708e+06 72330 394039. 1363.46 0.56 0.0159688 0.0137057 19870 87366 -1 328 13 123 161 9114 2904 1.77705 1.77705 -24.539 -1.77705 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00580726 0.00504644 26 14 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 2.15 vpr 62.00 MiB 0.03 6376 -1 -1 4 0.06 -1 -1 31884 -1 -1 6 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63492 19 10 60 70 1 46 35 17 17 289 -1 unnamed_device 23.6 MiB 0.02 186 1232 224 942 66 62.0 MiB 0.01 0.00 1.83817 -25.6813 -1.83817 1.83817 0.31 0.000184382 0.000170589 0.00452271 0.00419042 -1 -1 -1 -1 20 466 19 6.55708e+06 72330 394039. 1363.46 0.71 0.0279027 0.0235479 19870 87366 -1 393 15 214 298 11674 4307 2.03937 2.03937 -30.3326 -2.03937 0 0 477104. 1650.88 0.02 0.02 0.07 -1 -1 0.02 0.00672168 0.00579046 29 13 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 2.07 vpr 61.77 MiB 0.03 6324 -1 -1 4 0.06 -1 -1 31936 -1 -1 7 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63256 21 11 69 80 1 46 39 17 17 289 -1 unnamed_device 23.3 MiB 0.02 276 1359 263 1085 11 61.8 MiB 0.01 0.00 1.9859 -31.0743 -1.9859 1.9859 0.31 0.00021121 0.000195409 0.00496748 0.00458686 -1 -1 -1 -1 24 564 17 6.55708e+06 84385 448715. 1552.65 0.61 0.0325681 0.0275036 20734 103517 -1 514 9 133 201 13014 3345 1.7455 1.7455 -31.9552 -1.7455 0 0 554710. 1919.41 0.02 0.01 0.09 -1 -1 0.02 0.00525742 0.00461312 33 17 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 2.16 vpr 61.84 MiB 0.03 6428 -1 -1 5 0.06 -1 -1 32364 -1 -1 6 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63320 23 12 73 85 1 53 41 17 17 289 -1 unnamed_device 23.3 MiB 0.02 292 1441 261 1160 20 61.8 MiB 0.01 0.00 2.60682 -38.0792 -2.60682 2.60682 0.31 0.000219464 0.000203084 0.00513191 0.00474464 -1 -1 -1 -1 22 602 9 6.55708e+06 72330 420624. 1455.45 0.69 0.0348324 0.0294077 20158 92377 -1 535 10 166 220 13909 3706 2.48662 2.48662 -38.3511 -2.48662 0 0 500653. 1732.36 0.02 0.02 0.08 -1 -1 0.02 0.00585718 0.00513458 34 16 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 2.17 vpr 61.76 MiB 0.03 6308 -1 -1 5 0.06 -1 -1 31864 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63240 25 13 82 95 1 61 46 17 17 289 -1 unnamed_device 23.2 MiB 0.03 391 1932 388 1396 148 61.8 MiB 0.02 0.00 2.1851 -40.0296 -2.1851 2.1851 0.31 0.000241424 0.000223353 0.00638335 0.00590312 -1 -1 -1 -1 26 680 12 6.55708e+06 96440 477104. 1650.88 0.69 0.0630077 0.0530182 21022 109990 -1 649 11 188 284 12781 3584 2.1851 2.1851 -42.0607 -2.1851 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00671151 0.00588002 39 20 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.13 vpr 61.99 MiB 0.03 6376 -1 -1 5 0.06 -1 -1 32084 -1 -1 10 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63476 27 14 91 105 1 72 51 17 17 289 -1 unnamed_device 23.3 MiB 0.03 462 2683 577 1816 290 62.0 MiB 0.02 0.00 2.59656 -45.1104 -2.59656 2.59656 0.28 0.000274162 0.00025416 0.00861471 0.00797451 -1 -1 -1 -1 24 752 11 6.55708e+06 120550 448715. 1552.65 0.60 0.0418406 0.0358196 20734 103517 -1 739 14 209 307 17867 4574 2.3837 2.3837 -46.1866 -2.3837 0 0 554710. 1919.41 0.02 0.02 0.09 -1 -1 0.02 0.00866172 0.00751515 44 24 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.93 vpr 62.11 MiB 0.03 6296 -1 -1 6 0.06 -1 -1 31788 -1 -1 10 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63604 29 15 95 110 1 74 54 17 17 289 -1 unnamed_device 23.4 MiB 0.03 397 3318 653 2620 45 62.1 MiB 0.03 0.00 2.92362 -49.6372 -2.92362 2.92362 0.31 0.000285151 0.000264394 0.0100796 0.00934229 -1 -1 -1 -1 26 785 14 6.55708e+06 120550 477104. 1650.88 0.40 0.0406659 0.0350168 21022 109990 -1 694 10 212 341 15952 4689 2.76422 2.76422 -49.2109 -2.76422 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.0071525 0.00625742 46 23 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.29 vpr 61.78 MiB 0.03 6372 -1 -1 6 0.06 -1 -1 31792 -1 -1 10 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63260 31 16 104 120 1 74 57 17 17 289 -1 unnamed_device 23.1 MiB 0.03 388 2673 538 2060 75 61.8 MiB 0.02 0.00 2.4235 -49.7792 -2.4235 2.4235 0.33 0.000314307 0.000291768 0.00868864 0.00806347 -1 -1 -1 -1 26 798 10 6.55708e+06 120550 477104. 1650.88 0.75 0.0693169 0.05865 21022 109990 -1 689 13 250 353 19015 5274 2.1831 2.1831 -49.5094 -2.1831 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.00917228 0.00796703 50 27 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.37 vpr 61.91 MiB 0.03 6420 -1 -1 7 0.06 -1 -1 31836 -1 -1 10 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63400 33 17 108 125 1 77 60 17 17 289 -1 unnamed_device 23.2 MiB 0.03 484 3570 643 2715 212 61.9 MiB 0.03 0.00 3.41468 -59.8938 -3.41468 3.41468 0.31 0.000321271 0.000298431 0.0107363 0.00997272 -1 -1 -1 -1 26 947 11 6.55708e+06 120550 477104. 1650.88 0.84 0.079649 0.0676146 21022 109990 -1 849 9 238 356 22359 5793 3.41468 3.41468 -62.6758 -3.41468 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00804668 0.00715803 52 26 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.43 vpr 62.03 MiB 0.03 6348 -1 -1 7 0.06 -1 -1 32444 -1 -1 13 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63516 37 19 127 146 1 96 69 17 17 289 -1 unnamed_device 22.9 MiB 0.04 576 5709 1280 3850 579 62.0 MiB 0.04 0.00 2.95316 -65.5347 -2.95316 2.95316 0.31 0.000369839 0.00034352 0.0160103 0.014861 -1 -1 -1 -1 26 1011 13 6.55708e+06 156715 477104. 1650.88 0.88 0.0900938 0.0771875 21022 109990 -1 976 13 305 456 21173 5968 2.8997 2.8997 -67.669 -2.8997 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.0107541 0.00938794 63 35 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 1.97 vpr 62.04 MiB 0.03 6324 -1 -1 8 0.07 -1 -1 32080 -1 -1 14 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63524 41 21 139 160 1 106 76 17 17 289 -1 unnamed_device 22.8 MiB 0.05 691 4076 776 3111 189 62.0 MiB 0.03 0.00 2.9395 -74.3337 -2.9395 2.9395 0.31 0.000402257 0.000373288 0.0114107 0.010609 -1 -1 -1 -1 26 1257 13 6.55708e+06 168770 477104. 1650.88 0.38 0.0537184 0.0466845 21022 109990 -1 1170 8 268 383 24156 6017 2.9395 2.9395 -78.3932 -2.9395 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.00874971 0.00779802 67 37 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.55 vpr 62.20 MiB 0.03 6348 -1 -1 9 0.08 -1 -1 32332 -1 -1 14 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63696 45 23 152 175 1 114 82 17 17 289 -1 unnamed_device 22.9 MiB 0.05 656 5778 1200 4246 332 62.2 MiB 0.04 0.00 3.50896 -86.4899 -3.50896 3.50896 0.31 0.000435088 0.00040467 0.0154814 0.0143823 -1 -1 -1 -1 26 1263 12 6.55708e+06 168770 477104. 1650.88 0.95 0.113918 0.0981967 21022 109990 -1 1167 13 370 556 29616 8301 3.30776 3.30776 -86.348 -3.30776 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.0125489 0.0110314 73 40 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.53 vpr 62.25 MiB 0.03 6328 -1 -1 10 0.06 -1 -1 32632 -1 -1 15 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63740 49 25 165 190 1 123 89 17 17 289 -1 unnamed_device 22.9 MiB 0.05 770 12761 4334 6906 1521 62.2 MiB 0.08 0.00 4.11762 -102.077 -4.11762 4.11762 0.31 0.000469597 0.000436378 0.0316911 0.0294372 -1 -1 -1 -1 26 1420 16 6.55708e+06 180825 477104. 1650.88 0.96 0.113359 0.0994 21022 109990 -1 1279 14 412 589 33508 9008 3.87722 3.87722 -102.053 -3.87722 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.0142206 0.0125056 79 43 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.51 vpr 62.38 MiB 0.02 6300 -1 -1 11 0.07 -1 -1 32540 -1 -1 21 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63876 57 29 199 228 1 148 107 17 17 289 -1 unnamed_device 23.1 MiB 0.05 683 9215 2009 6469 737 62.4 MiB 0.06 0.00 5.01553 -132.266 -5.01553 5.01553 0.31 0.000568179 0.000529341 0.0225074 0.0209121 -1 -1 -1 -1 28 1411 13 6.55708e+06 253155 500653. 1732.36 0.87 0.141376 0.12279 21310 115450 -1 1240 9 447 590 31672 10140 4.76548 4.76548 -132.308 -4.76548 0 0 612192. 2118.31 0.03 0.03 0.10 -1 -1 0.03 0.0128546 0.0114383 96 57 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.16 vpr 62.64 MiB 0.03 6340 -1 -1 13 0.08 -1 -1 31956 -1 -1 20 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64148 65 33 224 257 1 164 118 17 17 289 -1 unnamed_device 22.9 MiB 0.06 989 18614 4289 12324 2001 62.6 MiB 0.10 0.00 5.28408 -156.845 -5.28408 5.28408 0.31 0.000640307 0.000596942 0.0431822 0.040187 -1 -1 -1 -1 28 1859 11 6.55708e+06 241100 500653. 1732.36 0.43 0.108776 0.0969116 21310 115450 -1 1667 10 458 639 35378 9665 5.04368 5.04368 -155.125 -5.04368 0 0 612192. 2118.31 0.03 0.04 0.10 -1 -1 0.03 0.0153278 0.0136288 106 62 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.18 vpr 62.82 MiB 0.04 6404 -1 -1 19 0.10 -1 -1 32408 -1 -1 34 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64332 97 49 340 389 1 260 180 17 17 289 -1 unnamed_device 23.8 MiB 0.10 1331 34724 8061 22998 3665 62.8 MiB 0.17 0.00 7.79296 -292.17 -7.79296 7.79296 0.31 0.000989413 0.000924399 0.0705726 0.0658766 -1 -1 -1 -1 28 2799 13 6.55708e+06 409870 500653. 1732.36 1.25 0.295876 0.264001 21310 115450 -1 2447 11 761 1108 56440 16024 7.48193 7.48193 -290.119 -7.48193 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0245827 0.0221141 165 98 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.08 vpr 63.86 MiB 0.03 6696 -1 -1 26 0.12 -1 -1 32676 -1 -1 42 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65388 129 65 454 519 1 343 236 17 17 289 -1 unnamed_device 24.2 MiB 0.12 1865 57827 16105 35644 6078 63.9 MiB 0.28 0.00 10.762 -492.423 -10.762 10.762 0.31 0.00132955 0.00123905 0.109086 0.101946 -1 -1 -1 -1 32 3613 18 6.55708e+06 506310 554710. 1919.41 0.88 0.330173 0.298856 22174 131602 -1 3191 11 997 1345 80150 22909 10.2468 10.2468 -479.947 -10.2468 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0334881 0.0303791 222 132 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.46 abc 29.31 MiB 0.03 6768 -1 -1 1 0.02 -1 -1 30016 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24016 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.40 abc 29.35 MiB 0.03 6568 -1 -1 1 0.02 -1 -1 30056 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23972 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.43 abc 29.32 MiB 0.02 6704 -1 -1 1 0.02 -1 -1 30028 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24232 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.44 abc 29.37 MiB 0.03 6724 -1 -1 1 0.02 -1 -1 30076 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23992 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.44 abc 29.43 MiB 0.03 6712 -1 -1 1 0.02 -1 -1 30132 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24400 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.36 abc 29.25 MiB 0.01 6568 -1 -1 1 0.02 -1 -1 29948 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24076 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.45 abc 29.25 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 29948 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24104 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.46 abc 29.45 MiB 0.03 6724 -1 -1 1 0.02 -1 -1 30152 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24160 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.46 abc 29.42 MiB 0.02 6732 -1 -1 1 0.02 -1 -1 30128 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23976 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.44 abc 29.38 MiB 0.02 6752 -1 -1 1 0.03 -1 -1 30088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24060 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.42 abc 29.38 MiB 0.03 6720 -1 -1 1 0.02 -1 -1 30080 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24464 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.47 abc 29.64 MiB 0.04 6568 -1 -1 1 0.03 -1 -1 30352 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24000 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.45 abc 29.68 MiB 0.02 6704 -1 -1 1 0.02 -1 -1 30392 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24308 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.43 abc 29.63 MiB 0.02 6708 -1 -1 1 0.03 -1 -1 30340 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23928 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.43 abc 29.68 MiB 0.04 6816 -1 -1 1 0.02 -1 -1 30392 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24268 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.49 abc 29.64 MiB 0.04 6588 -1 -1 1 0.03 -1 -1 30352 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24092 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 7 7 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.47 abc 29.68 MiB 0.03 6716 -1 -1 1 0.02 -1 -1 30392 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24088 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 8 8 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.48 abc 29.60 MiB 0.03 6760 -1 -1 1 0.03 -1 -1 30308 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24136 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 9 9 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.49 abc 29.75 MiB 0.03 6572 -1 -1 1 0.03 -1 -1 30460 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24012 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 13 13 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.45 abc 29.75 MiB 0.04 6852 -1 -1 1 0.04 -1 -1 30464 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24180 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 17 17 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.46 abc 29.29 MiB 0.02 6708 -1 -1 1 0.02 -1 -1 29988 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23656 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.41 abc 29.41 MiB 0.01 6716 -1 -1 1 0.02 -1 -1 30112 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24148 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.46 abc 29.51 MiB 0.03 6712 -1 -1 1 0.02 -1 -1 30216 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23796 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.43 abc 29.29 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 29996 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23912 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.42 abc 29.36 MiB 0.02 6712 -1 -1 1 0.02 -1 -1 30064 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23736 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.43 abc 29.29 MiB 0.03 6616 -1 -1 1 0.02 -1 -1 29992 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23772 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.44 abc 29.33 MiB 0.02 6652 -1 -1 1 0.02 -1 -1 30036 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23820 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.45 abc 29.42 MiB 0.02 6780 -1 -1 1 0.03 -1 -1 30128 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23864 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.47 abc 29.43 MiB 0.02 6708 -1 -1 1 0.03 -1 -1 30136 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23904 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.44 abc 29.49 MiB 0.02 6736 -1 -1 1 0.03 -1 -1 30200 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24060 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.47 abc 29.34 MiB 0.02 6708 -1 -1 1 0.02 -1 -1 30048 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23880 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.46 abc 29.67 MiB 0.02 6716 -1 -1 1 0.02 -1 -1 30384 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23820 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.49 abc 29.54 MiB 0.03 6696 -1 -1 1 0.03 -1 -1 30244 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24196 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.50 abc 29.68 MiB 0.03 6820 -1 -1 1 0.03 -1 -1 30396 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23788 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.49 abc 29.59 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30304 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23880 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.49 abc 29.71 MiB 0.03 6648 -1 -1 1 0.02 -1 -1 30428 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23816 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 7 7 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.51 abc 29.62 MiB 0.04 6588 -1 -1 1 0.02 -1 -1 30332 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23896 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 8 8 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.49 abc 29.64 MiB 0.03 6708 -1 -1 1 0.03 -1 -1 30348 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23884 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 9 9 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.51 abc 29.68 MiB 0.04 6620 -1 -1 1 0.03 -1 -1 30388 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23796 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 13 13 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.57 abc 29.66 MiB 0.04 6816 -1 -1 1 0.03 -1 -1 30372 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24136 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 17 17 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.88 vpr 61.86 MiB 0.03 6576 -1 -1 1 0.02 -1 -1 30168 -1 -1 3 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63344 11 6 41 42 1 26 20 17 17 289 -1 unnamed_device 23.1 MiB 0.01 136 263 59 203 1 61.9 MiB 0.01 0.00 0.803048 -13.0336 -0.803048 0.803048 0.31 0.000104173 9.5074e-05 0.00135463 0.00124089 -1 -1 -1 -1 20 227 9 6.64007e+06 37674 394039. 1363.46 0.49 0.00682042 0.00591582 20530 87850 -1 213 13 70 70 3370 1092 1.04345 1.04345 -14.39 -1.04345 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00377977 0.00328557 16 2 7 7 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 2.08 vpr 61.92 MiB 0.03 6604 -1 -1 1 0.02 -1 -1 30132 -1 -1 4 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63408 13 7 48 49 1 32 24 17 17 289 -1 unnamed_device 23.5 MiB 0.01 145 636 105 517 14 61.9 MiB 0.01 0.00 0.825048 -14.6191 -0.825048 0.825048 0.31 0.000122313 0.00011203 0.00266971 0.00244996 -1 -1 -1 -1 22 275 10 6.64007e+06 50232 420624. 1455.45 0.69 0.0223373 0.0186159 20818 92861 -1 235 15 108 108 5032 1552 0.912248 0.912248 -15.1079 -0.912248 0 0 500653. 1732.36 0.02 0.01 0.08 -1 -1 0.02 0.00472477 0.0040916 19 2 8 8 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.73 vpr 61.98 MiB 0.03 6804 -1 -1 1 0.02 -1 -1 30132 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63464 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 23.5 MiB 0.01 227 867 163 655 49 62.0 MiB 0.01 0.00 1.18536 -18.0665 -1.18536 1.18536 0.31 0.000140047 0.000128876 0.00345801 0.00317978 -1 -1 -1 -1 26 350 13 6.64007e+06 50232 477104. 1650.88 0.33 0.0189662 0.0160174 21682 110474 -1 351 10 125 125 6106 1854 0.954248 0.954248 -19.5944 -0.954248 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.00412996 0.00363203 22 2 9 9 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 2.03 vpr 61.89 MiB 0.03 6580 -1 -1 1 0.02 -1 -1 30028 -1 -1 5 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63380 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 23.5 MiB 0.02 174 943 169 760 14 61.9 MiB 0.01 0.00 1.19636 -19.914 -1.19636 1.19636 0.31 0.000158116 0.000145773 0.00358447 0.00330728 -1 -1 -1 -1 20 349 19 6.64007e+06 62790 394039. 1363.46 0.65 0.0185526 0.0157803 20530 87850 -1 320 10 155 155 7334 2477 1.07445 1.07445 -22.2008 -1.07445 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00446293 0.00391146 25 2 10 10 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 2.45 vpr 62.06 MiB 0.03 6640 -1 -1 1 0.02 -1 -1 30024 -1 -1 5 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63548 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 23.6 MiB 0.02 223 1134 190 934 10 62.1 MiB 0.01 0.00 1.20736 -23.2962 -1.20736 1.20736 0.31 0.000176833 0.000163455 0.00418602 0.00386617 -1 -1 -1 -1 28 410 12 6.64007e+06 62790 500653. 1732.36 0.99 0.037395 0.0312357 21970 115934 -1 362 11 131 131 7334 2115 0.932248 0.932248 -23.521 -0.932248 0 0 612192. 2118.31 0.03 0.01 0.10 -1 -1 0.03 0.00506579 0.00442078 28 2 11 11 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 2.04 vpr 62.12 MiB 0.03 6684 -1 -1 1 0.02 -1 -1 30132 -1 -1 6 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63608 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 23.5 MiB 0.02 323 1298 247 984 67 62.1 MiB 0.01 0.00 1.21836 -27.8009 -1.21836 1.21836 0.31 0.000202917 0.0001884 0.00461098 0.00426552 -1 -1 -1 -1 20 523 16 6.64007e+06 75348 394039. 1363.46 0.58 0.0203965 0.0174694 20530 87850 -1 509 12 155 155 10820 2929 0.998248 0.998248 -29.6258 -0.998248 0 0 477104. 1650.88 0.02 0.02 0.08 -1 -1 0.02 0.00641472 0.00562137 31 2 12 12 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.93 vpr 62.10 MiB 0.03 6704 -1 -1 1 0.02 -1 -1 30012 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63592 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 23.5 MiB 0.02 205 1770 299 1445 26 62.1 MiB 0.02 0.00 1.22936 -26.9843 -1.22936 1.22936 0.31 0.000145679 0.000130774 0.00573339 0.00531444 -1 -1 -1 -1 20 438 14 6.64007e+06 87906 394039. 1363.46 0.50 0.0189757 0.0164845 20530 87850 -1 382 11 177 177 8797 3204 1.11845 1.11845 -29.7081 -1.11845 0 0 477104. 1650.88 0.02 0.02 0.07 -1 -1 0.02 0.00584345 0.00509062 34 2 13 13 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.86 vpr 62.20 MiB 0.03 6616 -1 -1 1 0.02 -1 -1 29976 -1 -1 7 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63696 25 13 90 91 1 61 45 17 17 289 -1 unnamed_device 23.6 MiB 0.02 401 2525 518 1825 182 62.2 MiB 0.02 0.00 1.24036 -33.9356 -1.24036 1.24036 0.31 0.000224977 0.000208196 0.00775309 0.00718717 -1 -1 -1 -1 26 636 13 6.64007e+06 87906 477104. 1650.88 0.35 0.0327664 0.0282301 21682 110474 -1 602 8 158 158 11379 2754 0.889048 0.889048 -33.2549 -0.889048 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.00512806 0.00452575 37 2 14 14 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 1.84 vpr 62.09 MiB 0.03 6756 -1 -1 1 0.02 -1 -1 29980 -1 -1 8 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63576 27 14 97 98 1 67 49 17 17 289 -1 unnamed_device 23.4 MiB 0.02 262 2185 359 1806 20 62.1 MiB 0.02 0.00 1.25136 -32.6648 -1.25136 1.25136 0.31 0.000237796 0.00022075 0.00653957 0.00606642 -1 -1 -1 -1 26 537 12 6.64007e+06 100464 477104. 1650.88 0.35 0.0315952 0.0270894 21682 110474 -1 504 18 302 302 16010 5657 0.976248 0.976248 -33.9775 -0.976248 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00896876 0.00771322 40 2 15 15 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 2.36 vpr 62.20 MiB 0.03 6684 -1 -1 1 0.02 -1 -1 30316 -1 -1 8 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63696 29 15 104 105 1 73 52 17 17 289 -1 unnamed_device 23.6 MiB 0.02 394 3059 656 2338 65 62.2 MiB 0.03 0.00 1.26236 -37.9697 -1.26236 1.26236 0.31 0.000254084 0.000235264 0.00875769 0.00811532 -1 -1 -1 -1 26 742 12 6.64007e+06 100464 477104. 1650.88 0.86 0.0511371 0.0435734 21682 110474 -1 657 12 218 218 13114 3793 0.956248 0.956248 -37.9684 -0.956248 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.00724257 0.00634647 43 2 16 16 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 1.84 vpr 62.20 MiB 0.03 6604 -1 -1 1 0.02 -1 -1 30312 -1 -1 9 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63688 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 23.4 MiB 0.03 368 2838 548 2263 27 62.2 MiB 0.03 0.00 1.62267 -39.2436 -1.62267 1.62267 0.31 0.000272415 0.000252766 0.00798727 0.00740779 -1 -1 -1 -1 26 687 12 6.64007e+06 113022 477104. 1650.88 0.35 0.0363444 0.0313419 21682 110474 -1 634 10 243 243 17614 5237 0.964048 0.964048 -39.834 -0.964048 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00684108 0.00601986 46 2 17 17 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 1.89 vpr 62.15 MiB 0.03 6756 -1 -1 1 0.02 -1 -1 30296 -1 -1 9 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63640 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 23.2 MiB 0.03 441 2681 480 2040 161 62.1 MiB 0.03 0.00 1.63367 -43.1429 -1.63367 1.63367 0.31 0.000290913 0.000270625 0.00768241 0.00713958 -1 -1 -1 -1 26 842 14 6.64007e+06 113022 477104. 1650.88 0.38 0.0390819 0.0336684 21682 110474 -1 757 11 300 300 18950 5356 1.20445 1.20445 -46.9048 -1.20445 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.00764167 0.00669687 49 2 18 18 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.91 vpr 62.29 MiB 0.03 6832 -1 -1 1 0.02 -1 -1 30464 -1 -1 11 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63788 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 23.3 MiB 0.03 388 3603 641 2930 32 62.3 MiB 0.03 0.00 1.65567 -48.0323 -1.65567 1.65567 0.31 0.000336788 0.000314337 0.00967818 0.00901659 -1 -1 -1 -1 26 736 12 6.64007e+06 138138 477104. 1650.88 0.37 0.0439734 0.0379806 21682 110474 -1 650 11 285 285 15076 5113 1.05125 1.05125 -46.6701 -1.05125 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00852096 0.00742981 55 2 20 20 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.50 vpr 62.61 MiB 0.03 6636 -1 -1 1 0.02 -1 -1 30424 -1 -1 12 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64108 41 21 146 147 1 102 74 17 17 289 -1 unnamed_device 23.4 MiB 0.03 577 4104 822 3220 62 62.6 MiB 0.04 0.00 1.67767 -57.0444 -1.67767 1.67767 0.31 0.000362725 0.000337742 0.0106104 0.00987595 -1 -1 -1 -1 28 1040 17 6.64007e+06 150696 500653. 1732.36 0.95 0.0980832 0.0837458 21970 115934 -1 940 15 382 382 25658 7026 1.10745 1.10745 -54.7506 -1.10745 0 0 612192. 2118.31 0.03 0.03 0.10 -1 -1 0.03 0.0114861 0.00998555 61 2 22 22 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.05 vpr 62.53 MiB 0.04 6804 -1 -1 1 0.02 -1 -1 30312 -1 -1 13 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64032 45 23 160 161 1 114 81 17 17 289 -1 unnamed_device 23.3 MiB 0.03 761 9356 3852 5449 55 62.5 MiB 0.06 0.00 1.69967 -67.3409 -1.69967 1.69967 0.31 0.000389848 0.000362773 0.021996 0.0204828 -1 -1 -1 -1 28 1269 16 6.64007e+06 163254 500653. 1732.36 0.48 0.0649668 0.0571778 21970 115934 -1 1148 15 446 446 38197 9429 1.09525 1.09525 -62.8914 -1.09525 0 0 612192. 2118.31 0.03 0.03 0.10 -1 -1 0.03 0.0120875 0.0105482 67 2 24 24 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.81 vpr 62.48 MiB 0.02 6692 -1 -1 1 0.02 -1 -1 30456 -1 -1 14 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63980 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 23.2 MiB 0.04 813 11593 4672 6864 57 62.5 MiB 0.08 0.00 2.07098 -74.8771 -2.07098 2.07098 0.31 0.000425735 0.000396472 0.0264043 0.0245563 -1 -1 -1 -1 32 1237 11 6.64007e+06 175812 554710. 1919.41 1.18 0.102629 0.0897834 22834 132086 -1 1121 12 325 325 22310 5834 1.08305 1.08305 -65.8737 -1.08305 0 0 701300. 2426.64 0.03 0.03 0.11 -1 -1 0.03 0.0112433 0.00991557 73 2 26 26 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.11 vpr 62.69 MiB 0.03 6640 -1 -1 1 0.03 -1 -1 29968 -1 -1 17 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 57 29 202 203 1 143 103 17 17 289 -1 unnamed_device 23.3 MiB 0.04 935 15045 4530 8759 1756 62.7 MiB 0.09 0.00 2.11498 -89.4948 -2.11498 2.11498 0.31 0.000487016 0.000453823 0.0318696 0.029688 -1 -1 -1 -1 28 1595 16 6.64007e+06 213486 500653. 1732.36 0.46 0.0856085 0.0761532 21970 115934 -1 1379 14 443 443 34247 8513 1.21425 1.21425 -81.6596 -1.21425 0 0 612192. 2118.31 0.03 0.04 0.10 -1 -1 0.03 0.0142171 0.0125697 85 2 30 30 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.22 vpr 62.92 MiB 0.03 6704 -1 -1 1 0.03 -1 -1 30352 -1 -1 19 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64428 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 23.3 MiB 0.05 1122 18421 7032 10116 1273 62.9 MiB 0.11 0.00 2.50829 -108.018 -2.50829 2.50829 0.31 0.000566532 0.000528562 0.0381144 0.0355701 -1 -1 -1 -1 32 1704 14 6.64007e+06 238602 554710. 1919.41 0.47 0.0984369 0.0878945 22834 132086 -1 1535 11 465 465 38655 9331 1.18005 1.18005 -90.2429 -1.18005 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0138037 0.0122711 97 2 34 34 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.27 vpr 63.12 MiB 0.04 6704 -1 -1 1 0.03 -1 -1 30360 -1 -1 29 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64640 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 24.0 MiB 0.05 1707 39295 14344 22265 2686 63.1 MiB 0.23 0.00 3.38291 -181.168 -3.38291 3.38291 0.31 0.000869138 0.000815304 0.0720204 0.0674679 -1 -1 -1 -1 32 2666 14 6.64007e+06 364182 554710. 1919.41 1.40 0.256234 0.230504 22834 132086 -1 2405 18 776 776 67569 16733 1.47225 1.47225 -144.521 -1.47225 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0297577 0.0266197 145 2 50 50 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 2.83 vpr 63.39 MiB 0.03 6856 -1 -1 1 0.03 -1 -1 30340 -1 -1 39 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 24.4 MiB 0.09 2035 55365 19341 31922 4102 63.4 MiB 0.35 0.01 4.25753 -263.271 -4.25753 4.25753 0.31 0.00120102 0.00112888 0.09601 0.0902685 -1 -1 -1 -1 32 3291 15 6.64007e+06 489762 554710. 1919.41 0.63 0.229587 0.210068 22834 132086 -1 2910 19 1014 1014 86802 22344 1.61205 1.61205 -187.768 -1.61205 0 0 701300. 2426.64 0.03 0.10 0.11 -1 -1 0.03 0.0431002 0.038877 193 2 66 66 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.86 vpr 61.86 MiB 0.03 6576 -1 -1 1 0.02 -1 -1 30080 -1 -1 3 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63348 11 6 41 42 1 26 20 17 17 289 -1 unnamed_device 23.1 MiB 0.01 122 290 73 215 2 61.9 MiB 0.01 0.00 0.803048 -13.1372 -0.803048 0.803048 0.31 0.000104501 9.5109e-05 0.00144755 0.00132503 -1 -1 -1 -1 20 207 12 6.65987e+06 38034 394039. 1363.46 0.49 0.00728444 0.00630178 20530 87850 -1 188 9 73 73 3633 1144 0.922189 0.922189 -13.6636 -0.922189 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0031618 0.00280442 16 2 7 7 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.64 vpr 61.76 MiB 0.03 6768 -1 -1 1 0.02 -1 -1 30076 -1 -1 4 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63244 13 7 48 49 1 32 24 17 17 289 -1 unnamed_device 23.4 MiB 0.01 147 636 105 515 16 61.8 MiB 0.01 0.00 0.825048 -14.6534 -0.825048 0.825048 0.31 0.000122233 0.000112014 0.00268088 0.00245979 -1 -1 -1 -1 20 277 14 6.65987e+06 50712 394039. 1363.46 0.25 0.00752938 0.00664726 20530 87850 -1 231 8 84 84 5397 1657 0.901248 0.901248 -14.9767 -0.901248 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00337804 0.00300772 19 2 8 8 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 2.07 vpr 61.85 MiB 0.03 6640 -1 -1 1 0.02 -1 -1 30144 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63332 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 23.4 MiB 0.01 238 867 167 635 65 61.8 MiB 0.01 0.00 1.18536 -19.544 -1.18536 1.18536 0.32 0.000140851 0.000129741 0.00346244 0.0031901 -1 -1 -1 -1 20 420 8 6.65987e+06 50712 394039. 1363.46 0.64 0.0160163 0.0136691 20530 87850 -1 388 9 145 145 9151 2592 0.954248 0.954248 -21.1559 -0.954248 0 0 477104. 1650.88 0.02 0.01 0.09 -1 -1 0.02 0.00395321 0.00349714 22 2 9 9 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.96 vpr 61.82 MiB 0.01 6696 -1 -1 1 0.02 -1 -1 30004 -1 -1 5 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 23.4 MiB 0.01 172 895 165 716 14 61.8 MiB 0.01 0.00 1.19636 -19.7595 -1.19636 1.19636 0.32 0.000159483 0.000147394 0.00345089 0.00318641 -1 -1 -1 -1 20 361 13 6.65987e+06 63390 394039. 1363.46 0.57 0.0164468 0.0140398 20530 87850 -1 334 13 193 193 9618 3193 0.954248 0.954248 -21.3594 -0.954248 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00525668 0.00456049 25 2 10 10 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 2.36 vpr 62.02 MiB 0.02 6696 -1 -1 1 0.02 -1 -1 30008 -1 -1 5 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63512 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 23.5 MiB 0.01 220 1189 203 975 11 62.0 MiB 0.01 0.00 1.20736 -23.2065 -1.20736 1.20736 0.32 0.000176161 0.000162967 0.00434767 0.00401623 -1 -1 -1 -1 32 402 14 6.65987e+06 63390 554710. 1919.41 0.91 0.0374954 0.0312611 22834 132086 -1 323 9 92 92 4553 1340 0.757848 0.757848 -21.8538 -0.757848 0 0 701300. 2426.64 0.03 0.01 0.11 -1 -1 0.03 0.00454231 0.0040016 28 2 11 11 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 2.12 vpr 61.91 MiB 0.03 6696 -1 -1 1 0.02 -1 -1 30004 -1 -1 6 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63396 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 23.3 MiB 0.02 319 1424 271 1064 89 61.9 MiB 0.02 0.00 1.21836 -27.4574 -1.21836 1.21836 0.34 0.000195523 0.000181053 0.00506221 0.00469157 -1 -1 -1 -1 20 564 13 6.65987e+06 76068 394039. 1363.46 0.67 0.0207312 0.0178612 20530 87850 -1 505 7 127 127 8462 2321 0.878048 0.878048 -27.7026 -0.878048 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00445217 0.00395426 31 2 12 12 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 2.28 vpr 62.03 MiB 0.03 6560 -1 -1 1 0.02 -1 -1 30128 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63516 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 23.3 MiB 0.02 230 1554 244 1300 10 62.0 MiB 0.02 0.00 1.22936 -27.3766 -1.22936 1.22936 0.31 0.000212276 0.000196636 0.00515723 0.00478111 -1 -1 -1 -1 28 442 9 6.65987e+06 88746 500653. 1732.36 0.81 0.048974 0.0409901 21970 115934 -1 413 11 185 185 9296 3104 0.900048 0.900048 -28.4777 -0.900048 0 0 612192. 2118.31 0.03 0.02 0.10 -1 -1 0.03 0.00596745 0.00522525 34 2 13 13 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.90 vpr 62.18 MiB 0.02 6636 -1 -1 1 0.02 -1 -1 30072 -1 -1 7 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63672 25 13 90 91 1 61 45 17 17 289 -1 unnamed_device 23.5 MiB 0.02 409 3485 835 2303 347 62.2 MiB 0.03 0.00 1.24036 -33.7953 -1.24036 1.24036 0.31 0.000224442 0.000207614 0.0104748 0.0096921 -1 -1 -1 -1 26 637 8 6.65987e+06 88746 477104. 1650.88 0.39 0.0360189 0.031088 21682 110474 -1 624 11 212 212 14386 3643 0.911048 0.911048 -33.6091 -0.911048 0 0 585099. 2024.56 0.03 0.02 0.13 -1 -1 0.03 0.00647834 0.00570097 37 2 14 14 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.35 vpr 61.94 MiB 0.03 6756 -1 -1 1 0.02 -1 -1 30028 -1 -1 8 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63428 27 14 97 98 1 67 49 17 17 289 -1 unnamed_device 23.3 MiB 0.02 262 2185 395 1761 29 61.9 MiB 0.02 0.00 1.25136 -32.6942 -1.25136 1.25136 0.31 0.000238926 0.00022177 0.00659082 0.00611604 -1 -1 -1 -1 26 531 16 6.65987e+06 101424 477104. 1650.88 0.86 0.0704766 0.0570241 21682 110474 -1 471 16 277 277 14113 4827 1.02145 1.02145 -32.5992 -1.02145 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00833727 0.00721634 40 2 15 15 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.83 vpr 62.01 MiB 0.03 6712 -1 -1 1 0.02 -1 -1 30348 -1 -1 8 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63496 29 15 104 105 1 73 52 17 17 289 -1 unnamed_device 23.4 MiB 0.02 445 2380 471 1861 48 62.0 MiB 0.02 0.00 1.26236 -39.246 -1.26236 1.26236 0.31 0.000254392 0.000235531 0.00697532 0.00646239 -1 -1 -1 -1 26 753 15 6.65987e+06 101424 477104. 1650.88 0.36 0.0348818 0.0300011 21682 110474 -1 714 9 257 257 18102 4810 0.933048 0.933048 -38.8566 -0.933048 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.00607428 0.00537385 43 2 16 16 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.58 vpr 62.32 MiB 0.03 6700 -1 -1 1 0.02 -1 -1 30404 -1 -1 9 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63812 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 23.7 MiB 0.02 391 2303 365 1903 35 62.3 MiB 0.02 0.00 1.62267 -39.7198 -1.62267 1.62267 0.31 0.000271803 0.000252259 0.00662073 0.0061278 -1 -1 -1 -1 32 691 13 6.65987e+06 114102 554710. 1919.41 1.05 0.071966 0.0608376 22834 132086 -1 647 11 218 218 14191 3952 0.965248 0.965248 -38.9172 -0.965248 0 0 701300. 2426.64 0.03 0.02 0.11 -1 -1 0.03 0.00743991 0.00653078 46 2 17 17 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.61 vpr 62.15 MiB 0.03 6664 -1 -1 1 0.02 -1 -1 30320 -1 -1 9 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63644 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 23.1 MiB 0.02 437 3023 558 2261 204 62.2 MiB 0.03 0.00 1.63367 -43.0272 -1.63367 1.63367 0.31 0.000276267 0.000255251 0.00858576 0.0079773 -1 -1 -1 -1 32 784 16 6.65987e+06 114102 554710. 1919.41 1.06 0.0805083 0.0682591 22834 132086 -1 696 15 276 276 16973 4776 1.10745 1.10745 -44.1166 -1.10745 0 0 701300. 2426.64 0.03 0.02 0.11 -1 -1 0.03 0.00945995 0.00822878 49 2 18 18 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.90 vpr 62.24 MiB 0.02 6660 -1 -1 1 0.02 -1 -1 30292 -1 -1 11 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63732 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 23.3 MiB 0.03 392 3467 586 2833 48 62.2 MiB 0.03 0.00 1.65567 -48.2349 -1.65567 1.65567 0.31 0.000329593 0.000307324 0.00936662 0.00873063 -1 -1 -1 -1 26 812 15 6.65987e+06 139458 477104. 1650.88 0.40 0.0453993 0.039156 21682 110474 -1 712 12 341 341 19867 6706 1.22645 1.22645 -51.4169 -1.22645 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.00903974 0.00790258 55 2 20 20 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.62 vpr 62.30 MiB 0.03 6704 -1 -1 1 0.02 -1 -1 30312 -1 -1 12 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63800 41 21 146 147 1 102 74 17 17 289 -1 unnamed_device 23.1 MiB 0.03 531 4259 752 3396 111 62.3 MiB 0.04 0.00 1.67767 -55.8836 -1.67767 1.67767 0.31 0.000359195 0.000334602 0.0109398 0.0101848 -1 -1 -1 -1 30 896 10 6.65987e+06 152136 526063. 1820.29 1.07 0.0927812 0.0793515 22546 126617 -1 770 8 209 209 10850 3074 0.997048 0.997048 -50.9669 -0.997048 0 0 666494. 2306.21 0.03 0.02 0.11 -1 -1 0.03 0.00774313 0.0068671 61 2 22 22 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.75 vpr 62.52 MiB 0.02 6656 -1 -1 1 0.02 -1 -1 30252 -1 -1 13 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64016 45 23 160 161 1 114 81 17 17 289 -1 unnamed_device 23.2 MiB 0.03 764 9356 3815 5489 52 62.5 MiB 0.06 0.00 1.69967 -67.6805 -1.69967 1.69967 0.31 0.000389167 0.000362172 0.0220569 0.0205187 -1 -1 -1 -1 32 1188 12 6.65987e+06 164814 554710. 1919.41 1.13 0.113328 0.0982649 22834 132086 -1 1103 12 366 366 28680 7324 1.04225 1.04225 -60.952 -1.04225 0 0 701300. 2426.64 0.03 0.03 0.11 -1 -1 0.03 0.0106173 0.00935199 67 2 24 24 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.72 vpr 62.35 MiB 0.03 6692 -1 -1 1 0.02 -1 -1 30336 -1 -1 14 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63848 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 23.4 MiB 0.03 831 11593 4192 5757 1644 62.4 MiB 0.07 0.00 2.07098 -75.8197 -2.07098 2.07098 0.31 0.000422101 0.000393192 0.0262417 0.0244148 -1 -1 -1 -1 28 1333 28 6.65987e+06 177492 500653. 1732.36 1.09 0.124957 0.108589 21970 115934 -1 1219 17 437 437 39278 9751 1.18125 1.18125 -70.3009 -1.18125 0 0 612192. 2118.31 0.03 0.04 0.10 -1 -1 0.03 0.0145468 0.0127462 73 2 26 26 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.66 vpr 62.61 MiB 0.04 6704 -1 -1 1 0.03 -1 -1 30100 -1 -1 17 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64108 57 29 202 203 1 143 103 17 17 289 -1 unnamed_device 23.2 MiB 0.04 912 15286 4502 8913 1871 62.6 MiB 0.09 0.00 2.11498 -88.9574 -2.11498 2.11498 0.32 0.000489153 0.000455741 0.0323812 0.0301748 -1 -1 -1 -1 26 1550 18 6.65987e+06 215526 477104. 1650.88 0.98 0.121837 0.107277 21682 110474 -1 1388 13 443 443 31299 8177 1.24725 1.24725 -82.6298 -1.24725 0 0 585099. 2024.56 0.03 0.04 0.09 -1 -1 0.03 0.0137722 0.0122007 85 2 30 30 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.98 vpr 62.75 MiB 0.04 6612 -1 -1 1 0.03 -1 -1 30328 -1 -1 19 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64256 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 23.1 MiB 0.04 1143 18707 7317 10498 892 62.8 MiB 0.11 0.00 2.50829 -107.845 -2.50829 2.50829 0.31 0.000569974 0.000532034 0.0390222 0.0364211 -1 -1 -1 -1 32 1748 14 6.65987e+06 240882 554710. 1919.41 1.25 0.14817 0.130955 22834 132086 -1 1630 14 535 535 40050 9975 1.19105 1.19105 -91.6687 -1.19105 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0164661 0.0145733 97 2 34 34 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.52 vpr 62.78 MiB 0.04 6756 -1 -1 1 0.03 -1 -1 30356 -1 -1 29 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64284 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 23.7 MiB 0.06 1707 39295 13883 22023 3389 62.8 MiB 0.23 0.00 3.38291 -180.692 -3.38291 3.38291 0.31 0.000869288 0.000814436 0.0720259 0.0674873 -1 -1 -1 -1 30 2761 18 6.65987e+06 367662 526063. 1820.29 1.58 0.265662 0.238826 22546 126617 -1 2375 15 699 699 54381 13247 1.40705 1.40705 -140.081 -1.40705 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0257587 0.0231206 145 2 50 50 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 2.80 vpr 64.12 MiB 0.04 6792 -1 -1 1 0.03 -1 -1 30296 -1 -1 39 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65660 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2016 55365 18672 32218 4475 64.1 MiB 0.35 0.01 4.25753 -263.191 -4.25753 4.25753 0.31 0.00119825 0.00112662 0.0958231 0.0900876 -1 -1 -1 -1 32 3312 15 6.65987e+06 494442 554710. 1919.41 0.64 0.229644 0.210151 22834 132086 -1 2958 13 1029 1029 81817 21457 1.61205 1.61205 -189.09 -1.61205 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.032125 0.0291029 193 2 66 66 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_005bits.v common 2.28 vpr 62.79 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30164 -1 -1 1 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64292 11 6 41 42 1 20 18 17 17 289 -1 unnamed_device 24.4 MiB 0.03 62 386 62 311 13 62.8 MiB 0.01 0.00 0.701895 -12.1033 -0.701895 0.701895 0.33 0.000104225 9.5142e-05 0.00210608 0.00192352 -1 -1 -1 -1 22 161 9 6.95648e+06 14475.7 443629. 1535.05 0.83 0.0193973 0.0160855 23458 102101 -1 138 7 55 55 2772 942 0.74674 0.74674 -12.942 -0.74674 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00291234 0.00261908 8 2 7 7 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_006bits.v common 2.45 vpr 62.65 MiB 0.03 6560 -1 -1 1 0.02 -1 -1 30100 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64156 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 24.2 MiB 0.03 87 592 130 456 6 62.7 MiB 0.01 0.00 0.802432 -14.5164 -0.802432 0.802432 0.34 0.000127127 0.000116896 0.0028274 0.00258618 -1 -1 -1 -1 26 198 15 6.95648e+06 28951.4 503264. 1741.40 0.92 0.0318139 0.0262425 24322 120374 -1 178 11 63 63 3258 1111 0.74674 0.74674 -15.7863 -0.74674 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00406124 0.00358157 10 2 8 8 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 2.56 vpr 62.70 MiB 0.02 6608 -1 -1 1 0.02 -1 -1 30156 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64208 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 24.2 MiB 0.03 100 673 142 515 16 62.7 MiB 0.01 0.00 0.830632 -16.9552 -0.830632 0.830632 0.33 0.000138329 0.00012717 0.00304865 0.00280557 -1 -1 -1 -1 30 255 11 6.95648e+06 28951.4 556674. 1926.21 1.05 0.0371939 0.0307114 25186 138497 -1 211 13 123 123 6740 2400 0.955932 0.955932 -18.5062 -0.955932 0 0 706193. 2443.58 0.03 0.01 0.11 -1 -1 0.03 0.00478076 0.00417062 11 2 9 9 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_008bits.v common 2.31 vpr 63.02 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 29992 -1 -1 2 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64536 17 9 62 63 1 37 28 17 17 289 -1 unnamed_device 24.5 MiB 0.03 125 952 332 614 6 63.0 MiB 0.01 0.00 0.841632 -19.8878 -0.841632 0.841632 0.33 0.000157373 0.000144688 0.00413175 0.00380665 -1 -1 -1 -1 26 311 22 6.95648e+06 28951.4 503264. 1741.40 0.78 0.0457154 0.0377034 24322 120374 -1 298 20 261 261 14472 4694 0.960732 0.960732 -21.912 -0.960732 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00686066 0.00585132 13 2 10 10 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_009bits.v common 2.40 vpr 62.72 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30060 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64228 19 10 69 70 1 44 32 17 17 289 -1 unnamed_device 24.2 MiB 0.02 146 1832 488 1226 118 62.7 MiB 0.02 0.00 0.874632 -22.1583 -0.874632 0.874632 0.33 0.000174979 0.000161424 0.00696673 0.00643382 -1 -1 -1 -1 26 404 21 6.95648e+06 43427 503264. 1741.40 0.87 0.0526737 0.0439072 24322 120374 -1 318 21 284 284 18247 5948 1.29263 1.29263 -24.4314 -1.29263 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00790038 0.00673662 14 2 11 11 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_010bits.v common 1.97 vpr 62.73 MiB 0.03 6660 -1 -1 1 0.02 -1 -1 29992 -1 -1 3 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64236 21 11 76 77 1 49 35 17 17 289 -1 unnamed_device 24.1 MiB 0.02 155 2543 828 1282 433 62.7 MiB 0.02 0.00 0.896632 -24.6955 -0.896632 0.896632 0.33 0.000194126 0.000179697 0.0092792 0.00858868 -1 -1 -1 -1 26 462 31 6.95648e+06 43427 503264. 1741.40 0.45 0.0364336 0.0310881 24322 120374 -1 398 19 338 338 26201 10587 0.99734 0.99734 -27.2189 -0.99734 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00791891 0.00675717 16 2 12 12 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_011bits.v common 1.92 vpr 62.88 MiB 0.03 6692 -1 -1 1 0.02 -1 -1 30012 -1 -1 3 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64388 23 12 83 84 1 55 38 17 17 289 -1 unnamed_device 24.3 MiB 0.03 382 1361 315 963 83 62.9 MiB 0.01 0.00 0.907632 -31.8241 -0.907632 0.907632 0.33 0.000209316 0.000193583 0.00519236 0.0048121 -1 -1 -1 -1 28 709 21 6.95648e+06 43427 531479. 1839.03 0.41 0.0315098 0.0268375 24610 126494 -1 672 17 385 385 39114 9217 1.10803 1.10803 -35.7734 -1.10803 0 0 648988. 2245.63 0.03 0.02 0.10 -1 -1 0.03 0.007843 0.00674308 17 2 13 13 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_012bits.v common 2.49 vpr 63.14 MiB 0.03 6760 -1 -1 1 0.02 -1 -1 30096 -1 -1 4 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 25 13 90 91 1 60 42 17 17 289 -1 unnamed_device 24.5 MiB 0.02 217 1842 400 1425 17 63.1 MiB 0.02 0.00 0.918632 -30.4825 -0.918632 0.918632 0.33 0.000225704 0.000208561 0.00649227 0.00600972 -1 -1 -1 -1 26 646 19 6.95648e+06 57902.7 503264. 1741.40 0.93 0.0509913 0.0429348 24322 120374 -1 504 13 321 321 21249 6537 1.11903 1.11903 -35.2417 -1.11903 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00707951 0.00615094 19 2 14 14 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 2.59 vpr 63.15 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30196 -1 -1 4 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 27 14 97 98 1 66 45 17 17 289 -1 unnamed_device 24.5 MiB 0.03 301 1965 420 1532 13 63.1 MiB 0.02 0.00 0.951632 -34.1049 -0.951632 0.951632 0.33 0.000237918 0.000220458 0.00657517 0.00609508 -1 -1 -1 -1 30 661 16 6.95648e+06 57902.7 556674. 1926.21 1.05 0.0629534 0.0529979 25186 138497 -1 553 14 332 332 23518 6075 1.14103 1.14103 -37.6974 -1.14103 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00772022 0.00670017 20 2 15 15 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_014bits.v common 2.77 vpr 62.84 MiB 0.03 6756 -1 -1 1 0.02 -1 -1 30248 -1 -1 4 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64344 29 15 104 105 1 72 48 17 17 289 -1 unnamed_device 24.2 MiB 0.03 284 3615 1181 1970 464 62.8 MiB 0.03 0.00 0.962632 -36.5249 -0.962632 0.962632 0.33 0.000252111 0.000233608 0.0113814 0.0105342 -1 -1 -1 -1 28 727 17 6.95648e+06 57902.7 531479. 1839.03 1.19 0.079796 0.0676654 24610 126494 -1 620 18 431 431 33772 9630 1.64223 1.64223 -47.0349 -1.64223 0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.00956765 0.00827914 22 2 16 16 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_015bits.v common 2.54 vpr 62.99 MiB 0.03 6700 -1 -1 1 0.02 -1 -1 30292 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64500 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 24.2 MiB 0.04 453 4708 1459 2518 731 63.0 MiB 0.04 0.00 1.33396 -42.5374 -1.33396 1.33396 0.33 0.00027208 0.00025224 0.0140247 0.0130132 -1 -1 -1 -1 30 913 18 6.95648e+06 72378.4 556674. 1926.21 0.95 0.0723094 0.0618422 25186 138497 -1 790 14 414 414 38456 8768 1.20503 1.20503 -47.857 -1.20503 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.00869876 0.00758825 24 2 17 17 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_016bits.v common 2.15 vpr 62.87 MiB 0.03 6760 -1 -1 1 0.02 -1 -1 30248 -1 -1 5 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64376 33 17 118 119 1 81 55 17 17 289 -1 unnamed_device 23.9 MiB 0.05 377 6607 2742 3791 74 62.9 MiB 0.05 0.00 1.34496 -43.4191 -1.34496 1.34496 0.33 0.000294762 0.000272557 0.0193513 0.0179452 -1 -1 -1 -1 28 913 30 6.95648e+06 72378.4 531479. 1839.03 0.50 0.0577112 0.0502372 24610 126494 -1 715 17 452 452 41946 11009 1.42263 1.42263 -49.4656 -1.42263 0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.0108026 0.00939751 25 2 18 18 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_018bits.v common 2.33 vpr 63.01 MiB 0.04 6580 -1 -1 1 0.02 -1 -1 30336 -1 -1 5 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64524 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 23.9 MiB 0.07 393 3301 654 2600 47 63.0 MiB 0.03 0.00 1.36696 -49.8334 -1.36696 1.36696 0.33 0.000330266 0.000307361 0.0100521 0.00936704 -1 -1 -1 -1 32 864 42 6.95648e+06 72378.4 586450. 2029.24 0.67 0.0691101 0.0588358 25474 144626 -1 705 15 408 408 32526 9042 1.10173 1.10173 -52.471 -1.10173 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.0107581 0.00935112 28 2 20 20 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_020bits.v common 3.07 vpr 63.13 MiB 0.03 6580 -1 -1 1 0.03 -1 -1 30388 -1 -1 5 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 41 21 146 147 1 95 67 17 17 289 -1 unnamed_device 23.9 MiB 0.07 410 7955 3291 4607 57 63.1 MiB 0.05 0.00 1.38896 -55.723 -1.38896 1.38896 0.33 0.000373075 0.000347385 0.022255 0.0206821 -1 -1 -1 -1 30 1115 42 6.95648e+06 72378.4 556674. 1926.21 1.37 0.117238 0.100702 25186 138497 -1 768 18 563 563 47917 12726 1.26003 1.26003 -58.1622 -1.26003 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0132196 0.0114637 31 2 22 22 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_022bits.v common 2.81 vpr 63.12 MiB 0.03 6808 -1 -1 1 0.02 -1 -1 30328 -1 -1 6 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64636 45 23 160 161 1 107 74 17 17 289 -1 unnamed_device 23.9 MiB 0.08 569 10614 2660 7461 493 63.1 MiB 0.07 0.00 1.41096 -65.6384 -1.41096 1.41096 0.33 0.000389385 0.000362412 0.0278189 0.0259072 -1 -1 -1 -1 30 1184 24 6.95648e+06 86854.1 556674. 1926.21 1.10 0.102487 0.0892946 25186 138497 -1 976 14 527 527 35129 9046 1.24423 1.24423 -67.232 -1.24423 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.011989 0.010522 34 2 24 24 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_024bits.v common 2.43 vpr 63.29 MiB 0.01 6560 -1 -1 1 0.02 -1 -1 30380 -1 -1 7 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 49 25 174 175 1 119 81 17 17 289 -1 unnamed_device 24.0 MiB 0.05 854 11106 4608 6456 42 63.3 MiB 0.07 0.00 1.43296 -76.1933 -1.43296 1.43296 0.33 0.00042267 0.000393493 0.0281882 0.0262471 -1 -1 -1 -1 32 1488 18 6.95648e+06 101330 586450. 2029.24 0.71 0.0909348 0.0799055 25474 144626 -1 1358 24 681 681 103355 32923 1.59383 1.59383 -87.2355 -1.59383 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0192398 0.0167411 38 2 26 26 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_028bits.v common 2.72 vpr 63.51 MiB 0.03 6712 -1 -1 1 0.03 -1 -1 30024 -1 -1 8 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 57 29 202 203 1 142 94 17 17 289 -1 unnamed_device 24.1 MiB 0.06 701 13726 3066 10452 208 63.5 MiB 0.08 0.00 1.47696 -80.9741 -1.47696 1.47696 0.33 0.00048541 0.000452475 0.0327471 0.0305043 -1 -1 -1 -1 36 1504 25 6.95648e+06 115805 648988. 2245.63 0.95 0.130404 0.114538 26050 158493 -1 1275 19 669 669 58321 15600 1.45133 1.45133 -89.0754 -1.45133 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0182283 0.0160219 44 2 30 30 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_032bits.v common 3.02 vpr 63.56 MiB 0.04 6608 -1 -1 1 0.03 -1 -1 30416 -1 -1 9 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65084 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 23.9 MiB 0.08 910 17311 4711 11729 871 63.6 MiB 0.10 0.00 1.88129 -96.5486 -1.88129 1.88129 0.33 0.000568125 0.000530079 0.0404902 0.0378271 -1 -1 -1 -1 38 1716 50 6.95648e+06 130281 678818. 2348.85 1.16 0.17582 0.154761 26626 170182 -1 1485 18 787 787 58967 14897 1.32593 1.32593 -97.9313 -1.32593 0 0 902133. 3121.57 0.03 0.05 0.14 -1 -1 0.03 0.0202252 0.0178317 50 2 34 34 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_048bits.v common 6.63 vpr 63.82 MiB 0.03 6616 -1 -1 1 0.03 -1 -1 30440 -1 -1 14 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65356 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 24.5 MiB 0.10 1640 34012 12509 19150 2353 63.8 MiB 0.19 0.00 2.41762 -166.789 -2.41762 2.41762 0.33 0.000873313 0.000818471 0.0707271 0.0662884 -1 -1 -1 -1 46 2590 14 6.95648e+06 202660 828058. 2865.25 4.53 0.398032 0.354733 28066 200906 -1 2334 18 952 952 79254 17784 1.47173 1.47173 -153.194 -1.47173 0 0 1.01997e+06 3529.29 0.04 0.07 0.16 -1 -1 0.04 0.0305654 0.0274123 74 2 50 50 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_064bits.v common 7.79 vpr 64.66 MiB 0.04 6776 -1 -1 1 0.03 -1 -1 30312 -1 -1 19 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66216 129 65 454 455 1 324 213 17 17 289 -1 unnamed_device 24.8 MiB 0.13 1977 51013 20101 28701 2211 64.7 MiB 0.29 0.01 2.95395 -231.581 -2.95395 2.95395 0.33 0.00120007 0.00112846 0.0995914 0.093585 -1 -1 -1 -1 56 3124 19 6.95648e+06 275038 973134. 3367.25 5.43 0.673439 0.605837 29794 239141 -1 2776 20 1296 1296 121046 30748 1.89633 1.89633 -213.812 -1.89633 0 0 1.19926e+06 4149.71 0.05 0.11 0.19 -1 -1 0.05 0.0461238 0.0416744 98 2 66 66 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_005bits.v common 2.18 vpr 62.55 MiB 0.03 6700 -1 -1 1 0.02 -1 -1 30104 -1 -1 1 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64052 11 6 41 42 1 19 18 17 17 289 -1 unnamed_device 23.8 MiB 0.01 58 363 61 287 15 62.6 MiB 0.01 0.00 0.688132 -11.6961 -0.688132 0.688132 0.33 0.000103887 9.4676e-05 0.00199438 0.00182048 -1 -1 -1 -1 26 153 8 6.99608e+06 14715.7 503264. 1741.40 0.72 0.0238353 0.0195708 24322 120374 -1 139 8 48 48 2544 859 0.688132 0.688132 -12.6806 -0.688132 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00303976 0.00271809 8 2 7 7 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_006bits.v common 2.24 vpr 62.54 MiB 0.03 6608 -1 -1 1 0.02 -1 -1 29912 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64040 13 7 48 49 1 26 22 17 17 289 -1 unnamed_device 24.1 MiB 0.01 78 562 126 419 17 62.5 MiB 0.01 0.00 0.802432 -14.4602 -0.802432 0.802432 0.32 0.000121935 0.000111669 0.00267955 0.00245719 -1 -1 -1 -1 26 205 14 6.99608e+06 29431.4 503264. 1741.40 0.76 0.0294451 0.0243692 24322 120374 -1 197 17 97 97 5169 1930 0.916732 0.916732 -16.4331 -0.916732 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00493038 0.00425735 10 2 8 8 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_007bits.v common 2.42 vpr 62.64 MiB 0.03 6612 -1 -1 1 0.02 -1 -1 30092 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64140 15 8 55 56 1 31 25 17 17 289 -1 unnamed_device 24.1 MiB 0.01 98 637 131 492 14 62.6 MiB 0.01 0.00 0.813432 -16.8565 -0.813432 0.813432 0.31 6.2692e-05 5.6118e-05 0.0014755 0.00132676 -1 -1 -1 -1 32 226 11 6.99608e+06 29431.4 586450. 2029.24 0.92 0.0278602 0.0229111 25474 144626 -1 180 13 106 106 4615 1703 0.804379 0.804379 -17.6598 -0.804379 0 0 744469. 2576.02 0.03 0.01 0.12 -1 -1 0.03 0.00481667 0.00418904 11 2 9 9 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_008bits.v common 1.91 vpr 62.59 MiB 0.04 6560 -1 -1 1 0.02 -1 -1 30016 -1 -1 2 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 17 9 62 63 1 36 28 17 17 289 -1 unnamed_device 24.1 MiB 0.01 114 952 302 601 49 62.6 MiB 0.01 0.00 0.835432 -19.044 -0.835432 0.835432 0.34 0.000156766 0.000144322 0.00408126 0.00375596 -1 -1 -1 -1 28 296 22 6.99608e+06 29431.4 531479. 1839.03 0.38 0.0237415 0.0199754 24610 126494 -1 256 22 277 277 17430 6116 1.04203 1.04203 -20.1441 -1.04203 0 0 648988. 2245.63 0.03 0.02 0.10 -1 -1 0.03 0.00725829 0.0061685 13 2 10 10 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_009bits.v common 2.58 vpr 62.60 MiB 0.03 6716 -1 -1 1 0.02 -1 -1 30012 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 19 10 69 70 1 43 32 17 17 289 -1 unnamed_device 24.1 MiB 0.02 140 1832 485 1229 118 62.6 MiB 0.02 0.00 0.846432 -21.7224 -0.846432 0.846432 0.33 0.000173613 0.000160388 0.00696085 0.00643037 -1 -1 -1 -1 32 309 11 6.99608e+06 44147 586450. 2029.24 1.04 0.0505928 0.0421812 25474 144626 -1 264 17 235 235 13568 4536 0.971732 0.971732 -22.3105 -0.971732 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00673143 0.00577916 14 2 11 11 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_010bits.v common 2.41 vpr 62.58 MiB 0.03 6704 -1 -1 1 0.02 -1 -1 30008 -1 -1 3 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 21 11 76 77 1 48 35 17 17 289 -1 unnamed_device 24.1 MiB 0.02 190 2315 608 1263 444 62.6 MiB 0.02 0.00 0.868432 -25.6922 -0.868432 0.868432 0.33 0.000199171 0.000180565 0.00847415 0.00783455 -1 -1 -1 -1 26 414 17 6.99608e+06 44147 503264. 1741.40 0.90 0.0472016 0.0396651 24322 120374 -1 378 13 199 199 14854 4544 0.993732 0.993732 -27.7763 -0.993732 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.0061308 0.00533051 16 2 12 12 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_011bits.v common 2.46 vpr 62.75 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 29984 -1 -1 3 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64260 23 12 83 84 1 54 38 17 17 289 -1 unnamed_device 24.1 MiB 0.02 355 1487 338 1045 104 62.8 MiB 0.02 0.00 0.879432 -29.3885 -0.879432 0.879432 0.34 0.00021161 0.000195534 0.00560054 0.00518581 -1 -1 -1 -1 26 651 22 6.99608e+06 44147 503264. 1741.40 0.94 0.0633592 0.05278 24322 120374 -1 612 16 287 287 21910 5749 0.971732 0.971732 -32.8358 -0.971732 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00751229 0.00646523 17 2 13 13 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_012bits.v common 2.45 vpr 62.94 MiB 0.03 6696 -1 -1 1 0.02 -1 -1 30000 -1 -1 4 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64452 25 13 90 91 1 60 42 17 17 289 -1 unnamed_device 24.3 MiB 0.02 215 1842 394 1399 49 62.9 MiB 0.02 0.00 0.901432 -30.3131 -0.901432 0.901432 0.33 0.000281864 0.000257049 0.00829278 0.00764444 -1 -1 -1 -1 26 564 17 6.99608e+06 58862.7 503264. 1741.40 0.93 0.0537918 0.0453251 24322 120374 -1 521 18 365 365 24551 7622 1.14103 1.14103 -36.1835 -1.14103 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.0085692 0.00736037 19 2 14 14 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 2.56 vpr 62.73 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30148 -1 -1 4 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64240 27 14 97 98 1 66 45 17 17 289 -1 unnamed_device 24.1 MiB 0.02 232 1645 306 1308 31 62.7 MiB 0.02 0.00 0.912432 -32.6875 -0.912432 0.912432 0.33 0.000237403 0.000219852 0.00563039 0.0052098 -1 -1 -1 -1 28 634 16 6.99608e+06 58862.7 531479. 1839.03 0.99 0.0510613 0.0430376 24610 126494 -1 580 15 347 347 22140 6906 1.12098 1.12098 -38.2151 -1.12098 0 0 648988. 2245.63 0.03 0.02 0.10 -1 -1 0.03 0.00802719 0.00695465 20 2 15 15 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_014bits.v common 2.65 vpr 62.88 MiB 0.03 6700 -1 -1 1 0.02 -1 -1 30384 -1 -1 4 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64388 29 15 104 105 1 72 48 17 17 289 -1 unnamed_device 24.2 MiB 0.03 373 3702 1135 2001 566 62.9 MiB 0.03 0.00 0.934432 -38.3641 -0.934432 0.934432 0.33 0.000251966 0.000233344 0.0115225 0.0106543 -1 -1 -1 -1 30 767 25 6.99608e+06 58862.7 556674. 1926.21 1.06 0.0735093 0.06237 25186 138497 -1 628 13 341 341 24944 6277 1.08603 1.08603 -40.6345 -1.08603 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00773893 0.00675775 22 2 16 16 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_015bits.v common 2.06 vpr 62.76 MiB 0.03 6584 -1 -1 1 0.02 -1 -1 30324 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 24.1 MiB 0.03 329 4708 1728 2615 365 62.8 MiB 0.04 0.00 1.30576 -38.8078 -1.30576 1.30576 0.33 0.000270479 0.000250497 0.0140615 0.0130288 -1 -1 -1 -1 28 861 22 6.99608e+06 73578.4 531479. 1839.03 0.43 0.0470125 0.0407944 24610 126494 -1 671 33 467 467 69994 35425 1.31648 1.31648 -46.8964 -1.31648 0 0 648988. 2245.63 0.03 0.05 0.10 -1 -1 0.03 0.0161664 0.0137404 24 2 17 17 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_016bits.v common 2.63 vpr 62.89 MiB 0.03 6724 -1 -1 1 0.02 -1 -1 30464 -1 -1 5 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64400 33 17 118 119 1 81 55 17 17 289 -1 unnamed_device 23.8 MiB 0.03 332 6711 2788 3857 66 62.9 MiB 0.05 0.00 1.31676 -42.5221 -1.31676 1.31676 0.33 0.000290847 0.000269945 0.0196842 0.0182572 -1 -1 -1 -1 30 798 23 6.99608e+06 73578.4 556674. 1926.21 1.02 0.0861479 0.0739404 25186 138497 -1 633 14 378 378 25514 6912 1.12803 1.12803 -44.1937 -1.12803 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00909213 0.00792804 25 2 18 18 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_018bits.v common 2.26 vpr 62.82 MiB 0.03 6640 -1 -1 1 0.02 -1 -1 30308 -1 -1 5 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64324 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 23.8 MiB 0.03 358 4261 920 3151 190 62.8 MiB 0.03 0.00 1.33876 -48.1967 -1.33876 1.33876 0.33 0.000329896 0.000306815 0.0126606 0.0117764 -1 -1 -1 -1 32 835 17 6.99608e+06 73578.4 586450. 2029.24 0.64 0.056576 0.048753 25474 144626 -1 664 15 333 333 20812 6284 1.12373 1.12373 -51.9237 -1.12373 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.0106675 0.00927301 28 2 20 20 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_020bits.v common 2.31 vpr 62.79 MiB 0.04 6584 -1 -1 1 0.02 -1 -1 30456 -1 -1 5 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64292 41 21 146 147 1 94 67 17 17 289 -1 unnamed_device 23.8 MiB 0.03 468 7955 3317 4596 42 62.8 MiB 0.05 0.00 1.36076 -55.6855 -1.36076 1.36076 0.33 0.0003604 0.000335335 0.0220989 0.020532 -1 -1 -1 -1 32 929 17 6.99608e+06 73578.4 586450. 2029.24 0.64 0.0715016 0.0623443 25474 144626 -1 758 14 366 366 27217 7456 1.23803 1.23803 -58.6653 -1.23803 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.0110418 0.00964779 31 2 22 22 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_022bits.v common 2.91 vpr 62.83 MiB 0.02 6708 -1 -1 1 0.02 -1 -1 30332 -1 -1 6 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64340 45 23 160 161 1 106 74 17 17 289 -1 unnamed_device 23.7 MiB 0.04 574 10149 2496 7579 74 62.8 MiB 0.06 0.00 1.38276 -62.9133 -1.38276 1.38276 0.33 0.000392204 0.000364759 0.0268104 0.0248718 -1 -1 -1 -1 30 1236 38 6.99608e+06 88294.1 556674. 1926.21 1.25 0.124304 0.107554 25186 138497 -1 954 14 520 520 41622 10284 1.19403 1.19403 -64.1778 -1.19403 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.01195 0.0104728 34 2 24 24 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_024bits.v common 2.24 vpr 63.00 MiB 0.03 6760 -1 -1 1 0.03 -1 -1 30312 -1 -1 7 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64512 49 25 174 175 1 118 81 17 17 289 -1 unnamed_device 23.7 MiB 0.04 868 11106 3989 6115 1002 63.0 MiB 0.07 0.00 1.40476 -74.1905 -1.40476 1.40476 0.33 0.000424614 0.000394513 0.0281667 0.0262197 -1 -1 -1 -1 30 1519 43 6.99608e+06 103010 556674. 1926.21 0.52 0.0915366 0.080441 25186 138497 -1 1309 16 480 480 43224 9730 1.31503 1.31503 -80.1605 -1.31503 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0139185 0.0122012 38 2 26 26 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_028bits.v common 2.66 vpr 63.32 MiB 0.04 6704 -1 -1 1 0.02 -1 -1 30008 -1 -1 8 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64840 57 29 202 203 1 141 94 17 17 289 -1 unnamed_device 23.9 MiB 0.05 716 13726 3497 10051 178 63.3 MiB 0.08 0.00 1.44876 -81.7332 -1.44876 1.44876 0.33 0.000485892 0.000452708 0.0329705 0.0305998 -1 -1 -1 -1 36 1485 24 6.99608e+06 117725 648988. 2245.63 0.88 0.129849 0.114084 26050 158493 -1 1285 14 597 597 52011 13012 1.30403 1.30403 -83.6263 -1.30403 0 0 828058. 2865.25 0.03 0.04 0.13 -1 -1 0.03 0.0144526 0.0128002 44 2 30 30 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_032bits.v common 2.83 vpr 63.25 MiB 0.04 6688 -1 -1 1 0.03 -1 -1 30304 -1 -1 9 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64772 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 23.7 MiB 0.05 974 17311 5634 10760 917 63.3 MiB 0.11 0.00 1.85309 -98.3079 -1.85309 1.85309 0.33 0.000573006 0.000535177 0.040683 0.0380129 -1 -1 -1 -1 38 1748 34 6.99608e+06 132441 678818. 2348.85 1.01 0.16221 0.143137 26626 170182 -1 1535 17 764 764 60474 14239 1.41203 1.41203 -101.564 -1.41203 0 0 902133. 3121.57 0.03 0.05 0.14 -1 -1 0.03 0.0193024 0.0170044 50 2 34 34 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_048bits.v common 4.23 vpr 63.43 MiB 0.02 6560 -1 -1 1 0.03 -1 -1 30436 -1 -1 14 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64952 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 24.1 MiB 0.08 1658 34012 13319 19214 1479 63.4 MiB 0.19 0.00 2.38942 -166.658 -2.38942 2.38942 0.33 0.000871933 0.000816621 0.0708685 0.0663994 -1 -1 -1 -1 46 2542 21 6.99608e+06 206020 828058. 2865.25 2.20 0.318031 0.284999 28066 200906 -1 2386 18 1000 1000 89813 19714 1.40918 1.40918 -149.495 -1.40918 0 0 1.01997e+06 3529.29 0.04 0.07 0.16 -1 -1 0.04 0.0306471 0.0274583 74 2 50 50 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_064bits.v common 8.68 vpr 64.58 MiB 0.04 6868 -1 -1 1 0.03 -1 -1 30300 -1 -1 19 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66132 129 65 454 455 1 324 213 17 17 289 -1 unnamed_device 24.8 MiB 0.10 1985 51013 19564 29177 2272 64.6 MiB 0.31 0.01 2.92575 -230.422 -2.92575 2.92575 0.33 0.0012048 0.00113356 0.0999523 0.0940212 -1 -1 -1 -1 50 3267 26 6.99608e+06 279598 902133. 3121.57 6.41 0.669769 0.603211 28642 213929 -1 2965 18 1277 1277 117926 28131 1.74903 1.74903 -209.268 -1.74903 0 0 1.08113e+06 3740.92 0.04 0.10 0.17 -1 -1 0.04 0.0421011 0.0380301 98 2 66 66 0 0 + fixed_k6_frac_N8_22nm.xml adder_005bits.v common 1.73 vpr 61.99 MiB 0.03 6368 -1 -1 2 0.06 -1 -1 31820 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63480 11 6 34 40 1 23 19 17 17 289 -1 unnamed_device 23.2 MiB 0.01 185 119 39 80 0 62.0 MiB 0.00 0.00 1.02368 -16.2207 -1.02368 1.02368 0.33 0.000105613 9.6137e-05 0.000843747 0.000776845 -1 -1 -1 -1 20 272 6 6.79088e+06 26944 414966. 1435.87 0.27 0.00397713 0.00357669 22510 95286 -1 280 10 79 96 5531 1461 1.02368 1.02368 -16.6343 -1.02368 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00346008 0.00306058 10 7 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_006bits.v common 1.95 vpr 61.93 MiB 0.03 6440 -1 -1 3 0.05 -1 -1 31972 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63420 13 7 41 48 1 30 22 17 17 289 -1 unnamed_device 23.3 MiB 0.01 99 472 98 353 21 61.9 MiB 0.01 0.00 1.14898 -16.154 -1.14898 1.14898 0.33 0.000125154 0.000114524 0.00243451 0.00224419 -1 -1 -1 -1 20 280 10 6.79088e+06 26944 414966. 1435.87 0.53 0.00956601 0.00830799 22510 95286 -1 223 7 83 87 4348 1454 1.05944 1.05944 -17.1675 -1.05944 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00329137 0.00293956 11 9 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_007bits.v common 2.42 vpr 62.09 MiB 0.03 6444 -1 -1 3 0.05 -1 -1 32544 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63584 15 8 47 55 1 35 25 17 17 289 -1 unnamed_device 23.6 MiB 0.04 124 1141 451 677 13 62.1 MiB 0.01 0.00 1.31353 -19.8451 -1.31353 1.31353 0.33 0.000143611 0.000131677 0.00503436 0.0046201 -1 -1 -1 -1 24 275 11 6.79088e+06 26944 470940. 1629.55 0.93 0.0316593 0.0264652 23374 113417 -1 241 10 112 119 5467 1823 1.31353 1.31353 -21.0649 -1.31353 0 0 586450. 2029.24 0.03 0.01 0.09 -1 -1 0.03 0.00422996 0.00371899 13 10 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_008bits.v common 1.92 vpr 62.10 MiB 0.03 6416 -1 -1 3 0.06 -1 -1 32096 -1 -1 4 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63588 17 9 56 65 1 42 30 17 17 289 -1 unnamed_device 23.6 MiB 0.06 138 1364 351 850 163 62.1 MiB 0.02 0.00 1.56413 -22.2762 -1.56413 1.56413 0.33 0.000175061 0.00016151 0.00578447 0.00534538 -1 -1 -1 -1 26 380 13 6.79088e+06 53888 503264. 1741.40 0.36 0.0252761 0.0214839 23662 119890 -1 311 10 190 233 11383 4069 1.43883 1.43883 -23.4014 -1.43883 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00506057 0.00444233 17 14 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_009bits.v common 2.42 vpr 62.01 MiB 0.03 6376 -1 -1 4 0.06 -1 -1 32004 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63496 19 10 60 70 1 47 32 17 17 289 -1 unnamed_device 23.5 MiB 0.07 175 1032 216 789 27 62.0 MiB 0.01 0.00 1.65028 -27.4579 -1.65028 1.65028 0.33 0.000184083 0.000169959 0.00440207 0.00406982 -1 -1 -1 -1 26 388 8 6.79088e+06 40416 503264. 1741.40 0.83 0.0431103 0.0358263 23662 119890 -1 349 7 136 152 6381 2191 1.65028 1.65028 -28.9406 -1.65028 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00429807 0.00381194 17 13 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_010bits.v common 2.37 vpr 62.13 MiB 0.01 6416 -1 -1 4 0.06 -1 -1 31812 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63620 21 11 69 80 1 54 36 17 17 289 -1 unnamed_device 23.6 MiB 0.06 191 1452 298 1143 11 62.1 MiB 0.02 0.00 1.56413 -28.6885 -1.56413 1.56413 0.33 0.00021013 0.000194272 0.00585312 0.00542163 -1 -1 -1 -1 22 619 20 6.79088e+06 53888 443629. 1535.05 0.76 0.0405774 0.0341028 22798 101617 -1 442 11 230 273 12308 4104 1.51379 1.51379 -31.026 -1.51379 0 0 531479. 1839.03 0.02 0.02 0.09 -1 -1 0.02 0.006077 0.0053106 21 17 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_011bits.v common 2.02 vpr 62.25 MiB 0.03 6408 -1 -1 5 0.06 -1 -1 32476 -1 -1 4 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63748 23 12 73 85 1 57 39 17 17 289 -1 unnamed_device 23.7 MiB 0.10 324 1293 253 1010 30 62.3 MiB 0.01 0.00 1.90093 -37.0277 -1.90093 1.90093 0.33 0.000220235 0.000203862 0.00496718 0.00460762 -1 -1 -1 -1 26 610 11 6.79088e+06 53888 503264. 1741.40 0.36 0.0280228 0.0238754 23662 119890 -1 587 12 200 237 14071 3800 1.77563 1.77563 -37.5926 -1.77563 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00652735 0.00569607 21 16 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_012bits.v common 2.38 vpr 62.18 MiB 0.03 6372 -1 -1 5 0.06 -1 -1 31816 -1 -1 4 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63676 25 13 82 95 1 64 42 17 17 289 -1 unnamed_device 23.6 MiB 0.07 311 3498 1073 1762 663 62.2 MiB 0.03 0.00 2.11577 -39.2455 -2.11577 2.11577 0.33 0.000240811 0.000222276 0.0125095 0.0115677 -1 -1 -1 -1 26 678 11 6.79088e+06 53888 503264. 1741.40 0.77 0.0617736 0.0525154 23662 119890 -1 630 10 251 327 17898 4910 1.81483 1.81483 -40.2385 -1.81483 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00642909 0.00566045 25 20 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_013bits.v common 2.57 vpr 62.27 MiB 0.03 6368 -1 -1 5 0.06 -1 -1 32264 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63768 27 14 91 105 1 70 46 17 17 289 -1 unnamed_device 23.6 MiB 0.08 366 1440 252 1179 9 62.3 MiB 0.02 0.00 2.15497 -43.2188 -2.15497 2.15497 0.34 0.000272352 0.000251968 0.00569786 0.00529265 -1 -1 -1 -1 26 771 12 6.79088e+06 67360 503264. 1741.40 0.93 0.0585775 0.0494107 23662 119890 -1 724 15 295 415 26147 6829 2.06543 2.06543 -45.476 -2.06543 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00916542 0.00793504 28 24 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_014bits.v common 2.43 vpr 62.08 MiB 0.03 6384 -1 -1 6 0.06 -1 -1 31792 -1 -1 5 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63572 29 15 95 110 1 77 49 17 17 289 -1 unnamed_device 23.4 MiB 0.07 466 2363 475 1762 126 62.1 MiB 0.02 0.00 2.40562 -51.3873 -2.40562 2.40562 0.33 0.000283014 0.00026257 0.008428 0.00782966 -1 -1 -1 -1 26 1006 20 6.79088e+06 67360 503264. 1741.40 0.84 0.0737772 0.0621989 23662 119890 -1 868 15 357 442 37776 9302 2.28027 2.28027 -52.397 -2.28027 0 0 618332. 2139.56 0.03 0.03 0.08 -1 -1 0.03 0.00951784 0.00825793 29 23 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_015bits.v common 2.81 vpr 62.16 MiB 0.03 6416 -1 -1 6 0.06 -1 -1 31760 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63656 31 16 104 120 1 84 53 17 17 289 -1 unnamed_device 23.4 MiB 0.08 547 2231 435 1739 57 62.2 MiB 0.02 0.00 2.69548 -57.02 -2.69548 2.69548 0.33 0.000312731 0.000290207 0.00798741 0.00743841 -1 -1 -1 -1 30 1011 15 6.79088e+06 80832 556674. 1926.21 1.14 0.0619094 0.0525221 24526 138013 -1 888 11 296 383 24823 5960 2.44488 2.44488 -57.0491 -2.44488 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0117276 0.0101176 32 27 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_016bits.v common 2.77 vpr 62.21 MiB 0.03 6380 -1 -1 7 0.06 -1 -1 31840 -1 -1 5 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63704 33 17 108 125 1 84 55 17 17 289 -1 unnamed_device 23.5 MiB 0.14 411 6503 2709 3763 31 62.2 MiB 0.05 0.00 2.69553 -58.1741 -2.69553 2.69553 0.33 0.000323422 0.000300152 0.0211808 0.0196751 -1 -1 -1 -1 28 942 15 6.79088e+06 67360 531479. 1839.03 1.02 0.09488 0.0813611 23950 126010 -1 708 12 321 412 23073 6793 2.69553 2.69553 -57.9994 -2.69553 0 0 648988. 2245.63 0.03 0.02 0.10 -1 -1 0.03 0.00917799 0.00802688 31 26 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_018bits.v common 2.85 vpr 62.34 MiB 0.04 6408 -1 -1 7 0.06 -1 -1 32380 -1 -1 7 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63840 37 19 127 146 1 98 63 17 17 289 -1 unnamed_device 23.2 MiB 0.17 476 6063 1544 3786 733 62.3 MiB 0.04 0.00 2.90688 -68.4098 -2.90688 2.90688 0.33 0.000368248 0.000341607 0.0191151 0.0177558 -1 -1 -1 -1 26 1168 18 6.79088e+06 94304 503264. 1741.40 1.07 0.104535 0.0896586 23662 119890 -1 1004 13 384 508 32774 8739 2.90344 2.90344 -73.1338 -2.90344 0 0 618332. 2139.56 0.03 0.03 0.10 -1 -1 0.03 0.0111271 0.00974877 37 35 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_020bits.v common 3.15 vpr 62.30 MiB 0.04 6368 -1 -1 8 0.07 -1 -1 32016 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63792 41 21 139 160 1 107 70 17 17 289 -1 unnamed_device 23.3 MiB 0.14 570 6982 2815 4045 122 62.3 MiB 0.05 0.00 2.99652 -76.0046 -2.99652 2.99652 0.33 0.000399364 0.000370484 0.0206606 0.0191367 -1 -1 -1 -1 28 1580 50 6.79088e+06 107776 531479. 1839.03 1.37 0.132385 0.113608 23950 126010 -1 1054 10 373 485 28857 7567 2.74592 2.74592 -76.6852 -2.74592 0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.010177 0.00900614 41 37 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_022bits.v common 3.10 vpr 62.59 MiB 0.03 6416 -1 -1 9 0.07 -1 -1 32328 -1 -1 8 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 45 23 152 175 1 118 76 17 17 289 -1 unnamed_device 23.4 MiB 0.17 502 8076 3035 4695 346 62.6 MiB 0.06 0.00 3.44738 -89.4365 -3.44738 3.44738 0.33 0.00043407 0.000402995 0.0234092 0.0217395 -1 -1 -1 -1 28 1205 16 6.79088e+06 107776 531479. 1839.03 1.28 0.128429 0.111207 23950 126010 -1 1016 10 411 515 32993 10013 3.14645 3.14645 -88.4177 -3.14645 0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.0109613 0.00973903 46 40 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_024bits.v common 3.58 vpr 62.63 MiB 0.03 6464 -1 -1 10 0.09 -1 -1 32664 -1 -1 10 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64136 49 25 165 190 1 131 84 17 17 289 -1 unnamed_device 23.3 MiB 0.18 739 11247 4252 6647 348 62.6 MiB 0.07 0.00 3.86603 -103.96 -3.86603 3.86603 0.33 0.000472102 0.000438272 0.0304073 0.0282308 -1 -1 -1 -1 28 1645 20 6.79088e+06 134720 531479. 1839.03 1.66 0.152184 0.132201 23950 126010 -1 1446 27 611 946 116777 58516 3.66233 3.66233 -105.67 -3.66233 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0235639 0.0205086 51 43 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_028bits.v common 3.24 vpr 62.96 MiB 0.04 6380 -1 -1 11 0.07 -1 -1 32692 -1 -1 11 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64472 57 29 199 228 1 155 97 17 17 289 -1 unnamed_device 23.4 MiB 0.19 966 15637 5195 8163 2279 63.0 MiB 0.10 0.00 4.19267 -132.823 -4.19267 4.19267 0.33 0.000572989 0.00053382 0.0423166 0.0394322 -1 -1 -1 -1 30 1883 23 6.79088e+06 148192 556674. 1926.21 1.27 0.167367 0.146646 24526 138013 -1 1627 36 587 869 119586 67484 3.95993 3.95993 -132.604 -3.95993 0 0 706193. 2443.58 0.03 0.10 0.11 -1 -1 0.03 0.0362552 0.0315027 58 57 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_032bits.v common 4.55 vpr 62.89 MiB 0.03 6408 -1 -1 13 0.08 -1 -1 32052 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64404 65 33 224 257 1 173 110 17 17 289 -1 unnamed_device 23.3 MiB 0.33 796 9841 2082 7388 371 62.9 MiB 0.07 0.00 4.79019 -155.397 -4.79019 4.79019 0.33 0.000646067 0.000602862 0.0260827 0.0243204 -1 -1 -1 -1 40 1491 20 6.79088e+06 161664 706193. 2443.58 2.47 0.270638 0.235041 26254 175826 -1 1363 13 682 924 48199 14189 4.48925 4.48925 -144.593 -4.48925 0 0 926341. 3205.33 0.04 0.04 0.14 -1 -1 0.04 0.0184905 0.016418 66 62 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_048bits.v common 3.91 vpr 63.67 MiB 0.01 6528 -1 -1 19 0.10 -1 -1 32428 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65200 97 49 340 389 1 265 164 17 17 289 -1 unnamed_device 23.9 MiB 0.40 1609 33316 10415 19690 3211 63.7 MiB 0.18 0.00 6.98035 -294.114 -6.98035 6.98035 0.33 0.000979692 0.000914831 0.0760896 0.0710834 -1 -1 -1 -1 32 3037 18 6.79088e+06 242496 586450. 2029.24 1.57 0.319846 0.2854 24814 144142 -1 2813 16 988 1426 91867 23129 6.58396 6.58396 -295.091 -6.58396 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0326998 0.0292956 98 98 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_064bits.v common 3.69 vpr 64.08 MiB 0.04 6716 -1 -1 26 0.13 -1 -1 32516 -1 -1 23 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65616 129 65 454 519 1 349 217 17 17 289 -1 unnamed_device 24.3 MiB 0.62 2134 47740 17239 26981 3520 64.1 MiB 0.24 0.00 9.1792 -467.226 -9.1792 9.1792 0.33 0.00132682 0.00124252 0.101532 0.0950444 -1 -1 -1 -1 38 3693 17 6.79088e+06 309856 678818. 2348.85 0.94 0.287394 0.260813 25966 169698 -1 3277 14 1240 1597 98903 25444 8.678 8.678 -451.298 -8.678 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0401425 0.0363529 132 132 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_005bits.v common 2.05 vpr 62.20 MiB 0.03 6716 -1 -1 1 0.02 -1 -1 30044 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63692 11 6 41 42 1 27 19 17 17 289 -1 unnamed_device 23.5 MiB 0.04 82 494 104 366 24 62.2 MiB 0.01 0.00 0.811073 -12.9331 -0.811073 0.811073 0.33 0.000109216 0.000100055 0.00239581 0.00218085 -1 -1 -1 -1 22 222 7 6.87369e+06 27947.7 443629. 1535.05 0.59 0.0157082 0.0131251 23458 102101 -1 180 10 122 122 4992 1656 0.936373 0.936373 -14.3779 -0.936373 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00340253 0.00299828 12 2 7 7 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_006bits.v common 2.60 vpr 62.32 MiB 0.03 6612 -1 -1 1 0.02 -1 -1 30100 -1 -1 3 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63812 13 7 48 49 1 33 23 17 17 289 -1 unnamed_device 23.9 MiB 0.04 213 599 129 415 55 62.3 MiB 0.01 0.00 0.833073 -17.625 -0.833073 0.833073 0.33 0.000121975 0.000111736 0.00265288 0.00242771 -1 -1 -1 -1 32 353 12 6.87369e+06 41921.5 586450. 2029.24 1.07 0.0316859 0.0261142 25474 144626 -1 324 9 102 102 10094 2410 0.856592 0.856592 -18.7883 -0.856592 0 0 744469. 2576.02 0.03 0.01 0.12 -1 -1 0.03 0.00351684 0.00310223 15 2 8 8 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_007bits.v common 2.19 vpr 62.48 MiB 0.01 6668 -1 -1 1 0.03 -1 -1 30036 -1 -1 3 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63976 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 24.0 MiB 0.05 187 748 145 594 9 62.5 MiB 0.01 0.00 1.2044 -19.4991 -1.2044 1.2044 0.33 0.000139386 0.000128323 0.00316518 0.00290833 -1 -1 -1 -1 20 408 23 6.87369e+06 41921.5 414966. 1435.87 0.71 0.0194972 0.0163899 23170 95770 -1 392 10 179 179 14036 3970 1.20697 1.20697 -23.1723 -1.20697 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00417982 0.00366155 16 2 9 9 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_008bits.v common 1.96 vpr 62.47 MiB 0.03 6612 -1 -1 1 0.02 -1 -1 30000 -1 -1 3 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63968 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 24.0 MiB 0.05 149 997 208 726 63 62.5 MiB 0.01 0.00 1.2154 -21.2728 -1.2154 1.2154 0.25 7.035e-05 6.3019e-05 0.0019862 0.00178595 -1 -1 -1 -1 22 427 20 6.87369e+06 41921.5 443629. 1535.05 0.49 0.0172433 0.0142862 23458 102101 -1 345 13 233 233 11990 4205 1.12567 1.12567 -24.97 -1.12567 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00514588 0.00445328 19 2 10 10 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_009bits.v common 2.67 vpr 62.71 MiB 0.03 6672 -1 -1 1 0.02 -1 -1 29940 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64220 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 24.3 MiB 0.05 147 1332 336 883 113 62.7 MiB 0.01 0.00 1.2264 -23.8065 -1.2264 1.2264 0.33 0.000183123 0.000169976 0.00519838 0.00480106 -1 -1 -1 -1 32 310 19 6.87369e+06 41921.5 586450. 2029.24 1.08 0.0524689 0.0435148 25474 144626 -1 288 16 301 301 14927 5393 1.08167 1.08167 -24.3353 -1.08167 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00651021 0.00559509 20 2 11 11 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_010bits.v common 2.49 vpr 62.37 MiB 0.02 6712 -1 -1 1 0.02 -1 -1 29996 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63868 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 23.9 MiB 0.05 216 3399 1062 1618 719 62.4 MiB 0.03 0.00 1.2374 -27.5226 -1.2374 1.2374 0.35 0.000231461 0.000214059 0.0120169 0.0111098 -1 -1 -1 -1 28 433 11 6.87369e+06 55895.4 531479. 1839.03 0.91 0.0543141 0.0459095 24610 126494 -1 386 7 154 154 10219 3021 1.02237 1.02237 -29.2086 -1.02237 0 0 648988. 2245.63 0.03 0.01 0.10 -1 -1 0.03 0.00428849 0.00379636 22 2 12 12 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_011bits.v common 1.99 vpr 62.53 MiB 0.03 6704 -1 -1 1 0.02 -1 -1 30008 -1 -1 5 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64032 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 23.8 MiB 0.04 278 1740 348 1260 132 62.5 MiB 0.02 0.00 1.2484 -30.619 -1.2484 1.2484 0.33 0.000212692 0.000197557 0.00602394 0.00558597 -1 -1 -1 -1 30 492 12 6.87369e+06 69869.2 556674. 1926.21 0.43 0.0283989 0.0242014 25186 138497 -1 475 13 163 163 8919 2552 1.14767 1.14767 -34.0748 -1.14767 0 0 706193. 2443.58 0.03 0.02 0.13 -1 -1 0.03 0.00650489 0.00564162 24 2 13 13 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_012bits.v common 2.43 vpr 62.76 MiB 0.02 6708 -1 -1 1 0.02 -1 -1 30068 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64264 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 24.1 MiB 0.05 302 1693 290 1387 16 62.8 MiB 0.02 0.00 1.2594 -34.117 -1.2594 1.2594 0.33 0.000225641 0.000209301 0.00573914 0.00531382 -1 -1 -1 -1 26 604 12 6.87369e+06 69869.2 503264. 1741.40 0.88 0.0560887 0.0469461 24322 120374 -1 553 16 268 268 21363 5538 1.15867 1.15867 -37.5285 -1.15867 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00777771 0.00668641 26 2 14 14 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_013bits.v common 2.39 vpr 62.59 MiB 0.03 6668 -1 -1 1 0.02 -1 -1 29972 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64088 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 23.9 MiB 0.05 267 2752 605 2119 28 62.6 MiB 0.02 0.00 1.2704 -35.8231 -1.2704 1.2704 0.33 0.000237779 0.000220202 0.00864896 0.0080164 -1 -1 -1 -1 28 626 14 6.87369e+06 69869.2 531479. 1839.03 0.79 0.0596084 0.0503997 24610 126494 -1 565 16 360 360 19568 6390 1.11467 1.11467 -38.8099 -1.11467 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.0081905 0.0070539 28 2 15 15 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_014bits.v common 2.65 vpr 62.57 MiB 0.03 6728 -1 -1 1 0.02 -1 -1 30348 -1 -1 6 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 29 15 104 105 1 74 50 17 17 289 -1 unnamed_device 23.9 MiB 0.07 449 4926 1194 3103 629 62.6 MiB 0.04 0.00 1.2814 -41.6008 -1.2814 1.2814 0.34 0.000251491 0.000232904 0.0142724 0.0132062 -1 -1 -1 -1 30 748 14 6.87369e+06 83843 556674. 1926.21 0.98 0.0710628 0.0606964 25186 138497 -1 718 16 331 331 22142 5786 1.14767 1.14767 -43.9267 -1.14767 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00873591 0.00753771 31 2 16 16 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_015bits.v common 2.62 vpr 62.69 MiB 0.03 6648 -1 -1 1 0.02 -1 -1 30212 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 23.9 MiB 0.08 506 3122 687 2071 364 62.7 MiB 0.03 0.00 1.65273 -47.1101 -1.65273 1.65273 0.33 0.000271541 0.000251916 0.00930908 0.00863013 -1 -1 -1 -1 26 972 12 6.87369e+06 83843 503264. 1741.40 0.98 0.0729331 0.0618466 24322 120374 -1 878 14 403 403 35152 8582 1.18967 1.18967 -49.5108 -1.18967 0 0 618332. 2139.56 0.03 0.03 0.10 -1 -1 0.03 0.00844785 0.00733974 32 2 17 17 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_016bits.v common 2.13 vpr 62.65 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30260 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64156 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 23.7 MiB 0.08 355 7118 2954 4050 114 62.7 MiB 0.05 0.00 1.66373 -46.6834 -1.66373 1.66373 0.33 0.000292639 0.000271267 0.0202721 0.0187953 -1 -1 -1 -1 32 794 17 6.87369e+06 83843 586450. 2029.24 0.47 0.0529502 0.0463374 25474 144626 -1 640 13 379 379 22896 6687 1.20067 1.20067 -45.3375 -1.20067 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00851033 0.00741274 35 2 18 18 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_018bits.v common 2.11 vpr 62.69 MiB 0.03 6712 -1 -1 1 0.02 -1 -1 30340 -1 -1 7 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 23.7 MiB 0.08 649 7313 2500 4015 798 62.7 MiB 0.05 0.00 1.68573 -58.9222 -1.68573 1.68573 0.33 0.000329228 0.000305972 0.0201722 0.0187566 -1 -1 -1 -1 30 989 15 6.87369e+06 97816.9 556674. 1926.21 0.43 0.0557943 0.0488353 25186 138497 -1 1001 15 396 396 27469 6892 1.13037 1.13037 -58.2873 -1.13037 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0103837 0.00897525 38 2 20 20 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_020bits.v common 2.66 vpr 62.84 MiB 0.04 6776 -1 -1 1 0.02 -1 -1 30348 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64344 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 23.7 MiB 0.08 664 7846 2295 4568 983 62.8 MiB 0.05 0.00 1.70773 -65.3086 -1.70773 1.70773 0.33 0.000360815 0.000335551 0.0206228 0.0191812 -1 -1 -1 -1 26 1218 15 6.87369e+06 111791 503264. 1741.40 0.97 0.0861072 0.07439 24322 120374 -1 1110 16 473 473 35957 8835 1.22267 1.22267 -65.1761 -1.22267 0 0 618332. 2139.56 0.03 0.03 0.10 -1 -1 0.03 0.0118095 0.010231 42 2 22 22 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_022bits.v common 2.38 vpr 62.82 MiB 0.03 6620 -1 -1 1 0.02 -1 -1 30388 -1 -1 9 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64328 45 23 160 161 1 115 77 17 17 289 -1 unnamed_device 23.7 MiB 0.09 747 10020 3319 5209 1492 62.8 MiB 0.06 0.00 1.72973 -72.3274 -1.72973 1.72973 0.33 0.000390613 0.000363431 0.0251295 0.0233677 -1 -1 -1 -1 32 1248 13 6.87369e+06 125765 586450. 2029.24 0.63 0.0724594 0.0637838 25474 144626 -1 1131 17 445 445 37682 8907 1.17437 1.17437 -69.2803 -1.17437 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.013325 0.0115909 47 2 24 24 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_024bits.v common 2.75 vpr 63.02 MiB 0.01 6712 -1 -1 1 0.02 -1 -1 30424 -1 -1 9 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64528 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 23.8 MiB 0.09 769 9983 2785 6331 867 63.0 MiB 0.07 0.00 2.11206 -79.8727 -2.11206 2.11206 0.33 0.000420086 0.000391143 0.0244999 0.0228072 -1 -1 -1 -1 26 1428 20 6.87369e+06 125765 503264. 1741.40 1.07 0.110999 0.0968084 24322 120374 -1 1344 17 540 540 50274 12230 1.24467 1.24467 -78.2689 -1.24467 0 0 618332. 2139.56 0.03 0.04 0.10 -1 -1 0.03 0.0141755 0.012354 51 2 26 26 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_028bits.v common 2.79 vpr 63.39 MiB 0.04 6812 -1 -1 1 0.02 -1 -1 29920 -1 -1 11 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 24.0 MiB 0.09 986 14527 4652 8514 1361 63.4 MiB 0.09 0.00 2.15606 -99.1531 -2.15606 2.15606 0.33 0.000489951 0.000455425 0.0333882 0.031069 -1 -1 -1 -1 26 1828 21 6.87369e+06 153712 503264. 1741.40 1.06 0.129224 0.113522 24322 120374 -1 1668 18 675 675 67210 15649 1.38567 1.38567 -96.9365 -1.38567 0 0 618332. 2139.56 0.03 0.05 0.10 -1 -1 0.03 0.0170754 0.0149627 58 2 30 30 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_032bits.v common 2.49 vpr 63.42 MiB 0.02 6708 -1 -1 1 0.03 -1 -1 30476 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64940 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 23.8 MiB 0.10 1149 15890 6271 9336 283 63.4 MiB 0.10 0.00 2.56039 -116.289 -2.56039 2.56039 0.33 0.000570494 0.000532024 0.0359975 0.0335798 -1 -1 -1 -1 32 1980 19 6.87369e+06 167686 586450. 2029.24 0.70 0.114387 0.101416 25474 144626 -1 1790 14 625 625 55337 13048 1.32437 1.32437 -103.308 -1.32437 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0161927 0.014281 67 2 34 34 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_048bits.v common 2.84 vpr 63.51 MiB 0.04 6712 -1 -1 1 0.03 -1 -1 30432 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 24.2 MiB 0.14 1584 34212 11837 19501 2874 63.5 MiB 0.21 0.00 3.45705 -191.416 -3.45705 3.45705 0.33 0.000870741 0.000816649 0.0683671 0.0640663 -1 -1 -1 -1 32 2862 16 6.87369e+06 251529 586450. 2029.24 0.78 0.188371 0.170336 25474 144626 -1 2513 15 1047 1047 89318 22265 1.63267 1.63267 -163.007 -1.63267 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0257721 0.0230934 99 2 50 50 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_064bits.v common 4.67 vpr 64.36 MiB 0.04 6876 -1 -1 1 0.03 -1 -1 30368 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65900 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 24.5 MiB 0.14 2195 52618 20545 30099 1974 64.4 MiB 0.33 0.01 4.35372 -284.635 -4.35372 4.35372 0.33 0.00120258 0.00112994 0.099306 0.093418 -1 -1 -1 -1 32 3987 22 6.87369e+06 335372 586450. 2029.24 2.42 0.482133 0.43529 25474 144626 -1 3398 15 1362 1362 111584 27000 1.71237 1.71237 -212.376 -1.71237 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0357095 0.032221 131 2 66 66 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_005bits.v common 2.02 vpr 62.34 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30056 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63832 11 6 41 42 1 27 19 17 17 289 -1 unnamed_device 23.6 MiB 0.04 85 469 97 346 26 62.3 MiB 0.01 0.00 0.850273 -13.1081 -0.850273 0.850273 0.33 0.000104629 9.5431e-05 0.00228532 0.00208162 -1 -1 -1 -1 20 224 19 6.89349e+06 28187.7 414966. 1435.87 0.54 0.00970642 0.00829097 23170 95770 -1 202 12 128 128 7528 2536 1.05067 1.05067 -15.1349 -1.05067 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00366989 0.00319739 12 2 7 7 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_006bits.v common 2.11 vpr 62.34 MiB 0.03 6616 -1 -1 1 0.02 -1 -1 29868 -1 -1 3 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63836 13 7 48 49 1 33 23 17 17 289 -1 unnamed_device 23.9 MiB 0.04 162 727 181 475 71 62.3 MiB 0.01 0.00 0.872273 -16.5201 -0.872273 0.872273 0.33 0.000121537 0.000111263 0.00311797 0.00284901 -1 -1 -1 -1 22 322 13 6.89349e+06 42281.5 443629. 1535.05 0.61 0.0208679 0.0173929 23458 102101 -1 305 11 116 116 8809 2344 0.96032 0.96032 -18.8019 -0.96032 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00388052 0.00340595 15 2 8 8 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_007bits.v common 1.88 vpr 62.41 MiB 0.03 6620 -1 -1 1 0.02 -1 -1 30048 -1 -1 3 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63904 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 23.9 MiB 0.04 188 748 144 591 13 62.4 MiB 0.01 0.00 1.2216 -19.9265 -1.2216 1.2216 0.33 0.000139253 0.000128044 0.00321952 0.0029619 -1 -1 -1 -1 26 377 12 6.89349e+06 42281.5 503264. 1741.40 0.36 0.0186159 0.0157025 24322 120374 -1 329 14 197 197 12002 3194 0.881273 0.881273 -20.4462 -0.881273 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00485855 0.00418679 16 2 9 9 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_008bits.v common 2.08 vpr 62.23 MiB 0.03 6612 -1 -1 1 0.02 -1 -1 30144 -1 -1 3 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63728 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 23.8 MiB 0.04 152 1041 235 743 63 62.2 MiB 0.01 0.00 1.2326 -21.189 -1.2326 1.2326 0.33 0.000157184 0.000144821 0.00417962 0.00384695 -1 -1 -1 -1 20 343 11 6.89349e+06 42281.5 414966. 1435.87 0.58 0.0159801 0.0137231 23170 95770 -1 288 9 138 138 7110 2605 0.875073 0.875073 -22.7178 -0.875073 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00430274 0.00378195 19 2 10 10 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_009bits.v common 2.51 vpr 62.31 MiB 0.02 6644 -1 -1 1 0.02 -1 -1 29980 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63808 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 23.9 MiB 0.04 214 1182 282 820 80 62.3 MiB 0.01 0.00 1.2436 -24.8042 -1.2436 1.2436 0.33 0.00017517 0.000162061 0.00467232 0.004308 -1 -1 -1 -1 26 421 10 6.89349e+06 42281.5 503264. 1741.40 0.96 0.0457991 0.0380226 24322 120374 -1 376 13 193 193 11232 3145 0.995573 0.995573 -26.0806 -0.995573 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00556774 0.00481207 20 2 11 11 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_010bits.v common 2.49 vpr 62.41 MiB 0.03 6616 -1 -1 1 0.02 -1 -1 30076 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63904 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 24.0 MiB 0.04 179 3399 1263 1623 513 62.4 MiB 0.03 0.00 1.2546 -27.4421 -1.2546 1.2546 0.33 0.000191961 0.000177522 0.0116707 0.0107938 -1 -1 -1 -1 26 445 9 6.89349e+06 56375.4 503264. 1741.40 0.90 0.0446987 0.0379883 24322 120374 -1 370 13 231 231 16365 4692 1.12087 1.12087 -28.776 -1.12087 0 0 618332. 2139.56 0.03 0.02 0.12 -1 -1 0.03 0.00888603 0.00761606 22 2 12 12 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_011bits.v common 2.69 vpr 62.41 MiB 0.03 6704 -1 -1 1 0.02 -1 -1 30052 -1 -1 5 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63908 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 23.9 MiB 0.06 276 1604 327 1182 95 62.4 MiB 0.02 0.00 1.2656 -31.3421 -1.2656 1.2656 0.33 0.00021091 0.000195761 0.00556254 0.00515097 -1 -1 -1 -1 32 513 11 6.89349e+06 70469.2 586450. 2029.24 1.13 0.043551 0.0365875 25474 144626 -1 494 8 166 166 12156 3163 0.89902 0.89902 -31.8409 -0.89902 0 0 744469. 2576.02 0.03 0.01 0.12 -1 -1 0.03 0.00491505 0.00433884 24 2 13 13 0 0 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Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 24.0 MiB 0.05 270 2506 503 1985 18 62.6 MiB 0.02 0.00 1.2876 -36.1111 -1.2876 1.2876 0.33 0.000242909 0.000225486 0.0080733 0.00749067 -1 -1 -1 -1 28 602 16 6.89349e+06 70469.2 531479. 1839.03 0.39 0.0346112 0.0297881 24610 126494 -1 545 14 296 296 16842 5312 1.15387 1.15387 -38.9299 -1.15387 0 0 648988. 2245.63 0.03 0.02 0.10 -1 -1 0.03 0.00750924 0.00650717 28 2 15 15 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_014bits.v common 2.50 vpr 62.59 MiB 0.04 6692 -1 -1 1 0.02 -1 -1 30464 -1 -1 6 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 29 15 104 105 1 74 50 17 17 289 -1 unnamed_device 23.9 MiB 0.06 433 3454 892 2308 254 62.6 MiB 0.03 0.00 1.2986 -41.2946 -1.2986 1.2986 0.33 0.00025263 0.000234007 0.0102286 0.00945211 -1 -1 -1 -1 26 790 19 6.89349e+06 84563 503264. 1741.40 0.90 0.0691103 0.0585998 24322 120374 -1 761 9 290 290 20549 5463 0.97132 0.97132 -42.1866 -0.97132 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00604144 0.00534577 31 2 16 16 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_015bits.v common 2.54 vpr 62.51 MiB 0.03 6712 -1 -1 1 0.02 -1 -1 30392 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64008 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 23.8 MiB 0.07 506 3518 755 2345 418 62.5 MiB 0.03 0.00 1.66993 -47.3509 -1.66993 1.66993 0.30 0.000271833 0.000252145 0.0103953 0.00964078 -1 -1 -1 -1 26 937 10 6.89349e+06 84563 503264. 1741.40 0.94 0.0703325 0.0597716 24322 120374 -1 856 10 288 288 21575 5335 1.06632 1.06632 -47.5744 -1.06632 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00672837 0.00590934 32 2 17 17 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_016bits.v common 2.09 vpr 62.57 MiB 0.03 6812 -1 -1 1 0.02 -1 -1 30300 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 23.6 MiB 0.07 355 7118 2968 4031 119 62.6 MiB 0.05 0.00 1.68093 -46.6476 -1.68093 1.68093 0.33 0.000292539 0.000271644 0.02025 0.018783 -1 -1 -1 -1 32 742 16 6.89349e+06 84563 586450. 2029.24 0.44 0.0521433 0.045664 25474 144626 -1 627 13 345 345 22999 6204 1.12567 1.12567 -44.8602 -1.12567 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00839705 0.00729405 35 2 18 18 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_018bits.v common 2.71 vpr 62.67 MiB 0.02 6692 -1 -1 1 0.02 -1 -1 30332 -1 -1 7 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64172 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 23.7 MiB 0.07 618 7313 2319 4209 785 62.7 MiB 0.05 0.00 1.70293 -59.1014 -1.70293 1.70293 0.33 0.000330355 0.000307328 0.0203419 0.018847 -1 -1 -1 -1 26 1056 18 6.89349e+06 98656.9 503264. 1741.40 0.96 0.0990559 0.0848204 24322 120374 -1 974 13 338 338 26941 6941 1.00507 1.00507 -56.0319 -1.00507 0 0 618332. 2139.56 0.03 0.03 0.10 -1 -1 0.03 0.00939027 0.00815172 38 2 20 20 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 2.72 vpr 62.59 MiB 0.01 6612 -1 -1 1 0.02 -1 -1 30332 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 23.6 MiB 0.07 661 7846 2247 4897 702 62.6 MiB 0.05 0.00 1.72493 -65.1086 -1.72493 1.72493 0.33 0.000360281 0.000335234 0.020578 0.0191452 -1 -1 -1 -1 26 1172 14 6.89349e+06 112751 503264. 1741.40 0.96 0.0843787 0.0730066 24322 120374 -1 1083 11 383 383 31932 7864 1.04427 1.04427 -61.1172 -1.04427 0 0 618332. 2139.56 0.03 0.03 0.10 -1 -1 0.03 0.00897434 0.00786025 42 2 22 22 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 2.77 vpr 62.54 MiB 0.04 6692 -1 -1 1 0.02 -1 -1 30456 -1 -1 9 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64040 45 23 160 161 1 115 77 17 17 289 -1 unnamed_device 23.4 MiB 0.07 760 10020 3321 5690 1009 62.5 MiB 0.07 0.00 1.74693 -72.6551 -1.74693 1.74693 0.33 0.000391929 0.000364742 0.025148 0.0233979 -1 -1 -1 -1 28 1350 16 6.89349e+06 126845 531479. 1839.03 1.10 0.113977 0.098921 24610 126494 -1 1226 9 414 414 32996 8098 1.28387 1.28387 -71.8955 -1.28387 0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.00872835 0.00771702 47 2 24 24 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_024bits.v common 2.70 vpr 62.80 MiB 0.02 6668 -1 -1 1 0.03 -1 -1 30380 -1 -1 9 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 23.9 MiB 0.08 809 9983 2879 5663 1441 62.8 MiB 0.07 0.00 2.12926 -80.2814 -2.12926 2.12926 0.33 0.000421866 0.000392654 0.0245734 0.0228767 -1 -1 -1 -1 30 1352 17 6.89349e+06 126845 556674. 1926.21 0.92 0.111078 0.0966581 25186 138497 -1 1223 10 398 398 27529 6709 1.10827 1.10827 -72.8896 -1.10827 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0100241 0.00886901 51 2 26 26 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 3.26 vpr 62.83 MiB 0.04 6812 -1 -1 1 0.03 -1 -1 30012 -1 -1 11 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64340 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 23.5 MiB 0.08 997 14527 5181 7993 1353 62.8 MiB 0.09 0.00 2.17326 -99.1204 -2.17326 2.17326 0.33 0.00048722 0.000453359 0.0331513 0.0308519 -1 -1 -1 -1 28 1682 13 6.89349e+06 155032 531479. 1839.03 1.35 0.141383 0.123982 24610 126494 -1 1549 13 587 587 48315 11675 1.14137 1.14137 -86.9212 -1.14137 0 0 648988. 2245.63 0.03 0.04 0.10 -1 -1 0.03 0.0133467 0.0117682 58 2 30 30 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 2.56 vpr 63.10 MiB 0.03 6584 -1 -1 1 0.03 -1 -1 30264 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64616 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1136 15890 5118 9153 1619 63.1 MiB 0.10 0.00 2.57759 -117.501 -2.57759 2.57759 0.33 0.000568098 0.000530316 0.035727 0.0333474 -1 -1 -1 -1 32 1885 15 6.89349e+06 169126 586450. 2029.24 0.69 0.11053 0.0980873 25474 144626 -1 1735 13 637 637 57371 14126 1.35267 1.35267 -103.967 -1.35267 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0154282 0.013613 67 2 34 34 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 2.90 vpr 63.45 MiB 0.04 6712 -1 -1 1 0.03 -1 -1 30348 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64972 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1589 34212 11441 20008 2763 63.4 MiB 0.21 0.00 3.47425 -191.764 -3.47425 3.47425 0.33 0.000867802 0.000813674 0.0684317 0.0641065 -1 -1 -1 -1 32 2773 23 6.89349e+06 253689 586450. 2029.24 0.85 0.216363 0.194841 25474 144626 -1 2491 16 873 873 69957 17320 1.44532 1.44532 -153.656 -1.44532 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0271503 0.0243172 99 2 50 50 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_064bits.v common 3.32 vpr 63.73 MiB 0.02 6736 -1 -1 1 0.03 -1 -1 30372 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65256 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 24.4 MiB 0.13 2213 52618 20882 30344 1392 63.7 MiB 0.33 0.01 4.37092 -286.442 -4.37092 4.37092 0.33 0.0012033 0.001131 0.0996157 0.0936493 -1 -1 -1 -1 32 3862 23 6.89349e+06 338252 586450. 2029.24 1.06 0.296664 0.270031 25474 144626 -1 3389 12 1184 1184 101124 24774 1.64837 1.64837 -210.641 -1.64837 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0298483 0.0270215 131 2 66 66 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt index b09eed101d9..0581e25a8ca 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt @@ -1,1025 +1,1025 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 5.22 vpr 63.83 MiB 0.03 7104 -1 -1 14 0.34 -1 -1 36588 -1 -1 26 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65364 32 32 280 312 1 203 90 17 17 289 -1 unnamed_device 25.0 MiB 0.26 1396 5718 1043 4241 434 63.8 MiB 0.05 0.00 8.33526 -166.471 -8.33526 8.33526 0.85 0.000298132 0.000238364 0.0117609 0.00981176 -1 -1 -1 -1 28 3716 42 6.55708e+06 313430 500653. 1732.36 1.65 0.0689479 0.0577638 21310 115450 -1 3004 21 1526 4795 248684 58174 7.4395 7.4395 -161.842 -7.4395 0 0 612192. 2118.31 0.23 0.07 0.10 -1 -1 0.23 0.0202595 0.017917 186 186 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_002.v common 6.05 vpr 64.09 MiB 0.02 6952 -1 -1 14 0.37 -1 -1 36552 -1 -1 30 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65624 30 32 277 309 1 214 92 17 17 289 -1 unnamed_device 25.3 MiB 0.48 1292 9821 2314 6313 1194 64.1 MiB 0.07 0.00 7.97266 -161.847 -7.97266 7.97266 0.86 0.000279394 0.000221618 0.0166927 0.0134901 -1 -1 -1 -1 28 4133 49 6.55708e+06 361650 500653. 1732.36 1.94 0.0776588 0.0645059 21310 115450 -1 3143 20 1590 4541 279442 69927 7.1579 7.1579 -156.969 -7.1579 0 0 612192. 2118.31 0.54 0.07 0.11 -1 -1 0.54 0.0181305 0.0160094 189 189 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_003.v common 7.42 vpr 64.04 MiB 0.02 6880 -1 -1 11 0.26 -1 -1 36548 -1 -1 25 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65572 32 32 274 306 1 208 89 17 17 289 -1 unnamed_device 25.3 MiB 0.40 1387 5633 1032 4013 588 64.0 MiB 0.05 0.00 6.70549 -144.379 -6.70549 6.70549 0.83 0.000279145 0.000222543 0.0107434 0.00891549 -1 -1 -1 -1 38 3367 24 6.55708e+06 301375 638502. 2209.35 3.88 0.124863 0.104095 23326 155178 -1 2938 15 1203 3923 204412 45867 5.90278 5.90278 -137.681 -5.90278 0 0 851065. 2944.86 0.30 0.06 0.12 -1 -1 0.30 0.0163744 0.0147263 180 180 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_004.v common 5.60 vpr 64.01 MiB 0.02 7068 -1 -1 12 0.42 -1 -1 36704 -1 -1 29 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65548 29 32 269 301 1 203 90 17 17 289 -1 unnamed_device 25.2 MiB 0.44 1235 6522 1332 4656 534 64.0 MiB 0.05 0.00 7.67294 -144.969 -7.67294 7.67294 0.83 0.000278308 0.000221884 0.0118876 0.00978677 -1 -1 -1 -1 32 3833 44 6.55708e+06 349595 554710. 1919.41 1.83 0.0860144 0.0720033 22174 131602 -1 3094 42 2072 6957 632362 219498 7.25558 7.25558 -144.225 -7.25558 0 0 701300. 2426.64 0.26 0.15 0.11 -1 -1 0.26 0.0286853 0.0246033 185 184 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_005.v common 5.92 vpr 63.16 MiB 0.02 6896 -1 -1 13 0.40 -1 -1 36720 -1 -1 31 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64680 32 32 317 349 1 246 95 17 17 289 -1 unnamed_device 24.4 MiB 0.45 1620 8303 2009 5589 705 63.2 MiB 0.07 0.00 7.84931 -165.878 -7.84931 7.84931 0.93 0.000321232 0.00025629 0.0164354 0.0135238 -1 -1 -1 -1 30 4081 45 6.55708e+06 373705 526063. 1820.29 1.84 0.0971766 0.0824286 21886 126133 -1 3417 31 2192 6994 649153 243609 6.9587 6.9587 -160.39 -6.9587 0 0 666494. 2306.21 0.26 0.16 0.11 -1 -1 0.26 0.028572 0.0249935 224 223 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_006.v common 10.17 vpr 64.12 MiB 0.04 7008 -1 -1 12 0.34 -1 -1 36400 -1 -1 31 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65660 32 32 299 331 1 224 95 17 17 289 -1 unnamed_device 25.2 MiB 0.75 1415 13055 3582 8009 1464 64.1 MiB 0.09 0.00 7.00015 -146.985 -7.00015 7.00015 0.89 0.00031654 0.000247097 0.0221928 0.0178846 -1 -1 -1 -1 28 4777 41 6.55708e+06 373705 500653. 1732.36 5.70 0.160482 0.132999 21310 115450 -1 3425 17 1556 4990 279641 64342 6.22218 6.22218 -144.978 -6.22218 0 0 612192. 2118.31 0.34 0.07 0.24 -1 -1 0.34 0.0173854 0.0155007 206 205 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 6.18 vpr 63.48 MiB 0.02 6852 -1 -1 12 0.22 -1 -1 36320 -1 -1 27 27 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65000 27 32 210 242 1 165 86 17 17 289 -1 unnamed_device 24.7 MiB 0.44 974 6890 1587 4820 483 63.5 MiB 0.04 0.00 6.94984 -127.162 -6.94984 6.94984 0.84 0.000215012 0.000171308 0.0102381 0.00843267 -1 -1 -1 -1 28 2654 18 6.55708e+06 325485 500653. 1732.36 2.67 0.0775907 0.0646235 21310 115450 -1 2427 19 1010 2929 164353 38329 6.09998 6.09998 -124.429 -6.09998 0 0 612192. 2118.31 0.23 0.05 0.09 -1 -1 0.23 0.0129959 0.0114885 137 131 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_008.v common 5.01 vpr 63.83 MiB 0.02 7092 -1 -1 11 0.22 -1 -1 36588 -1 -1 28 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65360 31 32 264 296 1 200 91 17 17 289 -1 unnamed_device 24.9 MiB 0.29 1315 7231 1531 4891 809 63.8 MiB 0.05 0.00 6.53897 -136.036 -6.53897 6.53897 0.84 0.000258039 0.000203995 0.0120496 0.00982378 -1 -1 -1 -1 30 3221 27 6.55708e+06 337540 526063. 1820.29 1.56 0.0697046 0.059383 21886 126133 -1 2714 16 1147 3840 187272 43051 5.50098 5.50098 -128.943 -5.50098 0 0 666494. 2306.21 0.28 0.06 0.11 -1 -1 0.28 0.0171813 0.0154819 175 173 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_009.v common 8.07 vpr 63.88 MiB 0.02 6784 -1 -1 12 0.21 -1 -1 35732 -1 -1 25 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65412 31 32 234 266 1 190 88 17 17 289 -1 unnamed_device 24.9 MiB 0.40 1115 11203 2815 6442 1946 63.9 MiB 0.08 0.00 6.90263 -147 -6.90263 6.90263 0.90 0.000241734 0.000192658 0.0179692 0.0147247 -1 -1 -1 -1 30 2958 44 6.55708e+06 301375 526063. 1820.29 4.07 0.117929 0.098719 21886 126133 -1 2303 12 926 2399 117672 28295 6.17898 6.17898 -142.174 -6.17898 0 0 666494. 2306.21 0.55 0.04 0.13 -1 -1 0.55 0.0117269 0.010674 145 143 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_010.v common 5.40 vpr 63.82 MiB 0.02 6908 -1 -1 13 0.23 -1 -1 36480 -1 -1 25 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65356 32 32 253 285 1 194 89 17 17 289 -1 unnamed_device 25.0 MiB 0.56 1192 15137 4443 8200 2494 63.8 MiB 0.09 0.00 7.39554 -161.911 -7.39554 7.39554 0.89 0.000253042 0.000202028 0.0226291 0.0183277 -1 -1 -1 -1 30 3232 46 6.55708e+06 301375 526063. 1820.29 1.46 0.0802749 0.0670454 21886 126133 -1 2512 16 1069 2908 152436 34980 6.42904 6.42904 -155.481 -6.42904 0 0 666494. 2306.21 0.28 0.06 0.11 -1 -1 0.28 0.0189785 0.017127 162 159 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_011.v common 6.55 vpr 63.38 MiB 0.02 6884 -1 -1 12 0.20 -1 -1 36556 -1 -1 22 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64900 30 32 217 249 1 169 84 17 17 289 -1 unnamed_device 24.6 MiB 0.45 1009 4842 919 3670 253 63.4 MiB 0.04 0.00 7.00015 -143.218 -7.00015 7.00015 0.87 0.000220011 0.000175717 0.00853566 0.00713455 -1 -1 -1 -1 26 2871 22 6.55708e+06 265210 477104. 1650.88 3.11 0.0900748 0.0760941 21022 109990 -1 2368 17 940 2361 135836 31778 6.06078 6.06078 -139.79 -6.06078 0 0 585099. 2024.56 0.25 0.04 0.09 -1 -1 0.25 0.0130152 0.0115551 132 129 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_012.v common 7.24 vpr 63.75 MiB 0.02 6944 -1 -1 12 0.17 -1 -1 36084 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65280 32 32 227 259 1 176 85 17 17 289 -1 unnamed_device 24.9 MiB 0.24 1020 12547 3823 6487 2237 63.8 MiB 0.08 0.00 6.61272 -143.64 -6.61272 6.61272 0.84 0.000217803 0.000172726 0.0177674 0.0143939 -1 -1 -1 -1 30 2715 21 6.55708e+06 253155 526063. 1820.29 3.85 0.0933524 0.0779977 21886 126133 -1 2267 16 994 2621 133216 32040 5.61918 5.61918 -136.187 -5.61918 0 0 666494. 2306.21 0.26 0.04 0.11 -1 -1 0.26 0.0127213 0.0114209 138 133 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_013.v common 7.26 vpr 64.27 MiB 0.02 7056 -1 -1 13 0.33 -1 -1 37072 -1 -1 31 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65816 32 32 306 338 1 236 95 17 17 289 -1 unnamed_device 25.3 MiB 0.48 1509 7439 1652 5093 694 64.3 MiB 0.07 0.00 8.16384 -167.563 -8.16384 8.16384 0.88 0.000320998 0.000255221 0.0154697 0.0127613 -1 -1 -1 -1 32 3500 18 6.55708e+06 373705 554710. 1919.41 3.28 0.142958 0.11998 22174 131602 -1 3114 18 1384 4275 227959 52912 6.8823 6.8823 -154.863 -6.8823 0 0 701300. 2426.64 0.29 0.08 0.12 -1 -1 0.29 0.0228379 0.0205497 212 212 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_014.v common 12.34 vpr 64.51 MiB 0.02 7032 -1 -1 14 0.41 -1 -1 37004 -1 -1 29 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66060 32 32 302 334 1 235 93 17 17 289 -1 unnamed_device 25.5 MiB 0.52 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65484 32 32 259 291 1 202 91 17 17 289 -1 unnamed_device 25.0 MiB 0.29 1261 6619 1462 4468 689 63.9 MiB 0.05 0.00 7.87238 -161.512 -7.87238 7.87238 0.84 0.000258374 0.00020518 0.0110293 0.00907364 -1 -1 -1 -1 28 3782 22 6.55708e+06 325485 500653. 1732.36 1.41 0.0633755 0.0538763 21310 115450 -1 2987 36 1896 5422 530398 211567 6.74584 6.74584 -155.563 -6.74584 0 0 612192. 2118.31 0.26 0.16 0.10 -1 -1 0.26 0.0270705 0.0234281 167 165 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_115.v common 8.29 vpr 63.89 MiB 0.02 6992 -1 -1 13 0.32 -1 -1 36744 -1 -1 29 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65420 32 32 277 309 1 220 93 17 17 289 -1 unnamed_device 25.1 MiB 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Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65748 30 32 409 330 1 186 85 17 17 289 -1 unnamed_device 25.2 MiB 0.21 873 12919 4129 6395 2395 64.2 MiB 0.11 0.00 4.45516 -130.844 -4.45516 4.45516 0.89 0.000227213 0.000178692 0.0205306 0.016632 -1 -1 -1 -1 32 2188 21 6.64007e+06 288834 554710. 1919.41 0.97 0.0618261 0.0513815 22834 132086 -1 1899 23 1583 2754 164100 38700 3.84263 3.84263 -133.584 -3.84263 0 0 701300. 2426.64 0.30 0.06 0.13 -1 -1 0.30 0.0166886 0.0145581 142 91 30 30 89 30 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 4.12 vpr 64.32 MiB 0.02 7132 -1 -1 1 0.04 -1 -1 34196 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65864 32 32 387 309 1 186 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-1 26 2361 21 6.64007e+06 301392 477104. 1650.88 0.87 0.0530226 0.0443146 21682 110474 -1 1898 19 1382 2391 133144 31525 3.75363 3.75363 -131.002 -3.75363 0 0 585099. 2024.56 0.25 0.05 0.10 -1 -1 0.25 0.01433 0.0126017 138 34 87 29 29 29 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 4.16 vpr 64.22 MiB 0.02 7096 -1 -1 1 0.04 -1 -1 33828 -1 -1 22 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65764 32 32 376 288 1 195 86 17 17 289 -1 unnamed_device 25.3 MiB 0.15 849 15017 4515 8552 1950 64.2 MiB 0.13 0.00 4.14936 -139.21 -4.14936 4.14936 0.85 0.000243855 0.00019718 0.0213406 0.0171585 -1 -1 -1 -1 32 2158 19 6.64007e+06 276276 554710. 1919.41 0.93 0.0598378 0.0492011 22834 132086 -1 1883 23 1627 2940 175616 44084 3.50723 3.50723 -131.536 -3.50723 0 0 701300. 2426.64 0.29 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34368 -1 -1 20 27 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65300 27 32 269 226 1 135 79 17 17 289 -1 unnamed_device 24.8 MiB 0.12 536 12754 3285 8720 749 63.8 MiB 0.08 0.00 3.7877 -97.0533 -3.7877 3.7877 0.84 0.000161805 0.000127881 0.0142715 0.0115701 -1 -1 -1 -1 32 1263 20 6.64007e+06 251160 554710. 1919.41 0.99 0.0469307 0.0394295 22834 132086 -1 1040 20 890 1548 89627 21823 2.79977 2.79977 -89.8593 -2.79977 0 0 701300. 2426.64 0.30 0.04 0.12 -1 -1 0.30 0.0122122 0.0107845 97 34 54 27 27 27 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 4.34 vpr 64.30 MiB 0.02 7228 -1 -1 1 0.04 -1 -1 33624 -1 -1 34 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65848 31 32 317 242 1 185 97 17 17 289 -1 unnamed_device 25.4 MiB 0.14 948 16081 4441 8879 2761 64.3 MiB 0.12 0.00 3.49449 -109.504 -3.49449 3.49449 0.90 0.000233602 0.000187103 0.018421 0.0150374 -1 -1 -1 -1 28 2250 21 6.64007e+06 426972 500653. 1732.36 0.96 0.0538166 0.0450278 21970 115934 -1 1978 20 1191 1997 126595 29386 2.65357 2.65357 -104.975 -2.65357 0 0 612192. 2118.31 0.25 0.05 0.10 -1 -1 0.25 0.0139128 0.0120919 140 4 115 31 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 3.91 vpr 63.79 MiB 0.02 7108 -1 -1 1 0.03 -1 -1 34008 -1 -1 17 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65316 31 32 338 292 1 147 80 17 17 289 -1 unnamed_device 24.9 MiB 0.18 706 7820 1805 5417 598 63.8 MiB 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132086 -1 1778 22 1293 2043 128760 29112 2.85677 2.85677 -120.971 -2.85677 0 0 701300. 2426.64 0.31 0.05 0.12 -1 -1 0.31 0.0136456 0.0119649 121 34 64 32 32 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 4.29 vpr 63.91 MiB 0.02 7088 -1 -1 1 0.04 -1 -1 33784 -1 -1 18 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65448 30 32 325 273 1 151 80 17 17 289 -1 unnamed_device 25.0 MiB 0.18 822 14012 5060 7295 1657 63.9 MiB 0.10 0.00 3.4841 -115.834 -3.4841 3.4841 0.95 0.000216729 0.000174733 0.0187339 0.015216 -1 -1 -1 -1 28 1790 20 6.64007e+06 226044 500653. 1732.36 0.83 0.050825 0.0423282 21970 115934 -1 1551 18 1049 1513 95909 21865 2.76697 2.76697 -110.142 -2.76697 0 0 612192. 2118.31 0.26 0.04 0.10 -1 -1 0.26 0.0127133 0.0111761 110 63 30 30 60 30 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 386 305 1 188 98 17 17 289 -1 unnamed_device 25.3 MiB 0.21 893 19448 6133 10048 3267 64.3 MiB 0.16 0.00 3.56129 -122.026 -3.56129 3.56129 0.97 0.000249057 0.000200043 0.0238154 0.0191416 -1 -1 -1 -1 32 2126 22 6.64007e+06 426972 554710. 1919.41 1.00 0.0679577 0.0566976 22834 132086 -1 1768 20 1395 2386 143294 33441 2.87597 2.87597 -115.245 -2.87597 0 0 701300. 2426.64 0.30 0.05 0.14 -1 -1 0.30 0.0152489 0.0134 145 58 64 32 57 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 4.22 vpr 64.31 MiB 0.02 7232 -1 -1 1 0.04 -1 -1 34120 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66048 32 32 376 288 1 194 99 17 17 289 -1 unnamed_device 25.4 MiB 0.11 956 14691 4376 8904 1411 64.5 MiB 0.11 0.00 4.18856 -140.856 -4.18856 4.18856 0.87 0.000214277 0.000168514 0.0164732 0.0131539 -1 -1 -1 -1 32 2374 20 6.64007e+06 439530 554710. 1919.41 0.99 0.0570988 0.0477004 22834 132086 -1 2007 22 1606 2528 142742 34241 3.66543 3.66543 -137.36 -3.66543 0 0 701300. 2426.64 0.30 0.05 0.12 -1 -1 0.30 0.0163222 0.0143776 153 34 96 32 32 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 5.05 vpr 64.33 MiB 0.02 7024 -1 -1 1 0.04 -1 -1 34052 -1 -1 37 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65872 32 32 337 253 1 196 101 17 17 289 -1 unnamed_device 25.5 MiB 0.12 1019 8796 1857 6524 415 64.3 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65864 31 32 391 309 1 194 87 17 17 289 -1 unnamed_device 25.4 MiB 0.20 1058 10839 2803 6606 1430 64.3 MiB 0.09 0.00 3.4841 -118.469 -3.4841 3.4841 0.86 0.000221674 0.000175555 0.0145427 0.0117407 -1 -1 -1 -1 28 2547 22 6.64007e+06 301392 500653. 1732.36 0.90 0.0534732 0.0443312 21970 115934 -1 2220 21 1654 2736 175719 41104 3.11837 3.11837 -120.431 -3.11837 0 0 612192. 2118.31 0.27 0.06 0.10 -1 -1 0.27 0.01537 0.0133577 149 64 60 30 62 31 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 4.71 vpr 64.38 MiB 0.03 7248 -1 -1 1 0.05 -1 -1 34308 -1 -1 23 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65924 31 32 455 371 1 193 86 17 17 289 -1 unnamed_device 25.5 MiB 0.40 953 7835 1760 5704 371 64.4 MiB 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65528 31 32 305 250 1 158 81 17 17 289 -1 unnamed_device 25.2 MiB 0.14 655 13731 5030 6417 2284 64.0 MiB 0.09 0.00 3.7665 -117.146 -3.7665 3.7665 0.92 0.000186017 0.00014681 0.0168689 0.0135111 -1 -1 -1 -1 32 1675 22 6.64007e+06 226044 554710. 1919.41 0.92 0.0490117 0.0404927 22834 132086 -1 1426 19 1054 1688 97004 24503 2.74857 2.74857 -108.046 -2.74857 0 0 701300. 2426.64 0.30 0.04 0.12 -1 -1 0.30 0.0123819 0.0108236 116 34 62 31 31 31 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 4.38 vpr 64.52 MiB 0.02 7180 -1 -1 1 0.04 -1 -1 34092 -1 -1 38 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66068 31 32 395 311 1 196 101 17 17 289 -1 unnamed_device 25.7 MiB 0.15 910 7386 1527 5477 382 64.5 MiB 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65660 32 32 312 255 1 166 95 17 17 289 -1 unnamed_device 25.1 MiB 0.12 928 8735 1852 5986 897 64.1 MiB 0.06 0.00 3.50687 -122.364 -3.50687 3.50687 0.85 0.000201805 0.000161795 0.00962113 0.00787879 -1 -1 -1 -1 28 2268 21 6.64007e+06 389298 500653. 1732.36 0.88 0.0413011 0.0342616 21970 115934 -1 1966 19 1238 1976 126734 29630 3.00117 3.00117 -120.372 -3.00117 0 0 612192. 2118.31 0.27 0.04 0.10 -1 -1 0.27 0.0113774 0.00996614 125 34 63 32 32 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 4.25 vpr 64.13 MiB 0.02 7104 -1 -1 1 0.04 -1 -1 33876 -1 -1 18 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65672 32 32 370 314 1 164 82 17 17 289 -1 unnamed_device 25.4 MiB 0.20 885 10406 2864 6861 681 64.1 MiB 0.09 0.00 3.5031 -121.505 -3.5031 3.5031 0.92 0.000205124 0.000161668 0.0156831 0.012803 -1 -1 -1 -1 26 2176 22 6.64007e+06 226044 477104. 1650.88 0.87 0.0551054 0.0459777 21682 110474 -1 1889 21 1261 2024 140942 31764 3.17337 3.17337 -121.891 -3.17337 0 0 585099. 2024.56 0.26 0.05 0.11 -1 -1 0.26 0.0151839 0.0133115 121 94 0 0 94 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 4.31 vpr 63.74 MiB 0.03 7260 -1 -1 1 0.04 -1 -1 34180 -1 -1 42 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65272 32 32 469 351 1 233 106 17 17 289 -1 unnamed_device 25.0 MiB 0.14 1352 17606 4821 10688 2097 63.7 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65924 32 32 376 288 1 194 102 17 17 289 -1 unnamed_device 25.3 MiB 0.13 1027 16762 4357 10483 1922 64.4 MiB 0.12 0.00 4.27488 -146.847 -4.27488 4.27488 0.86 0.000231769 0.000184248 0.0180869 0.0143812 -1 -1 -1 -1 28 2732 21 6.64007e+06 477204 500653. 1732.36 0.91 0.0577514 0.0476383 21970 115934 -1 2262 19 1618 2382 151152 37456 3.85383 3.85383 -149.152 -3.85383 0 0 612192. 2118.31 0.26 0.05 0.10 -1 -1 0.26 0.015425 0.0135776 153 34 96 32 32 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 4.05 vpr 64.03 MiB 0.02 6916 -1 -1 1 0.03 -1 -1 34024 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65564 32 32 283 225 1 164 96 17 17 289 -1 unnamed_device 25.1 MiB 0.08 882 11046 2802 6952 1292 64.0 MiB 0.09 0.00 3.5621 -124.172 -3.5621 3.5621 0.96 0.000189392 0.000150366 0.0118212 0.00960726 -1 -1 -1 -1 30 1789 19 6.64007e+06 401856 526063. 1820.29 0.87 0.0428872 0.0358449 22546 126617 -1 1527 18 784 1304 70997 17006 2.46797 2.46797 -107.154 -2.46797 0 0 666494. 2306.21 0.28 0.03 0.11 -1 -1 0.28 0.0111268 0.00982292 124 3 96 32 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 4.39 vpr 64.39 MiB 0.03 7068 -1 -1 1 0.04 -1 -1 34344 -1 -1 43 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65940 32 32 438 320 1 235 107 17 17 289 -1 unnamed_device 25.8 MiB 0.16 1334 20347 5362 13158 1827 64.4 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65912 32 32 407 319 1 194 86 17 17 289 -1 unnamed_device 25.6 MiB 0.17 937 11048 2797 7564 687 64.4 MiB 0.09 0.00 4.21976 -143.232 -4.21976 4.21976 0.87 0.000224116 0.000176908 0.0162198 0.0132135 -1 -1 -1 -1 32 2064 24 6.64007e+06 276276 554710. 1919.41 1.01 0.0601819 0.0504569 22834 132086 -1 1768 20 1585 2461 150379 34846 3.63243 3.63243 -140.901 -3.63243 0 0 701300. 2426.64 0.29 0.06 0.12 -1 -1 0.29 0.018671 0.0163887 152 65 64 32 64 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 4.35 vpr 64.34 MiB 0.02 7140 -1 -1 1 0.04 -1 -1 34284 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65884 32 32 407 319 1 195 100 17 17 289 -1 unnamed_device 25.6 MiB 0.26 1070 15876 4480 9346 2050 64.3 MiB 0.14 0.00 4.25856 -146.098 -4.25856 4.25856 0.86 0.000234164 0.000186199 0.0192536 0.0154407 -1 -1 -1 -1 32 2599 21 6.64007e+06 452088 554710. 1919.41 0.99 0.0600367 0.0497525 22834 132086 -1 2322 21 1600 2740 173936 39501 3.61523 3.61523 -141.653 -3.61523 0 0 701300. 2426.64 0.29 0.06 0.12 -1 -1 0.29 0.015469 0.0135641 154 65 64 32 64 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 4.36 vpr 64.02 MiB 0.02 6916 -1 -1 1 0.04 -1 -1 34200 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65552 32 32 345 287 1 161 96 17 17 289 -1 unnamed_device 25.0 MiB 0.15 863 8856 1892 6516 448 64.0 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65572 30 32 325 273 1 157 81 17 17 289 -1 unnamed_device 25.3 MiB 0.17 812 12506 4081 6359 2066 64.0 MiB 0.09 0.00 3.5343 -115.469 -3.5343 3.5343 0.87 0.000192273 0.000151488 0.0162237 0.0130458 -1 -1 -1 -1 32 1937 21 6.64007e+06 238602 554710. 1919.41 0.91 0.0503033 0.0412744 22834 132086 -1 1726 23 1277 2198 156154 33320 2.60657 2.60657 -105.956 -2.60657 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.0144274 0.0124512 115 63 30 30 60 30 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 4.42 vpr 64.15 MiB 0.02 7072 -1 -1 1 0.04 -1 -1 33980 -1 -1 17 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65692 32 32 361 308 1 158 81 17 17 289 -1 unnamed_device 25.1 MiB 0.21 892 11281 2807 6986 1488 64.2 MiB 0.09 0.00 3.6865 -117.315 -3.6865 3.6865 1.00 0.000231686 0.000166095 0.0162594 0.0131115 -1 -1 -1 -1 30 1814 21 6.64007e+06 213486 526063. 1820.29 0.85 0.0531827 0.0438512 22546 126617 -1 1687 17 815 1359 86402 19223 2.67457 2.67457 -106.696 -2.67457 0 0 666494. 2306.21 0.28 0.04 0.11 -1 -1 0.28 0.0130339 0.0114756 114 91 0 0 91 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 4.41 vpr 64.18 MiB 0.03 7076 -1 -1 1 0.05 -1 -1 34084 -1 -1 37 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65720 31 32 335 251 1 196 100 17 17 289 -1 unnamed_device 25.3 MiB 0.11 1121 19124 6194 10224 2706 64.2 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65588 30 32 296 244 1 156 81 17 17 289 -1 unnamed_device 25.2 MiB 0.15 840 12856 4254 6466 2136 64.1 MiB 0.08 0.00 3.4921 -115.538 -3.4921 3.4921 0.85 0.000177735 0.000140207 0.0148918 0.0119814 -1 -1 -1 -1 32 1934 20 6.64007e+06 238602 554710. 1919.41 0.89 0.0448034 0.037139 22834 132086 -1 1742 21 1067 1755 114510 25571 2.86097 2.86097 -113.552 -2.86097 0 0 701300. 2426.64 0.29 0.04 0.12 -1 -1 0.29 0.012042 0.0105224 113 34 60 30 30 30 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 4.42 vpr 64.37 MiB 0.02 7184 -1 -1 1 0.04 -1 -1 34140 -1 -1 24 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65916 30 32 383 303 1 191 86 17 17 289 -1 unnamed_device 25.4 MiB 0.23 996 13127 3599 7422 2106 64.4 MiB 0.10 0.00 4.20393 -135.69 -4.20393 4.20393 0.88 0.00027076 0.000224256 0.0185437 0.0151405 -1 -1 -1 -1 26 2442 22 6.64007e+06 301392 477104. 1650.88 1.03 0.0631652 0.0531875 21682 110474 -1 2103 20 1623 2452 154154 35629 3.91003 3.91003 -142.145 -3.91003 0 0 585099. 2024.56 0.25 0.06 0.10 -1 -1 0.25 0.0164675 0.0144506 146 63 60 30 60 30 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 4.63 vpr 64.98 MiB 0.02 7308 -1 -1 1 0.04 -1 -1 34508 -1 -1 41 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66544 32 32 469 381 1 198 105 17 17 289 -1 unnamed_device 25.8 MiB 0.24 1061 10232 2187 7405 640 65.0 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65884 29 32 387 316 1 179 97 17 17 289 -1 unnamed_device 25.4 MiB 0.18 964 18079 5198 10699 2182 64.3 MiB 0.12 0.00 3.5353 -109.347 -3.5353 3.5353 0.89 0.000211216 0.000166725 0.0198423 0.0157529 -1 -1 -1 -1 32 2001 18 6.64007e+06 452088 554710. 1919.41 0.95 0.0622356 0.0517002 22834 132086 -1 1793 18 1207 1991 113093 26929 2.78997 2.78997 -103.83 -2.78997 0 0 701300. 2426.64 0.33 0.05 0.12 -1 -1 0.33 0.0154254 0.013583 136 88 26 26 85 29 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 4.20 vpr 63.82 MiB 0.02 6864 -1 -1 1 0.04 -1 -1 33836 -1 -1 17 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65868 32 32 381 303 1 188 97 17 17 289 -1 unnamed_device 25.3 MiB 0.20 927 16303 4785 8793 2725 64.3 MiB 0.12 0.00 4.16476 -135.871 -4.16476 4.16476 0.86 0.000214425 0.000169547 0.0186242 0.0149077 -1 -1 -1 -1 32 2140 22 6.64007e+06 414414 554710. 1919.41 0.94 0.0578515 0.0477727 22834 132086 -1 1889 20 1256 1910 116840 27528 3.41802 3.41802 -125.912 -3.41802 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.0157401 0.0137388 139 59 60 32 58 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 4.32 vpr 64.27 MiB 0.02 7348 -1 -1 1 0.04 -1 -1 34292 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65816 32 32 406 330 1 190 96 17 17 289 -1 unnamed_device 25.3 MiB 0.14 1051 17397 5163 9750 2484 64.3 MiB 0.13 0.00 4.41596 -136.112 -4.41596 4.41596 0.86 0.000231919 0.000184321 0.0204928 0.016475 -1 -1 -1 -1 26 2810 21 6.64007e+06 401856 477104. 1650.88 1.18 0.0640676 0.0533102 21682 110474 -1 2235 21 1299 2191 157955 34760 3.91883 3.91883 -135.985 -3.91883 0 0 585099. 2024.56 0.25 0.05 0.10 -1 -1 0.25 0.0148661 0.0129345 136 88 28 28 88 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 4.52 vpr 63.97 MiB 0.03 7192 -1 -1 1 0.04 -1 -1 34004 -1 -1 37 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65504 32 32 399 285 1 228 101 17 17 289 -1 unnamed_device 25.4 MiB 0.12 1159 10441 2545 7247 649 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65860 31 32 455 371 1 188 85 17 17 289 -1 unnamed_device 25.5 MiB 0.30 983 10501 2625 7195 681 64.3 MiB 0.09 0.00 4.43796 -139.728 -4.43796 4.43796 0.85 0.00023457 0.000184715 0.0160309 0.012969 -1 -1 -1 -1 32 2330 19 6.64007e+06 276276 554710. 1919.41 0.95 0.0563085 0.0465816 22834 132086 -1 2080 19 1285 2105 131522 30636 3.86303 3.86303 -142.801 -3.86303 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.015414 0.0134999 145 124 0 0 124 31 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 4.05 vpr 64.25 MiB 0.02 7148 -1 -1 1 0.03 -1 -1 33796 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65792 32 32 355 304 1 150 80 17 17 289 -1 unnamed_device 25.3 MiB 0.23 851 9540 2516 6274 750 64.2 MiB 0.07 0.00 3.72946 -115.235 -3.72946 3.72946 0.85 0.000199491 0.000156194 0.0128658 0.0103524 -1 -1 -1 -1 32 1856 20 6.64007e+06 200928 554710. 1919.41 0.87 0.0476618 0.0394235 22834 132086 -1 1679 16 644 994 63164 14955 2.68397 2.68397 -105.845 -2.68397 0 0 701300. 2426.64 0.30 0.03 0.12 -1 -1 0.30 0.0125449 0.0111185 109 89 0 0 89 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 4.45 vpr 64.20 MiB 0.02 7168 -1 -1 1 0.04 -1 -1 34168 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65736 32 32 364 282 1 196 97 17 17 289 -1 unnamed_device 25.2 MiB 0.12 1023 18745 6322 9498 2925 64.2 MiB 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66024 32 32 405 318 1 200 104 17 17 289 -1 unnamed_device 25.6 MiB 0.18 988 17184 5218 8807 3159 64.5 MiB 0.13 0.00 3.62559 -123.648 -3.62559 3.62559 0.85 0.000262181 0.000212009 0.0196698 0.0158139 -1 -1 -1 -1 28 2903 40 6.64007e+06 502320 500653. 1732.36 1.21 0.0678937 0.0560273 21970 115934 -1 2226 21 1439 2284 161332 37219 2.89997 2.89997 -117.754 -2.89997 0 0 612192. 2118.31 0.27 0.06 0.11 -1 -1 0.27 0.0155528 0.0135179 157 65 63 32 64 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 4.29 vpr 63.91 MiB 0.02 7172 -1 -1 1 0.04 -1 -1 34184 -1 -1 18 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65420 31 32 308 262 1 147 80 17 17 289 -1 unnamed_device 25.1 MiB 0.19 869 9368 2508 6076 784 63.9 MiB 0.07 0.00 3.34153 -105.882 -3.34153 3.34153 0.86 0.000229262 0.00019097 0.0116431 0.00942741 -1 -1 -1 -1 32 1866 23 6.64007e+06 213486 554710. 1919.41 0.90 0.0443576 0.0368834 22834 132086 -1 1656 18 876 1510 96218 21620 2.68277 2.68277 -105.301 -2.68277 0 0 701300. 2426.64 0.29 0.04 0.12 -1 -1 0.29 0.01071 0.00932685 106 55 31 31 53 31 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 7.59 vpr 64.20 MiB 0.02 7084 -1 -1 1 0.04 -1 -1 34136 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 383 307 1 184 97 17 17 289 -1 unnamed_device 25.2 MiB 0.18 879 9865 2512 6573 780 64.2 MiB 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65816 29 32 367 293 1 183 95 17 17 289 -1 unnamed_device 25.3 MiB 0.16 1020 16079 4107 10319 1653 64.3 MiB 0.12 0.00 3.72052 -109.725 -3.72052 3.72052 0.87 0.00022959 0.000175625 0.0188595 0.0150887 -1 -1 -1 -1 32 2087 23 6.64007e+06 426972 554710. 1919.41 0.91 0.0585367 0.048494 22834 132086 -1 1904 18 1088 1735 96314 23271 2.84497 2.84497 -106.604 -2.84497 0 0 701300. 2426.64 0.32 0.04 0.12 -1 -1 0.32 0.0132667 0.0116569 135 62 56 29 58 29 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 4.33 vpr 64.45 MiB 0.02 7376 -1 -1 1 0.04 -1 -1 34168 -1 -1 39 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65992 32 32 469 381 1 200 103 17 17 289 -1 unnamed_device 25.5 MiB 0.26 937 9020 1835 6701 484 64.4 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65932 32 32 401 316 1 196 101 17 17 289 -1 unnamed_device 25.4 MiB 0.18 1060 9736 1961 7168 607 64.4 MiB 0.08 0.00 3.51212 -122.885 -3.51212 3.51212 0.88 0.000222726 0.000175722 0.0125685 0.0102996 -1 -1 -1 -1 26 2722 22 6.64007e+06 464646 477104. 1650.88 1.04 0.0605853 0.0511951 21682 110474 -1 2283 20 1346 1924 137623 31055 2.99937 2.99937 -123.86 -2.99937 0 0 585099. 2024.56 0.26 0.06 0.11 -1 -1 0.26 0.0190909 0.0169345 151 65 61 32 64 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 4.56 vpr 64.48 MiB 0.03 7320 -1 -1 1 0.04 -1 -1 34364 -1 -1 45 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66024 32 32 500 382 1 232 109 17 17 289 -1 unnamed_device 26.0 MiB 0.25 1244 16489 4012 10933 1544 64.5 MiB 0.14 0.00 4.96651 -168.366 -4.96651 4.96651 0.87 0.000288065 0.000229579 0.0224214 0.0182557 -1 -1 -1 -1 26 3331 25 6.64007e+06 565110 477104. 1650.88 1.07 0.0755519 0.0630738 21682 110474 -1 2710 22 2295 3724 240942 54867 4.68148 4.68148 -171.314 -4.68148 0 0 585099. 2024.56 0.26 0.08 0.10 -1 -1 0.26 0.0211128 0.018455 188 96 64 32 96 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 3.92 vpr 63.66 MiB 0.02 6848 -1 -1 1 0.03 -1 -1 33740 -1 -1 15 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65188 30 32 246 229 1 118 77 17 17 289 -1 unnamed_device 24.9 MiB 0.11 483 10509 2545 7262 702 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66028 32 32 432 346 1 193 86 17 17 289 -1 unnamed_device 25.7 MiB 0.20 1064 14828 5337 7470 2021 64.5 MiB 0.12 0.00 4.34676 -140.278 -4.34676 4.34676 0.88 0.000231141 0.000181034 0.0207891 0.0166439 -1 -1 -1 -1 32 2306 25 6.64007e+06 276276 554710. 1919.41 0.95 0.0644728 0.0530903 22834 132086 -1 1995 20 1368 2467 139291 32056 3.42803 3.42803 -133.215 -3.42803 0 0 701300. 2426.64 0.29 0.05 0.13 -1 -1 0.29 0.0162241 0.0141842 149 94 32 32 94 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 4.61 vpr 64.40 MiB 0.03 7172 -1 -1 1 0.05 -1 -1 34224 -1 -1 39 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65944 31 32 421 339 1 193 102 17 17 289 -1 unnamed_device 25.6 MiB 0.19 994 11288 2808 7770 710 64.4 MiB 0.09 0.00 3.54427 -117.284 -3.54427 3.54427 0.94 0.000230643 0.000181768 0.0139695 0.0112671 -1 -1 -1 -1 26 2483 22 6.64007e+06 489762 477104. 1650.88 1.12 0.0609049 0.0511219 21682 110474 -1 2174 19 1650 2620 154872 38837 3.11657 3.11657 -120.491 -3.11657 0 0 585099. 2024.56 0.26 0.06 0.10 -1 -1 0.26 0.0167739 0.0147592 148 94 29 29 93 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 4.45 vpr 64.03 MiB 0.02 7248 -1 -1 1 0.05 -1 -1 34496 -1 -1 34 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65568 32 32 438 350 1 194 98 17 17 289 -1 unnamed_device 25.4 MiB 0.15 984 7523 1506 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0.0142431 0.0124293 141 65 54 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 4.25 vpr 63.87 MiB 0.03 7224 -1 -1 1 0.03 -1 -1 33956 -1 -1 22 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65400 29 32 343 267 1 184 83 17 17 289 -1 unnamed_device 25.0 MiB 0.15 792 11963 2924 7039 2000 63.9 MiB 0.07 0.00 4.3057 -123.39 -4.3057 4.3057 0.86 0.000205469 0.00016254 0.0160257 0.0130239 -1 -1 -1 -1 32 2326 24 6.65987e+06 278916 554710. 1919.41 1.07 0.0542803 0.0450852 22834 132086 -1 1788 22 1543 2752 171817 43958 3.46431 3.46431 -122.506 -3.46431 0 0 701300. 2426.64 0.30 0.06 0.13 -1 -1 0.30 0.0155374 0.0135797 138 34 87 29 29 29 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 4.35 vpr 63.99 MiB 0.03 7124 -1 -1 1 0.04 -1 -1 34212 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65524 32 32 376 288 1 195 84 17 17 289 -1 unnamed_device 25.3 MiB 0.24 1026 15456 4961 8586 1909 64.0 MiB 0.12 0.00 4.14936 -143.085 -4.14936 4.14936 0.86 0.000222356 0.000176445 0.021947 0.0177341 -1 -1 -1 -1 32 2589 20 6.65987e+06 253560 554710. 1919.41 0.97 0.0609418 0.0506463 22834 132086 -1 2222 22 1680 3105 206991 47036 3.69143 3.69143 -143.37 -3.69143 0 0 701300. 2426.64 0.30 0.07 0.12 -1 -1 0.30 0.0172213 0.015149 151 34 96 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 4.49 vpr 64.23 MiB 0.02 7084 -1 -1 1 0.04 -1 -1 33844 -1 -1 37 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65768 32 32 402 316 1 199 101 17 17 289 -1 unnamed_device 25.4 MiB 0.23 1029 9501 1978 7135 388 64.2 MiB 0.09 0.00 3.43623 -117.882 -3.43623 3.43623 0.92 0.000233029 0.00018302 0.0120644 0.00985763 -1 -1 -1 -1 32 2342 20 6.65987e+06 469086 554710. 1919.41 0.95 0.0528538 0.0443739 22834 132086 -1 1962 18 1126 1792 107710 25832 2.72371 2.72371 -112.034 -2.72371 0 0 701300. 2426.64 0.30 0.04 0.12 -1 -1 0.30 0.0149223 0.013213 154 64 63 32 63 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 4.07 vpr 63.64 MiB 0.02 6904 -1 -1 1 0.03 -1 -1 33952 -1 -1 19 27 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65164 27 32 269 226 1 135 78 17 17 289 -1 unnamed_device 24.9 MiB 0.14 580 13026 4344 6329 2353 63.6 MiB 0.09 0.00 3.7565 -98.351 -3.7565 3.7565 0.97 0.00016047 0.000126685 0.0158445 0.0128417 -1 -1 -1 -1 30 1411 19 6.65987e+06 240882 526063. 1820.29 0.86 0.0445457 0.0369664 22546 126617 -1 1171 19 804 1373 82491 19526 2.70051 2.70051 -92.1985 -2.70051 0 0 666494. 2306.21 0.29 0.03 0.11 -1 -1 0.29 0.0110419 0.00972093 96 34 54 27 27 27 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 4.19 vpr 63.96 MiB 0.02 7032 -1 -1 1 0.03 -1 -1 34040 -1 -1 33 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65492 31 32 317 242 1 185 96 17 17 289 -1 unnamed_device 25.2 MiB 0.30 1016 11265 2888 7039 1338 64.0 MiB 0.09 0.00 3.36201 -108.145 -3.36201 3.36201 0.86 0.000196594 0.000156412 0.0129528 0.0105918 -1 -1 -1 -1 26 2532 27 6.65987e+06 418374 477104. 1650.88 1.00 0.0530519 0.0445537 21682 110474 -1 2233 18 1175 2022 139017 32170 2.74797 2.74797 -107.276 -2.74797 0 0 585099. 2024.56 0.26 0.05 0.10 -1 -1 0.26 0.0129167 0.0114214 139 4 115 31 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 4.06 vpr 64.00 MiB 0.02 7112 -1 -1 1 0.03 -1 -1 33884 -1 -1 16 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65540 31 32 338 292 1 147 79 17 17 289 -1 unnamed_device 25.3 MiB 0.28 818 11571 4275 5789 1507 64.0 MiB 0.08 0.00 3.08801 -101.656 -3.08801 3.08801 0.86 0.000194887 0.000152233 0.0157148 0.0125822 -1 -1 -1 -1 28 2012 20 6.65987e+06 202848 500653. 1732.36 0.89 0.0503903 0.0416852 21970 115934 -1 1768 19 888 1441 101867 23067 2.77365 2.77365 -102.085 -2.77365 0 0 612192. 2118.31 0.26 0.04 0.11 -1 -1 0.26 0.0132013 0.0115096 105 85 0 0 84 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 5.70 vpr 63.76 MiB 0.02 7048 -1 -1 1 0.04 -1 -1 33868 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65288 32 32 314 256 1 162 80 17 17 289 -1 unnamed_device 24.8 MiB 0.23 642 11432 4032 4649 2751 63.8 MiB 0.07 0.00 3.56921 -118.924 -3.56921 3.56921 0.89 0.000204221 0.000163325 0.0157006 0.0127499 -1 -1 -1 -1 36 2044 28 6.65987e+06 202848 612192. 2118.31 2.19 0.0902007 0.0764587 23410 145293 -1 1461 25 1464 2371 152631 38874 3.06097 3.06097 -111.701 -3.06097 0 0 782063. 2706.10 0.32 0.06 0.13 -1 -1 0.32 0.0154486 0.0133314 121 34 64 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 4.36 vpr 63.83 MiB 0.02 7032 -1 -1 1 0.04 -1 -1 33896 -1 -1 17 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65364 30 32 325 273 1 151 79 17 17 289 -1 unnamed_device 25.0 MiB 0.23 688 7684 1925 5205 554 63.8 MiB 0.07 0.00 3.53806 -112.993 -3.53806 3.53806 0.89 0.000199151 0.000157834 0.0114809 0.00944231 -1 -1 -1 -1 32 1563 20 6.65987e+06 215526 554710. 1919.41 0.91 0.048507 0.0408916 22834 132086 -1 1404 20 939 1333 81887 19635 2.76697 2.76697 -105.554 -2.76697 0 0 701300. 2426.64 0.31 0.04 0.12 -1 -1 0.31 0.0142186 0.0125318 110 63 30 30 60 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 4.12 vpr 64.06 MiB 0.02 7060 -1 -1 1 0.04 -1 -1 33892 -1 -1 29 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65600 32 32 331 280 1 156 93 17 17 289 -1 unnamed_device 25.3 MiB 0.27 841 11223 2602 8034 587 64.1 MiB 0.08 0.00 3.27957 -108.894 -3.27957 3.27957 0.88 0.000190398 0.000148882 0.0118571 0.00951992 -1 -1 -1 -1 30 2020 22 6.65987e+06 367662 526063. 1820.29 0.88 0.0460649 0.038006 22546 126617 -1 1668 22 1025 1665 104569 24167 2.50305 2.50305 -103.61 -2.50305 0 0 666494. 2306.21 0.28 0.04 0.12 -1 -1 0.28 0.0129487 0.0112801 114 65 25 25 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 4.38 vpr 64.01 MiB 0.02 7108 -1 -1 1 0.04 -1 -1 34084 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65544 32 32 386 305 1 188 96 17 17 289 -1 unnamed_device 25.3 MiB 0.40 1002 18711 5900 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1.03 0.0597878 0.0508458 22834 132086 -1 2106 22 1643 2700 178482 44548 3.66751 3.66751 -139.961 -3.66751 0 0 701300. 2426.64 0.29 0.07 0.12 -1 -1 0.29 0.0203484 0.0177778 156 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 4.27 vpr 63.52 MiB 0.02 6840 -1 -1 1 0.04 -1 -1 34020 -1 -1 18 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65048 29 32 272 228 1 145 79 17 17 289 -1 unnamed_device 24.8 MiB 0.25 686 7177 1709 4538 930 63.5 MiB 0.06 0.00 3.15358 -93.6229 -3.15358 3.15358 0.88 0.000173679 0.000137734 0.0100514 0.00828262 -1 -1 -1 -1 28 1892 19 6.65987e+06 228204 500653. 1732.36 0.87 0.0409682 0.0344969 21970 115934 -1 1647 23 1148 1915 132777 31641 2.65245 2.65245 -95.4509 -2.65245 0 0 612192. 2118.31 0.27 0.06 0.11 -1 -1 0.27 0.0157757 0.0138858 107 29 58 29 24 24 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 4.59 vpr 64.16 MiB 0.02 7272 -1 -1 1 0.04 -1 -1 33708 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65696 32 32 401 315 1 192 84 17 17 289 -1 unnamed_device 25.4 MiB 0.27 1074 13992 4161 7846 1985 64.2 MiB 0.12 0.00 3.5141 -125.301 -3.5141 3.5141 0.88 0.000272516 0.000214316 0.02221 0.0180216 -1 -1 -1 -1 32 2362 21 6.65987e+06 253560 554710. 1919.41 0.97 0.0647798 0.0539167 22834 132086 -1 2100 19 1387 2433 160863 37488 3.00917 3.00917 -120.058 -3.00917 0 0 701300. 2426.64 0.33 0.05 0.12 -1 -1 0.33 0.0164651 0.0145785 146 63 64 32 62 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 5.22 vpr 64.17 MiB 0.02 7252 -1 -1 1 0.04 -1 -1 34176 -1 -1 34 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65712 32 32 383 303 1 185 98 17 17 289 -1 unnamed_device 25.4 MiB 0.40 934 18323 6450 8556 3317 64.2 MiB 0.11 0.00 3.6343 -123.732 -3.6343 3.6343 0.86 0.000218734 0.000172517 0.0218129 0.0175926 -1 -1 -1 -1 30 2378 28 6.65987e+06 431052 526063. 1820.29 1.45 0.074348 0.0625194 22546 126617 -1 1916 19 1275 1888 125113 28979 2.76277 2.76277 -114.988 -2.76277 0 0 666494. 2306.21 0.28 0.05 0.12 -1 -1 0.28 0.0161028 0.0141349 142 57 64 32 56 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 4.54 vpr 64.10 MiB 0.02 7124 -1 -1 1 0.04 -1 -1 34144 -1 -1 30 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65636 32 32 339 284 1 162 94 17 17 289 -1 unnamed_device 25.3 MiB 0.32 832 15430 4777 8379 2274 64.1 MiB 0.13 0.00 2.83964 -101.659 -2.83964 2.83964 0.86 0.00028625 0.00022412 0.020992 0.0168723 -1 -1 -1 -1 30 1996 22 6.65987e+06 380340 526063. 1820.29 0.95 0.060009 0.0498959 22546 126617 -1 1635 14 802 1184 72625 16499 2.18971 2.18971 -96.9741 -2.18971 0 0 666494. 2306.21 0.29 0.04 0.12 -1 -1 0.29 0.0132388 0.0119215 118 65 29 29 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 3.75 vpr 63.32 MiB 0.02 6928 -1 -1 1 0.03 -1 -1 33756 -1 -1 15 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64836 30 32 226 208 1 119 77 17 17 289 -1 unnamed_device 24.8 MiB 0.10 661 10835 3152 6204 1479 63.3 MiB 0.06 0.00 2.60038 -85.2282 -2.60038 2.60038 0.86 0.000146349 0.000115364 0.0115561 0.00926061 -1 -1 -1 -1 28 1452 20 6.65987e+06 190170 500653. 1732.36 0.80 0.0360421 0.0297892 21970 115934 -1 1272 18 515 793 57249 13039 1.71265 1.71265 -76.7055 -1.71265 0 0 612192. 2118.31 0.25 0.03 0.11 -1 -1 0.25 0.00829805 0.00726069 85 34 24 24 30 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 4.39 vpr 63.92 MiB 0.02 7144 -1 -1 1 0.05 -1 -1 34172 -1 -1 16 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65452 31 32 335 280 1 154 79 17 17 289 -1 unnamed_device 25.2 MiB 0.14 862 13768 4646 7227 1895 63.9 MiB 0.09 0.00 3.94338 -122.441 -3.94338 3.94338 0.88 0.00021207 0.000168982 0.018332 0.0148478 -1 -1 -1 -1 32 1822 20 6.65987e+06 202848 554710. 1919.41 0.89 0.0533518 0.0444459 22834 132086 -1 1666 18 875 1353 101459 22409 2.91545 2.91545 -114.226 -2.91545 0 0 701300. 2426.64 0.31 0.04 0.12 -1 -1 0.31 0.0129711 0.0115155 113 64 31 31 62 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 4.50 vpr 64.01 MiB 0.02 7076 -1 -1 1 0.05 -1 -1 33524 -1 -1 34 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65548 32 32 366 283 1 192 98 17 17 289 -1 unnamed_device 25.0 MiB 0.23 1067 12248 3339 7850 1059 64.0 MiB 0.09 0.00 4.06436 -136.288 -4.06436 4.06436 0.88 0.000235554 0.000189371 0.014899 0.0122004 -1 -1 -1 -1 30 2353 19 6.65987e+06 431052 526063. 1820.29 0.92 0.0565076 0.0477459 22546 126617 -1 2038 20 1356 2011 119922 27360 3.22177 3.22177 -126.056 -3.22177 0 0 666494. 2306.21 0.29 0.05 0.11 -1 -1 0.29 0.0157327 0.0139328 145 34 91 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 4.35 vpr 64.25 MiB 0.02 7212 -1 -1 1 0.04 -1 -1 34632 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65796 32 32 460 375 1 196 100 17 17 289 -1 unnamed_device 25.8 MiB 0.33 1107 12164 3260 7320 1584 64.3 MiB 0.10 0.00 3.45103 -121.866 -3.45103 3.45103 0.86 0.00025615 0.000191433 0.0153242 0.0120164 -1 -1 -1 -1 32 2586 24 6.65987e+06 456408 554710. 1919.41 0.93 0.060485 0.0497648 22834 132086 -1 2228 18 1253 1902 113164 26704 3.01545 3.01545 -117.593 -3.01545 0 0 701300. 2426.64 0.29 0.06 0.12 -1 -1 0.29 0.0194744 0.0173037 149 124 0 0 125 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 3.83 vpr 62.89 MiB 0.02 6876 -1 -1 1 0.03 -1 -1 34076 -1 -1 17 26 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64404 26 32 198 186 1 109 75 17 17 289 -1 unnamed_device 24.4 MiB 0.19 410 10345 3142 6004 1199 62.9 MiB 0.04 0.00 2.61938 -68.655 -2.61938 2.61938 0.86 0.000125071 9.7591e-05 0.00937445 0.00750279 -1 -1 -1 -1 30 1071 20 6.65987e+06 215526 526063. 1820.29 0.80 0.0298943 0.0246568 22546 126617 -1 892 17 477 715 39145 10340 1.85405 1.85405 -64.8879 -1.85405 0 0 666494. 2306.21 0.28 0.02 0.11 -1 -1 0.28 0.00774252 0.00681641 77 30 26 26 22 22 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 6.50 vpr 63.80 MiB 0.02 7092 -1 -1 1 0.05 -1 -1 33904 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65332 32 32 333 251 1 187 84 17 17 289 -1 unnamed_device 24.9 MiB 0.23 1115 13443 3576 8165 1702 63.8 MiB 0.11 0.00 4.2335 -135.193 -4.2335 4.2335 1.02 0.00019936 0.000157616 0.0172239 0.0140116 -1 -1 -1 -1 28 2630 26 6.65987e+06 253560 500653. 1732.36 2.84 0.0959019 0.0796908 21970 115934 -1 2272 22 1473 2541 181143 40800 3.73177 3.73177 -136.785 -3.73177 0 0 612192. 2118.31 0.26 0.06 0.10 -1 -1 0.26 0.0151157 0.013274 137 3 122 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 3.78 vpr 63.01 MiB 0.02 6776 -1 -1 1 0.03 -1 -1 33852 -1 -1 13 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64524 32 32 199 182 1 122 77 17 17 289 -1 unnamed_device 24.3 MiB 0.10 594 7901 1809 5857 235 63.0 MiB 0.05 0.00 2.22607 -81.2607 -2.22607 2.22607 0.85 0.000135476 0.000106952 0.00801793 0.00648837 -1 -1 -1 -1 32 1389 15 6.65987e+06 164814 554710. 1919.41 0.84 0.0304616 0.0255145 22834 132086 -1 1233 16 549 735 54361 13016 1.93825 1.93825 -78.4309 -1.93825 0 0 701300. 2426.64 0.29 0.03 0.12 -1 -1 0.29 0.00807441 0.00716267 81 3 53 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 4.63 vpr 64.14 MiB 0.02 7120 -1 -1 1 0.04 -1 -1 34116 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65684 32 32 376 288 1 195 97 17 17 289 -1 unnamed_device 25.4 MiB 0.15 1065 18079 5979 9630 2470 64.1 MiB 0.15 0.00 4.06247 -139.199 -4.06247 4.06247 0.94 0.000237937 0.000191141 0.0228789 0.0186552 -1 -1 -1 -1 32 2367 20 6.65987e+06 418374 554710. 1919.41 1.00 0.0679986 0.0572457 22834 132086 -1 2074 22 1496 2206 146587 33354 3.39397 3.39397 -131.759 -3.39397 0 0 701300. 2426.64 0.28 0.05 0.12 -1 -1 0.28 0.0168664 0.0149314 152 34 96 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 4.16 vpr 64.14 MiB 0.02 6960 -1 -1 1 0.04 -1 -1 34208 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65680 32 32 337 253 1 196 99 17 17 289 -1 unnamed_device 25.2 MiB 0.22 1134 16059 4004 10217 1838 64.1 MiB 0.13 0.00 3.38184 -119.391 -3.38184 3.38184 0.87 0.000220735 0.000175379 0.0179557 0.0144782 -1 -1 -1 -1 30 2478 22 6.65987e+06 443730 526063. 1820.29 0.91 0.0553238 0.0460675 22546 126617 -1 2138 23 1418 2253 152856 33329 2.67931 2.67931 -115.639 -2.67931 0 0 666494. 2306.21 0.28 0.05 0.11 -1 -1 0.28 0.0152187 0.0132582 150 3 124 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 6.06 vpr 64.15 MiB 0.02 7076 -1 -1 1 0.04 -1 -1 33948 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65688 32 32 407 319 1 197 99 17 17 289 -1 unnamed_device 25.6 MiB 0.15 1118 17199 4898 10401 1900 64.1 MiB 0.13 0.00 3.91784 -137.067 -3.91784 3.91784 0.84 0.000233033 0.000185887 0.0198197 0.0158727 -1 -1 -1 -1 30 2570 27 6.65987e+06 443730 526063. 1820.29 2.93 0.106041 0.0868113 22546 126617 -1 2132 19 1575 2660 153360 35523 3.16231 3.16231 -129.907 -3.16231 0 0 666494. 2306.21 0.27 0.05 0.11 -1 -1 0.27 0.0148045 0.0130393 153 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 3.92 vpr 63.66 MiB 0.02 6928 -1 -1 1 0.03 -1 -1 33652 -1 -1 15 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65184 32 32 294 246 1 149 79 17 17 289 -1 unnamed_device 24.8 MiB 0.18 736 8191 2107 5347 737 63.7 MiB 0.06 0.00 2.8895 -100.047 -2.8895 2.8895 0.86 0.000176608 0.000139393 0.010168 0.00825419 -1 -1 -1 -1 28 2097 23 6.65987e+06 190170 500653. 1732.36 0.84 0.0417828 0.0348056 21970 115934 -1 1812 19 1072 1768 132294 30499 2.85491 2.85491 -104.569 -2.85491 0 0 612192. 2118.31 0.26 0.04 0.11 -1 -1 0.26 0.011401 0.0100046 106 34 54 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 4.02 vpr 63.67 MiB 0.02 7024 -1 -1 1 0.04 -1 -1 34040 -1 -1 19 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65200 30 32 296 244 1 154 81 17 17 289 -1 unnamed_device 24.8 MiB 0.15 832 12156 3666 7026 1464 63.7 MiB 0.08 0.00 3.4951 -115.55 -3.4951 3.4951 0.88 0.00017766 0.000139605 0.0145473 0.0117716 -1 -1 -1 -1 32 1812 18 6.65987e+06 240882 554710. 1919.41 0.90 0.0452634 0.0376541 22834 132086 -1 1637 24 948 1418 102648 23106 2.94997 2.94997 -112.088 -2.94997 0 0 701300. 2426.64 0.30 0.04 0.12 -1 -1 0.30 0.0132396 0.0115416 115 34 60 30 30 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 4.35 vpr 63.80 MiB 0.02 7136 -1 -1 1 0.04 -1 -1 33784 -1 -1 20 28 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65328 28 32 278 232 1 150 80 17 17 289 -1 unnamed_device 25.0 MiB 0.20 593 11776 2929 8189 658 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0.046107 22834 132086 -1 1631 20 1209 1890 125284 30035 2.73971 2.73971 -110.442 -2.73971 0 0 701300. 2426.64 0.30 0.05 0.13 -1 -1 0.30 0.0136135 0.0120325 125 3 96 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 4.43 vpr 63.84 MiB 0.02 7024 -1 -1 1 0.05 -1 -1 34132 -1 -1 31 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65372 31 32 303 249 1 162 94 17 17 289 -1 unnamed_device 24.9 MiB 0.19 735 8614 2125 5723 766 63.8 MiB 0.08 0.00 3.29178 -108.454 -3.29178 3.29178 0.92 0.000219705 0.000167933 0.0124794 0.0104425 -1 -1 -1 -1 28 2096 24 6.65987e+06 393018 500653. 1732.36 0.97 0.0553195 0.0471305 21970 115934 -1 1861 24 1396 2258 163291 38205 2.77565 2.77565 -108.842 -2.77565 0 0 612192. 2118.31 0.27 0.06 0.11 -1 -1 0.27 0.0154836 0.0134816 119 34 61 31 31 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 4.56 vpr 63.98 MiB 0.03 6952 -1 -1 1 0.04 -1 -1 33856 -1 -1 30 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65516 29 32 312 264 1 154 91 17 17 289 -1 unnamed_device 25.0 MiB 0.29 717 8047 1725 5786 536 64.0 MiB 0.07 0.00 2.76744 -86.2128 -2.76744 2.76744 0.92 0.000180985 0.000142457 0.0100526 0.00824251 -1 -1 -1 -1 32 1718 21 6.65987e+06 380340 554710. 1919.41 0.95 0.0456769 0.038576 22834 132086 -1 1480 18 839 1446 82236 20096 1.99625 1.99625 -81.928 -1.99625 0 0 701300. 2426.64 0.34 0.04 0.14 -1 -1 0.34 0.0138296 0.0121381 109 61 29 29 57 29 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 6.55 vpr 64.14 MiB 0.03 7068 -1 -1 1 0.04 -1 -1 34152 -1 -1 39 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65684 32 32 423 310 1 229 103 17 17 289 -1 unnamed_device 25.6 MiB 0.38 1246 13117 3185 8526 1406 64.1 MiB 0.13 0.00 4.16036 -141.523 -4.16036 4.16036 0.86 0.000239798 0.000190496 0.0160078 0.0130221 -1 -1 -1 -1 28 3650 28 6.65987e+06 494442 500653. 1732.36 3.08 0.110543 0.0915706 21970 115934 -1 2889 22 2073 3566 281141 62285 3.86363 3.86363 -148.555 -3.86363 0 0 612192. 2118.31 0.26 0.08 0.10 -1 -1 0.26 0.0186994 0.0163891 179 29 128 32 27 27 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 4.55 vpr 64.27 MiB 0.03 7160 -1 -1 1 0.04 -1 -1 34264 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65812 32 32 403 317 1 198 99 17 17 289 -1 unnamed_device 25.4 MiB 0.31 1041 9447 2232 6542 673 64.3 MiB 0.08 0.00 3.5061 -122.514 -3.5061 3.5061 0.88 0.000240141 0.000185736 0.0125694 0.010158 -1 -1 -1 -1 32 2288 19 6.65987e+06 443730 554710. 1919.41 0.94 0.0522072 0.0436475 22834 132086 -1 1994 21 1391 2140 124097 29585 2.77297 2.77297 -115.234 -2.77297 0 0 701300. 2426.64 0.30 0.05 0.13 -1 -1 0.30 0.0162666 0.0142913 152 65 62 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 4.67 vpr 64.23 MiB 0.02 7172 -1 -1 1 0.04 -1 -1 34524 -1 -1 28 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65768 31 32 353 302 1 156 91 17 17 289 -1 unnamed_device 25.5 MiB 0.35 709 5599 957 4403 239 64.2 MiB 0.05 0.00 3.18838 -103.883 -3.18838 3.18838 0.89 0.000193365 0.000152611 0.0074812 0.00619347 -1 -1 -1 -1 26 2105 38 6.65987e+06 354984 477104. 1650.88 1.09 0.0499822 0.0417201 21682 110474 -1 1745 19 1012 1678 105217 25769 2.55939 2.55939 -102.816 -2.55939 0 0 585099. 2024.56 0.25 0.05 0.12 -1 -1 0.25 0.0146118 0.0129378 113 90 0 0 89 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 4.76 vpr 64.30 MiB 0.02 7324 -1 -1 1 0.06 -1 -1 33916 -1 -1 21 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65848 31 32 391 309 1 194 84 17 17 289 -1 unnamed_device 25.5 MiB 0.29 950 14541 4604 7502 2435 64.3 MiB 0.12 0.00 3.4921 -115.341 -3.4921 3.4921 0.94 0.000218513 0.000172546 0.0215484 0.0175215 -1 -1 -1 -1 32 2284 19 6.65987e+06 266238 554710. 1919.41 0.99 0.0643863 0.0538435 22834 132086 -1 1926 24 1607 2769 175988 39847 2.89577 2.89577 -113.543 -2.89577 0 0 701300. 2426.64 0.33 0.08 0.13 -1 -1 0.33 0.0231932 0.0205581 148 64 60 30 62 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 4.25 vpr 64.27 MiB 0.02 7372 -1 -1 1 0.04 -1 -1 34192 -1 -1 21 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65808 31 32 455 371 1 193 84 17 17 289 -1 unnamed_device 25.3 MiB 0.37 1075 7953 1851 5455 647 64.3 MiB 0.07 0.00 4.84238 -140.996 -4.84238 4.84238 0.86 0.000237949 0.000187108 0.0129485 0.0105657 -1 -1 -1 -1 30 2514 21 6.65987e+06 266238 526063. 1820.29 0.90 0.0558263 0.0463713 22546 126617 -1 2032 18 1004 1712 93766 22265 3.60671 3.60671 -132.535 -3.60671 0 0 666494. 2306.21 0.27 0.04 0.12 -1 -1 0.27 0.0155553 0.0136789 149 124 0 0 124 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 4.58 vpr 64.20 MiB 0.03 7360 -1 -1 1 0.04 -1 -1 34176 -1 -1 21 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65736 31 32 413 333 1 188 84 17 17 289 -1 unnamed_device 25.4 MiB 0.26 947 10332 2670 7099 563 64.2 MiB 0.09 0.00 4.78027 -132.754 -4.78027 4.78027 0.93 0.00023816 0.000188952 0.0164624 0.0135123 -1 -1 -1 -1 32 2150 18 6.65987e+06 266238 554710. 1919.41 0.90 0.0567469 0.0476182 22834 132086 -1 1930 19 1139 1864 120278 28305 3.69497 3.69497 -130.77 -3.69497 0 0 701300. 2426.64 0.29 0.05 0.15 -1 -1 0.29 0.0150248 0.0132065 143 90 31 31 89 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 4.64 vpr 64.31 MiB 0.03 7156 -1 -1 1 0.06 -1 -1 34028 -1 -1 33 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65852 31 32 391 309 1 193 96 17 17 289 -1 unnamed_device 25.5 MiB 0.30 995 11265 2756 7734 775 64.3 MiB 0.10 0.00 3.36361 -112.108 -3.36361 3.36361 0.86 0.000223451 0.000176788 0.0138665 0.0111909 -1 -1 -1 -1 32 2231 21 6.65987e+06 418374 554710. 1919.41 0.93 0.0535533 0.0445229 22834 132086 -1 2051 22 1429 2522 161477 37406 2.80191 2.80191 -109.124 -2.80191 0 0 701300. 2426.64 0.31 0.06 0.13 -1 -1 0.31 0.0200867 0.0178564 146 64 60 31 62 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 4.30 vpr 64.45 MiB 0.03 7084 -1 -1 1 0.04 -1 -1 34348 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 407 319 1 198 99 17 17 289 -1 unnamed_device 25.5 MiB 0.22 1091 9903 2241 6952 710 64.5 MiB 0.09 0.00 3.91784 -134.792 -3.91784 3.91784 0.85 0.000230603 0.000182409 0.0130468 0.0105336 -1 -1 -1 -1 30 2537 27 6.65987e+06 443730 526063. 1820.29 1.06 0.0560136 0.0466339 22546 126617 -1 2201 22 1649 2612 165739 37609 3.29771 3.29771 -131.299 -3.29771 0 0 666494. 2306.21 0.29 0.06 0.11 -1 -1 0.29 0.0162299 0.0141879 154 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 5.61 vpr 64.40 MiB 0.03 7436 -1 -1 1 0.06 -1 -1 33856 -1 -1 40 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65944 32 32 496 380 1 232 104 17 17 289 -1 unnamed_device 26.0 MiB 0.31 1184 18648 4691 11584 2373 64.4 MiB 0.18 0.00 4.06547 -137.623 -4.06547 4.06547 0.94 0.000290764 0.000232192 0.024197 0.0195494 -1 -1 -1 -1 34 2821 22 6.65987e+06 507120 585099. 2024.56 1.67 0.102929 0.0869897 23122 138558 -1 2347 19 1676 2732 179173 42035 3.71977 3.71977 -136.162 -3.71977 0 0 742403. 2568.87 0.31 0.06 0.12 -1 -1 0.31 0.0194582 0.0171595 184 96 62 32 96 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 4.13 vpr 63.97 MiB 0.02 6900 -1 -1 1 0.04 -1 -1 34076 -1 -1 18 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65508 31 32 305 250 1 158 81 17 17 289 -1 unnamed_device 25.0 MiB 0.23 685 11806 2914 7153 1739 64.0 MiB 0.08 0.00 3.55518 -111.493 -3.55518 3.55518 0.87 0.000188 0.000148625 0.0149034 0.0120671 -1 -1 -1 -1 32 1837 21 6.65987e+06 228204 554710. 1919.41 0.93 0.0484108 0.0402551 22834 132086 -1 1559 21 1192 1993 124706 29921 3.10705 3.10705 -109.722 -3.10705 0 0 701300. 2426.64 0.29 0.04 0.12 -1 -1 0.29 0.0130355 0.0114709 116 34 62 31 31 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 4.90 vpr 63.46 MiB 0.02 7272 -1 -1 1 0.04 -1 -1 33820 -1 -1 36 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64980 31 32 395 311 1 196 99 17 17 289 -1 unnamed_device 24.6 MiB 0.21 975 9675 2183 7040 452 63.5 MiB 0.10 0.00 4.0281 -131.106 -4.0281 4.0281 0.97 0.000240279 0.000188018 0.0149648 0.0123429 -1 -1 -1 -1 26 2958 42 6.65987e+06 456408 477104. 1650.88 1.34 0.0756727 0.0642825 21682 110474 -1 2412 20 1578 2670 189219 43824 3.73577 3.73577 -138.183 -3.73577 0 0 585099. 2024.56 0.25 0.06 0.10 -1 -1 0.25 0.0161226 0.0142303 150 64 62 31 62 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 4.71 vpr 64.20 MiB 0.03 7168 -1 -1 1 0.04 -1 -1 34352 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65744 32 32 397 313 1 196 97 17 17 289 -1 unnamed_device 25.4 MiB 0.32 1040 11641 3109 7665 867 64.2 MiB 0.11 0.00 3.62624 -117.445 -3.62624 3.62624 0.97 0.000279853 0.000230454 0.0155215 0.0126195 -1 -1 -1 -1 28 2841 21 6.65987e+06 418374 500653. 1732.36 0.94 0.0555543 0.0462223 21970 115934 -1 2311 25 1614 2976 197433 45925 2.86271 2.86271 -111.815 -2.86271 0 0 612192. 2118.31 0.26 0.08 0.10 -1 -1 0.26 0.022325 0.0196621 148 63 62 32 62 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 4.72 vpr 64.01 MiB 0.02 7056 -1 -1 1 0.03 -1 -1 33972 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65544 32 32 345 257 1 194 84 17 17 289 -1 unnamed_device 25.1 MiB 0.22 853 8685 1897 5601 1187 64.0 MiB 0.07 0.00 4.14936 -138.467 -4.14936 4.14936 0.85 0.000217517 0.000172692 0.0128369 0.0104785 -1 -1 -1 -1 32 2947 27 6.65987e+06 253560 554710. 1919.41 1.52 0.06375 0.0530946 22834 132086 -1 2183 20 1697 3130 202299 50463 4.17937 4.17937 -151.011 -4.17937 0 0 701300. 2426.64 0.29 0.06 0.12 -1 -1 0.29 0.0155497 0.013763 150 3 128 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 4.27 vpr 64.19 MiB 0.03 7320 -1 -1 1 0.03 -1 -1 35408 -1 -1 34 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65728 32 32 424 343 1 190 98 17 17 289 -1 unnamed_device 25.3 MiB 0.37 1097 11798 3144 7589 1065 64.2 MiB 0.11 0.00 3.29555 -116.715 -3.29555 3.29555 0.84 0.000239341 0.000187499 0.0156126 0.0125119 -1 -1 -1 -1 32 2347 22 6.65987e+06 431052 554710. 1919.41 0.90 0.0552587 0.0456105 22834 132086 -1 2185 19 1263 1818 115545 27756 2.61645 2.61645 -112.838 -2.61645 0 0 701300. 2426.64 0.30 0.05 0.12 -1 -1 0.30 0.0154936 0.0136053 145 96 25 25 96 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 4.28 vpr 64.00 MiB 0.02 7080 -1 -1 1 0.04 -1 -1 33932 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65536 32 32 395 311 1 194 99 17 17 289 -1 unnamed_device 25.2 MiB 0.34 1042 7623 1446 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0.0169885 0.0150001 150 34 96 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 4.69 vpr 63.94 MiB 0.02 7156 -1 -1 1 0.04 -1 -1 34404 -1 -1 37 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65476 32 32 407 319 1 197 101 17 17 289 -1 unnamed_device 25.4 MiB 0.27 1025 18901 5265 11118 2518 63.9 MiB 0.15 0.00 3.95704 -138.682 -3.95704 3.95704 0.91 0.000237819 0.000186986 0.0238361 0.0191897 -1 -1 -1 -1 32 2290 23 6.65987e+06 469086 554710. 1919.41 1.03 0.0687873 0.0572488 22834 132086 -1 2103 23 1697 2639 176451 40256 3.38671 3.38671 -133.347 -3.38671 0 0 701300. 2426.64 0.31 0.06 0.13 -1 -1 0.31 0.0183719 0.016118 153 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 4.80 vpr 64.04 MiB 0.03 7268 -1 -1 1 0.05 -1 -1 34192 -1 -1 34 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65572 31 32 449 367 1 193 97 17 17 289 -1 unnamed_device 25.4 MiB 0.38 1075 12529 3319 7633 1577 64.0 MiB 0.12 0.00 3.98298 -125.763 -3.98298 3.98298 0.94 0.000263789 0.000205086 0.0207667 0.0169871 -1 -1 -1 -1 28 2875 24 6.65987e+06 431052 500653. 1732.36 1.03 0.0680779 0.0567205 21970 115934 -1 2454 21 1535 2576 174851 40840 3.55825 3.55825 -129.218 -3.55825 0 0 612192. 2118.31 0.26 0.06 0.11 -1 -1 0.26 0.0179787 0.0156959 145 122 0 0 122 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 4.34 vpr 64.15 MiB 0.02 7280 -1 -1 1 0.04 -1 -1 34168 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65688 32 32 432 346 1 195 84 17 17 289 -1 unnamed_device 25.2 MiB 0.28 1088 15822 4733 9518 1571 64.1 MiB 0.12 0.00 4.01118 -127.976 -4.01118 4.01118 0.86 0.000230879 0.000181222 0.0223147 0.0178722 -1 -1 -1 -1 32 2447 24 6.65987e+06 253560 554710. 1919.41 0.96 0.0664386 0.0547738 22834 132086 -1 2163 22 1707 3104 193742 43407 3.17765 3.17765 -121.359 -3.17765 0 0 701300. 2426.64 0.31 0.06 0.11 -1 -1 0.31 0.0172721 0.0150439 149 94 32 32 94 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 4.50 vpr 63.73 MiB 0.02 6868 -1 -1 1 0.04 -1 -1 33984 -1 -1 30 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65264 32 32 312 255 1 166 94 17 17 289 -1 unnamed_device 24.8 MiB 0.20 771 8827 2156 6189 482 63.7 MiB 0.07 0.00 3.35364 -111.63 -3.35364 3.35364 0.93 0.000208378 0.000162646 0.0107347 0.00884616 -1 -1 -1 -1 28 2265 24 6.65987e+06 380340 500653. 1732.36 0.99 0.0512892 0.0436202 21970 115934 -1 1988 24 1408 2241 175119 41581 2.87885 2.87885 -113.156 -2.87885 0 0 612192. 2118.31 0.26 0.08 0.11 -1 -1 0.26 0.0198981 0.017597 124 34 63 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 4.33 vpr 63.97 MiB 0.02 7000 -1 -1 1 0.04 -1 -1 34116 -1 -1 18 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65508 32 32 370 314 1 164 82 17 17 289 -1 unnamed_device 25.2 MiB 0.32 775 7914 1954 5542 418 64.0 MiB 0.06 0.00 3.38184 -115.147 -3.38184 3.38184 0.86 0.000203243 0.000160444 0.0110477 0.008959 -1 -1 -1 -1 32 1876 23 6.65987e+06 228204 554710. 1919.41 0.90 0.0472121 0.0390771 22834 132086 -1 1751 22 1235 1983 135410 30234 2.53731 2.53731 -107.925 -2.53731 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.0157865 0.0138575 121 94 0 0 94 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 4.29 vpr 64.33 MiB 0.03 7156 -1 -1 1 0.04 -1 -1 34196 -1 -1 40 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65876 32 32 469 351 1 233 104 17 17 289 -1 unnamed_device 25.7 MiB 0.18 1358 14500 3674 9480 1346 64.3 MiB 0.14 0.00 4.6627 -160.408 -4.6627 4.6627 0.85 0.00029908 0.000212861 0.0201361 0.0162125 -1 -1 -1 -1 32 2828 20 6.65987e+06 507120 554710. 1919.41 0.98 0.0658264 0.0547301 22834 132086 -1 2592 20 2112 3449 200165 48304 4.13857 4.13857 -159.759 -4.13857 0 0 701300. 2426.64 0.30 0.06 0.11 -1 -1 0.30 0.0183217 0.0161196 187 65 96 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 4.72 vpr 64.27 MiB 0.03 7072 -1 -1 1 0.05 -1 -1 34176 -1 -1 31 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65812 32 32 368 284 1 194 95 17 17 289 -1 unnamed_device 25.5 MiB 0.31 954 14567 4735 7432 2400 64.3 MiB 0.12 0.00 3.51422 -121.562 -3.51422 3.51422 0.92 0.000224144 0.000176961 0.0190945 0.0155758 -1 -1 -1 -1 32 2355 23 6.65987e+06 393018 554710. 1919.41 1.02 0.0643413 0.0540318 22834 132086 -1 1996 20 1380 2125 138010 32355 2.94216 2.94216 -118.256 -2.94216 0 0 701300. 2426.64 0.30 0.05 0.13 -1 -1 0.30 0.0163025 0.0144465 146 34 92 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 4.08 vpr 64.00 MiB 0.02 6924 -1 -1 1 0.04 -1 -1 33800 -1 -1 30 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65536 30 32 296 244 1 158 92 17 17 289 -1 unnamed_device 24.9 MiB 0.19 839 17066 5534 9253 2279 64.0 MiB 0.11 0.00 3.49012 -114.14 -3.49012 3.49012 0.85 0.000180881 0.000144 0.0168054 0.0134939 -1 -1 -1 -1 32 1786 21 6.65987e+06 380340 554710. 1919.41 0.90 0.0479918 0.0398136 22834 132086 -1 1612 21 982 1572 108138 24890 2.66737 2.66737 -105.642 -2.66737 0 0 701300. 2426.64 0.29 0.04 0.12 -1 -1 0.29 0.0120459 0.010547 115 34 60 30 30 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 4.97 vpr 64.62 MiB 0.03 7472 -1 -1 1 0.05 -1 -1 34480 -1 -1 43 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66168 32 32 531 413 1 232 107 17 17 289 -1 unnamed_device 26.1 MiB 0.57 1333 18829 5161 11634 2034 64.6 MiB 0.17 0.00 4.64147 -157.361 -4.64147 4.64147 0.89 0.000289058 0.000225857 0.0250218 0.0197806 -1 -1 -1 -1 30 2844 21 6.65987e+06 545154 526063. 1820.29 0.97 0.0777588 0.0644079 22546 126617 -1 2398 23 2018 3072 157660 37757 4.17037 4.17037 -158 -4.17037 0 0 666494. 2306.21 0.28 0.06 0.12 -1 -1 0.28 0.0214825 0.0188006 186 127 32 32 128 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 4.48 vpr 63.95 MiB 0.02 7200 -1 -1 1 0.04 -1 -1 33812 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65480 32 32 376 288 1 194 100 17 17 289 -1 unnamed_device 25.5 MiB 0.21 1044 16340 4500 10034 1806 63.9 MiB 0.12 0.00 4.15932 -143.209 -4.15932 4.15932 0.94 0.000227382 0.000181584 0.0180974 0.0146392 -1 -1 -1 -1 28 2434 23 6.65987e+06 456408 500653. 1732.36 0.94 0.0595807 0.0496523 21970 115934 -1 2212 21 1724 2576 175138 40284 3.49823 3.49823 -139.756 -3.49823 0 0 612192. 2118.31 0.26 0.06 0.10 -1 -1 0.26 0.0186107 0.016527 151 34 96 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 4.01 vpr 64.04 MiB 0.02 6912 -1 -1 1 0.04 -1 -1 34056 -1 -1 31 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65580 32 32 283 225 1 164 95 17 17 289 -1 unnamed_device 25.0 MiB 0.14 722 13055 3473 8103 1479 64.0 MiB 0.10 0.00 3.50687 -117.927 -3.50687 3.50687 0.87 0.000204996 0.000163902 0.0137235 0.0110272 -1 -1 -1 -1 28 2310 22 6.65987e+06 393018 500653. 1732.36 0.92 0.0475175 0.0395702 21970 115934 -1 1874 19 1249 1926 119722 30066 2.97077 2.97077 -121.563 -2.97077 0 0 612192. 2118.31 0.26 0.05 0.10 -1 -1 0.26 0.0124692 0.0109595 123 3 96 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 4.84 vpr 64.14 MiB 0.03 7332 -1 -1 1 0.05 -1 -1 34392 -1 -1 41 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65680 32 32 438 320 1 235 105 17 17 289 -1 unnamed_device 25.5 MiB 0.26 1337 12702 3419 8223 1060 64.1 MiB 0.13 0.00 4.90437 -166.477 -4.90437 4.90437 0.93 0.000364548 0.000302208 0.0187206 0.0154481 -1 -1 -1 -1 30 3005 22 6.65987e+06 519798 526063. 1820.29 1.05 0.0671451 0.0565234 22546 126617 -1 2536 23 1897 3418 212452 47742 4.54303 4.54303 -164.492 -4.54303 0 0 666494. 2306.21 0.30 0.07 0.13 -1 -1 0.30 0.0194344 0.0170516 188 34 128 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 4.48 vpr 63.82 MiB 0.02 6744 -1 -1 1 0.04 -1 -1 33868 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65348 32 32 283 225 1 162 80 17 17 289 -1 unnamed_device 24.9 MiB 0.18 852 11260 3935 5447 1878 63.8 MiB 0.08 0.00 3.4749 -119.679 -3.4749 3.4749 0.95 0.000204384 0.000166857 0.0140302 0.0114205 -1 -1 -1 -1 32 2054 21 6.65987e+06 202848 554710. 1919.41 0.95 0.0482203 0.0405875 22834 132086 -1 1732 24 1316 2108 152415 36089 2.72571 2.72571 -112.904 -2.72571 0 0 701300. 2426.64 0.30 0.06 0.12 -1 -1 0.30 0.0157272 0.0139518 121 3 96 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 3.96 vpr 63.70 MiB 0.02 6972 -1 -1 1 0.04 -1 -1 33556 -1 -1 31 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65224 30 32 296 244 1 157 93 17 17 289 -1 unnamed_device 24.8 MiB 0.18 707 8073 1842 5622 609 63.7 MiB 0.07 0.00 3.47387 -110.471 -3.47387 3.47387 0.87 0.000185366 0.000147346 0.00897922 0.0073044 -1 -1 -1 -1 28 2018 21 6.65987e+06 393018 500653. 1732.36 0.87 0.0398835 0.0332487 21970 115934 -1 1690 19 1134 1899 121372 29545 2.89017 2.89017 -109.84 -2.89017 0 0 612192. 2118.31 0.26 0.05 0.10 -1 -1 0.26 0.0126448 0.0111171 113 34 60 30 30 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 4.38 vpr 64.29 MiB 0.03 7304 -1 -1 1 0.04 -1 -1 34060 -1 -1 33 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65828 29 32 393 319 1 182 94 17 17 289 -1 unnamed_device 25.2 MiB 0.36 964 15856 4549 8713 2594 64.3 MiB 0.11 0.00 3.50895 -109.722 -3.50895 3.50895 0.86 0.000215153 0.000170439 0.0186278 0.0149426 -1 -1 -1 -1 30 1987 21 6.65987e+06 418374 526063. 1820.29 0.86 0.0565959 0.0467885 22546 126617 -1 1675 18 1050 1751 89648 21297 2.54417 2.54417 -99.3535 -2.54417 0 0 666494. 2306.21 0.31 0.05 0.12 -1 -1 0.31 0.0162979 0.0143824 133 88 29 29 85 29 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 4.65 vpr 64.19 MiB 0.02 7076 -1 -1 1 0.05 -1 -1 34224 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65732 32 32 407 319 1 194 84 17 17 289 -1 unnamed_device 25.4 MiB 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0.29 0.014387 0.0125029 120 65 32 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 4.31 vpr 63.97 MiB 0.02 7032 -1 -1 1 0.04 -1 -1 34188 -1 -1 17 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65504 31 32 353 302 1 152 80 17 17 289 -1 unnamed_device 25.3 MiB 0.32 800 12464 4445 5613 2406 64.0 MiB 0.09 0.00 3.46898 -107.215 -3.46898 3.46898 0.89 0.00019997 0.000156691 0.0170875 0.013651 -1 -1 -1 -1 32 1807 19 6.65987e+06 215526 554710. 1919.41 0.91 0.0510589 0.0422033 22834 132086 -1 1612 21 941 1768 104618 25029 2.51805 2.51805 -100.388 -2.51805 0 0 701300. 2426.64 0.31 0.04 0.12 -1 -1 0.31 0.0133321 0.0116015 109 90 0 0 89 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 4.50 vpr 64.06 MiB 0.02 7200 -1 -1 1 0.04 -1 -1 33940 -1 -1 33 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65600 30 32 374 297 1 186 95 17 17 289 -1 unnamed_device 25.0 MiB 0.30 998 10463 2754 7099 610 64.1 MiB 0.09 0.00 3.41496 -111.837 -3.41496 3.41496 0.94 0.000213302 0.000170101 0.0129597 0.0105604 -1 -1 -1 -1 26 2353 22 6.65987e+06 418374 477104. 1650.88 0.96 0.0546171 0.045868 21682 110474 -1 2029 17 1123 1957 131265 30894 2.71545 2.71545 -108.984 -2.71545 0 0 585099. 2024.56 0.26 0.05 0.11 -1 -1 0.26 0.0141206 0.0125491 137 60 60 30 57 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 4.45 vpr 63.79 MiB 0.02 7108 -1 -1 1 0.04 -1 -1 34084 -1 -1 31 28 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65316 28 32 332 260 1 180 91 17 17 289 -1 unnamed_device 24.9 MiB 0.21 995 16207 5283 8775 2149 63.8 MiB 0.13 0.00 4.24344 -123.397 -4.24344 4.24344 0.94 0.000193242 0.000152952 0.0192057 0.015567 -1 -1 -1 -1 28 2452 19 6.65987e+06 393018 500653. 1732.36 0.95 0.0561114 0.0469721 21970 115934 -1 2053 21 1498 2513 164181 38572 3.61111 3.61111 -125.602 -3.61111 0 0 612192. 2118.31 0.27 0.05 0.12 -1 -1 0.27 0.0142277 0.0125585 133 34 84 28 28 28 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 4.05 vpr 63.76 MiB 0.02 6984 -1 -1 1 0.04 -1 -1 33920 -1 -1 18 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65288 30 32 325 273 1 157 80 17 17 289 -1 unnamed_device 25.1 MiB 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0.014366 0.01275 150 4 124 31 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 4.93 vpr 64.34 MiB 0.03 7188 -1 -1 1 0.04 -1 -1 34348 -1 -1 34 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65880 32 32 407 319 1 197 98 17 17 289 -1 unnamed_device 25.4 MiB 0.31 1037 13598 4125 8601 872 64.3 MiB 0.12 0.00 4.1263 -141.609 -4.1263 4.1263 0.92 0.000250062 0.000198811 0.0176691 0.0142417 -1 -1 -1 -1 26 2960 37 6.65987e+06 431052 477104. 1650.88 1.25 0.0779238 0.0658367 21682 110474 -1 2249 22 1692 3000 199861 46709 3.59517 3.59517 -140.665 -3.59517 0 0 585099. 2024.56 0.25 0.06 0.11 -1 -1 0.25 0.0178305 0.0156392 153 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 4.68 vpr 64.21 MiB 0.03 7304 -1 -1 1 0.04 -1 -1 33872 -1 -1 34 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65752 32 32 407 319 1 194 98 17 17 289 -1 unnamed_device 25.3 MiB 0.23 1033 10448 2380 7653 415 64.2 MiB 0.10 0.00 4.16458 -142.258 -4.16458 4.16458 0.88 0.000227579 0.000180213 0.0136564 0.0109757 -1 -1 -1 -1 28 2950 23 6.65987e+06 431052 500653. 1732.36 1.23 0.0616907 0.0516743 21970 115934 -1 2366 14 1336 2203 163664 38169 3.67477 3.67477 -147.386 -3.67477 0 0 612192. 2118.31 0.28 0.05 0.11 -1 -1 0.28 0.0135227 0.0121468 151 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 4.29 vpr 63.89 MiB 0.02 7244 -1 -1 1 0.04 -1 -1 33988 -1 -1 37 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65420 32 32 399 315 1 196 101 17 17 289 -1 unnamed_device 25.3 MiB 0.35 982 9031 1878 6401 752 63.9 MiB 0.08 0.00 3.86706 -126.941 -3.86706 3.86706 0.85 0.000223285 0.00017658 0.0110086 0.00892723 -1 -1 -1 -1 30 2516 24 6.65987e+06 469086 526063. 1820.29 0.97 0.0527037 0.0439763 22546 126617 -1 2125 20 1264 2174 119793 28949 3.29571 3.29571 -124.191 -3.29571 0 0 666494. 2306.21 0.27 0.05 0.12 -1 -1 0.27 0.0151636 0.0133061 148 65 60 30 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 4.55 vpr 63.67 MiB 0.02 7004 -1 -1 1 0.04 -1 -1 34100 -1 -1 18 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65196 30 32 296 244 1 156 80 17 17 289 -1 unnamed_device 24.8 MiB 0.31 698 7992 1870 5622 500 63.7 MiB 0.06 0.00 3.50927 -110.859 -3.50927 3.50927 0.90 0.000184222 0.00014674 0.010644 0.00873391 -1 -1 -1 -1 32 1861 17 6.65987e+06 228204 554710. 1919.41 0.97 0.0430998 0.0363375 22834 132086 -1 1458 20 905 1434 81381 21081 2.75597 2.75597 -105.004 -2.75597 0 0 701300. 2426.64 0.31 0.04 0.14 -1 -1 0.31 0.0144868 0.0128538 112 34 60 30 30 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 4.17 vpr 64.49 MiB 0.02 7112 -1 -1 1 0.04 -1 -1 34032 -1 -1 22 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66040 30 32 383 303 1 191 84 17 17 289 -1 unnamed_device 25.4 MiB 0.28 985 11796 3468 7405 923 64.5 MiB 0.11 0.00 4.19776 -134.529 -4.19776 4.19776 0.85 0.000230315 0.000182359 0.0172369 0.0139425 -1 -1 -1 -1 32 2009 21 6.65987e+06 278916 554710. 1919.41 0.90 0.0557442 0.0462361 22834 132086 -1 1752 20 1321 1969 105280 25542 3.56043 3.56043 -130.097 -3.56043 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.015448 0.0136244 145 63 60 30 60 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 4.63 vpr 64.05 MiB 0.02 7372 -1 -1 1 0.04 -1 -1 34400 -1 -1 39 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65592 32 32 469 381 1 198 103 17 17 289 -1 unnamed_device 25.6 MiB 0.24 1052 13117 2855 8842 1420 64.1 MiB 0.10 0.00 3.91498 -132.986 -3.91498 3.91498 0.94 0.000259669 0.00020629 0.0167786 0.013628 -1 -1 -1 -1 32 2453 22 6.65987e+06 494442 554710. 1919.41 0.98 0.0608658 0.0505698 22834 132086 -1 2157 22 1790 2994 187896 45084 3.62605 3.62605 -137.441 -3.62605 0 0 701300. 2426.64 0.30 0.06 0.13 -1 -1 0.30 0.0179191 0.0155926 154 127 0 0 128 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 4.72 vpr 63.97 MiB 0.02 7220 -1 -1 1 0.04 -1 -1 34316 -1 -1 31 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65504 31 32 425 341 1 189 94 17 17 289 -1 unnamed_device 25.4 MiB 0.16 1050 9679 2438 6769 472 64.0 MiB 0.09 0.00 3.91106 -131.382 -3.91106 3.91106 0.88 0.000427902 0.000363857 0.0153748 0.0126998 -1 -1 -1 -1 26 2853 26 6.65987e+06 393018 477104. 1650.88 1.25 0.0637988 0.0536406 21682 110474 -1 2216 22 1545 2682 190227 44085 3.91691 3.91691 -140.392 -3.91691 0 0 585099. 2024.56 0.26 0.06 0.10 -1 -1 0.26 0.0169902 0.0148516 146 94 31 31 93 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 4.57 vpr 64.14 MiB 0.03 7352 -1 -1 1 0.06 -1 -1 34172 -1 -1 30 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65680 30 32 404 328 1 182 92 17 17 289 -1 unnamed_device 25.4 MiB 0.29 992 11063 2679 7283 1101 64.1 MiB 0.09 0.00 3.74723 -113.498 -3.74723 3.74723 0.91 0.00021966 0.000173512 0.0141335 0.0114634 -1 -1 -1 -1 28 2320 21 6.65987e+06 380340 500653. 1732.36 0.88 0.0559482 0.0468534 21970 115934 -1 1911 18 1016 1843 106397 26846 3.08637 3.08637 -110.967 -3.08637 0 0 612192. 2118.31 0.26 0.05 0.11 -1 -1 0.26 0.0158639 0.0140921 136 92 26 26 90 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 4.90 vpr 64.11 MiB 0.02 7132 -1 -1 1 0.05 -1 -1 34024 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65644 32 32 407 319 1 198 85 17 17 289 -1 unnamed_device 25.3 MiB 0.39 1074 13477 4127 7567 1783 64.1 MiB 0.12 0.00 4.06547 -141.302 -4.06547 4.06547 1.00 0.000228597 0.000180904 0.0201545 0.0164508 -1 -1 -1 -1 32 2517 20 6.65987e+06 266238 554710. 1919.41 0.96 0.0598829 0.0497928 22834 132086 -1 2263 21 1834 3159 192050 44920 3.36097 3.36097 -134.209 -3.36097 0 0 701300. 2426.64 0.34 0.07 0.12 -1 -1 0.34 0.0181254 0.0160363 154 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 4.14 vpr 64.09 MiB 0.02 7372 -1 -1 1 0.03 -1 -1 34084 -1 -1 34 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65628 29 32 387 316 1 179 95 17 17 289 -1 unnamed_device 25.1 MiB 0.25 874 10895 2930 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0.0432357 0.0361987 22834 132086 -1 1754 22 1114 1735 125414 29154 2.86777 2.86777 -118.356 -2.86777 0 0 701300. 2426.64 0.29 0.05 0.11 -1 -1 0.29 0.0135667 0.0119384 117 3 96 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 5.04 vpr 63.94 MiB 0.03 7012 -1 -1 1 0.04 -1 -1 33880 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65472 32 32 407 319 1 194 97 17 17 289 -1 unnamed_device 25.5 MiB 0.41 1015 16525 5345 8784 2396 63.9 MiB 0.13 0.00 4.18856 -142.192 -4.18856 4.18856 1.03 0.000234025 0.000184401 0.021043 0.0171308 -1 -1 -1 -1 32 2391 18 6.65987e+06 418374 554710. 1919.41 0.97 0.061095 0.0511326 22834 132086 -1 1935 22 1491 2315 154663 35170 3.56843 3.56843 -134.747 -3.56843 0 0 701300. 2426.64 0.32 0.06 0.14 -1 -1 0.32 0.0188209 0.0165247 150 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 4.26 vpr 64.34 MiB 0.02 7044 -1 -1 1 0.03 -1 -1 34012 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65880 32 32 407 319 1 201 85 17 17 289 -1 unnamed_device 25.4 MiB 0.30 1026 16081 4881 8736 2464 64.3 MiB 0.12 0.00 4.23393 -146.239 -4.23393 4.23393 0.85 0.000227134 0.000178885 0.0222291 0.0178092 -1 -1 -1 -1 32 2423 20 6.65987e+06 266238 554710. 1919.41 0.94 0.0621139 0.0513255 22834 132086 -1 2088 20 1618 2397 158021 36521 3.54323 3.54323 -139.034 -3.54323 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.0166336 0.0146456 157 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 4.81 vpr 63.68 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 34116 -1 -1 29 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65204 32 32 315 267 1 158 93 17 17 289 -1 unnamed_device 24.8 MiB 0.25 688 16683 5557 7719 3407 63.7 MiB 0.10 0.00 3.44878 -105.048 -3.44878 3.44878 0.96 0.000192075 0.000150792 0.0183431 0.0147613 -1 -1 -1 -1 32 2061 28 6.65987e+06 367662 554710. 1919.41 1.10 0.0603129 0.0504057 22834 132086 -1 1604 22 1074 1599 128090 35387 2.74465 2.74465 -99.8729 -2.74465 0 0 701300. 2426.64 0.31 0.05 0.12 -1 -1 0.31 0.0149201 0.013139 111 55 32 32 54 27 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 4.32 vpr 63.91 MiB 0.02 6932 -1 -1 1 0.04 -1 -1 33900 -1 -1 18 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65448 31 32 275 220 1 160 81 17 17 289 -1 unnamed_device 25.1 MiB 0.21 720 9356 2387 5915 1054 63.9 MiB 0.08 0.00 3.4529 -113.153 -3.4529 3.4529 0.88 0.000182473 0.000145676 0.0118602 0.00971275 -1 -1 -1 -1 30 1921 19 6.65987e+06 228204 526063. 1820.29 0.92 0.0444613 0.037458 22546 126617 -1 1653 19 1135 1847 109681 25398 2.89017 2.89017 -110.427 -2.89017 0 0 666494. 2306.21 0.28 0.04 0.12 -1 -1 0.28 0.0128444 0.011367 118 4 93 31 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 6.30 vpr 64.00 MiB 0.02 7244 -1 -1 1 0.04 -1 -1 33892 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65536 32 32 381 303 1 188 96 17 17 289 -1 unnamed_device 25.0 MiB 0.38 913 5790 1032 4561 197 64.0 MiB 0.05 0.00 3.91316 -128.563 -3.91316 3.91316 0.85 0.000214525 0.000169549 0.00777021 0.0064358 -1 -1 -1 -1 26 2646 37 6.65987e+06 405696 477104. 1650.88 3.03 0.0950528 0.0790268 21682 110474 -1 2100 23 1573 2374 154692 36908 3.58831 3.58831 -133.102 -3.58831 0 0 585099. 2024.56 0.25 0.06 0.10 -1 -1 0.25 0.0169989 0.0146948 138 59 60 32 58 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 4.88 vpr 64.11 MiB 0.03 7320 -1 -1 1 0.04 -1 -1 33752 -1 -1 30 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65652 32 32 406 330 1 190 94 17 17 289 -1 unnamed_device 25.3 MiB 0.15 879 9892 2434 7009 449 64.1 MiB 0.10 0.00 4.11224 -123.302 -4.11224 4.11224 0.86 0.000321479 0.000268756 0.0144725 0.0118283 -1 -1 -1 -1 28 2708 31 6.65987e+06 380340 500653. 1732.36 1.43 0.0751404 0.0641647 21970 115934 -1 2190 24 1517 2512 179886 43994 3.75965 3.75965 -131.439 -3.75965 0 0 612192. 2118.31 0.26 0.06 0.11 -1 -1 0.26 0.0187983 0.0164705 134 88 28 28 88 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 4.56 vpr 64.03 MiB 0.03 7284 -1 -1 1 0.05 -1 -1 34032 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65564 32 32 399 285 1 228 99 17 17 289 -1 unnamed_device 25.6 MiB 0.22 1247 19251 5678 10972 2601 64.0 MiB 0.17 0.00 4.78976 -159.687 -4.78976 4.78976 0.86 0.000238781 0.000190561 0.0250133 0.0203764 -1 -1 -1 -1 32 2872 20 6.65987e+06 443730 554710. 1919.41 1.02 0.0727967 0.0613132 22834 132086 -1 2519 21 1954 3285 237082 51906 4.04943 4.04943 -149.419 -4.04943 0 0 701300. 2426.64 0.30 0.07 0.12 -1 -1 0.30 0.0175497 0.0155177 177 3 156 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 4.25 vpr 64.29 MiB 0.02 7276 -1 -1 1 0.04 -1 -1 33868 -1 -1 32 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65832 30 32 371 295 1 184 94 17 17 289 -1 unnamed_device 25.3 MiB 0.31 1003 9892 2469 6555 868 64.3 MiB 0.08 0.00 3.59821 -110.073 -3.59821 3.59821 0.85 0.00020839 0.000164853 0.0118818 0.00956624 -1 -1 -1 -1 32 2189 22 6.65987e+06 405696 554710. 1919.41 0.94 0.0497122 0.0414156 22834 132086 -1 1957 22 1356 2177 131501 31199 2.77671 2.77671 -109.109 -2.77671 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.0151062 0.0131895 136 59 60 30 56 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 4.36 vpr 63.53 MiB 0.02 6920 -1 -1 1 0.04 -1 -1 34212 -1 -1 20 27 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65056 27 32 269 226 1 143 79 17 17 289 -1 unnamed_device 24.8 MiB 0.12 768 12754 4322 6521 1911 63.5 MiB 0.08 0.00 3.3979 -99.6122 -3.3979 3.3979 0.96 0.00016626 0.000130912 0.0160227 0.013089 -1 -1 -1 -1 32 1486 19 6.65987e+06 253560 554710. 1919.41 0.97 0.0486231 0.0407528 22834 132086 -1 1328 19 850 1272 81588 19169 2.56737 2.56737 -92.6845 -2.56737 0 0 701300. 2426.64 0.31 0.04 0.13 -1 -1 0.31 0.0120134 0.0106387 107 34 54 27 27 27 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 4.41 vpr 64.48 MiB 0.03 7300 -1 -1 1 0.04 -1 -1 34204 -1 -1 40 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66028 32 32 493 378 1 232 104 17 17 289 -1 unnamed_device 26.0 MiB 0.28 1366 15232 4128 9656 1448 64.5 MiB 0.14 0.00 4.15924 -136.806 -4.15924 4.15924 0.85 0.000277765 0.000220544 0.0207731 0.0166701 -1 -1 -1 -1 32 3092 23 6.65987e+06 507120 554710. 1919.41 0.99 0.06996 0.0578366 22834 132086 -1 2778 24 2083 3703 243892 56131 3.46791 3.46791 -136.36 -3.46791 0 0 701300. 2426.64 0.31 0.07 0.12 -1 -1 0.31 0.0200441 0.0173711 184 95 62 31 95 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 4.17 vpr 64.46 MiB 0.02 7448 -1 -1 1 0.04 -1 -1 34200 -1 -1 21 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66012 31 32 455 371 1 189 84 17 17 289 -1 unnamed_device 25.5 MiB 0.24 989 7038 1632 4931 475 64.5 MiB 0.07 0.00 4.3087 -132.62 -4.3087 4.3087 0.84 0.000235578 0.000185919 0.0114304 0.00927209 -1 -1 -1 -1 32 2348 23 6.65987e+06 266238 554710. 1919.41 0.91 0.0526485 0.0432866 22834 132086 -1 2136 20 1285 2053 142990 32843 3.57811 3.57811 -134.798 -3.57811 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.0161723 0.0141581 145 124 0 0 124 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 4.48 vpr 63.89 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33896 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65424 32 32 355 304 1 151 80 17 17 289 -1 unnamed_device 24.9 MiB 0.22 741 9196 2428 5976 792 63.9 MiB 0.07 0.00 3.81463 -109.262 -3.81463 3.81463 0.95 0.000220879 0.000177835 0.0138884 0.0114192 -1 -1 -1 -1 32 1801 19 6.65987e+06 202848 554710. 1919.41 0.96 0.0532942 0.0449636 22834 132086 -1 1593 16 667 1046 64001 15581 2.76971 2.76971 -104.892 -2.76971 0 0 701300. 2426.64 0.31 0.04 0.13 -1 -1 0.31 0.0149849 0.013423 109 89 0 0 89 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 4.43 vpr 64.00 MiB 0.02 6912 -1 -1 1 0.04 -1 -1 34040 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65540 32 32 364 282 1 196 96 17 17 289 -1 unnamed_device 25.0 MiB 0.13 1123 15645 4083 9696 1866 64.0 MiB 0.12 0.00 4.2837 -136.384 -4.2837 4.2837 0.96 0.000211771 0.000167069 0.0188431 0.0153039 -1 -1 -1 -1 26 2734 22 6.65987e+06 405696 477104. 1650.88 1.01 0.0583938 0.0487463 21682 110474 -1 2304 21 1435 2192 157562 36356 3.90497 3.90497 -138.663 -3.90497 0 0 585099. 2024.56 0.25 0.05 0.10 -1 -1 0.25 0.0161463 0.0142706 146 34 90 30 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 4.86 vpr 64.05 MiB 0.03 7372 -1 -1 1 0.04 -1 -1 34460 -1 -1 36 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65584 31 32 443 336 1 220 99 17 17 289 -1 unnamed_device 25.6 MiB 0.34 1167 13551 3218 9177 1156 64.0 MiB 0.13 0.00 4.22766 -133.836 -4.22766 4.22766 0.90 0.000263693 0.000210924 0.0194889 0.0159014 -1 -1 -1 -1 32 2393 23 6.65987e+06 456408 554710. 1919.41 1.00 0.0709292 0.0599018 22834 132086 -1 2240 21 1644 2505 148012 35341 3.52031 3.52031 -130.484 -3.52031 0 0 701300. 2426.64 0.34 0.06 0.13 -1 -1 0.34 0.019955 0.0176184 171 64 87 31 62 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 6.08 vpr 64.07 MiB 0.02 7212 -1 -1 1 0.04 -1 -1 34212 -1 -1 33 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65604 30 32 373 297 1 186 95 17 17 289 -1 unnamed_device 25.0 MiB 0.30 1070 11111 2802 7426 883 64.1 MiB 0.09 0.00 3.62941 -110.797 -3.62941 3.62941 0.89 0.000216898 0.000171859 0.0133401 0.0108081 -1 -1 -1 -1 22 3059 42 6.65987e+06 418374 420624. 1455.45 2.81 0.0855172 0.0706322 20818 92861 -1 2541 19 1204 2230 204381 44907 3.36171 3.36171 -117.007 -3.36171 0 0 500653. 1732.36 0.23 0.06 0.08 -1 -1 0.23 0.0143945 0.0126119 134 61 58 30 58 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 4.28 vpr 64.42 MiB 0.02 7276 -1 -1 1 0.04 -1 -1 34076 -1 -1 42 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65964 32 32 407 319 1 201 106 17 17 289 -1 unnamed_device 25.3 MiB 0.26 1074 12606 3053 8336 1217 64.4 MiB 0.11 0.00 4.0783 -140.694 -4.0783 4.0783 0.85 0.000234095 0.000184681 0.0145852 0.0117767 -1 -1 -1 -1 30 2478 23 6.65987e+06 532476 526063. 1820.29 0.98 0.0550997 0.0457093 22546 126617 -1 2051 21 1402 2299 137271 31767 3.45817 3.45817 -133.145 -3.45817 0 0 666494. 2306.21 0.28 0.05 0.11 -1 -1 0.28 0.0156737 0.0136999 157 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 4.59 vpr 63.81 MiB 0.02 7204 -1 -1 1 0.04 -1 -1 34304 -1 -1 38 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65340 32 32 405 318 1 200 102 17 17 289 -1 unnamed_device 25.3 MiB 0.31 984 6766 1232 5172 362 63.8 MiB 0.07 0.00 3.41884 -115.761 -3.41884 3.41884 0.93 0.000247148 0.000195377 0.00970804 0.00800792 -1 -1 -1 -1 26 2790 23 6.65987e+06 481764 477104. 1650.88 0.94 0.0585829 0.0496962 21682 110474 -1 2277 22 1589 2490 166815 39888 2.87011 2.87011 -115.85 -2.87011 0 0 585099. 2024.56 0.26 0.07 0.10 -1 -1 0.26 0.0227187 0.0202367 155 65 63 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 3.90 vpr 63.59 MiB 0.02 7036 -1 -1 1 0.04 -1 -1 33988 -1 -1 16 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65112 29 32 287 238 1 135 77 17 17 289 -1 unnamed_device 24.8 MiB 0.09 508 12791 3386 7672 1733 63.6 MiB 0.06 0.00 3.7595 -104.085 -3.7595 3.7595 0.84 0.000167729 0.000131427 0.0150113 0.0120138 -1 -1 -1 -1 32 1446 20 6.65987e+06 202848 554710. 1919.41 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111 82 0 0 82 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 5.81 vpr 64.08 MiB 0.03 7044 -1 -1 1 0.04 -1 -1 34024 -1 -1 37 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65620 31 32 365 281 1 196 100 17 17 289 -1 unnamed_device 25.1 MiB 0.24 964 13556 3768 8523 1265 64.1 MiB 0.12 0.00 4.3897 -133.197 -4.3897 4.3897 0.86 0.000230146 0.000184894 0.0159005 0.0130657 -1 -1 -1 -1 28 2998 50 6.65987e+06 469086 500653. 1732.36 2.10 0.0712368 0.05962 21970 115934 -1 2210 24 2070 3451 281681 63736 3.91377 3.91377 -140.951 -3.91377 0 0 612192. 2118.31 0.27 0.10 0.11 -1 -1 0.27 0.024783 0.0221684 150 34 93 31 31 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 4.60 vpr 63.76 MiB 0.02 7180 -1 -1 1 0.06 -1 -1 33988 -1 -1 31 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65292 29 32 297 254 1 150 92 17 17 289 -1 unnamed_device 24.9 MiB 0.27 621 11063 2736 7707 620 63.8 MiB 0.08 0.00 3.58224 -95.8028 -3.58224 3.58224 0.91 0.000171037 0.000133562 0.0112281 0.00901717 -1 -1 -1 -1 26 1813 22 6.65987e+06 393018 477104. 1650.88 1.02 0.0490225 0.0412671 21682 110474 -1 1602 17 840 1268 82834 21231 2.78565 2.78565 -100.012 -2.78565 0 0 585099. 2024.56 0.26 0.04 0.10 -1 -1 0.26 0.0114202 0.0101537 108 56 29 29 52 26 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 4.77 vpr 63.80 MiB 0.02 7028 -1 -1 1 0.05 -1 -1 33896 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65328 32 32 314 256 1 160 80 17 17 289 -1 unnamed_device 24.9 MiB 0.23 823 7992 1920 5681 391 63.8 MiB 0.08 0.00 3.5141 -118.56 -3.5141 3.5141 0.95 0.000212288 0.000163298 0.0115542 0.00939533 -1 -1 -1 -1 32 1965 19 6.65987e+06 202848 554710. 1919.41 1.03 0.045829 0.0384227 22834 132086 -1 1725 18 1124 1875 121897 29067 2.82857 2.82857 -115.262 -2.82857 0 0 701300. 2426.64 0.32 0.05 0.12 -1 -1 0.32 0.0133285 0.0118801 119 34 64 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 4.35 vpr 64.30 MiB 0.03 7328 -1 -1 1 0.04 -1 -1 34104 -1 -1 36 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65848 31 32 387 307 1 189 99 17 17 289 -1 unnamed_device 25.5 MiB 0.28 997 12411 3191 8197 1023 64.3 MiB 0.09 0.00 3.50507 -117.588 -3.50507 3.50507 0.91 0.000225858 0.000175333 0.0148189 0.0118768 -1 -1 -1 -1 26 2261 19 6.65987e+06 456408 477104. 1650.88 0.88 0.0564569 0.0473976 21682 110474 -1 1929 20 1442 2138 126025 29548 2.78571 2.78571 -115.079 -2.78571 0 0 585099. 2024.56 0.25 0.06 0.10 -1 -1 0.25 0.0180723 0.0160056 142 64 58 31 62 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 4.08 vpr 63.61 MiB 0.02 6968 -1 -1 1 0.04 -1 -1 33824 -1 -1 16 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65140 31 32 308 262 1 147 79 17 17 289 -1 unnamed_device 24.7 MiB 0.32 889 12754 3806 7303 1645 63.6 MiB 0.08 0.00 3.11304 -101.246 -3.11304 3.11304 0.84 0.000195861 0.000155969 0.0154357 0.0123096 -1 -1 -1 -1 32 1732 19 6.65987e+06 202848 554710. 1919.41 0.88 0.0452196 0.037293 22834 132086 -1 1557 13 635 1065 56669 14489 2.67545 2.67545 -99.9304 -2.67545 0 0 701300. 2426.64 0.29 0.03 0.11 -1 -1 0.29 0.00953536 0.00851094 105 55 31 31 53 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 5.65 vpr 64.28 MiB 0.02 7132 -1 -1 1 0.04 -1 -1 34016 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 383 307 1 184 96 17 17 289 -1 unnamed_device 25.3 MiB 0.37 929 17616 5738 7949 3929 64.3 MiB 0.11 0.00 3.3979 -111.1 -3.3979 3.3979 0.87 0.000223965 0.000176453 0.0208594 0.0168011 -1 -1 -1 -1 32 2317 41 6.65987e+06 405696 554710. 1919.41 2.03 0.0852565 0.0710206 22834 132086 -1 1896 18 1239 2139 175466 43245 2.75477 2.75477 -106.462 -2.75477 0 0 701300. 2426.64 0.30 0.06 0.13 -1 -1 0.30 0.0168361 0.0150402 136 65 52 26 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 4.62 vpr 63.93 MiB 0.02 7308 -1 -1 1 0.03 -1 -1 34104 -1 -1 36 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65460 31 32 422 339 1 195 99 17 17 289 -1 unnamed_device 25.4 MiB 0.80 966 17427 4771 10069 2587 63.9 MiB 0.13 0.00 3.7525 -119.295 -3.7525 3.7525 0.85 0.000247417 0.00019615 0.0214676 0.0171495 -1 -1 -1 -1 28 2373 19 6.65987e+06 456408 500653. 1732.36 0.85 0.0599269 0.0493077 21970 115934 -1 2028 19 1642 2395 148618 35956 3.00737 3.00737 -117.232 -3.00737 0 0 612192. 2118.31 0.26 0.05 0.10 -1 -1 0.26 0.016465 0.0142604 148 93 31 31 92 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 4.63 vpr 63.84 MiB 0.02 6912 -1 -1 1 0.04 -1 -1 33908 -1 -1 18 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65376 32 32 333 279 1 160 82 17 17 289 -1 unnamed_device 25.0 MiB 0.29 861 11652 3522 6006 2124 63.8 MiB 0.08 0.00 2.81844 -100.349 -2.81844 2.81844 0.97 0.000198971 0.00015632 0.0156976 0.0127349 -1 -1 -1 -1 32 1853 21 6.65987e+06 228204 554710. 1919.41 1.01 0.0534988 0.0447903 22834 132086 -1 1607 17 1010 1569 98798 22749 2.60745 2.60745 -102.851 -2.60745 0 0 701300. 2426.64 0.30 0.04 0.12 -1 -1 0.30 0.0131704 0.011693 115 61 32 32 60 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 4.22 vpr 63.85 MiB 0.02 7132 -1 -1 1 0.03 -1 -1 33804 -1 -1 18 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65380 32 32 339 283 1 164 82 17 17 289 -1 unnamed_device 25.1 MiB 0.32 667 7380 1595 4913 872 63.8 MiB 0.05 0.00 3.38184 -112.707 -3.38184 3.38184 0.84 0.000206345 0.000165141 0.00994296 0.00808268 -1 -1 -1 -1 32 2059 26 6.65987e+06 228204 554710. 1919.41 1.01 0.0465543 0.038809 22834 132086 -1 1562 19 1091 1685 116660 29140 2.76171 2.76171 -110.403 -2.76171 0 0 701300. 2426.64 0.29 0.04 0.12 -1 -1 0.29 0.0124826 0.0109317 121 63 32 32 62 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 4.45 vpr 63.78 MiB 0.02 7264 -1 -1 1 0.04 -1 -1 34304 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65308 32 32 407 319 1 198 100 17 17 289 -1 unnamed_device 25.2 MiB 0.26 1042 12164 2979 8000 1185 63.8 MiB 0.10 0.00 4.02524 -139.262 -4.02524 4.02524 0.89 0.000224224 0.000177437 0.0143822 0.011598 -1 -1 -1 -1 28 2574 23 6.65987e+06 456408 500653. 1732.36 0.93 0.0544088 0.0451301 21970 115934 -1 2245 21 1795 2760 183069 42394 3.45191 3.45191 -135.897 -3.45191 0 0 612192. 2118.31 0.26 0.06 0.12 -1 -1 0.26 0.017424 0.0153585 154 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 4.23 vpr 64.05 MiB 0.02 7212 -1 -1 1 0.04 -1 -1 34152 -1 -1 32 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65592 29 32 367 293 1 183 93 17 17 289 -1 unnamed_device 25.1 MiB 0.28 974 17313 5216 9261 2836 64.1 MiB 0.13 0.00 3.57304 -105.909 -3.57304 3.57304 0.87 0.000215211 0.000171489 0.0209218 0.0168287 -1 -1 -1 -1 32 2030 20 6.65987e+06 405696 554710. 1919.41 0.87 0.0572275 0.0471326 22834 132086 -1 1783 15 787 1212 72557 17895 2.73571 2.73571 -101.927 -2.73571 0 0 701300. 2426.64 0.29 0.03 0.11 -1 -1 0.29 0.0132598 0.0118308 133 62 56 29 58 29 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 4.26 vpr 64.08 MiB 0.02 7196 -1 -1 1 0.04 -1 -1 34044 -1 -1 37 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65616 32 32 469 381 1 200 101 17 17 289 -1 unnamed_device 25.6 MiB 0.35 1004 11616 2968 7911 737 64.1 MiB 0.10 0.00 3.97241 -135.454 -3.97241 3.97241 0.86 0.000245837 0.000193262 0.0149478 0.0118908 -1 -1 -1 -1 32 2350 23 6.65987e+06 469086 554710. 1919.41 0.91 0.0575117 0.0473782 22834 132086 -1 2119 18 1433 2346 143697 34733 3.52231 3.52231 -134.27 -3.52231 0 0 701300. 2426.64 0.29 0.05 0.11 -1 -1 0.29 0.0155355 0.0136356 156 127 0 0 128 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 5.70 vpr 63.50 MiB 0.02 6808 -1 -1 1 0.03 -1 -1 33768 -1 -1 16 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65024 31 32 259 212 1 146 79 17 17 289 -1 unnamed_device 24.7 MiB 0.18 635 8698 2288 5521 889 63.5 MiB 0.07 0.00 2.9397 -95.8867 -2.9397 2.9397 0.87 0.000194796 0.000158562 0.0113121 0.00927696 -1 -1 -1 -1 32 1618 16 6.65987e+06 202848 554710. 1919.41 2.45 0.0849356 0.070936 22834 132086 -1 1428 19 892 1396 78771 21607 2.61571 2.61571 -97.4937 -2.61571 0 0 701300. 2426.64 0.30 0.04 0.12 -1 -1 0.30 0.0115836 0.0102602 105 4 85 31 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 4.50 vpr 64.24 MiB 0.02 7304 -1 -1 1 0.04 -1 -1 34068 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65784 32 32 418 338 1 190 97 17 17 289 -1 unnamed_device 25.4 MiB 0.22 948 20077 6167 11074 2836 64.2 MiB 0.15 0.00 4.10497 -133.778 -4.10497 4.10497 0.88 0.000237769 0.000187399 0.0253409 0.0202843 -1 -1 -1 -1 32 2138 21 6.65987e+06 418374 554710. 1919.41 0.96 0.0680995 0.0564173 22834 132086 -1 1855 19 1230 1767 113991 26733 3.46417 3.46417 -126.503 -3.46417 0 0 701300. 2426.64 0.29 0.06 0.13 -1 -1 0.29 0.0195772 0.0172145 142 92 28 28 92 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 4.96 vpr 63.83 MiB 0.02 7196 -1 -1 1 0.04 -1 -1 33884 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65364 32 32 376 318 1 156 80 17 17 289 -1 unnamed_device 25.0 MiB 0.24 805 9196 3450 4876 870 63.8 MiB 0.07 0.00 3.54047 -120.422 -3.54047 3.54047 0.91 0.000223891 0.00017629 0.0154269 0.0126552 -1 -1 -1 -1 30 2166 35 6.65987e+06 202848 526063. 1820.29 1.44 0.0876728 0.0760202 22546 126617 -1 1721 17 1153 1677 119370 27737 2.75177 2.75177 -114.486 -2.75177 0 0 666494. 2306.21 0.29 0.06 0.12 -1 -1 0.29 0.0177851 0.0159531 115 96 0 0 96 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 4.54 vpr 63.97 MiB 0.02 7188 -1 -1 1 0.05 -1 -1 33996 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65508 32 32 401 316 1 196 99 17 17 289 -1 unnamed_device 25.4 MiB 0.27 1002 18111 5520 9663 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 333 251 1 180 76 17 17 289 -1 unnamed_device 25.9 MiB 1.20 755 9836 4062 5477 297 64.6 MiB 0.06 0.00 4.01986 -136.639 -4.01986 4.01986 0.88 0.000197592 0.000156166 0.0149909 0.012293 -1 -1 -1 -1 42 2992 24 6.95648e+06 173708 744469. 2576.02 2.09 0.0694728 0.0583928 27202 183097 -1 2087 23 1911 2887 275152 61216 4.09781 4.09781 -148.697 -4.09781 0 0 949917. 3286.91 0.36 0.07 0.16 -1 -1 0.36 0.0154741 0.0135685 74 3 122 32 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml mult_025.v common 4.94 vpr 63.73 MiB 0.02 6652 -1 -1 1 0.04 -1 -1 34112 -1 -1 8 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65256 32 32 199 182 1 119 72 17 17 289 -1 unnamed_device 25.2 MiB 0.30 731 9906 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66316 31 32 455 371 1 185 77 17 17 289 -1 unnamed_device 26.1 MiB 2.35 778 10998 4559 6059 380 64.8 MiB 0.08 0.00 4.63397 -149.774 -4.63397 4.63397 0.90 0.00024371 0.000190966 0.0198411 0.0159577 -1 -1 -1 -1 42 3197 35 6.95648e+06 202660 744469. 2576.02 2.23 0.0831513 0.0680942 27202 183097 -1 2238 23 1687 2592 248478 54871 4.77941 4.77941 -161.64 -4.77941 0 0 949917. 3286.91 0.39 0.07 0.16 -1 -1 0.39 0.018557 0.0161691 78 124 0 0 124 31 -fixed_k6_frac_2ripple_N8_22nm.xml mult_040.v common 8.04 vpr 65.06 MiB 0.03 7216 -1 -1 1 0.04 -1 -1 34216 -1 -1 13 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66624 31 32 413 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66076 31 32 305 250 1 152 74 17 17 289 -1 unnamed_device 25.7 MiB 0.67 589 10304 4334 5652 318 64.5 MiB 0.06 0.00 3.38836 -119.14 -3.38836 3.38836 0.97 0.000184644 0.000145692 0.0143092 0.0116647 -1 -1 -1 -1 36 2300 43 6.95648e+06 159232 648988. 2245.63 2.69 0.0850846 0.0712621 26050 158493 -1 1707 19 1387 1919 175590 41198 3.54282 3.54282 -128.096 -3.54282 0 0 828058. 2865.25 0.31 0.05 0.14 -1 -1 0.31 0.0123226 0.0108318 62 34 62 31 31 31 -fixed_k6_frac_2ripple_N8_22nm.xml mult_045.v common 6.67 vpr 64.86 MiB 0.02 7144 -1 -1 1 0.04 -1 -1 34096 -1 -1 27 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66412 31 32 395 311 1 188 90 17 17 289 -1 unnamed_device 25.9 MiB 0.73 807 13959 3748 8318 1893 64.9 MiB 0.09 0.00 3.90275 -135.486 -3.90275 3.90275 0.98 0.000231152 0.000182294 0.0194515 0.0158095 -1 -1 -1 -1 42 2665 23 6.95648e+06 390843 744469. 2576.02 2.40 0.0885421 0.0735368 27202 183097 -1 2191 20 1849 2845 264362 56154 4.00046 4.00046 -148.359 -4.00046 0 0 949917. 3286.91 0.35 0.07 0.16 -1 -1 0.35 0.0172906 0.0153058 86 64 62 31 62 31 -fixed_k6_frac_2ripple_N8_22nm.xml mult_046.v common 9.86 vpr 64.84 MiB 0.02 7284 -1 -1 1 0.05 -1 -1 34128 -1 -1 26 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66396 32 32 397 313 1 188 90 17 17 289 -1 unnamed_device 25.9 MiB 0.91 803 11145 4511 6144 490 64.8 MiB 0.08 0.00 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 67160 32 32 531 413 1 225 95 17 17 289 -1 unnamed_device 26.7 MiB 1.98 1126 15215 3732 10105 1378 65.6 MiB 0.11 0.00 4.49524 -160.999 -4.49524 4.49524 0.91 0.000277122 0.000218207 0.0227717 0.0183203 -1 -1 -1 -1 50 2881 24 6.95648e+06 448746 902133. 3121.57 16.05 0.189725 0.155869 28642 213929 -1 2578 31 3160 4685 568753 162228 4.90641 4.90641 -174.584 -4.90641 0 0 1.08113e+06 3740.92 0.40 0.14 0.20 -1 -1 0.40 0.0246224 0.021161 103 127 32 32 128 32 -fixed_k6_frac_2ripple_N8_22nm.xml mult_061.v common 7.26 vpr 64.74 MiB 0.02 7212 -1 -1 1 0.04 -1 -1 33988 -1 -1 28 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66192 30 32 296 244 1 151 83 17 17 289 -1 unnamed_device 25.8 MiB 0.86 581 11423 4387 5607 1429 64.6 MiB 0.06 0.00 3.09676 -109.06 -3.09676 3.09676 0.94 0.00017616 0.000139195 0.0134055 0.0109111 -1 -1 -1 -1 38 2169 24 6.95648e+06 303989 678818. 2348.85 2.72 0.0680768 0.0566394 26626 170182 -1 1705 19 1262 1896 159278 35800 3.29047 3.29047 -118.286 -3.29047 0 0 902133. 3121.57 0.32 0.05 0.14 -1 -1 0.32 0.0117107 0.0103167 65 34 60 30 30 30 -fixed_k6_frac_2ripple_N8_22nm.xml mult_066.v common 7.79 vpr 64.72 MiB 0.03 7360 -1 -1 1 0.05 -1 -1 33964 -1 -1 20 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66420 32 32 366 283 1 215 87 17 17 289 -1 unnamed_device 25.9 MiB 0.61 873 12759 5251 7214 294 64.9 MiB 0.09 0.00 4.03513 -142.757 -4.03513 4.03513 0.92 0.00022868 0.000182409 0.019295 0.0157573 -1 -1 -1 -1 42 3024 42 6.99608e+06 338461 744469. 2576.02 13.02 0.167627 0.140752 27202 183097 -1 2381 21 2303 3171 353724 88771 4.2429 4.2429 -160.748 -4.2429 0 0 949917. 3286.91 0.35 0.09 0.15 -1 -1 0.35 0.0164715 0.0145842 97 34 91 32 32 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_022.v common 7.26 vpr 64.95 MiB 0.02 7336 -1 -1 1 0.04 -1 -1 34640 -1 -1 22 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66512 32 32 460 375 1 303 86 17 17 289 -1 unnamed_device 26.4 MiB 1.61 1281 15206 5059 7438 2709 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66184 32 32 376 288 1 218 81 17 17 289 -1 unnamed_device 25.8 MiB 1.32 835 12856 4936 6167 1753 64.6 MiB 0.08 0.00 3.83288 -138.607 -3.83288 3.83288 0.89 0.00021599 0.00016998 0.0192495 0.0156266 -1 -1 -1 -1 54 2823 49 6.99608e+06 250167 949917. 3286.91 5.84 0.127506 0.105907 29506 232905 -1 1943 24 2035 2954 239818 56718 4.18862 4.18862 -149.145 -4.18862 0 0 1.17392e+06 4061.99 0.41 0.07 0.21 -1 -1 0.41 0.0161238 0.0141157 95 34 96 32 32 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_027.v common 7.76 vpr 64.61 MiB 0.02 7036 -1 -1 1 0.04 -1 -1 33968 -1 -1 28 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66164 32 32 337 253 1 188 92 17 17 289 -1 unnamed_device 25.6 MiB 0.31 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66620 32 32 403 317 1 252 82 17 17 289 -1 unnamed_device 26.2 MiB 0.98 1127 14500 5161 6829 2510 65.1 MiB 0.11 0.00 3.90969 -144.443 -3.90969 3.90969 0.97 0.00022537 0.000178072 0.0238396 0.0193545 -1 -1 -1 -1 46 3349 32 6.99608e+06 264882 828058. 2865.25 5.45 0.144589 0.119953 28066 200906 -1 2712 21 2653 3652 420598 86614 4.50691 4.50691 -161.912 -4.50691 0 0 1.01997e+06 3529.29 0.40 0.11 0.18 -1 -1 0.40 0.0200355 0.0178052 110 65 62 32 64 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_037.v common 8.75 vpr 64.87 MiB 0.04 7184 -1 -1 1 0.05 -1 -1 34224 -1 -1 16 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66428 31 32 353 302 1 224 79 17 17 289 -1 unnamed_device 26.0 MiB 1.11 1061 8867 2259 5908 700 64.9 MiB 0.06 0.00 3.47679 -127.153 -3.47679 3.47679 0.94 0.000198827 0.000156777 0.0132116 0.0108281 -1 -1 -1 -1 40 2485 24 6.99608e+06 235451 706193. 2443.58 4.15 0.0987458 0.0811122 26914 176310 -1 2159 35 1875 1958 356327 152178 3.24576 3.24576 -128.28 -3.24576 0 0 926341. 3205.33 0.35 0.11 0.15 -1 -1 0.35 0.0193278 0.0166574 99 90 0 0 89 31 -fixed_k6_frac_2uripple_N8_22nm.xml mult_038.v common 6.62 vpr 64.75 MiB 0.03 7340 -1 -1 1 0.04 -1 -1 34028 -1 -1 18 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66308 31 32 391 309 1 242 81 17 17 289 -1 unnamed_device 25.7 MiB 0.93 1183 15656 5841 7703 2112 64.8 MiB 0.10 0.00 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66532 32 32 407 319 1 252 81 17 17 289 -1 unnamed_device 26.2 MiB 1.14 1214 6556 2392 3648 516 65.0 MiB 0.06 0.00 3.81945 -147.993 -3.81945 3.81945 0.96 0.000279184 0.000211029 0.0125466 0.0103975 -1 -1 -1 -1 46 2989 29 6.99608e+06 250167 828058. 2865.25 2.37 0.0880295 0.0738868 28066 200906 -1 2519 22 2224 2868 243990 48257 3.93982 3.93982 -158.396 -3.93982 0 0 1.01997e+06 3529.29 0.39 0.07 0.18 -1 -1 0.39 0.0172134 0.0151412 110 65 64 32 64 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_043.v common 11.70 vpr 65.39 MiB 0.03 7280 -1 -1 1 0.05 -1 -1 34328 -1 -1 22 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66964 32 32 496 380 1 313 86 17 17 289 -1 unnamed_device 26.3 MiB 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-fixed_k6_frac_2uripple_N8_22nm.xml mult_046.v common 7.21 vpr 64.75 MiB 0.04 7200 -1 -1 1 0.04 -1 -1 34136 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 397 313 1 246 84 17 17 289 -1 unnamed_device 25.9 MiB 1.54 1277 13077 4097 6940 2040 64.7 MiB 0.09 0.00 3.58873 -134.162 -3.58873 3.58873 0.99 0.000229633 0.000180938 0.0194183 0.0157603 -1 -1 -1 -1 42 3408 27 6.99608e+06 294314 744469. 2576.02 2.01 0.0800376 0.066476 27202 183097 -1 2874 20 1975 2784 237357 49435 3.78176 3.78176 -147.68 -3.78176 0 0 949917. 3286.91 0.36 0.08 0.17 -1 -1 0.36 0.0210986 0.0188864 108 63 62 32 62 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_047.v common 7.17 vpr 64.48 MiB 0.02 7164 -1 -1 1 0.04 -1 -1 33912 -1 -1 13 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66032 32 32 345 257 1 187 77 17 17 289 -1 unnamed_device 25.8 MiB 1.04 749 9368 3828 5102 438 64.5 MiB 0.06 0.00 3.60355 -132.937 -3.60355 3.60355 0.93 0.000213125 0.00016731 0.0149499 0.012205 -1 -1 -1 -1 56 2389 27 6.99608e+06 191304 973134. 3367.25 2.49 0.0828029 0.0693947 29794 239141 -1 1739 21 1825 3135 221688 52565 4.10836 4.10836 -144.078 -4.10836 0 0 1.19926e+06 4149.71 0.45 0.09 0.22 -1 -1 0.45 0.0220902 0.0198719 78 3 128 32 0 0 -fixed_k6_frac_2uripple_N8_22nm.xml mult_048.v common 7.58 vpr 64.88 MiB 0.02 7200 -1 -1 1 0.05 -1 -1 35376 -1 -1 19 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66440 32 32 424 343 1 266 83 17 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66340 31 32 449 367 1 290 85 17 17 289 -1 unnamed_device 26.4 MiB 2.11 1393 14035 5565 6766 1704 64.8 MiB 0.10 0.00 4.08308 -143.875 -4.08308 4.08308 0.96 0.000255139 0.000191975 0.0220399 0.0175298 -1 -1 -1 -1 46 3396 24 6.99608e+06 323745 828058. 2865.25 2.11 0.0987222 0.0814817 28066 200906 -1 2897 21 2039 2368 186090 38982 4.05885 4.05885 -147.773 -4.05885 0 0 1.01997e+06 3529.29 0.42 0.07 0.20 -1 -1 0.42 0.0220963 0.0195136 132 122 0 0 122 31 -fixed_k6_frac_2uripple_N8_22nm.xml mult_054.v common 7.29 vpr 64.72 MiB 0.04 7324 -1 -1 1 0.04 -1 -1 34048 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66272 32 32 432 346 1 281 85 17 17 289 -1 unnamed_device 26.1 MiB 1.10 1279 12175 4545 5316 2314 64.7 MiB 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66208 32 32 368 284 1 217 80 17 17 289 -1 unnamed_device 25.8 MiB 0.95 1017 10916 2707 7442 767 64.7 MiB 0.08 0.00 3.32994 -129.578 -3.32994 3.32994 1.03 0.000220964 0.000174747 0.0171409 0.0140139 -1 -1 -1 -1 40 2983 47 6.99608e+06 235451 706193. 2443.58 5.65 0.167246 0.139392 26914 176310 -1 2449 20 2023 2659 257257 52586 3.29722 3.29722 -135.821 -3.29722 0 0 926341. 3205.33 0.36 0.08 0.16 -1 -1 0.36 0.0181497 0.0161526 93 34 92 32 32 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_059.v common 7.62 vpr 64.62 MiB 0.04 7124 -1 -1 1 0.06 -1 -1 33716 -1 -1 24 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66168 30 32 296 244 1 177 86 17 17 289 -1 unnamed_device 25.7 MiB 0.91 690 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-fixed_k6_frac_2uripple_N8_22nm.xml mult_062.v common 9.33 vpr 64.30 MiB 0.03 6768 -1 -1 1 0.04 -1 -1 33912 -1 -1 24 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65848 32 32 283 225 1 158 88 17 17 289 -1 unnamed_device 25.6 MiB 0.34 689 12763 5259 7126 378 64.3 MiB 0.07 0.00 2.98775 -114.562 -2.98775 2.98775 1.06 0.000182842 0.000144177 0.0144186 0.0116779 -1 -1 -1 -1 46 1939 24 6.99608e+06 353176 828058. 2865.25 5.26 0.106654 0.0893777 28066 200906 -1 1527 21 1501 2262 149821 33894 3.01532 3.01532 -116.678 -3.01532 0 0 1.01997e+06 3529.29 0.40 0.05 0.18 -1 -1 0.40 0.0122811 0.0107309 70 3 96 32 0 0 -fixed_k6_frac_2uripple_N8_22nm.xml mult_063.v common 22.35 vpr 65.39 MiB 0.03 7272 -1 -1 1 0.05 -1 -1 34388 -1 -1 18 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66960 32 32 438 320 1 256 82 17 17 289 -1 unnamed_device 26.4 MiB 1.16 1185 13432 5656 7470 306 65.4 MiB 0.10 0.00 4.53729 -162.267 -4.53729 4.53729 1.07 0.000263201 0.000209673 0.0242107 0.019831 -1 -1 -1 -1 50 3497 30 6.99608e+06 264882 902133. 3121.57 17.27 0.194278 0.162778 28642 213929 -1 2557 23 2809 4093 320106 67773 4.92476 4.92476 -175.108 -4.92476 0 0 1.08113e+06 3740.92 0.44 0.09 0.19 -1 -1 0.44 0.022 0.0195436 112 34 128 32 32 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_064.v common 7.14 vpr 63.99 MiB 0.04 6820 -1 -1 1 0.04 -1 -1 33864 -1 -1 10 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65524 32 32 283 225 1 156 74 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66648 32 32 407 319 1 249 82 17 17 289 -1 unnamed_device 26.3 MiB 1.27 1170 5244 1136 3811 297 65.1 MiB 0.05 0.00 4.32144 -158.986 -4.32144 4.32144 1.00 0.000230503 0.000183217 0.0103799 0.00872211 -1 -1 -1 -1 46 3311 42 6.99608e+06 264882 828058. 2865.25 5.78 0.140111 0.117171 28066 200906 -1 2631 25 2845 3941 372150 72492 4.81551 4.81551 -175.677 -4.81551 0 0 1.01997e+06 3529.29 0.42 0.11 0.18 -1 -1 0.42 0.0232085 0.0205383 110 65 64 32 64 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_069.v common 7.76 vpr 64.56 MiB 0.04 7028 -1 -1 1 0.05 -1 -1 34096 -1 -1 15 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66112 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66156 30 32 325 273 1 204 77 17 17 289 -1 unnamed_device 25.8 MiB 1.97 887 12139 5086 6651 402 64.6 MiB 0.08 0.00 3.82453 -131.841 -3.82453 3.82453 1.01 0.000190891 0.000150526 0.0165867 0.0133726 -1 -1 -1 -1 38 3002 38 6.99608e+06 220735 678818. 2348.85 2.79 0.0817484 0.0683012 26626 170182 -1 2180 23 2088 2835 240005 53520 4.0456 4.0456 -144.414 -4.0456 0 0 902133. 3121.57 0.35 0.10 0.16 -1 -1 0.35 0.0265658 0.0238164 89 63 30 30 60 30 -fixed_k6_frac_2uripple_N8_22nm.xml mult_074.v common 8.01 vpr 64.73 MiB 0.02 7076 -1 -1 1 0.04 -1 -1 33840 -1 -1 15 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66284 32 32 361 308 1 241 79 17 17 289 -1 unnamed_device 25.8 MiB 1.46 1045 13430 4937 5959 2534 64.7 MiB 0.09 0.00 3.53869 -131.536 -3.53869 3.53869 0.98 0.000226974 0.000181446 0.021796 0.0177445 -1 -1 -1 -1 42 3258 28 6.99608e+06 220735 744469. 2576.02 2.86 0.122763 0.104468 27202 183097 -1 2507 23 2060 2527 240062 48931 3.41506 3.41506 -131.615 -3.41506 0 0 949917. 3286.91 0.44 0.08 0.18 -1 -1 0.44 0.0197599 0.0175337 105 91 0 0 91 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_075.v common 10.08 vpr 64.36 MiB 0.02 7012 -1 -1 1 0.06 -1 -1 33940 -1 -1 25 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65904 31 32 335 251 1 188 88 17 17 289 -1 unnamed_device 25.5 MiB 0.24 786 15688 6044 7337 2307 64.4 MiB 0.09 0.00 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66020 30 32 296 244 1 179 75 17 17 289 -1 unnamed_device 25.7 MiB 1.04 692 12241 5462 6298 481 64.5 MiB 0.07 0.00 3.58339 -124.571 -3.58339 3.58339 0.96 0.000183567 0.000145119 0.016464 0.0133148 -1 -1 -1 -1 46 2629 41 6.99608e+06 191304 828058. 2865.25 2.93 0.0913011 0.0769988 28066 200906 -1 1796 22 1604 2143 175253 41225 3.70046 3.70046 -130.475 -3.70046 0 0 1.01997e+06 3529.29 0.39 0.06 0.18 -1 -1 0.39 0.0133216 0.0117077 76 34 60 30 30 30 -fixed_k6_frac_2uripple_N8_22nm.xml mult_080.v common 12.51 vpr 64.85 MiB 0.03 7268 -1 -1 1 0.05 -1 -1 34044 -1 -1 18 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66404 30 32 383 303 1 237 80 17 17 289 -1 unnamed_device 26.1 MiB 2.48 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9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66680 32 32 407 319 1 252 83 17 17 289 -1 unnamed_device 26.2 MiB 1.18 985 15563 6705 8342 516 65.1 MiB 0.11 0.00 4.37079 -157.14 -4.37079 4.37079 0.96 0.000244224 0.000193967 0.0245303 0.0199559 -1 -1 -1 -1 46 3379 44 6.99608e+06 279598 828058. 2865.25 3.55 0.122301 0.102909 28066 200906 -1 2435 24 2773 3900 345445 73632 4.90351 4.90351 -180.423 -4.90351 0 0 1.01997e+06 3529.29 0.40 0.09 0.19 -1 -1 0.40 0.0193243 0.0170213 111 65 64 32 64 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_085.v common 8.24 vpr 64.73 MiB 0.03 7328 -1 -1 1 0.04 -1 -1 33952 -1 -1 20 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66288 29 32 387 316 1 240 81 17 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66712 32 32 407 319 1 252 82 17 17 289 -1 unnamed_device 26.3 MiB 1.08 1239 11118 3581 5407 2130 65.1 MiB 0.08 0.00 3.83715 -144.315 -3.83715 3.83715 0.89 0.00024052 0.00019174 0.0195501 0.0160437 -1 -1 -1 -1 40 3054 44 6.99608e+06 264882 706193. 2443.58 9.37 0.164638 0.135906 26914 176310 -1 2607 23 2389 2887 211349 46103 4.51132 4.51132 -164.932 -4.51132 0 0 926341. 3205.33 0.37 0.07 0.16 -1 -1 0.37 0.0190344 0.0167079 110 65 64 32 64 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_116.v common 8.59 vpr 64.79 MiB 0.02 7116 -1 -1 1 0.04 -1 -1 33976 -1 -1 21 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66340 29 32 367 293 1 222 82 17 17 289 -1 unnamed_device 26.0 MiB 1.96 912 9160 3705 5067 388 64.8 MiB 0.06 0.00 3.41124 -117.288 -3.41124 3.41124 0.94 0.000207571 0.00016423 0.0132526 0.0108472 -1 -1 -1 -1 38 3022 46 6.99608e+06 309029 678818. 2348.85 3.30 0.0824746 0.0680641 26626 170182 -1 2437 25 2136 2811 246062 52450 3.51187 3.51187 -127.239 -3.51187 0 0 902133. 3121.57 0.32 0.07 0.15 -1 -1 0.32 0.0176691 0.0154476 101 62 56 29 58 29 -fixed_k6_frac_2uripple_N8_22nm.xml mult_117.v common 18.33 vpr 64.91 MiB 0.02 7344 -1 -1 1 0.04 -1 -1 34152 -1 -1 22 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66472 32 32 469 381 1 309 86 17 17 289 -1 unnamed_device 26.3 MiB 1.04 1399 13316 4006 7788 1522 64.9 MiB 0.10 0.00 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66600 32 32 401 316 1 247 83 17 17 289 -1 unnamed_device 26.2 MiB 1.01 1122 13403 4777 5917 2709 65.0 MiB 0.09 0.00 3.33684 -128.047 -3.33684 3.33684 0.87 0.000224408 0.000178231 0.0197189 0.0161144 -1 -1 -1 -1 40 3281 42 6.99608e+06 279598 706193. 2443.58 11.50 0.162397 0.134694 26914 176310 -1 2604 23 2214 2913 246629 50304 3.47452 3.47452 -138.906 -3.47452 0 0 926341. 3205.33 0.35 0.08 0.16 -1 -1 0.35 0.0187151 0.0164243 106 65 61 32 64 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_122.v common 20.77 vpr 65.05 MiB 0.03 7364 -1 -1 1 0.05 -1 -1 34460 -1 -1 22 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66612 32 32 500 382 1 312 86 17 17 289 -1 unnamed_device 26.6 MiB 1.04 1505 15584 4795 8564 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65744 29 32 272 228 1 148 80 17 17 289 -1 unnamed_device 25.4 MiB 2.95 801 11776 3453 6762 1561 64.2 MiB 0.07 0.00 3.43775 -109.554 -3.43775 3.43775 0.89 0.000162292 0.000127804 0.0127527 0.0102608 -1 -1 -1 -1 32 1877 23 6.87369e+06 265503 586450. 2029.24 0.93 0.0418293 0.03461 25474 144626 -1 1647 23 1064 1825 119258 27812 2.99626 2.99626 -112.835 -2.99626 0 0 744469. 2576.02 0.29 0.04 0.13 -1 -1 0.29 0.012181 0.0105405 102 29 58 29 24 24 -fixed_k6_frac_ripple_N8_22nm.xml mult_016.v common 9.77 vpr 64.37 MiB 0.02 7148 -1 -1 1 0.05 -1 -1 33800 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65916 32 32 401 315 1 200 85 17 17 289 -1 unnamed_device 25.6 MiB 4.31 1029 14221 5946 7079 1196 64.4 MiB 0.10 0.00 3.65105 -129.633 -3.65105 3.65105 0.87 0.000224714 0.000177642 0.0207869 0.0167666 -1 -1 -1 -1 36 3065 50 6.87369e+06 293451 648988. 2245.63 2.19 0.0958683 0.0786595 26050 158493 -1 2297 19 1926 3226 237152 58676 3.45816 3.45816 -139.806 -3.45816 0 0 828058. 2865.25 0.33 0.07 0.16 -1 -1 0.33 0.0159029 0.0139562 145 63 64 32 62 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_017.v common 10.02 vpr 64.67 MiB 0.02 7264 -1 -1 1 0.04 -1 -1 34080 -1 -1 38 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66224 32 32 383 303 1 193 102 17 17 289 -1 unnamed_device 26.0 MiB 5.90 1063 17238 4632 10836 1770 64.7 MiB 0.13 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66448 32 32 376 288 1 202 100 17 17 289 -1 unnamed_device 26.0 MiB 1.21 1077 18660 4798 12102 1760 64.9 MiB 0.13 0.00 4.29809 -149.349 -4.29809 4.29809 0.89 0.000215605 0.000168808 0.0198175 0.0159125 -1 -1 -1 -1 32 2995 31 6.87369e+06 503058 586450. 2029.24 1.04 0.0622672 0.0514239 25474 144626 -1 2431 21 1840 2718 195257 46178 3.9299 3.9299 -152.07 -3.9299 0 0 744469. 2576.02 0.29 0.06 0.13 -1 -1 0.29 0.013973 0.0121396 155 34 96 32 32 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_027.v common 5.72 vpr 64.41 MiB 0.02 7124 -1 -1 1 0.04 -1 -1 34208 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65956 32 32 337 253 1 198 100 17 17 289 -1 unnamed_device 25.7 MiB 1.45 1035 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66304 32 32 403 317 1 200 103 17 17 289 -1 unnamed_device 26.0 MiB 3.98 1053 18419 4965 10740 2714 64.8 MiB 0.13 0.00 3.69025 -132.499 -3.69025 3.69025 0.87 0.000236148 0.000186453 0.0200595 0.0159935 -1 -1 -1 -1 32 2477 24 6.87369e+06 544980 586450. 2029.24 0.98 0.0615048 0.0505014 25474 144626 -1 2015 22 1749 2539 155694 36025 2.98996 2.98996 -128.336 -2.98996 0 0 744469. 2576.02 0.32 0.05 0.14 -1 -1 0.32 0.0156752 0.0135608 154 65 62 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_037.v common 8.92 vpr 64.12 MiB 0.02 7092 -1 -1 1 0.03 -1 -1 34300 -1 -1 31 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65664 31 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66028 31 32 391 309 1 195 99 17 17 289 -1 unnamed_device 25.7 MiB 3.37 1065 19023 5641 10657 2725 64.5 MiB 0.14 0.00 3.57405 -123.706 -3.57405 3.57405 0.90 0.000242943 0.000183485 0.0209234 0.0164715 -1 -1 -1 -1 34 2347 23 6.87369e+06 503058 618332. 2139.56 1.46 0.0807165 0.0656769 25762 151098 -1 1963 20 1564 2747 169520 40321 2.77566 2.77566 -115.861 -2.77566 0 0 787024. 2723.27 0.31 0.05 0.13 -1 -1 0.31 0.0136101 0.0117076 148 64 60 31 62 31 -fixed_k6_frac_ripple_N8_22nm.xml mult_042.v common 6.77 vpr 64.87 MiB 0.03 7196 -1 -1 1 0.04 -1 -1 34300 -1 -1 38 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66424 32 32 407 319 1 202 102 17 17 289 -1 unnamed_device 25.8 MiB 2.45 1155 19618 5472 12434 1712 64.9 MiB 0.15 0.00 4.1996 -146.035 -4.1996 4.1996 0.87 0.000223865 0.000176571 0.0213021 0.0169841 -1 -1 -1 -1 30 2958 23 6.87369e+06 531006 556674. 1926.21 1.06 0.0591899 0.048507 25186 138497 -1 2309 19 1570 2428 163554 36586 3.9064 3.9064 -153.734 -3.9064 0 0 706193. 2443.58 0.30 0.05 0.12 -1 -1 0.30 0.013815 0.01203 156 65 64 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_043.v common 8.61 vpr 65.12 MiB 0.03 7296 -1 -1 1 0.04 -1 -1 34172 -1 -1 42 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66680 32 32 496 380 1 234 106 17 17 289 -1 unnamed_device 26.1 MiB 4.22 1304 13356 3354 8810 1192 65.1 MiB 0.15 0.00 4.3641 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-1 -1 1 0.04 -1 -1 34144 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 397 313 1 198 99 17 17 289 -1 unnamed_device 25.8 MiB 2.66 1125 15147 4465 9540 1142 64.6 MiB 0.12 0.00 3.50375 -124.908 -3.50375 3.50375 0.87 0.000224984 0.000177759 0.017141 0.013773 -1 -1 -1 -1 30 2615 20 6.87369e+06 489084 556674. 1926.21 0.96 0.0533442 0.0438888 25186 138497 -1 2047 22 1534 2693 140187 33757 2.78966 2.78966 -116.866 -2.78966 0 0 706193. 2443.58 0.27 0.05 0.12 -1 -1 0.27 0.0145921 0.0125912 150 63 62 32 62 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_047.v common 7.32 vpr 64.48 MiB 0.02 7024 -1 -1 1 0.03 -1 -1 34096 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66032 32 32 345 257 1 202 85 17 17 289 -1 unnamed_device 25.5 MiB 2.52 962 16825 4488 11549 788 64.5 MiB 0.13 0.00 4.1996 -145.34 -4.1996 4.1996 0.88 0.000206785 0.000163548 0.021257 0.0171171 -1 -1 -1 -1 32 3332 24 6.87369e+06 293451 586450. 2029.24 1.60 0.0694849 0.0574817 25474 144626 -1 2278 21 1867 3241 210798 52491 3.89741 3.89741 -156.479 -3.89741 0 0 744469. 2576.02 0.32 0.06 0.13 -1 -1 0.32 0.0139255 0.0121673 147 3 128 32 0 0 -fixed_k6_frac_ripple_N8_22nm.xml mult_048.v common 9.63 vpr 64.85 MiB 0.03 7312 -1 -1 1 0.04 -1 -1 35468 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66404 32 32 424 343 1 195 100 17 17 289 -1 unnamed_device 25.8 MiB 4.91 1065 20980 6969 11401 2610 64.8 MiB 0.18 0.00 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64.57 MiB 0.02 7228 -1 -1 1 0.03 -1 -1 33876 -1 -1 39 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 376 288 1 202 103 17 17 289 -1 unnamed_device 25.7 MiB 1.42 958 13599 3600 8151 1848 64.6 MiB 0.08 0.00 4.3249 -147.82 -4.3249 4.3249 0.86 0.000216082 0.000170272 0.0142184 0.0113278 -1 -1 -1 -1 32 2911 36 6.87369e+06 544980 586450. 2029.24 1.63 0.0726237 0.060214 25474 144626 -1 2230 22 1793 2893 184546 46762 4.02571 4.02571 -159.108 -4.02571 0 0 744469. 2576.02 0.30 0.06 0.13 -1 -1 0.30 0.0155482 0.0134674 156 34 96 32 32 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_052.v common 10.15 vpr 64.68 MiB 0.02 7180 -1 -1 1 0.05 -1 -1 34132 -1 -1 41 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66236 32 32 407 319 1 202 105 17 17 289 -1 unnamed_device 25.8 MiB 3.72 1138 19865 5157 12797 1911 64.7 MiB 0.15 0.00 4.20633 -143.385 -4.20633 4.20633 0.86 0.000249249 0.000201686 0.0226384 0.0181355 -1 -1 -1 -1 30 2568 24 6.87369e+06 572927 556674. 1926.21 3.16 0.106058 0.0864942 25186 138497 -1 2323 25 1941 3133 245373 54886 3.8924 3.8924 -154.334 -3.8924 0 0 706193. 2443.58 0.27 0.07 0.12 -1 -1 0.27 0.015799 0.0135051 157 65 64 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_053.v common 9.40 vpr 65.14 MiB 0.03 7500 -1 -1 1 0.04 -1 -1 34216 -1 -1 37 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66700 31 32 449 367 1 195 100 17 17 289 -1 unnamed_device 26.0 MiB 5.09 910 8684 1839 6215 630 65.1 MiB 0.08 0.00 4.22589 -134.122 -4.22589 4.22589 0.88 0.000237887 0.00018619 0.0113147 0.00901135 -1 -1 -1 -1 30 2752 25 6.87369e+06 517032 556674. 1926.21 1.16 0.0547158 0.0450792 25186 138497 -1 2053 20 1379 2449 129700 33281 3.8074 3.8074 -136.498 -3.8074 0 0 706193. 2443.58 0.28 0.05 0.12 -1 -1 0.28 0.0140976 0.0121024 150 122 0 0 122 31 -fixed_k6_frac_ripple_N8_22nm.xml mult_054.v common 9.21 vpr 65.26 MiB 0.02 7100 -1 -1 1 0.05 -1 -1 33872 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66824 32 32 432 346 1 200 85 17 17 289 -1 unnamed_device 26.2 MiB 4.45 1073 15709 4453 9637 1619 65.3 MiB 0.12 0.00 4.13359 -143.434 -4.13359 4.13359 0.87 0.00023319 0.000183164 0.0217007 0.0173423 -1 -1 -1 -1 34 2807 23 6.87369e+06 293451 618332. 2139.56 1.56 0.086419 0.0705133 25762 151098 -1 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66724 32 32 469 351 1 236 108 17 17 289 -1 unnamed_device 25.9 MiB 2.85 1417 17327 4454 11447 1426 65.2 MiB 0.15 0.00 4.99284 -170.997 -4.99284 4.99284 0.85 0.000258779 0.000204777 0.0200466 0.0160881 -1 -1 -1 -1 30 3591 25 6.87369e+06 614849 556674. 1926.21 3.42 0.12118 0.100026 25186 138497 -1 2850 21 2202 3809 257801 56093 4.31865 4.31865 -166.494 -4.31865 0 0 706193. 2443.58 0.27 0.07 0.12 -1 -1 0.27 0.017747 0.0153865 189 65 96 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_058.v common 7.67 vpr 64.46 MiB 0.02 7028 -1 -1 1 0.03 -1 -1 34020 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66004 32 32 368 284 1 198 99 17 17 289 -1 unnamed_device 25.6 MiB 3.65 1065 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2089 22 6.87369e+06 461137 618332. 2139.56 1.44 0.070595 0.0579194 25762 151098 -1 1735 17 1235 1956 122081 30864 3.04926 3.04926 -122.245 -3.04926 0 0 787024. 2723.27 0.30 0.04 0.13 -1 -1 0.30 0.0105222 0.00916378 123 65 32 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_070.v common 9.85 vpr 64.05 MiB 0.03 7152 -1 -1 1 0.04 -1 -1 34184 -1 -1 18 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65592 31 32 353 302 1 160 81 17 17 289 -1 unnamed_device 25.2 MiB 5.31 853 13381 4420 7135 1826 64.1 MiB 0.09 0.00 3.47075 -119.995 -3.47075 3.47075 0.88 0.000192776 0.000150994 0.0163016 0.0129391 -1 -1 -1 -1 34 2045 22 6.87369e+06 251529 618332. 2139.56 1.43 0.0697653 0.0568018 25762 151098 -1 1733 21 1033 1932 133986 30887 2.70966 2.70966 -113.156 -2.70966 0 0 787024. 2723.27 0.32 0.05 0.13 -1 -1 0.32 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65860 28 32 332 260 1 180 95 17 17 289 -1 unnamed_device 25.4 MiB 2.04 910 12623 3390 8288 945 64.3 MiB 0.09 0.00 4.19891 -126.139 -4.19891 4.19891 0.86 0.000207099 0.000169791 0.0140662 0.0114999 -1 -1 -1 -1 28 2341 25 6.87369e+06 489084 531479. 1839.03 2.84 0.0843971 0.0696707 24610 126494 -1 2006 18 1450 2389 167831 39763 3.7341 3.7341 -130.294 -3.7341 0 0 648988. 2245.63 0.26 0.06 0.11 -1 -1 0.26 0.0149856 0.0131992 139 34 84 28 28 28 -fixed_k6_frac_ripple_N8_22nm.xml mult_073.v common 9.82 vpr 63.48 MiB 0.02 7148 -1 -1 1 0.04 -1 -1 33752 -1 -1 18 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66060 30 32 404 328 1 188 94 17 17 289 -1 unnamed_device 25.7 MiB 2.99 935 16921 4888 8942 3091 64.5 MiB 0.15 0.00 3.55591 -115.746 -3.55591 3.55591 0.97 0.000226366 0.00017879 0.0243287 0.0196111 -1 -1 -1 -1 32 2417 27 6.87369e+06 447163 586450. 2029.24 1.45 0.0757108 0.062121 25474 144626 -1 1907 21 1729 2823 182050 44816 2.83496 2.83496 -110.923 -2.83496 0 0 744469. 2576.02 0.29 0.05 0.12 -1 -1 0.29 0.0138646 0.0119459 141 92 26 26 90 30 -fixed_k6_frac_ripple_N8_22nm.xml mult_084.v common 11.37 vpr 64.75 MiB 0.03 7200 -1 -1 1 0.04 -1 -1 34252 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66304 32 32 407 319 1 202 85 17 17 289 -1 unnamed_device 25.9 MiB 6.65 1090 14593 4195 9072 1326 64.8 MiB 0.11 0.00 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65892 32 32 407 319 1 202 85 17 17 289 -1 unnamed_device 25.5 MiB 5.86 1089 15151 6141 8127 883 64.3 MiB 0.12 0.00 4.2388 -152.365 -4.2388 4.2388 0.87 0.000245556 0.00019339 0.0217641 0.0175302 -1 -1 -1 -1 34 2813 25 6.87369e+06 293451 618332. 2139.56 1.56 0.0870329 0.0714122 25762 151098 -1 2284 21 1936 3204 224975 50146 3.8064 3.8064 -151.466 -3.8064 0 0 787024. 2723.27 0.30 0.06 0.13 -1 -1 0.30 0.014551 0.0125512 147 65 64 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_089.v common 9.35 vpr 64.21 MiB 0.02 6920 -1 -1 1 0.04 -1 -1 34128 -1 -1 30 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65748 32 32 315 267 1 158 94 17 17 289 -1 unnamed_device 25.5 MiB 4.92 885 16708 5068 9384 2256 64.2 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66460 32 32 399 285 1 232 105 17 17 289 -1 unnamed_device 25.6 MiB 1.58 1421 17642 5571 10308 1763 64.9 MiB 0.16 0.00 4.86064 -164.755 -4.86064 4.86064 0.87 0.000263008 0.000213785 0.0204632 0.0165214 -1 -1 -1 -1 28 3916 26 6.87369e+06 572927 531479. 1839.03 1.92 0.0684584 0.0573019 24610 126494 -1 3082 22 2321 3773 334328 70756 4.99175 4.99175 -173.828 -4.99175 0 0 648988. 2245.63 0.25 0.08 0.11 -1 -1 0.25 0.0163948 0.0142184 183 3 156 32 0 0 -fixed_k6_frac_ripple_N8_22nm.xml mult_094.v common 7.72 vpr 64.30 MiB 0.02 7160 -1 -1 1 0.04 -1 -1 34256 -1 -1 32 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65844 30 32 371 295 1 188 94 17 17 289 -1 unnamed_device 25.7 MiB 3.49 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GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 405 318 1 201 106 17 17 289 -1 unnamed_device 25.7 MiB 3.95 1124 19356 5960 11281 2115 64.8 MiB 0.14 0.00 3.52575 -126.289 -3.52575 3.52575 0.95 0.000231539 0.000181695 0.0207286 0.0164649 -1 -1 -1 -1 28 2720 22 6.87369e+06 586901 531479. 1839.03 0.99 0.0592066 0.0484379 24610 126494 -1 2281 23 1865 2999 197983 46445 2.85366 2.85366 -124.307 -2.85366 0 0 648988. 2245.63 0.27 0.06 0.12 -1 -1 0.27 0.0147338 0.0126694 157 65 63 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_104.v common 6.55 vpr 63.94 MiB 0.02 7028 -1 -1 1 0.03 -1 -1 33844 -1 -1 19 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65472 29 32 287 238 1 155 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6.87369e+06 209608 618332. 2139.56 1.36 0.0639777 0.0520625 25762 151098 -1 1734 18 961 1429 108243 23610 2.77096 2.77096 -111.679 -2.77096 0 0 787024. 2723.27 0.30 0.04 0.13 -1 -1 0.30 0.010599 0.00915162 101 82 0 0 82 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 7.30 vpr 64.63 MiB 0.02 7164 -1 -1 1 0.04 -1 -1 34024 -1 -1 39 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66180 31 32 365 281 1 197 102 17 17 289 -1 unnamed_device 25.7 MiB 2.30 1129 19618 5686 11712 2220 64.6 MiB 0.16 0.00 4.1955 -141.345 -4.1955 4.1955 0.89 0.000219606 0.00017348 0.0206175 0.0165582 -1 -1 -1 -1 26 3057 24 6.87369e+06 544980 503264. 1741.40 1.82 0.0670987 0.0559839 24322 120374 -1 2634 18 1808 2912 248656 53210 4.1163 4.1163 -154.166 -4.1163 0 0 618332. 2139.56 0.25 0.07 0.11 -1 -1 0.25 0.0127215 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65684 32 32 314 256 1 168 80 17 17 289 -1 unnamed_device 25.4 MiB 4.82 751 9884 2209 6799 876 64.1 MiB 0.07 0.00 3.54365 -123.521 -3.54365 3.54365 0.88 0.000199945 0.00015956 0.0126742 0.0102434 -1 -1 -1 -1 34 2329 25 6.87369e+06 223581 618332. 2139.56 1.54 0.0700718 0.0578442 25762 151098 -1 1833 20 1450 2403 162142 41252 3.33286 3.33286 -129.55 -3.33286 0 0 787024. 2723.27 0.32 0.05 0.15 -1 -1 0.32 0.0131642 0.0115269 114 34 64 32 32 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_109.v common 7.99 vpr 64.91 MiB 0.02 7356 -1 -1 1 0.04 -1 -1 34352 -1 -1 35 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 339 283 1 166 80 17 17 289 -1 unnamed_device 25.6 MiB 4.20 885 10744 2853 7291 600 64.5 MiB 0.08 0.00 3.52165 -124.831 -3.52165 3.52165 0.89 0.000192461 0.000151372 0.0143825 0.0115919 -1 -1 -1 -1 32 2324 23 6.87369e+06 223581 586450. 2029.24 0.98 0.0508054 0.0421806 25474 144626 -1 1985 22 1341 2306 170125 38936 3.03826 3.03826 -124.192 -3.03826 0 0 744469. 2576.02 0.30 0.06 0.12 -1 -1 0.30 0.0154408 0.013459 112 63 32 32 62 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_115.v common 7.99 vpr 64.84 MiB 0.02 6996 -1 -1 1 0.04 -1 -1 34212 -1 -1 40 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66400 32 32 407 319 1 202 104 17 17 289 -1 unnamed_device 25.8 MiB 3.82 1034 13768 3498 9086 1184 64.8 MiB 0.11 0.00 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65964 32 32 418 338 1 194 101 17 17 289 -1 unnamed_device 25.5 MiB 2.27 980 17961 5545 9859 2557 64.4 MiB 0.13 0.00 4.28709 -142.511 -4.28709 4.28709 0.86 0.000234881 0.000184997 0.0202386 0.0161602 -1 -1 -1 -1 34 2224 22 6.87369e+06 517032 618332. 2139.56 1.46 0.0842825 0.068848 25762 151098 -1 1870 22 1465 2223 131927 31674 3.606 3.606 -133.315 -3.606 0 0 787024. 2723.27 0.30 0.05 0.13 -1 -1 0.30 0.0149753 0.0128466 147 92 28 28 92 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_120.v common 10.08 vpr 64.34 MiB 0.02 7016 -1 -1 1 0.04 -1 -1 33820 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65888 32 32 376 318 1 168 80 17 17 289 -1 unnamed_device 25.6 MiB 5.63 956 12808 4156 7121 1531 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65744 30 32 296 244 1 158 80 17 17 289 -1 unnamed_device 25.3 MiB 1.32 761 12120 5037 6663 420 64.2 MiB 0.08 0.00 3.55905 -117.266 -3.55905 3.55905 0.87 0.00017626 0.000139469 0.0142 0.0114757 -1 -1 -1 -1 32 1841 36 6.87369e+06 251529 586450. 2029.24 0.94 0.0492163 0.0407116 25474 144626 -1 1498 22 1417 2088 130027 30932 3.00236 3.00236 -116.529 -3.00236 0 0 744469. 2576.02 0.30 0.05 0.14 -1 -1 0.30 0.0119945 0.0103626 109 34 60 30 30 30 -fixed_k6_frac_ripple_N8_22nm.xml mult_125.v common 6.84 vpr 64.06 MiB 0.02 6868 -1 -1 1 0.04 -1 -1 33816 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65596 32 32 314 256 1 168 80 17 17 289 -1 unnamed_device 25.3 MiB 2.23 871 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65880 27 32 269 226 1 164 80 17 17 289 -1 unnamed_device 25.4 MiB 1.90 736 14528 4306 9196 1026 64.3 MiB 0.09 0.00 3.83226 -109.478 -3.83226 3.83226 0.85 0.000168821 0.000132794 0.0152965 0.0122355 -1 -1 -1 -1 30 2004 33 6.89349e+06 295971 556674. 1926.21 0.96 0.047321 0.0388631 25186 138497 -1 1617 20 1157 1681 96912 23589 3.00146 3.00146 -107.805 -3.00146 0 0 706193. 2443.58 0.28 0.04 0.12 -1 -1 0.28 0.0102131 0.00884307 112 34 54 27 27 27 -fixed_k6_frac_uripple_N8_22nm.xml mult_008.v common 5.75 vpr 64.38 MiB 0.02 7072 -1 -1 1 0.04 -1 -1 33712 -1 -1 35 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65928 31 32 317 242 1 187 98 17 17 289 -1 unnamed_device 25.5 MiB 1.15 921 14273 4376 7304 2593 64.4 MiB 0.10 0.00 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65936 32 32 331 280 1 215 84 17 17 289 -1 unnamed_device 25.5 MiB 2.55 879 15822 5947 6978 2897 64.4 MiB 0.10 0.00 3.8521 -121.987 -3.8521 3.8521 0.89 0.000196412 0.000155369 0.0188877 0.0151892 -1 -1 -1 -1 34 2631 49 6.89349e+06 281877 618332. 2139.56 1.63 0.0749337 0.0615648 25762 151098 -1 1815 17 1150 1285 88992 22042 3.20001 3.20001 -113.739 -3.20001 0 0 787024. 2723.27 0.32 0.04 0.13 -1 -1 0.32 0.0121447 0.0107 135 65 25 25 64 32 -fixed_k6_frac_uripple_N8_22nm.xml mult_013.v common 6.95 vpr 64.32 MiB 0.03 7300 -1 -1 1 0.04 -1 -1 33588 -1 -1 25 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65864 32 32 386 305 1 240 89 17 17 289 -1 unnamed_device 25.5 MiB 1.78 1132 13751 4297 6849 2605 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66144 32 32 383 303 1 236 89 17 17 289 -1 unnamed_device 25.8 MiB 1.69 1195 12959 3577 7748 1634 64.6 MiB 0.11 0.00 3.72345 -132.536 -3.72345 3.72345 0.91 0.000241694 0.000193082 0.0186371 0.0150399 -1 -1 -1 -1 34 2729 22 6.89349e+06 352346 618332. 2139.56 1.49 0.0838167 0.0690827 25762 151098 -1 2362 21 1803 2277 162810 37088 2.94846 2.94846 -122.186 -2.94846 0 0 787024. 2723.27 0.30 0.05 0.13 -1 -1 0.30 0.0142159 0.0123128 160 57 64 32 56 32 -fixed_k6_frac_uripple_N8_22nm.xml mult_018.v common 7.96 vpr 64.31 MiB 0.02 7200 -1 -1 1 0.03 -1 -1 33964 -1 -1 22 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 339 284 1 224 86 17 17 289 -1 unnamed_device 25.2 MiB 3.05 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65636 32 32 283 225 1 168 80 17 17 289 -1 unnamed_device 25.2 MiB 1.79 856 14700 5411 7261 2028 64.1 MiB 0.10 0.00 3.66161 -130.921 -3.66161 3.66161 0.87 0.000177824 0.000140661 0.0168182 0.0135649 -1 -1 -1 -1 34 2177 21 6.89349e+06 225501 618332. 2139.56 1.52 0.0675572 0.0561074 25762 151098 -1 1897 21 1382 2387 171811 37083 2.92106 2.92106 -127.327 -2.92106 0 0 787024. 2723.27 0.30 0.05 0.13 -1 -1 0.30 0.0116462 0.010097 114 3 96 32 0 0 -fixed_k6_frac_uripple_N8_22nm.xml mult_033.v common 6.93 vpr 64.16 MiB 0.02 7136 -1 -1 1 0.04 -1 -1 34188 -1 -1 19 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65696 31 32 303 249 1 191 82 17 17 289 -1 unnamed_device 25.4 MiB 2.19 976 14322 4714 7465 2143 64.2 MiB 0.10 0.00 3.81397 -130.472 -3.81397 3.81397 0.89 0.000185833 0.000146275 0.0165877 0.0133433 -1 -1 -1 -1 34 2278 30 6.89349e+06 267783 618332. 2139.56 1.47 0.0699933 0.0576751 25762 151098 -1 1938 21 1186 1746 114542 27145 2.89006 2.89006 -118.505 -2.89006 0 0 787024. 2723.27 0.30 0.04 0.14 -1 -1 0.30 0.0117794 0.0102476 121 34 61 31 31 31 -fixed_k6_frac_uripple_N8_22nm.xml mult_034.v common 7.02 vpr 64.14 MiB 0.02 7108 -1 -1 1 0.03 -1 -1 33872 -1 -1 23 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65676 29 32 312 264 1 201 84 17 17 289 -1 unnamed_device 25.4 MiB 2.44 1053 14724 4750 7690 2284 64.1 MiB 0.10 0.00 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65936 31 32 391 309 1 246 89 17 17 289 -1 unnamed_device 25.5 MiB 3.41 1248 13157 3309 8741 1107 64.4 MiB 0.11 0.00 4.45339 -147.016 -4.45339 4.45339 0.89 0.000221631 0.000175109 0.0167085 0.0134795 -1 -1 -1 -1 34 3100 24 6.89349e+06 366440 618332. 2139.56 1.58 0.0825087 0.0681385 25762 151098 -1 2555 19 1713 2442 149720 36465 3.8506 3.8506 -145.517 -3.8506 0 0 787024. 2723.27 0.32 0.05 0.13 -1 -1 0.32 0.0134436 0.0116491 170 64 60 30 62 31 -fixed_k6_frac_uripple_N8_22nm.xml mult_039.v common 8.35 vpr 64.84 MiB 0.02 7372 -1 -1 1 0.04 -1 -1 34396 -1 -1 31 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66396 31 32 455 371 1 307 94 17 17 289 -1 unnamed_device 25.8 MiB 3.03 1502 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66324 32 32 424 343 1 279 92 17 17 289 -1 unnamed_device 25.7 MiB 2.53 1256 18722 6037 9946 2739 64.8 MiB 0.14 0.00 4.28929 -144.626 -4.28929 4.28929 0.87 0.000236379 0.000186303 0.0236777 0.0189259 -1 -1 -1 -1 34 3110 23 6.89349e+06 394628 618332. 2139.56 1.42 0.0732182 0.0599722 25762 151098 -1 2659 20 1783 2122 143790 34717 3.2992 3.2992 -130.444 -3.2992 0 0 787024. 2723.27 0.30 0.05 0.13 -1 -1 0.30 0.0143469 0.0124184 185 96 25 25 96 32 -fixed_k6_frac_uripple_N8_22nm.xml mult_049.v common 8.26 vpr 64.65 MiB 0.02 7304 -1 -1 1 0.04 -1 -1 33872 -1 -1 27 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66204 32 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66352 31 32 449 367 1 300 94 17 17 289 -1 unnamed_device 25.9 MiB 2.63 1470 18625 5645 10509 2471 64.8 MiB 0.15 0.00 5.04279 -156.823 -5.04279 5.04279 0.87 0.00024531 0.000193161 0.0235858 0.0188101 -1 -1 -1 -1 34 3368 47 6.89349e+06 436909 618332. 2139.56 1.54 0.101234 0.0823807 25762 151098 -1 2690 20 1877 2226 151581 35363 3.93725 3.93725 -140.668 -3.93725 0 0 787024. 2723.27 0.32 0.05 0.14 -1 -1 0.32 0.015561 0.0135352 195 122 0 0 122 31 -fixed_k6_frac_uripple_N8_22nm.xml mult_054.v common 8.42 vpr 64.53 MiB 0.04 7264 -1 -1 1 0.04 -1 -1 34152 -1 -1 27 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66076 32 32 432 346 1 287 91 17 17 289 -1 unnamed_device 25.7 MiB 3.64 1477 9271 2383 5997 891 64.5 MiB 0.09 0.00 4.63225 -158.944 -4.63225 4.63225 0.89 0.000249436 0.000200627 0.0133427 0.0108658 -1 -1 -1 -1 34 3600 35 6.89349e+06 380534 618332. 2139.56 1.65 0.0826916 0.0675099 25762 151098 -1 2976 22 2460 3565 232523 53347 4.18666 4.18666 -156.524 -4.18666 0 0 787024. 2723.27 0.30 0.07 0.13 -1 -1 0.30 0.0156711 0.0134989 190 94 32 32 94 32 -fixed_k6_frac_uripple_N8_22nm.xml mult_055.v common 6.98 vpr 64.24 MiB 0.02 7044 -1 -1 1 0.03 -1 -1 34028 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65784 32 32 312 255 1 198 85 17 17 289 -1 unnamed_device 25.5 MiB 2.33 1085 16081 5241 8837 2003 64.2 MiB 0.11 0.00 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65936 32 32 407 319 1 264 90 17 17 289 -1 unnamed_device 25.5 MiB 2.93 1381 17577 5400 9797 2380 64.4 MiB 0.15 0.00 5.10907 -172.718 -5.10907 5.10907 0.89 0.000278374 0.000227814 0.0226901 0.0182244 -1 -1 -1 -1 34 3492 23 6.89349e+06 366440 618332. 2139.56 1.78 0.0934945 0.0775943 25762 151098 -1 2788 20 2119 3010 209008 45498 4.43325 4.43325 -167.168 -4.43325 0 0 787024. 2723.27 0.30 0.07 0.13 -1 -1 0.30 0.0167258 0.0145877 177 65 64 32 64 32 -fixed_k6_frac_uripple_N8_22nm.xml mult_085.v common 8.04 vpr 64.26 MiB 0.02 7372 -1 -1 1 0.04 -1 -1 33920 -1 -1 30 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65800 29 32 387 316 1 251 91 17 17 289 -1 unnamed_device 25.6 MiB 3.34 1289 17431 5289 9749 2393 64.3 MiB 0.13 0.00 4.47765 -137.075 -4.47765 4.47765 0.86 0.000211644 0.000167397 0.0205212 0.0164853 -1 -1 -1 -1 34 2899 29 6.89349e+06 422815 618332. 2139.56 1.47 0.0793412 0.0646242 25762 151098 -1 2542 19 1652 2288 151389 34203 3.3997 3.3997 -122.825 -3.3997 0 0 787024. 2723.27 0.31 0.05 0.13 -1 -1 0.31 0.0144247 0.012619 170 88 26 26 85 29 -fixed_k6_frac_uripple_N8_22nm.xml mult_086.v common 5.86 vpr 63.96 MiB 0.02 7020 -1 -1 1 0.04 -1 -1 34084 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65500 32 32 283 225 1 168 80 17 17 289 -1 unnamed_device 25.1 MiB 1.15 883 14872 4496 9235 1141 64.0 MiB 0.10 0.00 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65336 31 32 275 220 1 164 80 17 17 289 -1 unnamed_device 25.1 MiB 1.46 719 6444 1413 4474 557 63.8 MiB 0.06 0.00 3.59935 -121.473 -3.59935 3.59935 0.90 0.000172294 0.00013625 0.00813888 0.00664648 -1 -1 -1 -1 28 2235 20 6.89349e+06 239595 531479. 1839.03 0.98 0.0380221 0.0316999 24610 126494 -1 1909 20 1424 2243 170016 39128 3.12946 3.12946 -127.906 -3.12946 0 0 648988. 2245.63 0.26 0.05 0.11 -1 -1 0.26 0.0111476 0.00966853 112 4 93 31 0 0 -fixed_k6_frac_uripple_N8_22nm.xml mult_091.v common 7.04 vpr 64.33 MiB 0.02 7076 -1 -1 1 0.04 -1 -1 33796 -1 -1 25 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65872 32 32 381 303 1 240 89 17 17 289 -1 unnamed_device 25.5 MiB 2.20 1298 18107 5148 10871 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65312 29 32 367 293 1 231 87 17 17 289 -1 unnamed_device 25.0 MiB 2.57 1165 15639 4840 8583 2216 63.8 MiB 0.12 0.00 3.69045 -118.464 -3.69045 3.69045 0.90 0.000206669 0.000163271 0.0189307 0.0151556 -1 -1 -1 -1 30 2493 21 6.89349e+06 366440 556674. 1926.21 0.94 0.0573164 0.0475628 25186 138497 -1 2048 22 1565 2117 122502 28169 2.97676 2.97676 -113.932 -2.97676 0 0 706193. 2443.58 0.28 0.04 0.12 -1 -1 0.28 0.0135679 0.0117437 157 62 56 29 58 29 -fixed_k6_frac_uripple_N8_22nm.xml mult_117.v common 9.16 vpr 64.58 MiB 0.03 7488 -1 -1 1 0.05 -1 -1 34048 -1 -1 29 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66132 32 32 469 381 1 315 93 17 17 289 -1 unnamed_device 25.7 MiB 2.65 1517 16893 4853 9389 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x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 401 316 1 253 89 17 17 289 -1 unnamed_device 25.6 MiB 2.66 1223 15335 4617 8313 2405 64.5 MiB 0.13 0.00 3.74935 -130.887 -3.74935 3.74935 0.87 0.000224967 0.000178303 0.0201438 0.016268 -1 -1 -1 -1 34 2949 22 6.89349e+06 352346 618332. 2139.56 1.68 0.0925099 0.0771385 25762 151098 -1 2455 21 1607 2192 170274 37420 3.1004 3.1004 -127.579 -3.1004 0 0 787024. 2723.27 0.32 0.06 0.13 -1 -1 0.32 0.0156903 0.0135711 170 65 61 32 64 32 -fixed_k6_frac_uripple_N8_22nm.xml mult_122.v common 8.12 vpr 63.69 MiB 0.03 7444 -1 -1 1 0.04 -1 -1 34380 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65216 32 32 500 382 1 323 97 17 17 289 -1 unnamed_device 24.9 MiB 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0.0532119 0.0438963 25762 151098 -1 1575 16 677 697 55663 12945 2.31406 2.31406 -91.2888 -2.31406 0 0 787024. 2723.27 0.32 0.03 0.13 -1 -1 0.32 0.00820774 0.00718987 93 56 0 0 53 30 -fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 6.65 vpr 62.88 MiB 0.03 6984 -1 -1 1 0.05 -1 -1 33864 -1 -1 21 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64392 30 32 296 244 1 181 83 17 17 289 -1 unnamed_device 23.9 MiB 1.95 936 13763 4424 7248 2091 62.9 MiB 0.09 0.00 4.23979 -138.455 -4.23979 4.23979 0.88 0.000176156 0.000139181 0.0152404 0.0122558 -1 -1 -1 -1 34 2069 19 6.89349e+06 295971 618332. 2139.56 1.39 0.0610836 0.0501228 25762 151098 -1 1752 19 1387 2094 145324 33469 3.41345 3.41345 -131.279 -3.41345 0 0 787024. 2723.27 0.32 0.05 0.14 -1 -1 0.32 0.013382 0.0118796 124 34 60 30 30 30 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9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65140 25 32 251 214 1 162 81 17 17 289 -1 unnamed_device 25.1 MiB 1.69 638 13031 3446 7568 2017 63.6 MiB 0.08 0.00 3.8441 -98.0419 -3.8441 3.8441 0.91 0.000148241 0.000116908 0.0124021 0.00993332 -1 -1 -1 -1 34 1735 20 6.89349e+06 338252 618332. 2139.56 1.35 0.0530287 0.0433486 25762 151098 -1 1462 18 873 1225 71875 17963 3.18111 3.18111 -99.3117 -3.18111 0 0 787024. 2723.27 0.32 0.03 0.13 -1 -1 0.32 0.0093407 0.00808074 107 34 50 25 25 25 -fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 8.87 vpr 64.67 MiB 0.03 7260 -1 -1 1 0.06 -1 -1 34164 -1 -1 28 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66224 32 32 432 346 1 288 92 17 17 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placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64416 32 32 302 334 1 209 106 17 17 289 -1 unnamed_device 23.9 MiB 0.15 1516 10356 2279 7365 712 62.9 MiB 0.11 0.00 8.73986 -179.719 -8.73986 8.73986 0.36 0.000983572 0.000910051 0.044446 0.0411316 -1 -1 -1 -1 28 4246 29 6.55708e+06 506310 500653. 1732.36 0.99 0.181894 0.159405 21310 115450 -1 3245 18 1360 4616 242551 59872 7.65802 7.65802 -173.385 -7.65802 0 0 612192. 2118.31 0.03 0.09 0.10 -1 -1 0.03 0.0374401 0.0328965 216 208 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_015.v common 2.55 vpr 63.25 MiB 0.04 6640 -1 -1 11 0.20 -1 -1 32412 -1 -1 36 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 29 32 238 270 1 177 97 17 17 289 -1 unnamed_device 23.5 MiB 0.12 1173 9865 2533 6304 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64552 32 32 383 303 1 185 102 17 17 289 -1 unnamed_device 24.2 MiB 0.10 1120 15810 4601 9118 2091 63.0 MiB 0.16 0.00 3.5171 -123.44 -3.5171 3.5171 0.31 0.000745322 0.000691087 0.0520892 0.0482761 -1 -1 -1 -1 30 2224 21 6.64007e+06 477204 526063. 1820.29 1.40 0.217198 0.188922 22546 126617 -1 1939 16 1189 1826 115145 26469 3.00017 3.00017 -120.351 -3.00017 0 0 666494. 2306.21 0.03 0.08 0.10 -1 -1 0.03 0.0323529 0.0282406 146 57 64 32 56 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 2.45 vpr 62.86 MiB 0.03 6980 -1 -1 1 0.05 -1 -1 30104 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64372 32 32 339 284 1 162 99 17 17 289 -1 unnamed_device 23.8 MiB 0.11 968 16515 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64484 32 32 337 253 1 196 105 17 17 289 -1 unnamed_device 23.8 MiB 0.07 950 11961 2772 8489 700 63.0 MiB 0.13 0.00 3.50507 -117.309 -3.50507 3.50507 0.32 0.000697058 0.000646752 0.0361771 0.0334978 -1 -1 -1 -1 32 2114 18 6.64007e+06 514878 554710. 1919.41 1.46 0.235517 0.20326 22834 132086 -1 1863 23 1437 2509 146808 35996 2.78877 2.78877 -112.501 -2.78877 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.030771 0.0267278 156 3 124 32 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 2.58 vpr 63.36 MiB 0.05 7112 -1 -1 1 0.03 -1 -1 30600 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64880 32 32 407 319 1 197 104 17 17 289 -1 unnamed_device 24.4 MiB 0.08 1130 17184 5737 8837 2610 63.4 MiB 0.18 0.00 4.23656 -144.814 -4.23656 4.23656 0.31 0.000767369 0.000711388 0.0569018 0.0527002 -1 -1 -1 -1 32 2274 22 6.64007e+06 502320 554710. 1919.41 0.60 0.147862 0.130636 22834 132086 -1 1992 23 1622 2800 148797 36507 3.81983 3.81983 -142.34 -3.81983 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0334645 0.0290941 157 65 64 32 64 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 3.00 vpr 62.83 MiB 0.04 6916 -1 -1 1 0.03 -1 -1 30204 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64336 32 32 294 246 1 149 82 17 17 289 -1 unnamed_device 23.7 MiB 0.07 840 8270 2111 5830 329 62.8 MiB 0.09 0.00 3.06579 -105.423 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64860 31 32 303 249 1 162 101 17 17 289 -1 unnamed_device 23.6 MiB 0.07 862 11146 2592 7979 575 63.3 MiB 0.11 0.00 3.50687 -115.397 -3.50687 3.50687 0.31 0.000633728 0.000589298 0.0320851 0.0298131 -1 -1 -1 -1 26 2499 26 6.64007e+06 477204 477104. 1650.88 1.95 0.183781 0.15873 21682 110474 -1 1865 22 1267 2178 125582 31798 2.91577 2.91577 -114.15 -2.91577 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0264303 0.0229425 125 34 61 31 31 31 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 2.52 vpr 62.75 MiB 0.04 7028 -1 -1 1 0.03 -1 -1 30052 -1 -1 37 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64260 29 32 312 264 1 154 98 17 17 289 -1 unnamed_device 23.6 MiB 0.11 922 17198 5894 8996 2308 62.8 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 31 32 391 309 1 194 89 17 17 289 -1 unnamed_device 24.2 MiB 0.08 1079 9197 2284 6348 565 63.1 MiB 0.06 0.00 3.55147 -118.528 -3.55147 3.55147 0.24 0.000335013 0.000306723 0.0173535 0.0159879 -1 -1 -1 -1 32 2150 20 6.64007e+06 326508 554710. 1919.41 1.35 0.199218 0.170874 22834 132086 -1 1941 23 1473 2493 142325 34910 2.90497 2.90497 -115.356 -2.90497 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0327757 0.0285415 155 64 60 30 62 31 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 2.85 vpr 63.93 MiB 0.05 7300 -1 -1 1 0.03 -1 -1 30632 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65460 31 32 455 371 1 192 88 17 17 289 -1 unnamed_device 24.2 MiB 0.29 1002 14908 5470 7356 2082 63.9 MiB 0.17 0.00 4.45513 -137.3 -4.45513 4.45513 0.31 0.000834144 0.000775325 0.066533 0.0618773 -1 -1 -1 -1 32 2284 27 6.64007e+06 313950 554710. 1919.41 0.61 0.170249 0.150289 22834 132086 -1 1941 20 1342 2354 134944 33685 3.86483 3.86483 -138.007 -3.86483 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0326114 0.0283482 154 124 0 0 124 31 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 3.45 vpr 63.17 MiB 0.05 7124 -1 -1 1 0.03 -1 -1 30416 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64688 31 32 413 333 1 186 88 17 17 289 -1 unnamed_device 24.2 MiB 0.13 1027 11398 2983 7528 887 63.2 MiB 0.13 0.00 4.38913 -134.67 -4.38913 4.38913 0.34 0.000766712 0.000712184 0.0477711 0.0443788 -1 -1 -1 -1 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65224 32 32 395 311 1 194 106 17 17 289 -1 unnamed_device 24.1 MiB 0.14 1140 12606 3075 8755 776 63.7 MiB 0.14 0.00 3.50687 -121.034 -3.50687 3.50687 0.31 0.000763907 0.000708181 0.0411347 0.0381036 -1 -1 -1 -1 26 2863 33 6.64007e+06 527436 477104. 1650.88 1.46 0.241988 0.209195 21682 110474 -1 2394 20 1602 2796 167314 41417 2.85057 2.85057 -121.098 -2.85057 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0296906 0.0258573 153 61 64 32 60 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.63 vpr 63.01 MiB 0.05 7140 -1 -1 1 0.03 -1 -1 30420 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64524 32 32 405 318 1 200 105 17 17 289 -1 unnamed_device 24.0 MiB 0.12 1167 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 32 32 432 346 1 195 89 17 17 289 -1 unnamed_device 24.2 MiB 0.11 1141 15731 4718 8920 2093 63.2 MiB 0.17 0.00 4.14856 -139.91 -4.14856 4.14856 0.32 0.000810138 0.000744827 0.0667672 0.06186 -1 -1 -1 -1 32 2582 17 6.64007e+06 313950 554710. 1919.41 0.58 0.155449 0.137753 22834 132086 -1 2286 22 1613 2975 171935 42030 3.41023 3.41023 -130.66 -3.41023 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0341772 0.0297611 155 94 32 32 94 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 3.34 vpr 62.84 MiB 0.04 6808 -1 -1 1 0.03 -1 -1 30652 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64344 32 32 312 255 1 166 100 17 17 289 -1 unnamed_device 23.8 MiB 0.07 978 17964 4790 11291 1883 62.8 MiB 0.16 0.00 3.50687 -123.607 -3.50687 3.50687 0.31 0.000634391 0.000590427 0.0516727 0.0479857 -1 -1 -1 -1 32 2015 21 6.64007e+06 452088 554710. 1919.41 1.42 0.236854 0.20544 22834 132086 -1 1764 19 1043 1706 104857 24083 2.70957 2.70957 -114.861 -2.70957 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0239623 0.0208695 128 34 63 32 32 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 3.34 vpr 62.99 MiB 0.04 6944 -1 -1 1 0.03 -1 -1 30408 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64504 32 32 370 314 1 164 86 17 17 289 -1 unnamed_device 24.0 MiB 0.14 959 13694 3826 7953 1915 63.0 MiB 0.14 0.00 3.5031 -123.294 -3.5031 3.5031 0.31 0.000703797 0.000653041 0.0533381 0.0495388 -1 -1 -1 -1 32 2054 22 6.64007e+06 276276 554710. 1919.41 1.44 0.254834 0.220755 22834 132086 -1 1866 21 1185 1986 135253 31237 2.75177 2.75177 -114.926 -2.75177 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0284481 0.0247206 125 94 0 0 94 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 3.82 vpr 63.67 MiB 0.05 7264 -1 -1 1 0.03 -1 -1 30804 -1 -1 45 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65200 32 32 469 351 1 233 109 17 17 289 -1 unnamed_device 24.7 MiB 0.11 1361 11809 2725 8268 816 63.7 MiB 0.15 0.00 4.90898 -166.187 -4.90898 4.90898 0.31 0.000882608 0.000821324 0.0432573 0.0401574 -1 -1 -1 -1 26 3708 29 6.64007e+06 565110 477104. 1650.88 1.78 0.258756 0.223516 21682 110474 -1 2936 24 2542 4529 290190 66859 5.02189 5.02189 -184.485 -5.02189 0 0 585099. 2024.56 0.03 0.11 0.09 -1 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65336 32 32 406 330 1 190 102 17 17 289 -1 unnamed_device 24.2 MiB 0.10 992 12478 2933 7679 1866 63.8 MiB 0.11 0.00 4.52516 -135.426 -4.52516 4.52516 0.31 0.000756476 0.000701792 0.0423415 0.0392551 -1 -1 -1 -1 32 2451 20 6.64007e+06 477204 554710. 1919.41 1.84 0.267131 0.230443 22834 132086 -1 2005 18 1132 1883 102007 26645 3.80383 3.80383 -135.287 -3.80383 0 0 701300. 2426.64 0.05 0.07 0.13 -1 -1 0.05 0.0322026 0.0285569 147 88 28 28 88 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 2.57 vpr 63.09 MiB 0.03 7060 -1 -1 1 0.03 -1 -1 30500 -1 -1 44 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 32 32 399 285 1 228 108 17 17 289 -1 unnamed_device 24.3 MiB 0.07 1325 21182 6964 11671 2547 63.1 MiB 0.22 0.00 4.95022 -163.573 -4.95022 4.95022 0.31 0.000790751 0.000734727 0.0682016 0.0632932 -1 -1 -1 -1 32 2976 22 6.64007e+06 552552 554710. 1919.41 0.61 0.162701 0.144613 22834 132086 -1 2375 21 1636 2775 149856 36568 4.28689 4.28689 -157.468 -4.28689 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0331594 0.0290767 185 3 156 32 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 3.63 vpr 63.01 MiB 0.03 7056 -1 -1 1 0.03 -1 -1 30692 -1 -1 39 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64520 30 32 371 295 1 184 101 17 17 289 -1 unnamed_device 24.1 MiB 0.11 895 17726 5089 8956 3681 63.0 MiB 0.16 0.00 3.59647 -113.455 -3.59647 3.59647 0.32 0.000721907 0.000670482 0.0566287 0.0524999 -1 -1 -1 -1 28 2294 25 6.64007e+06 489762 500653. 1732.36 1.75 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64340 32 32 314 256 1 160 84 17 17 289 -1 unnamed_device 23.7 MiB 0.12 754 13077 3934 6633 2510 62.8 MiB 0.13 0.00 3.59624 -121.098 -3.59624 3.59624 0.31 0.000646421 0.000601399 0.0484737 0.0450874 -1 -1 -1 -1 32 2005 24 6.64007e+06 251160 554710. 1919.41 0.61 0.127184 0.112426 22834 132086 -1 1579 21 1361 2245 147119 38033 2.94077 2.94077 -118.328 -2.94077 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0264705 0.0230795 121 34 64 32 32 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 2.41 vpr 63.13 MiB 0.05 7172 -1 -1 1 0.03 -1 -1 30468 -1 -1 41 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 31 32 387 307 1 189 104 17 17 289 -1 unnamed_device 24.2 MiB 0.13 1070 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64328 30 32 296 244 1 137 80 17 17 289 -1 unnamed_device 23.7 MiB 0.06 686 13152 4141 7190 1821 62.8 MiB 0.14 0.00 3.45727 -110.065 -3.45727 3.45727 0.33 0.000612305 0.000569631 0.0564435 0.0523904 -1 -1 -1 -1 30 1478 23 6.64007e+06 226044 526063. 1820.29 1.01 0.197261 0.17187 22546 126617 -1 1314 19 848 1353 76955 18874 2.64537 2.64537 -102.521 -2.64537 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0232706 0.0202247 100 34 60 30 30 30 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 3.11 vpr 62.86 MiB 0.03 6776 -1 -1 1 0.03 -1 -1 30180 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64364 32 32 314 256 1 167 85 17 17 289 -1 unnamed_device 23.7 MiB 0.08 858 10873 2510 6865 1498 62.9 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64504 32 32 438 350 1 194 102 17 17 289 -1 unnamed_device 24.2 MiB 0.07 979 11288 2565 7046 1677 63.0 MiB 0.11 0.00 4.02833 -135.774 -4.02833 4.02833 0.31 0.000825015 0.000758332 0.0423022 0.0391608 -1 -1 -1 -1 30 2738 22 6.65987e+06 481764 526063. 1820.29 2.54 0.245848 0.213121 22546 126617 -1 1963 23 1686 2764 149139 37885 3.32871 3.32871 -131.231 -3.32871 0 0 666494. 2306.21 0.03 0.08 0.10 -1 -1 0.03 0.0359753 0.0313491 154 96 32 32 96 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 2.51 vpr 62.99 MiB 0.05 7160 -1 -1 1 0.03 -1 -1 30780 -1 -1 26 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64396 31 32 353 302 1 156 97 17 17 289 -1 unnamed_device 23.8 MiB 0.11 797 10753 2302 7921 530 62.9 MiB 0.11 0.00 3.28032 -107.646 -3.28032 3.28032 0.31 0.000689833 0.000634337 0.0363116 0.0336729 -1 -1 -1 -1 26 2397 31 6.65987e+06 431052 477104. 1650.88 0.97 0.12993 0.113818 21682 110474 -1 1782 22 1184 1981 146390 37209 2.87265 2.87265 -111.394 -2.87265 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.028321 0.0246033 117 90 0 0 89 31 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 2.52 vpr 62.88 MiB 0.04 7188 -1 -1 1 0.03 -1 -1 30372 -1 -1 26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65064 32 32 496 380 1 232 111 17 17 289 -1 unnamed_device 24.6 MiB 0.12 1279 19795 5512 12343 1940 63.5 MiB 0.21 0.00 4.1355 -142.457 -4.1355 4.1355 0.31 0.00091285 0.000844831 0.0714664 0.0662515 -1 -1 -1 -1 28 3135 37 6.65987e+06 595866 500653. 1732.36 1.76 0.32821 0.284568 21970 115934 -1 2553 20 1888 3079 188802 46009 3.50797 3.50797 -140.761 -3.50797 0 0 612192. 2118.31 0.03 0.09 0.10 -1 -1 0.03 0.0367567 0.0321191 190 96 62 32 96 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.39 vpr 62.62 MiB 0.05 6916 -1 -1 1 0.03 -1 -1 30488 -1 -1 20 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 32 32 395 311 1 194 106 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1147 12856 3159 9034 663 62.8 MiB 0.14 0.00 3.5401 -122.035 -3.5401 3.5401 0.31 0.000764599 0.000710168 0.0417941 0.0387737 -1 -1 -1 -1 28 2774 48 6.65987e+06 532476 500653. 1732.36 1.51 0.264529 0.228282 21970 115934 -1 2432 20 1563 2666 179161 43958 2.82857 2.82857 -120.753 -2.82857 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0299698 0.0261885 153 61 64 32 60 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.60 vpr 63.67 MiB 0.04 7124 -1 -1 1 0.03 -1 -1 30452 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64848 32 32 312 255 1 166 100 17 17 289 -1 unnamed_device 23.7 MiB 0.06 948 13092 3333 8859 900 63.3 MiB 0.12 0.00 3.35364 -114.677 -3.35364 3.35364 0.31 0.000641139 0.00059719 0.0388568 0.036055 -1 -1 -1 -1 30 2033 20 6.65987e+06 456408 526063. 1820.29 1.38 0.201509 0.174371 22546 126617 -1 1762 20 1100 1830 102561 24771 2.56705 2.56705 -108.258 -2.56705 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0251041 0.0218944 128 34 63 32 32 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 2.38 vpr 62.81 MiB 0.04 7024 -1 -1 1 0.03 -1 -1 30456 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64352 32 32 381 303 1 188 103 17 17 289 -1 unnamed_device 24.0 MiB 0.11 1076 14081 3693 8945 1443 62.8 MiB 0.14 0.00 3.93641 -131.645 -3.93641 3.93641 0.31 0.000742196 0.000690054 0.0458873 0.0426023 -1 -1 -1 -1 26 2525 22 6.65987e+06 494442 477104. 1650.88 0.62 0.133849 0.118097 21682 110474 -1 2205 23 1606 2318 148974 36221 3.64751 3.64751 -134.105 -3.64751 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0330027 0.0287536 145 59 60 32 58 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 2.90 vpr 63.58 MiB 0.05 7300 -1 -1 1 0.03 -1 -1 30472 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65164 32 32 405 318 1 200 108 17 17 289 -1 unnamed_device 24.2 MiB 0.12 1090 19897 6114 10922 2861 63.6 MiB 0.20 0.00 3.47384 -119.153 -3.47384 3.47384 0.32 0.000776576 0.000721115 0.0625927 0.0580912 -1 -1 -1 -1 30 2598 21 6.65987e+06 557832 526063. 1820.29 1.92 0.283759 0.24621 22546 126617 -1 2057 17 1450 2297 149814 35496 2.74451 2.74451 -113.792 -2.74451 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0276725 0.0243033 160 65 63 32 64 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 2.29 vpr 62.52 MiB 0.05 7024 -1 -1 1 0.03 -1 -1 30404 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64476 31 32 387 307 1 189 104 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1073 15232 3616 10043 1573 63.0 MiB 0.15 0.00 3.5933 -121.502 -3.5933 3.5933 0.32 0.000747396 0.000694772 0.0492652 0.0457064 -1 -1 -1 -1 26 2279 27 6.65987e+06 519798 477104. 1650.88 0.55 0.144125 0.127084 21682 110474 -1 1906 21 1326 2088 126708 30754 2.79857 2.79857 -113.894 -2.79857 0 0 585099. 2024.56 0.02 0.07 0.09 -1 -1 0.02 0.030524 0.0266578 148 64 58 31 62 31 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 2.28 vpr 62.66 MiB 0.05 6964 -1 -1 1 0.03 -1 -1 30420 -1 -1 19 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64164 31 32 308 262 1 147 82 17 17 289 -1 unnamed_device 23.4 MiB 0.11 885 12008 3839 6318 1851 62.7 MiB 0.11 0.00 2.84661 -98.4293 -2.84661 2.84661 0.31 0.000631232 0.000580188 0.0443964 0.0411781 -1 -1 -1 -1 32 1706 22 6.65987e+06 240882 554710. 1919.41 0.52 0.118512 0.104417 22834 132086 -1 1554 22 956 1612 90325 22983 2.62945 2.62945 -101.745 -2.62945 0 0 701300. 2426.64 0.03 0.06 0.08 -1 -1 0.03 0.0263038 0.0228571 110 55 31 31 53 31 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 3.32 vpr 63.18 MiB 0.05 7124 -1 -1 1 0.03 -1 -1 30452 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64700 32 32 383 307 1 184 102 17 17 289 -1 unnamed_device 24.3 MiB 0.11 1058 13430 3540 9051 839 63.2 MiB 0.15 0.00 3.5071 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64340 32 32 407 319 1 198 105 17 17 289 -1 unnamed_device 23.9 MiB 0.11 1080 13937 3664 9212 1061 62.8 MiB 0.15 0.00 3.90984 -134.389 -3.90984 3.90984 0.32 0.000774896 0.000718761 0.046587 0.0431798 -1 -1 -1 -1 28 2591 22 6.65987e+06 519798 500653. 1732.36 0.58 0.139162 0.122734 21970 115934 -1 2361 23 2066 3170 201155 50958 3.71431 3.71431 -142.327 -3.71431 0 0 612192. 2118.31 0.03 0.09 0.10 -1 -1 0.03 0.0339076 0.0295498 158 65 64 32 64 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 2.43 vpr 62.95 MiB 0.05 7192 -1 -1 1 0.03 -1 -1 30504 -1 -1 42 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64460 29 32 367 293 1 183 103 17 17 289 -1 unnamed_device 24.0 MiB 0.10 1000 10948 2708 7481 759 62.9 MiB 0.12 0.00 3.44084 -105.052 -3.44084 3.44084 0.31 0.000707491 0.000658083 0.0347288 0.0322952 -1 -1 -1 -1 32 2041 21 6.65987e+06 532476 554710. 1919.41 0.51 0.118473 0.104115 22834 132086 -1 1850 22 1076 1623 88236 23321 2.81351 2.81351 -106.952 -2.81351 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0302869 0.0263862 144 62 56 29 58 29 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 3.38 vpr 63.86 MiB 0.05 7164 -1 -1 1 0.03 -1 -1 30712 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65392 32 32 469 381 1 200 105 17 17 289 -1 unnamed_device 24.3 MiB 0.16 1096 12949 3437 8756 756 63.9 MiB 0.15 0.00 3.95704 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1234 67713 18322 2.47851 2.47851 -94.3327 -2.47851 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0203558 0.017821 109 4 85 31 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 3.33 vpr 63.71 MiB 0.05 7176 -1 -1 1 0.03 -1 -1 30396 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65240 32 32 418 338 1 190 102 17 17 289 -1 unnamed_device 24.0 MiB 0.09 1066 12716 3370 8608 738 63.7 MiB 0.14 0.00 4.13067 -135.986 -4.13067 4.13067 0.31 0.000785204 0.000729403 0.0456023 0.0421972 -1 -1 -1 -1 26 2687 32 6.65987e+06 481764 477104. 1650.88 1.50 0.224839 0.194903 21682 110474 -1 2099 23 1423 2143 149237 39624 3.57017 3.57017 -136.957 -3.57017 0 0 585099. 2024.56 0.02 0.08 0.09 -1 -1 0.02 0.0345441 0.0301138 149 92 28 28 92 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 3.20 vpr 62.77 MiB 0.03 7040 -1 -1 1 0.03 -1 -1 30244 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64276 32 32 376 318 1 156 82 17 17 289 -1 unnamed_device 23.6 MiB 0.13 926 13254 4558 6661 2035 62.8 MiB 0.13 0.00 3.55944 -125.789 -3.55944 3.55944 0.31 0.000723045 0.000671323 0.0555964 0.051664 -1 -1 -1 -1 32 1849 23 6.65987e+06 228204 554710. 1919.41 1.41 0.231785 0.201204 22834 132086 -1 1667 17 1110 1612 89987 22309 3.08297 3.08297 -125.343 -3.08297 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0249941 0.0218771 117 96 0 0 96 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.55 vpr 62.93 MiB 0.04 7000 -1 -1 1 0.03 -1 -1 30328 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64436 32 32 401 316 1 196 103 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1003 19142 5741 10397 3004 62.9 MiB 0.18 0.00 3.45184 -118.245 -3.45184 3.45184 0.32 0.000773902 0.000719397 0.063688 0.059114 -1 -1 -1 -1 32 2291 21 6.65987e+06 494442 554710. 1919.41 0.57 0.154084 0.136793 22834 132086 -1 1862 20 1350 2010 115617 29443 2.74451 2.74451 -110.58 -2.74451 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0308957 0.0270872 156 65 61 32 64 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 3.04 vpr 63.47 MiB 0.05 7348 -1 -1 1 0.03 -1 -1 30736 -1 -1 47 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64996 32 32 500 382 1 232 111 17 17 289 -1 unnamed_device 24.4 MiB 0.15 1286 15273 3766 9701 1806 63.5 MiB 0.17 0.00 4.72967 -161.298 -4.72967 4.72967 0.31 0.000917339 0.000851608 0.0561514 0.0521487 -1 -1 -1 -1 26 3444 26 6.65987e+06 595866 477104. 1650.88 0.93 0.17674 0.155699 21682 110474 -1 2751 21 2134 3367 219700 52402 4.79157 4.79157 -170.054 -4.79157 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0383862 0.0335311 190 96 64 32 96 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 2.98 vpr 62.69 MiB 0.04 6768 -1 -1 1 0.03 -1 -1 30160 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 30 32 246 229 1 118 80 17 17 289 -1 unnamed_device 23.1 MiB 0.08 541 7132 1642 4789 701 62.7 MiB 0.06 0.00 2.58318 -78.5582 -2.58318 2.58318 0.31 0.00052899 0.000492666 0.0236053 0.0219854 -1 -1 -1 -1 28 1428 32 6.65987e+06 228204 500653. 1732.36 1.30 0.153014 0.131237 21970 115934 -1 1128 14 573 813 60927 17486 1.63745 1.63745 -72.3167 -1.63745 0 0 612192. 2118.31 0.03 0.04 0.10 -1 -1 0.03 0.0158565 0.0138448 86 56 0 0 53 30 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.34 vpr 62.70 MiB 0.04 6916 -1 -1 1 0.03 -1 -1 30448 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64204 30 32 296 244 1 137 80 17 17 289 -1 unnamed_device 23.6 MiB 0.11 646 13152 3617 7215 2320 62.7 MiB 0.11 0.00 3.30481 -102.112 -3.30481 3.30481 0.31 0.000613314 0.000570714 0.0492634 0.0458682 -1 -1 -1 -1 32 1416 19 6.65987e+06 228204 554710. 1919.41 0.50 0.11968 0.106111 22834 132086 -1 1271 19 886 1393 71493 19264 2.61931 2.61931 -98.109 -2.61931 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0249757 0.0218013 100 34 60 30 30 30 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 3.36 vpr 62.68 MiB 0.04 7004 -1 -1 1 0.03 -1 -1 29968 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64180 32 32 314 256 1 167 85 17 17 289 -1 unnamed_device 23.7 MiB 0.08 836 10501 2382 7608 511 62.7 MiB 0.12 0.00 3.4859 -120.54 -3.4859 3.4859 0.31 0.000647384 0.000602776 0.0387371 0.0360456 -1 -1 -1 -1 30 2335 26 6.65987e+06 266238 526063. 1820.29 1.53 0.193827 0.168222 22546 126617 -1 1805 21 1249 2212 113029 28883 2.82977 2.82977 -114.788 -2.82977 0 0 666494. 2306.21 0.03 0.07 0.11 -1 -1 0.03 0.0269704 0.0235565 128 34 64 32 32 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_126.v common 2.50 vpr 62.52 MiB 0.04 7028 -1 -1 1 0.03 -1 -1 30464 -1 -1 38 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64020 25 32 251 214 1 138 95 17 17 289 -1 unnamed_device 23.4 MiB 0.05 608 15647 3933 10514 1200 62.5 MiB 0.12 0.00 3.31961 -85.6713 -3.31961 3.31961 0.31 0.00053389 0.000496806 0.0406082 0.0376997 -1 -1 -1 -1 26 1766 37 6.65987e+06 481764 477104. 1650.88 0.73 0.115752 0.101381 21682 110474 -1 1384 19 913 1343 87909 24454 2.89271 2.89271 -92.8305 -2.89271 0 0 585099. 2024.56 0.02 0.05 0.09 -1 -1 0.02 0.0201672 0.0175079 106 34 50 25 25 25 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 2.60 vpr 62.96 MiB 0.05 7196 -1 -1 1 0.03 -1 -1 30440 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64472 32 32 432 346 1 193 88 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1105 16078 5546 8034 2498 63.0 MiB 0.18 0.00 3.74158 -129.005 -3.74158 3.74158 0.31 0.000801314 0.00074477 0.0691049 0.0642531 -1 -1 -1 -1 32 2457 23 6.65987e+06 304272 554710. 1919.41 0.59 0.16526 0.14669 22834 132086 -1 2140 21 1584 2875 173957 42583 3.17765 3.17765 -125.504 -3.17765 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0328779 0.0286287 153 94 32 32 94 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 3.24 vpr 62.98 MiB 0.05 7296 -1 -1 1 0.03 -1 -1 30324 -1 -1 44 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64496 31 32 421 339 1 193 107 17 17 289 -1 unnamed_device 24.2 MiB 0.07 1092 17817 4773 10666 2378 63.0 MiB 0.17 0.00 3.5303 -118.773 -3.5303 3.5303 0.31 0.000784783 0.000729218 0.058218 0.0538467 -1 -1 -1 -1 28 2470 22 6.65987e+06 557832 500653. 1732.36 1.36 0.256565 0.222613 21970 115934 -1 2103 22 1837 2937 176557 43306 2.92871 2.92871 -116.544 -2.92871 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0329991 0.028701 154 94 29 29 93 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_001.v common 9.05 vpr 64.44 MiB 0.05 7264 -1 -1 1 0.03 -1 -1 30504 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65984 32 32 438 350 1 187 93 17 17 289 -1 unnamed_device 24.7 MiB 0.60 1068 16053 5016 9033 2004 64.4 MiB 0.15 0.00 3.77239 -143.21 -3.77239 3.77239 0.33 0.000819121 0.000752752 0.0650966 0.0603673 -1 -1 -1 -1 42 2696 36 6.95648e+06 419795 744469. 2576.02 6.47 0.380974 0.328752 27202 183097 -1 2317 23 2077 3288 264441 53308 3.91596 3.91596 -150.502 -3.91596 0 0 949917. 3286.91 0.04 0.10 0.14 -1 -1 0.04 0.0355501 0.030934 88 96 32 32 96 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_002.v common 4.39 vpr 63.74 MiB 0.05 7196 -1 -1 1 0.03 -1 -1 30664 -1 -1 15 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65268 30 32 409 330 1 175 77 17 17 289 -1 unnamed_device 24.8 MiB 1.05 835 12954 5477 7070 407 63.7 MiB 0.13 0.00 3.62689 -126.78 -3.62689 3.62689 0.33 0.000766347 0.000712217 0.0631769 0.0587644 -1 -1 -1 -1 38 2711 25 6.95648e+06 217135 678818. 2348.85 1.37 0.214696 0.187849 26626 170182 -1 2106 22 1943 3061 242645 53045 4.32786 4.32786 -151.679 -4.32786 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64920 29 32 343 267 1 176 78 17 17 289 -1 unnamed_device 24.5 MiB 0.25 1061 10204 3275 5543 1386 63.4 MiB 0.10 0.00 3.62689 -130.249 -3.62689 3.62689 0.33 0.000680633 0.00063309 0.0445894 0.041492 -1 -1 -1 -1 38 2540 28 6.95648e+06 246087 678818. 2348.85 1.10 0.161726 0.141209 26626 170182 -1 2162 24 1970 3085 253782 52395 3.96316 3.96316 -142.395 -3.96316 0 0 902133. 3121.57 0.04 0.09 0.13 -1 -1 0.04 0.0314043 0.0273255 79 34 87 29 29 29 + fixed_k6_frac_2ripple_N8_22nm.xml mult_005.v common 8.03 vpr 64.37 MiB 0.05 6972 -1 -1 1 0.03 -1 -1 30376 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65916 32 32 376 288 1 187 78 17 17 289 -1 unnamed_device 24.8 MiB 0.35 822 11366 4732 6273 361 64.4 MiB 0.12 0.00 3.66789 -136.565 -3.66789 3.66789 0.33 0.000742769 0.000689984 0.0532242 0.0494887 -1 -1 -1 -1 48 2549 24 6.95648e+06 202660 865456. 2994.66 5.76 0.284945 0.24735 28354 207349 -1 2110 21 2098 3593 283256 62966 3.93316 3.93316 -149.175 -3.93316 0 0 1.05005e+06 3633.38 0.04 0.10 0.16 -1 -1 0.04 0.0314303 0.0275526 79 34 96 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_006.v common 5.73 vpr 63.63 MiB 0.05 7140 -1 -1 1 0.03 -1 -1 30420 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65160 32 32 402 316 1 191 97 17 17 289 -1 unnamed_device 24.7 MiB 0.18 1077 14305 4216 7787 2302 63.6 MiB 0.12 0.00 3.01863 -119.444 -3.01863 3.01863 0.33 0.000765737 0.000708851 0.0521861 0.0483024 -1 -1 -1 -1 36 2784 41 6.95648e+06 477698 648988. 2245.63 3.67 0.310116 0.26763 26050 158493 -1 2431 19 1558 2270 202731 44402 3.16582 3.16582 -131.286 -3.16582 0 0 828058. 2865.25 0.03 0.08 0.13 -1 -1 0.03 0.0291793 0.0255119 93 64 63 32 63 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_007.v common 5.46 vpr 63.79 MiB 0.04 6936 -1 -1 1 0.03 -1 -1 30592 -1 -1 14 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65324 27 32 269 226 1 128 73 17 17 289 -1 unnamed_device 24.4 MiB 2.29 577 8129 3070 3829 1230 63.8 MiB 0.07 0.00 2.81185 -90.4167 -2.81185 2.81185 0.33 0.000567839 0.000528502 0.0325119 0.0302887 -1 -1 -1 -1 38 1395 35 6.95648e+06 202660 678818. 2348.85 1.37 0.158645 0.137322 26626 170182 -1 1153 18 916 1438 84006 20348 2.83942 2.83942 -96.2616 -2.83942 0 0 902133. 3121.57 0.03 0.05 0.14 -1 -1 0.03 0.0213373 0.0186289 56 34 54 27 27 27 + fixed_k6_frac_2ripple_N8_22nm.xml mult_008.v common 10.13 vpr 63.84 MiB 0.04 7012 -1 -1 1 0.03 -1 -1 30192 -1 -1 30 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65368 31 32 317 242 1 178 93 17 17 289 -1 unnamed_device 24.9 MiB 0.17 1057 11013 2654 7318 1041 63.8 MiB 0.10 0.00 2.9463 -110.957 -2.9463 2.9463 0.33 0.00067038 0.000621405 0.0371103 0.0345043 -1 -1 -1 -1 40 2428 25 6.95648e+06 434271 706193. 2443.58 8.04 0.307828 0.264922 26914 176310 -1 2119 24 1315 2149 186842 48456 3.20912 3.20912 -122.667 -3.20912 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0301775 0.0262335 85 4 115 31 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml mult_009.v common 4.83 vpr 63.58 MiB 0.05 7020 -1 -1 1 0.03 -1 -1 30152 -1 -1 12 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65104 31 32 338 292 1 142 75 17 17 289 -1 unnamed_device 24.6 MiB 0.83 586 8449 2574 4566 1309 63.6 MiB 0.08 0.00 2.81185 -97.8774 -2.81185 2.81185 0.33 0.000668743 0.000621811 0.0381379 0.0354913 -1 -1 -1 -1 44 1586 30 6.95648e+06 173708 787024. 2723.27 2.17 0.237151 0.20446 27778 195446 -1 1104 20 825 1227 84252 23016 2.94562 2.94562 -102.672 -2.94562 0 0 997811. 3452.63 0.04 0.06 0.16 -1 -1 0.04 0.0263065 0.0229401 57 85 0 0 84 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_010.v common 4.82 vpr 63.41 MiB 0.05 6848 -1 -1 1 0.03 -1 -1 30272 -1 -1 11 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64936 32 32 314 256 1 156 75 17 17 289 -1 unnamed_device 24.3 MiB 0.79 627 9871 4078 5538 255 63.4 MiB 0.10 0.00 2.97205 -115.921 -2.97205 2.97205 0.34 0.000647028 0.0006013 0.0438341 0.0408459 -1 -1 -1 -1 42 1803 27 6.95648e+06 159232 744469. 2576.02 2.15 0.268233 0.23105 27202 183097 -1 1493 23 1574 2212 156517 37213 2.93652 2.93652 -121.97 -2.93652 0 0 949917. 3286.91 0.04 0.07 0.14 -1 -1 0.04 0.0289656 0.0252216 63 34 64 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_011.v common 5.95 vpr 63.62 MiB 0.05 7048 -1 -1 1 0.03 -1 -1 30160 -1 -1 13 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65152 30 32 325 273 1 146 75 17 17 289 -1 unnamed_device 24.6 MiB 0.86 754 9397 3857 5236 304 63.6 MiB 0.09 0.00 2.95005 -111.061 -2.95005 2.95005 0.33 0.000644862 0.000599321 0.0406386 0.0377981 -1 -1 -1 -1 32 2003 39 6.95648e+06 188184 586450. 2029.24 3.23 0.271513 0.234061 25474 144626 -1 1696 21 1434 2017 171701 37391 3.20012 3.20012 -125.609 -3.20012 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0266087 0.0231499 61 63 30 30 60 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_012.v common 8.43 vpr 63.57 MiB 0.05 6940 -1 -1 1 0.03 -1 -1 30404 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65096 32 32 331 280 1 150 82 17 17 289 -1 unnamed_device 24.6 MiB 0.52 812 11118 3920 5250 1948 63.6 MiB 0.10 0.00 2.9793 -108.709 -2.9793 2.9793 0.33 0.000663809 0.000617097 0.0433514 0.0403456 -1 -1 -1 -1 34 2568 40 6.95648e+06 260562 618332. 2139.56 6.06 0.321941 0.276426 25762 151098 -1 1997 23 1324 2070 202850 43814 3.33157 3.33157 -128.102 -3.33157 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65344 32 32 407 319 1 192 94 17 17 289 -1 unnamed_device 24.8 MiB 0.60 836 13939 4431 7094 2414 63.8 MiB 0.13 0.00 3.86969 -139.597 -3.86969 3.86969 0.33 0.000781202 0.00072361 0.0540096 0.0501271 -1 -1 -1 -1 48 2382 47 6.95648e+06 434271 865456. 2994.66 2.91 0.339439 0.293708 28354 207349 -1 1936 22 2028 3003 232916 52891 4.27316 4.27316 -150.988 -4.27316 0 0 1.05005e+06 3633.38 0.04 0.05 0.12 -1 -1 0.04 0.0181227 0.0160795 90 65 64 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_015.v common 3.53 vpr 63.25 MiB 0.04 6956 -1 -1 1 0.03 -1 -1 30664 -1 -1 14 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64768 29 32 272 228 1 138 75 17 17 289 -1 unnamed_device 24.3 MiB 0.47 566 7975 3221 4328 426 63.2 MiB 0.07 0.00 2.93836 -96.7018 -2.93836 2.93836 0.33 0.000579085 0.000538813 0.0311578 0.0289894 -1 -1 -1 -1 42 1839 31 6.95648e+06 202660 744469. 2576.02 1.21 0.15386 0.133224 27202 183097 -1 1249 21 1035 1597 116659 31176 3.08382 3.08382 -109.335 -3.08382 0 0 949917. 3286.91 0.04 0.06 0.14 -1 -1 0.04 0.0240087 0.0208894 57 29 58 29 24 24 + fixed_k6_frac_2ripple_N8_22nm.xml mult_016.v common 9.88 vpr 64.35 MiB 0.04 7192 -1 -1 1 0.03 -1 -1 30420 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65896 32 32 401 315 1 186 78 17 17 289 -1 unnamed_device 24.8 MiB 1.16 1051 6718 1470 4903 345 64.4 MiB 0.08 0.00 2.93285 -118.01 -2.93285 2.93285 0.33 0.000766349 0.0007122 0.0337949 0.0314084 -1 -1 -1 -1 40 2582 20 6.95648e+06 202660 706193. 2443.58 6.81 0.326427 0.281084 26914 176310 -1 2318 21 1946 3047 245185 52239 3.19032 3.19032 -129.521 -3.19032 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0315594 0.0275657 79 63 64 32 62 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_017.v common 8.08 vpr 64.39 MiB 0.04 7100 -1 -1 1 0.03 -1 -1 30292 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65932 32 32 383 303 1 179 93 17 17 289 -1 unnamed_device 24.9 MiB 1.10 807 7443 1468 5595 380 64.4 MiB 0.08 0.00 3.0804 -116.29 -3.0804 3.0804 0.33 0.000743967 0.00068945 0.0294348 0.0269957 -1 -1 -1 -1 40 2287 38 6.95648e+06 419795 706193. 2443.58 5.09 0.329903 0.283274 26914 176310 -1 1865 24 1671 2241 168965 43042 3.42677 3.42677 -133.373 -3.42677 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0341624 0.0297364 83 57 64 32 56 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_018.v common 6.98 vpr 63.63 MiB 0.04 7088 -1 -1 1 0.03 -1 -1 30068 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65160 32 32 339 284 1 156 85 17 17 289 -1 unnamed_device 24.6 MiB 0.56 700 10687 3483 5569 1635 63.6 MiB 0.09 0.00 2.22111 -90.2873 -2.22111 2.22111 0.33 0.000670523 0.000622423 0.0409654 0.0380687 -1 -1 -1 -1 38 1911 29 6.95648e+06 303989 678818. 2348.85 4.56 0.280097 0.241158 26626 170182 -1 1497 28 1606 2322 200743 56036 2.19418 2.19418 -95.8841 -2.19418 0 0 902133. 3121.57 0.03 0.10 0.14 -1 -1 0.03 0.0347281 0.0300728 69 65 29 29 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_019.v common 3.85 vpr 63.71 MiB 0.04 6752 -1 -1 1 0.03 -1 -1 30184 -1 -1 12 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65240 30 32 226 208 1 116 74 17 17 289 -1 unnamed_device 24.3 MiB 0.14 714 10149 3183 6390 576 63.7 MiB 0.08 0.00 2.21746 -84.2994 -2.21746 2.21746 0.33 0.000510843 0.000475833 0.0346548 0.0322729 -1 -1 -1 -1 38 1456 26 6.95648e+06 173708 678818. 2348.85 1.91 0.186234 0.160283 26626 170182 -1 1292 20 731 961 83650 19590 2.05938 2.05938 -89.0505 -2.05938 0 0 902133. 3121.57 0.03 0.05 0.13 -1 -1 0.03 0.0200003 0.0173963 46 34 24 24 30 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_020.v common 9.11 vpr 63.62 MiB 0.05 7060 -1 -1 1 0.03 -1 -1 30540 -1 -1 12 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65152 31 32 335 280 1 151 75 17 17 289 -1 unnamed_device 24.6 MiB 0.74 615 9397 3718 5138 541 63.6 MiB 0.09 0.00 2.93905 -108.96 -2.93905 2.93905 0.33 0.000657083 0.000609906 0.0414978 0.0386046 -1 -1 -1 -1 38 2293 48 6.95648e+06 173708 678818. 2348.85 6.66 0.355163 0.305281 26626 170182 -1 1458 20 1336 2012 153236 36799 3.14792 3.14792 -120.423 -3.14792 0 0 902133. 3121.57 0.03 0.04 0.10 -1 -1 0.03 0.0149913 0.0133587 63 64 31 31 62 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_021.v common 8.10 vpr 64.19 MiB 0.04 6944 -1 -1 1 0.03 -1 -1 30128 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65732 32 32 366 283 1 184 93 17 17 289 -1 unnamed_device 24.5 MiB 0.25 997 17103 6265 8394 2444 64.2 MiB 0.14 0.00 3.69567 -136.934 -3.69567 3.69567 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64736 32 32 294 246 1 146 75 17 17 289 -1 unnamed_device 24.2 MiB 0.62 578 10819 4344 5833 642 63.2 MiB 0.09 0.00 2.9374 -102.673 -2.9374 2.9374 0.33 0.000617179 0.000573951 0.0445039 0.0414198 -1 -1 -1 -1 40 2030 34 6.95648e+06 159232 706193. 2443.58 2.41 0.179381 0.156219 26914 176310 -1 1381 23 1086 1653 119084 31432 3.02602 3.02602 -112.76 -3.02602 0 0 926341. 3205.33 0.04 0.06 0.14 -1 -1 0.04 0.0273198 0.0237438 58 34 54 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_030.v common 7.03 vpr 63.46 MiB 0.04 6980 -1 -1 1 0.03 -1 -1 30284 -1 -1 13 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65264 29 32 312 264 1 148 84 17 17 289 -1 unnamed_device 24.6 MiB 0.31 635 11064 3909 4785 2370 63.7 MiB 0.09 0.00 2.21891 -81.6895 -2.21891 2.21891 0.33 0.000623436 0.000578988 0.039937 0.0370801 -1 -1 -1 -1 40 1902 46 6.95648e+06 332941 706193. 2443.58 5.55 0.317169 0.271688 26914 176310 -1 1570 27 1498 2404 191874 48434 2.31468 2.31468 -91.5414 -2.31468 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0312514 0.0270471 68 61 29 29 57 29 + fixed_k6_frac_2ripple_N8_22nm.xml mult_035.v common 5.37 vpr 64.55 MiB 0.05 7212 -1 -1 1 0.03 -1 -1 30488 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66104 32 32 423 310 1 219 101 17 17 289 -1 unnamed_device 24.8 MiB 0.45 1182 15141 4783 8004 2354 64.6 MiB 0.14 0.00 3.79319 -141.215 -3.79319 3.79319 0.33 0.000835201 0.00076864 0.0565569 0.0524524 -1 -1 -1 -1 44 3177 26 6.95648e+06 535600 787024. 2723.27 2.97 0.346037 0.299004 27778 195446 -1 2566 22 2200 3706 303319 62532 3.75956 3.75956 -147.814 -3.75956 0 0 997811. 3452.63 0.04 0.10 0.15 -1 -1 0.04 0.0355552 0.031018 107 29 128 32 27 27 + fixed_k6_frac_2ripple_N8_22nm.xml mult_036.v common 4.96 vpr 64.28 MiB 0.05 7128 -1 -1 1 0.03 -1 -1 30384 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65824 32 32 403 317 1 190 96 17 17 289 -1 unnamed_device 24.7 MiB 0.67 1060 16083 4486 9706 1891 64.3 MiB 0.14 0.00 3.02515 -122.785 -3.02515 3.02515 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31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66100 31 32 455 371 1 184 78 17 17 289 -1 unnamed_device 24.9 MiB 1.50 845 13524 5793 7234 497 64.6 MiB 0.14 0.00 3.79794 -133.542 -3.79794 3.79794 0.33 0.000826826 0.000767866 0.0704672 0.0655095 -1 -1 -1 -1 40 2621 30 6.95648e+06 217135 706193. 2443.58 1.31 0.215857 0.189013 26914 176310 -1 2112 26 2232 3557 295737 79592 4.39226 4.39226 -155.198 -4.39226 0 0 926341. 3205.33 0.04 0.11 0.14 -1 -1 0.04 0.0400289 0.0346379 81 124 0 0 124 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_040.v common 8.74 vpr 63.83 MiB 0.05 7260 -1 -1 1 0.03 -1 -1 30448 -1 -1 15 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 65864 31 32 395 311 1 188 98 17 17 289 -1 unnamed_device 24.8 MiB 0.39 989 16748 5604 8391 2753 64.3 MiB 0.15 0.00 3.79506 -135.536 -3.79506 3.79506 0.33 0.000757519 0.000701627 0.059186 0.0547998 -1 -1 -1 -1 40 2470 25 6.95648e+06 506649 706193. 2443.58 1.23 0.193225 0.169288 26914 176310 -1 2238 31 2339 3708 347876 92384 4.08526 4.08526 -147.457 -4.08526 0 0 926341. 3205.33 0.03 0.09 0.10 -1 -1 0.03 0.0229175 0.0200935 94 64 62 31 62 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_046.v common 9.83 vpr 64.24 MiB 0.05 7192 -1 -1 1 0.03 -1 -1 30516 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65780 32 32 397 313 1 188 97 17 17 289 -1 unnamed_device 24.8 MiB 0.37 1148 16303 5501 8667 2135 64.2 MiB 0.15 0.00 3.03615 -120.283 -3.03615 3.03615 0.33 0.000762575 0.000706804 0.0585653 0.0542728 -1 -1 -1 -1 40 3009 39 6.95648e+06 477698 706193. 2443.58 7.50 0.334194 0.28839 26914 176310 -1 2538 23 1940 3291 262378 55301 3.13692 3.13692 -127.574 -3.13692 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0336333 0.029197 90 63 62 32 62 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_047.v common 5.99 vpr 64.25 MiB 0.05 7092 -1 -1 1 0.03 -1 -1 30516 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65788 32 32 345 257 1 187 78 17 17 289 -1 unnamed_device 24.6 MiB 0.72 808 11532 4802 6262 468 64.2 MiB 0.11 0.00 3.66789 -136.287 -3.66789 3.66789 0.33 0.000707703 0.000657989 0.0517912 0.0481796 -1 -1 -1 -1 50 2475 27 6.95648e+06 202660 902133. 3121.57 3.27 0.284452 0.246852 28642 213929 -1 2091 25 1980 3343 311147 72023 4.03826 4.03826 -147.211 -4.03826 0 0 1.08113e+06 3740.92 0.04 0.10 0.17 -1 -1 0.04 0.03405 0.0297223 79 3 128 32 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml mult_048.v common 10.76 vpr 63.57 MiB 0.04 7312 -1 -1 1 0.03 -1 -1 30428 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65100 32 32 424 343 1 182 96 17 17 289 -1 unnamed_device 24.7 MiB 1.02 1065 16521 4546 10556 1419 63.6 MiB 0.14 0.00 3.1848 -124.83 -3.1848 3.1848 0.33 0.000785387 0.000728964 0.0617577 0.0572851 -1 -1 -1 -1 38 2687 33 6.95648e+06 463222 678818. 2348.85 7.75 0.368946 0.319487 26626 170182 -1 2320 22 1567 2540 210400 44525 3.66637 3.66637 -135.719 -3.66637 0 0 902133. 3121.57 0.03 0.09 0.14 -1 -1 0.03 0.0336424 0.0293054 87 96 25 25 96 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_049.v common 7.18 vpr 63.57 MiB 0.02 7124 -1 -1 1 0.03 -1 -1 30252 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65092 32 32 395 311 1 186 99 17 17 289 -1 unnamed_device 24.8 MiB 0.50 1083 9903 2382 6922 599 63.6 MiB 0.10 0.00 3.01415 -121.42 -3.01415 3.01415 0.33 0.000772534 0.000710303 0.0358282 0.0332014 -1 -1 -1 -1 44 2470 21 6.95648e+06 506649 787024. 2723.27 4.75 0.297318 0.256316 27778 195446 -1 2151 19 1429 2157 174479 36240 2.78492 2.78492 -121.017 -2.78492 0 0 997811. 3452.63 0.04 0.07 0.15 -1 -1 0.04 0.0288609 0.0252417 90 61 64 32 60 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_050.v common 5.43 vpr 64.67 MiB 0.05 7044 -1 -1 1 0.03 -1 -1 30440 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66224 32 32 405 318 1 192 96 17 17 289 -1 unnamed_device 25.1 MiB 0.39 855 12579 3955 6361 2263 64.7 MiB 0.11 0.00 3.07535 -115.588 -3.07535 3.07535 0.33 0.000772691 0.000715687 0.0472455 0.0437473 -1 -1 -1 -1 52 2408 35 6.95648e+06 463222 926341. 3205.33 3.06 0.300148 0.259567 29218 227130 -1 1649 23 1921 2960 212859 52816 2.98672 2.98672 -119.129 -2.98672 0 0 1.14541e+06 3963.36 0.04 0.09 0.18 -1 -1 0.04 0.0340922 0.0297115 92 65 63 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_051.v common 8.45 vpr 64.41 MiB 0.05 7064 -1 -1 1 0.03 -1 -1 30688 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65956 32 32 376 288 1 186 95 17 17 289 -1 unnamed_device 24.8 MiB 0.51 904 11975 3915 5851 2209 64.4 MiB 0.11 0.00 3.80196 -138.017 -3.80196 3.80196 0.33 0.000744874 0.000691059 0.0437331 0.0405233 -1 -1 -1 -1 54 2450 40 6.95648e+06 448746 949917. 3286.91 5.92 0.36777 0.316519 29506 232905 -1 2084 23 1932 3144 338376 81728 3.85486 3.85486 -141.939 -3.85486 0 0 1.17392e+06 4061.99 0.04 0.11 0.19 -1 -1 0.04 0.0326879 0.0285039 88 34 96 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_052.v common 4.84 vpr 64.45 MiB 0.05 7040 -1 -1 1 0.03 -1 -1 30588 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65992 32 32 407 319 1 189 97 17 17 289 -1 unnamed_device 24.8 MiB 0.63 835 16303 5172 8841 2290 64.4 MiB 0.14 0.00 3.71319 -134.96 -3.71319 3.71319 0.33 0.000775862 0.000713547 0.0593351 0.0549642 -1 -1 -1 -1 38 2726 37 6.95648e+06 477698 678818. 2348.85 2.25 0.230379 0.20089 26626 170182 -1 2109 24 2198 3267 259879 60536 4.32506 4.32506 -159.241 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14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65932 32 32 432 346 1 187 78 17 17 289 -1 unnamed_device 24.8 MiB 0.54 837 12860 5438 7034 388 64.4 MiB 0.13 0.00 3.61409 -131.006 -3.61409 3.61409 0.33 0.000804261 0.00074721 0.0651314 0.0605464 -1 -1 -1 -1 42 2696 47 6.95648e+06 202660 744469. 2576.02 2.54 0.351541 0.304643 27202 183097 -1 2067 22 1762 3011 226876 51341 3.83296 3.83296 -139.071 -3.83296 0 0 949917. 3286.91 0.04 0.09 0.15 -1 -1 0.04 0.0346853 0.0302318 79 94 32 32 94 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_055.v common 10.65 vpr 63.37 MiB 0.04 6880 -1 -1 1 0.03 -1 -1 30520 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64888 32 32 312 255 1 160 90 17 17 289 -1 unnamed_device 24.5 MiB 0.14 768 14160 5227 6971 1962 63.4 MiB 0.11 0.00 2.94515 -113.956 -2.94515 2.94515 0.33 0.000637754 0.000590834 0.0472694 0.0438506 -1 -1 -1 -1 36 2903 45 6.95648e+06 376368 648988. 2245.63 8.65 0.303775 0.262638 26050 158493 -1 2089 22 1714 2771 272804 63076 3.24022 3.24022 -130.142 -3.24022 0 0 828058. 2865.25 0.03 0.09 0.13 -1 -1 0.03 0.0274157 0.0238458 73 34 63 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_056.v common 7.99 vpr 63.60 MiB 0.05 7160 -1 -1 1 0.03 -1 -1 30408 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65124 32 32 370 314 1 158 76 17 17 289 -1 unnamed_device 24.6 MiB 0.62 633 7596 1852 4646 1098 63.6 MiB 0.09 0.00 2.95805 -110.254 -2.95805 2.95805 0.34 0.000721358 0.00067093 0.0362416 0.0337131 -1 -1 -1 -1 50 1624 23 6.95648e+06 173708 902133. 3121.57 5.45 0.315953 0.271561 28642 213929 -1 1343 21 1345 2022 156849 37822 3.07172 3.07172 -118.613 -3.07172 0 0 1.08113e+06 3740.92 0.04 0.07 0.17 -1 -1 0.04 0.0289241 0.0252175 64 94 0 0 94 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_057.v common 18.28 vpr 64.62 MiB 0.04 7296 -1 -1 1 0.03 -1 -1 30848 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66168 32 32 469 351 1 223 98 17 17 289 -1 unnamed_device 25.0 MiB 0.45 1114 17423 6179 8626 2618 64.6 MiB 0.17 0.00 4.52726 -161.049 -4.52726 4.52726 0.33 0.000881204 0.000815262 0.0715494 0.0663738 -1 -1 -1 -1 50 3235 42 6.95648e+06 492173 902133. 3121.57 15.74 0.483072 0.417301 28642 213929 -1 2528 22 2389 3979 344470 76256 4.91551 4.91551 -173.271 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26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65040 32 32 345 287 1 155 90 17 17 289 -1 unnamed_device 24.5 MiB 0.97 694 11949 4515 6462 972 63.5 MiB 0.11 0.00 3.00763 -115.231 -3.00763 3.00763 0.33 0.000695616 0.000640177 0.04302 0.039867 -1 -1 -1 -1 42 2166 27 6.95648e+06 376368 744469. 2576.02 2.56 0.272814 0.234896 27202 183097 -1 1684 20 1439 2147 181429 42594 3.08572 3.08572 -123.618 -3.08572 0 0 949917. 3286.91 0.04 0.08 0.15 -1 -1 0.04 0.0267147 0.0233462 71 65 32 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_070.v common 6.71 vpr 63.63 MiB 0.05 7032 -1 -1 1 0.03 -1 -1 30444 -1 -1 12 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65156 31 32 353 302 1 146 75 17 17 289 -1 unnamed_device 24.6 MiB 0.93 612 8291 3398 4596 297 63.6 MiB 0.08 0.00 2.91705 -106.629 -2.91705 2.91705 0.33 0.00068008 0.00063168 0.0378053 0.0351459 -1 -1 -1 -1 46 1854 29 6.95648e+06 173708 828058. 2865.25 3.91 0.276337 0.237262 28066 200906 -1 1470 31 1482 2490 232383 80656 3.06512 3.06512 -114.478 -3.06512 0 0 1.01997e+06 3529.29 0.04 0.11 0.16 -1 -1 0.04 0.0377265 0.0326056 61 90 0 0 89 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_071.v common 4.45 vpr 64.16 MiB 0.05 7068 -1 -1 1 0.03 -1 -1 30472 -1 -1 34 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65704 30 32 374 297 1 178 96 17 17 289 -1 unnamed_device 24.5 MiB 0.40 821 14769 4586 7579 2604 64.2 MiB 0.13 0.00 3.02515 -108.016 -3.02515 3.02515 0.33 0.000722641 0.0006702 0.0511161 0.0473837 -1 -1 -1 -1 46 2030 27 6.95648e+06 492173 828058. 2865.25 2.07 0.267387 0.230902 28066 200906 -1 1721 23 1567 2496 164396 39597 3.13882 3.13882 -114.694 -3.13882 0 0 1.01997e+06 3529.29 0.04 0.08 0.16 -1 -1 0.04 0.0317639 0.0276667 87 60 60 30 57 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_072.v common 4.81 vpr 63.64 MiB 0.04 7108 -1 -1 1 0.03 -1 -1 30380 -1 -1 36 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65164 28 32 332 260 1 172 96 17 17 289 -1 unnamed_device 24.7 MiB 0.30 750 17397 5782 8505 3110 63.6 MiB 0.13 0.00 3.71919 -117.682 -3.71919 3.71919 0.33 0.000645624 0.000598523 0.0553633 0.0513525 -1 -1 -1 -1 44 2211 25 6.95648e+06 521125 787024. 2723.27 2.53 0.259532 0.224903 27778 195446 -1 1780 22 1725 3075 257842 57336 3.72466 3.72466 -122.473 -3.72466 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65212 32 32 361 308 1 152 76 17 17 289 -1 unnamed_device 24.7 MiB 0.76 616 9196 3757 5077 362 63.7 MiB 0.05 0.00 2.84485 -103.916 -2.84485 2.84485 0.26 0.000304913 0.000279654 0.0197365 0.018182 -1 -1 -1 -1 46 1840 34 6.95648e+06 173708 828058. 2865.25 4.33 0.250391 0.213816 28066 200906 -1 1394 35 1497 2433 166296 41613 2.87532 2.87532 -111.17 -2.87532 0 0 1.01997e+06 3529.29 0.04 0.09 0.16 -1 -1 0.04 0.0433451 0.0374291 62 91 0 0 91 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_075.v common 10.20 vpr 64.43 MiB 0.05 6980 -1 -1 1 0.03 -1 -1 30444 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65980 31 32 335 251 1 188 95 17 17 289 -1 unnamed_device 24.7 MiB 0.13 1144 16511 5176 9723 1612 64.4 MiB 0.15 0.00 3.78219 -141.259 -3.78219 3.78219 0.33 0.0006922 0.000642311 0.0556803 0.051684 -1 -1 -1 -1 44 2822 26 6.95648e+06 463222 787024. 2723.27 8.06 0.304996 0.264291 27778 195446 -1 2340 24 2046 3336 296556 60315 3.98996 3.98996 -154.33 -3.98996 0 0 997811. 3452.63 0.04 0.10 0.16 -1 -1 0.04 0.0322218 0.0281051 92 4 124 31 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml mult_076.v common 6.62 vpr 63.82 MiB 0.05 7100 -1 -1 1 0.03 -1 -1 30572 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65348 32 32 407 319 1 189 94 17 17 289 -1 unnamed_device 24.9 MiB 1.00 864 17134 7233 9262 639 63.8 MiB 0.15 0.00 3.74919 -137.193 -3.74919 3.74919 0.33 0.000780148 0.000717018 0.0650585 0.060269 -1 -1 -1 -1 52 2894 39 6.95648e+06 434271 926341. 3205.33 3.57 0.344887 0.299059 29218 227130 -1 2047 22 1993 3508 286773 66388 3.87496 3.87496 -144.842 -3.87496 0 0 1.14541e+06 3963.36 0.04 0.10 0.18 -1 -1 0.04 0.0329266 0.0287273 89 65 64 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_077.v common 5.94 vpr 63.82 MiB 0.05 7240 -1 -1 1 0.03 -1 -1 30488 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65352 32 32 407 319 1 187 93 17 17 289 -1 unnamed_device 24.9 MiB 1.14 894 17313 6821 8964 1528 63.8 MiB 0.16 0.00 3.81339 -139.726 -3.81339 3.81339 0.33 0.000783383 0.000727232 0.0673179 0.0624753 -1 -1 -1 -1 48 2550 23 6.95648e+06 419795 865456. 2994.66 2.79 0.321209 0.279312 28354 207349 -1 2170 24 2069 3371 308547 67749 4.02226 4.02226 -149.506 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/home/elgamma8/research/release/vtr-verilog-to-routing 65908 30 32 383 303 1 183 78 17 17 289 -1 unnamed_device 24.9 MiB 0.34 893 10702 4147 4571 1984 64.4 MiB 0.11 0.00 3.73035 -132.73 -3.73035 3.73035 0.33 0.000734314 0.000682468 0.0501984 0.0466866 -1 -1 -1 -1 34 2877 46 6.95648e+06 231611 618332. 2139.56 4.53 0.360062 0.310152 25762 151098 -1 2294 23 2043 2959 254014 56227 4.50466 4.50466 -154.048 -4.50466 0 0 787024. 2723.27 0.03 0.10 0.12 -1 -1 0.03 0.0329306 0.0287016 79 63 60 30 60 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_081.v common 13.33 vpr 64.45 MiB 0.05 7156 -1 -1 1 0.03 -1 -1 30832 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65992 32 32 469 381 1 190 99 17 17 289 -1 unnamed_device 24.9 MiB 1.08 1057 9675 2493 6229 953 64.4 MiB 0.10 0.00 3.83239 -141.999 -3.83239 3.83239 0.33 0.000852539 0.000791956 0.0391889 0.0364065 -1 -1 -1 -1 40 2810 26 6.95648e+06 506649 706193. 2443.58 10.27 0.400508 0.344736 26914 176310 -1 2406 25 2230 3734 317253 67036 4.36886 4.36886 -157.59 -4.36886 0 0 926341. 3205.33 0.04 0.11 0.14 -1 -1 0.04 0.0391247 0.0338521 92 127 0 0 128 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_082.v common 5.18 vpr 64.53 MiB 0.05 7196 -1 -1 1 0.03 -1 -1 30748 -1 -1 29 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66080 31 32 425 341 1 182 92 17 17 289 -1 unnamed_device 24.9 MiB 0.56 804 12926 4797 6175 1954 64.5 MiB 0.12 0.00 3.77419 -132.789 -3.77419 3.77419 0.33 0.000781678 0.000724755 0.05182 0.0480111 -1 -1 -1 -1 46 2386 39 6.95648e+06 419795 828058. 2865.25 2.65 0.323566 0.279626 28066 200906 -1 1742 26 2024 3121 217542 56896 3.81746 3.81746 -137.751 -3.81746 0 0 1.01997e+06 3529.29 0.04 0.10 0.16 -1 -1 0.04 0.0375528 0.0326026 87 94 31 31 93 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_083.v common 4.88 vpr 64.39 MiB 0.05 7268 -1 -1 1 0.03 -1 -1 30612 -1 -1 30 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65936 30 32 404 328 1 172 92 17 17 289 -1 unnamed_device 24.8 MiB 0.71 784 11684 3303 6454 1927 64.4 MiB 0.11 0.00 3.06483 -107.982 -3.06483 3.06483 0.33 0.000752562 0.000698047 0.0453498 0.0421498 -1 -1 -1 -1 44 1986 32 6.95648e+06 434271 787024. 2723.27 2.16 0.283655 0.244503 27778 195446 -1 1633 25 1707 2674 178629 42997 2.96332 2.96332 -111.845 -2.96332 0 0 997811. 3452.63 0.04 0.08 0.16 -1 -1 0.04 0.0352125 0.0305304 82 92 26 26 90 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_084.v common 10.29 vpr 63.78 MiB 0.05 7204 -1 -1 1 0.03 -1 -1 30504 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65308 32 32 407 319 1 193 78 17 17 289 -1 unnamed_device 24.8 MiB 0.98 970 13524 4161 8124 1239 63.8 MiB 0.14 0.00 3.70709 -138.158 -3.70709 3.70709 0.33 0.000772866 0.000717363 0.0660303 0.0613345 -1 -1 -1 -1 46 2848 44 6.95648e+06 202660 828058. 2865.25 7.32 0.417886 0.362144 28066 200906 -1 2393 22 2040 3350 304015 62919 4.15746 4.15746 -154.192 -4.15746 0 0 1.01997e+06 3529.29 0.04 0.10 0.16 -1 -1 0.04 0.0335983 0.0293839 81 65 64 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_085.v common 7.38 vpr 64.33 MiB 0.05 7252 -1 -1 1 0.03 -1 -1 30344 -1 -1 34 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65872 29 32 387 316 1 171 95 17 17 289 -1 unnamed_device 24.8 MiB 0.53 799 11543 3674 5805 2064 64.3 MiB 0.10 0.00 2.99215 -102.7 -2.99215 2.99215 0.33 0.000728462 0.000674606 0.0415125 0.0384754 -1 -1 -1 -1 36 2491 33 6.95648e+06 492173 648988. 2245.63 4.97 0.305982 0.26271 26050 158493 -1 1739 22 1523 2315 173906 41913 3.37362 3.37362 -114.306 -3.37362 0 0 828058. 2865.25 0.03 0.08 0.13 -1 -1 0.03 0.0308938 0.0268483 85 88 26 26 85 29 + fixed_k6_frac_2ripple_N8_22nm.xml mult_086.v common 4.24 vpr 63.20 MiB 0.04 6920 -1 -1 1 0.03 -1 -1 30340 -1 -1 11 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64720 32 32 283 225 1 154 75 17 17 289 -1 unnamed_device 24.2 MiB 0.73 634 10345 3746 4906 1693 63.2 MiB 0.09 0.00 2.95005 -113.271 -2.95005 2.95005 0.33 0.000610328 0.00056797 0.0421183 0.0392314 -1 -1 -1 -1 42 2214 29 6.95648e+06 159232 744469. 2576.02 1.68 0.170191 0.148201 27202 183097 -1 1662 20 1294 1970 184358 45262 3.02772 3.02772 -120.654 -3.02772 0 0 949917. 3286.91 0.04 0.07 0.14 -1 -1 0.04 0.0245907 0.0215065 62 3 96 32 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml mult_087.v common 12.95 vpr 64.38 MiB 0.05 7152 -1 -1 1 0.03 -1 -1 30488 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65924 32 32 407 319 1 187 91 17 17 289 -1 unnamed_device 24.8 MiB 2.49 995 13555 5305 7140 1110 64.4 MiB 0.13 0.00 3.78519 -140.535 -3.78519 3.78519 0.33 0.000778235 0.000720528 0.054465 0.0504447 -1 -1 -1 -1 42 2784 31 6.95648e+06 390843 744469. 2576.02 8.50 0.33905 0.293573 27202 183097 -1 2234 24 2085 3193 301812 63023 3.92696 3.92696 -150.426 -3.92696 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64884 32 32 315 267 1 152 86 17 17 289 -1 unnamed_device 24.3 MiB 0.44 767 11804 4844 6750 210 63.4 MiB 0.10 0.00 2.88585 -108.369 -2.88585 2.88585 0.33 0.000636465 0.000591064 0.0419709 0.0389871 -1 -1 -1 -1 38 1971 50 6.95648e+06 318465 678818. 2348.85 1.17 0.169719 0.147796 26626 170182 -1 1602 22 1339 2042 173752 53877 2.95852 2.95852 -112.019 -2.95852 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0268009 0.0233212 68 55 32 32 54 27 + fixed_k6_frac_2ripple_N8_22nm.xml mult_090.v common 3.47 vpr 63.25 MiB 0.05 6788 -1 -1 1 0.03 -1 -1 30440 -1 -1 12 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64768 31 32 275 220 1 154 75 17 17 289 -1 unnamed_device 24.2 MiB 0.24 876 9081 2616 5597 868 63.2 MiB 0.08 0.00 2.95305 -115.628 -2.95305 2.95305 0.33 0.000593954 0.000553134 0.0364921 0.0340113 -1 -1 -1 -1 38 2026 23 6.95648e+06 173708 678818. 2348.85 1.37 0.159325 0.138822 26626 170182 -1 1817 20 1467 2170 170840 37494 3.10392 3.10392 -126.814 -3.10392 0 0 902133. 3121.57 0.03 0.07 0.13 -1 -1 0.03 0.0240864 0.0210193 65 4 93 31 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml mult_091.v common 4.29 vpr 63.48 MiB 0.05 7052 -1 -1 1 0.03 -1 -1 30328 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65000 32 32 381 303 1 180 96 17 17 289 -1 unnamed_device 24.7 MiB 0.63 927 17178 7158 9678 342 63.5 MiB 0.14 0.00 3.69719 -130.339 -3.69719 3.69719 0.33 0.000742262 0.000687479 0.0611967 0.0566815 -1 -1 -1 -1 36 2786 48 6.95648e+06 463222 648988. 2245.63 1.65 0.22788 0.198897 26050 158493 -1 2199 24 1979 2920 237525 53484 3.88776 3.88776 -147.598 -3.88776 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0341537 0.0297461 86 59 60 32 58 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_092.v common 9.53 vpr 63.73 MiB 0.05 7268 -1 -1 1 0.03 -1 -1 30348 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65260 32 32 406 330 1 182 94 17 17 289 -1 unnamed_device 24.8 MiB 0.20 910 13087 4875 6895 1317 63.7 MiB 0.12 0.00 3.72106 -128.856 -3.72106 3.72106 0.33 0.000758331 0.00070384 0.0494498 0.0458613 -1 -1 -1 -1 38 2744 24 6.95648e+06 434271 678818. 2348.85 7.45 0.371848 0.32008 26626 170182 -1 1958 22 1825 2915 213896 51230 4.44216 4.44216 -143.258 -4.44216 0 0 902133. 3121.57 0.04 0.09 0.13 -1 -1 0.04 0.0322575 0.0280913 85 88 28 28 88 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_093.v common 13.35 vpr 64.48 MiB 0.05 7124 -1 -1 1 0.03 -1 -1 30500 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66024 32 32 399 285 1 218 98 17 17 289 -1 unnamed_device 24.8 MiB 0.22 1090 14948 4439 8116 2393 64.5 MiB 0.14 0.00 4.49114 -157.775 -4.49114 4.49114 0.33 0.000792848 0.000736771 0.0556148 0.0516116 -1 -1 -1 -1 44 3655 42 6.95648e+06 492173 787024. 2723.27 11.05 0.401725 0.347723 27778 195446 -1 2734 21 2285 3558 331809 73612 4.63201 4.63201 -168.752 -4.63201 0 0 997811. 3452.63 0.04 0.11 0.16 -1 -1 0.04 0.0339831 0.0298585 105 3 156 32 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml mult_094.v common 3.93 vpr 64.21 MiB 0.05 7200 -1 -1 1 0.03 -1 -1 30516 -1 -1 30 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65756 30 32 371 295 1 176 92 17 17 289 -1 unnamed_device 24.5 MiB 0.42 773 16031 4862 8616 2553 64.2 MiB 0.14 0.00 3.02515 -107.178 -3.02515 3.02515 0.33 0.000712777 0.000661625 0.0580159 0.0538366 -1 -1 -1 -1 40 2544 46 6.95648e+06 434271 706193. 2443.58 1.60 0.205228 0.178834 26914 176310 -1 1819 24 1746 2759 221514 53000 3.75432 3.75432 -120.684 -3.75432 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0327945 0.0285264 84 59 60 30 56 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_095.v common 3.47 vpr 63.25 MiB 0.04 7040 -1 -1 1 0.03 -1 -1 30672 -1 -1 15 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 27 32 269 226 1 135 74 17 17 289 -1 unnamed_device 24.2 MiB 0.29 834 7359 2280 4045 1034 63.2 MiB 0.07 0.00 2.86985 -98.9536 -2.86985 2.86985 0.33 0.000566146 0.000526225 0.0289215 0.0269497 -1 -1 -1 -1 32 1834 21 6.95648e+06 217135 586450. 2029.24 1.39 0.178093 0.153042 25474 144626 -1 1646 20 1127 1555 124124 27156 3.10102 3.10102 -112.718 -3.10102 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226312 0.0196526 60 34 54 27 27 27 + fixed_k6_frac_2ripple_N8_22nm.xml mult_096.v common 15.31 vpr 64.71 MiB 0.05 7320 -1 -1 1 0.03 -1 -1 30672 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66268 32 32 493 378 1 222 99 17 17 289 -1 unnamed_device 25.1 MiB 0.46 1306 14919 4313 9293 1313 64.7 MiB 0.15 0.00 3.80387 -141.931 -3.80387 3.80387 0.33 0.000908108 0.000843874 0.0625778 0.0580792 -1 -1 -1 -1 38 3944 44 6.95648e+06 506649 678818. 2348.85 12.78 0.440725 0.380228 26626 170182 -1 3006 25 2747 4678 399014 81226 4.05526 4.05526 -157.833 -4.05526 0 0 902133. 3121.57 0.03 0.13 0.13 -1 -1 0.03 0.0423983 0.0367877 109 95 62 31 95 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_097.v common 6.45 vpr 64.20 MiB 0.05 7332 -1 -1 1 0.03 -1 -1 30528 -1 -1 15 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65736 31 32 455 371 1 185 78 17 17 289 -1 unnamed_device 25.1 MiB 1.77 760 10204 4107 5326 771 64.2 MiB 0.11 0.00 3.76754 -132.461 -3.76754 3.76754 0.33 0.000830916 0.000772406 0.0542281 0.0504428 -1 -1 -1 -1 62 1887 20 6.95648e+06 217135 1.05005e+06 3633.38 2.72 0.321677 0.276732 30946 263737 -1 1513 22 1619 2464 160407 38798 4.09926 4.09926 -141.868 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32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65828 32 32 364 282 1 188 94 17 17 289 -1 unnamed_device 24.6 MiB 0.16 872 12235 3685 6337 2213 64.3 MiB 0.11 0.00 3.79096 -133.989 -3.79096 3.79096 0.33 0.000736219 0.00067696 0.044285 0.0410864 -1 -1 -1 -1 52 2436 27 6.95648e+06 434271 926341. 3205.33 3.01 0.29903 0.257725 29218 227130 -1 1955 23 1817 2761 224784 50670 3.93796 3.93796 -140.061 -3.93796 0 0 1.14541e+06 3963.36 0.04 0.09 0.18 -1 -1 0.04 0.0322204 0.0281007 88 34 90 30 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_100.v common 4.98 vpr 64.46 MiB 0.05 7296 -1 -1 1 0.03 -1 -1 30600 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66008 31 32 443 336 1 210 97 17 17 289 -1 unnamed_device 24.7 MiB 0.47 1008 10309 3050 5352 1907 64.5 MiB 0.11 0.00 3.78655 -135.19 -3.78655 3.78655 0.33 0.000846979 0.000786053 0.0425116 0.0395538 -1 -1 -1 -1 40 2671 33 6.95648e+06 492173 706193. 2443.58 2.53 0.317865 0.27328 26914 176310 -1 2235 29 2474 3465 283787 75948 4.35786 4.35786 -151.699 -4.35786 0 0 926341. 3205.33 0.04 0.12 0.14 -1 -1 0.04 0.0443633 0.0383883 103 64 87 31 62 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_101.v common 9.71 vpr 63.65 MiB 0.05 7204 -1 -1 1 0.03 -1 -1 30472 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65176 30 32 373 297 1 178 95 17 17 289 -1 unnamed_device 24.6 MiB 0.33 1053 17591 5567 10335 1689 63.6 MiB 0.15 0.00 2.95915 -111.602 -2.95915 2.95915 0.33 0.000718414 0.000667128 0.0611833 0.0567047 -1 -1 -1 -1 40 2583 24 6.95648e+06 477698 706193. 2443.58 7.41 0.324079 0.280739 26914 176310 -1 2311 22 1722 2902 232970 49578 2.98052 2.98052 -118.352 -2.98052 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0303733 0.0264167 86 61 58 30 58 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_102.v common 10.45 vpr 64.38 MiB 0.05 6996 -1 -1 1 0.04 -1 -1 30484 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65924 32 32 407 319 1 193 102 17 17 289 -1 unnamed_device 24.8 MiB 0.37 955 12716 3237 8898 581 64.4 MiB 0.12 0.00 3.77739 -138.851 -3.77739 3.77739 0.33 0.000775412 0.000719774 0.0443718 0.0411573 -1 -1 -1 -1 40 2793 38 6.95648e+06 550076 706193. 2443.58 8.11 0.373362 0.321643 26914 176310 -1 2288 22 1989 2937 263378 58824 4.37036 4.37036 -156.062 -4.37036 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0327769 0.0285741 95 65 64 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_103.v common 9.91 vpr 63.83 MiB 0.04 7144 -1 -1 1 0.03 -1 -1 30588 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65360 32 32 405 318 1 192 99 17 17 289 -1 unnamed_device 24.8 MiB 0.36 994 14463 3282 10605 576 63.8 MiB 0.14 0.00 3.08635 -120.858 -3.08635 3.08635 0.33 0.000776897 0.000719642 0.0545356 0.0505443 -1 -1 -1 -1 38 2560 23 6.95648e+06 506649 678818. 2348.85 7.65 0.384788 0.331479 26626 170182 -1 2177 21 1643 2221 175833 37705 3.16882 3.16882 -130.69 -3.16882 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.0320414 0.028007 94 65 63 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_104.v common 6.87 vpr 63.45 MiB 0.04 6976 -1 -1 1 0.03 -1 -1 30496 -1 -1 13 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64972 29 32 287 238 1 135 74 17 17 289 -1 unnamed_device 24.4 MiB 2.31 566 8444 3444 4596 404 63.4 MiB 0.07 0.00 2.81985 -96.9287 -2.81985 2.81985 0.33 0.000597536 0.000555252 0.034631 0.032233 -1 -1 -1 -1 36 1559 30 6.95648e+06 188184 648988. 2245.63 2.74 0.24753 0.211807 26050 158493 -1 1203 22 1078 1370 97012 23866 2.81132 2.81132 -105.046 -2.81132 0 0 828058. 2865.25 0.03 0.06 0.13 -1 -1 0.03 0.0255544 0.0221971 57 34 58 29 29 29 + fixed_k6_frac_2ripple_N8_22nm.xml mult_105.v common 5.56 vpr 64.38 MiB 0.05 6912 -1 -1 1 0.03 -1 -1 30244 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65924 32 32 334 290 1 148 76 17 17 289 -1 unnamed_device 24.6 MiB 0.29 701 9036 2643 5274 1119 64.4 MiB 0.08 0.00 2.9635 -104.243 -2.9635 2.9635 0.33 0.000661879 0.000614835 0.0393279 0.0365752 -1 -1 -1 -1 36 1741 27 6.95648e+06 173708 648988. 2245.63 3.45 0.275177 0.236366 26050 158493 -1 1405 21 1158 1558 112962 26210 3.04982 3.04982 -111.965 -3.04982 0 0 828058. 2865.25 0.03 0.06 0.13 -1 -1 0.03 0.0275127 0.0239783 60 82 0 0 82 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_106.v common 9.01 vpr 64.32 MiB 0.04 7124 -1 -1 1 0.03 -1 -1 30424 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65868 31 32 365 281 1 188 98 17 17 289 -1 unnamed_device 24.9 MiB 0.29 1068 17198 4744 11124 1330 64.3 MiB 0.14 0.00 3.78219 -137.213 -3.78219 3.78219 0.33 0.000721609 0.000669659 0.057735 0.0535352 -1 -1 -1 -1 42 2615 25 6.95648e+06 506649 744469. 2576.02 6.77 0.333788 0.289203 27202 183097 -1 2176 22 2043 3023 251062 52225 4.09926 4.09926 -150.342 -4.09926 0 0 949917. 3286.91 0.04 0.09 0.14 -1 -1 0.04 0.0305887 0.0266408 94 34 93 31 31 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_107.v common 5.13 vpr 63.99 MiB 0.05 7052 -1 -1 1 0.03 -1 -1 30552 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65528 29 32 297 254 1 141 84 17 17 289 -1 unnamed_device 24.3 MiB 0.41 578 12345 5122 6532 691 64.0 MiB 0.10 0.00 2.86863 -95.8049 -2.86863 2.86863 0.33 0.000603909 0.000561664 0.0427403 0.0397317 -1 -1 -1 -1 48 1549 29 6.95648e+06 332941 865456. 2994.66 2.88 0.225983 0.194731 28354 207349 -1 1315 24 1183 1871 131675 32208 2.85522 2.85522 -101.12 -2.85522 0 0 1.05005e+06 3633.38 0.04 0.07 0.16 -1 -1 0.04 0.0273014 0.0236141 65 56 29 29 52 26 + fixed_k6_frac_2ripple_N8_22nm.xml mult_108.v common 4.18 vpr 63.43 MiB 0.04 6920 -1 -1 1 0.03 -1 -1 30264 -1 -1 11 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64948 32 32 314 256 1 154 75 17 17 289 -1 unnamed_device 24.5 MiB 0.96 746 10345 4259 5889 197 63.4 MiB 0.10 0.00 2.93285 -115.609 -2.93285 2.93285 0.33 0.000650042 0.000604312 0.0445715 0.0414736 -1 -1 -1 -1 40 1880 20 6.95648e+06 159232 706193. 2443.58 1.40 0.170514 0.148777 26914 176310 -1 1701 24 1523 2134 204150 47477 3.51472 3.51472 -130.674 -3.51472 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.029555 0.0257005 62 34 64 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_109.v common 5.79 vpr 63.75 MiB 0.05 7216 -1 -1 1 0.03 -1 -1 30304 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65276 31 32 387 307 1 181 96 17 17 289 -1 unnamed_device 24.8 MiB 0.64 929 15864 4548 9162 2154 63.7 MiB 0.14 0.00 3.07535 -115.416 -3.07535 3.07535 0.33 0.000565143 0.000514805 0.0565728 0.0525191 -1 -1 -1 -1 36 2485 49 6.95648e+06 477698 648988. 2245.63 3.20 0.327486 0.283381 26050 158493 -1 1982 25 2078 2928 235069 55386 3.29232 3.29232 -128.257 -3.29232 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0353141 0.030716 89 64 58 31 62 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_110.v common 5.68 vpr 63.54 MiB 0.05 7104 -1 -1 1 0.03 -1 -1 30296 -1 -1 12 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65068 31 32 308 262 1 142 75 17 17 289 -1 unnamed_device 24.3 MiB 1.10 561 9081 3726 4991 364 63.5 MiB 0.08 0.00 2.878 -99.4515 -2.878 2.878 0.33 0.000625323 0.000580577 0.0384881 0.0358352 -1 -1 -1 -1 42 1873 44 6.95648e+06 173708 744469. 2576.02 2.71 0.261568 0.224788 27202 183097 -1 1399 34 1462 2239 198648 67215 2.97097 2.97097 -105.92 -2.97097 0 0 949917. 3286.91 0.04 0.10 0.15 -1 -1 0.04 0.0379742 0.0327631 57 55 31 31 53 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_111.v common 9.50 vpr 63.75 MiB 0.04 7140 -1 -1 1 0.03 -1 -1 30448 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65276 32 32 383 307 1 176 96 17 17 289 -1 unnamed_device 24.6 MiB 0.90 1008 15645 5715 8149 1781 63.7 MiB 0.13 0.00 2.93235 -112.949 -2.93235 2.93235 0.33 0.000736041 0.000680911 0.0553155 0.051248 -1 -1 -1 -1 38 2510 47 6.95648e+06 463222 678818. 2348.85 6.69 0.349571 0.302102 26626 170182 -1 2131 22 1477 2382 175778 38190 2.94132 2.94132 -122.271 -2.94132 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0312975 0.0272747 84 65 52 26 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_112.v common 3.97 vpr 64.48 MiB 0.05 7164 -1 -1 1 0.03 -1 -1 30420 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66032 31 32 422 339 1 187 95 17 17 289 -1 unnamed_device 24.8 MiB 0.95 814 14999 5034 7379 2586 64.5 MiB 0.13 0.00 3.12545 -115.097 -3.12545 3.12545 0.33 0.000787055 0.000728493 0.0575209 0.0531761 -1 -1 -1 -1 40 2613 32 6.95648e+06 463222 706193. 2443.58 1.09 0.196102 0.171338 26914 176310 -1 1926 21 1924 2659 204937 48092 3.45062 3.45062 -126.961 -3.45062 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0322371 0.028142 91 93 31 31 92 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_113.v common 4.74 vpr 63.47 MiB 0.04 6968 -1 -1 1 0.03 -1 -1 30320 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64996 32 32 333 279 1 154 76 17 17 289 -1 unnamed_device 24.3 MiB 0.43 634 9836 2564 5684 1588 63.5 MiB 0.09 0.00 2.83385 -103.376 -2.83385 2.83385 0.33 0.000658459 0.000612155 0.0427864 0.0398191 -1 -1 -1 -1 44 1831 49 6.95648e+06 173708 787024. 2723.27 2.44 0.279259 0.240577 27778 195446 -1 1296 22 1167 1847 118693 29957 3.27042 3.27042 -108.272 -3.27042 0 0 997811. 3452.63 0.04 0.07 0.15 -1 -1 0.04 0.0282458 0.0245808 62 61 32 32 60 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_114.v common 7.84 vpr 63.64 MiB 0.05 6968 -1 -1 1 0.03 -1 -1 30064 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65164 32 32 339 283 1 158 76 17 17 289 -1 unnamed_device 24.6 MiB 0.36 653 8716 2249 5094 1373 63.6 MiB 0.04 0.00 2.91085 -109.584 -2.91085 2.91085 0.25 0.000296029 0.000272482 0.0180277 0.0166447 -1 -1 -1 -1 46 1898 26 6.95648e+06 173708 828058. 2865.25 5.83 0.290743 0.24807 28066 200906 -1 1393 27 1458 2287 173544 43666 3.37552 3.37552 -120.828 -3.37552 0 0 1.01997e+06 3529.29 0.04 0.08 0.17 -1 -1 0.04 0.0333938 0.0289533 64 63 32 32 62 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_115.v common 4.98 vpr 63.68 MiB 0.05 7016 -1 -1 1 0.03 -1 -1 30740 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65208 32 32 407 319 1 190 96 17 17 289 -1 unnamed_device 24.8 MiB 0.59 846 15645 5217 8008 2420 63.7 MiB 0.14 0.00 3.76019 -138.157 -3.76019 3.76019 0.33 0.000776097 0.000720992 0.0584194 0.0541845 -1 -1 -1 -1 40 2973 41 6.95648e+06 463222 706193. 2443.58 2.39 0.237572 0.207353 26914 176310 -1 2139 22 2082 3061 234663 54691 4.28096 4.28096 -154.111 -4.28096 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0325639 0.0283912 91 65 64 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_116.v common 3.69 vpr 63.62 MiB 0.05 7200 -1 -1 1 0.03 -1 -1 30484 -1 -1 33 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65144 29 32 367 293 1 175 94 17 17 289 -1 unnamed_device 24.5 MiB 0.48 804 14791 5197 7141 2453 63.6 MiB 0.13 0.00 2.96363 -103.824 -2.96363 2.96363 0.33 0.000717323 0.000666661 0.052836 0.0490004 -1 -1 -1 -1 36 2587 50 6.95648e+06 477698 648988. 2245.63 1.33 0.215037 0.186915 26050 158493 -1 1915 21 1505 2184 169250 39755 3.09182 3.09182 -114.618 -3.09182 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0290436 0.0252849 87 62 56 29 58 29 + fixed_k6_frac_2ripple_N8_22nm.xml mult_117.v common 10.33 vpr 64.57 MiB 0.05 7276 -1 -1 1 0.03 -1 -1 30660 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66116 32 32 469 381 1 192 96 17 17 289 -1 unnamed_device 25.1 MiB 1.04 833 14769 5115 7175 2479 64.6 MiB 0.14 0.00 3.83239 -140.013 -3.83239 3.83239 0.33 0.000857044 0.000795576 0.0612803 0.0568805 -1 -1 -1 -1 40 3023 40 6.95648e+06 463222 706193. 2443.58 7.25 0.410817 0.353029 26914 176310 -1 2371 28 2471 3681 337820 82004 4.31396 4.31396 -161.444 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32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65156 32 32 418 338 1 182 93 17 17 289 -1 unnamed_device 24.7 MiB 0.49 1008 14373 5915 8161 297 63.6 MiB 0.12 0.00 3.76639 -134.285 -3.76639 3.76639 0.33 0.000782573 0.000725614 0.0562358 0.0521638 -1 -1 -1 -1 42 2357 30 6.95648e+06 419795 744469. 2576.02 5.40 0.336258 0.290782 27202 183097 -1 2106 20 1769 2470 198773 43978 3.72356 3.72356 -143.045 -3.72356 0 0 949917. 3286.91 0.04 0.08 0.14 -1 -1 0.04 0.0304509 0.0265932 85 92 28 28 92 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_120.v common 7.27 vpr 63.56 MiB 0.04 7128 -1 -1 1 0.03 -1 -1 30148 -1 -1 11 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65084 32 32 376 318 1 154 75 17 17 289 -1 unnamed_device 24.5 MiB 2.10 788 8607 3571 4894 142 63.6 MiB 0.09 0.00 2.94085 -114.746 -2.94085 2.94085 0.33 0.000713205 0.000662552 0.0414309 0.038531 -1 -1 -1 -1 34 2334 39 6.95648e+06 159232 618332. 2139.56 3.12 0.282429 0.243136 25762 151098 -1 1768 64 3392 4836 664245 272373 3.37362 3.37362 -130.543 -3.37362 0 0 787024. 2723.27 0.03 0.29 0.12 -1 -1 0.03 0.0739877 0.0634063 62 96 0 0 96 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_121.v common 8.27 vpr 64.46 MiB 0.05 7000 -1 -1 1 0.03 -1 -1 30348 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66012 32 32 401 316 1 188 94 17 17 289 -1 unnamed_device 25.0 MiB 0.77 1163 14578 4502 8146 1930 64.5 MiB 0.13 0.00 3.02515 -120.461 -3.02515 3.02515 0.33 0.000763621 0.000708978 0.0550876 0.0510326 -1 -1 -1 -1 38 2720 24 6.95648e+06 434271 678818. 2348.85 5.60 0.350026 0.302466 26626 170182 -1 2254 21 1648 2439 188931 40647 3.28132 3.28132 -131.597 -3.28132 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0314833 0.0274757 89 65 61 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_122.v common 4.40 vpr 64.71 MiB 0.05 7420 -1 -1 1 0.03 -1 -1 30792 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66268 32 32 500 382 1 222 101 17 17 289 -1 unnamed_device 25.0 MiB 1.00 1172 16081 5219 8297 2565 64.7 MiB 0.16 0.00 4.55644 -167.51 -4.55644 4.55644 0.33 0.000918369 0.000853658 0.0659489 0.0611756 -1 -1 -1 -1 42 3191 26 6.95648e+06 535600 744469. 2576.02 1.40 0.220628 0.193047 27202 183097 -1 2692 24 2813 4296 363308 73326 4.74021 4.74021 -177.029 -4.74021 0 0 949917. 3286.91 0.04 0.12 0.15 -1 -1 0.04 0.0425785 0.0370625 108 96 64 32 96 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_123.v common 3.89 vpr 63.56 MiB 0.04 6924 -1 -1 1 0.03 -1 -1 30152 -1 -1 12 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65084 30 32 246 229 1 115 74 17 17 289 -1 unnamed_device 24.0 MiB 0.31 487 9219 3932 4969 318 63.6 MiB 0.07 0.00 2.20646 -79.82 -2.20646 2.20646 0.33 0.000526981 0.000490756 0.033147 0.0308633 -1 -1 -1 -1 34 1402 21 6.95648e+06 173708 618332. 2139.56 1.80 0.193704 0.166313 25762 151098 -1 1112 20 754 1006 83380 21795 2.10948 2.10948 -84.4848 -2.10948 0 0 787024. 2723.27 0.03 0.05 0.12 -1 -1 0.03 0.021054 0.0182373 45 56 0 0 53 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_124.v common 6.01 vpr 63.31 MiB 0.04 6884 -1 -1 1 0.03 -1 -1 30416 -1 -1 12 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 30 32 296 244 1 141 74 17 17 289 -1 unnamed_device 24.3 MiB 1.22 714 11544 4893 6197 454 63.3 MiB 0.10 0.00 2.83685 -102.626 -2.83685 2.83685 0.33 0.000610989 0.000567908 0.0477614 0.044451 -1 -1 -1 -1 40 1762 24 6.95648e+06 173708 706193. 2443.58 2.95 0.279609 0.240749 26914 176310 -1 1496 21 1107 1674 190010 50002 3.09792 3.09792 -113.332 -3.09792 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0255234 0.0221883 58 34 60 30 30 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_125.v common 9.51 vpr 63.36 MiB 0.05 6876 -1 -1 1 0.03 -1 -1 30036 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64884 32 32 314 256 1 161 76 17 17 289 -1 unnamed_device 24.2 MiB 0.16 675 9356 3688 5198 470 63.4 MiB 0.09 0.00 2.98911 -115.235 -2.98911 2.98911 0.33 0.000645409 0.000600029 0.0399621 0.0371964 -1 -1 -1 -1 44 2328 48 6.95648e+06 173708 787024. 2723.27 7.46 0.332472 0.286341 27778 195446 -1 1719 22 1464 2394 196534 47359 3.50852 3.50852 -124.354 -3.50852 0 0 997811. 3452.63 0.04 0.08 0.15 -1 -1 0.04 0.0277999 0.0242654 66 34 64 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_126.v common 6.28 vpr 63.65 MiB 0.04 6996 -1 -1 1 0.03 -1 -1 30392 -1 -1 23 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65176 25 32 251 214 1 132 80 17 17 289 -1 unnamed_device 24.4 MiB 0.17 539 11776 4899 6026 851 63.6 MiB 0.11 0.00 3.0295 -88.2249 -3.0295 3.0295 0.33 0.000532627 0.000495578 0.0485384 0.0452027 -1 -1 -1 -1 32 1899 49 6.95648e+06 332941 586450. 2029.24 4.36 0.265617 0.228504 25474 144626 -1 1321 27 1201 1717 130920 30562 2.94452 2.94452 -95.9196 -2.94452 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0266542 0.0229613 61 34 50 25 25 25 + fixed_k6_frac_2ripple_N8_22nm.xml mult_127.v common 4.89 vpr 63.81 MiB 0.05 7120 -1 -1 1 0.03 -1 -1 30548 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65344 32 32 432 346 1 185 78 17 17 289 -1 unnamed_device 24.8 MiB 0.64 818 10868 4497 5970 401 63.8 MiB 0.12 0.00 3.72219 -135.01 -3.72219 3.72219 0.33 0.000804735 0.000747637 0.0553397 0.0514399 -1 -1 -1 -1 44 2570 26 6.95648e+06 202660 787024. 2723.27 2.33 0.297276 0.256946 27778 195446 -1 1944 21 1780 3078 212057 49868 3.97716 3.97716 -145.956 -3.97716 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65356 32 32 438 350 1 287 89 17 17 289 -1 unnamed_device 24.9 MiB 0.36 1233 11375 4637 6444 294 63.8 MiB 0.12 0.00 4.40054 -159.031 -4.40054 4.40054 0.33 0.000808814 0.000751192 0.0495967 0.0460748 -1 -1 -1 -1 42 3320 45 6.99608e+06 367892 744469. 2576.02 8.08 0.40144 0.344773 27202 183097 -1 2539 23 2414 2701 243477 63902 4.71111 4.71111 -173.083 -4.71111 0 0 949917. 3286.91 0.04 0.10 0.14 -1 -1 0.04 0.0359306 0.0313085 126 96 32 32 96 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_002.v common 6.30 vpr 63.62 MiB 0.05 7140 -1 -1 1 0.03 -1 -1 30596 -1 -1 25 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65152 30 32 409 330 1 257 87 17 17 289 -1 unnamed_device 24.6 MiB 0.35 1064 13335 4865 6427 2043 63.6 MiB 0.13 0.00 4.36632 -144.157 -4.36632 4.36632 0.34 0.000756055 0.000702402 0.0554984 0.0515527 -1 -1 -1 -1 50 2976 46 6.99608e+06 367892 902133. 3121.57 3.97 0.3417 0.294858 28642 213929 -1 2223 24 2360 3313 277236 67322 4.14654 4.14654 -145.435 -4.14654 0 0 1.08113e+06 3740.92 0.04 0.10 0.17 -1 -1 0.04 0.0346117 0.0301218 114 91 30 30 89 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_003.v common 3.87 vpr 64.24 MiB 0.05 7096 -1 -1 1 0.03 -1 -1 30464 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65784 32 32 387 309 1 241 85 17 17 289 -1 unnamed_device 24.6 MiB 0.50 1235 15523 5650 7863 2010 64.2 MiB 0.15 0.00 3.64599 -137.543 -3.64599 3.64599 0.33 0.000738812 0.000686248 0.0642401 0.0596489 -1 -1 -1 -1 40 3140 38 6.99608e+06 309029 706193. 2443.58 1.39 0.196641 0.172918 26914 176310 -1 2560 23 1930 2360 218707 46060 4.07156 4.07156 -152.256 -4.07156 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0329047 0.0286835 100 65 54 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_004.v common 4.56 vpr 63.96 MiB 0.04 7188 -1 -1 1 0.03 -1 -1 30420 -1 -1 20 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65500 29 32 343 267 1 201 81 17 17 289 -1 unnamed_device 24.4 MiB 0.38 847 11981 3747 5797 2437 64.0 MiB 0.11 0.00 3.84635 -127.029 -3.84635 3.84635 0.33 0.000686096 0.000637966 0.0493909 0.0459572 -1 -1 -1 -1 48 2100 31 6.99608e+06 294314 865456. 2994.66 2.34 0.265243 0.22956 28354 207349 -1 1595 22 1728 2558 187627 48523 3.83472 3.83472 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-1 -1 30516 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65200 32 32 402 316 1 251 93 17 17 289 -1 unnamed_device 24.6 MiB 0.32 1320 17313 6726 9274 1313 63.7 MiB 0.16 0.00 3.71319 -137.448 -3.71319 3.71319 0.33 0.000778887 0.000723269 0.0660236 0.0612872 -1 -1 -1 -1 40 3233 25 6.99608e+06 426755 706193. 2443.58 1.16 0.194054 0.170793 26914 176310 -1 2612 29 2337 3584 347075 89466 3.65466 3.65466 -141.846 -3.65466 0 0 926341. 3205.33 0.04 0.13 0.14 -1 -1 0.04 0.0404468 0.0350768 114 64 63 32 63 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_007.v common 3.06 vpr 63.43 MiB 0.05 6972 -1 -1 1 0.03 -1 -1 30628 -1 -1 17 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64948 27 32 269 226 1 156 76 17 17 289 -1 unnamed_device 24.4 MiB 0.35 793 10636 4431 5599 606 63.4 MiB 0.09 0.00 3.0735 -101.918 -3.0735 3.0735 0.33 0.000570738 0.00053129 0.039728 0.0369982 -1 -1 -1 -1 36 1866 21 6.99608e+06 250167 648988. 2245.63 0.94 0.126687 0.11096 26050 158493 -1 1715 21 1382 1942 186836 39004 3.21292 3.21292 -113.803 -3.21292 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.02326 0.0201542 68 34 54 27 27 27 + fixed_k6_frac_2uripple_N8_22nm.xml mult_008.v common 8.70 vpr 64.03 MiB 0.02 7064 -1 -1 1 0.03 -1 -1 30204 -1 -1 30 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65564 31 32 317 242 1 178 93 17 17 289 -1 unnamed_device 24.5 MiB 0.15 1053 15633 4964 8757 1912 64.0 MiB 0.13 0.00 2.8156 -108.673 -2.8156 2.8156 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65116 30 32 325 273 1 197 80 17 17 289 -1 unnamed_device 24.6 MiB 0.40 907 10916 3962 5331 1623 63.6 MiB 0.10 0.00 3.56495 -123.942 -3.56495 3.56495 0.33 0.000651363 0.000605652 0.0437044 0.0406188 -1 -1 -1 -1 38 2537 27 6.99608e+06 264882 678818. 2348.85 1.36 0.175213 0.152456 26626 170182 -1 1998 23 2038 2743 238850 68052 3.72141 3.72141 -139.11 -3.72141 0 0 902133. 3121.57 0.03 0.10 0.13 -1 -1 0.03 0.030142 0.0262821 86 63 30 30 60 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_012.v common 7.37 vpr 63.97 MiB 0.04 6988 -1 -1 1 0.03 -1 -1 30464 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65508 32 32 331 280 1 210 82 17 17 289 -1 unnamed_device 24.3 MiB 0.36 1146 9694 2399 6092 1203 64.0 MiB 0.09 0.00 3.0953 -120.741 -3.0953 3.0953 0.33 0.000658633 0.00061218 0.0384871 0.0357874 -1 -1 -1 -1 38 2566 46 6.99608e+06 264882 678818. 2348.85 5.11 0.323446 0.277602 26626 170182 -1 2137 22 1380 1520 128231 27765 3.32967 3.32967 -128.514 -3.32967 0 0 902133. 3121.57 0.03 0.07 0.14 -1 -1 0.03 0.028121 0.024473 85 65 25 25 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_013.v common 10.33 vpr 64.25 MiB 0.05 7132 -1 -1 1 0.03 -1 -1 30292 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65788 32 32 386 305 1 228 84 17 17 289 -1 unnamed_device 24.6 MiB 0.37 1223 5757 1291 4117 349 64.2 MiB 0.08 0.00 3.67909 -136.815 -3.67909 3.67909 0.33 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20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65808 32 32 401 315 1 244 84 17 17 289 -1 unnamed_device 24.7 MiB 1.24 1279 12711 5262 7205 244 64.3 MiB 0.13 0.00 3.55059 -132.497 -3.55059 3.55059 0.36 0.000770108 0.000715452 0.0560539 0.0520678 -1 -1 -1 -1 46 2879 20 6.99608e+06 294314 828058. 2865.25 2.46 0.273978 0.237341 28066 200906 -1 2421 23 2380 3740 245886 54523 3.60011 3.60011 -143.637 -3.60011 0 0 1.01997e+06 3529.29 0.04 0.10 0.16 -1 -1 0.04 0.0341191 0.0297451 108 63 64 32 62 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_017.v common 4.77 vpr 63.76 MiB 0.02 7160 -1 -1 1 0.03 -1 -1 30316 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65288 32 32 383 303 1 227 84 17 17 289 -1 unnamed_device 24.7 MiB 0.40 1158 9966 2544 6871 551 63.8 MiB 0.11 0.00 3.23714 -123.773 -3.23714 3.23714 0.34 0.000747831 0.000695384 0.0433814 0.0403347 -1 -1 -1 -1 40 2794 37 6.99608e+06 294314 706193. 2443.58 2.49 0.281413 0.24312 26914 176310 -1 2333 24 2014 2580 220082 47588 3.49952 3.49952 -139.157 -3.49952 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0342117 0.0298083 97 57 64 32 56 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_018.v common 7.84 vpr 63.98 MiB 0.04 6988 -1 -1 1 0.03 -1 -1 30124 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65512 32 32 339 284 1 218 83 17 17 289 -1 unnamed_device 24.3 MiB 0.39 1038 13763 4757 7523 1483 64.0 MiB 0.12 0.00 2.91805 -112.667 -2.91805 2.91805 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65772 32 32 366 283 1 215 97 17 17 289 -1 unnamed_device 24.7 MiB 0.31 958 14971 4356 8257 2358 64.2 MiB 0.13 0.00 4.00213 -141.214 -4.00213 4.00213 0.34 0.000727574 0.000676096 0.0518197 0.0481102 -1 -1 -1 -1 40 2774 47 6.99608e+06 485618 706193. 2443.58 2.09 0.207999 0.182008 26914 176310 -1 2148 21 1903 2841 256990 74288 4.3382 4.3382 -152.268 -4.3382 0 0 926341. 3205.33 0.04 0.10 0.14 -1 -1 0.04 0.0298727 0.026075 103 34 91 32 32 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_022.v common 5.19 vpr 63.86 MiB 0.05 7284 -1 -1 1 0.03 -1 -1 30560 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65396 32 32 460 375 1 304 91 17 17 289 -1 unnamed_device 24.9 MiB 0.47 1465 14983 5290 7359 2334 63.9 MiB 0.16 0.00 4.08533 -143.635 -4.08533 4.08533 0.34 0.000839968 0.000780835 0.0651483 0.0605954 -1 -1 -1 -1 48 3159 24 6.99608e+06 397324 865456. 2994.66 2.67 0.319591 0.276412 28354 207349 -1 2635 18 2010 2295 201415 50295 3.93832 3.93832 -148.233 -3.93832 0 0 1.05005e+06 3633.38 0.04 0.09 0.16 -1 -1 0.04 0.0309936 0.0270963 132 124 0 0 125 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_023.v common 2.82 vpr 63.16 MiB 0.04 6748 -1 -1 1 0.03 -1 -1 30556 -1 -1 16 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 26 32 198 186 1 125 74 17 17 289 -1 unnamed_device 23.7 MiB 0.28 507 10149 4254 5314 581 63.2 MiB 0.10 0.00 2.61785 -73.794 -2.61785 2.61785 0.33 0.00052234 0.000485184 0.0446462 0.041496 -1 -1 -1 -1 36 1335 24 6.99608e+06 235451 648988. 2245.63 0.79 0.116157 0.102295 26050 158493 -1 1082 18 603 752 57594 14524 2.30737 2.30737 -76.2676 -2.30737 0 0 828058. 2865.25 0.03 0.04 0.13 -1 -1 0.03 0.0165843 0.0144907 53 30 26 26 22 22 + fixed_k6_frac_2uripple_N8_22nm.xml mult_024.v common 8.97 vpr 63.15 MiB 0.04 6928 -1 -1 1 0.03 -1 -1 30204 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64668 32 32 333 251 1 181 78 17 17 289 -1 unnamed_device 24.3 MiB 0.84 917 12030 4510 6313 1207 63.2 MiB 0.12 0.00 3.49024 -127.709 -3.49024 3.49024 0.33 0.000882113 0.000820402 0.0535002 0.0496594 -1 -1 -1 -1 44 2529 42 6.99608e+06 206020 787024. 2723.27 6.18 0.337561 0.291936 27778 195446 -1 2012 21 1781 2845 248153 51952 3.59331 3.59331 -135.697 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64748 28 32 278 232 1 163 77 17 17 289 -1 unnamed_device 24.1 MiB 0.30 898 11813 3304 7441 1068 63.2 MiB 0.10 0.00 3.56439 -121.03 -3.56439 3.56439 0.33 0.000582792 0.00054258 0.0443042 0.0412529 -1 -1 -1 -1 42 2263 47 6.99608e+06 250167 744469. 2576.02 2.35 0.24824 0.213732 27202 183097 -1 1927 24 1129 1983 181139 37303 3.45416 3.45416 -123.961 -3.45416 0 0 949917. 3286.91 0.04 0.08 0.15 -1 -1 0.04 0.0269335 0.0233457 73 34 56 28 28 28 + fixed_k6_frac_2uripple_N8_22nm.xml mult_032.v common 5.09 vpr 63.59 MiB 0.03 6936 -1 -1 1 0.03 -1 -1 30364 -1 -1 11 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 65256 32 32 407 319 1 252 86 17 17 289 -1 unnamed_device 24.6 MiB 0.51 1090 16907 7321 9114 472 63.7 MiB 0.16 0.00 3.84815 -144.105 -3.84815 3.84815 0.33 0.000782806 0.000727461 0.071641 0.0665573 -1 -1 -1 -1 42 3318 46 6.99608e+06 323745 744469. 2576.02 10.46 0.418148 0.363014 27202 183097 -1 2456 29 2732 3557 313631 77793 4.36892 4.36892 -165.543 -4.36892 0 0 949917. 3286.91 0.04 0.12 0.15 -1 -1 0.04 0.0404369 0.035038 106 65 64 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_043.v common 9.40 vpr 64.26 MiB 0.05 7360 -1 -1 1 0.03 -1 -1 30788 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65800 32 32 496 380 1 313 90 17 17 289 -1 unnamed_device 25.2 MiB 0.50 1582 11547 3145 7670 732 64.3 MiB 0.14 0.00 4.28794 -157.671 -4.28794 4.28794 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65728 29 32 393 319 1 240 86 17 17 289 -1 unnamed_device 24.5 MiB 0.40 1231 14828 5539 7167 2122 64.2 MiB 0.14 0.00 3.52589 -122.812 -3.52589 3.52589 0.33 0.00073433 0.000681789 0.0606837 0.0563789 -1 -1 -1 -1 38 3483 25 6.99608e+06 367892 678818. 2348.85 9.08 0.331469 0.287412 26626 170182 -1 2762 20 2184 2966 249408 53951 3.62541 3.62541 -130.616 -3.62541 0 0 902133. 3121.57 0.03 0.09 0.14 -1 -1 0.03 0.0295916 0.0258818 111 88 29 29 85 29 + fixed_k6_frac_2uripple_N8_22nm.xml mult_067.v common 3.73 vpr 64.57 MiB 0.04 7140 -1 -1 1 0.03 -1 -1 30748 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66124 32 32 407 319 1 250 84 17 17 289 -1 unnamed_device 24.9 MiB 0.69 1211 14724 6283 7977 464 64.6 MiB 0.14 0.00 4.47024 -165.899 -4.47024 4.47024 0.33 0.000767102 0.000712252 0.0646944 0.0600997 -1 -1 -1 -1 42 3024 26 6.99608e+06 294314 744469. 2576.02 1.09 0.192098 0.168941 27202 183097 -1 2573 24 2506 3356 266293 59389 5.06801 5.06801 -179.766 -5.06801 0 0 949917. 3286.91 0.04 0.10 0.15 -1 -1 0.04 0.0352599 0.0307328 107 65 64 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_068.v common 11.50 vpr 64.34 MiB 0.04 7076 -1 -1 1 0.03 -1 -1 30708 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65880 32 32 407 319 1 249 85 17 17 289 -1 unnamed_device 24.7 MiB 0.65 1172 12919 4604 6148 2167 64.3 MiB 0.13 0.00 4.42939 -158.789 -4.42939 4.42939 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23 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65600 30 32 374 297 1 226 85 17 17 289 -1 unnamed_device 24.3 MiB 0.42 990 12733 4591 5781 2361 64.1 MiB 0.11 0.00 3.2948 -115.864 -3.2948 3.2948 0.33 0.000718725 0.000667694 0.0518642 0.0481849 -1 -1 -1 -1 50 2446 24 6.99608e+06 338461 902133. 3121.57 2.62 0.275226 0.238098 28642 213929 -1 1972 24 1918 2622 194283 48559 3.19707 3.19707 -121.425 -3.19707 0 0 1.08113e+06 3740.92 0.04 0.09 0.17 -1 -1 0.04 0.0328931 0.028642 100 60 60 30 57 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_072.v common 3.45 vpr 63.32 MiB 0.05 7124 -1 -1 1 0.04 -1 -1 30496 -1 -1 25 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64840 28 32 332 260 1 195 85 17 17 289 -1 unnamed_device 24.4 MiB 0.31 1003 6409 2401 3531 477 63.3 MiB 0.07 0.00 3.82205 -126.533 -3.82205 3.82205 0.33 0.00066289 0.000617122 0.0254201 0.0237124 -1 -1 -1 -1 38 2515 23 6.99608e+06 367892 678818. 2348.85 1.22 0.152501 0.132161 26626 170182 -1 2269 28 2236 3241 337187 98313 4.23992 4.23992 -143.46 -4.23992 0 0 902133. 3121.57 0.03 0.13 0.13 -1 -1 0.03 0.0342635 0.0297172 88 34 84 28 28 28 + fixed_k6_frac_2uripple_N8_22nm.xml mult_073.v common 4.81 vpr 63.40 MiB 0.04 6928 -1 -1 1 0.03 -1 -1 30212 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64920 30 32 325 273 1 204 80 17 17 289 -1 unnamed_device 24.3 MiB 0.39 1052 14012 5462 6811 1739 63.4 MiB 0.12 0.00 3.90653 -137.71 -3.90653 3.90653 0.33 0.000650497 0.000605108 0.0555379 0.0516654 -1 -1 -1 -1 44 2316 24 6.99608e+06 264882 787024. 2723.27 2.41 0.277551 0.240219 27778 195446 -1 2071 44 2896 3928 469909 173674 3.6477 3.6477 -132.698 -3.6477 0 0 997811. 3452.63 0.04 0.19 0.15 -1 -1 0.04 0.0489188 0.0420951 86 63 30 30 60 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_074.v common 4.70 vpr 63.59 MiB 0.05 7036 -1 -1 1 0.03 -1 -1 30320 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65112 32 32 361 308 1 237 84 17 17 289 -1 unnamed_device 24.4 MiB 0.40 1052 13626 4473 6882 2271 63.6 MiB 0.13 0.00 3.46859 -125.68 -3.46859 3.46859 0.33 0.000693365 0.000644071 0.0542717 0.0503975 -1 -1 -1 -1 44 2754 30 6.99608e+06 294314 787024. 2723.27 2.37 0.272055 0.235196 27778 195446 -1 2112 25 1909 2369 196518 45972 3.56566 3.56566 -129.624 -3.56566 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65920 32 32 407 319 1 249 87 17 17 289 -1 unnamed_device 24.7 MiB 0.31 1238 8727 2205 5715 807 64.4 MiB 0.10 0.00 4.31154 -156.569 -4.31154 4.31154 0.33 0.000773857 0.000719495 0.0379417 0.0352146 -1 -1 -1 -1 38 3518 32 6.99608e+06 338461 678818. 2348.85 1.70 0.175096 0.152396 26626 170182 -1 2958 25 2711 3680 352834 74473 4.68111 4.68111 -171.74 -4.68111 0 0 902133. 3121.57 0.03 0.12 0.13 -1 -1 0.03 0.0363705 0.0315752 105 65 64 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_077.v common 9.72 vpr 63.94 MiB 0.05 7144 -1 -1 1 0.03 -1 -1 30380 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65476 32 32 407 319 1 248 85 17 17 289 -1 unnamed_device 24.9 MiB 0.40 1289 7711 1655 5862 194 63.9 MiB 0.10 0.00 4.54847 -159.975 -4.54847 4.54847 0.33 0.000776719 0.000721466 0.0349948 0.0325352 -1 -1 -1 -1 46 3139 42 6.99608e+06 309029 828058. 2865.25 7.43 0.26383 0.227743 28066 200906 -1 2534 21 2174 2990 224195 48442 4.42484 4.42484 -162.7 -4.42484 0 0 1.01997e+06 3529.29 0.04 0.09 0.16 -1 -1 0.04 0.0320405 0.0280087 106 65 64 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_078.v common 4.02 vpr 63.72 MiB 0.05 7140 -1 -1 1 0.03 -1 -1 30380 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65248 32 32 399 315 1 250 86 17 17 289 -1 unnamed_device 24.7 MiB 0.42 1229 15017 6317 8415 285 63.7 MiB 0.15 0.00 3.80163 -136.823 -3.80163 3.80163 0.33 0.000763786 0.0007091 0.063708 0.059041 -1 -1 -1 -1 48 3288 34 6.99608e+06 323745 865456. 2994.66 1.63 0.225777 0.197283 28354 207349 -1 2629 24 2392 3459 274832 60108 3.65631 3.65631 -138.78 -3.65631 0 0 1.05005e+06 3633.38 0.04 0.10 0.16 -1 -1 0.04 0.0349164 0.0304211 104 65 60 30 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_079.v common 8.45 vpr 63.25 MiB 0.04 6940 -1 -1 1 0.03 -1 -1 30408 -1 -1 17 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 30 32 296 244 1 177 79 17 17 289 -1 unnamed_device 24.1 MiB 0.32 778 10726 3078 5744 1904 63.2 MiB 0.10 0.00 3.0932 -110.285 -3.0932 3.0932 0.33 0.000609563 0.0005667 0.0407636 0.0378909 -1 -1 -1 -1 38 2358 25 6.99608e+06 250167 678818. 2348.85 6.33 0.27111 0.234205 26626 170182 -1 1969 21 1586 2235 207800 45573 3.25447 3.25447 -123.974 -3.25447 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.0254469 0.0221535 73 34 60 30 30 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_080.v common 8.71 vpr 64.29 MiB 0.05 7044 -1 -1 1 0.03 -1 -1 30364 -1 -1 21 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65836 30 32 383 303 1 235 83 17 17 289 -1 unnamed_device 24.7 MiB 0.38 1198 14303 4504 8197 1602 64.3 MiB 0.14 0.00 4.62177 -156.286 -4.62177 4.62177 0.33 0.00073958 0.000687065 0.0614497 0.0571291 -1 -1 -1 -1 38 3098 34 6.99608e+06 309029 678818. 2348.85 6.34 0.361023 0.311836 26626 170182 -1 2603 19 2214 3134 240633 52283 4.62344 4.62344 -161.886 -4.62344 0 0 902133. 3121.57 0.03 0.09 0.14 -1 -1 0.03 0.0285404 0.0249821 102 63 60 30 60 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_081.v common 5.44 vpr 64.70 MiB 0.05 7348 -1 -1 1 0.03 -1 -1 30836 -1 -1 28 32 0 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27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66140 32 32 493 378 1 313 91 17 17 289 -1 unnamed_device 25.1 MiB 0.42 1492 16411 6100 7697 2614 64.6 MiB 0.18 0.00 4.57134 -160.625 -4.57134 4.57134 0.33 0.000911256 0.00084626 0.0764421 0.0710434 -1 -1 -1 -1 54 3582 33 6.99608e+06 397324 949917. 3286.91 4.50 0.428916 0.370043 29506 232905 -1 2767 24 2560 3729 282156 63406 4.55301 4.55301 -161.557 -4.55301 0 0 1.17392e+06 4061.99 0.04 0.11 0.18 -1 -1 0.04 0.0411328 0.0357344 137 95 62 31 95 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_097.v common 9.80 vpr 63.95 MiB 0.05 7324 -1 -1 1 0.03 -1 -1 30556 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65040 30 32 373 297 1 228 85 17 17 289 -1 unnamed_device 24.4 MiB 0.44 1206 13477 4531 6953 1993 63.5 MiB 0.13 0.00 3.74367 -132.253 -3.74367 3.74367 0.33 0.000719791 0.00066916 0.0547673 0.0509122 -1 -1 -1 -1 44 2895 25 6.99608e+06 338461 787024. 2723.27 2.38 0.281536 0.243742 27778 195446 -1 2424 19 1616 2330 170737 36982 3.71286 3.71286 -134.409 -3.71286 0 0 997811. 3452.63 0.04 0.07 0.15 -1 -1 0.04 0.0273469 0.0238845 99 61 58 30 58 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_102.v common 4.87 vpr 63.64 MiB 0.04 7016 -1 -1 1 0.03 -1 -1 30472 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65164 32 32 407 319 1 252 87 17 17 289 -1 unnamed_device 24.6 MiB 0.32 1123 16023 6720 8873 430 63.6 MiB 0.16 0.00 4.43684 -158.443 -4.43684 4.43684 0.33 0.000787457 0.000732047 0.0679509 0.0630974 -1 -1 -1 -1 50 3055 30 6.99608e+06 338461 902133. 3121.57 2.56 0.312864 0.271781 28642 213929 -1 2505 20 2207 2741 196823 45094 4.32121 4.32121 -161.091 -4.32121 0 0 1.08113e+06 3740.92 0.04 0.08 0.17 -1 -1 0.04 0.0306376 0.0267673 105 65 64 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_103.v common 8.07 vpr 63.64 MiB 0.05 7056 -1 -1 1 0.03 -1 -1 30448 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65168 32 32 405 318 1 253 85 17 17 289 -1 unnamed_device 24.6 MiB 0.39 1415 15337 5616 8436 1285 63.6 MiB 0.14 0.00 3.0955 -123.55 -3.0955 3.0955 0.33 0.00076674 0.000712295 0.0661456 0.0614431 -1 -1 -1 -1 40 2973 25 6.99608e+06 309029 706193. 2443.58 5.72 0.370882 0.318658 26914 176310 -1 2620 23 2150 2820 218958 48809 3.61382 3.61382 -140.947 -3.61382 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.033936 0.0295804 107 65 63 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_104.v common 3.63 vpr 63.34 MiB 0.04 6976 -1 -1 1 0.03 -1 -1 30580 -1 -1 17 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64864 29 32 287 238 1 170 78 17 17 289 -1 unnamed_device 24.2 MiB 0.32 666 8876 3323 4226 1327 63.3 MiB 0.08 0.00 3.1285 -107.074 -3.1285 3.1285 0.33 0.000610837 0.000568394 0.0342537 0.0319048 -1 -1 -1 -1 34 2262 30 6.99608e+06 250167 618332. 2139.56 1.55 0.16008 0.138268 25762 151098 -1 1537 21 1619 2035 155412 38445 3.36877 3.36877 -119.496 -3.36877 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0244987 0.0212967 72 34 58 29 29 29 + fixed_k6_frac_2uripple_N8_22nm.xml mult_105.v common 6.89 vpr 63.38 MiB 0.04 6968 -1 -1 1 0.03 -1 -1 30096 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64900 32 32 334 290 1 208 81 17 17 289 -1 unnamed_device 24.3 MiB 0.43 1166 6206 1355 4310 541 63.4 MiB 0.07 0.00 4.11048 -136.015 -4.11048 4.11048 0.33 0.000659925 0.000613867 0.0257308 0.0239495 -1 -1 -1 -1 40 2270 30 6.99608e+06 250167 706193. 2443.58 4.65 0.290196 0.248394 26914 176310 -1 2122 18 1181 1410 111217 24820 3.80255 3.80255 -133.933 -3.80255 0 0 926341. 3205.33 0.04 0.06 0.14 -1 -1 0.04 0.0241211 0.0210959 90 82 0 0 82 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_106.v common 3.73 vpr 64.18 MiB 0.04 7172 -1 -1 1 0.03 -1 -1 30372 -1 -1 19 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65716 31 32 365 281 1 217 82 17 17 289 -1 unnamed_device 24.5 MiB 0.32 1147 12898 4995 5597 2306 64.2 MiB 0.13 0.00 3.86834 -142 -3.86834 3.86834 0.33 0.000720904 0.000669682 0.0547434 0.0509063 -1 -1 -1 -1 36 3082 32 6.99608e+06 279598 648988. 2245.63 1.53 0.179425 0.157376 26050 158493 -1 2514 23 2327 3090 280116 62616 4.42821 4.42821 -161.244 -4.42821 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0318403 0.0277092 91 34 93 31 31 31 + fixed_k6_frac_2uripple_N8_22nm.xml mult_107.v common 3.26 vpr 63.38 MiB 0.02 7008 -1 -1 1 0.03 -1 -1 30424 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64896 29 32 297 254 1 181 80 17 17 289 -1 unnamed_device 24.2 MiB 0.31 830 9712 4017 5322 373 63.4 MiB 0.08 0.00 3.34864 -106.469 -3.34864 3.34864 0.33 0.000603881 0.000561558 0.0360932 0.0335729 -1 -1 -1 -1 40 1948 31 6.99608e+06 279598 706193. 2443.58 1.18 0.16134 0.13969 26914 176310 -1 1672 20 1255 1552 125286 28838 3.00031 3.00031 -107.625 -3.00031 0 0 926341. 3205.33 0.04 0.06 0.14 -1 -1 0.04 0.0241952 0.0210568 79 56 29 29 52 26 + fixed_k6_frac_2uripple_N8_22nm.xml mult_108.v common 3.50 vpr 63.43 MiB 0.04 6912 -1 -1 1 0.03 -1 -1 30260 -1 -1 15 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64948 32 32 314 256 1 188 79 17 17 289 -1 unnamed_device 24.2 MiB 0.36 895 9881 4069 5606 206 63.4 MiB 0.09 0.00 3.0973 -120.067 -3.0973 3.0973 0.33 0.000650451 0.00059899 0.040462 0.0376572 -1 -1 -1 -1 40 2218 28 6.99608e+06 220735 706193. 2443.58 1.25 0.172399 0.149807 26914 176310 -1 1932 28 2074 2680 291160 87479 3.45207 3.45207 -131.583 -3.45207 0 0 926341. 3205.33 0.04 0.11 0.14 -1 -1 0.04 0.0330448 0.0286302 75 34 64 32 32 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_109.v common 8.37 vpr 63.55 MiB 0.05 7192 -1 -1 1 0.03 -1 -1 30488 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65076 31 32 387 307 1 238 84 17 17 289 -1 unnamed_device 24.6 MiB 0.38 1114 13626 4545 6760 2321 63.6 MiB 0.13 0.00 3.60415 -130.344 -3.60415 3.60415 0.33 0.000744748 0.000692384 0.0583437 0.0540895 -1 -1 -1 -1 38 3132 24 6.99608e+06 309029 678818. 2348.85 6.02 0.349426 0.301337 26626 170182 -1 2521 25 2729 3732 309316 66755 3.77881 3.77881 -142.753 -3.77881 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66036 32 32 383 307 1 232 85 17 17 289 -1 unnamed_device 24.9 MiB 0.41 1097 14035 5866 7813 356 64.5 MiB 0.13 0.00 3.64125 -130.197 -3.64125 3.64125 0.33 0.000735643 0.000683183 0.0582656 0.0540201 -1 -1 -1 -1 44 2644 37 6.99608e+06 309029 787024. 2723.27 1.21 0.188576 0.16524 27778 195446 -1 2227 21 1685 2220 176554 44126 3.82396 3.82396 -138.43 -3.82396 0 0 997811. 3452.63 0.04 0.08 0.15 -1 -1 0.04 0.030419 0.0265708 102 65 52 26 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_112.v common 3.92 vpr 63.90 MiB 0.05 7264 -1 -1 1 0.03 -1 -1 30472 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65436 31 32 422 339 1 272 88 17 17 289 -1 unnamed_device 24.8 MiB 0.42 1424 15103 5056 7808 2239 63.9 MiB 0.15 0.00 4.24588 -151.83 -4.24588 4.24588 0.33 0.000788099 0.000731914 0.0637956 0.0591968 -1 -1 -1 -1 38 3816 42 6.99608e+06 367892 678818. 2348.85 1.54 0.2123 0.185979 26626 170182 -1 2995 20 2675 3652 293854 62663 4.19435 4.19435 -157.692 -4.19435 0 0 902133. 3121.57 0.03 0.10 0.13 -1 -1 0.03 0.0314511 0.0275132 119 93 31 31 92 31 + fixed_k6_frac_2uripple_N8_22nm.xml mult_113.v common 3.59 vpr 64.04 MiB 0.02 7004 -1 -1 1 0.03 -1 -1 30356 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65580 32 32 333 279 1 208 82 17 17 289 -1 unnamed_device 24.4 MiB 0.38 1167 13076 3755 7840 1481 64.0 MiB 0.12 0.00 3.22189 -126.373 -3.22189 3.22189 0.33 0.000671703 0.000618407 0.0512917 0.0475594 -1 -1 -1 -1 38 2940 44 6.99608e+06 264882 678818. 2348.85 1.37 0.173524 0.151669 26626 170182 -1 2358 19 1606 2229 178314 38534 3.34676 3.34676 -129.325 -3.34676 0 0 902133. 3121.57 0.03 0.07 0.13 -1 -1 0.03 0.0253234 0.0221217 85 61 32 32 60 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_114.v common 4.53 vpr 63.43 MiB 0.04 6888 -1 -1 1 0.03 -1 -1 30116 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64952 32 32 339 283 1 211 82 17 17 289 -1 unnamed_device 24.3 MiB 0.36 917 12364 4451 6156 1757 63.4 MiB 0.11 0.00 3.63989 -128.991 -3.63989 3.63989 0.33 0.00067204 0.000624224 0.0490385 0.0456041 -1 -1 -1 -1 42 2577 26 6.99608e+06 264882 744469. 2576.02 2.33 0.265612 0.229418 27202 183097 -1 1974 21 1463 1798 131008 32318 3.79276 3.79276 -142.235 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-1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65112 29 32 367 293 1 220 84 17 17 289 -1 unnamed_device 24.5 MiB 0.36 1112 11430 4239 5486 1705 63.6 MiB 0.11 0.00 3.04335 -110.206 -3.04335 3.04335 0.33 0.00071264 0.000659741 0.0475405 0.0441043 -1 -1 -1 -1 34 3058 35 6.99608e+06 338461 618332. 2139.56 4.45 0.300304 0.259023 25762 151098 -1 2487 20 1867 2516 191914 44595 3.32957 3.32957 -122.999 -3.32957 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0281985 0.0246124 101 62 56 29 58 29 + fixed_k6_frac_2uripple_N8_22nm.xml mult_117.v common 5.16 vpr 64.54 MiB 0.05 7184 -1 -1 1 0.03 -1 -1 30644 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66088 32 32 469 381 1 309 91 17 17 289 -1 unnamed_device 25.1 MiB 0.50 1451 17635 5731 9015 2889 64.5 MiB 0.18 0.00 4.9146 -172.985 -4.9146 4.9146 0.33 0.00087653 0.000815367 0.0780793 0.0726099 -1 -1 -1 -1 40 4076 36 6.99608e+06 397324 706193. 2443.58 2.78 0.372763 0.323318 26914 176310 -1 3032 23 2765 3245 274464 62366 5.7329 5.7329 -198.714 -5.7329 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0212485 0.0187799 132 127 0 0 128 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_118.v common 6.87 vpr 63.40 MiB 0.05 6944 -1 -1 1 0.03 -1 -1 30284 -1 -1 12 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 31 32 259 212 1 144 75 17 17 289 -1 unnamed_device 24.0 MiB 0.62 607 9713 4010 5428 275 63.4 MiB 0.08 0.00 2.81885 -98.97 -2.81885 2.81885 0.33 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65208 32 32 274 306 1 198 84 17 17 289 -1 unnamed_device 23.9 MiB 0.62 1234 12711 4362 6553 1796 63.7 MiB 0.13 0.00 6.93533 -144.489 -6.93533 6.93533 0.33 0.000900392 0.000834539 0.0661293 0.0613616 -1 -1 -1 -1 46 2868 32 6.79088e+06 269440 828058. 2865.25 2.76 0.335933 0.290814 27406 200422 -1 2349 17 1287 4024 196793 48150 5.78973 5.78973 -132.886 -5.78973 0 0 1.01997e+06 3529.29 0.04 0.08 0.16 -1 -1 0.04 0.0330675 0.0291265 135 180 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_004.v common 4.17 vpr 63.22 MiB 0.04 6708 -1 -1 12 0.33 -1 -1 32832 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65172 31 32 264 296 1 193 86 17 17 289 -1 unnamed_device 23.9 MiB 0.60 1220 9536 2544 6437 555 63.6 MiB 0.10 0.00 6.78954 -136.027 -6.78954 6.78954 0.33 0.000844903 0.000781822 0.0460384 0.0425566 -1 -1 -1 -1 38 3274 32 6.79088e+06 309856 678818. 2348.85 1.50 0.224921 0.194565 25966 169698 -1 2633 17 1198 3613 193992 44793 5.78203 5.78203 -131.142 -5.78203 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0310318 0.0272896 124 173 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_009.v common 5.81 vpr 62.96 MiB 0.04 6700 -1 -1 12 0.17 -1 -1 32412 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65840 32 32 361 393 1 259 92 17 17 289 -1 unnamed_device 24.7 MiB 0.72 1675 9821 2468 6259 1094 64.3 MiB 0.12 0.00 8.49462 -180.844 -8.49462 8.49462 0.33 0.00113116 0.00104754 0.0584007 0.0540699 -1 -1 -1 -1 32 5477 46 6.79088e+06 377216 586450. 2029.24 6.32 0.463813 0.400212 24814 144142 -1 4152 58 4745 16433 1624290 646059 8.00188 8.00188 -180.946 -8.00188 0 0 744469. 2576.02 0.03 0.62 0.12 -1 -1 0.03 0.121806 0.104932 187 267 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_058.v common 10.53 vpr 63.98 MiB 0.04 6704 -1 -1 13 0.29 -1 -1 32716 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 32 32 238 270 1 167 80 17 17 289 -1 unnamed_device 23.8 MiB 0.34 1009 10056 3067 4893 2096 63.3 MiB 0.10 0.00 6.37179 -142.275 -6.37179 6.37179 0.33 0.000734437 0.000680156 0.0458146 0.0424751 -1 -1 -1 -1 30 2840 28 6.79088e+06 215552 556674. 1926.21 2.68 0.234692 0.203008 24526 138013 -1 2125 20 991 2582 119455 29953 5.78618 5.78618 -138.331 -5.78618 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0297151 0.0260505 100 144 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_063.v common 5.58 vpr 63.25 MiB 0.05 6996 -1 -1 12 0.29 -1 -1 32852 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64712 32 32 277 309 1 207 86 17 17 289 -1 unnamed_device 24.2 MiB 0.60 1382 8591 2239 5858 494 63.2 MiB 0.10 0.00 7.91581 -161.259 -7.91581 7.91581 0.33 0.000913371 0.000847226 0.0450635 0.0417541 -1 -1 -1 -1 38 3350 25 6.79088e+06 296384 678818. 2348.85 2.32 0.2926 0.252355 25966 169698 -1 2787 16 1251 3857 189868 44623 7.15279 7.15279 -153.16 -7.15279 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0321713 0.0284014 138 183 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_078.v common 9.96 vpr 63.31 MiB 0.05 6804 -1 -1 13 0.33 -1 -1 33256 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64940 32 32 277 309 1 203 85 17 17 289 -1 unnamed_device 24.4 MiB 0.81 1340 13849 4059 7638 2152 63.4 MiB 0.14 0.00 7.74106 -161.688 -7.74106 7.74106 0.33 0.000906466 0.00084094 0.0714624 0.0662797 -1 -1 -1 -1 34 3696 38 6.79088e+06 282912 618332. 2139.56 1.21 0.234614 0.20537 25102 150614 -1 2984 20 1482 4209 226980 52735 6.74184 6.74184 -158.649 -6.74184 0 0 787024. 2723.27 0.03 0.09 0.12 -1 -1 0.03 0.037172 0.0325816 135 183 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_116.v common 3.73 vpr 62.84 MiB 0.02 6852 -1 -1 11 0.19 -1 -1 32724 -1 -1 22 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64616 32 32 235 267 1 174 85 17 17 289 -1 unnamed_device 24.0 MiB 0.42 1119 12361 3329 7454 1578 63.1 MiB 0.11 0.00 7.36852 -166.004 -7.36852 7.36852 0.33 0.000750919 0.000696197 0.0528367 0.0489875 -1 -1 -1 -1 36 2782 17 6.79088e+06 282912 648988. 2245.63 2.17 0.273945 0.237408 25390 158009 -1 2366 14 955 2497 138037 32540 6.58432 6.58432 -158.848 -6.58432 0 0 828058. 2865.25 0.03 0.06 0.12 -1 -1 0.03 0.0242351 0.0214443 107 141 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_121.v common 5.48 vpr 63.56 MiB 0.05 6808 -1 -1 12 0.22 -1 -1 32888 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65088 32 32 265 297 1 192 85 17 17 289 -1 unnamed_device 23.8 MiB 1.07 1078 14593 5070 7208 2315 63.6 MiB 0.15 0.00 7.08202 -153.624 -7.08202 7.08202 0.33 0.000866045 0.000801126 0.0729181 0.0675734 -1 -1 -1 -1 42 2583 22 6.79088e+06 282912 744469. 2576.02 2.28 0.325852 0.282352 26542 182613 -1 2078 15 1025 2965 145160 36401 5.91852 5.91852 -141.174 -5.91852 0 0 949917. 3286.91 0.04 0.07 0.15 -1 -1 0.04 0.0306689 0.0271112 125 171 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_122.v common 5.02 vpr 64.26 MiB 0.05 6984 -1 -1 15 0.47 -1 -1 32836 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65804 32 32 344 376 1 252 91 17 17 289 -1 unnamed_device 24.5 MiB 0.82 1721 10291 2790 6459 1042 64.3 MiB 0.13 0.00 9.60297 -194.922 -9.60297 9.60297 0.33 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 30 32 409 330 1 192 86 17 17 289 -1 unnamed_device 24.2 MiB 2.95 1037 12749 4416 6197 2136 63.3 MiB 0.14 0.00 4.18449 -135.92 -4.18449 4.18449 0.33 0.000755725 0.000701569 0.0532811 0.0494806 -1 -1 -1 -1 32 2593 34 6.87369e+06 335372 586450. 2029.24 0.65 0.154987 0.136111 25474 144626 -1 1987 22 1738 2948 159843 42253 3.7121 3.7121 -137.584 -3.7121 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0313519 0.0271426 141 91 30 30 89 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_003.v common 5.86 vpr 63.40 MiB 0.04 7016 -1 -1 1 0.03 -1 -1 30396 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 32 32 387 309 1 191 100 17 17 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Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64884 27 32 269 226 1 146 79 17 17 289 -1 unnamed_device 23.7 MiB 1.93 818 12923 4188 6960 1775 63.4 MiB 0.12 0.00 3.47075 -103.849 -3.47075 3.47075 0.33 0.000565726 0.000526652 0.0450654 0.0419682 -1 -1 -1 -1 32 1806 29 6.87369e+06 279477 586450. 2029.24 1.47 0.222765 0.191829 25474 144626 -1 1564 22 1168 2001 119983 28902 2.91296 2.91296 -103.344 -2.91296 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0235488 0.0203495 103 34 54 27 27 27 + fixed_k6_frac_ripple_N8_22nm.xml mult_008.v common 4.45 vpr 63.29 MiB 0.05 7088 -1 -1 1 0.03 -1 -1 30228 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64808 31 32 317 242 1 187 98 17 17 289 -1 unnamed_device 24.3 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 32 32 331 280 1 161 96 17 17 289 -1 unnamed_device 24.0 MiB 1.62 993 13236 3578 8478 1180 63.2 MiB 0.13 0.00 3.48455 -118.435 -3.48455 3.48455 0.33 0.000657594 0.000609717 0.0418718 0.0388044 -1 -1 -1 -1 32 2209 21 6.87369e+06 447163 586450. 2029.24 1.52 0.228799 0.197263 25474 144626 -1 1846 20 1139 1945 130898 31151 2.66236 2.66236 -110.707 -2.66236 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0247864 0.0214565 116 65 25 25 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_013.v common 6.98 vpr 63.43 MiB 0.05 7136 -1 -1 1 0.03 -1 -1 30300 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64948 32 32 386 305 1 195 99 17 17 289 -1 unnamed_device 24.3 MiB 4.17 977 19707 6512 10053 3142 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0.04 7144 -1 -1 1 0.03 -1 -1 30520 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64972 32 32 401 315 1 200 86 17 17 289 -1 unnamed_device 24.3 MiB 2.82 1115 15773 4732 9095 1946 63.4 MiB 0.16 0.00 3.52575 -125.388 -3.52575 3.52575 0.33 0.000772531 0.000717559 0.0662559 0.0615514 -1 -1 -1 -1 32 2906 30 6.87369e+06 307425 586450. 2029.24 2.19 0.312394 0.27116 25474 144626 -1 2427 22 2029 3433 234126 57574 3.09026 3.09026 -131.793 -3.09026 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0317234 0.0275455 145 63 64 32 62 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_017.v common 6.95 vpr 63.33 MiB 0.05 7144 -1 -1 1 0.03 -1 -1 30240 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64852 32 32 383 303 1 193 103 17 17 289 -1 unnamed_device 24.3 MiB 4.17 1033 10225 2381 7241 603 63.3 MiB 0.09 0.00 3.55695 -125.38 -3.55695 3.55695 0.33 0.000527944 0.000479759 0.0252969 0.0231207 -1 -1 -1 -1 30 2330 25 6.87369e+06 544980 556674. 1926.21 0.98 0.116663 0.100789 25186 138497 -1 1916 23 1479 2321 129964 32109 2.88996 2.88996 -119.301 -2.88996 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0315576 0.0273331 148 57 64 32 56 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_018.v common 5.64 vpr 63.15 MiB 0.04 6840 -1 -1 1 0.03 -1 -1 30132 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 32 32 339 284 1 165 94 17 17 289 -1 unnamed_device 24.2 MiB 2.29 861 16495 5119 8899 2477 63.1 MiB 0.15 0.00 2.97721 -105.51 -2.97721 2.97721 0.33 0.000672635 0.00062511 0.0542118 0.0503248 -1 -1 -1 -1 32 2032 26 6.87369e+06 419215 586450. 2029.24 1.52 0.22393 0.194297 25474 144626 -1 1525 20 1283 2179 122131 32242 2.16112 2.16112 -94.0688 -2.16112 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0255937 0.0221844 118 65 29 29 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_019.v common 3.20 vpr 63.31 MiB 0.04 6716 -1 -1 1 0.03 -1 -1 30272 -1 -1 15 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64832 30 32 226 208 1 119 77 17 17 289 -1 unnamed_device 23.7 MiB 0.83 708 9042 3454 4658 930 63.3 MiB 0.07 0.00 2.76391 -93.2661 -2.76391 2.76391 0.33 0.00050239 0.000467889 0.0294658 0.0274435 -1 -1 -1 -1 32 1457 18 6.87369e+06 209608 586450. 2029.24 0.68 0.101206 0.0883047 25474 144626 -1 1255 15 579 856 60701 14448 1.84342 1.84342 -82.8045 -1.84342 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0155573 0.0135349 73 34 24 24 30 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_020.v common 4.00 vpr 63.68 MiB 0.04 6924 -1 -1 1 0.03 -1 -1 30368 -1 -1 19 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65208 31 32 335 280 1 165 82 17 17 289 -1 unnamed_device 24.0 MiB 1.56 906 13610 3953 7473 2184 63.7 MiB 0.13 0.00 4.23969 -129.95 -4.23969 4.23969 0.34 0.000673921 0.00062764 0.053103 0.0494269 -1 -1 -1 -1 32 2070 22 6.87369e+06 265503 586450. 2029.24 0.57 0.131366 0.116249 25474 144626 -1 1697 15 912 1358 93698 21781 3.1389 3.1389 -120.145 -3.1389 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.02054 0.017889 113 64 31 31 62 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_021.v common 3.75 vpr 63.82 MiB 0.04 7052 -1 -1 1 0.03 -1 -1 30136 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65352 32 32 366 283 1 197 102 17 17 289 -1 unnamed_device 24.2 MiB 1.07 1119 17952 5305 10368 2279 63.8 MiB 0.16 0.00 4.22105 -144.562 -4.22105 4.22105 0.33 0.000731228 0.000679596 0.0578907 0.0537838 -1 -1 -1 -1 32 2576 22 6.87369e+06 531006 586450. 2029.24 0.81 0.165502 0.145799 25474 144626 -1 2079 21 1588 2325 140087 33143 3.5888 3.5888 -137.535 -3.5888 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0287367 0.024956 151 34 91 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_022.v common 6.10 vpr 63.68 MiB 0.05 7192 -1 -1 1 0.03 -1 -1 30620 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65204 32 32 460 375 1 199 104 17 17 289 -1 unnamed_device 24.6 MiB 2.80 1172 19624 5698 11079 2847 63.7 MiB 0.15 0.00 3.80272 -131.055 -3.80272 3.80272 0.35 0.000381998 0.000351029 0.0474611 0.0436295 -1 -1 -1 -1 28 3282 32 6.87369e+06 558954 531479. 1839.03 1.38 0.160013 0.139393 24610 126494 -1 2623 24 1856 3107 291154 78871 3.855 3.855 -141.694 -3.855 0 0 648988. 2245.63 0.03 0.11 0.10 -1 -1 0.03 0.0364804 0.0313998 154 124 0 0 125 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_023.v common 4.68 vpr 63.19 MiB 0.04 6700 -1 -1 1 0.02 -1 -1 30708 -1 -1 18 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64708 26 32 198 186 1 109 76 17 17 289 -1 unnamed_device 23.7 MiB 1.66 596 9676 3280 4936 1460 63.2 MiB 0.07 0.00 2.74191 -77.6931 -2.74191 2.74191 0.33 0.000442931 0.000412026 0.0281821 0.0262149 -1 -1 -1 -1 32 1249 22 6.87369e+06 251529 586450. 2029.24 1.29 0.154764 0.133132 25474 144626 -1 1132 20 607 999 75312 18294 2.03582 2.03582 -76.1177 -2.03582 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0171715 0.0148634 70 30 26 26 22 22 + fixed_k6_frac_ripple_N8_22nm.xml mult_024.v common 4.99 vpr 63.30 MiB 0.04 6932 -1 -1 1 0.03 -1 -1 30112 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64820 32 32 333 251 1 196 87 17 17 289 -1 unnamed_device 24.3 MiB 1.41 1189 15831 5026 8598 2207 63.3 MiB 0.16 0.00 4.1666 -144.095 -4.1666 4.1666 0.33 0.000685072 0.000637317 0.0587906 0.0546903 -1 -1 -1 -1 32 2811 25 6.87369e+06 321398 586450. 2029.24 1.67 0.263581 0.229024 25474 144626 -1 2285 22 1540 2599 177810 42595 3.8734 3.8734 -148.875 -3.8734 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.028838 0.0250352 143 3 122 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_025.v common 3.53 vpr 63.11 MiB 0.04 6796 -1 -1 1 0.03 -1 -1 30424 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64628 32 32 199 182 1 122 77 17 17 289 -1 unnamed_device 23.7 MiB 0.60 804 11324 4283 5922 1119 63.1 MiB 0.09 0.00 2.37678 -91.0069 -2.37678 2.37678 0.33 0.000467352 0.000434509 0.0338642 0.0314978 -1 -1 -1 -1 30 1526 21 6.87369e+06 181660 556674. 1926.21 1.26 0.142626 0.124141 25186 138497 -1 1276 15 532 689 48402 11520 1.93872 1.93872 -87.9909 -1.93872 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0146748 0.012876 72 3 53 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_026.v common 5.40 vpr 63.95 MiB 0.05 7080 -1 -1 1 0.03 -1 -1 30516 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65480 32 32 376 288 1 202 101 17 17 289 -1 unnamed_device 24.2 MiB 0.88 969 13261 3427 8940 894 63.9 MiB 0.14 0.00 4.32457 -145.823 -4.32457 4.32457 0.33 0.000742868 0.000691175 0.0440029 0.040873 -1 -1 -1 -1 28 3100 47 6.87369e+06 517032 531479. 1839.03 2.61 0.269503 0.233255 24610 126494 -1 2411 23 2057 3269 242126 62287 4.5109 4.5109 -157.957 -4.5109 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0315161 0.0273367 155 34 96 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_027.v common 4.00 vpr 63.46 MiB 0.04 7080 -1 -1 1 0.03 -1 -1 30120 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64980 32 32 337 253 1 198 101 17 17 289 -1 unnamed_device 24.4 MiB 0.92 1115 9736 2184 6547 1005 63.5 MiB 0.11 0.00 3.53495 -124.767 -3.53495 3.53495 0.33 0.000708282 0.000654294 0.0311928 0.0289347 -1 -1 -1 -1 30 2469 22 6.87369e+06 517032 556674. 1926.21 1.28 0.189028 0.163454 25186 138497 -1 2002 21 1395 2409 133701 32486 2.89016 2.89016 -117.09 -2.89016 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0278384 0.0241707 151 3 124 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_028.v common 6.37 vpr 64.21 MiB 0.05 7124 -1 -1 1 0.03 -1 -1 30532 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65752 32 32 407 319 1 202 104 17 17 289 -1 unnamed_device 24.7 MiB 1.13 1055 13036 3588 8403 1045 64.2 MiB 0.14 0.00 4.2809 -144.104 -4.2809 4.2809 0.33 0.00078174 0.000726997 0.0437557 0.0405274 -1 -1 -1 -1 28 3474 41 6.87369e+06 558954 531479. 1839.03 3.28 0.255436 0.22109 24610 126494 -1 2528 22 2162 3811 289506 69194 4.03971 4.03971 -155.286 -4.03971 0 0 648988. 2245.63 0.03 0.10 0.10 -1 -1 0.03 0.0313674 0.0271723 156 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_029.v common 4.15 vpr 63.41 MiB 0.04 6824 -1 -1 1 0.03 -1 -1 30108 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64928 32 32 294 246 1 157 80 17 17 289 -1 unnamed_device 24.0 MiB 1.15 754 11948 3802 6412 1734 63.4 MiB 0.11 0.00 3.07332 -107.198 -3.07332 3.07332 0.33 0.000611879 0.000569338 0.0445328 0.0414247 -1 -1 -1 -1 30 1864 23 6.87369e+06 223581 556674. 1926.21 1.25 0.186041 0.161539 25186 138497 -1 1405 19 817 1358 76499 19622 2.60936 2.60936 -106.109 -2.60936 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.022867 0.0198891 104 34 54 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_030.v common 3.52 vpr 63.02 MiB 0.04 6976 -1 -1 1 0.03 -1 -1 30088 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64532 30 32 296 244 1 160 81 17 17 289 -1 unnamed_device 24.0 MiB 1.13 897 12156 3930 6335 1891 63.0 MiB 0.12 0.00 3.54295 -120.85 -3.54295 3.54295 0.33 0.000612449 0.000569801 0.0444946 0.0413873 -1 -1 -1 -1 32 1986 25 6.87369e+06 265503 586450. 2029.24 0.56 0.119501 0.105273 25474 144626 -1 1615 22 1274 1935 140595 32787 2.83966 2.83966 -116.899 -2.83966 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0256004 0.0221305 109 34 60 30 30 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_031.v common 4.51 vpr 63.31 MiB 0.05 6888 -1 -1 1 0.03 -1 -1 30252 -1 -1 20 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 28 32 278 232 1 150 80 17 17 289 -1 unnamed_device 23.6 MiB 1.22 721 12808 3405 8634 769 63.3 MiB 0.12 0.00 3.48175 -105.896 -3.48175 3.48175 0.33 0.00058427 0.00054379 0.0457607 0.0426031 -1 -1 -1 -1 32 1911 27 6.87369e+06 279477 586450. 2029.24 1.47 0.196705 0.170264 25474 144626 -1 1576 20 1146 1943 113904 29907 3.02426 3.02426 -108.885 -3.02426 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226945 0.0194929 104 34 56 28 28 28 + fixed_k6_frac_ripple_N8_22nm.xml mult_032.v common 4.26 vpr 63.03 MiB 0.04 6784 -1 -1 1 0.03 -1 -1 30372 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64544 32 32 283 225 1 168 83 17 17 289 -1 unnamed_device 23.9 MiB 1.55 989 9983 2839 5973 1171 63.0 MiB 0.10 0.00 3.52575 -126.669 -3.52575 3.52575 0.33 0.00061684 0.00057454 0.0357093 0.0332609 -1 -1 -1 -1 32 2281 37 6.87369e+06 265503 586450. 2029.24 0.85 0.141467 0.123329 25474 144626 -1 1904 21 1562 2639 186474 42654 2.76766 2.76766 -121.308 -2.76766 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0248173 0.0215091 115 3 96 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_033.v common 3.22 vpr 63.66 MiB 0.05 6980 -1 -1 1 0.03 -1 -1 30248 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65188 31 32 303 249 1 163 95 17 17 289 -1 unnamed_device 24.0 MiB 0.78 845 15215 4592 7994 2629 63.7 MiB 0.14 0.00 3.50375 -117.395 -3.50375 3.50375 0.33 0.000626809 0.000582838 0.0461669 0.0429028 -1 -1 -1 -1 32 2080 22 6.87369e+06 447163 586450. 2029.24 0.58 0.119837 0.105722 25474 144626 -1 1622 23 1301 2198 133984 33915 2.85066 2.85066 -110.644 -2.85066 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0269005 0.0233078 119 34 61 31 31 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_034.v common 5.52 vpr 63.15 MiB 0.03 6928 -1 -1 1 0.03 -1 -1 30152 -1 -1 33 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 29 32 312 264 1 154 94 17 17 289 -1 unnamed_device 23.9 MiB 2.36 922 12022 3402 7419 1201 63.1 MiB 0.11 0.00 2.87654 -95.4564 -2.87654 2.87654 0.33 0.000623822 0.000578701 0.0370939 0.034354 -1 -1 -1 -1 32 1829 20 6.87369e+06 461137 586450. 2029.24 1.44 0.215994 0.185864 25474 144626 -1 1603 17 984 1705 94014 23813 2.02952 2.02952 -88.5363 -2.02952 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65556 32 32 403 317 1 200 103 17 17 289 -1 unnamed_device 24.5 MiB 2.69 1161 9984 2299 6887 798 64.0 MiB 0.12 0.00 3.66173 -128.462 -3.66173 3.66173 0.33 0.000770426 0.000715526 0.0351384 0.0325169 -1 -1 -1 -1 28 2693 27 6.87369e+06 544980 531479. 1839.03 1.55 0.243432 0.209689 24610 126494 -1 2360 19 1925 2873 182260 45046 2.99616 2.99616 -129.298 -2.99616 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0280704 0.024391 154 65 62 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_037.v common 6.30 vpr 63.27 MiB 0.05 7076 -1 -1 1 0.03 -1 -1 30508 -1 -1 31 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64784 31 32 353 302 1 160 94 17 17 289 -1 unnamed_device 24.0 MiB 3.14 911 12661 3506 8208 947 63.3 MiB 0.12 0.00 3.47075 -118.785 -3.47075 3.47075 0.33 0.000679038 0.000629437 0.0422431 0.0391776 -1 -1 -1 -1 28 2101 21 6.87369e+06 433189 531479. 1839.03 1.35 0.218656 0.18868 24610 126494 -1 1923 21 1291 2156 139833 35089 3.06856 3.06856 -119.491 -3.06856 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0268995 0.0232219 116 90 0 0 89 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_038.v common 5.13 vpr 63.39 MiB 0.05 7148 -1 -1 1 0.03 -1 -1 30360 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 31 32 391 309 1 195 86 17 17 289 -1 unnamed_device 24.2 MiB 2.27 1158 14639 5381 7464 1794 63.4 MiB 0.17 0.00 3.53495 -122.885 -3.53495 3.53495 0.33 0.000742938 0.00068998 0.0600531 0.0557636 -1 -1 -1 -1 32 2673 35 6.87369e+06 321398 586450. 2029.24 0.89 0.196215 0.171741 25474 144626 -1 2240 20 1617 2629 179174 42111 3.13256 3.13256 -125.645 -3.13256 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0288827 0.02511 141 64 60 30 62 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_039.v common 7.79 vpr 63.59 MiB 0.05 7320 -1 -1 1 0.03 -1 -1 30488 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65112 31 32 455 371 1 198 86 17 17 289 -1 unnamed_device 24.5 MiB 4.95 1142 15773 5258 8448 2067 63.6 MiB 0.18 0.00 4.89027 -151.644 -4.89027 4.89027 0.33 0.000842905 0.000783698 0.0723096 0.0672411 -1 -1 -1 -1 32 2743 25 6.87369e+06 321398 586450. 2029.24 0.85 0.198848 0.174671 25474 144626 -1 2290 21 1515 2578 168142 40772 3.93805 3.93805 -146.284 -3.93805 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65496 31 32 391 309 1 195 99 17 17 289 -1 unnamed_device 24.3 MiB 2.30 1085 13323 3719 8474 1130 64.0 MiB 0.15 0.00 3.56305 -121.781 -3.56305 3.56305 0.33 0.000750292 0.000695055 0.0469947 0.043466 -1 -1 -1 -1 32 2458 26 6.87369e+06 503058 586450. 2029.24 0.83 0.164638 0.143846 25474 144626 -1 1962 21 1734 3018 163687 41150 2.98326 2.98326 -115.348 -2.98326 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0302449 0.0263189 149 64 60 31 62 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_042.v common 8.17 vpr 64.33 MiB 0.05 7208 -1 -1 1 0.03 -1 -1 30508 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65876 32 32 407 319 1 202 103 17 17 289 -1 unnamed_device 24.8 MiB 1.74 1175 14322 3573 9808 941 64.3 MiB 0.15 0.00 4.3428 -150.925 -4.3428 4.3428 0.33 0.0007668 0.000712902 0.0478086 0.0443512 -1 -1 -1 -1 26 3596 47 6.87369e+06 544980 503264. 1741.40 4.48 0.334679 0.288774 24322 120374 -1 2764 34 2811 4835 447833 101045 4.5329 4.5329 -163.977 -4.5329 0 0 618332. 2139.56 0.03 0.14 0.10 -1 -1 0.03 0.0446884 0.0385203 156 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_043.v common 5.61 vpr 64.00 MiB 0.05 7292 -1 -1 1 0.03 -1 -1 30764 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65540 32 32 496 380 1 234 106 17 17 289 -1 unnamed_device 25.0 MiB 2.89 1315 14106 3332 9481 1293 64.0 MiB 0.18 0.00 4.3641 -148.76 -4.3641 4.3641 0.33 0.000913768 0.000848271 0.0544141 0.0505209 -1 -1 -1 -1 32 3325 28 6.87369e+06 586901 586450. 2029.24 0.69 0.170009 0.149215 25474 144626 -1 2623 22 2115 3321 198523 50434 4.0397 4.0397 -157.94 -4.0397 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.037404 0.0324118 186 96 62 32 96 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_044.v common 4.39 vpr 62.99 MiB 0.04 6960 -1 -1 1 0.03 -1 -1 30552 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64500 31 32 305 250 1 164 81 17 17 289 -1 unnamed_device 23.9 MiB 2.07 945 8306 2134 5368 804 63.0 MiB 0.09 0.00 3.51475 -122.042 -3.51475 3.51475 0.33 0.0006264 0.000583386 0.0316576 0.0294713 -1 -1 -1 -1 32 2051 21 6.87369e+06 251529 586450. 2029.24 0.57 0.104635 0.0918106 25474 144626 -1 1786 20 1319 2146 137058 32821 2.95396 2.95396 -122.035 -2.95396 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64876 32 32 397 313 1 198 99 17 17 289 -1 unnamed_device 24.2 MiB 1.72 1312 16515 4792 9681 2042 63.4 MiB 0.18 0.00 3.52701 -124.222 -3.52701 3.52701 0.33 0.000756812 0.000701615 0.0574427 0.053151 -1 -1 -1 -1 30 2985 27 6.87369e+06 489084 556674. 1926.21 0.80 0.151833 0.133736 25186 138497 -1 2612 18 1625 2936 191570 44956 2.88196 2.88196 -120.53 -2.88196 0 0 706193. 2443.58 0.03 0.08 0.11 -1 -1 0.03 0.0264691 0.023027 150 63 62 32 62 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_047.v common 4.30 vpr 63.34 MiB 0.05 7036 -1 -1 1 0.03 -1 -1 30464 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64864 32 32 345 257 1 202 87 17 17 289 -1 unnamed_device 24.3 MiB 1.76 1031 15447 4347 9193 1907 63.3 MiB 0.17 0.00 4.1996 -144.506 -4.1996 4.1996 0.33 0.000706404 0.000657267 0.0588578 0.0547481 -1 -1 -1 -1 32 2895 23 6.87369e+06 321398 586450. 2029.24 0.66 0.143471 0.127238 25474 144626 -1 2288 23 2010 3668 237373 58414 3.8954 3.8954 -150.851 -3.8954 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0303079 0.0263189 147 3 128 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_048.v common 6.83 vpr 63.51 MiB 0.05 7088 -1 -1 1 0.03 -1 -1 30368 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 32 32 424 343 1 195 104 17 17 289 -1 unnamed_device 24.5 MiB 3.47 1164 18648 5381 11612 1655 63.5 MiB 0.18 0.00 3.52575 -126.751 -3.52575 3.52575 0.33 0.000780876 0.000725701 0.0634594 0.0587907 -1 -1 -1 -1 26 2648 39 6.87369e+06 558954 503264. 1741.40 1.44 0.252115 0.219239 24322 120374 -1 2239 22 1531 2600 178956 42448 3.24386 3.24386 -130.882 -3.24386 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0319613 0.027676 150 96 25 25 96 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_049.v common 6.86 vpr 63.62 MiB 0.05 7152 -1 -1 1 0.03 -1 -1 30368 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65148 32 32 395 311 1 198 103 17 17 289 -1 unnamed_device 24.5 MiB 3.34 1149 18178 5141 10104 2933 63.6 MiB 0.18 0.00 3.65105 -129.099 -3.65105 3.65105 0.33 0.000765584 0.000711031 0.0596975 0.0554178 -1 -1 -1 -1 28 2782 22 6.87369e+06 544980 531479. 1839.03 1.60 0.255503 0.22208 24610 126494 -1 2328 21 1707 3104 208619 51126 3.38476 3.38476 -123.951 -3.38476 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0304756 0.0264434 152 61 64 32 60 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_050.v common 6.72 vpr 64.06 MiB 0.05 7156 -1 -1 1 0.03 -1 -1 30428 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65596 32 32 405 318 1 201 104 17 17 289 -1 unnamed_device 24.5 MiB 2.76 1197 19868 5863 11669 2336 64.1 MiB 0.20 0.00 3.61805 -127.892 -3.61805 3.61805 0.33 0.000769266 0.000714418 0.0653848 0.0605519 -1 -1 -1 -1 28 3033 24 6.87369e+06 558954 531479. 1839.03 1.97 0.277699 0.241262 24610 126494 -1 2594 22 2007 3268 239230 57218 3.27506 3.27506 -132.18 -3.27506 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0318897 0.027649 156 65 63 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_051.v common 2.89 vpr 64.03 MiB 0.02 7140 -1 -1 1 0.04 -1 -1 30520 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65564 32 32 376 288 1 202 104 17 17 289 -1 unnamed_device 24.3 MiB 0.93 1150 19136 5645 11051 2440 64.0 MiB 0.10 0.00 4.23385 -148.233 -4.23385 4.23385 0.25 0.000325426 0.00029842 0.0272704 0.0250031 -1 -1 -1 -1 32 2791 24 6.87369e+06 558954 586450. 2029.24 0.41 0.0701023 0.0617397 25474 144626 -1 2250 23 1968 3230 221453 52196 3.7891 3.7891 -147.336 -3.7891 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0315215 0.0273298 156 34 96 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_052.v common 6.51 vpr 64.16 MiB 0.05 7244 -1 -1 1 0.03 -1 -1 30784 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65700 32 32 407 319 1 202 105 17 17 289 -1 unnamed_device 24.6 MiB 2.62 1145 20606 5563 13214 1829 64.2 MiB 0.20 0.00 4.1996 -142.893 -4.1996 4.1996 0.33 0.000773114 0.000717867 0.0667821 0.0618703 -1 -1 -1 -1 34 2517 29 6.87369e+06 572927 618332. 2139.56 1.95 0.30449 0.263883 25762 151098 -1 2214 22 1811 2978 183813 46622 3.9067 3.9067 -149.325 -3.9067 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0313269 0.0271562 157 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_053.v common 7.82 vpr 63.69 MiB 0.05 7392 -1 -1 1 0.03 -1 -1 30528 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65220 31 32 449 367 1 195 100 17 17 289 -1 unnamed_device 24.7 MiB 3.63 1067 17268 4540 10656 2072 63.7 MiB 0.18 0.00 4.21489 -136.932 -4.21489 4.21489 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64820 32 32 370 314 1 166 82 17 17 289 -1 unnamed_device 24.3 MiB 2.68 980 13788 4117 8145 1526 63.3 MiB 0.15 0.00 3.56085 -129.056 -3.56085 3.56085 0.33 0.000703297 0.000652593 0.0566934 0.0526315 -1 -1 -1 -1 30 2359 21 6.87369e+06 251529 556674. 1926.21 1.44 0.219007 0.190404 25186 138497 -1 1930 22 1354 2129 140760 32404 2.88186 2.88186 -125.993 -2.88186 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0291445 0.0252505 113 94 0 0 94 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_057.v common 5.19 vpr 64.33 MiB 0.05 7288 -1 -1 1 0.03 -1 -1 30756 -1 -1 45 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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0.33 0.000715182 0.000666935 0.0354636 0.0329477 -1 -1 -1 -1 32 2542 20 6.87369e+06 489084 586450. 2029.24 1.53 0.209861 0.181299 25474 144626 -1 2038 20 1385 2121 129429 31025 3.05446 3.05446 -125.324 -3.05446 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0279555 0.0243171 150 34 92 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_059.v common 3.96 vpr 63.70 MiB 0.05 6880 -1 -1 1 0.03 -1 -1 30436 -1 -1 31 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65228 30 32 296 244 1 160 93 17 17 289 -1 unnamed_device 24.1 MiB 0.64 720 11853 2709 7510 1634 63.7 MiB 0.10 0.00 3.58505 -114.7 -3.58505 3.58505 0.33 0.000617614 0.000575341 0.0369468 0.0342607 -1 -1 -1 -1 30 2038 29 6.87369e+06 433189 556674. 1926.21 1.56 0.202629 0.174747 25186 138497 -1 1489 21 1124 1783 90984 26180 2.85866 2.85866 -114.937 -2.85866 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65480 32 32 376 288 1 202 104 17 17 289 -1 unnamed_device 24.2 MiB 2.88 1096 19624 5769 11241 2614 63.9 MiB 0.18 0.00 4.2308 -146.72 -4.2308 4.2308 0.33 0.000746072 0.000692515 0.0625144 0.0579168 -1 -1 -1 -1 32 2571 23 6.87369e+06 558954 586450. 2029.24 0.60 0.151855 0.134453 25474 144626 -1 2045 21 1677 2570 158948 39079 3.8456 3.8456 -143.771 -3.8456 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0292746 0.0254061 156 34 96 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_062.v common 4.22 vpr 63.06 MiB 0.04 6872 -1 -1 1 0.03 -1 -1 30288 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 32 32 283 225 1 168 98 17 17 289 -1 unnamed_device 23.9 MiB 0.88 899 18098 6040 9605 2453 63.1 MiB 0.15 0.00 3.61805 -127.303 -3.61805 3.61805 0.33 0.000613324 0.000570955 0.0511833 0.0475788 -1 -1 -1 -1 32 2263 22 6.87369e+06 475111 586450. 2029.24 1.52 0.202656 0.176277 25474 144626 -1 1761 21 1383 2192 151668 36597 2.95696 2.95696 -121.662 -2.95696 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0244908 0.0212215 123 3 96 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_063.v common 6.60 vpr 64.32 MiB 0.05 7212 -1 -1 1 0.03 -1 -1 30864 -1 -1 45 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65868 32 32 438 320 1 236 109 17 17 289 -1 unnamed_device 24.6 MiB 2.54 1291 20389 5708 11832 2849 64.3 MiB 0.22 0.00 4.94208 -168.29 -4.94208 4.94208 0.33 0.000850867 0.000791664 0.0695921 0.0646805 -1 -1 -1 -1 32 3292 27 6.87369e+06 628823 586450. 2029.24 2.04 0.327614 0.283956 25474 144626 -1 2625 22 2526 4446 310721 73337 4.56925 4.56925 -171.748 -4.56925 0 0 744469. 2576.02 0.03 0.11 0.12 -1 -1 0.03 0.0352502 0.0305223 189 34 128 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_064.v common 4.15 vpr 63.11 MiB 0.04 6780 -1 -1 1 0.03 -1 -1 30408 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64624 32 32 283 225 1 168 82 17 17 289 -1 unnamed_device 24.0 MiB 1.56 947 13610 4549 7009 2052 63.1 MiB 0.13 0.00 3.54365 -126.361 -3.54365 3.54365 0.33 0.000611131 0.000568901 0.0486451 0.0452949 -1 -1 -1 -1 32 2213 19 6.87369e+06 251529 586450. 2029.24 0.78 0.13438 0.118327 25474 144626 -1 1884 21 1485 2490 174745 40690 2.95696 2.95696 -125.229 -2.95696 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0245192 0.0212342 114 3 96 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_065.v common 5.23 vpr 63.18 MiB 0.05 6880 -1 -1 1 0.03 -1 -1 30368 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 30 32 296 244 1 162 95 17 17 289 -1 unnamed_device 24.1 MiB 1.94 847 12839 3221 8494 1124 63.2 MiB 0.12 0.00 3.53801 -116.955 -3.53801 3.53801 0.33 0.000621705 0.00057914 0.0385308 0.0358153 -1 -1 -1 -1 26 2367 31 6.87369e+06 461137 503264. 1741.40 1.48 0.188074 0.162548 24322 120374 -1 1900 21 1392 2297 159121 39320 3.08556 3.08556 -121.668 -3.08556 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0246692 0.0213 118 34 60 30 30 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_066.v common 6.21 vpr 63.55 MiB 0.05 7276 -1 -1 1 0.03 -1 -1 30404 -1 -1 35 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65080 29 32 393 319 1 184 96 17 17 289 -1 unnamed_device 24.4 MiB 2.83 979 10827 2630 7177 1020 63.6 MiB 0.12 0.00 3.61805 -112.96 -3.61805 3.61805 0.33 0.000739424 0.000687465 0.038744 0.0359292 -1 -1 -1 -1 30 2274 23 6.87369e+06 489084 556674. 1926.21 1.55 0.229251 0.197547 25186 138497 -1 1721 19 1105 1908 90980 24484 2.75066 2.75066 -107.331 -2.75066 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0268335 0.0233232 141 88 29 29 85 29 + fixed_k6_frac_ripple_N8_22nm.xml mult_067.v common 5.75 vpr 63.53 MiB 0.05 7208 -1 -1 1 0.03 -1 -1 30672 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65052 32 32 407 319 1 202 87 17 17 289 -1 unnamed_device 24.3 MiB 2.33 930 7959 1713 5891 355 63.5 MiB 0.11 0.00 4.2388 -145.479 -4.2388 4.2388 0.33 0.000774665 0.000717646 0.0344985 0.0319606 -1 -1 -1 -1 30 2629 23 6.87369e+06 321398 556674. 1926.21 1.57 0.209352 0.180755 25186 138497 -1 1871 18 1718 2679 166549 40728 3.648 3.648 -141.73 -3.648 0 0 706193. 2443.58 0.03 0.09 0.11 -1 -1 0.03 0.0328073 0.0285125 147 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_068.v common 6.64 vpr 64.01 MiB 0.05 7196 -1 -1 1 0.03 -1 -1 30632 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65548 32 32 407 319 1 202 102 17 17 289 -1 unnamed_device 24.2 MiB 3.99 1011 13192 3264 8603 1325 64.0 MiB 0.14 0.00 4.2699 -143.724 -4.2699 4.2699 0.33 0.00077125 0.000716466 0.0452503 0.0419891 -1 -1 -1 -1 30 2526 23 6.87369e+06 531006 556674. 1926.21 0.76 0.136836 0.120435 25186 138497 -1 2010 23 1859 3223 181999 45116 3.6168 3.6168 -139.905 -3.6168 0 0 706193. 2443.58 0.03 0.08 0.11 -1 -1 0.03 0.0327175 0.0283991 155 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_069.v common 6.15 vpr 63.31 MiB 0.05 6876 -1 -1 1 0.03 -1 -1 30508 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64832 32 32 345 287 1 168 98 17 17 289 -1 unnamed_device 24.3 MiB 2.81 851 13373 3762 8362 1249 63.3 MiB 0.13 0.00 3.52575 -122.419 -3.52575 3.52575 0.33 0.000677114 0.00062979 0.0424472 0.0393624 -1 -1 -1 -1 28 2227 24 6.87369e+06 475111 531479. 1839.03 1.49 0.226038 0.195381 24610 126494 -1 1950 20 1530 2375 156947 39894 3.06826 3.06826 -126.732 -3.06826 0 0 648988. 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65132 30 32 374 297 1 189 97 17 17 289 -1 unnamed_device 24.6 MiB 2.51 1035 12529 3126 8556 847 63.6 MiB 0.13 0.00 3.62905 -119.689 -3.62905 3.62905 0.33 0.000721992 0.00066963 0.0429819 0.0398325 -1 -1 -1 -1 26 2897 29 6.87369e+06 489084 503264. 1741.40 1.60 0.206091 0.178504 24322 120374 -1 2445 19 1503 2481 179127 44386 3.19986 3.19986 -127.798 -3.19986 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.02689 0.0233994 144 60 60 30 57 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_072.v common 4.10 vpr 63.40 MiB 0.05 7120 -1 -1 1 0.03 -1 -1 30368 -1 -1 35 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64920 28 32 332 260 1 180 95 17 17 289 -1 unnamed_device 24.4 MiB 1.43 952 17807 6266 8549 2992 63.4 MiB 0.17 0.00 4.2699 -127.29 -4.2699 4.2699 0.33 0.000662328 0.000615428 0.0567935 0.0527895 -1 -1 -1 -1 28 2387 24 6.87369e+06 489084 531479. 1839.03 0.78 0.138312 0.122399 24610 126494 -1 2002 19 1529 2511 177079 42805 3.6088 3.6088 -128.236 -3.6088 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0248427 0.0215994 139 34 84 28 28 28 + fixed_k6_frac_ripple_N8_22nm.xml mult_073.v common 4.96 vpr 63.31 MiB 0.05 6904 -1 -1 1 0.03 -1 -1 30216 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64832 30 32 325 273 1 161 81 17 17 289 -1 unnamed_device 24.1 MiB 2.52 898 13556 4057 8084 1415 63.3 MiB 0.13 0.00 3.50375 -117.529 -3.50375 3.50375 0.33 0.000649845 0.000604665 0.0520676 0.0484313 -1 -1 -1 -1 32 2221 20 6.87369e+06 265503 586450. 2029.24 0.57 0.12622 0.111731 25474 144626 -1 1795 21 1299 2260 159091 36914 2.82066 2.82066 -114.863 -2.82066 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0259517 0.0224026 110 63 30 30 60 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_074.v common 5.86 vpr 63.38 MiB 0.05 6912 -1 -1 1 0.03 -1 -1 30336 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64900 32 32 361 308 1 163 82 17 17 289 -1 unnamed_device 24.1 MiB 3.19 824 8804 2201 5514 1089 63.4 MiB 0.10 0.00 3.47695 -115.33 -3.47695 3.47695 0.35 0.000696267 0.000647352 0.0366908 0.0341135 -1 -1 -1 -1 32 2099 23 6.87369e+06 251529 586450. 2029.24 0.78 0.143621 0.124944 25474 144626 -1 1776 19 1093 1793 115987 28998 2.75366 2.75366 -112.872 -2.75366 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65564 32 32 407 319 1 202 103 17 17 289 -1 unnamed_device 24.2 MiB 3.76 1231 19383 5317 12294 1772 64.0 MiB 0.19 0.00 4.22285 -147.062 -4.22285 4.22285 0.33 0.000778242 0.000721253 0.0651145 0.0602538 -1 -1 -1 -1 32 3199 26 6.87369e+06 544980 586450. 2029.24 1.79 0.297577 0.258264 25474 144626 -1 2441 20 1822 3196 212930 49914 3.6718 3.6718 -147.592 -3.6718 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0294434 0.0255651 156 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_077.v common 9.80 vpr 64.23 MiB 0.05 7144 -1 -1 1 0.03 -1 -1 30392 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65776 32 32 407 319 1 202 102 17 17 289 -1 unnamed_device 24.7 MiB 3.75 944 19618 5376 10136 4106 64.2 MiB 0.17 0.00 4.27923 -143.211 -4.27923 4.27923 0.33 0.000774509 0.0007197 0.0666149 0.0617933 -1 -1 -1 -1 38 3009 25 6.87369e+06 531006 678818. 2348.85 4.02 0.314785 0.273663 26626 170182 -1 2070 27 1946 3321 223670 64347 4.2823 4.2823 -145.755 -4.2823 0 0 902133. 3121.57 0.03 0.10 0.13 -1 -1 0.03 0.0374599 0.0324198 155 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_078.v common 7.72 vpr 63.89 MiB 0.05 7072 -1 -1 1 0.03 -1 -1 30584 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65428 32 32 399 315 1 198 103 17 17 289 -1 unnamed_device 24.1 MiB 2.62 1101 18901 5395 10733 2773 63.9 MiB 0.21 0.00 4.21489 -141.08 -4.21489 4.21489 0.34 0.000756944 0.000702815 0.0701323 0.0650259 -1 -1 -1 -1 28 3533 26 6.87369e+06 544980 531479. 1839.03 3.09 0.290448 0.252681 24610 126494 -1 2557 21 1759 3006 236786 55479 3.9567 3.9567 -147.253 -3.9567 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0301146 0.0261642 152 65 60 30 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_079.v common 4.51 vpr 63.10 MiB 0.05 6936 -1 -1 1 0.03 -1 -1 30356 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 30 32 296 244 1 160 81 17 17 289 -1 unnamed_device 24.0 MiB 2.16 811 8131 2113 5235 783 63.1 MiB 0.09 0.00 3.50375 -115.041 -3.50375 3.50375 0.33 0.000615393 0.000572913 0.0305644 0.028444 -1 -1 -1 -1 32 2043 19 6.87369e+06 265503 586450. 2029.24 0.57 0.100501 0.0881055 25474 144626 -1 1701 21 1175 1973 126862 31034 2.96496 2.96496 -117.093 -2.96496 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0246417 0.0213432 110 34 60 30 30 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_080.v common 6.26 vpr 63.30 MiB 0.05 7148 -1 -1 1 0.03 -1 -1 30376 -1 -1 24 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64824 30 32 383 303 1 192 86 17 17 289 -1 unnamed_device 24.2 MiB 3.02 998 9536 2273 6581 682 63.3 MiB 0.11 0.00 4.25789 -139.005 -4.25789 4.25789 0.33 0.00074191 0.000689601 0.0393657 0.036587 -1 -1 -1 -1 30 2333 22 6.87369e+06 335372 556674. 1926.21 1.39 0.205752 0.178308 25186 138497 -1 1885 21 1596 2515 141236 34135 3.5228 3.5228 -133.425 -3.5228 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0291919 0.0253499 140 63 60 30 60 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_081.v common 7.45 vpr 64.23 MiB 0.05 7276 -1 -1 1 0.03 -1 -1 30852 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65776 32 32 469 381 1 202 107 17 17 289 -1 unnamed_device 24.5 MiB 4.70 1135 19588 6002 11154 2432 64.2 MiB 0.20 0.00 4.29189 -148.036 -4.29189 4.29189 0.33 0.000855811 0.000795502 0.0686583 0.0637435 -1 -1 -1 -1 32 2822 34 6.87369e+06 600875 586450. 2029.24 0.73 0.182253 0.160272 25474 144626 -1 2236 22 1970 3411 223133 54425 3.6088 3.6088 -140.997 -3.6088 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0345331 0.029776 158 127 0 0 128 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_082.v common 4.92 vpr 64.15 MiB 0.05 7216 -1 -1 1 0.03 -1 -1 30460 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65688 31 32 425 341 1 197 98 17 17 289 -1 unnamed_device 24.6 MiB 1.21 1141 19448 6231 10726 2491 64.1 MiB 0.20 0.00 4.30289 -146.351 -4.30289 4.30289 0.33 0.000781644 0.000725131 0.0711285 0.0659157 -1 -1 -1 -1 32 2686 23 6.87369e+06 489084 586450. 2029.24 1.71 0.299615 0.260246 25474 144626 -1 2052 23 1877 3089 196870 47667 3.5338 3.5338 -136.163 -3.5338 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0337744 0.0293123 150 94 31 31 93 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_083.v common 5.70 vpr 63.40 MiB 0.05 7272 -1 -1 1 0.03 -1 -1 30480 -1 -1 34 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 30 32 404 328 1 188 96 17 17 289 -1 unnamed_device 24.2 MiB 2.01 1065 18054 5358 10040 2656 63.4 MiB 0.18 0.00 3.59605 -119.759 -3.59605 3.59605 0.33 0.00081945 0.000766068 0.0646998 0.0600821 -1 -1 -1 -1 28 2564 22 6.87369e+06 475111 531479. 1839.03 1.77 0.270153 0.234929 24610 126494 -1 2063 19 1593 2688 167070 41776 3.09326 3.09326 -120.307 -3.09326 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.028226 0.0245706 142 92 26 26 90 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_084.v common 8.39 vpr 63.37 MiB 0.05 7016 -1 -1 1 0.03 -1 -1 30532 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64892 32 32 407 319 1 202 87 17 17 289 -1 unnamed_device 24.2 MiB 4.63 949 16407 6991 7912 1504 63.4 MiB 0.16 0.00 4.2354 -145.24 -4.2354 4.2354 0.33 0.000772793 0.000717614 0.068577 0.063707 -1 -1 -1 -1 34 3451 45 6.87369e+06 321398 618332. 2139.56 1.82 0.246696 0.215458 25762 151098 -1 2227 24 2270 3978 255976 66268 4.3046 4.3046 -154.958 -4.3046 0 0 787024. 2723.27 0.03 0.10 0.12 -1 -1 0.03 0.0339345 0.0293887 147 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_085.v common 4.41 vpr 63.30 MiB 0.02 7256 -1 -1 1 0.03 -1 -1 30404 -1 -1 36 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 29 32 387 316 1 181 97 17 17 289 -1 unnamed_device 24.2 MiB 1.95 1023 13861 3933 8688 1240 63.3 MiB 0.14 0.00 3.54105 -111.845 -3.54105 3.54105 0.33 0.000741536 0.000681895 0.0479005 0.0443245 -1 -1 -1 -1 26 2429 23 6.87369e+06 503058 503264. 1741.40 0.61 0.134169 0.117894 24322 120374 -1 2203 20 1527 2550 176515 42383 3.15456 3.15456 -118.618 -3.15456 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0281841 0.0244437 138 88 26 26 85 29 + fixed_k6_frac_ripple_N8_22nm.xml mult_086.v common 3.46 vpr 63.24 MiB 0.04 6860 -1 -1 1 0.03 -1 -1 30432 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 32 32 283 225 1 168 82 17 17 289 -1 unnamed_device 24.1 MiB 0.94 998 12542 3592 7114 1836 63.2 MiB 0.12 0.00 3.53195 -129.235 -3.53195 3.53195 0.33 0.00061261 0.000570281 0.045175 0.0420068 -1 -1 -1 -1 32 2144 29 6.87369e+06 251529 586450. 2029.24 0.80 0.145624 0.127554 25474 144626 -1 1833 21 1429 2173 145252 34704 2.83966 2.83966 -125.078 -2.83966 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.024812 0.0215335 114 3 96 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_087.v common 7.24 vpr 63.44 MiB 0.05 7148 -1 -1 1 0.03 -1 -1 30560 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64960 32 32 407 319 1 202 102 17 17 289 -1 unnamed_device 24.5 MiB 4.63 1144 20094 6405 10924 2765 63.4 MiB 0.20 0.00 4.3249 -149.538 -4.3249 4.3249 0.33 0.000774111 0.000719268 0.0678336 0.0628953 -1 -1 -1 -1 32 2698 22 6.87369e+06 531006 586450. 2029.24 0.65 0.159596 0.14127 25474 144626 -1 2153 21 1807 2822 188316 44685 3.7701 3.7701 -144.194 -3.7701 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0307341 0.026714 155 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_088.v common 8.13 vpr 64.19 MiB 0.04 7160 -1 -1 1 0.03 -1 -1 30364 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65732 32 32 407 319 1 202 87 17 17 289 -1 unnamed_device 24.4 MiB 4.07 922 15639 5289 7574 2776 64.2 MiB 0.17 0.00 4.25669 -145.061 -4.25669 4.25669 0.33 0.000769819 0.000714718 0.0652538 0.060608 -1 -1 -1 -1 36 2458 23 6.87369e+06 321398 648988. 2245.63 2.05 0.288458 0.250238 26050 158493 -1 1854 23 1816 2924 196456 49015 3.9064 3.9064 -141.863 -3.9064 0 0 828058. 2865.25 0.03 0.09 0.13 -1 -1 0.03 0.0334663 0.0289911 147 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_089.v common 6.80 vpr 63.20 MiB 0.04 7088 -1 -1 1 0.03 -1 -1 30388 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64716 32 32 315 267 1 158 95 17 17 289 -1 unnamed_device 24.0 MiB 3.39 889 10031 2536 7112 383 63.2 MiB 0.10 0.00 3.48439 -117.289 -3.48439 3.48439 0.33 0.000640293 0.000593722 0.0322523 0.0298511 -1 -1 -1 -1 26 2494 50 6.87369e+06 433189 503264. 1741.40 1.64 0.200857 0.173039 24322 120374 -1 1966 20 1201 2057 156416 39138 3.11686 3.11686 -121.082 -3.11686 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64808 32 32 381 303 1 194 99 17 17 289 -1 unnamed_device 24.3 MiB 2.81 1004 18339 5620 10081 2638 63.3 MiB 0.18 0.00 4.21143 -138.827 -4.21143 4.21143 0.33 0.000741737 0.00068996 0.062068 0.0576067 -1 -1 -1 -1 32 2426 25 6.87369e+06 489084 586450. 2029.24 1.61 0.282514 0.244981 25474 144626 -1 1959 20 1356 2079 141662 34145 3.5578 3.5578 -130.794 -3.5578 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0282301 0.0245219 144 59 60 32 58 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_092.v common 4.76 vpr 63.29 MiB 0.05 7228 -1 -1 1 0.03 -1 -1 30304 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64812 32 32 406 330 1 191 98 17 17 289 -1 unnamed_device 24.1 MiB 1.15 1050 12248 3256 7931 1061 63.3 MiB 0.14 0.00 4.15685 -135.946 -4.15685 4.15685 0.33 0.000763552 0.000709219 0.0441766 0.0409039 -1 -1 -1 -1 32 2666 23 6.87369e+06 475111 586450. 2029.24 1.72 0.268884 0.23177 25474 144626 -1 2174 20 1394 2281 155652 37795 3.62136 3.62136 -135.059 -3.62136 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0292805 0.0254453 142 88 28 28 88 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_093.v common 5.17 vpr 63.54 MiB 0.05 7224 -1 -1 1 0.03 -1 -1 30512 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65068 32 32 399 285 1 232 104 17 17 289 -1 unnamed_device 24.5 MiB 1.03 1271 9620 2298 6733 589 63.5 MiB 0.12 0.00 4.95294 -165.009 -4.95294 4.95294 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42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66068 32 32 493 378 1 233 106 17 17 289 -1 unnamed_device 24.9 MiB 2.49 1329 20856 6846 10957 3053 64.5 MiB 0.25 0.00 4.2988 -145.63 -4.2988 4.2988 0.33 0.000908484 0.000841446 0.0786036 0.0727899 -1 -1 -1 -1 34 3745 25 6.87369e+06 586901 618332. 2139.56 3.37 0.35274 0.305335 25762 151098 -1 2842 22 2418 4406 318963 74864 3.8867 3.8867 -144.829 -3.8867 0 0 787024. 2723.27 0.03 0.11 0.12 -1 -1 0.03 0.0371682 0.0321277 184 95 62 31 95 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_097.v common 6.50 vpr 63.67 MiB 0.05 7332 -1 -1 1 0.03 -1 -1 30600 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65196 31 32 455 371 1 198 86 17 17 289 -1 unnamed_device 24.6 MiB 3.72 969 10292 2693 6968 631 63.7 MiB 0.13 0.00 5.04825 -153.046 -5.04825 5.04825 0.33 0.000827217 0.000769784 0.0476629 0.0443182 -1 -1 -1 -1 32 2736 33 6.87369e+06 321398 586450. 2029.24 0.87 0.187222 0.162903 25474 144626 -1 2049 21 1361 2091 140337 35584 4.10255 4.10255 -146.565 -4.10255 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0331857 0.0287172 144 124 0 0 124 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_098.v common 6.54 vpr 63.22 MiB 0.05 7160 -1 -1 1 0.03 -1 -1 30384 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64740 32 32 355 304 1 161 82 17 17 289 -1 unnamed_device 24.0 MiB 3.38 829 11474 3124 7170 1180 63.2 MiB 0.12 0.00 3.7386 -117.206 -3.7386 3.7386 0.33 0.000685433 0.000636355 0.0463019 0.0430183 -1 -1 -1 -1 28 2287 21 6.87369e+06 251529 531479. 1839.03 1.33 0.220296 0.190693 24610 126494 -1 1926 19 1177 1801 142449 34364 2.91816 2.91816 -119.998 -2.91816 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0250793 0.0217538 108 89 0 0 89 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_099.v common 4.87 vpr 63.93 MiB 0.04 7076 -1 -1 1 0.03 -1 -1 30512 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65468 32 32 364 282 1 196 98 17 17 289 -1 unnamed_device 24.3 MiB 0.95 1139 19448 6515 10263 2670 63.9 MiB 0.19 0.00 4.23385 -144.907 -4.23385 4.23385 0.33 0.000718442 0.000667695 0.0646027 0.0599307 -1 -1 -1 -1 30 2683 24 6.87369e+06 475111 556674. 1926.21 1.99 0.240566 0.209858 25186 138497 -1 2068 18 1240 1851 106675 25903 3.7591 3.7591 -139.692 -3.7591 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64872 30 32 373 297 1 188 99 17 17 289 -1 unnamed_device 24.3 MiB 1.69 1033 18795 5927 9774 3094 63.4 MiB 0.19 0.00 3.58505 -115.362 -3.58505 3.58505 0.33 0.000722756 0.000671595 0.0616 0.0572047 -1 -1 -1 -1 28 2699 26 6.87369e+06 517032 531479. 1839.03 2.10 0.263132 0.2286 24610 126494 -1 2197 25 1835 3179 208579 51177 3.14156 3.14156 -118.269 -3.14156 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0328167 0.0283615 144 61 58 30 58 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_102.v common 6.58 vpr 64.07 MiB 0.04 7100 -1 -1 1 0.03 -1 -1 30484 -1 -1 46 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65604 32 32 407 319 1 202 110 17 17 289 -1 unnamed_device 24.5 MiB 2.48 1104 21939 6697 12218 3024 64.1 MiB 0.21 0.00 4.26989 -146.214 -4.26989 4.26989 0.33 0.000780945 0.000725395 0.0672548 0.0623564 -1 -1 -1 -1 28 3104 28 6.87369e+06 642796 531479. 1839.03 2.18 0.277559 0.241293 24610 126494 -1 2421 21 2056 3450 244961 58711 4.14 4.14 -149.625 -4.14 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0310418 0.0269398 160 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_103.v common 5.36 vpr 63.46 MiB 0.05 7052 -1 -1 1 0.03 -1 -1 30516 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64984 32 32 405 318 1 201 106 17 17 289 -1 unnamed_device 24.5 MiB 2.78 1162 18856 5235 12009 1612 63.5 MiB 0.18 0.00 3.52575 -124.656 -3.52575 3.52575 0.33 0.000775346 0.000718795 0.0604867 0.0560114 -1 -1 -1 -1 28 2666 30 6.87369e+06 586901 531479. 1839.03 0.64 0.159673 0.140781 24610 126494 -1 2294 21 1638 2584 168506 39834 3.04356 3.04356 -125.841 -3.04356 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0306125 0.0265386 157 65 63 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_104.v common 4.13 vpr 63.04 MiB 0.04 7080 -1 -1 1 0.03 -1 -1 30480 -1 -1 20 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64552 29 32 287 238 1 155 81 17 17 289 -1 unnamed_device 24.0 MiB 1.54 803 12331 3349 7158 1824 63.0 MiB 0.11 0.00 3.53195 -114.094 -3.53195 3.53195 0.33 0.000594501 0.000553827 0.043937 0.0409176 -1 -1 -1 -1 32 1796 25 6.87369e+06 279477 586450. 2029.24 0.75 0.134583 0.118008 25474 144626 -1 1473 20 1118 1664 106970 25049 2.85686 2.85686 -113.062 -2.85686 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0234324 0.0202674 107 34 58 29 29 29 + fixed_k6_frac_ripple_N8_22nm.xml mult_105.v common 4.94 vpr 63.16 MiB 0.05 7012 -1 -1 1 0.03 -1 -1 30156 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64672 32 32 334 290 1 154 81 17 17 289 -1 unnamed_device 23.9 MiB 2.39 889 8831 2178 6177 476 63.2 MiB 0.09 0.00 3.7565 -114.859 -3.7565 3.7565 0.35 0.000651672 0.000605737 0.0348874 0.03242 -1 -1 -1 -1 32 1843 20 6.87369e+06 237555 586450. 2029.24 0.75 0.131586 0.114593 25474 144626 -1 1566 21 937 1352 87466 21450 2.92726 2.92726 -110.063 -2.92726 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0259282 0.0224473 102 82 0 0 82 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 4.31 vpr 63.90 MiB 0.05 7120 -1 -1 1 0.03 -1 -1 30416 -1 -1 39 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65432 31 32 365 281 1 197 102 17 17 289 -1 unnamed_device 24.2 MiB 1.63 1141 17714 5354 10065 2295 63.9 MiB 0.18 0.00 4.28537 -144.975 -4.28537 4.28537 0.33 0.000731564 0.000672837 0.0560893 0.0519217 -1 -1 -1 -1 26 2765 25 6.87369e+06 544980 503264. 1741.40 0.79 0.15216 0.134256 24322 120374 -1 2394 19 1730 2896 192147 49140 4.132 4.132 -151.551 -4.132 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0270606 0.0235739 152 34 93 31 31 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_107.v common 6.62 vpr 63.02 MiB 0.04 6984 -1 -1 1 0.03 -1 -1 30376 -1 -1 32 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64536 29 32 297 254 1 148 93 17 17 289 -1 unnamed_device 24.0 MiB 3.08 711 17523 7364 8811 1348 63.0 MiB 0.15 0.00 3.48301 -104.839 -3.48301 3.48301 0.33 0.000678214 0.000625626 0.0515323 0.0476674 -1 -1 -1 -1 32 1844 23 6.87369e+06 447163 586450. 2029.24 1.68 0.233039 0.20087 25474 144626 -1 1430 20 1023 1684 109422 28099 2.93196 2.93196 -102.499 -2.93196 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0229676 0.0198241 108 56 29 29 52 26 + fixed_k6_frac_ripple_N8_22nm.xml mult_108.v common 6.96 vpr 63.40 MiB 0.04 6776 -1 -1 1 0.03 -1 -1 30224 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64920 32 32 314 256 1 168 82 17 17 289 -1 unnamed_device 24.2 MiB 3.37 907 12186 5086 6820 280 63.4 MiB 0.12 0.00 3.52575 -126.076 -3.52575 3.52575 0.33 0.000649434 0.000604341 0.0461654 0.0429588 -1 -1 -1 -1 36 2041 25 6.87369e+06 251529 648988. 2245.63 1.85 0.23834 0.205904 26050 158493 -1 1676 22 1442 2340 168113 41738 2.92396 2.92396 -119.414 -2.92396 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0144365 0.0126743 114 34 64 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_109.v common 5.17 vpr 63.38 MiB 0.05 7156 -1 -1 1 0.03 -1 -1 30364 -1 -1 38 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64900 31 32 387 307 1 193 101 17 17 289 -1 unnamed_device 24.3 MiB 2.39 1125 17726 4908 10315 2503 63.4 MiB 0.18 0.00 3.65725 -124.867 -3.65725 3.65725 0.33 0.000743512 0.000690673 0.0587036 0.0544582 -1 -1 -1 -1 32 2384 23 6.87369e+06 531006 586450. 2029.24 0.81 0.170519 0.149952 25474 144626 -1 1941 22 1596 2436 147466 35647 3.03726 3.03726 -116.56 -3.03726 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0308456 0.0267553 148 64 58 31 62 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_110.v common 5.99 vpr 63.04 MiB 0.04 6960 -1 -1 1 0.03 -1 -1 30348 -1 -1 17 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64552 31 32 308 262 1 154 80 17 17 289 -1 unnamed_device 23.9 MiB 2.83 883 8336 2238 5700 398 63.0 MiB 0.09 0.00 3.07332 -106.515 -3.07332 3.07332 0.33 0.000623655 0.000580678 0.0321098 0.0298728 -1 -1 -1 -1 26 2205 20 6.87369e+06 237555 503264. 1741.40 1.36 0.194692 0.167731 24322 120374 -1 1778 19 1124 1815 137522 32680 2.99326 2.99326 -121.385 -2.99326 0 0 618332. 2139.56 0.03 0.06 0.10 -1 -1 0.03 0.0229435 0.0198963 103 55 31 31 53 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_111.v common 5.14 vpr 63.95 MiB 0.04 7136 -1 -1 1 0.03 -1 -1 30476 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65484 32 32 383 307 1 190 101 17 17 289 -1 unnamed_device 24.3 MiB 2.54 1053 18196 4930 10917 2349 63.9 MiB 0.18 0.00 3.63031 -121.705 -3.63031 3.63031 0.33 0.000734279 0.00068219 0.0594197 0.0550985 -1 -1 -1 -1 30 2320 47 6.87369e+06 517032 556674. 1926.21 0.66 0.172678 0.151644 25186 138497 -1 1771 20 975 1633 82292 21490 2.77866 2.77866 -111.157 -2.77866 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0283294 0.0246798 143 65 52 26 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_112.v common 6.47 vpr 63.70 MiB 0.05 7140 -1 -1 1 0.03 -1 -1 30252 -1 -1 39 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65224 31 32 422 339 1 196 102 17 17 289 -1 unnamed_device 24.7 MiB 3.07 1065 19142 5683 10528 2931 63.7 MiB 0.19 0.00 3.61805 -124.185 -3.61805 3.61805 0.33 0.000785502 0.000728936 0.0658729 0.0610449 -1 -1 -1 -1 30 2186 20 6.87369e+06 544980 556674. 1926.21 1.42 0.244531 0.213169 25186 138497 -1 1793 21 1543 2324 131571 32107 2.86186 2.86186 -116.026 -2.86186 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0312002 0.0270359 151 93 31 31 92 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_113.v common 5.73 vpr 63.69 MiB 0.05 7088 -1 -1 1 0.03 -1 -1 30356 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65216 32 32 333 279 1 164 82 17 17 289 -1 unnamed_device 24.0 MiB 2.51 798 7024 1571 5156 297 63.7 MiB 0.09 0.00 3.12352 -109.491 -3.12352 3.12352 0.33 0.000661365 0.000614863 0.028191 0.0262299 -1 -1 -1 -1 30 2322 21 6.87369e+06 251529 556674. 1926.21 1.52 0.1809 0.155834 25186 138497 -1 1705 22 1146 1813 110801 27576 2.85996 2.85996 -114.1 -2.85996 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0273634 0.0236873 110 61 32 32 60 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_114.v common 5.16 vpr 63.17 MiB 0.05 6996 -1 -1 1 0.03 -1 -1 30108 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64688 32 32 339 283 1 166 81 17 17 289 -1 unnamed_device 24.0 MiB 2.74 790 5856 1196 3825 835 63.2 MiB 0.08 0.00 3.50375 -120.315 -3.50375 3.50375 0.33 0.000668234 0.000621218 0.0244303 0.0227368 -1 -1 -1 -1 32 2209 24 6.87369e+06 237555 586450. 2029.24 0.60 0.105262 0.0916136 25474 144626 -1 1787 20 1278 2173 147014 36806 3.08556 3.08556 -123.57 -3.08556 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 29 32 367 293 1 185 95 17 17 289 -1 unnamed_device 24.2 MiB 2.12 929 7223 1505 5248 470 63.2 MiB 0.09 0.00 3.56305 -112.306 -3.56305 3.56305 0.33 0.000709598 0.00066013 0.0259172 0.0240869 -1 -1 -1 -1 32 2450 25 6.87369e+06 475111 586450. 2029.24 1.67 0.236998 0.203241 25474 144626 -1 1723 20 1187 1934 105365 27235 3.04926 3.04926 -112.724 -3.04926 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.027155 0.0235801 141 62 56 29 58 29 + fixed_k6_frac_ripple_N8_22nm.xml mult_117.v common 7.31 vpr 63.66 MiB 0.05 7240 -1 -1 1 0.03 -1 -1 30676 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65188 32 32 469 381 1 202 105 17 17 289 -1 unnamed_device 24.5 MiB 4.64 1148 19865 5788 12352 1725 63.7 MiB 0.20 0.00 4.2388 -147.714 -4.2388 4.2388 0.33 0.000862195 0.000800938 0.0716368 0.0664075 -1 -1 -1 -1 32 2766 22 6.87369e+06 572927 586450. 2029.24 0.65 0.17168 0.151682 25474 144626 -1 2252 21 1785 2897 183545 43998 3.6481 3.6481 -141.582 -3.6481 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0333568 0.0287883 157 127 0 0 128 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_118.v common 4.22 vpr 63.21 MiB 0.04 6808 -1 -1 1 0.03 -1 -1 30440 -1 -1 17 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64728 31 32 259 212 1 155 80 17 17 289 -1 unnamed_device 23.6 MiB 1.00 771 11948 3657 6485 1806 63.2 MiB 0.11 0.00 3.09052 -105.03 -3.09052 3.09052 0.33 0.000573463 0.000534012 0.0415517 0.0387278 -1 -1 -1 -1 32 1807 22 6.87369e+06 237555 586450. 2029.24 1.42 0.185585 0.161711 25474 144626 -1 1538 19 976 1534 98343 24653 2.87716 2.87716 -110.55 -2.87716 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0213093 0.0185046 104 4 85 31 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_119.v common 4.33 vpr 63.55 MiB 0.05 7168 -1 -1 1 0.03 -1 -1 30412 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65076 32 32 418 338 1 194 101 17 17 289 -1 unnamed_device 24.3 MiB 1.55 1202 17256 4935 10275 2046 63.6 MiB 0.17 0.00 4.21805 -142.394 -4.21805 4.21805 0.33 0.000786939 0.000730724 0.0600142 0.0556031 -1 -1 -1 -1 32 2704 27 6.87369e+06 517032 586450. 2029.24 0.86 0.180988 0.158835 25474 144626 -1 2253 21 1613 2321 167558 38682 3.7331 3.7331 -143.417 -3.7331 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0313769 0.0272202 147 92 28 28 92 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_120.v common 6.76 vpr 63.42 MiB 0.05 7056 -1 -1 1 0.03 -1 -1 30148 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64944 32 32 376 318 1 168 82 17 17 289 -1 unnamed_device 24.3 MiB 3.97 908 7558 1836 5408 314 63.4 MiB 0.09 0.00 3.59615 -125.953 -3.59615 3.59615 0.33 0.000710981 0.000660498 0.0324529 0.030153 -1 -1 -1 -1 32 2031 27 6.87369e+06 251529 586450. 2029.24 0.95 0.153416 0.13275 25474 144626 -1 1719 22 1362 2002 124828 31033 2.89906 2.89906 -123.708 -2.89906 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0294741 0.025474 114 96 0 0 96 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_121.v common 5.27 vpr 63.42 MiB 0.05 7052 -1 -1 1 0.03 -1 -1 30400 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64940 32 32 401 316 1 199 103 17 17 289 -1 unnamed_device 24.2 MiB 2.59 1047 20106 6225 10936 2945 63.4 MiB 0.19 0.00 3.57101 -124.74 -3.57101 3.57101 0.33 0.000768123 0.000714366 0.0669362 0.0621563 -1 -1 -1 -1 28 2774 30 6.87369e+06 544980 531479. 1839.03 0.74 0.166014 0.14687 24610 126494 -1 2197 22 1770 2827 191011 48782 3.32186 3.32186 -131.581 -3.32186 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0318332 0.0276685 154 65 61 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_122.v common 8.06 vpr 64.39 MiB 0.05 7360 -1 -1 1 0.03 -1 -1 30796 -1 -1 47 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65932 32 32 500 382 1 236 111 17 17 289 -1 unnamed_device 24.7 MiB 4.16 1334 21391 6019 13210 2162 64.4 MiB 0.24 0.00 5.00794 -170.227 -5.00794 5.00794 0.33 0.000916929 0.000851788 0.0768448 0.0711612 -1 -1 -1 -1 34 3011 24 6.87369e+06 656770 618332. 2139.56 1.78 0.31193 0.271113 25762 151098 -1 2498 24 2178 3771 230476 57119 4.72775 4.72775 -176.408 -4.72775 0 0 787024. 2723.27 0.03 0.10 0.12 -1 -1 0.03 0.0407005 0.0352068 190 96 64 32 96 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_123.v common 5.11 vpr 63.17 MiB 0.04 6908 -1 -1 1 0.03 -1 -1 30152 -1 -1 15 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64688 30 32 246 229 1 118 77 17 17 289 -1 unnamed_device 23.7 MiB 2.05 600 5130 1094 3499 537 63.2 MiB 0.05 0.00 2.80201 -86.4967 -2.80201 2.80201 0.33 0.000526559 0.000490729 0.0181796 0.0169262 -1 -1 -1 -1 32 1340 20 6.87369e+06 209608 586450. 2029.24 1.33 0.160159 0.136701 25474 144626 -1 1125 17 501 729 39368 10821 1.96972 1.96972 -82.7331 -1.96972 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0179094 0.0155243 72 56 0 0 53 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_124.v common 3.83 vpr 63.54 MiB 0.03 7032 -1 -1 1 0.02 -1 -1 30524 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65068 30 32 296 244 1 158 81 17 17 289 -1 unnamed_device 23.9 MiB 0.88 853 13731 4499 7083 2149 63.5 MiB 0.13 0.00 3.55905 -117.205 -3.55905 3.55905 0.33 0.000619692 0.000576772 0.0502622 0.0467755 -1 -1 -1 -1 30 1784 22 6.87369e+06 265503 556674. 1926.21 1.16 0.207443 0.180195 25186 138497 -1 1505 20 1040 1546 87369 21376 3.00236 3.00236 -117.588 -3.00236 0 0 706193. 2443.58 0.04 0.06 0.11 -1 -1 0.04 0.0256121 0.0224304 109 34 60 30 30 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_125.v common 5.41 vpr 63.29 MiB 0.04 6908 -1 -1 1 0.03 -1 -1 30116 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 32 32 314 256 1 168 82 17 17 289 -1 unnamed_device 24.1 MiB 1.55 813 13610 4570 6521 2519 63.3 MiB 0.14 0.00 3.54365 -123.01 -3.54365 3.54365 0.33 0.00064556 0.000599784 0.0513418 0.0477432 -1 -1 -1 -1 36 2314 26 6.87369e+06 251529 648988. 2245.63 1.95 0.247455 0.214353 26050 158493 -1 1792 25 1631 2926 208357 54408 3.10126 3.10126 -123.47 -3.10126 0 0 828058. 2865.25 0.03 0.09 0.13 -1 -1 0.03 0.0298074 0.0257994 114 34 64 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_126.v common 3.81 vpr 63.31 MiB 0.05 6860 -1 -1 1 0.03 -1 -1 30488 -1 -1 37 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 25 32 251 214 1 139 94 17 17 289 -1 unnamed_device 23.7 MiB 0.73 757 15004 4162 8299 2543 63.3 MiB 0.12 0.00 3.44875 -92.5459 -3.44875 3.44875 0.33 0.000535278 0.000498443 0.0393721 0.0365858 -1 -1 -1 -1 26 1811 20 6.87369e+06 517032 503264. 1741.40 1.32 0.175615 0.151497 24322 120374 -1 1614 19 1028 1796 118492 29292 3.05256 3.05256 -97.0385 -3.05256 0 0 618332. 2139.56 0.03 0.06 0.10 -1 -1 0.03 0.0197168 0.0170434 105 34 50 25 25 25 + fixed_k6_frac_ripple_N8_22nm.xml mult_127.v common 6.21 vpr 63.57 MiB 0.02 7224 -1 -1 1 0.03 -1 -1 30508 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65096 32 32 432 346 1 200 86 17 17 289 -1 unnamed_device 24.5 MiB 2.83 1089 15584 5798 8091 1695 63.6 MiB 0.18 0.00 4.16249 -143.194 -4.16249 4.16249 0.33 0.000800668 0.000743979 0.0684708 0.0636369 -1 -1 -1 -1 30 2528 23 6.87369e+06 307425 556674. 1926.21 1.47 0.254511 0.22214 25186 138497 -1 1986 21 1753 3227 174348 43308 3.5888 3.5888 -138.86 -3.5888 0 0 706193. 2443.58 0.03 0.08 0.11 -1 -1 0.03 0.0319715 0.0277482 145 94 32 32 94 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_128.v common 5.21 vpr 63.52 MiB 0.05 7172 -1 -1 1 0.03 -1 -1 30328 -1 -1 40 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65044 31 32 421 339 1 195 103 17 17 289 -1 unnamed_device 24.5 MiB 2.41 1002 13358 3288 9107 963 63.5 MiB 0.14 0.00 3.58505 -119.642 -3.58505 3.58505 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65048 32 32 387 309 1 253 94 17 17 289 -1 unnamed_device 24.4 MiB 1.39 1289 15643 4373 9722 1548 63.5 MiB 0.17 0.00 4.10566 -141.292 -4.10566 4.10566 0.33 0.000900432 0.000831399 0.0574687 0.0533419 -1 -1 -1 -1 26 3438 40 6.89349e+06 422815 503264. 1741.40 1.41 0.235827 0.205113 24322 120374 -1 2791 19 1731 2127 162157 38059 3.871 3.871 -144.587 -3.871 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0272732 0.0237211 163 65 54 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_004.v common 4.66 vpr 63.21 MiB 0.05 6992 -1 -1 1 0.03 -1 -1 30604 -1 -1 27 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64560 31 32 317 242 1 187 98 17 17 289 -1 unnamed_device 23.9 MiB 0.79 1086 16523 4545 9530 2448 63.0 MiB 0.15 0.00 3.3697 -112.289 -3.3697 3.3697 0.33 0.000660774 0.000614032 0.0506958 0.0470607 -1 -1 -1 -1 32 2443 21 6.89349e+06 493284 586450. 2029.24 0.78 0.146505 0.128768 25474 144626 -1 2019 19 1143 1954 114229 28334 2.77861 2.77861 -109.807 -2.77861 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0244802 0.0212692 142 4 115 31 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_009.v common 3.97 vpr 63.07 MiB 0.05 7220 -1 -1 1 0.03 -1 -1 30148 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 31 32 338 292 1 226 88 17 17 289 -1 unnamed_device 23.8 MiB 1.20 1157 14323 4572 7373 2378 63.1 MiB 0.15 0.00 4.06464 -134.474 -4.06464 4.06464 0.33 0.000664123 0.000617403 0.050763 0.047131 -1 -1 -1 -1 32 3057 29 6.89349e+06 352346 586450. 2029.24 0.90 0.156146 0.136589 25474 144626 -1 2346 20 1487 1827 150561 34363 3.3447 3.3447 -127.373 -3.3447 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0253661 0.0219819 135 85 0 0 84 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_010.v common 4.03 vpr 63.19 MiB 0.04 6788 -1 -1 1 0.03 -1 -1 30372 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 32 32 314 256 1 193 85 17 17 289 -1 unnamed_device 24.0 MiB 1.38 1003 14035 4618 7503 1914 63.2 MiB 0.14 0.00 3.73335 -131.185 -3.73335 3.73335 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64912 32 32 386 305 1 240 92 17 17 289 -1 unnamed_device 24.3 MiB 0.93 1321 18515 6156 9982 2377 63.4 MiB 0.20 0.00 4.0839 -143.379 -4.0839 4.0839 0.33 0.000756452 0.000703052 0.0701448 0.065168 -1 -1 -1 -1 32 2882 23 6.89349e+06 394628 586450. 2029.24 1.56 0.263566 0.229932 25474 144626 -1 2320 22 1764 2437 159060 37188 3.04555 3.04555 -129.006 -3.04555 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0307837 0.0266916 158 58 64 32 57 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_014.v common 6.08 vpr 63.27 MiB 0.02 7048 -1 -1 1 0.04 -1 -1 30564 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64792 32 32 407 319 1 264 95 17 17 289 -1 unnamed_device 24.1 MiB 1.67 1515 17807 5526 10110 2171 63.3 MiB 0.20 0.00 5.10149 -174.569 -5.10149 5.10149 0.33 0.000782436 0.000727452 0.066614 0.0618444 -1 -1 -1 -1 30 3629 24 6.89349e+06 436909 556674. 1926.21 2.48 0.289196 0.251456 25186 138497 -1 2863 21 2115 2749 198519 44318 4.32705 4.32705 -170.378 -4.32705 0 0 706193. 2443.58 0.03 0.09 0.16 -1 -1 0.03 0.0317348 0.0276811 174 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_015.v common 3.66 vpr 63.43 MiB 0.04 6956 -1 -1 1 0.03 -1 -1 30732 -1 -1 22 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64952 29 32 272 228 1 171 83 17 17 289 -1 unnamed_device 23.7 MiB 1.08 924 12323 4386 5618 2319 63.4 MiB 0.11 0.00 3.63755 -113.774 -3.63755 3.63755 0.33 0.00058211 0.000541802 0.0417248 0.0388655 -1 -1 -1 -1 34 1905 19 6.89349e+06 310065 618332. 2139.56 0.78 0.15071 0.13128 25762 151098 -1 1729 20 1044 1450 88575 22251 3.04066 3.04066 -110.817 -3.04066 0 0 787024. 2723.27 0.03 0.05 0.12 -1 -1 0.03 0.0223184 0.0193403 109 29 58 29 24 24 + fixed_k6_frac_uripple_N8_22nm.xml mult_016.v common 6.48 vpr 63.55 MiB 0.05 7148 -1 -1 1 0.03 -1 -1 30420 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65072 32 32 401 315 1 256 92 17 17 289 -1 unnamed_device 24.4 MiB 2.55 1531 16859 5081 9680 2098 63.5 MiB 0.19 0.00 4.39629 -154.321 -4.39629 4.39629 0.33 0.000772822 0.000715626 0.0653816 0.0605141 -1 -1 -1 -1 28 3515 23 6.89349e+06 394628 531479. 1839.03 1.93 0.270115 0.235025 24610 126494 -1 3014 19 2269 3616 246411 56974 3.545 3.545 -146.114 -3.545 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64580 32 32 339 284 1 224 89 17 17 289 -1 unnamed_device 24.1 MiB 1.50 1258 13157 3692 8051 1414 63.1 MiB 0.14 0.00 3.60335 -129.041 -3.60335 3.60335 0.33 0.000674635 0.000627831 0.0468074 0.043497 -1 -1 -1 -1 30 2881 25 6.89349e+06 352346 556674. 1926.21 1.70 0.234358 0.203026 25186 138497 -1 2182 17 1104 1497 91335 21903 2.66425 2.66425 -116.788 -2.66425 0 0 706193. 2443.58 0.03 0.06 0.13 -1 -1 0.03 0.0230353 0.0201227 137 65 29 29 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_019.v common 3.68 vpr 63.17 MiB 0.04 6828 -1 -1 1 0.03 -1 -1 30192 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64688 30 32 226 208 1 143 80 17 17 289 -1 unnamed_device 23.7 MiB 0.90 838 11776 3393 6972 1411 63.2 MiB 0.09 0.00 3.10286 -101.836 -3.10286 3.10286 0.33 0.00050415 0.000469789 0.0360115 0.0335082 -1 -1 -1 -1 26 1682 19 6.89349e+06 253689 503264. 1741.40 1.05 0.135675 0.117914 24322 120374 -1 1556 18 769 879 68164 16574 2.31947 2.31947 -97.434 -2.31947 0 0 618332. 2139.56 0.03 0.05 0.10 -1 -1 0.03 0.0180737 0.0156881 80 34 24 24 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_020.v common 4.34 vpr 63.24 MiB 0.05 7008 -1 -1 1 0.03 -1 -1 30472 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 31 32 335 280 1 217 87 17 17 289 -1 unnamed_device 24.0 MiB 1.66 1174 11223 2879 7192 1152 63.2 MiB 0.12 0.00 4.32035 -143.77 -4.32035 4.32035 0.33 0.000660483 0.000614364 0.0406654 0.0378133 -1 -1 -1 -1 32 2540 22 6.89349e+06 338252 586450. 2029.24 0.81 0.139364 0.121872 25474 144626 -1 2136 18 1187 1646 106119 25575 3.445 3.445 -138.062 -3.445 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0254304 0.0221108 139 64 31 31 62 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_021.v common 4.32 vpr 63.16 MiB 0.04 6976 -1 -1 1 0.03 -1 -1 30256 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 32 32 366 283 1 228 106 17 17 289 -1 unnamed_device 24.1 MiB 1.27 1198 19606 5729 9767 4110 63.2 MiB 0.17 0.00 4.66313 -155.697 -4.66313 4.66313 0.33 0.000727903 0.000675351 0.0597099 0.0552916 -1 -1 -1 -1 32 3108 38 6.89349e+06 591941 586450. 2029.24 1.17 0.210355 0.183773 25474 144626 -1 2180 21 1904 2743 175307 45584 4.05824 4.05824 -148.746 -4.05824 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64420 26 32 198 186 1 129 78 17 17 289 -1 unnamed_device 23.5 MiB 0.74 637 12030 3326 7451 1253 62.9 MiB 0.09 0.00 2.88461 -78.8989 -2.88461 2.88461 0.33 0.000440092 0.000409523 0.0332636 0.0309327 -1 -1 -1 -1 24 1634 41 6.89349e+06 281877 470940. 1629.55 1.11 0.150845 0.130427 24034 113901 -1 1317 22 772 957 74343 18260 2.29195 2.29195 -79.8024 -2.29195 0 0 586450. 2029.24 0.03 0.05 0.09 -1 -1 0.03 0.0186709 0.0161636 76 30 26 26 22 22 + fixed_k6_frac_uripple_N8_22nm.xml mult_024.v common 4.70 vpr 63.17 MiB 0.04 6932 -1 -1 1 0.03 -1 -1 30116 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64688 32 32 333 251 1 196 87 17 17 289 -1 unnamed_device 23.9 MiB 1.16 1167 15063 4427 8897 1739 63.2 MiB 0.16 0.00 4.12784 -142.508 -4.12784 4.12784 0.33 0.000685681 0.000637517 0.0559723 0.0519633 -1 -1 -1 -1 32 2813 22 6.89349e+06 324158 586450. 2029.24 1.64 0.233566 0.203102 25474 144626 -1 2117 19 1337 2275 135687 32011 3.58075 3.58075 -138.09 -3.58075 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0254392 0.0221542 143 3 122 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_025.v common 3.28 vpr 62.93 MiB 0.04 6744 -1 -1 1 0.03 -1 -1 30488 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64444 32 32 199 182 1 122 77 17 17 289 -1 unnamed_device 23.5 MiB 0.48 758 9857 3324 5266 1267 62.9 MiB 0.08 0.00 2.24722 -87.4594 -2.24722 2.24722 0.33 0.0004674 0.000434708 0.0296772 0.0276125 -1 -1 -1 -1 30 1512 19 6.89349e+06 183220 556674. 1926.21 1.08 0.134196 0.116634 25186 138497 -1 1235 17 463 698 44396 10589 1.75616 1.75616 -83.6758 -1.75616 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0160881 0.0140619 72 3 53 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_026.v common 4.17 vpr 63.77 MiB 0.05 7028 -1 -1 1 0.03 -1 -1 30608 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65304 32 32 376 288 1 233 91 17 17 289 -1 unnamed_device 24.2 MiB 1.17 1168 13555 3574 8990 991 63.8 MiB 0.15 0.00 4.73011 -159.818 -4.73011 4.73011 0.33 0.000749456 0.000697181 0.051715 0.0480754 -1 -1 -1 -1 32 3172 41 6.89349e+06 380534 586450. 2029.24 1.08 0.194557 0.17019 25474 144626 -1 2214 20 1861 2669 170127 41472 3.89866 3.89866 -151.991 -3.89866 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0284247 0.0247428 158 34 96 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_027.v common 4.46 vpr 63.38 MiB 0.05 6980 -1 -1 1 0.03 -1 -1 30132 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64896 32 32 337 253 1 198 101 17 17 289 -1 unnamed_device 24.4 MiB 0.78 1124 9031 1841 6476 714 63.4 MiB 0.10 0.00 3.4888 -121.478 -3.4888 3.4888 0.33 0.00069141 0.000643026 0.0288 0.026754 -1 -1 -1 -1 26 2703 32 6.89349e+06 521472 503264. 1741.40 1.83 0.210315 0.181529 24322 120374 -1 2329 25 1648 2587 172707 40900 2.78661 2.78661 -120.803 -2.78661 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0319214 0.0276231 151 3 124 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_028.v common 5.58 vpr 63.46 MiB 0.05 7156 -1 -1 1 0.03 -1 -1 30596 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64980 32 32 407 319 1 264 94 17 17 289 -1 unnamed_device 24.2 MiB 1.96 1502 17773 5551 9919 2303 63.5 MiB 0.20 0.00 4.64215 -161.497 -4.64215 4.64215 0.33 0.000770465 0.000715798 0.0666924 0.0619586 -1 -1 -1 -1 30 3264 28 6.89349e+06 422815 556674. 1926.21 1.64 0.252643 0.220499 25186 138497 -1 2552 19 2024 2797 142241 36192 3.75146 3.75146 -152.492 -3.75146 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0284633 0.0247982 173 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_029.v common 4.01 vpr 63.67 MiB 0.04 6824 -1 -1 1 0.03 -1 -1 30084 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65200 32 32 294 246 1 188 83 17 17 289 -1 unnamed_device 24.3 MiB 1.36 1108 13403 4630 7095 1678 63.7 MiB 0.14 0.00 3.59005 -129.708 -3.59005 3.59005 0.33 0.000617113 0.000574729 0.0480705 0.044737 -1 -1 -1 -1 32 2442 21 6.89349e+06 267783 586450. 2029.24 0.78 0.140603 0.12352 25474 144626 -1 1997 19 1132 1634 114303 26570 2.74266 2.74266 -122.977 -2.74266 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0228836 0.0198641 116 34 54 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_030.v common 4.79 vpr 63.05 MiB 0.04 6980 -1 -1 1 0.03 -1 -1 30136 -1 -1 21 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64568 30 32 296 244 1 182 83 17 17 289 -1 unnamed_device 24.0 MiB 1.57 1078 12323 3284 7488 1551 63.1 MiB 0.13 0.00 4.27029 -140.501 -4.27029 4.27029 0.33 0.000623398 0.000580978 0.0441116 0.0410269 -1 -1 -1 -1 30 2160 33 6.89349e+06 295971 556674. 1926.21 1.38 0.194503 0.168642 25186 138497 -1 1847 19 1187 1829 102616 25341 3.3695 3.3695 -127.916 -3.3695 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0229967 0.0200005 120 34 60 30 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_031.v common 4.71 vpr 63.27 MiB 0.05 6880 -1 -1 1 0.03 -1 -1 30212 -1 -1 22 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64792 28 32 278 232 1 173 82 17 17 289 -1 unnamed_device 23.9 MiB 1.38 1003 14500 4764 7501 2235 63.3 MiB 0.14 0.00 4.23389 -129.733 -4.23389 4.23389 0.33 0.000582815 0.000542217 0.0495344 0.046131 -1 -1 -1 -1 32 2137 21 6.89349e+06 310065 586450. 2029.24 1.47 0.19217 0.167087 25474 144626 -1 1818 21 1106 1913 131028 30791 3.36645 3.36645 -121.548 -3.36645 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0235656 0.020402 116 34 56 28 28 28 + fixed_k6_frac_uripple_N8_22nm.xml mult_032.v common 4.02 vpr 63.31 MiB 0.05 6884 -1 -1 1 0.03 -1 -1 30284 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 32 32 283 225 1 168 83 17 17 289 -1 unnamed_device 23.6 MiB 1.31 995 9983 2978 5831 1174 63.3 MiB 0.11 0.00 3.60535 -128.599 -3.60535 3.60535 0.33 0.000608754 0.000566731 0.0364156 0.0339066 -1 -1 -1 -1 32 2253 45 6.89349e+06 267783 586450. 2029.24 0.90 0.160442 0.139464 25474 144626 -1 1932 18 1291 2131 173660 38323 2.91826 2.91826 -127.221 -2.91826 0 0 744469. 2576.02 0.04 0.08 0.12 -1 -1 0.04 0.0241167 0.0211408 115 3 96 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_033.v common 5.97 vpr 63.01 MiB 0.04 6968 -1 -1 1 0.03 -1 -1 30272 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64524 31 32 303 249 1 191 86 17 17 289 -1 unnamed_device 24.0 MiB 1.20 907 14828 6219 7954 655 63.0 MiB 0.15 0.00 3.98415 -131.57 -3.98415 3.98415 0.33 0.000637205 0.000592814 0.051749 0.0481409 -1 -1 -1 -1 28 3090 42 6.89349e+06 324158 531479. 1839.03 2.92 0.255636 0.221463 24610 126494 -1 2151 19 1466 2137 156655 40733 3.14066 3.14066 -126.902 -3.14066 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0235051 0.0204161 121 34 61 31 31 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_034.v common 4.43 vpr 63.15 MiB 0.05 7072 -1 -1 1 0.03 -1 -1 30212 -1 -1 25 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 29 32 312 264 1 201 86 17 17 289 -1 unnamed_device 23.9 MiB 1.17 1104 15773 5239 8417 2117 63.1 MiB 0.15 0.00 3.69355 -116.513 -3.69355 3.69355 0.33 0.000624524 0.000580633 0.0540431 0.0501986 -1 -1 -1 -1 28 2477 23 6.89349e+06 352346 531479. 1839.03 1.41 0.220149 0.191174 24610 126494 -1 2134 17 1208 1592 98897 24521 2.92316 2.92316 -114.783 -2.92316 0 0 648988. 2245.63 0.03 0.06 0.10 -1 -1 0.03 0.0213852 0.0185626 130 61 29 29 57 29 + fixed_k6_frac_uripple_N8_22nm.xml mult_035.v common 4.44 vpr 63.41 MiB 0.05 7212 -1 -1 1 0.03 -1 -1 30452 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64932 32 32 423 310 1 254 93 17 17 289 -1 unnamed_device 24.4 MiB 1.48 1413 16263 4557 9710 1996 63.4 MiB 0.19 0.00 4.60705 -160.408 -4.60705 4.60705 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26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64692 32 32 368 284 1 225 90 17 17 289 -1 unnamed_device 24.1 MiB 1.17 1065 11748 3163 7762 823 63.2 MiB 0.14 0.00 3.82 -129.667 -3.82 3.82 0.33 0.000728354 0.000677457 0.0449102 0.0417487 -1 -1 -1 -1 34 2622 24 6.89349e+06 366440 618332. 2139.56 0.98 0.187458 0.163164 25762 151098 -1 2082 19 1560 2262 126074 32981 2.88186 2.88186 -122.428 -2.88186 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0269576 0.0234409 151 34 92 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_059.v common 4.18 vpr 62.98 MiB 0.04 7036 -1 -1 1 0.03 -1 -1 30400 -1 -1 34 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64492 30 32 296 244 1 183 96 17 17 289 -1 unnamed_device 23.9 MiB 0.99 1065 10827 2630 7184 1013 63.0 MiB 0.11 0.00 4.28819 -133.732 -4.28819 4.28819 0.33 0.000620962 0.000574826 0.0325883 0.0302153 -1 -1 -1 -1 26 2530 28 6.89349e+06 479191 503264. 1741.40 1.35 0.182638 0.157298 24322 120374 -1 2242 28 1520 2635 216315 62883 3.7564 3.7564 -135.697 -3.7564 0 0 618332. 2139.56 0.03 0.10 0.10 -1 -1 0.03 0.032201 0.0277818 129 34 60 30 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_060.v common 5.68 vpr 64.02 MiB 0.05 7436 -1 -1 1 0.04 -1 -1 30900 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65560 32 32 531 413 1 356 103 17 17 289 -1 unnamed_device 25.0 MiB 2.20 1973 21552 6975 11898 2679 64.0 MiB 0.29 0.00 6.49481 -214.549 -6.49481 6.49481 0.33 0.000956296 0.000887927 0.0879429 0.0816438 -1 -1 -1 -1 32 4754 49 6.89349e+06 549660 586450. 2029.24 1.33 0.302547 0.264497 25474 144626 -1 3626 19 2684 3381 245763 60782 5.74388 5.74388 -209.908 -5.74388 0 0 744469. 2576.02 0.03 0.10 0.12 -1 -1 0.03 0.0354734 0.0308974 230 127 32 32 128 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_061.v common 4.80 vpr 63.18 MiB 0.05 7076 -1 -1 1 0.03 -1 -1 30448 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64700 32 32 376 288 1 225 90 17 17 289 -1 unnamed_device 24.1 MiB 1.09 1228 16974 4785 10461 1728 63.2 MiB 0.18 0.00 4.44639 -155.101 -4.44639 4.44639 0.33 0.000747652 0.000695557 0.0652856 0.0606932 -1 -1 -1 -1 30 2788 24 6.89349e+06 366440 556674. 1926.21 1.59 0.240185 0.210238 25186 138497 -1 2313 21 1772 2460 154590 35823 3.9319 3.9319 -147.023 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0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64900 32 32 438 320 1 267 95 17 17 289 -1 unnamed_device 24.4 MiB 1.56 1501 17807 4939 10901 1967 63.4 MiB 0.23 0.00 5.46259 -184.464 -5.46259 5.46259 0.33 0.000849969 0.000791236 0.0728097 0.0677385 -1 -1 -1 -1 32 3872 46 6.89349e+06 436909 586450. 2029.24 1.16 0.237545 0.208277 25474 144626 -1 2984 23 2248 3385 241015 56567 5.0328 5.0328 -185.031 -5.0328 0 0 744469. 2576.02 0.03 0.10 0.12 -1 -1 0.03 0.0366065 0.0317044 188 34 128 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_064.v common 3.90 vpr 63.39 MiB 0.04 6936 -1 -1 1 0.03 -1 -1 30248 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64912 32 32 283 225 1 168 82 17 17 289 -1 unnamed_device 23.7 MiB 1.31 894 13610 5225 7262 1123 63.4 MiB 0.13 0.00 3.61335 -129.478 -3.61335 3.61335 0.33 0.000616373 0.00057349 0.0489363 0.0455634 -1 -1 -1 -1 32 2299 22 6.89349e+06 253689 586450. 2029.24 0.80 0.142003 0.124912 25474 144626 -1 1818 19 1402 2342 149181 35719 2.92106 2.92106 -124.168 -2.92106 0 0 744469. 2576.02 0.03 0.04 0.09 -1 -1 0.03 0.0127971 0.011263 114 3 96 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_065.v common 4.25 vpr 62.95 MiB 0.04 6912 -1 -1 1 0.03 -1 -1 30112 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64456 30 32 296 244 1 185 84 17 17 289 -1 unnamed_device 23.9 MiB 0.78 983 15090 5268 7800 2022 62.9 MiB 0.14 0.00 3.71935 -122.134 -3.71935 3.71935 0.34 0.00061946 0.000576334 0.0528802 0.0492205 -1 -1 -1 -1 32 2249 38 6.89349e+06 310065 586450. 2029.24 1.53 0.220572 0.19161 25474 144626 -1 1759 21 1240 1711 103616 25757 3.17801 3.17801 -120.108 -3.17801 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0247395 0.0214495 118 34 60 30 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_066.v common 5.14 vpr 63.39 MiB 0.04 7176 -1 -1 1 0.03 -1 -1 30320 -1 -1 33 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 29 32 393 319 1 252 94 17 17 289 -1 unnamed_device 24.2 MiB 1.33 1341 18199 5258 10538 2403 63.4 MiB 0.19 0.00 4.13664 -130.224 -4.13664 4.13664 0.33 0.000738038 0.000685287 0.0654014 0.0607404 -1 -1 -1 -1 28 3301 35 6.89349e+06 465097 531479. 1839.03 1.81 0.277343 0.241104 24610 126494 -1 2504 21 1727 2312 165397 39519 3.4561 3.4561 -128.16 -3.4561 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0298808 0.0259522 168 88 29 29 85 29 + fixed_k6_frac_uripple_N8_22nm.xml mult_067.v common 5.48 vpr 63.34 MiB 0.05 7240 -1 -1 1 0.03 -1 -1 30784 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 32 32 407 319 1 264 95 17 17 289 -1 unnamed_device 24.2 MiB 1.82 1221 12407 3290 7924 1193 63.3 MiB 0.14 0.00 5.16911 -173.806 -5.16911 5.16911 0.33 0.000779363 0.000724302 0.0469731 0.0436453 -1 -1 -1 -1 32 3125 20 6.89349e+06 436909 586450. 2029.24 1.72 0.282038 0.243868 25474 144626 -1 2420 23 2196 3091 179353 44427 4.73405 4.73405 -171.972 -4.73405 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0334452 0.0290599 173 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_068.v common 4.95 vpr 63.94 MiB 0.05 7044 -1 -1 1 0.03 -1 -1 30656 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65476 32 32 407 319 1 264 95 17 17 289 -1 unnamed_device 24.2 MiB 1.80 1231 8951 1983 6660 308 63.9 MiB 0.12 0.00 5.05324 -167.397 -5.05324 5.05324 0.35 0.000775867 0.000720909 0.0346246 0.0321574 -1 -1 -1 -1 34 3282 24 6.89349e+06 436909 618332. 2139.56 1.12 0.191107 0.165711 25762 151098 -1 2448 20 2092 2934 200786 47072 4.79705 4.79705 -174.942 -4.79705 0 0 787024. 2723.27 0.03 0.09 0.12 -1 -1 0.03 0.0299895 0.0261215 175 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_069.v common 4.03 vpr 63.32 MiB 0.04 6980 -1 -1 1 0.03 -1 -1 30524 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64840 32 32 345 287 1 220 89 17 17 289 -1 unnamed_device 24.3 MiB 1.22 1016 14741 4173 7811 2757 63.3 MiB 0.15 0.00 4.27829 -143.109 -4.27829 4.27829 0.34 0.000678002 0.000630406 0.0526872 0.0489865 -1 -1 -1 -1 32 2726 35 6.89349e+06 352346 586450. 2029.24 0.83 0.168639 0.147749 25474 144626 -1 1899 20 1232 1423 98620 23951 3.3857 3.3857 -129.596 -3.3857 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0263435 0.0228985 136 65 32 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_070.v common 5.11 vpr 63.30 MiB 0.05 7028 -1 -1 1 0.03 -1 -1 30468 -1 -1 26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 31 32 353 302 1 231 89 17 17 289 -1 unnamed_device 24.2 MiB 1.47 1227 8999 2014 6221 764 63.3 MiB 0.11 0.00 4.43069 -143.689 -4.43069 4.43069 0.33 0.000689588 0.000641809 0.0330719 0.0307387 -1 -1 -1 -1 28 3099 22 6.89349e+06 366440 531479. 1839.03 1.75 0.220305 0.189725 24610 126494 -1 2588 21 1666 2118 145227 36584 3.9119 3.9119 -140.139 -3.9119 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0274964 0.0238227 142 90 0 0 89 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_071.v common 4.96 vpr 63.36 MiB 0.05 7140 -1 -1 1 0.03 -1 -1 30432 -1 -1 31 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64880 30 32 374 297 1 236 93 17 17 289 -1 unnamed_device 24.3 MiB 1.29 1263 17943 5889 9476 2578 63.4 MiB 0.19 0.00 3.98278 -131.19 -3.98278 3.98278 0.33 0.000719207 0.000668391 0.0640912 0.0594873 -1 -1 -1 -1 26 3455 39 6.89349e+06 436909 503264. 1741.40 1.74 0.275059 0.239402 24322 120374 -1 2762 21 1913 2858 208201 47445 3.41131 3.41131 -134.426 -3.41131 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0291052 0.0252606 161 60 60 30 57 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_072.v common 3.73 vpr 63.24 MiB 0.05 7080 -1 -1 1 0.03 -1 -1 30392 -1 -1 27 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64756 28 32 332 260 1 203 87 17 17 289 -1 unnamed_device 24.0 MiB 0.99 936 12375 3003 7042 2330 63.2 MiB 0.13 0.00 4.59085 -131.386 -4.59085 4.59085 0.33 0.000669455 0.000622708 0.0462473 0.0431111 -1 -1 -1 -1 32 2579 22 6.89349e+06 380534 586450. 2029.24 0.86 0.145096 0.127288 25474 144626 -1 1932 16 1168 1740 102968 26808 4.35596 4.35596 -134.764 -4.35596 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0216679 0.0189282 142 34 84 28 28 28 + fixed_k6_frac_uripple_N8_22nm.xml mult_073.v common 6.88 vpr 63.06 MiB 0.05 7032 -1 -1 1 0.03 -1 -1 30208 -1 -1 24 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64572 30 32 325 273 1 208 86 17 17 289 -1 unnamed_device 23.8 MiB 1.75 1061 14639 6063 7932 644 63.1 MiB 0.15 0.00 4.67543 -143.963 -4.67543 4.67543 0.33 0.000646754 0.000601523 0.0523043 0.0486486 -1 -1 -1 -1 30 3104 46 6.89349e+06 338252 556674. 1926.21 3.18 0.235055 0.204448 25186 138497 -1 2284 21 1485 2041 154074 36200 3.492 3.492 -132 -3.492 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0259833 0.0225035 131 63 30 30 60 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_074.v common 5.67 vpr 63.28 MiB 0.04 6932 -1 -1 1 0.03 -1 -1 30320 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64800 32 32 361 308 1 245 90 17 17 289 -1 unnamed_device 24.2 MiB 1.39 1306 14361 4140 7938 2283 63.3 MiB 0.15 0.00 4.25449 -145.014 -4.25449 4.25449 0.33 0.000701879 0.00065219 0.0519651 0.0482643 -1 -1 -1 -1 28 3359 38 6.89349e+06 366440 531479. 1839.03 2.29 0.254873 0.220716 24610 126494 -1 2678 27 1972 2454 207890 58002 3.3777 3.3777 -136.729 -3.3777 0 0 648988. 2245.63 0.03 0.10 0.10 -1 -1 0.03 0.034048 0.029393 144 91 0 0 91 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_075.v common 6.10 vpr 63.39 MiB 0.05 7068 -1 -1 1 0.03 -1 -1 30148 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64916 31 32 335 251 1 197 100 17 17 289 -1 unnamed_device 24.2 MiB 0.88 932 17268 5400 7852 4016 63.4 MiB 0.15 0.00 4.36065 -141.282 -4.36065 4.36065 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 32 32 399 315 1 257 93 17 17 289 -1 unnamed_device 24.1 MiB 1.76 1404 17523 6159 8784 2580 63.2 MiB 0.20 0.00 4.56713 -153.013 -4.56713 4.56713 0.33 0.000761838 0.000706965 0.066083 0.0613463 -1 -1 -1 -1 32 3702 24 6.89349e+06 408721 586450. 2029.24 0.94 0.184324 0.162289 25474 144626 -1 2700 21 1764 2529 155980 37292 3.8129 3.8129 -145.514 -3.8129 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0305139 0.0265566 169 65 60 30 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_079.v common 4.25 vpr 63.10 MiB 0.05 6980 -1 -1 1 0.03 -1 -1 30448 -1 -1 21 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64616 30 32 296 244 1 185 83 17 17 289 -1 unnamed_device 24.1 MiB 1.09 999 11963 3206 7400 1357 63.1 MiB 0.12 0.00 4.11194 -131.981 -4.11194 4.11194 0.34 0.000622359 0.000579722 0.0429193 0.039954 -1 -1 -1 -1 30 2219 20 6.89349e+06 295971 556674. 1926.21 1.29 0.194284 0.16852 25186 138497 -1 1868 18 1140 1614 101876 24036 3.12985 3.12985 -120.641 -3.12985 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0221432 0.019271 118 34 60 30 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_080.v common 4.50 vpr 63.24 MiB 0.05 7092 -1 -1 1 0.03 -1 -1 30372 -1 -1 28 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 30 32 383 303 1 241 90 17 17 289 -1 unnamed_device 24.1 MiB 1.72 1228 13155 3873 7280 2002 63.2 MiB 0.15 0.00 4.93324 -157.041 -4.93324 4.93324 0.33 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0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0326715 0.0283189 196 127 0 0 128 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_082.v common 5.46 vpr 63.44 MiB 0.02 7272 -1 -1 1 0.03 -1 -1 30772 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64964 31 32 425 341 1 280 98 17 17 289 -1 unnamed_device 24.5 MiB 1.69 1433 19898 6263 10776 2859 63.4 MiB 0.21 0.00 5.19789 -171.346 -5.19789 5.19789 0.33 0.00078494 0.000729042 0.0718066 0.0666239 -1 -1 -1 -1 28 3483 21 6.89349e+06 493284 531479. 1839.03 1.93 0.279576 0.243742 24610 126494 -1 2768 19 2123 2590 197715 46849 4.66075 4.66075 -169.956 -4.66075 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0159056 0.0140709 184 94 31 31 93 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_083.v common 6.21 vpr 63.36 MiB 0.05 7224 -1 -1 1 0.03 -1 -1 30488 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64876 30 32 404 328 1 261 95 17 17 289 -1 unnamed_device 24.2 MiB 1.60 1466 16943 5275 9110 2558 63.4 MiB 0.19 0.00 4.58423 -145.605 -4.58423 4.58423 0.34 0.000753953 0.000700732 0.0625049 0.0579699 -1 -1 -1 -1 28 3595 39 6.89349e+06 465097 531479. 1839.03 2.61 0.296221 0.256997 24610 126494 -1 2856 23 2400 3459 235720 55615 3.8522 3.8522 -142.438 -3.8522 0 0 648988. 2245.63 0.03 0.10 0.10 -1 -1 0.03 0.033048 0.0286617 174 92 26 26 90 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_084.v common 5.88 vpr 63.41 MiB 0.05 7072 -1 -1 1 0.03 -1 -1 30592 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64936 32 32 407 319 1 264 94 17 17 289 -1 unnamed_device 24.3 MiB 1.86 1438 16921 4532 10127 2262 63.4 MiB 0.20 0.00 5.09969 -174.568 -5.09969 5.09969 0.33 0.000769951 0.000714253 0.0638066 0.0591767 -1 -1 -1 -1 26 3901 31 6.89349e+06 422815 503264. 1741.40 2.01 0.263499 0.229188 24322 120374 -1 3079 22 2458 3494 309356 69378 4.58385 4.58385 -176.85 -4.58385 0 0 618332. 2139.56 0.03 0.11 0.10 -1 -1 0.03 0.0326723 0.0283961 174 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_085.v common 5.01 vpr 63.24 MiB 0.05 7284 -1 -1 1 0.03 -1 -1 30360 -1 -1 34 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64756 29 32 387 316 1 251 95 17 17 289 -1 unnamed_device 24.1 MiB 1.48 1300 13919 3823 7524 2572 63.2 MiB 0.15 0.00 4.50731 -134.302 -4.50731 4.50731 0.34 0.000837393 0.000785725 0.0499097 0.0463459 -1 -1 -1 -1 28 3058 30 6.89349e+06 479191 531479. 1839.03 1.59 0.25121 0.217412 24610 126494 -1 2557 19 1761 2383 146907 36045 3.9319 3.9319 -131.067 -3.9319 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0276474 0.0240476 169 88 26 26 85 29 + fixed_k6_frac_uripple_N8_22nm.xml mult_086.v common 3.46 vpr 63.39 MiB 0.02 6852 -1 -1 1 0.03 -1 -1 30232 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 32 32 283 225 1 168 82 17 17 289 -1 unnamed_device 23.7 MiB 0.79 953 15034 4497 9060 1477 63.4 MiB 0.15 0.00 3.60415 -127.643 -3.60415 3.60415 0.33 0.000610265 0.000567997 0.0533095 0.049604 -1 -1 -1 -1 32 2236 44 6.89349e+06 253689 586450. 2029.24 0.89 0.181995 0.158961 25474 144626 -1 1894 20 1208 1986 122611 29252 2.96316 2.96316 -124.924 -2.96316 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0237067 0.020599 114 3 96 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_087.v common 4.83 vpr 63.48 MiB 0.05 7052 -1 -1 1 0.03 -1 -1 30336 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65008 32 32 407 319 1 259 94 17 17 289 -1 unnamed_device 24.3 MiB 1.63 1301 16069 5243 8056 2770 63.5 MiB 0.18 0.00 5.15687 -172.128 -5.15687 5.15687 0.33 0.000791386 0.000735263 0.0613103 0.0569259 -1 -1 -1 -1 34 3362 22 6.89349e+06 422815 618332. 2139.56 1.15 0.219914 0.1925 25762 151098 -1 2671 23 2330 3274 223930 53683 4.50619 4.50619 -169.447 -4.50619 0 0 787024. 2723.27 0.03 0.10 0.12 -1 -1 0.03 0.0341173 0.0296211 172 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_088.v common 5.11 vpr 63.35 MiB 0.05 7044 -1 -1 1 0.03 -1 -1 30520 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 407 319 1 263 94 17 17 289 -1 unnamed_device 24.2 MiB 2.20 1383 17134 5303 9222 2609 63.3 MiB 0.19 0.00 5.10782 -172.27 -5.10782 5.10782 0.33 0.000773712 0.000717737 0.0647863 0.0601172 -1 -1 -1 -1 32 3271 22 6.89349e+06 422815 586450. 2029.24 0.89 0.182116 0.160392 25474 144626 -1 2692 19 2085 2832 175192 41819 4.52939 4.52939 -167.419 -4.52939 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0285049 0.0248437 172 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_089.v common 4.92 vpr 63.04 MiB 0.05 6948 -1 -1 1 0.03 -1 -1 30472 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 32 32 315 267 1 204 88 17 17 289 -1 unnamed_device 23.9 MiB 1.05 986 9838 2323 6939 576 63.0 MiB 0.10 0.00 3.75491 -121.625 -3.75491 3.75491 0.33 0.000649994 0.000603938 0.0340968 0.0316787 -1 -1 -1 -1 28 2822 25 6.89349e+06 338252 531479. 1839.03 1.99 0.224225 0.192873 24610 126494 -1 2192 21 1376 1671 132502 32852 3.01905 3.01905 -120.319 -3.01905 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0258106 0.0223522 124 55 32 32 54 27 + fixed_k6_frac_uripple_N8_22nm.xml mult_090.v common 4.47 vpr 63.21 MiB 0.05 6924 -1 -1 1 0.03 -1 -1 30396 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64724 31 32 275 220 1 164 81 17 17 289 -1 unnamed_device 23.6 MiB 1.07 803 9881 3191 5068 1622 63.2 MiB 0.09 0.00 3.59935 -120.624 -3.59935 3.59935 0.33 0.000605233 0.000564063 0.0355859 0.033138 -1 -1 -1 -1 32 2124 35 6.89349e+06 253689 586450. 2029.24 1.56 0.21792 0.187665 25474 144626 -1 1628 20 1203 1831 121960 30492 3.23576 3.23576 -119.48 -3.23576 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0233256 0.0202238 112 4 93 31 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_091.v common 4.85 vpr 63.33 MiB 0.05 7160 -1 -1 1 0.03 -1 -1 30312 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64852 32 32 381 303 1 240 92 17 17 289 -1 unnamed_device 24.2 MiB 1.15 1231 13754 4153 8203 1398 63.3 MiB 0.15 0.00 4.56339 -148.311 -4.56339 4.56339 0.33 0.000740831 0.0006887 0.0515433 0.0478362 -1 -1 -1 -1 28 3040 24 6.89349e+06 394628 531479. 1839.03 1.72 0.275416 0.238331 24610 126494 -1 2614 23 1820 2296 164135 40448 4.0873 4.0873 -145.854 -4.0873 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64916 32 32 399 285 1 232 104 17 17 289 -1 unnamed_device 24.2 MiB 0.88 1512 14012 4050 8858 1104 63.4 MiB 0.18 0.00 4.95818 -166.989 -4.95818 4.95818 0.33 0.000796918 0.000738904 0.0477977 0.0443417 -1 -1 -1 -1 32 3643 28 6.89349e+06 563754 586450. 2029.24 1.15 0.199029 0.173637 25474 144626 -1 2795 21 2045 3563 248050 55674 4.52739 4.52739 -164.832 -4.52739 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.0174675 0.0154246 183 3 156 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_094.v common 5.04 vpr 63.23 MiB 0.05 7136 -1 -1 1 0.03 -1 -1 30472 -1 -1 30 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64784 32 32 355 304 1 244 89 17 17 289 -1 unnamed_device 24.2 MiB 1.43 1277 9989 2458 6925 606 63.3 MiB 0.11 0.00 4.48385 -143.454 -4.48385 4.48385 0.34 0.000690008 0.000638492 0.0376752 0.0348434 -1 -1 -1 -1 30 2753 21 6.89349e+06 352346 556674. 1926.21 1.44 0.19703 0.170514 25186 138497 -1 2325 18 1389 1653 105535 25688 3.503 3.503 -135.401 -3.503 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0246385 0.0214264 142 89 0 0 89 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_099.v common 5.60 vpr 63.30 MiB 0.04 7060 -1 -1 1 0.03 -1 -1 30340 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 64932 29 32 287 238 1 178 84 17 17 289 -1 unnamed_device 24.0 MiB 0.92 753 14907 5576 6751 2580 63.4 MiB 0.13 0.00 3.831 -117.329 -3.831 3.831 0.33 0.00060551 0.000563981 0.0513937 0.0478521 -1 -1 -1 -1 32 2165 25 6.89349e+06 324158 586450. 2029.24 0.84 0.151921 0.133256 25474 144626 -1 1559 20 1409 1830 122009 30591 3.06071 3.06071 -112.057 -3.06071 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0231868 0.0200793 115 34 58 29 29 29 + fixed_k6_frac_uripple_N8_22nm.xml mult_105.v common 5.52 vpr 63.20 MiB 0.04 6912 -1 -1 1 0.03 -1 -1 30248 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64712 32 32 334 290 1 222 87 17 17 289 -1 unnamed_device 24.0 MiB 1.22 1101 13911 5707 7810 394 63.2 MiB 0.15 0.00 4.70868 -138.961 -4.70868 4.70868 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 32 32 314 256 1 194 85 17 17 289 -1 unnamed_device 23.9 MiB 1.53 1169 12733 4095 6614 2024 63.1 MiB 0.13 0.00 3.8782 -135.142 -3.8782 3.8782 0.34 0.000657222 0.000612326 0.0469677 0.0437456 -1 -1 -1 -1 28 2823 24 6.89349e+06 295971 531479. 1839.03 1.85 0.231118 0.200661 24610 126494 -1 2360 20 1668 2279 200006 44131 3.38931 3.38931 -137.549 -3.38931 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0249365 0.0215969 123 34 64 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_109.v common 5.67 vpr 63.39 MiB 0.05 7108 -1 -1 1 0.03 -1 -1 30416 -1 -1 29 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64912 31 32 387 307 1 244 92 17 17 289 -1 unnamed_device 24.2 MiB 1.75 1268 16652 5558 8745 2349 63.4 MiB 0.18 0.00 4.36484 -143.839 -4.36484 4.36484 0.33 0.000745649 0.000692421 0.0626172 0.0581734 -1 -1 -1 -1 28 3192 22 6.89349e+06 408721 531479. 1839.03 1.94 0.270943 0.235581 24610 126494 -1 2762 21 2177 2939 216914 52041 3.78855 3.78855 -145.228 -3.78855 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.030277 0.0263235 163 64 58 31 62 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_110.v common 3.71 vpr 63.01 MiB 0.05 6956 -1 -1 1 0.03 -1 -1 30348 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64524 31 32 308 262 1 197 86 17 17 289 -1 unnamed_device 23.9 MiB 1.12 1033 8024 1908 5498 618 63.0 MiB 0.09 0.00 3.26322 -110.856 -3.26322 3.26322 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64532 32 32 333 279 1 216 87 17 17 289 -1 unnamed_device 23.8 MiB 2.09 1217 9879 2720 6405 754 63.0 MiB 0.11 0.00 3.54325 -124.984 -3.54325 3.54325 0.33 0.000660706 0.000614519 0.0362522 0.0337014 -1 -1 -1 -1 30 2687 20 6.89349e+06 324158 556674. 1926.21 1.36 0.188275 0.162908 25186 138497 -1 2129 16 1092 1526 86472 21544 2.8315 2.8315 -116.981 -2.8315 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.0217635 0.0189492 133 61 32 32 60 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_114.v common 4.83 vpr 63.34 MiB 0.04 6896 -1 -1 1 0.03 -1 -1 30120 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 32 32 339 283 1 218 86 17 17 289 -1 unnamed_device 24.3 MiB 0.86 980 8591 2112 5922 557 63.3 MiB 0.11 0.00 3.8741 -128.661 -3.8741 3.8741 0.33 0.000673254 0.00062665 0.0326141 0.0303366 -1 -1 -1 -1 28 3027 43 6.89349e+06 310065 531479. 1839.03 2.11 0.240563 0.206551 24610 126494 -1 2382 22 1731 2107 166869 42558 3.37841 3.37841 -133.561 -3.37841 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0279856 0.0242131 132 63 32 32 62 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_115.v common 5.50 vpr 63.46 MiB 0.05 7048 -1 -1 1 0.03 -1 -1 30848 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64988 32 32 407 319 1 264 94 17 17 289 -1 unnamed_device 24.3 MiB 1.25 1282 15643 3802 10271 1570 63.5 MiB 0.19 0.00 4.6143 -156.82 -4.6143 4.6143 0.33 0.000778574 0.00072427 0.058865 0.0547005 -1 -1 -1 -1 30 3171 38 6.89349e+06 422815 556674. 1926.21 2.22 0.25593 0.222346 25186 138497 -1 2462 19 1846 2253 127632 31903 4.11336 4.11336 -155.135 -4.11336 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0282964 0.0246222 170 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_116.v common 3.71 vpr 63.23 MiB 0.02 7196 -1 -1 1 0.03 -1 -1 30668 -1 -1 29 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64744 29 32 367 293 1 233 90 17 17 289 -1 unnamed_device 24.1 MiB 1.17 1203 10542 2870 6902 770 63.2 MiB 0.07 0.00 3.69745 -116.178 -3.69745 3.69745 0.25 0.000317735 0.000292613 0.0181715 0.016705 -1 -1 -1 -1 26 3071 25 6.89349e+06 408721 503264. 1741.40 1.06 0.111552 0.0958251 24322 120374 -1 2431 22 1447 1929 143218 33711 3.6346 3.6346 -123.643 -3.6346 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 31 32 259 212 1 155 80 17 17 289 -1 unnamed_device 23.6 MiB 0.82 745 8336 2043 5166 1127 63.3 MiB 0.09 0.00 2.99217 -101.039 -2.99217 2.99217 0.33 0.000574136 0.000534957 0.0295149 0.0274887 -1 -1 -1 -1 32 1906 32 6.89349e+06 239595 586450. 2029.24 0.58 0.106354 0.0929425 25474 144626 -1 1632 21 1057 1694 108711 26729 2.72261 2.72261 -106.292 -2.72261 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0230958 0.0199982 104 4 85 31 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_119.v common 4.92 vpr 63.41 MiB 0.05 7168 -1 -1 1 0.03 -1 -1 30340 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64936 32 32 418 338 1 273 95 17 17 289 -1 unnamed_device 24.5 MiB 1.64 1217 9599 2333 5862 1404 63.4 MiB 0.12 0.00 5.60308 -177.161 -5.60308 5.60308 0.33 0.000803468 0.000746944 0.037283 0.0345942 -1 -1 -1 -1 34 3214 39 6.89349e+06 436909 618332. 2139.56 1.29 0.211084 0.182635 25762 151098 -1 2321 20 1852 2491 152053 38190 5.20054 5.20054 -174.876 -5.20054 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0301735 0.0262642 178 92 28 28 92 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_120.v common 5.59 vpr 63.27 MiB 0.04 7000 -1 -1 1 0.03 -1 -1 30132 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64784 32 32 376 318 1 259 91 17 17 289 -1 unnamed_device 24.2 MiB 1.80 1321 16615 4991 9246 2378 63.3 MiB 0.18 0.00 5.02744 -166.554 -5.02744 5.02744 0.33 0.000715759 0.000664942 0.0607316 0.0563724 -1 -1 -1 -1 32 3248 26 6.89349e+06 380534 586450. 2029.24 1.87 0.254283 0.220939 25474 144626 -1 2576 20 1850 2349 165532 38600 4.36539 4.36539 -162.705 -4.36539 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0275449 0.0239539 153 96 0 0 96 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_121.v common 5.63 vpr 63.23 MiB 0.05 7160 -1 -1 1 0.03 -1 -1 30320 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 32 32 401 316 1 253 94 17 17 289 -1 unnamed_device 24.1 MiB 1.68 1306 19051 6211 10037 2803 63.2 MiB 0.21 0.00 3.73835 -130.804 -3.73835 3.73835 0.33 0.000763021 0.000709152 0.0711454 0.0660209 -1 -1 -1 -1 28 3343 23 6.89349e+06 422815 531479. 1839.03 1.95 0.281782 0.244986 24610 126494 -1 2689 21 1843 2447 192473 46184 3.1084 3.1084 -130.26 -3.1084 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0311229 0.0270762 168 65 61 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_122.v common 4.83 vpr 63.66 MiB 0.05 7360 -1 -1 1 0.03 -1 -1 30772 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65192 32 32 500 382 1 322 102 17 17 289 -1 unnamed_device 24.8 MiB 1.53 1462 15096 4398 9006 1692 63.7 MiB 0.19 0.00 5.86158 -190.116 -5.86158 5.86158 0.33 0.000919181 0.000854379 0.061316 0.0569405 -1 -1 -1 -1 32 4699 41 6.89349e+06 535566 586450. 2029.24 1.25 0.266879 0.23192 25474 144626 -1 3190 22 2412 2931 198387 48002 5.40169 5.40169 -188.235 -5.40169 0 0 744469. 2576.02 0.03 0.10 0.12 -1 -1 0.03 0.0382229 0.0331721 214 96 64 32 96 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_123.v common 3.79 vpr 63.16 MiB 0.04 6768 -1 -1 1 0.03 -1 -1 30240 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64672 30 32 246 229 1 160 81 17 17 289 -1 unnamed_device 23.6 MiB 0.90 892 12856 4155 7039 1662 63.2 MiB 0.10 0.00 3.53735 -105.472 -3.53735 3.53735 0.33 0.000533269 0.000496561 0.040837 0.038018 -1 -1 -1 -1 30 1687 20 6.89349e+06 267783 556674. 1926.21 1.08 0.160413 0.138837 25186 138497 -1 1417 14 544 570 40251 9509 2.31396 2.31396 -91.0321 -2.31396 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0156975 0.0136917 88 56 0 0 53 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 3.92 vpr 62.93 MiB 0.05 7080 -1 -1 1 0.03 -1 -1 30492 -1 -1 23 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64444 30 32 296 244 1 181 85 17 17 289 -1 unnamed_device 23.8 MiB 1.29 886 13105 4113 6709 2283 62.9 MiB 0.12 0.00 4.28025 -136.671 -4.28025 4.28025 0.33 0.000613731 0.000571122 0.0450939 0.0419413 -1 -1 -1 -1 32 2067 23 6.89349e+06 324158 586450. 2029.24 0.78 0.137946 0.120725 25474 144626 -1 1700 19 1159 1686 109933 26904 3.31165 3.31165 -125.274 -3.31165 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.022771 0.0197669 123 34 60 30 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_125.v common 4.76 vpr 63.23 MiB 0.04 6816 -1 -1 1 0.03 -1 -1 30112 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64744 32 32 314 256 1 199 85 17 17 289 -1 unnamed_device 24.0 MiB 1.78 1163 14407 4027 8826 1554 63.2 MiB 0.15 0.00 4.37635 -153.345 -4.37635 4.37635 0.33 0.000649324 0.000604396 0.0520894 0.0484335 -1 -1 -1 -1 32 3043 47 6.89349e+06 295971 586450. 2029.24 1.08 0.17418 0.152423 25474 144626 -1 2472 18 1486 2592 197683 43427 3.7754 3.7754 -146.81 -3.7754 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0230032 0.0200354 126 34 64 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_126.v common 4.35 vpr 63.06 MiB 0.05 6988 -1 -1 1 0.03 -1 -1 30404 -1 -1 26 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64572 25 32 251 214 1 162 83 17 17 289 -1 unnamed_device 23.6 MiB 0.98 688 11423 2933 7572 918 63.1 MiB 0.10 0.00 3.8262 -99.1533 -3.8262 3.8262 0.33 0.000535906 0.00049956 0.035518 0.0331009 -1 -1 -1 -1 28 2060 38 6.89349e+06 366440 531479. 1839.03 1.52 0.18858 0.162195 24610 126494 -1 1597 20 1045 1416 94744 24504 3.09471 3.09471 -100.32 -3.09471 0 0 648988. 2245.63 0.03 0.05 0.11 -1 -1 0.03 0.0207982 0.0179176 103 34 50 25 25 25 + fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 5.31 vpr 63.52 MiB 0.05 7212 -1 -1 1 0.03 -1 -1 30608 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65044 32 32 432 346 1 288 97 17 17 289 -1 unnamed_device 24.5 MiB 2.27 1580 18079 5345 10673 2061 63.5 MiB 0.21 0.00 4.63015 -159.985 -4.63015 4.63015 0.33 0.000798293 0.00074155 0.0678044 0.0629363 -1 -1 -1 -1 32 3820 28 6.89349e+06 465097 586450. 2029.24 1.01 0.196504 0.17261 25474 144626 -1 3049 22 2642 3823 268741 61061 3.84746 3.84746 -153.108 -3.84746 0 0 744469. 2576.02 0.03 0.10 0.12 -1 -1 0.03 0.0334057 0.028964 187 94 32 32 94 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_128.v common 5.98 vpr 63.41 MiB 0.05 7280 -1 -1 1 0.03 -1 -1 30368 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64932 31 32 421 339 1 274 97 17 17 289 -1 unnamed_device 24.4 MiB 2.09 1424 7645 1561 5653 431 63.4 MiB 0.10 0.00 4.77128 -155.482 -4.77128 4.77128 0.33 0.000785282 0.00072944 0.0294522 0.0273626 -1 -1 -1 -1 36 3008 22 6.89349e+06 479191 648988. 2245.63 1.97 0.23972 0.206091 26050 158493 -1 2694 17 1684 2423 159887 38092 4.07659 4.07659 -150.939 -4.07659 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0270512 0.0236163 182 94 29 29 93 31 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores/config/golden_results.txt index 1cd9c9c84b1..4e15e0febf8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 598.66 vpr 960.23 MiB 13.68 133976 -1 -1 27 17.69 -1 -1 143016 -1 -1 5856 641 0 0 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 983276 641 128 52347 52475 1 24532 6625 91 91 8281 clb auto 357.7 MiB 160.79 318332 960.2 MiB 89.62 0.73 12.6254 -34290.9 -12.6254 12.6254 72.13 0.0592375 0.0517226 8.48988 7.13926 68 455834 31 2.5209e+08 7.05985e+07 3.55803e+07 4296.62 157.20 31.0104 26.6124 421084 16 109170 237403 17951291 3376200 13.6905 13.6905 -36287.5 -13.6905 0 0 4.43124e+07 5351.09 22.01 7.24 3.1936 2.8713 42271 15098 -1 -1 -1 -1 - k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 2.70 vpr 62.27 MiB 0.03 9516 -1 -1 11 0.24 -1 -1 37588 -1 -1 46 54 0 0 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 63768 54 51 469 520 1 312 151 10 10 100 clb auto 24.4 MiB 0.10 2353 62.3 MiB 0.07 0.00 5.08149 -205.596 -5.08149 5.08149 0.17 0.000392086 0.000311852 0.015759 0.0132278 50 5234 25 1.91864e+06 554530 264954. 2649.54 1.11 0.148127 0.128494 4614 22 1947 8386 484081 113201 5.49532 5.49532 -235.774 -5.49532 0 0 317040. 3170.40 0.08 0.11 0.03397 0.0308444 359 359 -1 -1 -1 -1 - k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 721.72 vpr 993.43 MiB 13.23 119524 -1 -1 1 4.23 -1 -1 173176 -1 -1 5778 641 0 0 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1017272 641 128 63843 53443 1 24926 6547 90 90 8100 clb auto 410.9 MiB 27.41 304069 991.9 MiB 226.58 1.31 7.15186 -24073.5 -7.15186 7.15186 71.60 0.0585901 0.0478535 9.32155 7.68188 84 399830 26 2.53171e+08 7.25663e+07 4.14494e+07 5117.21 284.66 36.1117 30.8063 377918 28 85229 152359 14087442 2558840 6.0606 6.0606 -24169.7 -6.0606 0 0 5.22475e+07 6450.30 26.97 7.77 4.41712 3.91642 43425 3440 12624 36 0 0 - k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 4.43 vpr 62.77 MiB 0.03 9708 -1 -1 4 0.16 -1 -1 37160 -1 -1 42 54 0 0 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64280 54 51 517 516 1 303 147 10 10 100 clb auto 24.8 MiB 1.39 2083 62.8 MiB 0.08 0.00 4.02436 -195.095 -4.02436 4.02436 0.17 0.000342444 0.000276702 0.0186213 0.015713 54 4284 26 1.94278e+06 527436 279084. 2790.84 1.66 0.190374 0.164594 3699 14 1415 5494 270401 63439 4.06651 4.06651 -209.119 -4.06651 0 0 343682. 3436.82 0.09 0.07 0.0271413 0.0252567 315 291 60 18 54 18 - k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 601.64 vpr 995.39 MiB 13.26 119624 -1 -1 1 3.96 -1 -1 173248 -1 -1 5777 641 0 0 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1019280 641 128 63843 53443 1 24852 6546 90 90 8100 clb auto 418.2 MiB 43.82 300188 995.4 MiB 232.78 1.24 6.78969 -23600.7 -6.78969 6.78969 70.51 0.0553422 0.0482949 9.58768 7.83378 70 420422 50 2.53845e+08 7.32471e+07 3.57218e+07 4410.10 152.16 34.4167 29.3473 391652 15 95578 169458 17599752 3082471 6.14994 6.14994 -24121.7 -6.14994 0 0 4.49017e+07 5543.42 22.47 6.34 2.82915 2.54089 43447 3440 12624 36 0 0 - k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 4.80 vpr 62.46 MiB 0.03 9556 -1 -1 4 0.16 -1 -1 37128 -1 -1 41 54 0 0 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 63956 54 51 517 516 1 301 146 10 10 100 clb auto 24.7 MiB 1.00 2091 62.5 MiB 0.07 0.00 3.49134 -180.988 -3.49134 3.49134 0.17 0.000334437 0.000274835 0.0142493 0.0122451 46 4918 46 1.94854e+06 519798 244280. 2442.80 2.43 0.235119 0.203245 3980 19 1895 7398 407017 96041 3.5254 3.5254 -198.595 -3.5254 0 0 298105. 2981.05 0.08 0.09 0.030901 0.028364 314 291 60 18 54 18 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 904.68 vpr 1.14 GiB 18.37 133724 -1 -1 27 15.68 -1 -1 139168 -1 -1 6624 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1194824 641 128 52347 52475 1 22515 7393 97 97 9409 clb auto 310.4 MiB 22.85 298740 9149996 3753498 5333891 62607 1166.8 MiB 96.26 0.74 15.7412 -38591.1 -15.7412 15.7412 30.42 0.089974 0.0781796 12.053 10.084 -1 -1 -1 -1 56 426274 31 2.89231e+08 7.98576e+07 3.46650e+07 3684.24 657.45 60.0816 49.7342 912566 8524037 -1 405147 17 94617 217119 15169611 3148784 13.8543 13.8543 -35439 -13.8543 0 0 4.24521e+07 4511.86 2.43 8.46 7.26 -1 -1 2.43 4.03963 3.48005 44415 15098 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 5.25 vpr 64.36 MiB 0.08 9300 -1 -1 11 0.25 -1 -1 32860 -1 -1 54 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65900 54 51 469 520 1 286 159 11 11 121 clb auto 25.2 MiB 0.16 2396 14349 2717 10798 834 64.4 MiB 0.15 0.00 5.78243 -247.508 -5.78243 5.78243 0.13 0.00148725 0.00137134 0.0570149 0.052511 -1 -1 -1 -1 46 5422 28 2.09946e+06 650970 304223. 2514.24 3.13 0.592987 0.51407 10132 69752 -1 4577 18 1669 7724 363406 87385 5.1128 5.1128 -231.102 -5.1128 0 0 371547. 3070.64 0.01 0.15 0.06 -1 -1 0.01 0.0601602 0.0534512 359 359 -1 -1 -1 -1 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 945.24 vpr 1.22 GiB 14.77 119136 -1 -1 1 4.75 -1 -1 169236 -1 -1 6208 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1275364 641 128 63843 53443 1 25019 6977 94 94 8836 clb auto 345.6 MiB 24.23 286843 10336022 4163054 5963355 209613 1245.5 MiB 252.94 1.74 6.91605 -25945.5 -6.91605 6.91605 29.94 0.0859758 0.0710401 13.9672 11.53 -1 -1 -1 -1 66 396883 44 2.78555e+08 7.79671e+07 3.71258e+07 4201.65 555.20 59.0437 48.8196 947360 9542419 -1 370537 18 99136 180208 14815346 2853307 4.59448 4.59448 -22721.2 -4.59448 0 0 4.63522e+07 5245.84 2.74 7.65 8.20 -1 -1 2.74 3.85648 3.30259 44203 3442 12624 36 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 7.69 vpr 65.05 MiB 0.08 9280 -1 -1 4 0.16 -1 -1 33104 -1 -1 51 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66608 54 51 517 516 1 297 156 11 11 121 clb auto 25.7 MiB 1.55 2180 12307 2298 9064 945 65.0 MiB 0.15 0.00 4.53625 -236.732 -4.53625 4.53625 0.13 0.00143278 0.00131459 0.0488556 0.0451651 -1 -1 -1 -1 42 4925 36 2.13115e+06 640458 271555. 2244.25 4.18 0.701293 0.605871 10024 64108 -1 4231 30 2262 11552 672859 177202 3.82788 3.82788 -212.131 -3.82788 0 0 347739. 2873.88 0.01 0.24 0.06 -1 -1 0.01 0.0855185 0.0753713 315 295 60 18 54 18 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 536.95 vpr 1.18 GiB 18.45 119164 -1 -1 1 4.62 -1 -1 169160 -1 -1 6224 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1233924 641 128 63843 53443 1 25134 6993 94 94 8836 clb auto 353.0 MiB 37.25 281948 10233972 4151923 5847650 234399 1205.0 MiB 273.47 1.74 6.79691 -25446.5 -6.79691 6.79691 30.65 0.0837999 0.0722687 14.1256 11.7008 -1 -1 -1 -1 68 391509 39 2.79293e+08 7.8915e+07 3.80124e+07 4301.99 106.46 44.7539 37.1554 956196 9731417 -1 364633 17 102524 185933 15374308 2998695 4.58117 4.58117 -22276.8 -4.58117 0 0 4.73504e+07 5358.81 3.23 8.69 8.17 -1 -1 3.23 4.10562 3.53354 44381 3442 12624 36 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 5.18 vpr 64.96 MiB 0.09 9316 -1 -1 4 0.16 -1 -1 33216 -1 -1 49 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66520 54 51 517 516 1 302 154 11 11 121 clb auto 25.8 MiB 0.53 2227 11278 1862 8633 783 65.0 MiB 0.14 0.01 4.6946 -234.829 -4.6946 4.6946 0.13 0.00145318 0.00133151 0.0449965 0.0415935 -1 -1 -1 -1 40 4906 30 2.13871e+06 621222 258219. 2134.04 2.74 0.473879 0.41168 9904 61394 -1 4507 16 1551 6485 367369 88315 4.05888 4.05888 -216.164 -4.05888 0 0 338486. 2797.40 0.01 0.14 0.06 -1 -1 0.01 0.054532 0.0488347 316 295 60 18 54 18 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores_frac/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores_frac/config/golden_results.txt index fa1e6a13164..04afcf5aa7b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores_frac/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores_frac/config/golden_results.txt @@ -1,11 +1,11 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_2ripple_N8_22nm.xml Md5Core.v common 1345.54 vpr 843.61 MiB 19.63 119156 -1 -1 1 4.60 -1 -1 169172 -1 -1 3158 641 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 863860 641 128 63843 53443 1 23908 3927 67 67 4489 clb auto 333.0 MiB 941.47 238707 4308618 1653800 2561467 93351 843.6 MiB 113.38 1.02 7.62466 -26238.2 -7.62466 7.62466 38.80 0.0900086 0.0781522 12.8973 10.8798 94 348495 43 1.40629e+08 4.5715e+07 2.66495e+07 5936.62 150.85 46.5822 39.074 610042 7319579 -1 311881 17 109690 149750 16562445 2801122 6.6934 6.6934 -24791.4 -6.6934 0 0 3.32742e+07 7412.38 14.55 8.41 6.36 -1 -1 14.55 4.14356 3.60079 23344 3442 12624 36 0 0 -k6_frac_2ripple_N8_22nm.xml cordic.v common 8.48 vpr 64.71 MiB 0.08 9264 -1 -1 4 0.67 -1 -1 32964 -1 -1 30 54 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66264 54 51 517 516 1 317 135 9 9 81 clb auto 26.0 MiB 3.70 1928 12591 2777 8745 1069 64.7 MiB 0.14 0.00 4.22749 -230.57 -4.22749 4.22749 0.17 0.00141093 0.00129827 0.0575671 0.0532357 58 4528 48 1.45065e+06 434271 237595. 2933.27 1.94 0.466668 0.405335 7864 57025 -1 3678 22 2146 7902 424283 100359 3.88422 3.88422 -214.982 -3.88422 0 0 298762. 3688.42 0.06 0.18 0.07 -1 -1 0.06 0.0681518 0.0603634 223 295 60 18 54 18 -k6_frac_2uripple_N8_22nm.xml Md5Core.v common 1078.50 vpr 824.74 MiB 19.19 119160 -1 -1 1 4.32 -1 -1 169116 -1 -1 3164 641 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 844532 641 128 63843 53443 1 23903 3933 67 67 4489 clb auto 325.8 MiB 725.52 236753 4379445 1690051 2596186 93208 824.7 MiB 92.80 0.77 7.40731 -25921.7 -7.40731 7.40731 38.55 0.0817046 0.0702754 12.4206 10.4665 94 336057 42 1.41393e+08 4.65612e+07 2.66495e+07 5936.62 125.43 41.24 34.5853 610042 7319579 -1 304945 16 105315 145559 15279873 2577115 6.2474 6.2474 -24272.2 -6.2474 0 0 3.32742e+07 7412.38 12.66 7.72 6.34 -1 -1 12.66 3.82185 3.32566 23332 3442 12624 36 0 0 -k6_frac_2uripple_N8_22nm.xml cordic.v common 4.58 vpr 64.71 MiB 0.10 9248 -1 -1 4 0.67 -1 -1 32908 -1 -1 31 54 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66260 54 51 517 516 1 322 136 9 9 81 clb auto 26.0 MiB 0.32 1855 10955 2337 7732 886 64.7 MiB 0.12 0.00 4.14249 -227.55 -4.14249 4.14249 0.17 0.00138708 0.00127662 0.049497 0.0457647 60 4035 30 1.45905e+06 456186 242836. 2997.97 1.47 0.347941 0.302314 7944 58396 -1 3327 18 1973 6844 325272 81930 3.74077 3.74077 -210.366 -3.74077 0 0 304930. 3764.57 0.07 0.14 0.07 -1 -1 0.07 0.0558437 0.0496984 227 295 60 18 54 18 -k6_frac_N8_22nm.xml Md5Core.v common 1232.05 vpr 861.79 MiB 18.39 133792 -1 -1 27 15.07 -1 -1 139148 -1 -1 3438 641 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 882472 641 128 52347 52475 1 23739 4207 70 70 4900 clb auto 279.5 MiB 756.19 255287 4315476 1661008 2584916 69552 855.8 MiB 55.93 0.45 15.3287 -39294.9 -15.3287 15.3287 41.71 0.0836165 0.0720047 11.6572 9.72775 90 377297 35 1.54829e+08 4.63167e+07 2.82429e+07 5763.86 264.70 56.8895 47.4295 638746 7615755 -1 353369 19 110041 232156 17925116 3249677 13.664 13.664 -36226.3 -13.664 0 0 3.48442e+07 7111.06 15.25 10.12 6.75 -1 -1 15.25 4.78713 4.16617 24673 15098 -1 -1 -1 -1 -k6_frac_N8_22nm.xml cordic.v common 6.46 vpr 64.57 MiB 0.07 9144 -1 -1 11 0.71 -1 -1 32832 -1 -1 34 54 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66120 54 51 469 520 1 309 139 9 9 81 clb auto 25.4 MiB 0.22 2174 8396 1359 6431 606 64.6 MiB 0.10 0.00 6.18892 -253.076 -6.18892 6.18892 0.17 0.00148504 0.00137147 0.0408609 0.0378237 64 4974 36 1.41552e+06 458048 257695. 3181.41 3.49 0.665842 0.574693 8044 62425 -1 4274 16 1979 7908 463358 108363 5.6854 5.6854 -236.355 -5.6854 0 0 325495. 4018.46 0.07 0.16 0.08 -1 -1 0.07 0.0545932 0.0486561 260 359 -1 -1 -1 -1 -k6_frac_ripple_N8_22nm.xml Md5Core.v common 1505.87 vpr 940.51 MiB 18.52 119108 -1 -1 1 4.45 -1 -1 169136 -1 -1 3939 641 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 963080 641 128 63843 53443 1 22927 4708 75 75 5625 clb auto 305.9 MiB 883.44 247966 5684356 2056083 3381895 246378 940.5 MiB 196.60 1.29 8.34964 -24574.8 -8.34964 8.34964 52.46 0.0937 0.0766502 13.4951 11.1191 80 342149 48 1.79437e+08 5.50405e+07 2.91229e+07 5177.40 271.91 57.9694 48.0698 717126 7920329 -1 325246 23 104183 175560 15728014 2904682 5.77787 5.77787 -21906 -5.77787 0 0 3.65283e+07 6493.92 13.62 8.30 6.56 -1 -1 13.62 4.37971 3.70517 29971 3442 12624 36 0 0 -k6_frac_ripple_N8_22nm.xml cordic.v common 6.28 vpr 64.21 MiB 0.10 9368 -1 -1 4 0.67 -1 -1 32960 -1 -1 32 54 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65748 54 51 517 516 1 308 137 9 9 81 clb auto 25.5 MiB 1.79 1973 8256 1458 6016 782 64.2 MiB 0.10 0.00 4.53631 -225.368 -4.53631 4.53631 0.17 0.0013957 0.00128956 0.0377693 0.034954 58 4378 29 1.43308e+06 447163 237595. 2933.27 1.75 0.39112 0.338338 7864 57025 -1 3755 20 1946 7125 408241 97925 3.83476 3.83476 -204.238 -3.83476 0 0 298762. 3688.42 0.07 0.16 0.07 -1 -1 0.07 0.0595007 0.0525933 235 295 60 18 54 18 -k6_frac_uripple_N8_22nm.xml Md5Core.v common 982.08 vpr 949.34 MiB 19.21 119216 -1 -1 1 4.29 -1 -1 169148 -1 -1 4035 641 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 972120 641 128 63843 53443 1 23951 4804 76 76 5776 clb auto 298.1 MiB 444.87 279860 5758360 2092735 3370157 295468 949.3 MiB 155.35 1.08 9.03188 -27023.3 -9.03188 9.03188 53.40 0.0797474 0.0683203 12.4205 10.4126 74 366559 30 1.87279e+08 5.68659e+07 2.80207e+07 4851.23 229.52 50.1288 41.5608 710444 7492861 -1 338755 20 85472 118774 11490599 2020589 7.0444 7.0444 -24245.9 -7.0444 0 0 3.48777e+07 6038.39 13.16 7.09 6.21 -1 -1 13.16 4.01472 3.43224 30624 3442 12624 36 0 0 -k6_frac_uripple_N8_22nm.xml cordic.v common 4.79 vpr 64.06 MiB 0.10 9168 -1 -1 4 0.67 -1 -1 33056 -1 -1 34 54 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65600 54 51 517 516 1 312 139 9 9 81 clb auto 25.4 MiB 0.60 1998 7319 1124 5518 677 64.1 MiB 0.09 0.00 4.76334 -234.438 -4.76334 4.76334 0.17 0.00141492 0.00129496 0.0342431 0.0317551 58 4035 26 1.43728e+06 479191 237595. 2933.27 1.43 0.331668 0.287909 7864 57025 -1 3625 18 1765 6255 317707 78027 3.8948 3.8948 -205.264 -3.8948 0 0 298762. 3688.42 0.06 0.14 0.07 -1 -1 0.06 0.0568345 0.050492 249 295 60 18 54 18 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_frac_2ripple_N8_22nm.xml Md5Core.v common 719.95 vpr 930.50 MiB 18.37 119188 -1 -1 1 4.56 -1 -1 169196 -1 -1 3410 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 952828 641 128 63843 53443 1 23477 4179 70 70 4900 clb auto 332.1 MiB 370.76 235506 4781911 1870571 2798467 112873 865.1 MiB 103.32 0.86 7.52141 -26074.7 -7.52141 7.52141 20.32 0.0816713 0.0703528 12.6522 10.5227 -1 -1 -1 -1 96 327519 29 1.58307e+08 4.93629e+07 2.96071e+07 6042.26 146.59 47.2488 39.3458 672214 8127938 -1 305311 18 111930 152921 15206824 2753649 6.01093 6.01093 -24357.7 -6.01093 0 0 3.70091e+07 7552.87 2.30 7.89 6.99 -1 -1 2.30 4.22181 3.66195 23430 3442 12624 36 0 0 + k6_frac_2ripple_N8_22nm.xml cordic.v common 7.37 vpr 65.34 MiB 0.09 9348 -1 -1 4 0.15 -1 -1 33220 -1 -1 32 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66908 54 51 517 516 1 313 137 9 9 81 clb auto 26.1 MiB 3.87 2057 10727 2058 7633 1036 65.3 MiB 0.13 0.00 4.23609 -233.261 -4.23609 4.23609 0.09 0.00141962 0.00130738 0.0490049 0.0453196 -1 -1 -1 -1 60 4196 22 1.45065e+06 463222 242836. 2997.97 1.84 0.496698 0.430402 7944 58396 -1 3645 17 1759 5910 307112 75726 4.31905 4.31905 -218.777 -4.31905 0 0 304930. 3764.57 0.01 0.13 0.06 -1 -1 0.01 0.0544893 0.0486012 228 295 60 18 54 18 + k6_frac_2uripple_N8_22nm.xml Md5Core.v common 1251.68 vpr 860.31 MiB 18.93 119300 -1 -1 1 4.88 -1 -1 169228 -1 -1 3405 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 880956 641 128 63843 53443 1 23524 4174 70 70 4900 clb auto 324.2 MiB 248.39 239120 4740787 1863060 2780694 97033 860.3 MiB 124.98 1.00 7.3147 -25736.6 -7.3147 7.3147 20.89 0.091958 0.0752357 13.2611 11.0893 -1 -1 -1 -1 82 347465 34 1.59139e+08 5.01078e+07 2.58747e+07 5280.54 778.86 64.8144 53.6614 628122 6995602 -1 313528 19 112390 157276 15412644 2790255 5.6429 5.6429 -24107.4 -5.6429 0 0 3.23196e+07 6595.84 1.82 8.47 5.85 -1 -1 1.82 4.58889 3.93913 23428 3442 12624 36 0 0 + k6_frac_2uripple_N8_22nm.xml cordic.v common 3.44 vpr 65.43 MiB 0.09 9216 -1 -1 4 0.16 -1 -1 33192 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67000 54 51 517 516 1 318 138 9 9 81 clb auto 26.3 MiB 0.36 1922 16158 3946 10822 1390 65.4 MiB 0.18 0.00 4.1935 -227.995 -4.1935 4.1935 0.09 0.0013986 0.00129103 0.0703328 0.065036 -1 -1 -1 -1 56 3937 25 1.45905e+06 485618 231774. 2861.41 1.23 0.383785 0.335697 7704 54090 -1 3462 17 1880 6549 321379 84144 3.8246 3.8246 -211.788 -3.8246 0 0 286113. 3532.26 0.01 0.13 0.05 -1 -1 0.01 0.0554246 0.0493896 232 295 60 18 54 18 + k6_frac_N8_22nm.xml Md5Core.v common 1278.24 vpr 857.64 MiB 19.62 133848 -1 -1 27 16.10 -1 -1 139176 -1 -1 3560 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 878220 641 128 52347 52475 1 22613 4329 71 71 5041 clb auto 278.2 MiB 210.81 253837 4483111 1724795 2697814 60502 857.6 MiB 66.74 0.54 15.7271 -39246.4 -15.7271 15.7271 20.00 0.0880225 0.0759431 12.0413 10.1053 -1 -1 -1 -1 80 373760 27 1.56446e+08 4.79603e+07 2.60147e+07 5160.63 890.35 63.5702 52.7719 626238 7057181 -1 349344 18 105464 224026 16594796 3174287 13.5919 13.5919 -36084.3 -13.5919 0 0 3.26297e+07 6472.86 1.84 8.74 5.89 -1 -1 1.84 4.37319 3.77951 24995 15098 -1 -1 -1 -1 + k6_frac_N8_22nm.xml cordic.v common 3.34 vpr 64.39 MiB 0.09 9404 -1 -1 11 0.21 -1 -1 33040 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65936 54 51 469 520 1 307 138 9 9 81 clb auto 25.3 MiB 0.23 2168 10462 1941 7796 725 64.4 MiB 0.12 0.00 6.49963 -254.17 -6.49963 6.49963 0.09 0.00148553 0.00136363 0.0501404 0.0462173 -1 -1 -1 -1 64 4590 31 1.41552e+06 444576 257695. 3181.41 1.35 0.391024 0.341283 8044 62425 -1 4035 18 1888 7794 404854 99129 5.61742 5.61742 -233.114 -5.61742 0 0 325495. 4018.46 0.01 0.15 0.06 -1 -1 0.01 0.0624396 0.0556903 262 359 -1 -1 -1 -1 + k6_frac_ripple_N8_22nm.xml Md5Core.v common 1236.62 vpr 974.87 MiB 18.63 119092 -1 -1 1 5.40 -1 -1 169112 -1 -1 4156 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 998268 641 128 63843 53443 1 22922 4925 77 77 5929 clb auto 303.2 MiB 860.38 269984 5994337 2194745 3524702 274890 974.9 MiB 179.38 1.17 7.28071 -25362.6 -7.28071 7.28071 24.44 0.0868232 0.070468 12.705 10.4847 -1 -1 -1 -1 74 383007 50 1.88597e+08 5.80724e+07 2.87929e+07 4856.27 92.21 41.4301 34.2283 728640 7699156 -1 360816 23 121596 201798 19887743 3889899 5.17537 5.17537 -23064.7 -5.17537 0 0 3.58422e+07 6045.24 2.14 9.78 6.48 -1 -1 2.14 4.76556 4.03104 30007 3442 12624 36 0 0 + k6_frac_ripple_N8_22nm.xml cordic.v common 5.17 vpr 64.61 MiB 0.09 9384 -1 -1 4 0.16 -1 -1 33188 -1 -1 35 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66160 54 51 517 516 1 306 140 9 9 81 clb auto 25.6 MiB 1.86 2034 15749 3494 10440 1815 64.6 MiB 0.19 0.00 4.60908 -224.227 -4.60908 4.60908 0.09 0.00141288 0.00129939 0.0670027 0.0617908 -1 -1 -1 -1 56 4304 35 1.43308e+06 489084 231774. 2861.41 1.49 0.487985 0.424161 7704 54090 -1 3690 17 1831 6439 331209 84904 3.85365 3.85365 -205.536 -3.85365 0 0 286113. 3532.26 0.01 0.13 0.05 -1 -1 0.01 0.054238 0.0481705 239 295 60 18 54 18 + k6_frac_uripple_N8_22nm.xml Md5Core.v common 1259.85 vpr 1.03 GiB 18.42 119200 -1 -1 1 5.18 -1 -1 169000 -1 -1 4209 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1080808 641 128 63843 53443 1 23625 4978 78 78 6084 clb auto 298.6 MiB 267.64 265982 6207934 2313787 3686907 207240 1055.5 MiB 218.86 1.42 8.76338 -26782 -8.76338 8.76338 26.03 0.086622 0.0748437 13.4573 11.3319 -1 -1 -1 -1 58 374194 42 1.94536e+08 5.93179e+07 2.42024e+07 3978.04 672.28 59.587 49.4099 688856 6339671 -1 334274 17 91351 128675 11823089 2309725 6.4004 6.4004 -23909.5 -6.4004 0 0 3.02494e+07 4971.96 1.65 7.05 5.14 -1 -1 1.65 3.73867 3.13107 30395 3442 12624 36 0 0 + k6_frac_uripple_N8_22nm.xml cordic.v common 4.05 vpr 64.43 MiB 0.08 9404 -1 -1 4 0.16 -1 -1 33148 -1 -1 35 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65972 54 51 517 516 1 310 140 9 9 81 clb auto 25.4 MiB 0.67 2149 11030 2051 7862 1117 64.4 MiB 0.14 0.00 4.36445 -234.289 -4.36445 4.36445 0.09 0.00141199 0.00129434 0.0496983 0.0458465 -1 -1 -1 -1 56 4579 37 1.43728e+06 493284 231774. 2861.41 1.63 0.469693 0.406996 7704 54090 -1 3879 20 1959 7459 402962 103780 3.73026 3.73026 -208.468 -3.73026 0 0 286113. 3532.26 0.01 0.15 0.05 -1 -1 0.01 0.0602283 0.0532613 256 295 60 18 54 18 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt index 7964e15f7be..413802afe0b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt @@ -1,31 +1,31 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.86 vpr 64.10 MiB 0.09 9392 -1 -1 3 0.28 -1 -1 34500 -1 53004 68 99 1 0 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 65640 99 130 363 493 1 258 298 12 12 144 clb auto 25.1 MiB 0.11 959 66963 20877 35036 11050 64.1 MiB 0.25 0.00 2.19547 -220.397 -2.19547 2.19547 0.26 0.000888885 0.000830781 0.083606 0.0788776 -1 -1 -1 -1 44 1703 11 5.66058e+06 4.21279e+06 360780. 2505.42 0.90 0.275088 0.252948 13094 71552 -1 1588 7 435 526 37760 12301 2.62103 2.62103 -239.974 -2.62103 0 0 470765. 3269.20 0.10 0.04 0.07 -1 -1 0.10 0.0257276 0.0238689 0.008006 0.2706 0.07512 0.6543 -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 9.49 vpr 67.67 MiB 0.04 9348 -1 -1 15 0.30 -1 -1 34596 -1 54736 39 162 0 5 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 69296 162 96 999 932 1 700 302 16 16 256 mult_36 auto 28.2 MiB 0.21 5813 84298 23720 53467 7111 67.7 MiB 0.68 0.01 20.9992 -1841.13 -20.9992 20.9992 0.46 0.00373748 0.0035203 0.323095 0.304438 -1 -1 -1 -1 46 13307 40 1.21132e+07 4.08187e+06 727248. 2840.81 3.84 1.09252 1.01361 24972 144857 -1 10229 22 3566 7249 945644 266838 22.6939 22.6939 -1995.17 -22.6939 0 0 934704. 3651.19 0.21 0.39 0.13 -1 -1 0.21 0.18746 0.174886 0.007576 0.3575 0.01677 0.6257 -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 696.57 vpr 553.42 MiB 19.92 218908 -1 -1 127 252.42 -1 -1 94120 -1 131280 2033 114 44 8 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 566700 114 102 29627 29353 1 15945 2301 55 55 3025 clb auto 210.0 MiB 31.31 230514 1642173 595704 1018876 27593 540.5 MiB 48.51 0.39 78.2692 -58089.8 -78.2692 78.2692 24.93 0.086973 0.0768336 10.7593 9.09845 -1 -1 -1 -1 96 342970 28 1.75831e+08 1.3685e+08 1.91810e+07 6340.82 195.12 37.5378 31.1093 414120 4030168 -1 311902 20 61622 243318 13757769 2438696 78.5659 78.5659 -72067.7 -78.5659 -30.242 -0.295467 2.39857e+07 7929.14 7.35 8.59 3.70 -1 -1 7.35 4.77392 4.09434 0.1059 0.4192 0.01061 0.5702 -k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 3.66 vpr 64.15 MiB 0.08 9336 -1 -1 3 0.27 -1 -1 34464 -1 53020 68 99 1 0 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 65692 99 130 363 493 1 258 298 12 12 144 clb auto 25.1 MiB 0.10 959 66963 20877 35036 11050 64.2 MiB 0.23 0.00 2.19547 -220.397 -2.19547 2.19547 0.26 0.00129073 0.00122255 0.0905854 0.0857208 -1 -1 -1 -1 44 1703 11 5.66058e+06 4.21279e+06 360780. 2505.42 0.84 0.340653 0.313119 13094 71552 -1 1588 7 435 526 37760 12301 2.62103 2.62103 -239.974 -2.62103 0 0 470765. 3269.20 0.11 0.04 0.07 -1 -1 0.11 0.0252461 0.0233937 0.008984 0.2412 0.06695 0.6919 -k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml diffeq1.v common 9.88 vpr 67.66 MiB 0.06 9504 -1 -1 15 0.36 -1 -1 34620 -1 54700 39 162 0 5 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 69280 162 96 999 932 1 700 302 16 16 256 mult_36 auto 28.3 MiB 0.30 5813 84298 23720 53467 7111 67.7 MiB 0.67 0.01 20.9992 -1841.13 -20.9992 20.9992 0.51 0.00364719 0.0034382 0.315399 0.297153 -1 -1 -1 -1 46 12939 32 1.21132e+07 4.08187e+06 727248. 2840.81 3.83 1.0356 0.96046 24972 144857 -1 10365 21 3566 7284 931163 263037 22.5015 22.5015 -1988.97 -22.5015 0 0 934704. 3651.19 0.21 0.37 0.13 -1 -1 0.21 0.171081 0.159064 0.007926 0.3458 0.01615 0.6381 -k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml LU8PEEng.v common 756.18 vpr 600.11 MiB 20.31 219020 -1 -1 127 246.99 -1 -1 94172 -1 131552 1938 114 44 8 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 614516 114 102 29627 29353 1 15590 2206 53 53 2809 clb auto 215.9 MiB 63.87 221505 1566792 581029 965817 19946 520.7 MiB 48.75 0.46 78.7649 -55802 -78.7649 78.7649 23.32 0.0977564 0.0805634 11.7533 9.85012 -1 -1 -1 -1 100 329890 44 1.63647e+08 1.3173e+08 1.82848e+07 6509.36 229.47 52.8122 43.5211 391934 3893229 -1 296717 20 58974 234587 13009606 2288152 78.7037 78.7037 -67475.2 -78.7037 -22.6809 -0.293253 2.30694e+07 8212.69 7.40 8.50 3.68 -1 -1 7.40 4.85419 4.15005 0.1043 0.409 0.01013 0.5808 -k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.47 vpr 64.21 MiB 0.06 9328 -1 -1 3 0.27 -1 -1 34516 -1 52912 67 99 1 0 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 65756 99 130 363 493 1 258 297 12 12 144 clb auto 25.3 MiB 0.09 912 71577 22752 36592 12233 64.2 MiB 0.25 0.00 2.17749 -221.419 -2.17749 2.17749 0.27 0.00128772 0.00121844 0.0973662 0.092124 -1 -1 -1 -1 34 1812 15 5.66058e+06 4.1589e+06 307677. 2136.65 1.55 0.509645 0.466454 12584 59343 -1 1647 10 548 718 46799 16285 2.55443 2.55443 -235.172 -2.55443 0 0 377431. 2621.05 0.09 0.05 0.06 -1 -1 0.09 0.0317434 0.0293207 0.007928 0.2374 0.06937 0.6933 -k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml diffeq1.v common 12.05 vpr 68.07 MiB 0.06 9312 -1 -1 15 0.35 -1 -1 34604 -1 54616 38 162 0 5 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 69704 162 96 999 932 1 699 301 16 16 256 mult_36 auto 28.7 MiB 0.28 5611 83965 25982 50757 7226 68.1 MiB 0.70 0.01 20.9967 -1752.4 -20.9967 20.9967 0.56 0.00368208 0.00346882 0.327374 0.307452 -1 -1 -1 -1 46 13011 47 1.21132e+07 4.02797e+06 761464. 2974.47 5.84 1.16752 1.08182 25952 154797 -1 9769 32 3388 7483 1099104 316197 22.1698 22.1698 -1892.97 -22.1698 0 0 979054. 3824.43 0.22 0.47 0.13 -1 -1 0.22 0.238042 0.220618 0.007946 0.3448 0.01646 0.6388 -k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml LU8PEEng.v common 797.26 vpr 576.95 MiB 19.66 219040 -1 -1 127 244.26 -1 -1 94192 -1 131488 1859 114 44 8 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 590792 114 102 29627 29353 1 15873 2127 53 53 2809 clb auto 211.2 MiB 207.60 222448 1492484 550042 918799 23643 576.9 MiB 40.72 0.33 78.3072 -55670.6 -78.3072 78.3072 24.05 0.0857385 0.0755555 10.3641 8.60779 -1 -1 -1 -1 100 323169 38 1.63647e+08 1.27472e+08 1.91159e+07 6805.25 143.13 34.3369 28.4206 405500 4174239 -1 294891 16 55655 220410 11983026 2178775 79.6382 79.6382 -66134.4 -79.6382 -17.5339 -0.29436 2.40369e+07 8557.10 8.05 8.07 3.74 -1 -1 8.05 4.53198 3.91629 0.1084 0.4017 0.01015 0.5881 -k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.43 vpr 64.35 MiB 0.08 9280 -1 -1 3 0.26 -1 -1 34500 -1 53000 67 99 1 0 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 65892 99 130 363 493 1 258 297 12 12 144 clb auto 25.3 MiB 0.09 912 71577 22752 36592 12233 64.3 MiB 0.25 0.00 2.17749 -221.419 -2.17749 2.17749 0.27 0.00129969 0.00123005 0.0974263 0.0921907 -1 -1 -1 -1 32 1947 38 5.66058e+06 4.1589e+06 295695. 2053.44 1.50 0.475807 0.435965 12440 56522 -1 1697 11 551 747 46498 15792 2.47803 2.47803 -236.591 -2.47803 0 0 361905. 2513.23 0.08 0.06 0.05 -1 -1 0.08 0.0336462 0.0310363 0.009086 0.2044 0.06066 0.7349 -k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml diffeq1.v common 10.08 vpr 67.89 MiB 0.06 9368 -1 -1 15 0.36 -1 -1 34708 -1 54736 38 162 0 5 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 69524 162 96 999 932 1 699 301 16 16 256 mult_36 auto 28.5 MiB 0.28 5610 83965 25979 50756 7230 67.9 MiB 0.67 0.01 20.9967 -1752.69 -20.9967 20.9967 0.55 0.00362376 0.00341442 0.318346 0.299793 -1 -1 -1 -1 48 12263 38 1.21132e+07 4.02797e+06 791884. 3093.30 3.91 1.12515 1.04331 26208 159478 -1 9793 21 3197 6813 893738 262077 22.0098 22.0098 -1892.01 -22.0098 0 0 1.01413e+06 3961.44 0.23 0.37 0.14 -1 -1 0.23 0.172385 0.160478 0.008313 0.3353 0.01608 0.6486 -k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml LU8PEEng.v common 835.73 vpr 605.52 MiB 20.55 218940 -1 -1 127 246.80 -1 -1 94084 -1 131572 1784 114 44 8 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 620056 114 102 29627 29353 1 15339 2052 51 51 2601 clb auto 213.3 MiB 206.13 223335 1422758 511358 886246 25154 537.5 MiB 43.06 0.33 78.4175 -55205.9 -78.4175 78.4175 23.01 0.0899449 0.0795648 10.6024 8.96248 -1 -1 -1 -1 102 313896 24 1.52527e+08 1.2343e+08 1.80757e+07 6949.52 173.09 45.2786 37.4329 380370 3944208 -1 292217 19 55586 222906 12296761 2246282 79.3608 79.3608 -63694 -79.3608 -16.4456 -0.29436 2.25881e+07 8684.41 6.62 7.83 3.47 -1 -1 6.62 4.56129 3.92303 0.107 0.3895 0.009646 0.6009 -k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.60 vpr 64.82 MiB 0.06 9320 -1 -1 3 0.27 -1 -1 34644 -1 52860 67 99 1 0 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 66372 99 130 363 493 1 263 297 12 12 144 clb auto 25.8 MiB 0.09 901 72567 24766 36583 11218 64.8 MiB 0.26 0.00 2.17749 -223.572 -2.17749 2.17749 0.31 0.00129642 0.00122674 0.0986744 0.0933585 -1 -1 -1 -1 38 1762 11 5.66058e+06 4.1589e+06 347689. 2414.51 1.65 0.348272 0.319946 13432 70334 -1 1528 9 475 592 34104 11793 2.5464 2.5464 -238.385 -2.5464 0 0 440062. 3055.98 0.10 0.05 0.04 -1 -1 0.10 0.0299128 0.0276617 0.00795 0.2306 0.07376 0.6956 -k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 10.06 vpr 68.09 MiB 0.06 9364 -1 -1 15 0.38 -1 -1 34700 -1 54620 36 162 0 5 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 69728 162 96 999 932 1 700 299 16 16 256 mult_36 auto 28.8 MiB 0.24 5618 84215 26483 50655 7077 68.1 MiB 0.67 0.01 20.8745 -1914.57 -20.8745 20.8745 0.57 0.00362065 0.00341374 0.323005 0.304388 -1 -1 -1 -1 52 12761 39 1.21132e+07 3.92018e+06 875283. 3419.07 3.97 1.22658 1.13606 27812 183157 -1 9204 19 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logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc + 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/home/elgamma8/research/release/vtr-verilog-to-routing 554912 114 102 29627 29353 1 15922 2251 54 54 2916 clb auto 210.9 MiB 119.52 222919 1580073 571874 985592 22607 531.1 MiB 48.29 0.39 77.8953 -57999.4 -77.8953 77.8953 11.52 0.0926883 0.0822081 11.0789 9.32318 -1 -1 -1 -1 96 331929 43 1.70873e+08 1.34156e+08 1.84738e+07 6335.34 178.58 39.6952 32.8705 399532 3879924 -1 299844 21 60223 237835 13208126 2353586 78.7014 78.7014 -70108.8 -78.7014 -29.771 -0.29436 2.31021e+07 7922.54 1.11 9.04 3.72 -1 -1 1.11 5.15092 4.42498 0.1048 0.4082 0.01076 0.5811 + k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.05 vpr 65.32 MiB 0.08 9324 -1 -1 3 0.27 -1 -1 34472 -1 52808 69 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66884 99 130 363 493 1 258 299 12 12 144 clb auto 25.6 MiB 0.09 913 66233 21239 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70232 162 96 999 932 1 692 302 16 16 256 mult_36 auto 28.6 MiB 0.26 5546 83286 26609 49026 7651 68.6 MiB 0.64 0.01 21.0243 -1894.68 -21.0243 21.0243 0.26 0.00355367 0.00335054 0.310396 0.292545 -1 -1 -1 -1 54 11790 34 1.21132e+07 4.08187e+06 835850. 3265.04 6.08 1.44279 1.33344 26248 167850 -1 9592 19 3142 6275 854413 269675 22.0932 22.0932 -1987.22 -22.0932 0 0 1.08614e+06 4242.72 0.04 0.35 0.15 -1 -1 0.04 0.160799 0.149782 0.00805 0.3587 0.01739 0.6239 + k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 719.26 vpr 546.14 MiB 18.47 218876 -1 -1 127 261.95 -1 -1 94060 -1 131520 1971 114 44 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 559248 114 102 29627 29353 1 15847 2239 54 54 2916 clb auto 209.6 MiB 135.16 225408 1598108 582829 992381 22898 530.2 MiB 44.62 0.37 78.1966 -55511.9 -78.1966 78.1966 9.94 0.0937316 0.0830703 10.8349 9.12795 -1 -1 -1 -1 98 325803 29 1.70873e+08 1.33509e+08 1.87532e+07 6431.13 134.61 35.0377 28.9908 405364 4004376 -1 300586 20 59494 234219 12688820 2264650 78.0957 78.0957 -66362.9 -78.0957 -27.2952 -0.295467 2.37782e+07 8154.37 1.22 8.76 3.81 -1 -1 1.22 4.98031 4.28265 0.1071 0.4088 0.01084 0.5803 + k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 3.21 vpr 65.15 MiB 0.06 9328 -1 -1 3 0.33 -1 -1 34540 -1 52848 69 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66716 99 130 363 493 1 263 299 12 12 144 clb auto 25.4 MiB 0.10 990 67232 22930 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3.69 -1 -1 1.15 4.54132 3.87896 0.1061 0.3948 0.01039 0.5948 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt index e44f94f6fb4..746a413d647 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt @@ -1,15 +1,15 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 1042.27 vpr 681.79 MiB 25.44 379864 -1 -1 22 518.01 -1 -1 154072 -1 116500 2560 257 0 11 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 698152 257 32 32041 31556 1 18655 2860 61 61 3721 clb auto 233.1 MiB 36.39 248784 1971184 693534 1249697 27953 667.6 MiB 67.38 0.57 17.2227 -24536 -17.2227 17.2227 32.23 0.0949015 0.0847155 10.7087 9.08247 -1 -1 -1 -1 82 383775 24 2.18169e+08 1.42327e+08 2.04246e+07 5489.00 212.07 51.8327 42.9917 475364 4274107 -1 368989 20 108548 499678 20761050 3200843 17.2471 17.2471 -24997.9 -17.2471 0 0 2.56329e+07 6888.72 9.50 12.11 3.85 -1 -1 9.50 5.44089 4.71206 0.1728 0.4587 0.02687 0.5144 -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml blob_merge.v common 178.53 vpr 135.18 MiB 0.80 62972 -1 -1 18 80.57 -1 -1 65724 -1 50856 547 36 0 0 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 138428 36 100 6600 6700 1 2882 683 30 30 900 clb auto 68.0 MiB 4.70 44999 244169 69488 159892 14789 114.4 MiB 5.78 0.06 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 341240 506 553 3285 3838 1 3021 1578 50 50 2500 memory auto 47.5 MiB 4.88 14975 1131087 537386 412299 181402 333.2 MiB 5.48 0.06 7.31798 -1716.46 -7.31798 7.31798 9.59 0.0233425 0.0202789 2.88885 2.58827 -1 -1 -1 -1 38 21877 13 1.47946e+08 5.11946e+07 6.86584e+06 2746.33 21.59 9.34517 8.46777 251304 1421084 -1 21223 14 3882 5152 957849 258652 7.69928 7.69928 -2017.61 -7.69928 -4.40929 -0.295467 8.69095e+06 3476.38 0.42 0.99 1.24 -1 -1 0.42 0.812677 0.750095 0.16 0.1404 0.03929 0.8203 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkPktMerge.v common 11.90 vpr 71.21 MiB 0.17 16564 -1 -1 2 0.57 -1 -1 33572 -1 60112 29 311 15 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72916 311 156 972 1128 1 953 511 28 28 784 memory auto 28.6 MiB 0.52 8675 196543 71995 115326 9222 71.2 MiB 1.12 0.02 3.94157 -4520.2 -3.94157 3.94157 0.88 0.00450683 0.00400124 0.539697 0.478132 -1 -1 -1 -1 38 14424 15 4.25198e+07 9.78293e+06 2.03942e+06 2601.30 3.08 1.42389 1.26202 75902 416746 -1 13482 13 2485 2939 742342 220707 4.30811 4.30811 -5120.27 -4.30811 -9.59348 -0.340786 2.58559e+06 3297.95 0.11 0.34 0.35 -1 -1 0.11 0.190264 0.171934 0.08518 0.1546 0.01779 0.8276 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkSMAdapter4B.v common 20.15 vpr 76.48 MiB 0.45 30028 -1 -1 7 2.80 -1 -1 37892 -1 59140 166 193 5 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78316 193 205 2232 2437 1 1230 569 20 20 400 memory auto 35.7 MiB 1.01 9358 240983 80731 132632 27620 76.5 MiB 1.73 0.02 5.06623 -2804.81 -5.06623 5.06623 0.43 0.00696087 0.00630657 0.736351 0.662847 -1 -1 -1 -1 46 17929 33 2.07112e+07 1.16864e+07 1.18195e+06 2954.88 7.39 2.49645 2.21716 40048 238620 -1 14832 16 4536 11233 579630 132122 5.42812 5.42812 -3017.08 -5.42812 -8.60084 -0.359474 1.52036e+06 3800.91 0.05 0.44 0.21 -1 -1 0.05 0.286104 0.260109 0.02818 0.2078 0.02581 0.7664 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml or1200.v common 55.48 vpr 103.80 MiB 0.94 40848 -1 -1 27 5.16 -1 -1 43924 -1 61440 247 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 106292 385 394 3979 4310 1 2366 1029 27 27 729 io auto 47.1 MiB 2.79 31256 577452 220184 332574 24694 90.8 MiB 5.47 0.06 14.223 -11856.8 -14.223 14.223 0.83 0.016611 0.0155207 2.13767 1.96728 -1 -1 -1 -1 78 49772 44 3.93038e+07 1.48038e+07 3.65949e+06 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0.258873 0.02191 0.4692 0.04307 0.4877 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml sha.v common 522.61 abc 94.14 MiB 1.59 38664 -1 -1 20 496.43 -1 -1 96404 -1 46400 231 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 86112 38 36 3404 3440 1 1299 305 20 20 400 clb auto 42.7 MiB 1.75 14687 64943 16819 44848 3276 84.1 MiB 1.34 0.02 13.5301 -4881.23 -13.5301 13.5301 0.43 0.00872776 0.00786542 0.616796 0.54249 -1 -1 -1 -1 56 24982 33 2.07112e+07 1.24495e+07 1.41661e+06 3541.53 7.53 2.50686 2.16704 42444 283345 -1 21461 15 5499 21648 703274 121673 14.3477 14.3477 -5041.91 -14.3477 0 0 1.80858e+06 4521.44 0.06 0.57 0.24 -1 -1 0.06 0.350084 0.313149 0.01034 0.3838 0.02922 0.587 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mcml.v common 8023.20 vpr 1.87 GiB 83.23 923700 -1 -1 75 6961.27 -1 -1 447876 -1 340272 7516 36 159 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1957912 36 356 135102 133883 1 42070 8094 103 103 10609 clb auto 726.6 MiB 80.63 518483 11055510 4565633 6404934 84943 1912.0 MiB 184.45 1.38 68.3226 -364781 -68.3226 68.3226 42.76 0.254885 0.21869 37.8791 31.4262 -1 -1 -1 -1 82 699404 45 6.46441e+08 5.02852e+08 5.95200e+07 5610.33 254.16 127.752 104.712 1372100 12531702 -1 665004 19 157793 498465 26586492 5156950 69.6527 69.6527 -457878 -69.6527 0 0 7.45804e+07 7029.92 3.45 20.21 11.41 -1 -1 3.45 13.9724 11.9555 0.2965 0.3745 0.01315 0.6123 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc/config/golden_results.txt index 4c1d5cbd7fa..801b3e6f120 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc/config/golden_results.txt @@ -1,21 +1,21 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 6.44 vpr 64.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65860 14 8 926 934 0 490 100 11 11 121 clb auto 24.8 MiB 0.91 4540 5436 746 4365 325 64.3 MiB 0.22 0.01 4.4958 -31.528 -4.4958 nan 0.32 0.00518513 0.00476183 0.142243 0.131594 52 7157 39 4.36541e+06 4.20373e+06 379421. 3135.71 3.12 1.54305 1.41039 12531 77429 -1 6624 17 3168 14393 437125 83566 4.8594 nan -34.0978 -4.8594 0 0 499620. 4129.09 0.12 0.35 0.11 -1 -1 0.12 0.217292 0.201716 -k6_frac_N10_40nm.xml apex2.pre-vpr.blif common 10.42 vpr 66.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 103 38 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 67776 38 3 1113 1116 0 662 144 13 13 169 clb auto 26.6 MiB 1.57 7370 11454 1699 8583 1172 66.2 MiB 0.36 0.01 5.6032 -16.0295 -5.6032 nan 0.48 0.00608264 0.00556782 0.216301 0.199813 66 12625 26 6.52117e+06 5.55108e+06 710325. 4203.11 5.48 1.80568 1.65233 19379 142405 -1 11924 18 4624 23024 803122 126844 5.75407 nan -16.4608 -5.75407 0 0 879032. 5201.38 0.21 0.49 0.22 -1 -1 0.21 0.268726 0.249892 -k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 8.36 vpr 64.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65900 9 19 897 916 0 556 110 12 12 144 clb auto 24.8 MiB 1.43 6155 6948 1152 5347 449 64.4 MiB 0.19 0.00 4.85584 -79.8781 -4.85584 nan 0.40 0.00184535 0.00164299 0.102414 0.0941394 64 10771 28 5.3894e+06 4.41931e+06 575115. 3993.85 4.15 1.4005 1.27741 16224 115365 -1 9685 19 3941 19896 705511 115372 5.17072 nan -84.2996 -5.17072 0 0 716128. 4973.11 0.16 0.44 0.18 -1 -1 0.16 0.238518 0.221526 -k6_frac_N10_40nm.xml bigkey.pre-vpr.blif common 9.13 vpr 65.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 67428 229 197 1364 1561 1 539 497 16 16 256 io auto 26.3 MiB 0.80 3888 151956 45040 98819 8097 65.8 MiB 1.02 0.01 3.01736 -656.133 -3.01736 3.01736 0.79 0.00693433 0.00645616 0.560233 0.521561 38 7443 37 1.05632e+07 3.82647e+06 667532. 2607.55 3.90 2.38635 2.22107 25328 137766 -1 6882 14 1605 4348 206877 47610 3.0708 3.0708 -728.475 -3.0708 0 0 843755. 3295.92 0.23 0.33 0.19 -1 -1 0.23 0.246405 0.231441 -k6_frac_N10_40nm.xml clma.pre-vpr.blif common 43.74 vpr 89.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 307 62 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91560 62 82 3672 3754 1 2344 451 20 20 400 clb auto 45.4 MiB 4.13 29194 126595 33709 86071 6815 89.4 MiB 3.36 0.04 7.83344 -342.752 -7.83344 7.83344 1.33 0.0213741 0.0195703 1.719 1.5557 92 46721 44 1.74617e+07 1.65455e+07 2.37849e+06 5946.23 27.30 8.57955 7.81451 54288 506964 -1 42503 16 14653 63396 2356990 367690 8.12752 8.12752 -355.073 -8.12752 0 0 3.01539e+06 7538.48 0.77 1.55 0.89 -1 -1 0.77 0.838641 0.780724 -k6_frac_N10_40nm.xml des.pre-vpr.blif common 9.42 vpr 62.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 51 256 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64488 256 245 954 1199 0 578 552 18 18 324 io auto 23.8 MiB 0.31 4966 131806 34568 89483 7755 63.0 MiB 0.74 0.01 3.70962 -712.314 -3.70962 nan 1.04 0.00594369 0.00563587 0.363143 0.344074 36 9086 34 1.37969e+07 2.74859e+06 824466. 2544.65 4.56 1.92823 1.82519 31748 166456 -1 8145 16 2076 4578 247499 55677 4.28288 nan -799.816 -4.28288 0 0 1.01518e+06 3133.28 0.29 0.31 0.23 -1 -1 0.29 0.217585 0.206808 -k6_frac_N10_40nm.xml diffeq.pre-vpr.blif common 5.00 vpr 64.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 65 64 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66216 64 39 1371 1410 1 542 168 11 11 121 clb auto 25.5 MiB 0.49 3387 16373 2957 12425 991 64.7 MiB 0.34 0.01 5.33717 -1012.06 -5.33717 5.33717 0.32 0.00551817 0.00506527 0.217367 0.199664 46 5978 20 4.36541e+06 3.50311e+06 343362. 2837.71 2.08 1.1317 1.03145 12051 69045 -1 5146 15 1964 5478 158754 33013 5.81148 5.81148 -1104.11 -5.81148 0 0 440296. 3638.81 0.10 0.26 0.10 -1 -1 0.10 0.200354 0.185353 -k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 13.46 vpr 65.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70 229 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 67568 229 197 1362 1559 1 570 496 16 16 256 io auto 26.5 MiB 0.92 4585 165304 49025 107137 9142 66.0 MiB 1.16 0.01 3.10283 -686.218 -3.10283 3.10283 0.79 0.00699037 0.00652345 0.625484 0.582292 34 9041 35 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-1 84 41 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66792 41 35 1006 1041 0 604 160 12 12 144 clb auto 25.8 MiB 1.25 6526 13180 2280 9516 1384 65.2 MiB 0.34 0.01 4.5556 -135.416 -4.5556 nan 0.40 0.00567464 0.00519319 0.194713 0.180099 64 11365 46 5.3894e+06 4.5271e+06 575115. 3993.85 7.24 2.30466 2.10936 16224 115365 -1 10143 18 4137 19881 679868 115960 4.93645 nan -144.738 -4.93645 0 0 716128. 4973.11 0.16 0.46 0.18 -1 -1 0.16 0.25103 0.233257 -k6_frac_N10_40nm.xml spla.pre-vpr.blif common 21.57 vpr 77.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 216 16 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79132 16 46 2232 2278 0 1170 278 17 17 289 clb auto 35.6 MiB 2.77 15884 45628 10574 32142 2912 77.3 MiB 1.36 0.02 5.95671 -204.452 -5.95671 nan 0.91 0.0133587 0.0121199 0.775594 0.707225 74 25546 32 1.21262e+07 1.16411e+07 1.39325e+06 4820.95 11.37 4.19873 3.8273 35379 286977 -1 24647 19 7675 42760 1737904 249467 6.14143 nan -217.643 -6.14143 0 0 1.74421e+06 6035.33 0.44 1.20 0.46 -1 -1 0.44 0.621038 0.575028 -k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 4.92 vpr 65.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 61 52 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66784 52 122 1461 1583 1 474 235 10 10 100 clb auto 26.2 MiB 0.55 2490 35711 8852 25144 1715 65.2 MiB 0.47 0.01 4.73051 -1125.66 -4.73051 4.73051 0.26 0.00536421 0.00491253 0.285644 0.261717 46 4691 25 3.44922e+06 3.28753e+06 276332. 2763.32 2.04 1.3096 1.19377 9816 55112 -1 4036 15 1411 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place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 5.16 vpr 64.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65944 14 8 926 934 0 490 100 11 11 121 clb auto 24.8 MiB 0.89 4639 5668 847 4419 402 64.4 MiB 0.16 0.01 4.54815 -31.8355 -4.54815 nan 0.11 0.00261159 0.00232467 0.0841871 0.076513 -1 -1 -1 -1 48 7214 49 4.36541e+06 4.20373e+06 357017. 2950.55 2.66 0.880153 0.750327 12171 71069 -1 6577 19 3324 15359 408061 81134 4.87162 nan -34.7178 -4.87162 0 0 455885. 3767.64 0.01 0.27 0.06 -1 -1 0.01 0.140373 0.125542 + k6_frac_N10_40nm.xml apex2.pre-vpr.blif common 7.63 vpr 66.33 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/home/elgamma8/research/release/vtr-verilog-to-routing 65932 9 19 897 916 0 556 110 12 12 144 clb auto 24.9 MiB 1.39 6252 7474 1266 5720 488 64.4 MiB 0.21 0.01 4.74237 -77.8307 -4.74237 nan 0.14 0.00279294 0.00250543 0.096856 0.0884436 -1 -1 -1 -1 62 10739 47 5.3894e+06 4.41931e+06 554770. 3852.57 3.46 1.02986 0.886777 15940 110000 -1 9728 17 4391 21118 675575 120995 5.20821 nan -84.4166 -5.20821 0 0 687181. 4772.09 0.02 0.31 0.09 -1 -1 0.02 0.132804 0.119663 + k6_frac_N10_40nm.xml bigkey.pre-vpr.blif common 5.33 vpr 65.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67420 229 197 1364 1561 1 539 497 16 16 256 io auto 26.1 MiB 0.79 4504 148022 42306 97632 8084 65.8 MiB 0.82 0.01 2.97254 -656.061 -2.97254 2.97254 0.27 0.00449011 0.00417919 0.35606 0.331144 -1 -1 -1 -1 36 7822 26 1.05632e+07 3.82647e+06 638738. 2495.07 1.79 1.11868 1.02782 24820 128426 -1 7098 11 1611 3987 187232 44731 3.15649 3.15649 -738.429 -3.15649 0 0 786978. 3074.13 0.03 0.20 0.10 -1 -1 0.03 0.13819 0.129003 + k6_frac_N10_40nm.xml clma.pre-vpr.blif common 29.41 vpr 89.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 316 62 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 91496 62 82 3672 3754 1 2348 460 20 20 400 clb auto 45.2 MiB 3.88 29602 121160 32274 82250 6636 89.4 MiB 2.62 0.04 7.97523 -360.045 -7.97523 7.97523 0.44 0.0148917 0.0123882 0.964104 0.824254 -1 -1 -1 -1 92 48575 45 1.74617e+07 1.70305e+07 2.37849e+06 5946.23 17.26 5.37402 4.51033 54288 506964 -1 43403 17 15069 65645 2357098 375873 8.16272 8.16272 -366.296 -8.16272 0 0 3.01539e+06 7538.48 0.10 1.23 0.42 -1 -1 0.10 0.552812 0.496854 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66192 64 39 1371 1410 1 541 167 10 10 100 clb auto 25.1 MiB 0.50 3623 18986 4100 13819 1067 64.6 MiB 0.29 0.01 5.32461 -1004.72 -5.32461 5.32461 0.09 0.00311791 0.00279289 0.147968 0.134197 -1 -1 -1 -1 50 5495 30 3.44922e+06 3.44922e+06 295697. 2956.97 2.48 1.15638 1.00085 10016 58256 -1 4877 17 1881 5375 141590 30815 5.49357 5.49357 -1059.83 -5.49357 0 0 379824. 3798.24 0.01 0.11 0.03 -1 -1 0.01 0.0869823 0.0803709 + k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 7.24 vpr 65.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67020 229 197 1362 1559 1 570 496 16 16 256 io auto 25.9 MiB 0.92 5066 137836 36889 92766 8181 65.4 MiB 0.83 0.01 2.91431 -671.379 -2.91431 2.91431 0.27 0.00448988 0.00419125 0.351186 0.326741 -1 -1 -1 -1 36 8862 27 1.05632e+07 3.77258e+06 638738. 2495.07 3.54 1.6488 1.51079 24820 128426 -1 7675 13 1986 5211 265646 63312 3.18697 3.18697 -739.19 -3.18697 0 0 786978. 3074.13 0.03 0.23 0.10 -1 -1 0.03 0.157841 0.146845 + k6_frac_N10_40nm.xml elliptic.pre-vpr.blif common 14.52 vpr 77.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 171 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79436 131 114 3421 3535 1 1164 416 16 16 256 clb auto 36.3 MiB 3.47 10474 95088 26501 63930 4657 77.6 MiB 1.19 0.02 7.51043 -4391.12 -7.51043 7.51043 0.27 0.00762209 0.00685426 0.530205 0.466193 -1 -1 -1 -1 56 18313 31 1.05632e+07 9.21587e+06 942187. 3680.42 6.67 2.5886 2.2427 28136 192436 -1 15484 16 5183 22017 710369 128360 7.51944 7.51944 -4543.65 -7.51944 0 0 1.20185e+06 4694.72 0.04 0.54 0.15 -1 -1 0.04 0.344922 0.311996 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 25.26 vpr 82.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 285 10 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84000 10 10 2659 2669 0 1401 305 19 19 361 clb auto 39.5 MiB 4.53 26220 51605 13492 36245 1868 82.0 MiB 1.24 0.02 6.59302 -61.9652 -6.59302 nan 0.39 0.00787717 0.00693136 0.475136 0.405537 -1 -1 -1 -1 90 42829 31 1.55754e+07 1.53598e+07 2.09179e+06 5794.43 14.64 3.52852 2.9687 48131 439069 -1 39158 17 9518 58062 2365838 328796 6.83753 nan -64.8858 -6.83753 0 0 2.60973e+06 7229.16 0.09 1.12 0.37 -1 -1 0.09 0.426225 0.383395 + k6_frac_N10_40nm.xml ex5p.pre-vpr.blif common 4.09 vpr 62.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 8 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64476 8 63 761 824 0 435 134 10 10 100 clb auto 23.6 MiB 0.77 3999 11420 2063 8488 869 63.0 MiB 0.21 0.01 3.77984 -169.82 -3.77984 nan 0.09 0.00239284 0.00215421 0.0972723 0.0888313 -1 -1 -1 -1 58 6565 28 3.44922e+06 3.39532e+06 342720. 3427.20 1.79 0.648473 0.563539 10608 68480 -1 5918 16 2541 10577 323005 63220 4.22288 nan -188.35 -4.22288 0 0 435638. 4356.38 0.01 0.19 0.06 -1 -1 0.01 0.105677 0.0956385 + k6_frac_N10_40nm.xml frisc.pre-vpr.blif common 13.26 vpr 77.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 167 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79316 20 116 3175 3291 1 1338 303 15 15 225 clb auto 36.2 MiB 3.13 14602 62340 15718 42273 4349 77.5 MiB 1.19 0.02 8.56273 -4519.63 -8.56273 8.56273 0.23 0.00775606 0.00702614 0.536242 0.475888 -1 -1 -1 -1 80 24018 43 9.10809e+06 9.0003e+06 1.12687e+06 5008.33 5.63 2.43667 2.13078 28171 234221 -1 21050 15 6703 26493 1041429 176822 9.09101 9.09101 -4756.62 -9.09101 0 0 1.41774e+06 6301.08 0.04 0.61 0.19 -1 -1 0.04 0.331662 0.300028 + k6_frac_N10_40nm.xml misex3.pre-vpr.blif common 4.57 vpr 63.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65212 14 14 828 842 0 475 99 11 11 121 clb auto 24.1 MiB 0.92 4532 5343 748 4219 376 63.7 MiB 0.15 0.01 4.39029 -57.6027 -4.39029 nan 0.11 0.00248516 0.00222328 0.0774866 0.0708311 -1 -1 -1 -1 52 7728 41 4.36541e+06 3.82647e+06 379421. 3135.71 2.10 0.733439 0.630441 12531 77429 -1 6634 16 3040 13763 383785 71279 4.69105 nan -60.7462 -4.69105 0 0 499620. 4129.09 0.01 0.22 0.06 -1 -1 0.01 0.11464 0.1034 + k6_frac_N10_40nm.xml pdc.pre-vpr.blif common 21.91 vpr 82.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 272 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84436 16 40 2839 2879 0 1511 328 19 19 361 clb auto 39.8 MiB 3.39 23598 55698 13292 40268 2138 82.5 MiB 1.30 0.02 6.48626 -238.484 -6.48626 nan 0.40 0.00882838 0.00732248 0.497678 0.42275 -1 -1 -1 -1 82 38584 40 1.55754e+07 1.46592e+07 1.91630e+06 5308.30 12.46 3.24821 2.7604 46331 403357 -1 35281 17 9680 52085 1891572 294823 6.8403 nan -243.508 -6.8403 0 0 2.40187e+06 6653.38 0.08 1.01 0.33 -1 -1 0.08 0.437512 0.392895 + k6_frac_N10_40nm.xml s298.pre-vpr.blif common 2.88 vpr 62.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63972 4 6 726 732 1 395 74 10 10 100 clb auto 23.1 MiB 0.73 3639 2709 340 2252 117 62.5 MiB 0.07 0.00 6.02711 -48.0055 -6.02711 6.02711 0.08 0.0010205 0.000898899 0.032602 0.0300701 -1 -1 -1 -1 50 5470 24 3.44922e+06 3.44922e+06 295697. 2956.97 0.91 0.327596 0.288129 10016 58256 -1 4992 17 2195 9283 271197 50082 6.42868 6.42868 -51.2874 -6.42868 0 0 379824. 3798.24 0.01 0.18 0.05 -1 -1 0.01 0.106672 0.0965561 + k6_frac_N10_40nm.xml s38417.pre-vpr.blif common 12.83 vpr 86.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 250 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 88964 29 106 4782 4888 1 1993 385 18 18 324 clb auto 44.6 MiB 2.49 13385 89985 21640 60579 7766 86.9 MiB 1.53 0.02 5.22969 -3570.14 -5.22969 5.22969 0.35 0.00959865 0.008535 0.694501 0.599971 -1 -1 -1 -1 50 21612 42 1.37969e+07 1.34735e+07 1.08879e+06 3360.46 4.74 2.80262 2.39638 34656 222912 -1 19075 14 7130 20879 621675 127526 5.31212 5.31212 -3691.5 -5.31212 0 0 1.40279e+06 4329.61 0.05 0.58 0.17 -1 -1 0.05 0.405856 0.364092 + k6_frac_N10_40nm.xml s38584.1.pre-vpr.blif common 15.17 vpr 85.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 228 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 88036 38 304 4422 4726 1 1994 570 18 18 324 clb auto 43.2 MiB 2.53 13819 172996 49998 111442 11556 86.0 MiB 2.00 0.03 4.76683 -2916.88 -4.76683 4.76683 0.34 0.00989457 0.00890887 0.808389 0.705884 -1 -1 -1 -1 58 23055 36 1.37969e+07 1.22878e+07 1.26150e+06 3893.53 6.60 3.80943 3.29187 36592 261672 -1 20398 14 6469 17425 591858 126037 4.97859 4.97859 -3048.53 -4.97859 0 0 1.60510e+06 4954.00 0.05 0.58 0.21 -1 -1 0.05 0.422141 0.383308 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.65 vpr 65.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66668 41 35 1006 1041 0 604 160 12 12 144 clb auto 25.4 MiB 1.19 6515 13180 2173 9685 1322 65.1 MiB 0.24 0.01 4.58553 -134.055 -4.58553 nan 0.14 0.00264486 0.00235005 0.0999925 0.09047 -1 -1 -1 -1 64 10841 30 5.3894e+06 4.5271e+06 575115. 3993.85 2.46 0.814658 0.704026 16224 115365 -1 9534 17 3641 17204 511035 92223 4.88481 nan -140.076 -4.88481 0 0 716128. 4973.11 0.02 0.29 0.09 -1 -1 0.02 0.147344 0.133243 + k6_frac_N10_40nm.xml spla.pre-vpr.blif common 20.41 vpr 77.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 216 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78924 16 46 2232 2278 0 1170 278 17 17 289 clb auto 35.3 MiB 2.70 16089 42000 9359 30203 2438 77.1 MiB 0.81 0.02 5.95204 -207.143 -5.95204 nan 0.30 0.00525519 0.00454263 0.288327 0.254222 -1 -1 -1 -1 68 27700 45 1.21262e+07 1.16411e+07 1.30851e+06 4527.71 13.13 2.97958 2.51831 34227 265321 -1 23554 19 8023 43603 1540936 228530 6.17174 nan -217.21 -6.17174 0 0 1.61843e+06 5600.10 0.05 0.86 0.21 -1 -1 0.05 0.373493 0.33657 + k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 3.28 vpr 65.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66580 52 122 1461 1583 1 472 237 10 10 100 clb auto 25.6 MiB 0.57 2690 30290 6635 22073 1582 65.0 MiB 0.30 0.01 4.95966 -1122.48 -4.95966 4.95966 0.09 0.00301411 0.00273882 0.141986 0.129529 -1 -1 -1 -1 46 4786 25 3.44922e+06 3.39532e+06 276332. 2763.32 1.04 0.627009 0.552567 9816 55112 -1 4250 13 1489 3922 122560 29939 5.00101 5.00101 -1209.26 -5.00101 0 0 354105. 3541.05 0.01 0.16 0.04 -1 -1 0.01 0.116497 0.106123 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt index 1ceb9578fa8..9405554e3bd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt @@ -1,20 +1,20 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_40nm.xml alu4.pre-vpr.blif common 8.55 vpr 64.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 97 14 -1 -1 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65700 14 8 926 934 0 517 119 12 12 144 clb auto 25.0 MiB 0.45 4999 8879 1390 6975 514 64.2 MiB 0.20 0.01 5.06551 -38.2757 -5.06551 nan 0.39 0.00158196 0.0012423 0.0754693 0.0645508 -1 -1 -1 -1 44 7317 35 1.8e+06 1.746e+06 394711. 2741.05 4.48 0.974727 0.839816 11464 79652 -1 6325 25 4240 16737 572059 90972 5.28978 nan -37.6562 -5.28978 0 0 511253. 3550.37 0.18 0.38 0.07 -1 -1 0.18 0.171255 0.155339 -k6_N10_40nm.xml apex2.pre-vpr.blif common 8.76 vpr 65.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 114 38 -1 -1 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 67348 39 3 1113 1117 0 676 156 13 13 169 clb auto 26.1 MiB 0.64 7918 14821 2638 10792 1391 65.8 MiB 0.42 0.01 5.90722 -17.5854 -5.90722 nan 0.47 0.00428283 0.00360168 0.158762 0.140089 -1 -1 -1 -1 62 12758 32 2.178e+06 2.052e+06 652532. 3861.14 3.88 0.891905 0.775114 15366 127615 -1 12093 24 6108 26868 1139076 155556 5.87992 nan -17.0763 -5.87992 0 0 801739. 4744.02 0.27 0.51 0.12 -1 -1 0.27 0.197711 0.179939 -k6_N10_40nm.xml apex4.pre-vpr.blif common 7.45 vpr 64.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 95 9 -1 -1 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65620 9 19 897 916 0 568 123 12 12 144 clb auto 24.7 MiB 0.49 6597 8358 1363 6514 481 64.1 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64460 8 63 761 824 0 451 153 12 12 144 clb auto 24.0 MiB 0.36 4546 14468 2684 10639 1145 62.9 MiB 0.26 0.01 4.52309 -198.681 -4.52309 nan 0.49 0.00118271 0.000925606 0.101229 0.0900942 -1 -1 -1 -1 48 7679 49 1.8e+06 1.476e+06 423548. 2941.31 5.16 1.03606 0.893613 11752 84318 -1 6741 20 4041 16856 693280 109643 4.56024 nan -202.106 -4.56024 0 0 546237. 3793.31 0.18 0.27 0.08 -1 -1 0.18 0.102123 0.0923636 -k6_N10_40nm.xml frisc.pre-vpr.blif common 32.16 vpr 76.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 242 20 -1 -1 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 78444 20 116 3175 3291 1 1258 378 18 18 324 clb auto 35.6 MiB 1.06 15200 83704 21342 56824 5538 76.6 MiB 1.48 0.02 10.1942 -5061.1 -10.1942 10.1942 1.08 0.00401498 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65816 52 122 1461 1583 1 525 279 13 13 169 clb auto 25.2 MiB 0.34 3205 42185 9478 30169 2538 64.3 MiB 0.30 0.01 5.73017 -1218.51 -5.73017 5.73017 0.48 0.00160768 0.00134372 0.0787468 0.0649553 -1 -1 -1 -1 30 5038 31 2.178e+06 1.89e+06 350324. 2072.92 0.92 0.326072 0.27382 12006 67531 -1 4389 18 2512 6814 252428 49786 5.32906 5.32906 -1222.04 -5.32906 0 0 430798. 2549.10 0.15 0.26 0.06 -1 -1 0.15 0.14434 0.131338 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77376 131 114 3421 3535 1 1197 487 18 18 324 clb auto 34.5 MiB 0.88 12132 123047 34177 83673 5197 75.6 MiB 1.33 0.02 7.4606 -4613.61 -7.4606 7.4606 0.33 0.00799169 0.00683063 0.533887 0.467114 -1 -1 -1 -1 52 19935 35 4.608e+06 4.356e+06 1.09957e+06 3393.73 5.62 2.58917 2.24384 27876 225772 -1 16865 24 7619 33177 1410533 212600 7.58148 7.58148 -4794.49 -7.58148 0 0 1.44575e+06 4462.18 0.05 0.80 0.17 -1 -1 0.05 0.430849 0.380256 + k6_N10_40nm.xml ex1010.pre-vpr.blif common 23.62 vpr 79.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 322 10 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81104 10 10 2659 2669 0 1386 342 20 20 400 clb auto 36.8 MiB 1.37 27552 61287 15872 43555 1860 79.2 MiB 1.33 0.02 7.05556 -66.589 -7.05556 nan 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0.02 6.63208 -224.84 -6.63208 nan 0.38 0.00689474 0.00584076 0.390968 0.336886 -1 -1 -1 -1 60 30174 42 5.202e+06 4.77e+06 1.43744e+06 3981.82 14.90 3.32674 2.80555 32910 290117 -1 25425 24 9835 57132 2445755 336723 6.52939 nan -226.972 -6.52939 0 0 1.79849e+06 4981.96 0.06 1.14 0.23 -1 -1 0.06 0.410205 0.363021 + k6_N10_40nm.xml tseng.pre-vpr.blif common 5.72 vpr 64.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 112 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65796 52 122 1461 1583 1 500 286 13 13 169 clb auto 24.6 MiB 0.31 3158 39808 8713 28658 2437 64.3 MiB 0.35 0.01 6.15771 -1276.75 -6.15771 6.15771 0.16 0.00319459 0.00292205 0.149655 0.136345 -1 -1 -1 -1 26 4848 34 2.178e+06 2.016e+06 310759. 1838.81 2.44 1.14951 1.00345 11502 59218 -1 4210 17 2436 6640 243507 54081 5.71256 5.71256 -1266.26 -5.71256 0 0 383419. 2268.75 0.01 0.20 0.05 -1 -1 0.01 0.124909 0.111658 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_hard_block_arch/config/golden_results.txt index f5251301604..a3f5660315d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_hard_block_arch/config/golden_results.txt @@ -1,9 +1,9 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time num_fpu -hard_fpu_arch_timing.xml bfly.v common 6.14 vpr 62.38 MiB 0.04 7212 -1 -1 1 0.05 -1 -1 31024 -1 -1 0 193 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63872 193 64 833 649 1 353 260 24 24 576 io auto 23.4 MiB 3.45 5270 64093 26913 36818 362 62.4 MiB 0.81 0.01 2.985 -1388.77 -2.985 2.985 0.00 0.00780093 0.00749265 0.620138 0.595835 7269 20.6506 1911 5.42898 502 663 292581 62228 1.06129e+06 103149 1.28794e+06 2236.02 4 31350 258969 -1 2.985 2.985 -1374.24 -2.985 -40.8482 -0.0851 0.57 -1 -1 62.4 MiB 0.17 0.727974 0.700185 62.4 MiB -1 0.45 3 -hard_fpu_arch_timing.xml bgm.v common 7.32 vpr 66.50 MiB 0.09 8960 -1 -1 1 0.06 -1 -1 31548 -1 -1 0 257 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68092 257 32 1281 693 1 861 298 38 38 1444 block_FPU auto 27.5 MiB 1.16 16522 99798 44225 55105 468 66.5 MiB 2.09 0.02 2.985 -3185.75 -2.985 2.985 0.00 0.0163994 0.0158581 1.68623 1.6313 22762 26.4674 5833 6.78256 1476 2064 1080688 230994 2.90196e+06 309448 3.35777e+06 2325.33 6 79768 674274 -1 2.985 2.985 -3345.27 -2.985 -44.0704 -0.0851 1.36 -1 -1 66.5 MiB 0.55 1.97993 1.91753 66.5 MiB -1 1.25 9 -hard_fpu_arch_timing.xml dscg.v common 9.89 vpr 62.29 MiB 0.05 7196 -1 -1 1 0.06 -1 -1 31120 -1 -1 0 129 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63784 129 64 769 585 1 438 197 30 30 900 block_FPU auto 23.5 MiB 6.56 6049 46610 19774 26513 323 62.3 MiB 0.78 0.01 2.985 -1429.54 -2.985 2.985 0.00 0.00752857 0.00722714 0.624964 0.600088 8579 19.6316 2232 5.10755 679 809 410931 90713 1.6779e+06 137533 2.03108e+06 2256.75 4 48532 406344 -1 2.985 2.985 -1485.8 -2.985 -28.1681 -0.0851 0.84 -1 -1 62.3 MiB 0.19 0.729083 0.700795 62.3 MiB -1 0.73 4 -hard_fpu_arch_timing.xml fir.v common 57.40 vpr 62.87 MiB 0.06 7616 -1 -1 1 0.06 -1 -1 31352 -1 -1 28 161 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64376 161 32 993 808 1 515 225 30 30 900 block_FPU auto 23.7 MiB 53.91 6735 58365 23997 33194 1174 62.9 MiB 0.83 0.01 2.985 -1375.04 -2.985 2.985 0.00 0.00723697 0.00689036 0.632448 0.602154 9598 18.6732 2539 4.93969 850 1033 535877 116345 1.6779e+06 201714 2.03108e+06 2256.75 7 48532 406344 -1 2.985 2.985 -1451.27 -2.985 -40.9671 -0.0851 0.85 -1 -1 62.9 MiB 0.26 0.773667 0.737616 62.9 MiB -1 0.73 4 -hard_fpu_arch_timing.xml mm3.v common 3.90 vpr 60.56 MiB 0.04 6828 -1 -1 1 0.04 -1 -1 30604 -1 -1 0 193 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62012 193 32 545 422 1 289 227 21 21 441 io auto 22.0 MiB 1.92 3480 45207 19008 25799 400 60.6 MiB 0.45 0.01 2.985 -824.702 -2.985 2.985 0.00 0.00499164 0.00480908 0.336809 0.324626 4551 15.8021 1192 4.13889 400 400 194592 43581 809148 68766.3 979092. 2220.16 4 24050 197379 -1 2.985 2.985 -811.598 -2.985 -21.7856 -0.0851 0.43 -1 -1 60.6 MiB 0.11 0.404833 0.390442 60.6 MiB -1 0.34 2 -hard_fpu_arch_timing.xml ode.v common 56.49 vpr 64.68 MiB 0.06 8012 -1 -1 1 0.10 -1 -1 34068 -1 -1 135 130 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66228 130 72 1194 1103 1 573 339 19 19 361 io auto 25.2 MiB 53.93 4794 91276 29206 58307 3763 64.7 MiB 0.80 0.01 2.985 -1385.68 -2.985 2.985 0.00 0.0067648 0.00635986 0.538663 0.506206 6805 11.8969 1780 3.11189 1273 1397 405829 81804 653279 378215 795482. 2203.55 9 19802 160939 -1 2.985 2.985 -1384.18 -2.985 -52.6319 -0.0851 0.36 -1 -1 64.7 MiB 0.24 0.695262 0.654681 64.7 MiB -1 0.27 2 -hard_fpu_arch_timing.xml syn2.v common 5.41 vpr 61.97 MiB 0.06 7400 -1 -1 1 0.04 -1 -1 30732 -1 -1 0 161 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63456 161 128 641 490 1 475 293 30 30 900 block_FPU auto 23.2 MiB 1.84 7788 82913 36084 46392 437 62.0 MiB 0.98 0.01 2.985 -1564.05 -2.985 2.985 0.00 0.00836211 0.00808883 0.729693 0.705711 10286 21.7004 2724 5.74684 792 992 508821 108959 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1586.47 -2.985 -16.4184 -0.0851 0.85 -1 -1 62.0 MiB 0.24 0.860584 0.83302 62.0 MiB -1 0.73 4 -hard_fpu_arch_timing.xml syn7.v common 16.79 vpr 112.52 MiB 0.13 9896 -1 -1 1 0.08 -1 -1 32560 -1 -1 0 161 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 115216 161 128 1921 499 1 1728 310 54 54 2916 block_FPU auto 37.0 MiB 2.60 46119 121878 61470 59985 423 112.5 MiB 5.38 0.04 2.985 -8198.94 -2.985 2.985 0.00 0.0373253 0.0362774 4.41941 4.29869 62568 36.2293 15926 9.22177 4142 7176 4439104 909795 6.08571e+06 722046 6.89978e+06 2366.18 7 161598 1383069 -1 2.985 2.985 -8701.55 -2.985 -33.0188 -0.0851 2.79 -1 -1 112.5 MiB 1.75 5.1621 5.02634 112.5 MiB -1 2.86 21 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time num_fpu + hard_fpu_arch_timing.xml bfly.v common 4.85 vpr 63.30 MiB 0.06 7264 -1 -1 1 0.05 -1 -1 30848 -1 -1 0 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 193 64 833 649 1 353 260 24 24 576 io auto 23.2 MiB 3.26 5607 63264 26769 36140 355 63.3 MiB 0.43 0.01 2.985 -1370.5 -2.985 2.985 0.00 0.00322632 0.00304499 0.253266 0.239228 -1 -1 -1 -1 7398 21.0170 1937 5.50284 510 675 229921 59199 1.06129e+06 103149 1.28794e+06 2236.02 4 31350 258969 -1 2.985 2.985 -1377.54 -2.985 -40.8482 -0.0851 0.28 -1 -1 63.3 MiB 0.08 0.301441 0.284814 63.3 MiB -1 0.06 3 + hard_fpu_arch_timing.xml bgm.v common 4.12 vpr 66.32 MiB 0.10 8964 -1 -1 1 0.06 -1 -1 31456 -1 -1 0 257 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67912 257 32 1281 693 1 861 298 38 38 1444 block_FPU auto 27.2 MiB 1.08 16965 98803 43154 54026 1623 66.3 MiB 0.98 0.01 2.985 -3182.68 -2.985 2.985 0.00 0.00568488 0.00537845 0.58516 0.553989 -1 -1 -1 -1 23078 26.8349 5961 6.93140 1605 2215 922235 248459 2.90196e+06 309448 3.35777e+06 2325.33 6 79768 674274 -1 2.985 2.985 -3356.06 -2.985 -44.0704 -0.0851 0.72 -1 -1 66.3 MiB 0.26 0.693055 0.656725 66.3 MiB -1 0.16 9 + hard_fpu_arch_timing.xml dscg.v common 7.96 vpr 62.73 MiB 0.05 7136 -1 -1 1 0.05 -1 -1 31104 -1 -1 0 129 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64240 129 64 769 585 1 438 197 30 30 900 block_FPU auto 22.9 MiB 6.25 6253 46037 19417 26312 308 62.7 MiB 0.40 0.00 2.985 -1429.58 -2.985 2.985 0.00 0.0029514 0.00277598 0.244908 0.230423 -1 -1 -1 -1 8636 19.7620 2241 5.12815 682 799 306937 82874 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1494.72 -2.985 -28.2077 -0.0851 0.44 -1 -1 62.7 MiB 0.10 0.294062 0.276714 62.7 MiB -1 0.10 4 + hard_fpu_arch_timing.xml fir.v common 51.65 vpr 63.12 MiB 0.07 7520 -1 -1 1 0.05 -1 -1 31324 -1 -1 28 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64636 161 32 993 808 1 515 225 30 30 900 block_FPU auto 23.5 MiB 49.72 6935 58365 24143 33008 1214 63.1 MiB 0.46 0.00 2.985 -1371.83 -2.985 2.985 0.00 0.00297047 0.00275784 0.264671 0.246456 -1 -1 -1 -1 9669 18.8113 2558 4.97665 860 1036 384010 103019 1.6779e+06 201714 2.03108e+06 2256.75 6 48532 406344 -1 2.985 2.985 -1450.61 -2.985 -40.9671 -0.0851 0.43 -1 -1 63.1 MiB 0.12 0.322443 0.30033 63.1 MiB -1 0.10 4 + hard_fpu_arch_timing.xml mm3.v common 3.05 vpr 61.30 MiB 0.05 6704 -1 -1 1 0.04 -1 -1 30656 -1 -1 0 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62772 193 32 545 422 1 289 227 21 21 441 io auto 21.6 MiB 1.86 3735 46591 19762 26388 441 61.3 MiB 0.27 0.00 2.985 -824.634 -2.985 2.985 0.00 0.00215884 0.00205042 0.152585 0.145074 -1 -1 -1 -1 4594 15.9514 1212 4.20833 428 428 158702 42530 809148 68766.3 979092. 2220.16 5 24050 197379 -1 2.985 2.985 -813.802 -2.985 -21.7856 -0.0851 0.22 -1 -1 61.3 MiB 0.06 0.187066 0.177642 61.3 MiB -1 0.04 2 + hard_fpu_arch_timing.xml ode.v common 53.80 vpr 65.19 MiB 0.08 7820 -1 -1 1 0.10 -1 -1 33844 -1 -1 141 130 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66756 130 72 1194 1103 1 571 345 19 19 361 io auto 24.7 MiB 52.04 4959 94647 30568 59629 4450 65.2 MiB 0.52 0.01 2.985 -1386.18 -2.985 2.985 0.00 0.00315775 0.00290682 0.254985 0.234605 -1 -1 -1 -1 6658 11.6807 1749 3.06842 1205 1317 282347 70583 653279 391968 795482. 2203.55 10 19802 160939 -1 2.985 2.985 -1383.62 -2.985 -52.7624 -0.0851 0.18 -1 -1 65.2 MiB 0.14 0.337469 0.310228 65.2 MiB -1 0.04 2 + hard_fpu_arch_timing.xml syn2.v common 3.68 vpr 62.52 MiB 0.06 7168 -1 -1 1 0.04 -1 -1 30800 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64016 161 128 641 490 1 475 293 30 30 900 block_FPU auto 23.1 MiB 1.75 8122 82913 36462 46039 412 62.5 MiB 0.55 0.01 2.985 -1569.74 -2.985 2.985 0.00 0.00410324 0.00391013 0.301248 0.287236 -1 -1 -1 -1 10417 21.9768 2760 5.82278 773 969 358629 94838 1.6779e+06 137533 2.03108e+06 2256.75 6 48532 406344 -1 2.985 2.985 -1593.86 -2.985 -16.4581 -0.0851 0.42 -1 -1 62.5 MiB 0.13 0.364652 0.347661 62.5 MiB -1 0.09 4 + hard_fpu_arch_timing.xml syn7.v common 9.24 vpr 112.29 MiB 0.15 9816 -1 -1 1 0.08 -1 -1 32480 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 114988 161 128 1921 499 1 1728 310 54 54 2916 block_FPU auto 36.7 MiB 2.42 46604 125022 60723 63851 448 112.3 MiB 2.55 0.03 2.985 -8233.69 -2.985 2.985 0.00 0.011887 0.0112692 1.44511 1.37115 -1 -1 -1 -1 63797 36.9409 16261 9.41575 4499 7822 3665481 927835 6.08571e+06 722046 6.89978e+06 2366.18 7 161598 1383069 -1 2.985 2.985 -8717.74 -2.985 -33.0585 -0.0851 1.48 -1 -1 112.3 MiB 0.90 1.70466 1.62007 112.3 MiB -1 0.40 21 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt index 940651b7efd..7f926449ba3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt @@ -1,8 +1,8 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - soft_fpu_arch_timing.xml bfly.v common 210.98 vpr 342.67 MiB 4.56 167920 -1 -1 60 101.38 -1 -1 88668 -1 -1 6915 193 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 350896 193 64 24163 24227 1 18280 7172 86 86 7396 clb auto 215.1 MiB 4.38 228607 338.0 MiB 65.70 0.55 37.264 -17207 -37.264 37.264 1.34 0.0392839 0.0347954 4.55714 3.73911 378957 160332 446958 44726667 5530437 1.61728e+07 1.58496e+07 1.77311e+07 2397.39 32 40.8797 40.8797 -18421.3 -40.8797 -52.9827 -0.0851 338.0 MiB 11.74 7.82746 6.47064 338.0 MiB 9.25 - soft_fpu_arch_timing.xml bgm.v common 1155.84 vpr 845.20 MiB 24.67 405584 -1 -1 60 700.25 -1 -1 201356 -1 -1 17932 257 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 865488 257 32 61892 61924 1 47401 18221 136 136 18496 clb auto 524.0 MiB 13.72 615364 823.9 MiB 323.25 2.38 36.8643 -42955.7 -36.8643 36.8643 4.76 0.112517 0.0992696 13.1458 10.8406 999640 415440 1173043 116925879 14611095 4.11556e+07 4.11006e+07 4.47194e+07 2417.79 31 40.3221 40.3221 -46134 -40.3221 -78.8244 -0.0851 823.9 MiB 31.31 22.1047 18.3137 823.9 MiB 25.41 - soft_fpu_arch_timing.xml dscg.v common 196.75 vpr 320.08 MiB 4.33 168696 -1 -1 60 99.00 -1 -1 88224 -1 -1 6472 129 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 327760 129 64 22456 22520 1 16929 6665 83 83 6889 clb auto 202.3 MiB 4.08 204998 312.4 MiB 57.65 0.46 36.2779 -14866.4 -36.2779 36.2779 1.18 0.035477 0.0314625 4.20235 3.44545 345906 140160 401628 40518883 4971695 1.50382e+07 1.48343e+07 1.65016e+07 2395.36 25 39.7359 39.7359 -15878 -39.7359 -46.6351 -0.0851 312.4 MiB 10.09 6.77644 5.59725 312.4 MiB 8.39 - soft_fpu_arch_timing.xml fir.v common 184.82 vpr 324.23 MiB 3.29 149532 -1 -1 60 88.59 -1 -1 84480 -1 -1 6576 161 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 332012 161 32 22750 22782 1 17239 6769 84 84 7056 clb auto 204.3 MiB 4.30 208218 318.1 MiB 56.24 0.50 34.5565 -15161.3 -34.5565 34.5565 1.21 0.0355809 0.0315045 4.10389 3.3815 348929 154532 426175 40951738 5214122 1.54118e+07 1.50726e+07 1.69066e+07 2396.05 29 38.5028 38.5028 -16251.6 -38.5028 -52.5409 -0.0851 318.1 MiB 10.72 7.03873 5.80747 318.1 MiB 8.80 - soft_fpu_arch_timing.xml mm3.v common 108.31 vpr 241.86 MiB 1.44 108788 -1 -1 60 47.09 -1 -1 66008 -1 -1 4729 193 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 247668 193 32 16498 16530 1 12703 4954 71 71 5041 clb auto 151.8 MiB 2.99 145106 237.7 MiB 33.84 0.29 36.43 -10714.8 -36.43 36.43 0.78 0.0274769 0.0218478 2.93832 2.40093 249436 111649 305614 29509234 3745335 1.09126e+07 1.08393e+07 1.20254e+07 2385.52 27 39.0748 39.0748 -11430.1 -39.0748 -29.8922 -0.0851 237.7 MiB 7.49 4.92141 4.05414 237.7 MiB 6.12 - soft_fpu_arch_timing.xml ode.v common 83.78 vpr 206.61 MiB 1.49 110724 -1 -1 60 34.93 -1 -1 64700 -1 -1 4046 130 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 211564 130 72 14280 14352 1 10655 4248 66 66 4356 clb auto 132.0 MiB 2.53 126661 203.3 MiB 25.42 0.23 33.6749 -11373.8 -33.6749 33.6749 0.63 0.0217049 0.0192436 2.43891 2.00506 210198 84432 240099 23319963 2968136 9.38847e+06 9.27387e+06 1.03689e+07 2380.36 27 37.9042 37.9042 -12186.3 -37.9042 -62.8382 -0.0851 203.3 MiB 6.05 4.10709 3.41493 203.3 MiB 5.21 - soft_fpu_arch_timing.xml syn2.v common 241.70 vpr 358.75 MiB 4.26 187176 -1 -1 59 121.03 -1 -1 93136 -1 -1 7281 161 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 367364 161 128 25307 25435 1 19423 7570 88 88 7744 clb auto 224.9 MiB 4.77 234396 352.9 MiB 73.31 0.60 34.8871 -19280.1 -34.8871 34.8871 1.39 0.0405268 0.0357603 4.95119 4.03621 394777 190635 523094 51317356 6505901 1.69521e+07 1.66885e+07 1.85753e+07 2398.67 40 39.0062 39.0062 -20597.8 -39.0062 -37.8125 -0.0851 352.9 MiB 14.07 9.11454 7.49626 352.9 MiB 9.46 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + soft_fpu_arch_timing.xml bfly.v common 218.61 vpr 359.48 MiB 4.91 167836 -1 -1 59 101.39 -1 -1 87824 -1 -1 7340 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 368112 193 64 24210 24274 1 17856 7597 88 88 7744 clb auto 175.2 MiB 7.13 225319 7621897 3212176 4390908 18813 359.5 MiB 72.98 0.60 42.8236 -19565.7 -42.8236 42.8236 0.01 0.0573859 0.0512591 6.89379 5.84877 -1 -1 -1 -1 368191 20.6235 92948 5.20630 130349 394015 30949248 4051469 1.69521e+07 1.68237e+07 1.85753e+07 2398.67 25 418068 3685924 -1 39.6673 39.6673 -18140.5 -39.6673 -54.7919 -0.0851 3.95 -1 -1 359.5 MiB 11.14 10.3565 8.75089 359.5 MiB -1 1.01 + soft_fpu_arch_timing.xml bgm.v common 1037.62 vpr 914.45 MiB 26.28 405280 -1 -1 60 660.49 -1 -1 203444 -1 -1 18904 257 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 936396 257 32 61976 62008 1 46325 19193 140 140 19600 clb auto 419.4 MiB 22.97 596630 25961245 10613132 15303353 44760 914.4 MiB 244.51 2.09 44.1177 -49389.4 -44.1177 44.1177 0.02 0.135011 0.11835 15.2682 12.6503 -1 -1 -1 -1 964345 20.8183 242567 5.23654 339210 1013781 79857050 10583069 4.36493e+07 4.33284e+07 4.74065e+07 2418.70 31 1058292 9395004 -1 41.0998 41.0998 -45704.6 -41.0998 -98.6648 -0.0851 10.18 -1 -1 914.4 MiB 29.50 25.1448 20.7983 914.4 MiB -1 2.72 + soft_fpu_arch_timing.xml dscg.v common 210.26 vpr 342.20 MiB 4.32 168364 -1 -1 60 101.02 -1 -1 87488 -1 -1 6907 129 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 350408 129 64 22611 22675 1 16729 7100 86 86 7396 clb auto 165.7 MiB 6.79 220446 7100940 2996754 4090499 13687 342.2 MiB 66.64 0.56 43.5901 -17476.1 -43.5901 43.5901 0.01 0.0532765 0.0476953 6.30841 5.34291 -1 -1 -1 -1 358090 21.4092 90377 5.40338 124278 375194 30762916 3990281 1.61728e+07 1.58313e+07 1.77311e+07 2397.39 24 399276 3518724 -1 40.7277 40.7277 -16249.7 -40.7277 -52.6715 -0.0851 3.85 -1 -1 342.2 MiB 10.53 9.49355 8.00671 342.2 MiB -1 0.96 + soft_fpu_arch_timing.xml fir.v common 196.96 vpr 343.11 MiB 3.59 149312 -1 -1 59 90.17 -1 -1 83512 -1 -1 6922 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 351344 161 32 22819 22851 1 16866 7115 86 86 7396 clb auto 166.8 MiB 7.04 199474 6915717 2912308 3989791 13618 343.1 MiB 64.14 0.58 40.5059 -17267.1 -40.5059 40.5059 0.01 0.0584 0.048947 6.37642 5.38999 -1 -1 -1 -1 337722 20.0274 85356 5.06173 145553 416282 30884732 4213664 1.61728e+07 1.58657e+07 1.77311e+07 2397.39 32 399276 3518724 -1 37.6419 37.6419 -16015.1 -37.6419 -59.9389 -0.0851 3.71 -1 -1 343.1 MiB 11.94 10.2688 8.65711 343.1 MiB -1 1.07 + soft_fpu_arch_timing.xml mm3.v common 118.95 vpr 275.90 MiB 2.45 108596 -1 -1 59 45.41 -1 -1 58472 -1 -1 5066 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 282524 193 32 16754 16786 1 12491 5291 74 74 5476 clb auto 125.9 MiB 4.96 146469 4475536 1818353 2641694 15489 275.9 MiB 42.98 0.37 41.7388 -12064.6 -41.7388 41.7388 0.00 0.0413345 0.0348399 4.58602 3.90866 -1 -1 -1 -1 245866 19.6882 62306 4.98927 109264 305433 22333496 3068702 1.18822e+07 1.16117e+07 1.30782e+07 2388.28 34 295596 2597004 -1 39.2533 39.2533 -11158.6 -39.2533 -32.4114 -0.0851 2.73 -1 -1 275.9 MiB 8.90 7.59926 6.44593 275.9 MiB -1 0.74 + soft_fpu_arch_timing.xml ode.v common 93.35 vpr 240.33 MiB 2.44 110172 -1 -1 59 33.13 -1 -1 65808 -1 -1 4287 130 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 246100 130 72 14367 14439 1 10374 4489 68 68 4624 clb auto 109.3 MiB 4.08 127157 3557929 1403830 2141831 12268 240.3 MiB 33.73 0.32 40.5533 -13292.3 -40.5533 40.5533 0.00 0.0389352 0.033177 4.01164 3.41586 -1 -1 -1 -1 208721 20.1274 52866 5.09797 78139 230635 17685168 2400784 9.98439e+06 9.82624e+06 1.10168e+07 2382.52 26 249588 2188524 -1 36.7396 36.7396 -12330.1 -36.7396 -66.7867 -0.0851 2.36 -1 -1 240.3 MiB 6.75 6.16378 5.23035 240.3 MiB -1 0.60 + soft_fpu_arch_timing.xml syn2.v common 242.74 vpr 375.87 MiB 4.96 186956 -1 -1 59 118.30 -1 -1 91564 -1 -1 7728 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 384888 161 128 25405 25533 1 18921 8017 90 90 8100 clb auto 183.0 MiB 7.71 234549 8028217 3391444 4616392 20381 375.9 MiB 75.43 0.64 42.3604 -22270.1 -42.3604 42.3604 0.01 0.0617653 0.0552171 6.77016 5.75861 -1 -1 -1 -1 385300 20.3658 97359 5.14610 136904 413779 32546376 4303699 1.77497e+07 1.7713e+07 1.94391e+07 2399.89 32 437292 3857004 -1 39.1789 39.1789 -20606.8 -39.1789 -41.0113 -0.0851 4.35 -1 -1 375.9 MiB 12.57 11.1492 9.4112 375.9 MiB -1 1.08 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt index 239e48d4b20..2054d1011a1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt @@ -1,24 +1,24 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time -stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 311.8 274 967 36 59 0 2 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1735732 22 252 53001 29054 7 24654 1338 89 66 5874 DSP auto 23.51 252822 67.35 0.34 7.26641 -38060.9 -6.26641 2.79561 72.76 0.0922902 0.0742036 19.4784 15.1106 354720 83977 171255 284760839 58437920 0 0 108076000 18399.1 50 7.93667 2.94925 -43306.7 -6.93667 0 0 48.18 30.2955 24.559 65.43 -stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 215.82 36 1583 10 10 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1495008 3 33 48977 39238 1 25960 1639 54 40 2160 LAB auto 60.22 275660 73.3 0.48 76.888 -77679.7 -75.888 76.888 8.1 0.0956007 0.0692678 14.5078 10.6502 370341 90509 238008 217472654 23545267 0 0 39646500 18354.9 28 71.6492 71.6492 -105914 -70.6492 0 0 28.14 21.4905 16.5041 21.42 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2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1755572 227 309 49176 40422 1 28183 2519 85 63 5355 io auto 77.01 312290 91.24 0.69 195.971 -119913 -194.971 195.971 50.83 0.0991588 0.084565 16.0983 11.5643 406195 106821 335442 213233166 16541048 0 0 98440800 18383 22 188.774 188.774 -136523 -187.774 0 0 25.35 22.7627 17.0347 58.18 -stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 247.43 36 1332 8 149 2 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1629816 3 33 52402 39411 1 28117 1527 73 54 3942 M9K auto 61.3 324276 56.9 0.43 16.9115 -306564 -15.9115 16.9115 21.92 0.115668 0.0811981 14.2927 9.97478 446671 101291 248928 219409565 29355499 0 0 72633900 18425.6 49 17.5096 17.5096 -329353 -16.5096 0 0 36.21 25.5848 19.3127 40 -stratixiv_arch.timing.xml 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VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1076940 18 17 2291 2142 1 1504 119 16 12 192 LAB M9K auto 4.08 10271 0.96 0.01 4.965 -3328.06 -3.965 3.70554 0.09 0.00544208 0.00414461 0.470524 0.35424 14141 4076 9559 7859416 739818 0 0 3350780 17452 20 5.1517 3.94454 -3676.27 -4.1517 0 0 0.88 0.737841 0.591727 0.41 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 240.41 vpr 1.80 GiB 274 1048 36 59 0 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1886012 22 252 53001 29054 7 22984 1419 89 66 5874 DSP auto 1200.1 MiB 62.75 248316 1021579 298715 629192 93672 1841.8 MiB 68.63 0.51 7.79847 -44076.4 -6.79847 3.16357 0.04 0.165964 0.147061 22.0804 19.3916 348037 15.1637 76678 3.34080 64297 133419 118695520 34142571 0 0 1.08074e+08 18398.6 17 1714760 18504579 -1 8.25872 3.11653 -42832.7 -7.25872 0 0 39.08 -1 -1 1841.8 MiB 30.91 29.1651 25.7894 1841.8 MiB -1 9.35 + stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 221.39 vpr 1.47 GiB 36 1585 10 10 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 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x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1847692 131 314 57881 45152 1 32833 2672 73 54 3942 io auto 1361.0 MiB 91.84 318946 2041412 717468 1272847 51097 1720.0 MiB 112.21 1.13 221.943 -77080.5 -220.943 221.943 0.03 0.22642 0.192763 26.2516 22.5036 431464 13.1709 103995 3.17455 107179 331669 90059672 17820477 0 0 7.26311e+07 18424.9 19 1148308 12423798 -1 191.341 191.341 -83524.8 -190.341 0 0 25.61 -1 -1 1725.7 MiB 33.11 36.9562 31.8075 1720.0 MiB -1 6.07 + stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 56.10 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1212332 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1061.2 MiB 12.53 72155 253216 50624 190930 11662 1175.4 MiB 10.11 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24.86 21.4146 18.4508 2972.2 MiB -1 30.90 + stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 287.28 vpr 3.37 GiB 1107 725 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3531216 403 704 15490 16194 1 8534 1832 167 124 20708 io auto 1059.1 MiB 60.75 187193 1324022 523278 764997 35747 3448.5 MiB 22.39 0.20 12.7682 -23323.6 -11.7682 6.27217 0.13 0.0592033 0.0490591 7.25586 6.09591 231524 27.1328 38817 4.54905 24809 96129 21440863 3812157 0 0 3.84009e+08 18544.0 14 5987112 65598998 -1 12.9996 6.14541 -26165.8 -11.9996 0 0 128.07 -1 -1 3448.5 MiB 8.23 9.74816 8.27075 3448.5 MiB -1 40.93 + stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 104.00 vpr 1.15 GiB 35 739 0 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1206076 18 17 16969 16357 1 6288 780 39 29 1131 LAB auto 1055.9 MiB 57.16 84377 244832 62116 178083 4633 1170.5 MiB 9.34 0.14 7.65805 -46422.6 -6.65805 7.65805 0.01 0.0407227 0.0346923 3.31901 2.66458 119256 18.9777 28323 4.50716 18857 88786 20657004 3728094 0 0 2.05929e+07 18207.7 16 331560 3499109 -1 7.35046 7.35046 -45160 -6.35046 0 0 8.61 -1 -1 1170.5 MiB 7.38 5.40776 4.46635 1170.5 MiB -1 1.72 + stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 25.34 vpr 990.99 MiB 35 78 0 8 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1014772 18 17 2291 2142 1 1448 121 16 12 192 LAB M9K auto 952.6 MiB 5.77 10189 9390 1103 7334 953 991.0 MiB 0.58 0.01 5.3129 -4153.14 -4.3129 4.5918 0.00 0.00761951 0.00626889 0.283964 0.242647 14035 9.71280 3656 2.53010 3331 8155 2407464 497474 0 0 3.34790e+06 17437.0 10 54372 558374 -1 5.45077 4.46245 -3957.23 -4.45077 0 0 1.88 -1 -1 991.0 MiB 0.85 0.560139 0.494736 991.0 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt index afdc3a7228c..cd660523188 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt @@ -1,23 +1,23 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time -stratixiv_arch.timing.xml gsm_switch_stratixiv_arch_timing.blif common 3434.92 136 21492 0 1848 0 1 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 9760656 100 36 504627 490068 5 200916 23477 255 189 48195 M9K auto 700.76 -1 1504.23 11.74 8.0573 -1.40572e+06 -8.0 5.6189 177.19 1.11051 0.713981 193.057 125.871 5385844 441201 1322987 933414169 132816309 0 0 8.91222e+08 18492.0 12 9.0 6.19052 -1.94741e+06 -8.20679 0 0 180.15 240.444 164.718 597.95 -stratixiv_arch.timing.xml mes_noc_stratixiv_arch_timing.blif common 5178.68 5 23760 0 800 0 8 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 9098808 3 2 577696 547568 17 345674 24573 193 143 27599 LAB auto 1364.30 -1 2826.61 26.29 11.27 -2.97906e+06 -10.27 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Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5971932 264 588 355537 274786 1 218574 15265 150 111 16650 LAB auto 395.29 -1 2053.18 13.33 866.716 -868475 -865.716 866.716 59.74 0.852057 0.609981 129.74 93.1704 3069575 1205817 3821898 2625594594 200491408 0 0 3.08278e+08 18515.2 43 857.427 857.427 -1.06208e+06 -856.427 0 0 316.47 210.711 159.272 198.99 -stratixiv_arch.timing.xml sparcT2_core_stratixiv_arch_timing.blif common 3101.89 451 14725 0 260 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5492144 239 212 302755 300220 1 184812 15436 153 113 17289 LAB auto 720.50 -1 1616.14 9.31 10.5604 -686489 -9.56037 10.5604 74.77 0.872497 0.578117 133.503 89.1183 4841206 557658 2081616 1599598820 153094223 0 0 3.20293e+08 18525.8 65 10.8439 10.8439 -962235 -9.84391 0 0 295.90 247.633 179.457 246.21 -stratixiv_arch.timing.xml cholesky_bdti_stratixiv_arch_timing.blif common 2191.28 162 9680 132 600 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5522328 94 68 331744 255478 1 156536 10574 169 125 21125 DSP auto 343.39 -1 889.63 8.09 8.69851 -566131 -7.69851 8.69851 109.08 1.20758 0.935206 125.961 91.4 2616338 369944 775061 1257487865 245527477 0 0 3.91827e+08 18548.0 18 9.26921 9.26921 -849140 -8.26921 0 0 268.77 166.745 126.095 403.77 -stratixiv_arch.timing.xml minres_stratixiv_arch_timing.blif common 2432.68 229 7818 78 1459 0 1 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 6819488 129 100 316623 257480 3 183470 9585 225 167 37575 M9K auto 381.42 -1 827.15 4.18 7.64836 -339381 -6.64836 4.9105 204.80 0.749549 0.556493 143.207 105.834 2913341 385664 736714 785197968 116848060 0 0 6.95909e+08 18520.5 15 8.94983 6.16821 -534628 -7.94983 0 0 140.68 181.401 138.116 657.28 -stratixiv_arch.timing.xml stap_qrd_stratixiv_arch_timing.blif common 2706.95 150 15899 75 553 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 4970724 68 82 284051 234177 1 144423 16677 158 117 18486 LAB auto 315.03 -1 1579.67 9.66 6.97142 -374581 -5.97142 6.97142 129.35 0.569765 0.447079 154.643 112.186 2649637 299124 721610 828065173 126669656 0 0 3.42752e+08 18541.2 16 7.53291 7.53291 -591536 -6.53291 0 0 196.94 202.379 151.111 327.94 -stratixiv_arch.timing.xml openCV_stratixiv_arch_timing.blif common 2406.79 208 7145 213 785 40 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5944316 106 102 279132 212552 1 168784 8391 209 155 32395 DSP auto 412.15 -1 692.21 4.57 10.0969 -598047 -9.09688 10.0969 169.15 0.727472 0.55054 116.775 85.9459 3370536 460982 1021226 1164410289 196307724 0 0 6.00287e+08 18530.2 43 10.8759 10.8759 -859659 -9.87586 0 0 300.88 195.6 151.617 643.04 -stratixiv_arch.timing.xml bitonic_mesh_stratixiv_arch_timing.blif common 3396.68 119 7239 85 1664 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 6841728 87 32 233978 190746 1 146198 9107 242 179 43318 M9K auto 559.97 -1 1127.28 6.90 12.1144 -1.51589e+06 -11.1144 12.1144 221.34 1.21887 0.860698 175.663 128.302 4588292 456078 1491126 1548811766 242407085 0 0 8.01751e+08 18508.5 18 12.7209 12.7209 -1.86107e+06 -11.7209 0 0 304.05 240.372 183.004 932.96 -stratixiv_arch.timing.xml segmentation_stratixiv_arch_timing.blif common 1763.17 441 6937 15 481 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 3718544 72 369 178312 137832 1 108345 7874 136 101 13736 M9K auto 185.42 -1 1080.57 6.58 851.19 -389269 -850.19 851.19 54.10 0.501823 0.365842 89.6848 65.6521 1630334 475504 1473018 1179152997 94653229 0 0 2.53781e+08 18475.6 24 837.727 837.727 -515162 -836.727 0 0 172.25 126.618 95.8909 165.68 -stratixiv_arch.timing.xml SLAM_spheric_stratixiv_arch_timing.blif common 884.93 479 5366 37 0 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 2821524 323 156 140638 111354 1 78004 5882 95 70 6650 LAB auto 212.42 -1 396.74 2.66 78.3162 -375071 -77.3162 78.3162 29.78 0.331472 0.280128 50.9109 37.3753 1612271 249303 845612 794012785 90253580 0 0 1.22432e+08 18410.9 20 77.2015 77.2015 -414731 -76.2015 0 0 107.22 71.3949 54.5921 73.43 -stratixiv_arch.timing.xml des90_stratixiv_arch_timing.blif common 1446.48 117 4233 44 860 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 4013740 85 32 138853 110549 1 87969 5254 171 127 21717 M9K auto 282.94 -1 444.78 4.09 11.4477 -770173 -10.4477 11.4477 81.79 0.834987 0.625928 85.2758 63.1207 2230768 283309 861480 732978149 114988063 0 0 4.02762e+08 18545.9 57 12.2596 12.2596 -928196 -11.2596 0 0 239.80 184.596 144.573 274.03 -stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 582.49 77 3123 89 136 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 2813800 42 35 119888 86875 1 51283 3425 129 96 12384 DSP auto 85.55 -1 117.60 0.94 7.88637 -71260.7 -6.88637 5.1277 63.82 0.276687 0.214216 36.7265 27.9182 749667 110099 187821 250313976 47472949 0 0 2.28642e+08 18462.7 29 8.05602 5.58124 -112257 -7.05602 0 0 57.52 54.3082 43.3457 181.77 -stratixiv_arch.timing.xml sparcT1_core_stratixiv_arch_timing.blif common 791.54 310 4000 1 128 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 2316624 173 137 92814 91975 1 60944 4439 82 61 5002 LAB auto 250.21 -1 292.72 2.97 7.69498 -527081 -6.69498 7.69498 18.58 0.484786 0.335188 47.2008 32.1521 1293421 213067 742140 562420350 57380434 0 0 9.19900e+07 18390.6 34 8.28235 8.28235 -655221 -7.28235 0 0 115.19 81.8934 60.2717 57.04 -stratixiv_arch.timing.xml stereo_vision_stratixiv_arch_timing.blif common 563.33 506 3246 76 113 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 2744440 172 334 127090 94090 3 61732 3941 129 96 12384 DSP auto 81.66 -1 117.95 0.82 7.16483 -51326.5 -6.16483 3.19482 60.85 0.192659 0.134604 27.0351 19.0385 580833 129881 199489 173990883 19816534 0 0 2.28642e+08 18462.7 24 7.39025 3.26548 -71146 -6.39025 0 0 30.31 39.7283 29.6661 189.20 -stratixiv_arch.timing.xml cholesky_mc_stratixiv_arch_timing.blif common 822.42 262 4765 59 444 16 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 3139848 111 151 140214 108592 1 66751 5546 125 93 11625 M9K auto 127.78 -1 257.07 1.60 6.64077 -177966 -5.64077 6.64077 58.12 0.325199 0.243045 52.6464 38.4057 1180344 153949 342701 556413254 117858039 0 0 2.14514e+08 18452.8 16 6.97434 6.97434 -288912 -5.97434 0 0 137.35 70.3563 53.4736 154.69 -stratixiv_arch.timing.xml directrf_stratixiv_arch_timing.blif common 13033.91 319 61450 240 2535 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 19989968 62 257 1374456 930989 2 679981 64544 317 235 74495 M9K auto 1100.54 -1 8835.77 82.27 10.0391 -1.7189e+06 -9.03907 8.60202 365.26 2.32644 1.66281 526.865 374.58 12211049 1565796 2766063 3167014806 442243815 0 0 1.38708e+09 18619.7 36 10.5916 9.11279 -2.47963e+06 -9.59162 0 0 683.17 734.274 541.813 1479.59 -stratixiv_arch.timing.xml bitcoin_miner_stratixiv_arch_timing.blif common 12379.71 385 32503 0 1331 0 1 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 14041524 353 32 1446409 1087537 2 848902 34220 225 167 37575 LAB auto 800.01 -1 8905.24 34.75 8.79365 -825548 -7.79365 8.79365 142.25 1.97467 1.46614 404.675 290.131 10667459 2667357 3983335 3475083060 437778344 0 0 6.95909e+08 18520.5 221 13.7216 13.7216 -1.26214e+06 -12.7216 0 0 1592.57 1348.11 1039.94 533.31 -stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 9437.46 373 16571 116 5040 16 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 18756984 178 195 663067 568001 2 413013 22116 430 319 137170 M9K auto 1116.15 -1 3180.91 12.00 22.8182 -3.14594e+06 -21.8182 7.83218 755.18 1.81031 1.31598 435.301 309.645 17977564 1024239 1942686 3346505372 605233804 0 0 2.57820e+09 18795.7 28 23.0087 9.77401 -5.72551e+06 -22.0087 0 0 898.40 569.516 420.296 2890.28 -stratixiv_arch.timing.xml sparcT1_chip2_stratixiv_arch_timing.blif common 9296.08 1891 33629 3 506 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 12985200 815 1076 764693 760412 1423 416439 36029 280 207 57960 io auto 1621.50 -1 5111.77 25.16 15.6661 -3.78262e+06 -14.6661 4.89313 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9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3240872 111 151 140214 108592 1 66275 5543 125 93 11625 M9K auto 1990.1 MiB 150.70 788106 6330929 2486828 3764499 79602 2999.6 MiB 253.72 2.29 6.96286 -206320 -5.96286 6.96286 0.08 0.604795 0.483861 67.9341 55.4074 1136243 17.1454 244932 3.69592 141963 302339 243323807 67066242 0 0 2.14511e+08 18452.6 16 3364308 36745094 -1 7.39694 7.39694 -298154 -6.39694 0 0 72.92 -1 -1 2999.6 MiB 76.78 90.4375 75.2977 2999.6 MiB -1 19.73 + stratixiv_arch.timing.xml directrf_stratixiv_arch_timing.blif common 12532.52 vpr 19.50 GiB 319 61499 240 2535 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 20448160 62 257 1374456 930989 2 664817 64593 317 235 74495 M9K auto 11400.2 MiB 1506.39 10830328 216389546 87578779 128174025 636742 16624.7 MiB 9335.15 60.39 9.32838 -1.81224e+06 -8.32838 8.21814 0.67 3.53075 2.88911 658.938 543.734 11749927 17.6766 2324437 3.49689 1382377 2282905 1372376586 322363776 0 0 1.38707e+09 18619.7 14 21381670 236483135 -1 9.87707 8.61989 -2.31232e+06 -8.87707 0 0 452.96 -1 -1 16912.8 MiB 513.06 803.854 668.88 16624.7 MiB -1 182.00 + stratixiv_arch.timing.xml bitcoin_miner_stratixiv_arch_timing.blif common 11466.83 vpr 14.34 GiB 385 35914 0 1331 0 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 15035956 353 32 1446409 1087537 2 802897 37631 236 175 41300 LAB auto 8407.8 MiB 1414.82 8069197 81976111 30515078 50803021 658012 10893.1 MiB 8936.33 46.36 8.82853 -897986 -7.82853 8.82853 0.36 2.99104 2.55745 469.647 390.463 9365241 11.6644 2162474 2.69335 1742182 2571548 800029867 152528004 0 0 7.64522e+08 18511.4 17 11894042 131060469 -1 10.6871 10.6871 -1.2059e+06 -9.68713 0 0 251.35 -1 -1 12829.2 MiB 343.34 618.45 518.897 10893.1 MiB -1 88.27 + stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 6830.28 vpr 19.49 GiB 373 16678 116 5040 16 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 20438632 178 195 663067 568001 2 406083 22223 430 319 137170 M9K auto 5700.5 MiB 1520.96 15354107 51862695 21830000 29930794 101901 19959.6 MiB 3339.60 16.18 26.6172 -3.23472e+06 -25.6172 8.81163 0.77 2.93237 2.42302 522.353 431.036 16386901 40.3553 3026953 7.45434 917037 1739755 1410990275 326533180 0 0 2.57820e+09 18795.6 12 39390806 435738327 -1 24.6154 10.5061 -5.75347e+06 -23.6154 0 0 796.86 -1 -1 19959.6 MiB 463.24 629.617 524.068 19959.6 MiB -1 347.65 + stratixiv_arch.timing.xml sparcT1_chip2_stratixiv_arch_timing.blif common 8297.71 vpr 12.67 GiB 1891 33747 3 506 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 13287316 815 1076 764693 760412 1423 413569 36147 280 207 57960 io auto 6871.8 MiB 2181.98 6321041 78292272 33005860 44758558 527854 11353.1 MiB 4930.46 30.53 17.7516 -4.16163e+06 -16.7516 4.89119 0.50 2.84274 2.25204 405.671 323.281 7527876 18.5260 1630241 4.01199 988164 3143557 705151553 127852079 0 0 1.07374e+09 18525.6 21 16684552 184042692 -1 17.843 5.02145 -4.80984e+06 -16.843 0 0 348.44 -1 -1 11473.0 MiB 340.62 553.004 447.083 11353.1 MiB -1 132.10 + stratixiv_arch.timing.xml LU_Network_stratixiv_arch_timing.blif common 6343.70 vpr 11.23 GiB 399 31093 112 1175 0 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 11773496 85 185 721554 630079 28 405002 32781 220 163 35860 LAB auto 6475.4 MiB 1009.92 5178404 84458444 33598600 50279421 580423 8859.9 MiB 4446.05 26.77 8.14669 -688925 -7.14669 5.20564 0.30 3.77527 2.96208 508.454 405.77 6249071 15.4486 1362456 3.36819 825418 1759906 637573300 144402801 0 0 6.64232e+08 18522.9 14 10351778 113707977 -1 8.89873 5.39961 -915798 -7.89873 0 0 217.81 -1 -1 10398.6 MiB 257.32 623.547 504.372 8859.9 MiB -1 73.73 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/golden_results.txt index 923229b832d..92b4e95ed1c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/golden_results.txt @@ -1,6 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 26.57 vpr 82.09 MiB -1 -1 4.09 45804 3 0.98 -1 -1 40164 -1 -1 112 236 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84056 236 305 3195 3007 1 1538 660 19 19 361 io auto 44.6 MiB 1.97 12550 82.1 MiB 2.18 0.03 4.23319 -2592.08 -4.23319 4.23319 0.09 0.00734041 0.00664649 0.800573 0.722627 22506 5369 14230 2808527 640885 1.72706e+07 8.96013e+06 2.90560e+06 8048.76 16 4.88723 4.88723 -2997.25 -4.88723 -6.66982 -0.193384 82.1 MiB 1.04 1.20892 1.10479 82.1 MiB 1.24 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 26.32 vpr 82.26 MiB -1 -1 3.75 46008 3 0.93 -1 -1 40016 -1 -1 120 236 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84232 236 305 3195 3007 1 1534 668 19 19 361 io auto 45.3 MiB 2.86 12092 82.3 MiB 2.03 0.03 4.31218 -2553.6 -4.31218 4.31218 0.07 0.00696218 0.00631702 0.765105 0.691642 19341 4478 11708 2097942 457216 1.72706e+07 9.39128e+06 2.71656e+06 7525.11 12 4.99952 4.99952 -3010.14 -4.99952 0 0 82.3 MiB 0.83 1.12422 1.027 82.3 MiB 1.15 - k6_frac_N10_mem32K_40nm.xml raygentop.v common 26.02 vpr 77.67 MiB -1 -1 4.82 49248 8 1.50 -1 -1 41880 -1 -1 116 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 79536 235 305 2594 2755 1 1443 663 19 19 361 io auto 39.9 MiB 2.23 11448 77.7 MiB 1.82 0.03 4.41088 -2430.87 -4.41088 4.41088 0.08 0.00649293 0.00576414 0.647429 0.579732 18768 3833 11059 1989583 427191 1.72706e+07 9.1757e+06 2.71663e+06 7525.28 11 5.29026 5.29026 -2756.74 -5.29026 -8.67533 -0.17036 77.7 MiB 0.75 0.955384 0.866802 77.7 MiB 1.18 - k6_N10_mem32K_40nm.xml raygentop.v common 25.03 vpr 76.39 MiB -1 -1 4.72 48856 8 1.50 -1 -1 41792 -1 -1 165 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 78228 235 305 2594 2755 1 1461 712 19 19 361 io auto 38.7 MiB 0.95 12269 76.4 MiB 1.85 0.03 4.59709 -2576.68 -4.59709 4.59709 0.09 0.00642268 0.00566871 0.591253 0.53058 18465 7376 21416 6225690 1224003 1.72706e+07 1.18165e+07 2.57233e+06 7125.57 19 4.96959 4.96959 -2849.65 -4.96959 -0.0066982 -0.0066982 76.4 MiB 1.84 0.995979 0.901619 76.4 MiB 1.10 - hard_fpu_arch_timing.xml raygentop.v common 389.64 vpr 322.97 MiB -1 -1 36.07 182560 40 111.52 -1 -1 74952 -1 -1 3776 235 -1 -1 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 330724 235 305 20496 20801 1 8995 4316 68 68 4624 clb auto 158.1 MiB 4.44 176765 323.0 MiB 49.61 0.36 22.409 -30564.1 -22.409 22.409 1.35 0.0561504 0.0436831 6.55008 5.20912 249819 53589 173978 17781644 1967620 9.87441e+06 8.65503e+06 1.89440e+07 4096.88 23 25.1849 25.1849 -37219.3 -25.1849 -0.1702 -0.0851 323.0 MiB 8.47 9.92861 8.04481 323.0 MiB 16.99 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 21.07 vpr 83.23 MiB -1 -1 4.77 42300 3 0.69 -1 -1 37768 -1 -1 119 236 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85232 236 305 3199 3011 1 1524 667 19 19 361 io auto 42.1 MiB 2.01 12616 262837 90033 158763 14041 83.2 MiB 2.05 0.03 4.49369 -2806.86 -4.49369 4.49369 0.00 0.00966118 0.00895805 0.835281 0.769463 -1 -1 -1 -1 21210 13.9908 5587 3.68536 5140 14335 1484939 342866 1.72706e+07 9.33739e+06 3.48716e+06 9659.72 17 58198 611635 -1 4.74754 4.74754 -2972.19 -4.74754 -0.452504 -0.0215478 0.56 -1 -1 83.2 MiB 0.75 1.24852 1.15404 83.2 MiB -1 0.11 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 22.29 vpr 83.17 MiB -1 -1 4.81 42876 3 0.69 -1 -1 37760 -1 -1 129 236 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85164 236 305 3199 3011 1 1520 677 19 19 361 io auto 42.5 MiB 2.79 12380 244299 81189 149577 13533 83.2 MiB 1.87 0.03 4.65817 -2859.2 -4.65817 4.65817 0.00 0.00866299 0.00799175 0.759534 0.696955 -1 -1 -1 -1 18640 12.3280 4948 3.27249 4102 10444 795414 174592 1.72706e+07 9.87633e+06 3.27351e+06 9067.88 17 54883 545335 -1 4.90067 4.90067 -2957.57 -4.90067 0 0 0.53 -1 -1 83.2 MiB 0.52 1.13157 1.04213 83.2 MiB -1 0.11 + k6_frac_N10_mem32K_40nm.xml raygentop.v common 21.25 vpr 78.37 MiB -1 -1 5.87 46604 8 0.98 -1 -1 37824 -1 -1 117 235 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80252 235 305 2600 2761 1 1433 664 19 19 361 io auto 37.8 MiB 1.95 11898 272794 88380 167366 17048 78.4 MiB 1.97 0.03 5.27944 -2662.29 -5.27944 5.27944 0.00 0.00791855 0.00732648 0.794863 0.732871 -1 -1 -1 -1 18276 12.8163 4830 3.38710 3901 10985 836374 182612 1.72706e+07 9.2296e+06 3.27351e+06 9067.88 11 53999 544685 -1 5.16248 5.16248 -2765.43 -5.16248 -4.72457 -0.168146 0.53 -1 -1 78.4 MiB 0.41 1.06143 0.98183 78.4 MiB -1 0.10 + k6_N10_mem32K_40nm.xml raygentop.v common 19.60 vpr 77.53 MiB -1 -1 6.09 46284 8 0.99 -1 -1 37804 -1 -1 193 235 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79388 235 305 2600 2761 1 1403 740 19 19 361 io clb auto 36.9 MiB 1.01 12379 261650 87521 161400 12729 77.5 MiB 1.85 0.03 5.29995 -2784.97 -5.29995 5.29995 0.00 0.0080991 0.00750467 0.669483 0.615668 -1 -1 -1 -1 17144 12.2808 4591 3.28868 6555 20515 2226044 437383 1.72706e+07 1.33255e+07 3.09093e+06 8562.13 21 47590 507115 -1 5.08294 5.08294 -2786.98 -5.08294 -12.7904 -0.246958 0.50 -1 -1 77.5 MiB 0.79 1.07204 0.98586 77.5 MiB -1 0.10 + hard_fpu_arch_timing.xml raygentop.v common 237.56 vpr 393.52 MiB -1 -1 40.57 186152 41 66.23 -1 -1 72764 -1 -1 3955 235 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 402960 235 305 20447 20752 1 8685 4495 70 70 4900 clb auto 132.2 MiB 4.43 172483 4046324 1736449 2271923 37952 393.5 MiB 31.14 0.27 27.318 -38433 -27.318 27.318 0.02 0.0410618 0.0358058 4.84871 4.07471 -1 -1 -1 -1 244983 28.2271 61861 7.12766 48213 160239 16322926 1805170 1.04337e+07 9.0653e+06 2.44008e+07 4979.75 20 487536 5108624 -1 25.2535 25.2535 -40276.6 -25.2535 -0.3404 -0.0851 6.81 -1 -1 393.5 MiB 5.85 6.95088 5.84398 393.5 MiB -1 1.57 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/golden_results.txt index dfbbf4d2833..d459ca13114 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - k4_n4_v7_bidir.xml dsip.blif common 68.50 vpr 103.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 390 229 -1 -1 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 106276 229 197 1815 2012 1 1190 816 29 29 841 io auto 29.4 MiB 0.37 11620 103.8 MiB 2.16 0.04 6.8651 -1709.92 -6.8651 6.8651 1.11 0.00477376 0.00418939 0.496235 0.436882 15380 5691 17014 6186367 416954 2.187e+07 1.17e+07 -1 -1 13 8.65812 8.65812 -2235.57 -8.65812 0 0 103.8 MiB 1.40 0.704858 0.627073 103.8 MiB 9.22 - k4_n4_v7_bidir.xml elliptic.blif common 106.33 vpr 146.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 996 131 -1 -1 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 150432 131 114 4855 4969 1 2150 1241 34 34 1156 clb auto 49.8 MiB 0.89 31903 146.9 MiB 4.39 0.05 19.6462 -11430.7 -19.6462 19.6462 1.76 0.0110664 0.00959187 0.986311 0.840225 41276 10265 46782 11439440 713310 3.072e+07 2.988e+07 -1 -1 18 23.458 23.458 -14291.4 -23.458 0 0 146.9 MiB 3.13 1.66205 1.43613 146.9 MiB 13.74 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k4_n4_v7_bidir.xml dsip.blif common 25.73 vpr 128.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 443 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 131904 229 197 1815 2012 1 1190 869 29 29 841 io auto 27.9 MiB 0.38 11808 386354 130262 246701 9391 128.8 MiB 2.12 0.03 8.26026 -2002.89 -8.26026 8.26026 0.00 0.00584398 0.00529802 0.564955 0.515177 -1 -1 -1 -1 14837 12.4786 3857 3.24390 5280 18595 4288015 314127 2.187e+07 1.329e+07 -1 -1 12 141714 3348831 -1 10.3649 10.3649 -2489.23 -10.3649 0 0 1.96 -1 -1 128.8 MiB 0.87 0.747411 0.681765 128.8 MiB -1 0.72 + k4_n4_v7_bidir.xml elliptic.blif common 38.86 vpr 178.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1023 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 182996 131 114 4855 4969 1 2112 1268 34 34 1156 clb auto 44.7 MiB 0.81 31400 563788 196591 359179 8018 178.7 MiB 4.04 0.04 22.2892 -11723.6 -22.2892 22.2892 0.01 0.0103809 0.00927175 1.12003 0.959229 -1 -1 -1 -1 40056 18.9749 10269 4.86452 9570 44105 8008892 526134 3.072e+07 3.069e+07 -1 -1 19 194754 4643496 -1 27.7541 27.7541 -14616.1 -27.7541 0 0 2.77 -1 -1 178.7 MiB 1.77 1.60391 1.38102 178.7 MiB -1 1.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/golden_results.txt index 14bf14c7160..35eb454cdb9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 70.22 vpr 81.37 MiB -1 -1 5.14 48880 13 1.49 -1 -1 41348 -1 -1 256 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 83320 235 305 3025 3186 1 2385 803 26 26 676 mult_36 auto 37.3 MiB 0.66 17792 81.4 MiB 2.66 0.04 4.07341 -1915.66 -4.07341 4.07341 0.18 0.00727701 0.00657869 0.640946 0.566051 26395 7994 25461 5630378 1530085 3.88769e+06 1.79395e+06 7.17610e+06 10615.5 16 4.6849 4.6849 -2313.21 -4.6849 -34.8532 -0.36083 81.4 MiB 1.99 1.02377 0.915351 81.4 MiB 9.69 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 27.97 vpr 90.66 MiB -1 -1 6.04 46344 13 0.96 -1 -1 37412 -1 -1 258 235 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 92832 235 305 3050 3211 1 2409 805 26 26 676 mult_36 auto 35.0 MiB 0.56 18548 318960 106153 197804 15003 90.7 MiB 2.80 0.04 4.63435 -2030.57 -4.63435 4.63435 0.00 0.00954579 0.00885942 0.841339 0.769886 -1 -1 -1 -1 27327 11.3768 12604 5.24729 7556 24511 3145050 770465 3.88769e+06 1.80175e+06 7.17610e+06 10615.5 17 154908 1423382 -1 4.95816 4.95816 -2400.04 -4.95816 -4.91839 -0.302506 2.27 -1 -1 90.7 MiB 1.13 1.2245 1.12379 90.7 MiB -1 0.68 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/golden_results.txt index 5261852db4a..b062cee3d4b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 18.21 vpr 75.18 MiB -1 -1 4.72 49096 13 1.40 -1 -1 41408 -1 -1 256 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 76984 235 305 3025 3186 1 2385 803 26 26 676 mult_36 auto 37.5 MiB 0.60 17960 75.2 MiB 2.54 0.04 4.07552 -1959 -4.07552 4.07552 0.15 0.00692304 0.00628985 0.617946 0.554056 27960 9568 30531 5163874 1503608 3.88769e+06 1.79395e+06 3.89335e+06 5759.39 21 4.86688 4.86688 -2303.87 -4.86688 -33.7771 -0.30051 75.2 MiB 1.82 1.04903 0.946401 75.2 MiB 4.50 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 13.99 vpr 76.51 MiB -1 -1 6.07 46336 13 0.97 -1 -1 37404 -1 -1 258 235 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78348 235 305 3050 3211 1 2409 805 26 26 676 mult_36 auto 35.1 MiB 0.56 18006 296502 98971 182176 15355 76.5 MiB 2.50 0.04 4.59638 -1990.69 -4.59638 4.59638 0.00 0.00877395 0.00813036 0.734286 0.67238 -1 -1 -1 -1 27613 11.4958 13095 5.45171 8944 28960 2940446 834435 3.88769e+06 1.80175e+06 3.89335e+06 5759.39 15 97004 733416 -1 4.97823 4.97823 -2391.62 -4.97823 -8.61767 -0.284072 1.15 -1 -1 76.5 MiB 0.93 1.05837 0.970896 76.5 MiB -1 0.34 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/golden_results.txt index 067a8cc5230..e2eda83b3b7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 1504.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 2859008 42 35 119888 86875 1 51143 3418 129 96 12384 DSP auto 85.58 583323 119.39 0.71 7.89477 -209772 -7.89477 7.89477 208.83 0.200591 0.17182 32.4665 25.7145 744976 -1 -1 -1 -1 0 0 2.28642e+08 18462.7 33 8.25962 8.25962 -264487 -8.25962 0 0 57.37 50.95 41.9616 169.27 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 966.64 vpr 2.85 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2990436 42 35 119888 86875 1 50848 3434 129 96 12384 DSP auto 1744.6 MiB 111.96 593082 3188765 1210302 1953134 25329 2920.3 MiB 129.15 1.03 7.82707 -223897 -7.82707 7.82707 0.07 0.354575 0.31728 46.7861 40.8662 -1 -1 -1 -1 760648 14.9737 161961 3.18827 105791 178983 117012215 31658104 0 0 2.28639e+08 18462.4 15 3593250 39165143 -1 8.06159 8.06159 -257707 -8.06159 0 0 77.93 -1 -1 2920.3 MiB 38.69 62.4048 54.9606 2920.3 MiB -1 22.61 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt index c1dc0afb50f..ad32242d902 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt @@ -1,41 +1,41 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_n4_v7_bidir.xml alu4.blif common 14.52 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 477 14 -1 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68932 14 8 1536 1544 0 1088 499 24 24 576 clb auto 27.1 MiB 0.35 13713 125113 37636 85702 1775 67.3 MiB 0.82 0.01 14.0421 -101.788 -14.0421 nan 0.88 0.00340676 0.00297335 0.220724 0.194701 28 19990 27 1.452e+07 1.431e+07 -1 -1 8.80 1.43324 1.22449 21174 279108 -1 19228 18 7062 27087 2139856 196285 17.1451 nan -119.753 -17.1451 0 0 -1 -1 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28.1 MiB 0.20 9992 137732 37830 95961 3941 67.7 MiB 0.64 0.01 13.4033 -2671.54 -13.4033 13.4033 0.70 0.00195077 0.00171362 0.173386 0.151149 24 14332 21 1.323e+07 1.245e+07 -1 -1 6.54 1.33161 1.13731 18402 227975 -1 13634 22 6342 21307 1309693 133684 15.9009 15.9009 -3236.59 -15.9009 0 0 -1 -1 0.30 0.48 0.13 -1 -1 0.30 0.194956 0.169766 -k4_n4_v7_bidir.xml dsip.blif common 17.59 vpr 67.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 390 229 -1 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69036 229 197 1815 2012 1 1190 816 29 29 841 io auto 27.7 MiB 0.36 11545 347617 108721 229249 9647 67.4 MiB 1.72 0.02 7.21771 -1868.83 -7.21771 7.21771 1.36 0.00518736 0.00474124 0.503797 0.459535 18 18641 50 2.187e+07 1.17e+07 -1 -1 9.53 1.95931 1.76098 25794 279159 -1 15915 19 6571 20190 1355499 141050 8.71824 8.71824 -2334.27 -8.71824 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2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 120424 10 10 4608 4618 0 3617 1527 41 41 1681 clb auto 48.8 MiB 1.07 44970 713436 251975 459721 1740 117.6 MiB 5.30 0.06 23.5124 -229.462 -23.5124 nan 3.51 0.00978634 0.00856467 0.959665 0.808442 28 68638 30 4.563e+07 4.521e+07 -1 -1 48.39 4.23166 3.50982 61362 838935 -1 63940 21 25222 100656 7392341 708511 28.5457 nan -270.488 -28.5457 0 0 -1 -1 1.24 2.14 0.48 -1 -1 1.24 0.496082 0.429934 -k4_n4_v7_bidir.xml ex5p.blif common 10.49 vpr 63.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 342 8 -1 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65300 8 63 1072 1135 0 906 413 21 21 441 clb auto 24.4 MiB 0.27 11449 84948 23521 59664 1763 63.8 MiB 0.57 0.01 12.8622 -575.489 -12.8622 nan 0.65 0.00267296 0.002391 0.164293 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ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time 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x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71692 38 3 1916 1919 0 1483 667 28 28 784 clb auto 29.5 MiB 0.29 19984 195838 60682 130920 4236 70.0 MiB 1.45 0.02 17.0385 -49.2963 -17.0385 nan 0.49 0.00449691 0.00389108 0.328393 0.287877 -1 -1 -1 -1 28 30181 48 2.028e+07 1.878e+07 -1 -1 17.00 1.80013 1.5249 28758 383844 -1 28376 15 9150 33071 2590424 247096 20.7907 nan -60.2269 -20.7907 0 0 -1 -1 0.07 0.68 0.22 -1 -1 0.07 0.170018 0.15064 + k4_n4_v7_bidir.xml apex4.blif common 9.32 vpr 64.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 434 9 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66272 9 19 1271 1290 0 989 462 23 23 529 clb auto 25.3 MiB 0.38 13918 105777 29780 74317 1680 64.7 MiB 0.80 0.01 13.9047 -226.083 -13.9047 nan 0.32 0.00309616 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75676 256 245 1847 2092 0 1412 985 34 34 1156 io auto 28.8 MiB 0.47 16647 378208 121053 242540 14615 73.9 MiB 1.97 0.03 12.9369 -2198.65 -12.9369 nan 0.75 0.00633861 0.00581167 0.523122 0.480492 -1 -1 -1 -1 18 23173 26 3.072e+07 1.452e+07 -1 -1 5.70 2.0657 1.87447 35364 387024 -1 21989 19 8778 32560 2141080 246703 15.131 nan -2729.2 -15.131 0 0 -1 -1 0.07 0.71 0.23 -1 -1 0.07 0.271271 0.249347 + k4_n4_v7_bidir.xml diffeq.blif common 7.63 vpr 67.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69484 64 39 1935 1974 1 1077 542 23 23 529 clb auto 28.0 MiB 0.35 10284 139709 36550 99088 4071 67.9 MiB 1.01 0.02 13.3471 -2484.01 -13.3471 13.3471 0.32 0.00419252 0.00369096 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-1 -1 -1 -1 -1 -1 -1 -1 -1 1094 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 123920 20 116 4445 4561 1 2290 1230 36 36 1296 clb auto 44.1 MiB 0.99 38255 580886 202911 367450 10525 120.6 MiB 4.25 0.05 29.223 -16576.9 -29.223 29.223 1.43 0.0105708 0.00897893 0.999254 0.851085 -1 -1 -1 -1 26 40614 39 3.468e+07 3.282e+07 -1 -1 79.50 4.26322 3.57492 104992 763300 -1 37284 18 13336 60167 5347576 900846 28.6821 28.6821 -16996 -28.6821 0 0 -1 -1 0.20 1.82 0.58 -1 -1 0.20 0.421201 0.366517 + k4_n4_v7_l1_bidir.xml misex3.blif common 17.56 vpr 65.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 450 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67284 14 14 1411 1425 0 1056 478 24 24 576 clb auto 26.1 MiB 0.40 13799 121898 36530 83432 1936 65.7 MiB 0.91 0.01 18.1166 -222.755 -18.1166 nan 0.58 0.00323875 0.00286176 0.229781 0.204181 -1 -1 -1 -1 21 15917 38 1.452e+07 1.35e+07 -1 -1 12.60 1.01596 0.869596 39160 271852 -1 13861 19 6925 26912 1892268 324238 17.8372 nan -222.89 -17.8372 0 0 -1 -1 0.06 0.66 0.21 -1 -1 0.06 0.14886 0.130215 + k4_n4_v7_l1_bidir.xml pdc.blif common 418.57 vpr 161.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1606 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 164932 16 40 4591 4631 0 3616 1662 43 43 1849 clb auto 50.4 MiB 1.48 71388 995502 386267 603819 5416 155.6 MiB 7.56 0.07 36.0567 -1232.66 -36.0567 nan 2.15 0.0118231 0.00974149 1.23901 1.02884 -1 -1 -1 -1 34 83956 48 5.043e+07 4.818e+07 -1 -1 394.83 5.32434 4.35296 185730 1416087 -1 74292 16 24740 103095 11970321 1866116 34.9964 nan -1210.26 -34.9964 0 0 -1 -1 0.37 3.72 1.11 -1 -1 0.37 0.501094 0.427155 + k4_n4_v7_l1_bidir.xml s298.blif common 14.97 vpr 70.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 573 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71716 4 6 1942 1948 1 1167 583 26 26 676 clb auto 29.8 MiB 0.37 13721 168529 51547 115716 1266 70.0 MiB 1.27 0.02 26.8992 -206.444 -26.8992 26.8992 0.69 0.00496419 0.00432315 0.361202 0.317423 -1 -1 -1 -1 17 15103 41 1.728e+07 1.719e+07 -1 -1 8.88 1.36971 1.16775 39072 254696 -1 13708 17 7890 40380 2928639 390491 25.7904 25.7904 -205.684 -25.7904 0 0 -1 -1 0.06 0.94 0.21 -1 -1 0.06 0.209805 0.184411 + k4_n4_v7_l1_bidir.xml s38417.blif common 61.66 vpr 189.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1852 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 193636 29 106 7534 7640 1 4623 1987 46 46 2116 clb auto 61.8 MiB 1.63 45682 1150699 423694 711314 15691 189.1 MiB 8.82 0.10 24.016 -14000.6 -24.016 24.016 2.46 0.0169007 0.0139461 1.64128 1.36389 -1 -1 -1 -1 16 41981 27 5.808e+07 5.556e+07 -1 -1 37.78 5.55941 4.54523 118272 756192 -1 39731 15 23886 81328 4350389 861432 23.6137 23.6137 -14728 -23.6137 0 0 -1 -1 0.20 2.01 0.59 -1 -1 0.20 0.647233 0.553971 + k4_n4_v7_l1_bidir.xml s38584.1.blif common 67.22 vpr 183.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1787 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 187696 38 304 7475 7779 1 4320 2129 45 45 2025 clb auto 61.8 MiB 1.45 43799 1343749 517594 801490 24665 183.3 MiB 9.49 0.12 21.0587 -13121.7 -21.0587 21.0587 2.45 0.0167009 0.0137478 1.77708 1.46891 -1 -1 -1 -1 16 39654 47 5.547e+07 5.361e+07 -1 -1 43.54 5.72828 4.70791 113090 722879 -1 37482 13 19902 66283 3641519 680597 20.2436 20.2436 -13770 -20.2436 0 0 -1 -1 0.19 1.67 0.56 -1 -1 0.19 0.58033 0.500952 + k4_n4_v7_l1_bidir.xml seq.blif common 39.62 vpr 69.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 567 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71260 41 35 1791 1826 0 1347 643 26 26 676 clb auto 29.0 MiB 0.45 18608 203145 65187 132320 5638 69.6 MiB 1.44 0.02 18.1385 -520.265 -18.1385 nan 0.69 0.00437225 0.00383137 0.338582 0.298021 -1 -1 -1 -1 24 20201 48 1.728e+07 1.701e+07 -1 -1 33.10 1.88123 1.59699 51072 366016 -1 19098 15 8908 34158 2699342 394310 17.881 nan -530.81 -17.881 0 0 -1 -1 0.08 0.83 0.27 -1 -1 0.08 0.160739 0.141136 + k4_n4_v7_l1_bidir.xml spla.blif common 187.45 vpr 130.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1282 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 133456 16 46 3706 3752 0 2852 1344 38 38 1444 clb auto 43.1 MiB 1.08 48851 705674 261242 438237 6195 129.8 MiB 4.82 0.05 28.2789 -928.469 -28.2789 nan 1.62 0.00923375 0.00767658 0.87033 0.724376 -1 -1 -1 -1 30 55651 36 3.888e+07 3.846e+07 -1 -1 170.35 3.95474 3.27046 133344 1000208 -1 49871 15 17906 78246 6885546 1014380 27.1504 nan -941.372 -27.1504 0 0 -1 -1 0.25 2.27 0.77 -1 -1 0.25 0.36105 0.312454 + k4_n4_v7_l1_bidir.xml tseng.blif common 6.87 vpr 64.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 292 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65932 52 122 1483 1605 1 725 466 20 20 400 clb auto 25.0 MiB 0.16 6135 112438 30480 78177 3781 64.4 MiB 0.46 0.01 11.1777 -2780.46 -11.1777 11.1777 0.26 0.00160816 0.00140359 0.112456 0.0992435 -1 -1 -1 -1 14 6150 30 9.72e+06 8.76e+06 -1 -1 4.21 0.681536 0.590913 19872 120996 -1 5573 18 4232 15969 711167 147306 11.3812 11.3812 -3151.62 -11.3812 0 0 -1 -1 0.03 0.34 0.09 -1 -1 0.03 0.138745 0.122462 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/golden_results.txt index 9a0185a4a79..bb78a015d23 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml sha.v common 44.03 vpr 73.78 MiB -1 -1 3.12 49440 21 3.46 -1 -1 43232 -1 -1 149 38 -1 -1 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 75548 38 36 2570 2606 1 1074 223 15 15 225 clb auto 36.3 MiB 1.63 9037 73.8 MiB 0.90 0.01 11.9791 -2411.35 -11.9791 11.9791 0.03 0.00596368 0.00534087 0.447849 0.394176 -1 12486 10 9.10809e+06 8.03021e+06 2.53713e+06 11276.1 0.39 0.766703 0.68744 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml sha.v common 27.28 vpr 73.95 MiB -1 -1 4.23 47424 21 2.24 -1 -1 40536 -1 -1 150 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75720 38 36 2570 2606 1 1074 224 15 15 225 clb auto 33.2 MiB 1.42 8222 34904 7738 25262 1904 73.9 MiB 0.73 0.01 13.816 -2613.59 -13.816 13.816 0.00 0.0060727 0.0053926 0.356833 0.315667 -1 -1 -1 -1 -1 11320 14 9.10809e+06 8.0841e+06 2.53713e+06 11276.1 0.33 0.616726 0.549992 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt index 8308ae3e0d1..fce3205d8f2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt @@ -1,11 +1,11 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml bigkey.blif common 11.30 vpr 63.27 MiB -1 -1 -1 -1 3 0.32 -1 -1 34796 -1 -1 53 229 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64792 229 197 1023 1220 1 510 479 16 16 256 io auto 24.4 MiB 0.26 3412 154065 46239 98678 9148 63.3 MiB 0.73 0.01 2.41239 -578.515 -2.41239 2.41239 0.56 0.00388149 0.00363052 0.3504 0.328056 34 6563 36 1.05632e+07 2.85638e+06 613832. 2397.78 7.21 1.89404 1.73907 24564 122629 -1 5999 13 1330 2398 156004 35692 2.69369 2.69369 -639.318 -2.69369 0 0 751777. 2936.63 0.19 0.17 0.10 -1 -1 0.19 0.128614 0.119851 -k6_frac_N10_40nm.xml clma.blif common 7.57 vpr 60.88 MiB -1 -1 -1 -1 7 2.24 -1 -1 39876 -1 -1 77 36 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62344 36 82 542 624 1 389 195 11 11 121 clb auto 22.2 MiB 0.52 2075 39180 14775 18229 6176 60.9 MiB 0.27 0.00 4.56725 -162.762 -4.56725 4.56725 0.22 0.00159549 0.00146528 0.119745 0.110395 40 4742 31 4.36541e+06 4.14984e+06 303235. 2506.08 2.55 0.592576 0.518987 11571 60661 -1 3946 19 2186 7344 217806 45734 4.7836 4.7836 -183.173 -4.7836 0 0 379421. 3135.71 0.08 0.13 0.05 -1 -1 0.08 0.0725952 0.0652714 -k6_frac_N10_40nm.xml diffeq.blif common 4.35 vpr 62.58 MiB -1 -1 -1 -1 8 0.40 -1 -1 34344 -1 -1 52 64 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64080 64 39 941 980 1 449 155 10 10 100 clb auto 23.7 MiB 0.70 2754 14299 2774 10573 952 62.6 MiB 0.19 0.00 5.00123 -878.262 -5.00123 5.00123 0.18 0.00232392 0.00210955 0.0947283 0.0862055 46 4930 28 3.44922e+06 2.80249e+06 276332. 2763.32 1.38 0.487916 0.424969 9816 55112 -1 4472 14 1803 5492 169063 35103 5.16783 5.16783 -930.109 -5.16783 0 0 354105. 3541.05 0.07 0.14 0.04 -1 -1 0.07 0.0907073 0.0819924 -k6_frac_N10_40nm.xml dsip.blif common 7.40 vpr 64.36 MiB -1 -1 -1 -1 3 0.30 -1 -1 34644 -1 -1 68 229 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65904 229 197 1135 1332 1 648 494 16 16 256 io auto 24.9 MiB 0.70 4700 170318 50861 109699 9758 64.4 MiB 0.86 0.01 2.3875 -617.47 -2.3875 2.3875 0.55 0.00411276 0.00382969 0.375801 0.34991 34 9287 43 1.05632e+07 3.66479e+06 613832. 2397.78 2.70 1.24173 1.13943 24564 122629 -1 8151 13 2265 5666 327590 69866 2.60848 2.60848 -674.007 -2.60848 0 0 751777. 2936.63 0.18 0.22 0.10 -1 -1 0.18 0.147267 0.137349 -k6_frac_N10_40nm.xml elliptic.blif common 12.50 vpr 72.55 MiB -1 -1 -1 -1 10 1.33 -1 -1 37408 -1 -1 133 131 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74288 131 114 2471 2585 1 970 378 14 14 196 clb auto 32.0 MiB 2.92 9165 74142 19344 51191 3607 72.5 MiB 0.75 0.02 7.14215 -3414.64 -7.14215 7.14215 0.39 0.00547722 0.00485817 0.331988 0.297156 64 15825 36 7.76074e+06 7.1679e+06 810706. 4136.26 3.87 1.47043 1.28666 22444 164128 -1 14159 17 4519 20253 781043 131442 7.47917 7.47917 -3699.02 -7.47917 0 0 1.00880e+06 5146.95 0.21 0.43 0.13 -1 -1 0.21 0.253091 0.228552 -k6_frac_N10_40nm.xml frisc.blif common 16.27 vpr 74.19 MiB -1 -1 -1 -1 12 2.02 -1 -1 37188 -1 -1 153 20 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75968 20 116 2477 2593 1 1088 289 15 15 225 clb auto 33.3 MiB 3.67 12581 59499 15581 39947 3971 74.2 MiB 0.86 0.01 8.14365 -3747.83 -8.14365 8.14365 0.46 0.00553861 0.00488686 0.382187 0.339626 74 21933 44 9.10809e+06 8.24578e+06 1.06098e+06 4715.46 5.56 1.63058 1.41486 27275 217117 -1 19654 18 5722 25295 1201911 194668 8.26982 8.26982 -3960.51 -8.26982 0 0 1.32822e+06 5903.22 0.28 0.55 0.17 -1 -1 0.28 0.277444 0.249442 -k6_frac_N10_40nm.xml s298.blif common 5.81 vpr 62.13 MiB -1 -1 -1 -1 8 0.57 -1 -1 33988 -1 -1 61 4 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63620 4 6 671 677 1 350 71 10 10 100 clb auto 23.2 MiB 0.91 3493 3283 433 2659 191 62.1 MiB 0.10 0.00 5.33805 -43.3781 -5.33805 5.33805 0.18 0.00193693 0.00174134 0.0562002 0.0515773 52 5783 22 3.44922e+06 3.28753e+06 305142. 3051.42 2.47 0.614574 0.526903 10212 61796 -1 5397 17 2148 10775 376607 64965 5.90507 5.90507 -48.8576 -5.90507 0 0 401807. 4018.07 0.08 0.19 0.05 -1 -1 0.08 0.0945264 0.084902 -k6_frac_N10_40nm.xml s38417.blif common 14.75 vpr 78.14 MiB -1 -1 -1 -1 6 3.01 -1 -1 42440 -1 -1 179 29 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80016 29 106 3450 3556 1 1198 314 16 16 256 clb auto 37.1 MiB 2.04 8989 70670 18144 45519 7007 78.1 MiB 0.96 0.01 4.74073 -2890.12 -4.74073 4.74073 0.54 0.00636901 0.00556012 0.4763 0.414513 48 14980 41 1.05632e+07 9.64703e+06 819368. 3200.65 4.15 2.12828 1.82805 26860 167058 -1 13212 15 5024 17286 529604 104654 4.75139 4.75139 -2966.77 -4.75139 0 0 1.04748e+06 4091.72 0.24 0.42 0.13 -1 -1 0.24 0.302619 0.272356 -k6_frac_N10_40nm.xml s38584.1.blif common 16.03 vpr 78.52 MiB -1 -1 -1 -1 6 2.15 -1 -1 41076 -1 -1 194 38 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80400 38 304 3259 3563 1 1574 536 16 16 256 clb auto 37.8 MiB 3.25 9889 183320 55884 108640 18796 78.5 MiB 1.52 0.02 4.27217 -2394.9 -4.27217 4.27217 0.54 0.00692031 0.00615749 0.646279 0.571663 58 17695 25 1.05632e+07 1.04554e+07 977637. 3818.90 4.53 2.11223 1.84277 28644 201685 -1 15484 13 5074 13582 483608 102794 4.69981 4.69981 -2495.41 -4.69981 0 0 1.24374e+06 4858.37 0.28 0.40 0.16 -1 -1 0.28 0.308951 0.281339 -k6_frac_N10_40nm.xml tseng.blif common 3.98 vpr 60.70 MiB -1 -1 -1 -1 7 0.27 -1 -1 34484 -1 -1 34 52 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62156 52 122 664 786 1 355 208 8 8 64 io clb auto 22.0 MiB 0.68 1783 26080 5856 18588 1636 60.7 MiB 0.20 0.00 4.2185 -596.347 -4.2185 4.2185 0.10 0.00193464 0.00178089 0.0920256 0.0848454 58 3398 46 1.94018e+06 1.8324e+06 203254. 3175.84 1.50 0.686589 0.603505 6532 39661 -1 2965 13 1169 3143 108747 29150 4.26194 4.26194 -630.352 -4.26194 0 0 258247. 4035.11 0.05 0.10 0.03 -1 -1 0.05 0.0682836 0.0622434 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml bigkey.blif common 5.65 vpr 64.37 MiB -1 -1 -1 -1 3 0.37 -1 -1 34760 -1 -1 53 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65912 229 197 1023 1220 1 510 479 16 16 256 io auto 23.7 MiB 0.27 3641 154065 46430 98015 9620 64.4 MiB 0.75 0.01 2.42373 -577.247 -2.42373 2.42373 0.27 0.00402185 0.0037687 0.347336 0.325429 -1 -1 -1 -1 36 6328 35 1.05632e+07 2.85638e+06 638738. 2495.07 2.33 1.3288 1.226 24820 128426 -1 5481 8 1306 2376 126862 31374 2.67597 2.67597 -632.008 -2.67597 0 0 786978. 3074.13 0.03 0.14 0.10 -1 -1 0.03 0.10014 0.0939306 + k6_frac_N10_40nm.xml clma.blif common 7.01 vpr 61.45 MiB -1 -1 -1 -1 7 2.26 -1 -1 40008 -1 -1 79 36 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62928 36 82 542 624 1 389 197 11 11 121 clb auto 22.0 MiB 0.54 2089 43172 15722 20877 6573 61.5 MiB 0.30 0.01 4.60077 -165.07 -4.60077 4.60077 0.11 0.00158856 0.00146661 0.128968 0.119097 -1 -1 -1 -1 44 4139 30 4.36541e+06 4.25763e+06 327165. 2703.84 1.96 0.513339 0.454587 11931 67129 -1 3316 16 1708 5716 138864 32420 4.83136 4.83136 -175.151 -4.83136 0 0 426099. 3521.48 0.01 0.11 0.05 -1 -1 0.01 0.0673334 0.0609583 + k6_frac_N10_40nm.xml diffeq.blif common 4.08 vpr 63.54 MiB -1 -1 -1 -1 8 0.41 -1 -1 34312 -1 -1 52 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65060 64 39 941 980 1 449 155 10 10 100 clb auto 23.5 MiB 0.77 2832 12635 2438 9282 915 63.5 MiB 0.18 0.01 4.98272 -882.824 -4.98272 4.98272 0.09 0.00238086 0.0021534 0.0867068 0.0790903 -1 -1 -1 -1 46 4591 19 3.44922e+06 2.80249e+06 276332. 2763.32 1.21 0.589006 0.512826 9816 55112 -1 4111 18 1656 5042 136520 29654 5.41789 5.41789 -952.235 -5.41789 0 0 354105. 3541.05 0.01 0.16 0.04 -1 -1 0.01 0.110724 0.0994958 + k6_frac_N10_40nm.xml dsip.blif common 7.35 vpr 64.67 MiB -1 -1 -1 -1 3 0.33 -1 -1 34628 -1 -1 68 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66224 229 197 1135 1332 1 648 494 16 16 256 io auto 25.0 MiB 0.72 5390 162510 50223 103313 8974 64.7 MiB 0.91 0.01 2.31397 -600.978 -2.31397 2.31397 0.27 0.00421493 0.00392148 0.372643 0.347093 -1 -1 -1 -1 34 9972 32 1.05632e+07 3.66479e+06 613832. 2397.78 3.30 1.45616 1.33282 24564 122629 -1 8332 13 2339 5868 306706 68264 2.51113 2.51113 -669.569 -2.51113 0 0 751777. 2936.63 0.03 0.23 0.10 -1 -1 0.03 0.152244 0.141942 + k6_frac_N10_40nm.xml elliptic.blif common 11.64 vpr 72.78 MiB -1 -1 -1 -1 10 1.34 -1 -1 37432 -1 -1 134 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74524 131 114 2471 2585 1 965 379 14 14 196 clb auto 31.8 MiB 3.04 9493 78526 21300 53244 3982 72.8 MiB 0.92 0.02 6.66989 -3362.18 -6.66989 6.66989 0.19 0.00621513 0.00561729 0.393073 0.34792 -1 -1 -1 -1 64 15463 36 7.76074e+06 7.2218e+06 810706. 4136.26 3.33 1.63306 1.42706 22444 164128 -1 13666 16 4234 17970 605416 107406 6.78748 6.78748 -3469.91 -6.78748 0 0 1.00880e+06 5146.95 0.03 0.43 0.13 -1 -1 0.03 0.272075 0.245691 + k6_frac_N10_40nm.xml frisc.blif common 13.54 vpr 74.06 MiB -1 -1 -1 -1 12 2.03 -1 -1 37144 -1 -1 154 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75836 20 116 2477 2593 1 1095 290 15 15 225 clb auto 33.2 MiB 3.17 12890 61666 15631 41457 4578 74.1 MiB 0.67 0.01 8.02167 -3816.55 -8.02167 8.02167 0.17 0.00308355 0.00276008 0.244864 0.21648 -1 -1 -1 -1 74 21484 43 9.10809e+06 8.29968e+06 1.06098e+06 4715.46 4.50 1.57616 1.37159 27275 217117 -1 19434 16 5788 25215 1069833 185373 8.27179 8.27179 -4029.23 -8.27179 0 0 1.32822e+06 5903.22 0.04 0.55 0.17 -1 -1 0.04 0.282827 0.255609 + k6_frac_N10_40nm.xml s298.blif common 4.79 vpr 62.54 MiB -1 -1 -1 -1 8 0.58 -1 -1 33952 -1 -1 61 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64036 4 6 671 677 1 350 71 10 10 100 clb auto 23.2 MiB 0.90 3495 3137 432 2529 176 62.5 MiB 0.10 0.00 5.3014 -43.7499 -5.3014 5.3014 0.09 0.00191372 0.00173621 0.0550982 0.0506336 -1 -1 -1 -1 54 5597 27 3.44922e+06 3.28753e+06 316276. 3162.76 1.25 0.504852 0.437208 10312 63908 -1 5157 17 2266 11525 327366 61505 5.48392 5.48392 -46.8399 -5.48392 0 0 411339. 4113.39 0.01 0.18 0.05 -1 -1 0.01 0.0985021 0.0889271 + k6_frac_N10_40nm.xml s38417.blif common 14.29 vpr 78.14 MiB -1 -1 -1 -1 6 3.06 -1 -1 42400 -1 -1 176 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80012 29 106 3450 3556 1 1190 311 16 16 256 clb auto 36.9 MiB 1.87 8949 65597 16026 43107 6464 78.1 MiB 1.20 0.02 4.50231 -2905.37 -4.50231 4.50231 0.27 0.00878799 0.00788817 0.629893 0.548582 -1 -1 -1 -1 46 15732 39 1.05632e+07 9.48534e+06 786978. 3074.13 4.38 2.35028 2.01673 26604 162157 -1 13635 14 5142 17426 519616 106370 4.53102 4.53102 -2987.6 -4.53102 0 0 1.01084e+06 3948.58 0.03 0.46 0.12 -1 -1 0.03 0.329139 0.295823 + k6_frac_N10_40nm.xml s38584.1.blif common 15.85 vpr 78.47 MiB -1 -1 -1 -1 6 2.17 -1 -1 41016 -1 -1 203 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80352 38 304 3259 3563 1 1559 545 17 17 289 clb auto 37.3 MiB 3.11 10446 174095 49766 105233 19096 78.5 MiB 1.70 0.02 4.29015 -2399.8 -4.29015 4.29015 0.30 0.00816298 0.00737727 0.707435 0.623009 -1 -1 -1 -1 58 17767 23 1.21262e+07 1.09405e+07 1.11519e+06 3858.79 4.82 2.79347 2.44034 32499 230706 -1 16008 15 5250 14700 516522 110817 4.81093 4.81093 -2541.32 -4.81093 0 0 1.41877e+06 4909.24 0.05 0.49 0.18 -1 -1 0.05 0.36595 0.331861 + k6_frac_N10_40nm.xml tseng.blif common 3.49 vpr 61.39 MiB -1 -1 -1 -1 7 0.30 -1 -1 34332 -1 -1 33 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62864 52 122 664 786 1 358 207 8 8 64 io clb auto 21.8 MiB 0.69 1908 22239 4478 16280 1481 61.4 MiB 0.19 0.01 4.25559 -597.466 -4.25559 4.25559 0.05 0.00195021 0.00179724 0.0809638 0.0748422 -1 -1 -1 -1 58 3323 26 1.94018e+06 1.7785e+06 203254. 3175.84 1.00 0.508961 0.449326 6532 39661 -1 2850 14 1079 2916 89573 24965 4.64398 4.64398 -644.298 -4.64398 0 0 258247. 4035.11 0.01 0.11 0.03 -1 -1 0.01 0.0730931 0.0666261 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt index e7281d70fba..6a59a733970 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 47.21 vpr 98.92 MiB -1 -1 5.05 65016 8 3.45 -1 -1 44040 -1 -1 251 385 2 1 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 101292 385 362 4531 4417 1 2465 1001 26 26 676 io auto 59.7 MiB 5.71 30896 96.5 MiB 3.76 0.04 8.37958 -9104.32 -8.37958 8.37958 1.98 0.00830834 0.00758752 1.05656 0.959646 90 47787 47 3.69863e+07 1.50194e+07 3.84682e+06 5690.57 18.16 4.21656 3.81172 44385 19 10566 34671 3451960 662494 9.05146 9.05146 -10537 -9.05146 0 0 4.81243e+06 7118.99 1.55 1.22 0.549245 0.511207 - k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 19.74 vpr 79.73 MiB -1 -1 2.63 46860 4 2.10 -1 -1 41524 -1 -1 132 38 0 0 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 81640 38 36 2744 2493 1 1037 206 16 16 256 clb auto 42.8 MiB 2.33 8753 79.7 MiB 0.86 0.01 9.36767 -2501.88 -9.36767 9.36767 0.82 0.00550316 0.00491598 0.40002 0.356102 62 13665 39 1.21132e+07 7.11401e+06 968026. 3781.35 6.03 2.53777 2.22319 12472 21 4184 9814 370969 64997 10.7551 10.7551 -3015.2 -10.7551 0 0 1.20332e+06 4700.46 0.45 0.55 0.435383 0.391894 - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 28.60 vpr 68.80 MiB -1 -1 17.23 47568 3 0.87 -1 -1 38244 -1 -1 44 196 1 0 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 70452 196 193 1202 1347 1 614 434 15 15 225 io auto 30.8 MiB 0.96 3011 68.8 MiB 0.68 0.01 2.01184 -980.486 -2.01184 2.01184 0.78 0.00265232 0.00237738 0.259845 0.234269 40 6048 22 1.03862e+07 2.91934e+06 568276. 2525.67 4.59 1.09948 1.00544 5465 12 1709 2607 217962 55517 2.51002 2.51002 -1171.5 -2.51002 0 0 712852. 3168.23 0.29 0.17 0.113728 0.107732 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 39.01 vpr 82.69 MiB -1 -1 4.24 45940 3 1.03 -1 -1 40156 -1 -1 120 236 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84672 236 305 3195 3007 1 1534 668 19 19 361 io auto 45.6 MiB 3.15 12151 82.7 MiB 2.21 0.03 4.27652 -2642.42 -4.27652 4.27652 1.33 0.00627945 0.00562841 0.771371 0.692542 62 23629 24 1.72706e+07 9.39128e+06 1.42198e+06 3939.00 19.99 3.88206 3.48504 20659 16 6434 17007 3134575 708021 4.9842 4.9842 -3082.5 -4.9842 0 0 1.76637e+06 4892.99 0.79 1.16 0.398852 0.370941 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 45.88 vpr 105.39 MiB -1 -1 6.79 63484 8 3.06 -1 -1 40704 -1 -1 250 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 107916 385 362 4415 4299 1 2365 1000 26 26 676 io auto 53.4 MiB 8.02 30064 545782 201861 320153 23768 96.5 MiB 5.36 0.06 9.17025 -9814.95 -9.17025 9.17025 0.75 0.0154429 0.0143793 1.79153 1.64504 -1 -1 -1 -1 86 44693 20 3.69863e+07 1.49655e+07 3.69198e+06 5461.52 13.35 6.72204 6.1687 89040 769342 -1 41511 17 9662 32287 1739041 311622 9.36868 9.36868 -10331.7 -9.36868 0 0 4.67059e+06 6909.16 0.16 1.11 0.68 -1 -1 0.16 0.681008 0.635643 + k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 15.44 vpr 81.45 MiB -1 -1 3.43 44504 3 1.23 -1 -1 39800 -1 -1 141 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83404 38 36 2739 2488 1 1022 215 17 17 289 clb auto 40.5 MiB 1.96 8926 42010 10393 28489 3128 81.4 MiB 0.91 0.01 10.0828 -2706.04 -10.0828 10.0828 0.30 0.00541664 0.00477131 0.391772 0.345384 -1 -1 -1 -1 62 13454 38 1.34605e+07 7.59905e+06 1.10657e+06 3828.96 3.45 1.77757 1.52314 31771 216973 -1 12449 21 4102 9497 328915 58876 10.8931 10.8931 -3012.43 -10.8931 0 0 1.37508e+06 4758.06 0.05 0.40 0.19 -1 -1 0.05 0.289893 0.256286 + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 24.74 vpr 70.58 MiB -1 -1 17.86 45828 3 0.69 -1 -1 35540 -1 -1 48 196 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72272 196 193 1201 1346 1 606 438 15 15 225 io auto 31.2 MiB 0.83 3130 146694 39708 93961 13025 70.6 MiB 0.73 0.01 2.24601 -1081.12 -2.24601 2.24601 0.23 0.00356204 0.00332113 0.333364 0.31069 -1 -1 -1 -1 36 6058 29 1.03862e+07 3.13491e+06 520410. 2312.93 1.93 1.18409 1.08635 21110 102306 -1 5134 10 1618 2340 136007 39516 2.56471 2.56471 -1177.45 -2.56471 0 0 643451. 2859.78 0.02 0.14 0.09 -1 -1 0.02 0.102579 0.095844 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 22.86 vpr 83.41 MiB -1 -1 4.78 42380 3 0.69 -1 -1 37656 -1 -1 129 236 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85412 236 305 3199 3011 1 1520 677 19 19 361 io auto 42.5 MiB 2.99 12761 268067 88565 164726 14776 83.4 MiB 2.03 0.03 4.74988 -2887.79 -4.74988 4.74988 0.39 0.00859777 0.00794312 0.829104 0.763261 -1 -1 -1 -1 62 24213 37 1.72706e+07 9.87633e+06 1.42198e+06 3939.00 7.32 3.04293 2.76861 40483 281719 -1 20603 18 6062 15441 1381198 347776 4.88181 4.88181 -3127.07 -4.88181 0 0 1.76637e+06 4892.99 0.06 0.66 0.24 -1 -1 0.06 0.38505 0.357195 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/golden_results.txt index cf79f555b8c..a4f9b24ece9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 641.67 vpr 492.06 MiB -1 -1 62.37 452332 97 114.33 -1 -1 115316 -1 -1 2134 114 45 8 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 503872 114 102 35773 31864 1 16914 2403 56 56 3136 clb auto 343.5 MiB 83.71 223478 368.9 MiB 77.61 0.67 65.1983 -51745.6 -65.1983 65.1983 1.35 0.10571 0.0920455 13.1674 10.7012 -1 321806 23 1.8697e+08 1.4284e+08 2.05038e+07 6538.21 25.53 21.7816 18.0231 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 487.31 vpr 496.91 MiB -1 -1 76.36 452592 97 71.44 -1 -1 112732 -1 -1 2151 114 45 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 508836 114 102 35834 31925 1 16897 2420 56 56 3136 clb auto 278.8 MiB 75.84 221426 1805060 662974 1113867 28219 408.5 MiB 56.83 0.51 73.2133 -55671.2 -73.2133 73.2133 0.01 0.0965983 0.0857314 13.1957 10.9836 -1 -1 -1 -1 -1 309163 22 1.8697e+08 1.43756e+08 2.23321e+07 7121.20 10.26 19.311 16.2288 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt index f2b439ff03e..b88815848b4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 1315.84 77 3123 89 136 0 0 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 2858228 42 35 119888 86875 1 51283 3425 129 96 12384 DSP auto 86.66 609879 114.00 0.78 7.31659 -73007.4 -6.31659 6.39652 193.04 0.230423 0.177265 33.2852 25.4119 777696 -1 -1 -1 -1 0 0 2.28642e+08 18462.7 20 7.77193 6.96909 -118197 -6.77193 0 0 50.21 46.7196 37.2174 149.58 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 868.60 vpr 2.85 GiB 77 3136 89 136 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2992704 42 35 119888 86875 1 50816 3438 129 96 12384 DSP auto 1747.1 MiB 107.17 582667 3141815 1177622 1941316 22877 2922.6 MiB 141.55 1.07 8.30634 -81008.6 -7.30634 5.71368 0.07 0.395558 0.333308 50.4231 42.3852 753664 14.8455 159283 3.13753 108681 189329 132420316 35517631 0 0 2.28639e+08 18462.4 18 3593250 39165143 -1 8.74065 6.13717 -112227 -7.74065 0 0 68.73 -1 -1 2922.6 MiB 45.88 68.8436 58.8864 2922.6 MiB -1 22.31 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_other/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_other/config/golden_results.txt index 71836073bd1..b1f58c98f8e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_other/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_other/config/golden_results.txt @@ -1,24 +1,24 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time -stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 311.80 274 967 36 59 0 2 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1686764 22 252 53001 29054 7 24654 1338 89 66 5874 DSP auto 23.51 252822 67.35 0.34 7.26641 -38060.9 -6.26641 2.79561 72.76 0.0922902 0.0742036 19.4784 15.1106 354720 83977 171255 284760839 58437920 0 0 1.08076e+08 18399.1 50 7.93667 2.94925 -43306.7 -6.93667 0 0 48.18 30.2955 24.559 65.43 -stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 215.82 36 1583 10 10 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1399980 3 33 48977 39238 1 25960 1639 54 40 2160 LAB auto 60.22 275660 73.30 0.48 76.888 -77679.7 -75.888 76.888 8.10 0.0956007 0.0692678 14.5078 10.6502 370341 90509 238008 217472654 23545267 0 0 3.96465e+07 18354.9 28 71.6492 71.6492 -105914 -70.6492 0 0 28.14 21.4905 16.5041 21.42 -stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 492.02 211 2256 3 210 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1898600 38 173 62892 59064 3 36122 2680 86 64 5504 M9K auto 130.91 654114 131.72 0.80 13.3368 -342543 -12.3368 7.39474 50.51 0.177306 0.126609 25.7151 17.5933 892864 172996 611822 407520129 46601819 0 0 1.01289e+08 18402.8 68 14.1432 7.7062 -394796 -13.1432 0 0 73.84 51.3879 38.3937 62.13 -stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 613.15 574 2805 16 0 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1988108 4 570 66175 54803 2 39637 3395 91 67 6097 io auto 110.71 677805 163.29 1.08 28.2408 -109542 -27.2408 6.93264 72.80 0.187151 0.130173 25.6141 17.899 973037 224900 867383 947842960 143826835 0 0 1.12157e+08 18395.4 25 29.6387 8.19964 -124725 -28.6387 0 0 154.76 37.9372 28.0766 66.17 -stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 1318.55 40 3678 172 1 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 4743240 19 21 171111 96274 1 72623 3891 194 144 27936 DSP auto 76.77 765977 145.09 1.60 5.16314 -128136 -4.16314 3.90969 508.03 0.285112 0.239247 42.3664 34.8257 874132 150455 182899 349628973 70478863 0 0 5.18919e+08 18575.3 13 5.45721 4.48464 -179446 -4.45721 0 0 63.66 54.6347 45.956 400.24 -stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 341.45 536 1972 7 4 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1657868 227 309 49176 40422 1 28183 2519 85 63 5355 io auto 77.01 312290 91.24 0.69 195.971 -119913 -194.971 195.971 50.83 0.0991588 0.084565 16.0983 11.5643 406195 106821 335442 213233166 16541048 0 0 9.84408e+07 18383.0 22 188.774 188.774 -136523 -187.774 0 0 25.35 22.7627 17.0347 58.18 -stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 247.43 36 1332 8 149 2 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1531868 3 33 52402 39411 1 28117 1527 73 54 3942 M9K auto 61.30 324276 56.90 0.43 16.9115 -306564 -15.9115 16.9115 21.92 0.115668 0.0811981 14.2927 9.97478 446671 101291 248928 219409565 29355499 0 0 7.26339e+07 18425.6 49 17.5096 17.5096 -329353 -16.5096 0 0 36.21 25.5848 19.3127 40.00 -stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 103.86 251 951 1 17 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1118884 55 196 20131 19956 1 8395 1220 44 33 1452 io auto 36.33 120394 17.88 0.13 7.53064 -73100.4 -6.53064 7.53064 5.18 0.0385338 0.0250793 5.54194 3.66441 176474 31041 128473 83605460 6753731 0 0 2.65099e+07 18257.5 28 8.2232 8.2232 -80771.2 -7.2232 0 0 10.41 8.44641 6.09178 14.90 -stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 219.94 255 2095 1 28 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1429560 84 171 36458 36247 3 20591 2379 62 46 2852 LAB auto 73.17 304905 58.87 0.36 12.4545 -84121.6 -11.4545 3.90486 14.28 0.0957957 0.0630812 14.7936 9.65547 399311 62124 215218 133537079 11346973 0 0 5.24521e+07 18391.3 13 13.7366 4.34743 -96722.9 -12.7366 0 0 15.78 19.0668 13.1481 28.90 -stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 423.80 69 2106 10 295 16 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 2030312 36 33 57796 49182 1 20383 2496 105 78 8190 M9K auto 64.78 248417 57.14 0.43 8.87852 -98126.1 -7.87852 8.87852 101.81 0.102251 0.0739036 16.5433 11.9168 401785 70797 206901 253160930 44501707 0 0 1.50986e+08 18435.5 70 8.73181 8.73181 -152440 -7.73181 0 0 59.20 32.5906 25.4858 95.57 -stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 414.48 478 1243 1 300 4 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1930672 202 276 35125 30509 3 21597 2026 106 79 8374 M9K auto 62.32 273262 46.18 0.37 9.02165 -38875.4 -8.02165 2.98256 116.87 0.119629 0.0874896 15.1424 10.6139 427620 69908 196969 259577742 42937167 0 0 1.54360e+08 18433.2 24 9.59492 3.21937 -53394.2 -8.59492 0 0 49.61 22.0979 16.4463 95.83 -stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 221.49 5 335 31 105 0 2 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1529424 3 2 14862 10304 26 7545 478 89 66 5874 DSP auto 32.10 110073 8.69 0.05 5.6799 -31954.6 -4.6799 3.86103 73.08 0.0297436 0.0249301 5.08886 3.80117 162487 18820 40748 49231361 8764921 0 0 1.08076e+08 18399.1 13 5.94858 4.19214 -42746.9 -4.94858 0 0 8.06 6.74261 5.24191 66.24 -stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 453.16 693 1772 25 16 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 2041664 35 658 51416 37539 1 27838 2506 108 80 8640 io auto 58.41 242409 99.55 0.46 37.8217 -58716.9 -36.8217 37.8217 112.56 0.0923575 0.0800076 22.4325 16.6445 339418 92511 294098 299646713 40180048 0 0 1.59377e+08 18446.5 21 38.6529 38.6529 -63587.1 -37.6529 0 0 37.23 29.0352 22.2784 99.48 -stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 370.66 753 1134 5 32 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 2077072 13 740 25173 25306 1 12841 1924 117 87 10179 io auto 43.57 162862 27.12 0.18 9.4498 -29888.4 -8.4498 7.62781 119.49 0.0419754 0.0337119 7.41368 5.12874 203573 33756 127355 88616513 6903805 0 0 1.87947e+08 18464.1 16 10.0597 7.94534 -35332.5 -9.05972 0 0 10.27 10.3001 7.58645 123.59 -stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 254.87 117 2162 0 0 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1586756 79 38 66795 54922 1 35874 2279 62 46 2852 LAB auto 66.38 265514 91.85 0.60 9.73271 -169191 -8.73271 9.73271 14.10 0.109447 0.0754959 15.151 10.2167 353280 150391 325210 185311692 14766611 0 0 5.24521e+07 18391.3 39 10.5988 10.5988 -198966 -9.59881 0 0 26.10 26.0487 19.0873 27.50 -stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 199.98 213 1566 26 4 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1599748 139 74 57121 41054 1 24187 1809 75 56 4200 DSP auto 50.57 166705 40.06 0.27 5.67384 -21057.2 -4.67384 4.83115 17.58 0.089833 0.0688155 14.1813 10.5486 223321 55207 100513 123731930 21668188 0 0 7.74195e+07 18433.2 28 6.01154 5.30578 -34881.6 -5.01154 0 0 20.05 20.8584 16.3292 41.08 -stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 93.73 54 671 0 40 0 1 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1075876 2 52 16673 16662 2 12020 766 38 28 1064 LAB auto 28.79 181169 14.48 0.11 5.49667 -21261.7 -4.49667 4.87568 5.83 0.044069 0.0283665 5.5448 3.63538 246051 57719 179681 173183538 18866158 0 0 1.93821e+07 18216.2 19 6.0422 5.29849 -27330.5 -5.0422 0 0 19.56 8.20931 5.7957 8.71 -stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 310.33 445 2166 19 51 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1713300 131 314 57881 45152 1 32966 2681 73 54 3942 io auto 70.45 321679 104.87 0.89 196.373 -68832.2 -195.373 196.373 21.24 0.227108 0.170335 20.1175 14.878 433232 110664 348056 280252346 23247136 0 0 7.26339e+07 18425.6 39 188.336 188.336 -82847 -187.336 0 0 37.14 33.2841 25.9806 41.01 -stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 54.29 42 750 0 0 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1042248 13 29 26295 20086 1 12417 792 39 29 1131 LAB auto 9.43 75218 10.95 0.06 4.87175 -4560.25 -3.87175 2.71822 4.94 0.0168256 0.0134598 2.75581 1.80879 82722 32407 46016 30062452 2507226 0 0 2.05958e+07 18210.3 16 4.98602 2.75435 -5381.95 -3.98602 0 0 3.35 3.89581 2.77576 9.91 -stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 678.97 964 982 19 34 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 2781748 542 422 37277 26038 1 20655 1999 147 109 16023 io auto 41.73 267816 73.62 0.80 7.80246 -38033.5 -6.80246 7.6263 258.47 0.0892357 0.0697083 13.6631 10.2442 362796 92851 202881 211513388 35702086 0 0 2.96650e+08 18514.0 55 8.53312 8.20447 -44732.7 -7.53312 0 0 41.77 24.7555 19.7387 200.64 -stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 799.35 1107 724 0 0 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 3223976 403 704 15490 16194 1 8415 1831 167 124 20708 io auto 37.55 190229 16.71 0.14 11.4027 -21636.9 -10.4027 4.89489 400.55 0.0371088 0.0262547 5.13621 3.50481 233299 26413 105009 64404491 4696027 0 0 3.84012e+08 18544.1 14 11.8994 5.31154 -27542.3 -10.8994 0 0 7.34 6.87555 4.97917 259.42 -stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 89.94 35 730 0 6 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1046032 18 17 16969 16357 1 6291 771 39 29 1131 LAB auto 39.14 82220 9.36 0.08 6.86051 -43809.9 -5.86051 6.86051 4.27 0.0198281 0.0155483 3.08359 2.01596 116615 27639 146882 73829529 5721062 0 0 2.05958e+07 18210.3 43 7.27333 7.27333 -49633.6 -6.27333 0 0 10.96 6.52073 4.82028 9.83 -stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 16.85 35 76 0 8 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1076940 18 17 2291 2142 1 1504 119 16 12 192 LAB M9K auto 4.08 10271 0.96 0.01 4.965 -3328.06 -3.965 3.70554 0.09 0.00544208 0.00414461 0.470524 0.35424 14141 4076 9559 7859416 739818 0 0 3.35078e+06 17452.0 20 5.1517 3.94454 -3676.27 -4.1517 0 0 0.88 0.737841 0.591727 0.41 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2102508 4 570 66175 54803 2 39221 3376 91 67 6097 io auto 1442.4 MiB 160.90 637050 2737396 996225 1655508 85663 2024.5 MiB 152.59 1.32 31.0835 -120493 -30.0835 7.14678 0.05 0.24893 0.221734 29.4275 24.9184 899667 22.9413 200386 5.10980 182427 712388 314287781 64497091 0 0 1.12154e+08 18394.9 22 1777086 19206576 -1 31.4681 7.0455 -124410 -30.4681 0 0 40.50 -1 -1 2024.5 MiB 89.22 43.711 37.2882 2024.5 MiB -1 9.88 + stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 581.34 vpr 4.71 GiB 40 3697 172 1 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 4942252 19 21 171111 96274 1 69059 3910 194 144 27936 DSP auto 1879.6 MiB 92.06 765653 3945030 1609251 2318045 17734 4826.4 MiB 169.94 1.44 6.56186 -137549 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1271264 55 196 20131 19956 1 8273 1224 44 33 1452 io auto 1086.7 MiB 51.58 121891 590184 190135 382049 18000 1219.4 MiB 16.94 0.19 8.00991 -79285.3 -7.00991 8.00991 0.01 0.0540335 0.042834 5.3265 4.25169 175526 21.2244 41043 4.96288 27288 110050 30231721 5468094 0 0 2.65070e+07 18255.5 16 423692 4510959 -1 8.24194 8.24194 -78833.9 -7.24194 0 0 10.78 -1 -1 1219.4 MiB 10.31 7.96372 6.52567 1219.4 MiB -1 2.08 + stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 249.81 vpr 1.51 GiB 255 2122 1 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1578260 84 171 36458 36247 3 20327 2406 62 46 2852 LAB auto 1227.7 MiB 129.65 282856 1613906 577988 956437 79481 1496.5 MiB 49.09 0.46 12.7635 -89890.6 -11.7635 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1767028 3 2 14862 10304 26 7583 476 89 66 5874 DSP auto 1033.8 MiB 53.02 124138 182462 49732 129080 3650 1725.6 MiB 10.85 0.11 5.88079 -31819.8 -4.88079 4.5134 0.03 0.0618536 0.0525314 6.42815 5.46252 179249 23.7196 37106 4.91015 18387 40581 28916864 7312373 0 0 1.08074e+08 18398.6 14 1714760 18504579 -1 6.28555 4.43959 -39032.4 -5.28555 0 0 38.34 -1 -1 1725.6 MiB 8.47 8.90485 7.65703 1725.6 MiB -1 8.94 + stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 303.21 vpr 2.16 GiB 693 1797 25 16 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2264080 35 658 51416 37539 1 27427 2531 108 80 8640 io auto 1279.4 MiB 79.02 241934 2243861 754419 1344439 145003 2211.0 MiB 86.86 0.75 41.8615 -66574.8 -40.8615 41.8615 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1740272 139 74 57121 41054 1 24001 1808 75 56 4200 DSP auto 1288.6 MiB 70.43 167389 1300988 426055 839266 35667 1699.5 MiB 55.74 0.51 5.92747 -26440.3 -4.92747 5.12571 0.04 0.163802 0.140085 19.2082 16.3816 226209 9.42655 53807 2.24224 52155 95084 47723189 13084284 0 0 7.74167e+07 18432.5 19 1223026 13250712 -1 6.18889 5.28844 -34182.8 -5.18889 0 0 27.88 -1 -1 1699.5 MiB 17.42 27.0898 23.3547 1699.5 MiB -1 6.41 + stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 102.62 vpr 1.18 GiB 54 665 0 40 0 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1232304 2 52 16673 16662 2 12027 760 37 27 999 LAB auto 1064.5 MiB 40.48 185817 260785 68816 184545 7424 1165.2 MiB 13.22 0.17 6.43593 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36.2469 31.1156 1720.1 MiB -1 6.18 + stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 56.35 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1213036 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1061.7 MiB 12.38 72155 253216 50624 190930 11662 1175.9 MiB 10.02 0.13 5.18599 -5515.92 -4.18599 2.85104 0.01 0.0366291 0.0316121 2.8417 2.37087 84093 6.76152 20141 1.61944 25550 34715 9357710 1681121 0 0 2.05929e+07 18207.7 16 331560 3499109 -1 5.29142 2.82099 -5638.13 -4.29142 0 0 8.52 -1 -1 1175.9 MiB 3.91 4.51909 3.83081 1175.9 MiB -1 1.49 + stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 335.23 vpr 2.90 GiB 964 1119 19 34 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3043780 542 422 37277 26038 1 20403 2136 147 109 16023 io auto 1148.7 MiB 80.27 272838 1734636 659517 1007756 67363 2972.4 MiB 69.82 0.57 8.43041 -42423.1 -7.43041 8.08995 0.09 0.110892 0.0979927 15.5695 13.2591 363091 17.7986 78522 3.84912 59722 139345 87871064 23006283 0 0 2.96647e+08 18513.8 19 4640960 50771684 -1 8.69484 7.49966 -42054.1 -7.69484 0 0 98.95 -1 -1 2972.4 MiB 25.07 21.2025 18.289 2972.4 MiB -1 29.48 + stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 287.05 vpr 3.37 GiB 1107 725 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3531316 403 704 15490 16194 1 8534 1832 167 124 20708 io auto 1059.2 MiB 60.68 187193 1324022 523278 764997 35747 3448.6 MiB 22.04 0.19 12.7682 -23323.6 -11.7682 6.27217 0.11 0.058631 0.0487404 7.24478 6.0757 231524 27.1328 38817 4.54905 24809 96129 21440863 3812157 0 0 3.84009e+08 18544.0 14 5987112 65598998 -1 12.9996 6.14541 -26165.8 -11.9996 0 0 128.48 -1 -1 3448.6 MiB 8.30 9.76557 8.27695 3448.6 MiB -1 39.20 + stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 105.89 vpr 1.15 GiB 35 739 0 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1206268 18 17 16969 16357 1 6288 780 39 29 1131 LAB auto 1055.9 MiB 58.67 84377 244832 62116 178083 4633 1170.7 MiB 9.36 0.15 7.65805 -46422.6 -6.65805 7.65805 0.01 0.0403174 0.0343915 3.27761 2.60777 119256 18.9777 28323 4.50716 18857 88786 20657004 3728094 0 0 2.05929e+07 18207.7 16 331560 3499109 -1 7.35046 7.35046 -45160 -6.35046 0 0 8.57 -1 -1 1170.7 MiB 7.33 5.31368 4.36758 1170.7 MiB -1 1.64 + stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 24.32 vpr 991.27 MiB 35 78 0 8 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1015056 18 17 2291 2142 1 1448 121 16 12 192 LAB M9K auto 952.9 MiB 5.78 10189 9390 1103 7334 953 991.3 MiB 0.56 0.01 5.3129 -4153.14 -4.3129 4.5918 0.00 0.00719423 0.00593688 0.266582 0.228623 14035 9.71280 3656 2.53010 3331 8155 2407464 497474 0 0 3.34790e+06 17437.0 10 54372 558374 -1 5.45077 4.46245 -3957.23 -4.45077 0 0 1.85 -1 -1 991.3 MiB 0.84 0.535245 0.473492 991.3 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_quick_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_quick_qor/config/golden_results.txt index d7048468870..82ffc857817 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_quick_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_quick_qor/config/golden_results.txt @@ -1,23 +1,23 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time -stratixiv_arch.timing.xml gsm_switch_stratixiv_arch_timing.blif common 3434.92 136 21492 0 1848 0 1 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 9760656 100 36 504627 490068 5 200916 23477 255 189 48195 M9K auto 700.76 -1 1504.23 11.74 8.0573 -1.40572e+06 -8.0573 5.6189 177.19 1.11051 0.713981 193.057 125.871 5385844 441201 1322987 933414169 132816309 0 0 8.91222e+08 18492.0 12 9.20679 6.19052 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sparcT2_core_stratixiv_arch_timing.blif common 3101.89 451 14725 0 260 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5492144 239 212 302755 300220 1 184812 15436 153 113 17289 LAB auto 720.50 -1 1616.14 9.31 10.5604 -686489 -9.56037 10.5604 74.77 0.872497 0.578117 133.503 89.1183 4841206 557658 2081616 1599598820 153094223 0 0 3.20293e+08 18525.8 65 10.8439 10.8439 -962235 -9.84391 0 0 295.90 247.633 179.457 246.21 -stratixiv_arch.timing.xml cholesky_bdti_stratixiv_arch_timing.blif common 2191.28 162 9680 132 600 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5522328 94 68 331744 255478 1 156536 10574 169 125 21125 DSP auto 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196307724 0 0 6.00287e+08 18530.2 43 10.8759 10.8759 -859659 -9.87586 0 0 300.88 195.6 151.617 643.04 -stratixiv_arch.timing.xml bitonic_mesh_stratixiv_arch_timing.blif common 3396.68 119 7239 85 1664 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 6841728 87 32 233978 190746 1 146198 9107 242 179 43318 M9K auto 559.97 -1 1127.28 6.90 12.1144 -1.51589e+06 -11.1144 12.1144 221.34 1.21887 0.860698 175.663 128.302 4588292 456078 1491126 1548811766 242407085 0 0 8.01751e+08 18508.5 18 12.7209 12.7209 -1.86107e+06 -11.7209 0 0 304.05 240.372 183.004 932.96 -stratixiv_arch.timing.xml segmentation_stratixiv_arch_timing.blif common 1763.17 441 6937 15 481 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 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4176.1 MiB 102.09 117.721 99.3918 4176.1 MiB -1 40.63 + stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 421.30 vpr 2.85 GiB 77 3136 89 136 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2991324 42 35 119888 86875 1 50816 3438 129 96 12384 DSP auto 1745.7 MiB 108.53 589279 3141815 1167038 1945807 28970 2921.2 MiB 122.40 1.04 7.38717 -81468.3 -6.38717 5.54912 0.07 0.387866 0.32584 48.8479 41.3623 766630 15.1010 160642 3.16430 100455 168766 108374381 28508729 0 0 2.28639e+08 18462.4 15 3593250 39165143 -1 7.60292 5.98464 -114944 -6.60292 0 0 77.84 -1 -1 2921.2 MiB 37.56 65.2582 56.1183 2921.2 MiB -1 19.09 + stratixiv_arch.timing.xml sparcT1_core_stratixiv_arch_timing.blif common 695.98 vpr 2.32 GiB 310 4015 1 128 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2437260 173 137 92814 91975 1 60525 4454 82 61 5002 LAB auto 1682.1 MiB 328.02 905799 3923864 1456413 2412431 55020 2002.6 MiB 208.23 1.73 9.26063 -594496 -8.26063 9.26063 0.04 0.361226 0.287081 41.9149 33.3166 1241316 20.5105 280369 4.63259 192705 660207 193204537 36029492 0 0 9.19872e+07 18390.1 17 1450842 15736794 -1 9.26352 9.26352 -654561 -8.26352 0 0 33.03 -1 -1 2227.7 MiB 64.37 59.3287 48.138 2002.6 MiB -1 7.27 + stratixiv_arch.timing.xml stereo_vision_stratixiv_arch_timing.blif common 369.28 vpr 2.83 GiB 506 3280 76 113 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2962964 172 334 127090 94090 3 61320 3975 129 96 12384 DSP auto 1700.4 MiB 92.28 509805 3655075 1361648 2244810 48617 2893.5 MiB 106.78 1.02 7.86325 -61457.1 -6.86325 3.46836 0.06 0.267265 0.217852 32.269 26.2483 592827 9.66870 127681 2.08241 120500 173662 60165583 13187056 0 0 2.28639e+08 18462.4 15 3593250 39165143 -1 7.51746 3.25652 -73809.5 -6.51746 0 0 72.77 -1 -1 2893.5 MiB 24.19 43.7993 36.2426 2893.5 MiB -1 18.65 + stratixiv_arch.timing.xml cholesky_mc_stratixiv_arch_timing.blif common 617.64 vpr 3.09 GiB 262 4762 59 444 16 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3240764 111 151 140214 108592 1 66275 5543 125 93 11625 M9K auto 1990.3 MiB 151.48 788106 6330929 2486828 3764499 79602 2999.8 MiB 232.35 1.87 6.96286 -206320 -5.96286 6.96286 0.07 0.500192 0.409213 65.7757 53.6456 1136243 17.1454 244932 3.69592 141963 302339 243323807 67066242 0 0 2.14511e+08 18452.6 16 3364308 36745094 -1 7.39694 7.39694 -298154 -6.39694 0 0 72.75 -1 -1 2999.8 MiB 72.42 87.4449 72.7019 2999.8 MiB -1 18.74 + stratixiv_arch.timing.xml directrf_stratixiv_arch_timing.blif common 12065.34 vpr 19.50 GiB 319 61499 240 2535 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 20448212 62 257 1374456 930989 2 664817 64593 317 235 74495 M9K auto 11400.2 MiB 1468.30 10830328 216389546 87578779 128174025 636742 16624.7 MiB 9036.53 60.52 9.32838 -1.81224e+06 -8.32838 8.21814 0.64 3.49044 2.85081 631.297 518.226 11749927 17.6766 2324437 3.49689 1382377 2282905 1372376586 322363776 0 0 1.38707e+09 18619.7 14 21381670 236483135 -1 9.87707 8.61989 -2.31232e+06 -8.87707 0 0 423.56 -1 -1 16912.8 MiB 478.20 764.49 633.315 16624.7 MiB -1 172.48 + stratixiv_arch.timing.xml bitcoin_miner_stratixiv_arch_timing.blif common 10920.08 vpr 14.34 GiB 385 35914 0 1331 0 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 15035900 353 32 1446409 1087537 2 802897 37631 236 175 41300 LAB auto 8407.9 MiB 1399.69 8069197 81976111 30515078 50803021 658012 10893.4 MiB 8471.96 46.28 8.82853 -897986 -7.82853 8.82853 0.36 2.98543 2.55333 437.471 361.343 9365241 11.6644 2162474 2.69335 1742182 2571548 800029867 152528004 0 0 7.64522e+08 18511.4 17 11894042 131060469 -1 10.6871 10.6871 -1.2059e+06 -9.68713 0 0 248.62 -1 -1 12829.4 MiB 335.71 579.023 482.876 10893.4 MiB -1 83.17 + stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 6630.33 vpr 19.49 GiB 373 16678 116 5040 16 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 20438700 178 195 663067 568001 2 406083 22223 430 319 137170 M9K auto 5700.6 MiB 1488.67 15354107 51862695 21830000 29930794 101901 19959.7 MiB 3209.27 16.23 26.6172 -3.23472e+06 -25.6172 8.81163 0.75 2.90058 2.38659 503.078 413.353 16386901 40.3553 3026953 7.45434 917037 1739755 1410990275 326533180 0 0 2.57820e+09 18795.6 12 39390806 435738327 -1 24.6154 10.5061 -5.75347e+06 -23.6154 0 0 818.19 -1 -1 19959.7 MiB 464.81 608.245 504.614 19959.7 MiB -1 324.73 + stratixiv_arch.timing.xml sparcT1_chip2_stratixiv_arch_timing.blif common 8193.12 vpr 12.67 GiB 1891 33747 3 506 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 13287440 815 1076 764693 760412 1423 413569 36147 280 207 57960 io auto 6871.9 MiB 2170.60 6321041 78292272 33005860 44758558 527854 11353.3 MiB 4815.14 29.77 17.7516 -4.16163e+06 -16.7516 4.89119 0.49 2.87248 2.26378 416.975 332.994 7527876 18.5260 1630241 4.01199 988164 3143557 705151553 127852079 0 0 1.07374e+09 18525.6 21 16684552 184042692 -1 17.843 5.02145 -4.80984e+06 -16.843 0 0 356.76 -1 -1 11473.0 MiB 368.46 581.186 470.324 11353.3 MiB -1 125.64 + stratixiv_arch.timing.xml LU_Network_stratixiv_arch_timing.blif common 6013.51 vpr 11.23 GiB 399 31093 112 1175 0 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 11773592 85 185 721554 630079 28 405002 32781 220 163 35860 LAB auto 6475.5 MiB 1002.80 5178404 84458444 33598600 50279421 580423 8860.1 MiB 4172.19 24.46 8.14669 -688925 -7.14669 5.20564 0.32 2.89777 2.30021 490.741 391.133 6249071 15.4486 1362456 3.36819 825418 1759906 637573300 144402801 0 0 6.64232e+08 18522.9 14 10351778 113707977 -1 8.89873 5.39961 -915798 -7.89873 0 0 217.47 -1 -1 10398.8 MiB 253.99 604.773 489.305 8860.1 MiB -1 69.95 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph/config/golden_results.txt index 94c339dadc7..2bd7b64568f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph/config/golden_results.txt @@ -1,6 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 15.44 0.32 30784 3 1.53 -1 -1 39924 -1 -1 100 214 0 8 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 72096 214 305 2963 2869 1 1462 627 19 19 361 io auto 1.29 11329 1.92 0.02 4.35337 -2516.86 -4.35337 4.35337 0.06 0.00328107 0.00285296 0.738956 0.625763 20096 -1 -1 -1 -1 1.72706e+07 8.5574e+06 2.90560e+06 8048.76 17 4.76636 4.76636 -2957.47 -4.76636 0 0 0.58 0.953726 0.825808 1.10 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 15.47 0.42 30800 3 1.31 -1 -1 39976 -1 -1 111 214 0 8 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 70728 214 305 2963 2869 1 1440 638 19 19 361 io auto 2.27 10427 1.32 0.01 4.36814 -2472.84 -4.36814 4.36814 0.05 0.00317149 0.00278315 0.443043 0.379506 17186 -1 -1 -1 -1 1.72706e+07 9.15023e+06 2.71656e+06 7525.11 12 4.72208 4.72208 -2856.74 -4.72208 0 0 0.43 0.616587 0.542339 0.70 - k6_frac_N10_mem32K_40nm.xml raygentop.v common 17.49 0.42 31904 8 1.69 -1 -1 40332 -1 -1 104 214 0 9 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 68708 214 305 2625 2741 1 1440 632 22 22 484 mult_36 auto 2.50 11461 1.44 0.02 4.30553 -2458.71 -4.30553 4.30553 0.09 0.00294167 0.00252875 0.478138 0.403453 18517 -1 -1 -1 -1 2.50602e+07 9.16898e+06 3.71564e+06 7676.94 12 5.02187 5.02187 -2941.43 -5.02187 0 0 0.53 0.630845 0.545873 0.89 - k6_N10_mem32K_40nm.xml raygentop.v common 17.74 0.33 31864 8 1.76 -1 -1 40228 -1 -1 164 214 0 9 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 65808 214 305 2625 2741 1 1482 692 22 22 484 mult_36 auto 0.65 12264 1.70 0.02 4.21675 -2419.09 -4.21675 4.21675 0.14 0.00304558 0.00252583 0.51155 0.423932 18017 -1 -1 -1 -1 2.50602e+07 1.24026e+07 3.52243e+06 7277.74 49 4.898 4.898 -2810.42 -4.898 0 0 2.32 0.867474 0.743958 1.39 - hard_fpu_arch_timing.xml raygentop.v common 159.25 0.60 66344 38 100.76 -1 -1 67464 -1 -1 2217 211 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 229228 211 305 9491 9796 1 6956 2733 53 53 2809 clb auto 1.57 68376 10.58 0.09 21.0864 -5585.28 -21.0864 21.0864 0.42 0.0102485 0.00869648 1.45593 1.02314 106554 -1 -1 -1 -1 5.87942e+06 5.0818e+06 1.13971e+07 4057.33 27 22.8705 22.8705 -6341.42 -22.8705 -0.0851 -0.0851 3.38 2.35962 1.78429 4.77 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 18.10 vpr 84.26 MiB 0.49 31568 -1 -1 3 1.10 -1 -1 40400 -1 -1 119 214 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 86280 214 305 2963 2869 1 1465 646 19 19 361 io auto 42.9 MiB 2.38 11473 279746 97784 164344 17618 84.3 MiB 2.03 0.03 4.50048 -2595.18 -4.50048 4.50048 0.00 0.00847397 0.00785036 0.847998 0.78148 -1 -1 -1 -1 19540 13.4666 5175 3.56651 4591 11814 1372016 333143 1.72706e+07 9.58139e+06 2.90560e+06 8048.76 12 52798 501983 -1 4.7575 4.7575 -2835.11 -4.7575 0 0 0.44 -1 -1 84.3 MiB 0.59 1.16192 1.07597 84.3 MiB -1 0.10 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 16.87 vpr 84.21 MiB 0.49 31612 -1 -1 3 1.08 -1 -1 40360 -1 -1 123 214 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 86232 214 305 2963 2869 1 1444 650 19 19 361 io auto 43.2 MiB 2.84 11413 231398 76618 140983 13797 84.2 MiB 1.01 0.02 4.67106 -2660.25 -4.67106 4.67106 0.00 0.0042158 0.00385403 0.364929 0.335739 -1 -1 -1 -1 17576 12.2909 4673 3.26783 3635 8404 916352 219992 1.72706e+07 9.79696e+06 2.71656e+06 7525.11 13 49483 447175 -1 4.79628 4.79628 -2823.47 -4.79628 0 0 0.33 -1 -1 84.2 MiB 0.32 0.56686 0.527395 84.2 MiB -1 0.09 + k6_frac_N10_mem32K_40nm.xml raygentop.v common 19.25 vpr 79.38 MiB 0.51 32832 -1 -1 8 1.59 -1 -1 40644 -1 -1 117 214 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81284 214 305 2625 2741 1 1438 645 22 22 484 mult_36 auto 38.5 MiB 2.62 11780 287500 97684 170577 19239 79.4 MiB 1.98 0.03 4.70477 -2668 -4.70477 4.70477 0.00 0.00775198 0.00716962 0.832076 0.767666 -1 -1 -1 -1 18108 12.7074 4758 3.33895 3393 7424 854677 202496 2.50602e+07 9.8696e+06 3.71564e+06 7676.94 15 65910 614443 -1 4.88861 4.88861 -2835.89 -4.88861 0 0 0.57 -1 -1 79.4 MiB 0.53 1.15898 1.07234 79.4 MiB -1 0.13 + k6_N10_mem32K_40nm.xml raygentop.v common 16.82 vpr 78.59 MiB 0.51 32832 -1 -1 8 1.69 -1 -1 40844 -1 -1 198 214 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80472 214 305 2625 2741 1 1415 726 22 22 484 mult_36 auto 37.4 MiB 1.14 12153 264867 85581 162230 17056 78.6 MiB 1.77 0.02 4.91361 -2793.64 -4.91361 4.91361 0.00 0.00766742 0.0070794 0.656327 0.603669 -1 -1 -1 -1 16547 11.8024 4369 3.11626 6679 17662 2743548 596669 2.50602e+07 1.4235e+07 3.52243e+06 7277.74 26 57210 572443 -1 4.90022 4.90022 -2862.69 -4.90022 0 0 0.55 -1 -1 78.6 MiB 0.94 1.10615 1.01763 78.6 MiB -1 0.12 + hard_fpu_arch_timing.xml raygentop.v common 138.65 vpr 231.80 MiB 0.99 70388 -1 -1 38 69.46 -1 -1 68188 -1 -1 2403 211 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 237368 211 305 9491 9796 1 6660 2919 55 55 3025 clb auto 80.5 MiB 2.31 66631 1817043 654938 1126978 35127 231.8 MiB 13.17 0.11 26.0917 -6594.81 -26.0917 26.0917 0.00 0.0168338 0.0140529 2.38382 2.05463 -1 -1 -1 -1 110311 16.5956 28136 4.23289 74198 194987 16052984 1871492 6.31033e+06 5.50811e+06 1.22764e+07 4058.32 35 255054 2544855 -1 23.6419 23.6419 -6371.61 -23.6419 -0.0851 -0.0851 2.53 -1 -1 231.8 MiB 5.25 4.12195 3.55168 231.8 MiB -1 0.79 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_bidir/config/golden_results.txt index 36fa7bb0a1b..5f9d2a62a25 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_bidir/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - k4_n4_v7_bidir.xml dsip.blif common 27.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 390 229 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 118552 229 197 1815 2012 1 1190 816 29 29 841 io auto 0.33 11648 1.49 0.02 7.41386 -1808.21 -7.41386 7.41386 0.61 0.0021178 0.0016946 0.281919 0.225954 15856 -1 -1 -1 -1 2.187e+07 1.17e+07 -1 -1 20 9.24582 9.24582 -2352.55 -9.24582 0 0 0.83 0.391481 0.321957 5.69 - k4_n4_v7_bidir.xml elliptic.blif common 48.58 -1 -1 -1 -1 -1 -1 -1 -1 -1 996 131 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 169988 131 114 4855 4969 1 2150 1241 34 34 1156 clb auto 0.88 31542 3.21 0.03 21.1193 -11571.9 -21.1193 21.1193 0.90 0.00449081 0.00368456 0.662064 0.449287 40462 -1 -1 -1 -1 3.072e+07 2.988e+07 -1 -1 20 26.9983 26.9983 -14687.8 -26.9983 0 0 1.69 1.0392 0.770433 7.04 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k4_n4_v7_bidir.xml dsip.blif common 24.15 vpr 129.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 443 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 132104 229 197 1815 2012 1 1190 869 29 29 841 io auto 28.1 MiB 0.38 11808 386354 130262 246701 9391 129.0 MiB 1.99 0.02 8.26026 -2002.89 -8.26026 8.26026 0.00 0.00522947 0.00475426 0.50234 0.458325 -1 -1 -1 -1 14837 12.4786 3857 3.24390 5280 18595 4288015 314127 2.187e+07 1.329e+07 -1 -1 12 141714 3348831 -1 10.3649 10.3649 -2489.23 -10.3649 0 0 1.93 -1 -1 129.0 MiB 0.71 0.66274 0.604038 129.0 MiB -1 0.64 + k4_n4_v7_bidir.xml elliptic.blif common 39.80 vpr 178.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1023 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 182672 131 114 4855 4969 1 2112 1268 34 34 1156 clb auto 44.4 MiB 0.83 31400 563788 196591 359179 8018 178.4 MiB 3.77 0.04 22.2892 -11723.6 -22.2892 22.2892 0.00 0.0101629 0.00906485 0.918798 0.79034 -1 -1 -1 -1 40056 18.9749 10269 4.86452 9570 44105 8008892 526134 3.072e+07 3.069e+07 -1 -1 19 194754 4643496 -1 27.7541 27.7541 -14616.1 -27.7541 0 0 2.78 -1 -1 178.4 MiB 1.65 1.38449 1.19731 178.4 MiB -1 0.94 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_complex_switch/config/golden_results.txt index a3bec08d847..ab193c4d4af 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_complex_switch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_complex_switch/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 29.30 0.39 31692 12 1.62 -1 -1 37060 -1 -1 238 214 0 9 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 91116 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 0.46 16418 1.91 0.02 3.92422 -1914.18 -3.92422 3.92422 0.10 0.00303059 0.00265402 0.424989 0.354567 24730 -1 -1 -1 -1 3.88769e+06 1.9974e+06 7.17610e+06 10615.5 17 4.06116 4.06116 -2255.58 -4.06116 0 0 1.44 0.597094 0.511983 5.30 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 24.33 vpr 90.75 MiB 0.51 32872 -1 -1 12 1.55 -1 -1 40880 -1 -1 238 214 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 92924 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 35.0 MiB 0.55 17879 291515 96968 176018 18529 90.7 MiB 2.29 0.03 4.04097 -2026.17 -4.04097 4.04097 0.00 0.00789147 0.00729898 0.68601 0.631189 -1 -1 -1 -1 25655 11.8335 11525 5.31596 7010 22783 3120920 787237 3.88769e+06 1.9974e+06 7.17610e+06 10615.5 17 154908 1423382 -1 4.23901 4.23901 -2367.29 -4.23901 0 0 2.25 -1 -1 90.7 MiB 0.90 1.00021 0.919765 90.7 MiB -1 0.66 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_error_check/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_error_check/config/golden_results.txt index 7e7ccf79b1f..d6391fd6791 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_error_check/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_error_check/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 12.84 0.38 31704 12 2.23 -1 -1 37112 -1 -1 238 214 0 9 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 74736 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 0.66 16553 2.42 0.03 3.96803 -1941.86 -3.96803 3.96803 0.09 0.0050075 0.00438498 0.553215 0.461746 25791 -1 -1 -1 -1 3.88769e+06 1.9974e+06 3.89335e+06 5759.39 17 4.2505 4.2505 -2428.8 -4.2505 0 0 1.81 0.756122 0.644202 2.88 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 10.04 vpr 76.59 MiB 0.56 32824 -1 -1 12 1.57 -1 -1 41056 -1 -1 238 214 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78432 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 35.0 MiB 0.55 18203 298521 99577 180379 18565 76.6 MiB 2.21 0.03 4.02384 -2044.4 -4.02384 4.02384 0.00 0.0078973 0.00729681 0.668637 0.615335 -1 -1 -1 -1 27105 12.5023 12496 5.76384 9844 29663 3742250 1056449 3.88769e+06 1.9974e+06 3.89335e+06 5759.39 18 97004 733416 -1 4.47172 4.47172 -2442.55 -4.47172 0 0 1.15 -1 -1 76.6 MiB 1.23 1.03037 0.946995 76.6 MiB -1 0.36 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_titan/config/golden_results.txt index 067a8cc5230..d3376c5e4de 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 1504.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 2859008 42 35 119888 86875 1 51143 3418 129 96 12384 DSP auto 85.58 583323 119.39 0.71 7.89477 -209772 -7.89477 7.89477 208.83 0.200591 0.17182 32.4665 25.7145 744976 -1 -1 -1 -1 0 0 2.28642e+08 18462.7 33 8.25962 8.25962 -264487 -8.25962 0 0 57.37 50.95 41.9616 169.27 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 993.75 vpr 2.85 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2990508 42 35 119888 86875 1 50848 3434 129 96 12384 DSP auto 1744.8 MiB 110.48 593082 3188765 1210302 1953134 25329 2920.4 MiB 131.36 1.01 7.82707 -223897 -7.82707 7.82707 0.07 0.35368 0.316469 47.6901 41.67 -1 -1 -1 -1 760648 14.9737 161961 3.18827 105791 178983 117012215 31658104 0 0 2.28639e+08 18462.4 15 3593250 39165143 -1 8.06159 8.06159 -257707 -8.06159 0 0 77.71 -1 -1 2920.4 MiB 39.46 63.6187 56.0573 2920.4 MiB -1 21.95 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt index 79387b20d65..9d333670603 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt @@ -1,41 +1,41 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_n4_v7_bidir.xml alu4.blif common 14.12 vpr 67.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 477 14 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68808 14 8 1536 1544 0 1088 499 24 24 576 clb auto 26.9 MiB 0.35 13713 125113 37636 85702 1775 67.2 MiB 0.83 0.01 14.0421 -101.788 -14.0421 nan 0.89 0.00337182 0.00294136 0.228232 0.201212 28 19990 27 1.452e+07 1.431e+07 -1 -1 8.35 1.31835 1.12022 21174 279108 -1 19228 18 7062 27087 2139856 196285 17.1451 nan -119.753 -17.1451 0 0 -1 -1 0.37 0.58 0.16 -1 -1 0.37 0.149382 0.130325 -k4_n4_v7_bidir.xml apex2.blif common 20.08 vpr 69.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 598 38 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71168 38 3 1916 1919 0 1508 639 27 27 729 clb auto 29.3 MiB 0.47 20032 176703 52353 120171 4179 69.5 MiB 1.23 0.02 17.5139 -50.2777 -17.5139 nan 1.17 0.00472981 0.00411722 0.317696 0.278113 31 29578 36 1.875e+07 1.794e+07 -1 -1 12.05 1.72453 1.47135 28210 394495 -1 28636 22 10688 37557 3476301 294242 20.8295 nan -58.5593 -20.8295 0 0 -1 -1 0.56 1.01 0.23 -1 -1 0.56 0.253299 0.22082 -k4_n4_v7_bidir.xml apex4.blif common 15.04 vpr 65.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 410 9 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66588 9 19 1271 1290 0 989 438 23 23 529 clb auto 25.5 MiB 0.27 13508 95172 26074 67665 1433 65.0 MiB 0.65 0.01 13.1269 -216.571 -13.1269 nan 0.83 0.00276239 0.0024392 0.1738 0.155352 31 20275 34 1.323e+07 1.23e+07 -1 -1 9.83 1.0323 0.884588 20514 283063 -1 18947 16 6713 24480 2299733 193456 16.0497 nan -259.266 -16.0497 0 0 -1 -1 0.39 0.53 0.16 -1 -1 0.39 0.116433 0.102846 -k4_n4_v7_bidir.xml bigkey.blif common 19.30 vpr 69.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 456 229 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71668 229 197 2152 2349 1 1587 882 29 29 841 io auto 29.8 MiB 0.34 12720 440594 137247 291517 11830 70.0 MiB 2.20 0.02 8.05109 -1841.77 -8.05109 8.05109 1.37 0.00589079 0.00536855 0.626379 0.566795 18 20694 46 2.187e+07 1.368e+07 -1 -1 10.54 2.27299 2.02358 25794 279159 -1 18007 20 8342 23483 1514225 162064 9.13231 9.13231 -2338.69 -9.13231 0 0 -1 -1 0.39 0.61 0.17 -1 -1 0.39 0.250982 0.22507 -k4_n4_v7_bidir.xml clma.blif common 125.73 vpr 199.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2521 62 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 204696 62 82 8460 8542 1 6346 2665 53 53 2809 clb auto 74.6 MiB 2.08 106112 1720282 687942 1019943 12397 191.1 MiB 12.56 0.13 27.7798 -1475.05 -27.7798 27.7798 5.67 0.0212825 0.0174879 2.07784 1.7299 39 139827 30 7.803e+07 7.563e+07 -1 -1 77.34 8.16732 6.70717 121914 1953961 -1 145653 37 50338 174644 40465788 3496071 37.5154 37.5154 -1994.17 -37.5154 0 0 -1 -1 3.29 8.98 1.16 -1 -1 3.29 1.60084 1.35094 -k4_n4_v7_bidir.xml des.blif common 21.96 vpr 73.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 449 256 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75736 256 245 1847 2092 0 1443 950 34 34 1156 io auto 28.6 MiB 0.43 15858 337046 106006 219615 11425 74.0 MiB 1.69 0.02 13.6482 -2283.71 -13.6482 nan 2.03 0.00653534 0.00597695 0.503268 0.461334 18 23829 44 3.072e+07 1.347e+07 -1 -1 11.46 2.34979 2.13492 35364 387024 -1 21475 27 8540 28313 2203704 220439 16.6899 nan -2838.96 -16.6899 0 0 -1 -1 0.56 0.82 0.23 -1 -1 0.56 0.360996 0.330838 -k4_n4_v7_bidir.xml diffeq.blif common 12.81 vpr 67.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 415 64 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69116 64 39 1935 1974 1 1102 518 23 23 529 clb auto 27.8 MiB 0.35 9992 137732 37830 95961 3941 67.5 MiB 0.95 0.01 13.4033 -2671.54 -13.4033 13.4033 0.80 0.00428173 0.00383691 0.312705 0.277181 24 14332 21 1.323e+07 1.245e+07 -1 -1 7.02 1.61062 1.38241 18402 227975 -1 13634 22 6342 21307 1309693 133684 15.9009 15.9009 -3236.59 -15.9009 0 0 -1 -1 0.30 0.50 0.13 -1 -1 0.30 0.20143 0.175765 -k4_n4_v7_bidir.xml dsip.blif common 17.77 vpr 67.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 390 229 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68900 229 197 1815 2012 1 1190 816 29 29 841 io auto 27.5 MiB 0.32 11545 347617 108721 229249 9647 67.3 MiB 1.74 0.02 7.21771 -1868.83 -7.21771 7.21771 1.36 0.00565774 0.00516606 0.524959 0.478887 18 18641 50 2.187e+07 1.17e+07 -1 -1 9.76 2.03171 1.82626 25794 279159 -1 15915 19 6571 20190 1355499 141050 8.71824 8.71824 -2334.27 -8.71824 0 0 -1 -1 0.39 0.53 0.17 -1 -1 0.39 0.218562 0.197453 -k4_n4_v7_bidir.xml elliptic.blif common 55.36 vpr 90.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1000 131 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93164 131 114 4855 4969 1 2139 1245 34 34 1156 clb auto 44.4 MiB 0.80 31454 550235 189587 353717 6931 90.2 MiB 3.44 0.04 23.2801 -11982.4 -23.2801 23.2801 1.99 0.0102012 0.00912611 0.93124 0.796503 29 50282 41 3.072e+07 3e+07 -1 -1 39.75 4.26668 3.61139 43448 604980 -1 46002 25 13205 58637 9554007 846071 38.8565 38.8565 -19809.8 -38.8565 0 0 -1 -1 0.87 2.29 0.35 -1 -1 0.87 0.550161 0.477667 -k4_n4_v7_bidir.xml ex1010.blif common 70.88 vpr 117.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1507 10 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 120624 10 10 4608 4618 0 3617 1527 41 41 1681 clb auto 49.0 MiB 1.01 44970 713436 251975 459721 1740 117.8 MiB 5.24 0.06 23.5124 -229.462 -23.5124 nan 3.18 0.0097988 0.00855656 0.894426 0.754306 28 68638 30 4.563e+07 4.521e+07 -1 -1 49.13 4.21383 3.49296 61362 838935 -1 63940 21 25222 100656 7392341 708511 28.5457 nan -270.488 -28.5457 0 0 -1 -1 1.32 2.31 0.49 -1 -1 1.32 0.568954 0.493491 -k4_n4_v7_bidir.xml ex5p.blif common 10.49 vpr 63.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 342 8 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65140 8 63 1072 1135 0 906 413 21 21 441 clb auto 24.3 MiB 0.26 11449 84948 23521 59664 1763 63.6 MiB 0.57 0.01 12.8622 -575.489 -12.8622 nan 0.65 0.0025827 0.00230286 0.159252 0.143541 35 17128 25 1.083e+07 1.026e+07 -1 -1 5.53 0.949583 0.821185 18442 269153 -1 17835 36 8694 28272 4470817 400190 22.7431 nan -871.031 -22.7431 0 0 -1 -1 0.35 0.95 0.15 -1 -1 0.35 0.19761 0.170925 -k4_n4_v7_bidir.xml frisc.blif common 42.63 vpr 94.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1051 20 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 96356 20 116 4445 4561 1 2326 1187 35 35 1225 clb auto 43.5 MiB 0.91 37678 522593 180255 332319 10019 91.3 MiB 3.77 0.04 26.7351 -13400.3 -26.7351 26.7351 2.15 0.0120194 0.0108773 1.0849 0.940114 35 54338 28 3.267e+07 3.153e+07 -1 -1 24.33 3.94847 3.3672 50922 772933 -1 56811 45 18725 83358 16216109 1534592 31.802 31.802 -18151.6 -31.802 0 0 -1 -1 1.17 3.76 0.44 -1 -1 1.17 0.873991 0.748271 -k4_n4_v7_bidir.xml misex3.blif common 18.72 vpr 65.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 431 14 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 67172 14 14 1411 1425 0 1079 459 23 23 529 clb auto 26.0 MiB 0.34 13374 101292 28145 71403 1744 65.6 MiB 0.68 0.01 13.1746 -165.157 -13.1746 nan 0.79 0.00303589 0.00266696 0.186267 0.165347 29 21582 50 1.323e+07 1.293e+07 -1 -1 13.16 1.49464 1.27631 19986 270173 -1 20352 22 8774 29285 3704651 332778 24.3868 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vpr 63.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 367 8 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65236 8 63 1072 1135 0 898 438 22 22 484 clb auto 24.3 MiB 0.28 11915 106806 31455 73557 1794 63.7 MiB 0.76 0.01 16.2558 -718.217 -16.2558 nan 0.48 0.00266047 0.00239417 0.186827 0.16858 -1 -1 -1 -1 24 13413 30 1.2e+07 1.101e+07 -1 -1 18.57 1.14807 0.989575 36000 257712 -1 11900 15 6787 23733 1853955 288518 16.2529 nan -726.803 -16.2529 0 0 -1 -1 0.05 0.53 0.19 -1 -1 0.05 0.103498 0.0915159 + k4_n4_v7_l1_bidir.xml frisc.blif common 38.93 vpr 121.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1094 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 123968 20 116 4445 4561 1 2290 1230 36 36 1296 clb auto 44.0 MiB 1.00 38255 580886 202911 367450 10525 121.0 MiB 4.07 0.05 29.223 -16576.9 -29.223 29.223 1.13 0.0106484 0.00904003 0.940065 0.801656 -1 -1 -1 -1 26 40614 39 3.468e+07 3.282e+07 -1 -1 24.94 2.98417 2.53653 104992 763300 -1 37284 18 13336 60167 5347576 900846 28.6821 28.6821 -16996 -28.6821 0 0 -1 -1 0.20 1.82 0.58 -1 -1 0.20 0.419427 0.365252 + k4_n4_v7_l1_bidir.xml misex3.blif common 45.92 vpr 66.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 450 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67696 14 14 1411 1425 0 1056 478 24 24 576 clb auto 26.5 MiB 0.37 13799 121898 36530 83432 1936 66.1 MiB 0.90 0.01 18.1166 -222.755 -18.1166 nan 0.60 0.00309451 0.00272996 0.216068 0.191921 -1 -1 -1 -1 21 15917 38 1.452e+07 1.35e+07 -1 -1 40.79 1.44479 1.22595 39160 271852 -1 13861 19 6925 26912 1892268 324238 17.8372 nan -222.89 -17.8372 0 0 -1 -1 0.06 0.64 0.20 -1 -1 0.06 0.144778 0.126476 + k4_n4_v7_l1_bidir.xml pdc.blif common 185.86 vpr 161.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1606 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 165376 16 40 4591 4631 0 3616 1662 43 43 1849 clb auto 50.5 MiB 1.46 71388 995502 386267 603819 5416 155.7 MiB 7.79 0.07 36.0567 -1232.66 -36.0567 nan 2.17 0.0114444 0.00941235 1.37422 1.1363 -1 -1 -1 -1 34 83956 48 5.043e+07 4.818e+07 -1 -1 161.61 5.08837 4.17381 185730 1416087 -1 74292 16 24740 103095 11970321 1866116 34.9964 nan -1210.26 -34.9964 0 0 -1 -1 0.37 3.70 1.22 -1 -1 0.37 0.489235 0.420817 + k4_n4_v7_l1_bidir.xml s298.blif common 12.12 vpr 70.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 573 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71732 4 6 1942 1948 1 1167 583 26 26 676 clb auto 29.8 MiB 0.37 13721 168529 51547 115716 1266 70.1 MiB 0.87 0.01 26.8992 -206.444 -26.8992 26.8992 0.51 0.00299887 0.00257425 0.223433 0.19287 -1 -1 -1 -1 17 15103 41 1.728e+07 1.719e+07 -1 -1 6.67 0.869853 0.739775 39072 254696 -1 13708 17 7890 40380 2928639 390491 25.7904 25.7904 -205.684 -25.7904 0 0 -1 -1 0.06 0.93 0.19 -1 -1 0.06 0.19636 0.172164 + k4_n4_v7_l1_bidir.xml s38417.blif common 85.43 vpr 189.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1852 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 194024 29 106 7534 7640 1 4623 1987 46 46 2116 clb auto 62.1 MiB 1.48 45682 1150699 423694 711314 15691 189.5 MiB 8.94 0.10 24.016 -14000.6 -24.016 24.016 2.52 0.0168312 0.0139048 1.65489 1.37293 -1 -1 -1 -1 16 41981 27 5.808e+07 5.556e+07 -1 -1 61.09 6.8711 5.59216 118272 756192 -1 39731 15 23886 81328 4350389 861432 23.6137 23.6137 -14728 -23.6137 0 0 -1 -1 0.21 2.06 0.61 -1 -1 0.21 0.672518 0.576412 + k4_n4_v7_l1_bidir.xml s38584.1.blif common 89.69 vpr 183.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1787 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 187676 38 304 7475 7779 1 4320 2129 45 45 2025 clb auto 61.8 MiB 1.45 43799 1343749 517594 801490 24665 183.3 MiB 9.55 0.12 21.0587 -13121.7 -21.0587 21.0587 2.33 0.0205892 0.0168564 1.8726 1.54631 -1 -1 -1 -1 16 39654 47 5.547e+07 5.361e+07 -1 -1 65.95 7.05965 5.7985 113090 722879 -1 37482 13 19902 66283 3641519 680597 20.2436 20.2436 -13770 -20.2436 0 0 -1 -1 0.19 1.67 0.56 -1 -1 0.19 0.582155 0.503652 + k4_n4_v7_l1_bidir.xml seq.blif common 39.04 vpr 69.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 567 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71060 41 35 1791 1826 0 1347 643 26 26 676 clb auto 28.8 MiB 0.45 18608 203145 65187 132320 5638 69.4 MiB 1.45 0.02 18.1385 -520.265 -18.1385 nan 0.69 0.00440251 0.00379688 0.341235 0.296573 -1 -1 -1 -1 24 20201 48 1.728e+07 1.701e+07 -1 -1 32.66 1.86519 1.57725 51072 366016 -1 19098 15 8908 34158 2699342 394310 17.881 nan -530.81 -17.881 0 0 -1 -1 0.08 0.84 0.27 -1 -1 0.08 0.169259 0.148746 + k4_n4_v7_l1_bidir.xml spla.blif common 55.44 vpr 130.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1282 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 133644 16 46 3706 3752 0 2852 1344 38 38 1444 clb auto 43.3 MiB 0.97 48851 705674 261242 438237 6195 130.4 MiB 5.28 0.05 28.2789 -928.469 -28.2789 nan 1.62 0.00915224 0.00762446 0.960488 0.808085 -1 -1 -1 -1 30 55651 36 3.888e+07 3.846e+07 -1 -1 38.42 2.90573 2.41614 133344 1000208 -1 49871 15 17906 78246 6885546 1014380 27.1504 nan -941.372 -27.1504 0 0 -1 -1 0.25 2.26 0.77 -1 -1 0.25 0.363869 0.316143 + k4_n4_v7_l1_bidir.xml tseng.blif common 11.07 vpr 64.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 292 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65992 52 122 1483 1605 1 725 466 20 20 400 clb auto 25.0 MiB 0.25 6135 112438 30480 78177 3781 64.4 MiB 0.73 0.01 11.1777 -2780.46 -11.1777 11.1777 0.38 0.00330812 0.00294725 0.224125 0.201235 -1 -1 -1 -1 14 6150 30 9.72e+06 8.76e+06 -1 -1 7.57 1.13613 0.985613 19872 120996 -1 5573 18 4232 15969 711167 147306 11.3812 11.3812 -3151.62 -11.3812 0 0 -1 -1 0.03 0.33 0.09 -1 -1 0.03 0.136984 0.120602 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_func_formal/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_func_formal/config/golden_results.txt index a64f0a882d0..9878ca23cf5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_func_formal/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_func_formal/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time placement_technique reward uniform_percentage median_percentage wmedian_percentage wcent_percentage fr_percentage critUni_percentage centroid_percentage - k6_frac_N10_40nm.xml sha.v common 2075.74 0.69 36476 20 506.72 -1 -1 95572 -1 -1 208 38 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 75108 38 36 3404 3440 1 1290 282 17 17 289 clb auto 1.64 12508 1.22 0.01 11.3503 -3905.76 -11.3503 11.3503 0.02 0.00324856 0.00264942 0.47841 0.349287 -1 17462 12 1.21262e+07 1.121e+07 3.33009e+06 11522.8 0.29 0.692138 0.542275 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml stereovision3.v common 1.42 0.05 8820 4 0.11 -1 -1 33040 -1 -1 13 11 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 25032 23 30 262 304 2 110 66 6 6 36 clb auto 0.09 358 0.09 0.00 2.24318 -154.283 -2.24318 2.0857 0.00 0.000283319 0.000227979 0.0465577 0.036372 -1 397 9 862304 700622 300248. 8340.23 0.02 0.0593364 0.0478995 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml sha.v common 1573.18 abc 94.10 MiB 2.09 38248 -1 -1 20 467.44 -1 -1 96356 -1 -1 207 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82452 38 36 3404 3440 1 1294 281 17 17 289 clb auto 38.8 MiB 2.28 12837 53641 12833 37659 3149 80.5 MiB 1.12 0.02 13.5016 -4515.69 -13.5016 13.5016 0.00 0.00752789 0.00668401 0.495491 0.4378 -1 -1 -1 -1 -1 17934 16 1.21262e+07 1.11561e+07 3.33009e+06 11522.8 0.50 0.863052 0.768227 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml stereovision3.v common 1.63 vpr 58.65 MiB 0.08 9400 -1 -1 4 0.15 -1 -1 33352 -1 -1 13 11 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 60056 23 30 262 304 2 110 66 6 6 36 clb auto 19.5 MiB 0.09 409 2593 543 1856 194 58.6 MiB 0.02 0.00 2.55648 -171.328 -2.55648 2.31607 0.00 0.00037611 0.000333951 0.0105184 0.00953081 -1 -1 -1 -1 -1 426 9 862304 700622 300248. 8340.23 0.02 0.0265046 0.024223 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_multiclock_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_multiclock_mcnc/config/golden_results.txt index 76aa77f8ebe..f952fd79e3d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_multiclock_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_multiclock_mcnc/config/golden_results.txt @@ -1,11 +1,11 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml bigkey.blif common 15.50 vpr 63.39 MiB -1 -1 -1 -1 3 0.37 -1 -1 34844 -1 -1 53 229 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64912 229 197 1023 1220 1 510 479 16 16 256 io auto 24.2 MiB 0.27 3412 154065 46239 98678 9148 63.4 MiB 0.95 0.01 2.41239 -578.515 -2.41239 2.41239 0.79 0.00631748 0.00590554 0.537724 0.50284 34 6563 36 1.05632e+07 2.85638e+06 613832. 2397.78 10.54 3.12398 2.91529 24564 122629 -1 5999 13 1330 2398 156004 35692 2.69369 2.69369 -639.318 -2.69369 0 0 751777. 2936.63 0.21 0.25 0.16 -1 -1 0.21 0.197289 0.185691 -k6_frac_N10_40nm.xml clma.blif common 8.18 vpr 60.61 MiB -1 -1 -1 -1 7 2.28 -1 -1 39892 -1 -1 77 36 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62060 36 82 542 624 1 389 195 11 11 121 clb auto 21.8 MiB 0.54 2075 39180 14775 18229 6176 60.6 MiB 0.39 0.01 4.56725 -162.762 -4.56725 4.56725 0.32 0.00290424 0.00269628 0.21446 0.199553 40 4742 31 4.36541e+06 4.14984e+06 303235. 2506.08 2.72 0.896352 0.821286 11571 60661 -1 3946 19 2186 7344 217806 45734 4.7836 4.7836 -183.173 -4.7836 0 0 379421. 3135.71 0.09 0.20 0.08 -1 -1 0.09 0.124637 0.115259 -k6_frac_N10_40nm.xml diffeq.blif common 5.52 vpr 62.28 MiB -1 -1 -1 -1 8 0.40 -1 -1 34272 -1 -1 52 64 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63776 64 39 941 980 1 449 155 10 10 100 clb auto 23.5 MiB 0.73 2754 14299 2774 10573 952 62.3 MiB 0.27 0.01 5.00123 -878.262 -5.00123 5.00123 0.25 0.00444533 0.00408514 0.170524 0.156838 46 4930 28 3.44922e+06 2.80249e+06 276332. 2763.32 2.10 0.960344 0.875051 9816 55112 -1 4472 14 1803 5492 169063 35103 5.16783 5.16783 -930.109 -5.16783 0 0 354105. 3541.05 0.08 0.21 0.08 -1 -1 0.08 0.15494 0.143538 -k6_frac_N10_40nm.xml dsip.blif common 9.71 vpr 64.65 MiB -1 -1 -1 -1 3 0.33 -1 -1 34640 -1 -1 68 229 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66204 229 197 1135 1332 1 648 494 16 16 256 io auto 25.3 MiB 0.73 4700 170318 50861 109699 9758 64.7 MiB 1.18 0.02 2.3875 -617.47 -2.3875 2.3875 0.78 0.00683703 0.00637878 0.619128 0.577611 34 9287 43 1.05632e+07 3.66479e+06 613832. 2397.78 3.93 2.05956 1.91939 24564 122629 -1 8151 13 2265 5666 327590 69866 2.60848 2.60848 -674.007 -2.60848 0 0 751777. 2936.63 0.21 0.32 0.16 -1 -1 0.21 0.222292 0.209372 -k6_frac_N10_40nm.xml elliptic.blif common 15.88 vpr 72.66 MiB -1 -1 -1 -1 10 1.34 -1 -1 37424 -1 -1 133 131 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74408 131 114 2471 2585 1 970 378 14 14 196 clb auto 32.2 MiB 3.03 9165 74142 19344 51191 3607 72.7 MiB 1.13 0.02 7.14215 -3414.64 -7.14215 7.14215 0.57 0.0112416 0.0101644 0.638433 0.581928 64 15825 36 7.76074e+06 7.1679e+06 810706. 4136.26 5.95 2.90989 2.65593 22444 164128 -1 14159 17 4519 20253 781043 131442 7.47917 7.47917 -3699.02 -7.47917 0 0 1.00880e+06 5146.95 0.24 0.70 0.25 -1 -1 0.24 0.461466 0.427062 -k6_frac_N10_40nm.xml frisc.blif common 19.77 vpr 74.44 MiB -1 -1 -1 -1 12 2.03 -1 -1 37396 -1 -1 153 20 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76224 20 116 2477 2593 1 1088 289 15 15 225 clb auto 33.6 MiB 3.85 12581 59499 15581 39947 3971 74.4 MiB 1.33 0.02 8.14365 -3747.83 -8.14365 8.14365 0.64 0.0112947 0.0102836 0.764701 0.696515 74 21933 44 9.10809e+06 8.24578e+06 1.06098e+06 4715.46 8.34 3.32442 3.03038 27275 217117 -1 19654 18 5722 25295 1201911 194668 8.26982 8.26982 -3960.51 -8.26982 0 0 1.32822e+06 5903.22 0.30 0.43 0.18 -1 -1 0.30 0.243345 0.22521 -k6_frac_N10_40nm.xml s298.blif common 7.43 vpr 62.24 MiB -1 -1 -1 -1 8 0.57 -1 -1 33856 -1 -1 61 4 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63732 4 6 671 677 1 350 71 10 10 100 clb auto 23.4 MiB 0.92 3493 3283 433 2659 191 62.2 MiB 0.16 0.01 5.33805 -43.3781 -5.33805 5.33805 0.25 0.00397189 0.00366099 0.105657 0.0981952 52 5783 22 3.44922e+06 3.28753e+06 305142. 3051.42 3.75 1.33758 1.22437 10212 61796 -1 5397 17 2148 10775 376607 64965 5.90507 5.90507 -48.8576 -5.90507 0 0 401807. 4018.07 0.09 0.27 0.09 -1 -1 0.09 0.165044 0.153465 -k6_frac_N10_40nm.xml s38417.blif common 18.81 vpr 78.45 MiB -1 -1 -1 -1 6 3.02 -1 -1 42408 -1 -1 179 29 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80332 29 106 3450 3556 1 1198 314 16 16 256 clb auto 37.5 MiB 2.17 8989 70670 18144 45519 7007 78.4 MiB 1.55 0.02 4.74073 -2890.12 -4.74073 4.74073 0.79 0.0138904 0.0125607 0.984666 0.887956 48 14980 41 1.05632e+07 9.64703e+06 819368. 3200.65 6.57 4.33054 3.91711 26860 167058 -1 13212 15 5024 17286 529604 104654 4.75139 4.75139 -2966.77 -4.75139 0 0 1.04748e+06 4091.72 0.30 0.71 0.23 -1 -1 0.30 0.554676 0.511839 -k6_frac_N10_40nm.xml s38584.1.blif common 18.55 vpr 78.51 MiB -1 -1 -1 -1 6 2.16 -1 -1 40952 -1 -1 194 38 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80396 38 304 3259 3563 1 1574 536 16 16 256 clb auto 37.8 MiB 2.15 9889 183320 55884 108640 18796 78.5 MiB 2.36 0.03 4.27217 -2394.9 -4.27217 4.27217 0.56 0.0145306 0.0132396 1.31178 1.18976 58 17695 25 1.05632e+07 1.04554e+07 977637. 3818.90 7.00 4.20263 3.82602 28644 201685 -1 15484 13 5074 13582 483608 102794 4.69981 4.69981 -2495.41 -4.69981 0 0 1.24374e+06 4858.37 0.31 0.65 0.30 -1 -1 0.31 0.521931 0.485523 -k6_frac_N10_40nm.xml tseng.blif common 4.95 vpr 60.83 MiB -1 -1 -1 -1 7 0.25 -1 -1 34444 -1 -1 34 52 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62292 52 122 664 786 1 355 208 8 8 64 io clb auto 22.2 MiB 0.71 1783 26080 5856 18588 1636 60.8 MiB 0.28 0.01 4.2185 -596.347 -4.2185 4.2185 0.15 0.00333934 0.00308628 0.153624 0.142133 58 3398 46 1.94018e+06 1.8324e+06 203254. 3175.84 2.23 1.20749 1.10156 6532 39661 -1 2965 13 1169 3143 108747 29150 4.26194 4.26194 -630.352 -4.26194 0 0 258247. 4035.11 0.06 0.15 0.06 -1 -1 0.06 0.107329 0.0995631 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml bigkey.blif common 6.23 vpr 64.53 MiB -1 -1 -1 -1 3 0.37 -1 -1 34788 -1 -1 53 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66076 229 197 1023 1220 1 510 479 16 16 256 io auto 23.9 MiB 0.27 3641 154065 46430 98015 9620 64.5 MiB 0.74 0.01 2.42373 -577.247 -2.42373 2.42373 0.26 0.00398091 0.00373104 0.340965 0.319373 -1 -1 -1 -1 36 6328 35 1.05632e+07 2.85638e+06 638738. 2495.07 2.89 1.48274 1.36625 24820 128426 -1 5481 8 1306 2376 126862 31374 2.67597 2.67597 -632.008 -2.67597 0 0 786978. 3074.13 0.03 0.13 0.10 -1 -1 0.03 0.0974416 0.0913862 + k6_frac_N10_40nm.xml clma.blif common 7.46 vpr 61.55 MiB -1 -1 -1 -1 7 2.24 -1 -1 39940 -1 -1 79 36 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63032 36 82 542 624 1 389 197 11 11 121 clb auto 22.1 MiB 0.53 2089 43172 15722 20877 6573 61.6 MiB 0.30 0.01 4.60077 -165.07 -4.60077 4.60077 0.11 0.00158818 0.0014666 0.129463 0.1196 -1 -1 -1 -1 44 4139 30 4.36541e+06 4.25763e+06 327165. 2703.84 2.77 0.732744 0.643123 11931 67129 -1 3316 16 1708 5716 138864 32420 4.83136 4.83136 -175.151 -4.83136 0 0 426099. 3521.48 0.01 0.11 0.05 -1 -1 0.01 0.0672002 0.0607985 + k6_frac_N10_40nm.xml diffeq.blif common 4.01 vpr 63.38 MiB -1 -1 -1 -1 8 0.41 -1 -1 34292 -1 -1 52 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64900 64 39 941 980 1 449 155 10 10 100 clb auto 23.4 MiB 0.70 2832 12635 2438 9282 915 63.4 MiB 0.18 0.01 4.98272 -882.824 -4.98272 4.98272 0.09 0.00234454 0.00211606 0.0863666 0.0788215 -1 -1 -1 -1 46 4591 19 3.44922e+06 2.80249e+06 276332. 2763.32 1.20 0.589632 0.513259 9816 55112 -1 4111 18 1656 5042 136520 29654 5.41789 5.41789 -952.235 -5.41789 0 0 354105. 3541.05 0.01 0.15 0.04 -1 -1 0.01 0.107362 0.0964647 + k6_frac_N10_40nm.xml dsip.blif common 7.36 vpr 64.88 MiB -1 -1 -1 -1 3 0.33 -1 -1 34684 -1 -1 68 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66440 229 197 1135 1332 1 648 494 16 16 256 io auto 25.2 MiB 0.71 5390 162510 50223 103313 8974 64.9 MiB 0.94 0.01 2.31397 -600.978 -2.31397 2.31397 0.26 0.00420661 0.00390485 0.388428 0.36156 -1 -1 -1 -1 34 9972 32 1.05632e+07 3.66479e+06 613832. 2397.78 3.22 1.46481 1.34083 24564 122629 -1 8332 13 2339 5868 306706 68264 2.51113 2.51113 -669.569 -2.51113 0 0 751777. 2936.63 0.03 0.22 0.10 -1 -1 0.03 0.14848 0.138451 + k6_frac_N10_40nm.xml elliptic.blif common 11.38 vpr 72.87 MiB -1 -1 -1 -1 10 1.33 -1 -1 37312 -1 -1 134 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74616 131 114 2471 2585 1 965 379 14 14 196 clb auto 31.9 MiB 3.01 9493 78526 21300 53244 3982 72.9 MiB 0.89 0.02 6.66989 -3362.18 -6.66989 6.66989 0.19 0.00572216 0.00514529 0.368526 0.328102 -1 -1 -1 -1 64 15463 36 7.76074e+06 7.2218e+06 810706. 4136.26 3.17 1.56022 1.36164 22444 164128 -1 13666 16 4234 17970 605416 107406 6.78748 6.78748 -3469.91 -6.78748 0 0 1.00880e+06 5146.95 0.03 0.41 0.13 -1 -1 0.03 0.262304 0.236626 + k6_frac_N10_40nm.xml frisc.blif common 14.61 vpr 74.16 MiB -1 -1 -1 -1 12 2.04 -1 -1 37212 -1 -1 154 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75944 20 116 2477 2593 1 1095 290 15 15 225 clb auto 33.3 MiB 3.71 12890 61666 15631 41457 4578 74.2 MiB 0.99 0.02 8.02167 -3816.55 -8.02167 8.02167 0.22 0.00590075 0.00528608 0.419513 0.373344 -1 -1 -1 -1 74 21484 43 9.10809e+06 8.29968e+06 1.06098e+06 4715.46 4.44 1.71833 1.49724 27275 217117 -1 19434 16 5788 25215 1069833 185373 8.27179 8.27179 -4029.23 -8.27179 0 0 1.32822e+06 5903.22 0.04 0.53 0.17 -1 -1 0.04 0.276787 0.249571 + k6_frac_N10_40nm.xml s298.blif common 5.13 vpr 62.66 MiB -1 -1 -1 -1 8 0.60 -1 -1 33840 -1 -1 61 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 4 6 671 677 1 350 71 10 10 100 clb auto 23.3 MiB 0.92 3495 3137 432 2529 176 62.7 MiB 0.11 0.00 5.3014 -43.7499 -5.3014 5.3014 0.09 0.00193317 0.0017562 0.0558011 0.0513432 -1 -1 -1 -1 54 5597 27 3.44922e+06 3.28753e+06 316276. 3162.76 1.97 0.645928 0.55799 10312 63908 -1 5157 17 2266 11525 327366 61505 5.48392 5.48392 -46.8399 -5.48392 0 0 411339. 4113.39 0.01 0.18 0.05 -1 -1 0.01 0.0964402 0.0870985 + k6_frac_N10_40nm.xml s38417.blif common 14.45 vpr 78.21 MiB -1 -1 -1 -1 6 3.08 -1 -1 42448 -1 -1 176 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80088 29 106 3450 3556 1 1190 311 16 16 256 clb auto 36.9 MiB 2.12 8949 65597 16026 43107 6464 78.2 MiB 1.04 0.02 4.50231 -2905.37 -4.50231 4.50231 0.26 0.0069377 0.00610226 0.499027 0.435137 -1 -1 -1 -1 46 15732 39 1.05632e+07 9.48534e+06 786978. 3074.13 4.30 2.34785 2.00419 26604 162157 -1 13635 14 5142 17426 519616 106370 4.53102 4.53102 -2987.6 -4.53102 0 0 1.01084e+06 3948.58 0.03 0.49 0.12 -1 -1 0.03 0.357573 0.323077 + k6_frac_N10_40nm.xml s38584.1.blif common 15.91 vpr 78.62 MiB -1 -1 -1 -1 6 2.20 -1 -1 41012 -1 -1 203 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80504 38 304 3259 3563 1 1559 545 17 17 289 clb auto 37.4 MiB 3.13 10446 174095 49766 105233 19096 78.6 MiB 1.73 0.02 4.29015 -2399.8 -4.29015 4.29015 0.30 0.0081369 0.00733169 0.717489 0.631478 -1 -1 -1 -1 58 17767 23 1.21262e+07 1.09405e+07 1.11519e+06 3858.79 4.85 2.80811 2.44124 32499 230706 -1 16008 15 5250 14700 516522 110817 4.81093 4.81093 -2541.32 -4.81093 0 0 1.41877e+06 4909.24 0.05 0.47 0.18 -1 -1 0.05 0.353691 0.320217 + k6_frac_N10_40nm.xml tseng.blif common 3.79 vpr 61.52 MiB -1 -1 -1 -1 7 0.51 -1 -1 34300 -1 -1 33 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63000 52 122 664 786 1 358 207 8 8 64 io clb auto 22.0 MiB 0.69 1908 22239 4478 16280 1481 61.5 MiB 0.19 0.01 4.25559 -597.466 -4.25559 4.25559 0.05 0.0019736 0.00181929 0.081938 0.075812 -1 -1 -1 -1 58 3323 26 1.94018e+06 1.7785e+06 203254. 3175.84 1.01 0.511783 0.451955 6532 39661 -1 2850 14 1079 2916 89573 24965 4.64398 4.64398 -644.298 -4.64398 0 0 258247. 4035.11 0.01 0.11 0.03 -1 -1 0.01 0.0729861 0.0664889 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt index 38a7505faba..b77b4bd5ed6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 68.70 vpr 141.21 MiB 0.93 39844 -1 -1 8 4.37 -1 -1 41924 -1 -1 258 385 2 1 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 144600 385 394 4673 4537 1 2422 1040 27 27 729 io auto 62.8 MiB 9.25 31099 601478 234916 341577 24985 100.0 MiB 5.37 0.06 7.91028 -9390.87 -7.91028 7.91028 2.16 0.0160116 0.0148357 1.92959 1.75908 98 45582 18 3.93038e+07 1.53967e+07 4.48119e+06 6147.03 34.34 8.78739 8.0602 101765 947141 -1 43516 17 9970 36172 3767326 768291 8.49882 8.49882 -10225.8 -8.49882 0 0 5.68448e+06 7797.64 1.45 1.61 0.90 -1 -1 1.45 0.711623 0.664406 -k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 248.04 abc 92.62 MiB 2.07 38132 -1 -1 3 222.88 -1 -1 94848 -1 -1 156 38 0 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85708 38 36 2995 2744 1 1210 230 17 17 289 clb auto 46.9 MiB 2.35 11187 48102 12239 32898 2965 83.7 MiB 1.02 0.02 8.50665 -2425.54 -8.50665 8.50665 0.68 0.00648791 0.00577114 0.492669 0.42844 86 15535 20 1.34605e+07 8.40746e+06 1.47169e+06 5092.36 8.86 2.72296 2.3536 36379 299185 -1 14997 15 3639 10555 369332 60267 10.0216 10.0216 -2922.92 -10.0216 0 0 1.86203e+06 6443.01 0.42 0.41 0.32 -1 -1 0.42 0.297614 0.2695 -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 8.70 vpr 70.45 MiB 0.75 45128 -1 -1 3 0.52 -1 -1 37948 -1 -1 92 142 0 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72136 142 193 1069 1140 1 565 427 14 14 196 clb auto 32.4 MiB 0.82 1818 153092 57142 75216 20734 70.4 MiB 0.62 0.01 2.94229 -453.47 -2.94229 2.94229 0.43 0.00270225 0.00251819 0.270422 0.252062 36 4119 16 9.20055e+06 4.95825e+06 447080. 2281.02 1.25 0.678648 0.626119 18336 87587 -1 3545 13 1258 1911 94099 25244 3.69367 3.69367 -542.415 -3.69367 0 0 553089. 2821.88 0.13 0.13 0.06 -1 -1 0.13 0.0968577 0.090647 -k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 24.99 vpr 84.66 MiB 0.47 31528 -1 -1 3 1.06 -1 -1 40312 -1 -1 112 214 0 8 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86692 214 305 2963 2869 1 1445 639 19 19 361 io auto 46.9 MiB 2.82 10827 256482 85370 157603 13509 84.7 MiB 1.63 0.02 4.36739 -2477.41 -4.36739 4.36739 0.89 0.00721181 0.00661461 0.712875 0.654201 56 24300 32 1.72706e+07 9.20413e+06 1.27879e+06 3542.35 11.31 2.9929 2.72715 39043 256479 -1 19887 20 6510 14395 4285781 1013890 4.87643 4.87643 -2933.55 -4.87643 0 0 1.63234e+06 4521.70 0.37 1.20 0.23 -1 -1 0.37 0.376058 0.348776 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 35.73 vpr 117.99 MiB 0.88 39796 -1 -1 8 4.27 -1 -1 42064 -1 -1 258 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 120820 385 394 4673 4537 1 2402 1040 27 27 729 io auto 55.2 MiB 8.87 31226 590944 229570 335529 25845 99.0 MiB 4.01 0.05 8.49305 -10507.1 -8.49305 8.49305 0.67 0.00985407 0.00919392 1.21454 1.10916 -1 -1 -1 -1 92 45492 18 3.93038e+07 1.53967e+07 4.24291e+06 5820.18 8.25 3.43478 3.14555 98853 888777 -1 43336 19 10072 35436 1903495 335341 8.64458 8.64458 -10958.4 -8.64458 0 0 5.38988e+06 7393.52 0.21 1.31 0.80 -1 -1 0.21 0.81131 0.758475 + k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 252.53 abc 92.89 MiB 2.10 38212 -1 -1 3 229.65 -1 -1 95116 -1 -1 155 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85380 38 36 2995 2744 1 1203 229 17 17 289 clb auto 42.6 MiB 2.62 11670 42229 10578 28453 3198 83.4 MiB 1.00 0.02 9.56668 -2644.49 -9.56668 9.56668 0.30 0.00653116 0.00584439 0.427666 0.375753 -1 -1 -1 -1 68 16961 39 1.34605e+07 8.35357e+06 1.21205e+06 4193.96 7.00 2.98402 2.54931 32923 238265 -1 15449 21 4262 11796 386501 67599 10.0346 10.0346 -2927.77 -10.0346 0 0 1.50552e+06 5209.41 0.05 0.47 0.21 -1 -1 0.05 0.348571 0.310711 + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 9.27 vpr 70.62 MiB 0.76 45212 -1 -1 3 0.57 -1 -1 37660 -1 -1 97 142 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72316 142 193 1069 1140 1 544 432 14 14 196 clb auto 31.5 MiB 1.33 1935 140784 46814 73686 20284 70.6 MiB 0.61 0.01 3.36481 -502.007 -3.36481 3.36481 0.20 0.00294747 0.00276699 0.269116 0.252539 -1 -1 -1 -1 42 3322 13 9.20055e+06 5.22772e+06 506340. 2583.37 1.96 1.10351 1.01282 19116 100245 -1 3124 11 1007 1567 69332 19451 3.55486 3.55486 -535.708 -3.55486 0 0 635007. 3239.83 0.02 0.12 0.09 -1 -1 0.02 0.0909108 0.0848666 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 20.73 vpr 84.22 MiB 0.49 31708 -1 -1 3 1.08 -1 -1 40516 -1 -1 123 214 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 86244 214 305 2963 2869 1 1444 650 19 19 361 io auto 43.2 MiB 3.52 11237 214514 71103 131344 12067 84.2 MiB 1.56 0.03 4.53 -2651.41 -4.53 4.53 0.39 0.00798613 0.00737775 0.647388 0.59775 -1 -1 -1 -1 58 21099 31 1.72706e+07 9.79696e+06 1.32779e+06 3678.09 7.97 3.16487 2.88635 39763 268823 -1 18983 16 5722 13316 1766310 456164 4.74311 4.74311 -2886.77 -4.74311 0 0 1.69263e+06 4688.74 0.06 0.74 0.27 -1 -1 0.06 0.376597 0.351474 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt index 472b47cb7f6..806aa8c8a19 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 628.23 vpr 523.07 MiB 4.94 207220 -1 -1 101 125.94 -1 -1 108124 -1 -1 2196 114 44 8 success b37c31d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-04-04T16:52:55 gh-actions-runner-vtr-auto-spawned70 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 535628 114 102 38224 33865 1 18116 2464 57 57 3249 clb auto 366.7 MiB 79.89 235628 1915489 723145 1160834 31510 434.9 MiB 90.41 0.75 68.8354 -54271.6 -68.8354 68.8354 1.27 0.122715 0.109144 14.833 12.338 -1 337567 24 1.92089e+08 1.45633e+08 2.12617e+07 6544.09 29.31 22.8823 19.2537 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 461.97 vpr 520.77 MiB 5.52 207104 -1 -1 101 82.80 -1 -1 104772 -1 -1 2232 114 44 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 533268 114 102 38224 33865 1 17936 2500 57 57 3249 clb auto 296.6 MiB 87.81 234808 1969860 734649 1200070 35141 428.8 MiB 60.45 0.51 75.4166 -53786.3 -75.4166 75.4166 0.01 0.108744 0.090072 13.6268 11.3009 -1 -1 -1 -1 -1 329498 24 1.92089e+08 1.47573e+08 2.12617e+07 6544.09 11.64 20.3553 17.0367 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff_titan/config/golden_results.txt index f2b439ff03e..18b3e54aa6f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 1315.84 77 3123 89 136 0 0 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 2858228 42 35 119888 86875 1 51283 3425 129 96 12384 DSP auto 86.66 609879 114.00 0.78 7.31659 -73007.4 -6.31659 6.39652 193.04 0.230423 0.177265 33.2852 25.4119 777696 -1 -1 -1 -1 0 0 2.28642e+08 18462.7 20 7.77193 6.96909 -118197 -6.77193 0 0 50.21 46.7196 37.2174 149.58 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 875.57 vpr 2.85 GiB 77 3136 89 136 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2992920 42 35 119888 86875 1 50816 3438 129 96 12384 DSP auto 1747.3 MiB 113.44 582667 3141815 1177622 1941316 22877 2922.8 MiB 131.76 0.97 8.30634 -81008.6 -7.30634 5.71368 0.07 0.390966 0.330249 50.2947 42.4929 753664 14.8455 159283 3.13753 108681 189329 132420316 35517631 0 0 2.28639e+08 18462.4 18 3593250 39165143 -1 8.74065 6.13717 -112227 -7.74065 0 0 78.47 -1 -1 2922.8 MiB 45.38 68.7408 59.0089 2922.8 MiB -1 22.64 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt index 05102b14630..4719bdbbc41 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt @@ -1,15 +1,15 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml bgm.v common 94.08 yosys 239.28 MiB -1 -1 49.30 245024 18 13.22 -1 -1 51004 -1 -1 689 257 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 115188 257 32 6041 6073 1 5235 978 30 30 900 clb auto 57.2 MiB 1.23 29985 112.5 MiB 5.78 0.07 6.0875 -2546.45 -6.0875 6.0875 0.21 0.0116004 0.00952958 0.966535 0.81325 47934 24472 85349 11868342 2593378 4.97244e+06 2.6871e+06 9.69309e+06 10770.1 19 6.86469 6.86469 -2916.73 -6.86469 0 0 112.5 MiB 3.47 1.59485 1.36176 112.5 MiB 14.13 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml blob_merge.v common 111.52 yosys 302.91 MiB -1 -1 17.69 310184 11 18.95 -1 -1 60792 -1 -1 1309 36 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 199576 36 100 10272 10372 1 9717 1445 41 41 1681 clb auto 91.3 MiB 1.71 84755 194.9 MiB 22.24 0.23 4.16019 -1591.46 -4.16019 4.16019 0.51 0.0327612 0.0271477 3.22883 2.67515 138099 47433 159547 25268625 4863134 8.95136e+06 5.1051e+06 1.84779e+07 10992.2 18 4.66194 4.66194 -1818.85 -4.66194 0 0 194.9 MiB 8.70 4.88548 4.09248 194.9 MiB 30.37 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml boundtop.v common 19.98 vpr 63.44 MiB -1 -1 14.95 35240 7 0.23 -1 -1 37236 -1 -1 84 195 1 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64960 195 193 1172 1365 1 837 473 15 15 225 io memory auto 25.4 MiB 0.13 3551 63.4 MiB 0.68 0.01 2.02671 -779.537 -2.02671 2.02671 0.04 0.0019832 0.00177416 0.190053 0.170064 5389 2076 6396 795212 201029 1.16234e+06 410348 2.18283e+06 9701.45 12 2.21102 2.21102 -902.31 -2.21102 -5.18176 -0.375057 63.4 MiB 0.27 0.270471 0.244687 63.4 MiB 2.21 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml LU8PEEng.v common 494.37 vpr 715.82 MiB -1 -1 73.42 337876 197 97.67 -1 -1 83744 -1 -1 2994 114 84 8 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 733004 114 102 27412 27322 1 24802 3302 86 86 7396 memory auto 208.9 MiB 7.36 251641 715.8 MiB 75.10 0.65 63.9648 -36231.9 -63.9648 63.9648 2.70 0.0670445 0.0543409 7.08657 5.72048 339513 88760 297702 125893415 50379905 4.18276e+07 1.95778e+07 8.44414e+07 11417.2 23 71.4148 71.4148 -60631.2 -71.4148 -145.469 -0.36083 715.8 MiB 58.92 10.8826 8.92707 715.8 MiB 142.88 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mkDelayWorker32B.v common 194.12 vpr 556.41 MiB -1 -1 14.86 128884 6 5.85 -1 -1 60228 -1 -1 530 506 80 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 569760 506 553 3101 3654 1 3095 1669 82 82 6724 memory auto 47.2 MiB 1.67 22423 556.4 MiB 4.95 0.05 6.05217 -1454.35 -6.05217 6.05217 2.62 0.0154982 0.013967 2.20022 1.96905 25147 4320 5400 6396252 2098319 3.85878e+07 8.68684e+06 7.66484e+07 11399.2 14 6.28816 6.28816 -1748.1 -6.28816 -21.3514 -0.36083 556.4 MiB 2.98 2.83156 2.55993 556.4 MiB 138.42 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mkSMAdapter4B.v common 42.90 vpr 132.11 MiB -1 -1 7.13 57948 12 3.00 -1 -1 40372 -1 -1 268 193 10 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 135280 193 205 2654 2859 1 2029 676 37 37 1369 memory auto 36.3 MiB 0.49 16037 132.1 MiB 2.25 0.03 3.73419 -2252.01 -3.73419 3.73419 0.34 0.00539662 0.00465347 0.562454 0.485859 23850 7572 24450 6218122 1974634 7.45627e+06 1.87268e+06 1.49196e+07 10898.2 15 4.1 4.1 -2552.52 -4.1 -16.2594 -0.362934 132.1 MiB 2.33 0.801166 0.701352 132.1 MiB 21.99 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml or1200.v common 39.95 vpr 96.50 MiB -1 -1 6.09 70384 45 5.24 -1 -1 41644 -1 -1 506 385 4 1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 98816 385 394 5015 5346 1 4350 1290 27 27 729 io clb auto 53.1 MiB 0.87 41926 96.2 MiB 8.07 0.08 12.8573 -9363.03 -12.8573 12.8573 0.17 0.0144261 0.0132607 1.60279 1.42637 60904 14787 54657 9040768 2197120 4.06709e+06 2.42319e+06 7.75339e+06 10635.7 17 14.1675 14.1675 -10940.6 -14.1675 0 0 96.2 MiB 3.48 2.34681 2.10329 96.2 MiB 11.60 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 24.52 vpr 81.19 MiB -1 -1 4.98 48784 13 1.22 -1 -1 41592 -1 -1 256 235 1 6 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 83140 235 305 3025 3186 1 2385 803 26 26 676 mult_36 auto 37.2 MiB 0.54 17792 81.2 MiB 2.23 0.03 4.07341 -1915.66 -4.07341 4.07341 0.14 0.00596069 0.00545514 0.514273 0.454401 26395 7994 25461 5630378 1530085 3.88769e+06 1.79395e+06 7.17610e+06 10615.5 16 4.6849 4.6849 -2313.21 -4.6849 -34.8532 -0.36083 81.2 MiB 1.82 0.812614 0.726893 81.2 MiB 10.22 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml sha.v common 19.66 vpr 79.00 MiB -1 -1 3.03 50220 31 2.57 -1 -1 43480 -1 -1 339 38 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 80900 38 36 3594 3630 1 2712 413 22 22 484 clb auto 41.5 MiB 0.56 19133 79.0 MiB 1.85 0.03 9.67412 -2335.65 -9.67412 9.67412 0.09 0.00827985 0.00698716 0.450426 0.38139 31734 11686 45588 5830197 1332550 2.41174e+06 1.3221e+06 5.02684e+06 10386.0 19 11.0674 11.0674 -2864.8 -11.0674 0 0 79.0 MiB 2.11 0.88857 0.765334 79.0 MiB 6.48 - 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gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 407536 113 145 23206 21071 1 16047 2016 62 62 3844 mult_36 auto 141.4 MiB 3.29 143820 398.0 MiB 37.12 0.30 4.32437 -16925.8 -4.32437 4.32437 1.40 0.0406386 0.0362444 4.69579 4.02718 184101 52325 148236 47967259 12664479 2.17057e+07 1.19118e+07 4.33614e+07 11280.3 11 4.51376 4.51376 -20726.1 -4.51376 0 0 398.0 MiB 15.31 6.30117 5.46654 398.0 MiB 75.08 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision2.v common 872.12 vpr 1.36 GiB -1 -1 42.72 330780 25 179.00 -1 -1 138520 -1 -1 4676 149 0 179 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1427112 149 182 52817 45103 1 44034 5186 122 122 14884 mult_36 auto 326.8 MiB 10.95 610462 1393.7 MiB 226.09 1.76 13.0565 -37981.2 -13.0565 13.0565 6.72 0.159797 0.135184 18.8147 15.9648 736559 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-58.8084 -0.0952056 -0.03838 104.27 -1 -1 3052.1 MiB 56.17 58.8307 49.565 3052.1 MiB -1 54.29 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt index ff1ef00e2e0..35a4467c277 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt @@ -1,21 +1,21 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_mem32K_40nm.xml arm_core.v common 280.20 vpr 257.79 MiB -1 -1 25.75 122844 25 38.75 -1 -1 67596 -1 -1 880 133 24 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 263980 133 179 13858 14037 1 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2.50602e+07 1.49286e+07 1.81652e+06 3753.13 13.19 4.54237 3.95427 52870 368945 -1 28855 15 10906 34558 982071 189322 9.64046 9.64046 -3932.02 -9.64046 0 0 2.31597e+06 4785.06 0.53 0.76 0.31 -1 -1 0.53 0.488917 0.443615 2580 2833 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml blob_merge.v common 89.76 parmys 291.04 MiB -1 -1 15.38 298020 7 11.99 -1 -1 57968 -1 -1 566 36 0 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 163404 36 100 6840 6940 1 3200 702 30 30 900 clb auto 85.5 MiB 4.42 44186 278204 76945 183206 18053 122.5 MiB 4.81 0.05 5.85686 -2192.32 -5.85686 5.85686 2.38 0.0180181 0.0160503 1.85784 1.60892 68 71187 28 4.8774e+07 3.0504e+07 4.08678e+06 4540.87 35.59 8.94537 7.61686 104936 820930 -1 63255 15 15176 68305 3028418 384879 6.04948 6.04948 -2275.21 -6.04948 0 0 5.07014e+06 5633.48 1.15 1.64 0.67 -1 -1 1.15 0.867118 0.785571 4872 6243 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml boundtop.v common 19.71 vpr 67.77 MiB -1 -1 12.00 31536 4 0.23 -1 -1 34556 -1 -1 42 195 1 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69400 195 193 1088 1281 1 593 431 15 15 225 io auto 29.8 MiB 0.40 2789 140353 37684 89836 12833 67.8 MiB 0.68 0.01 2.5026 -1068.95 -2.5026 2.5026 0.45 0.0035004 0.00326724 0.318219 0.29679 42 5940 17 1.03862e+07 2.81155e+06 589524. 2620.11 3.76 1.43455 1.31489 21486 116796 -1 5209 12 1582 2286 164748 45289 2.70224 2.70224 -1159.85 -2.70224 -0.575265 -0.201936 739091. 3284.85 0.16 0.16 0.11 -1 -1 0.16 0.112943 0.105183 347 531 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.90 vpr 64.06 MiB -1 -1 0.34 18776 3 0.09 -1 -1 33160 -1 -1 68 99 1 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65600 99 130 343 473 1 225 298 12 12 144 clb auto 25.6 MiB 0.15 593 66963 19571 35031 12361 64.1 MiB 0.23 0.00 1.865 -117.456 -1.865 1.865 0.27 0.00127756 0.00120824 0.0904413 0.0855813 42 1503 16 5.66058e+06 4.21279e+06 345702. 2400.71 1.53 0.430255 0.394458 12810 66778 -1 1212 8 350 556 27894 7863 2.02345 2.02345 -142.963 -2.02345 -0.458472 -0.106489 434679. 3018.61 0.09 0.04 0.07 -1 -1 0.09 0.0281257 0.026127 144 154 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml diffeq1.v common 11.92 vpr 67.45 MiB -1 -1 0.54 23452 15 0.32 -1 -1 34120 -1 -1 36 162 0 5 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69068 162 96 994 935 1 694 299 16 16 256 mult_36 auto 29.4 MiB 0.28 5022 91208 31929 52152 7127 67.4 MiB 0.66 0.01 21.1771 -1637.49 -21.1771 21.1771 0.51 0.0034124 0.00320223 0.331093 0.310751 56 12767 47 1.21132e+07 3.92018e+06 870502. 3400.40 6.96 1.28868 1.18762 26504 172068 -1 9174 19 3073 5862 965990 269588 22.2519 22.2519 -1734.32 -22.2519 0 0 1.11200e+06 4343.75 0.24 0.38 0.17 -1 -1 0.24 0.15888 0.147497 337 479 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml diffeq2.v common 12.80 vpr 65.55 MiB -1 -1 0.20 22176 16 0.24 -1 -1 33572 -1 -1 27 66 0 5 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 67124 66 96 610 551 1 452 194 16 16 256 mult_36 auto 27.3 MiB 0.30 3491 41708 11675 25394 4639 65.6 MiB 0.36 0.01 16.8255 -937.879 -16.8255 16.8255 0.51 0.00238587 0.00225299 0.189255 0.178809 50 9637 45 1.21132e+07 3.43514e+06 780512. 3048.87 8.84 1.16511 1.07001 25484 153448 -1 7566 22 3118 6840 1168639 359265 17.7302 17.7302 -1031.17 -17.7302 0 0 1.00276e+06 3917.05 0.21 0.38 0.14 -1 -1 0.21 0.120297 0.111441 235 288 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml mkDelayWorker32B.v common 81.17 vpr 332.60 MiB -1 -1 13.40 124716 5 3.43 -1 -1 56692 -1 -1 460 506 47 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 340580 506 553 3055 3608 1 2790 1566 50 50 2500 memory auto 52.9 MiB 4.44 15016 1146906 560934 403027 182945 332.6 MiB 5.64 0.06 7.02534 -1950.88 -7.02534 7.02534 18.86 0.0232393 0.0210229 3.05303 2.74244 38 22534 14 1.47946e+08 5.05479e+07 6.86584e+06 2746.33 17.59 8.34828 7.5787 251304 1421084 -1 21732 15 3907 5076 1040584 239224 7.06661 7.06661 -2232.41 -7.06661 -3.54638 -0.295467 8.69095e+06 3476.38 2.71 1.06 1.22 -1 -1 2.71 0.855401 0.790478 953 1207 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml mkPktMerge.v common 20.83 vpr 75.12 MiB -1 -1 1.22 25852 2 0.36 -1 -1 33772 -1 -1 27 311 15 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76920 311 156 972 1128 1 953 509 28 28 784 memory auto 30.4 MiB 0.49 9059 189392 67096 112947 9349 71.6 MiB 1.08 0.02 4.05723 -4390.2 -4.05723 4.05723 1.83 0.00563434 0.00500276 0.552809 0.49016 48 14303 15 4.25198e+07 9.67514e+06 2.50616e+06 3196.63 10.09 2.37376 2.1062 80602 506684 -1 13827 14 2506 2832 619608 160214 4.25681 4.25681 -4915.31 -4.25681 -18.6727 -0.360359 3.20999e+06 4094.38 0.77 0.33 0.43 -1 -1 0.77 0.195921 0.177483 109 186 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml mkSMAdapter4B.v common 26.49 vpr 76.90 MiB -1 -1 6.16 54304 7 2.23 -1 -1 39368 -1 -1 153 193 5 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78748 193 205 2152 2357 1 1161 556 20 20 400 memory auto 39.4 MiB 1.52 8858 231341 79266 127842 24233 76.9 MiB 1.59 0.02 4.96605 -2953.62 -4.96605 4.96605 0.81 0.00676456 0.00610519 0.727478 0.653919 50 16222 33 2.07112e+07 1.09858e+07 1.26944e+06 3173.59 9.27 2.9981 2.67772 40848 252947 -1 14533 15 4363 10859 617682 132576 4.91884 4.91884 -3085.46 -4.91884 -7.99782 -0.340786 1.63222e+06 4080.54 0.37 0.42 0.23 -1 -1 0.37 0.267345 0.244193 947 1174 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml or1200.v common 57.25 vpr 106.50 MiB -1 -1 5.56 66516 27 4.10 -1 -1 41788 -1 -1 251 385 2 1 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 109052 385 394 3884 4215 1 2355 1033 27 27 729 io auto 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3.25894 39599 281069 -1 19716 13 5626 15462 1415752 327524 5.02806 5.02806 -2816.27 -5.02806 -1.25369 -0.0304031 1.76637e+06 4892.99 0.44 0.61 0.25 -1 -1 0.44 0.300482 0.280819 1038 1294 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml sha.v common 16.37 vpr 79.59 MiB -1 -1 2.93 46276 21 2.14 -1 -1 41028 -1 -1 149 38 0 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81500 38 36 2570 2606 1 1074 223 17 17 289 clb auto 42.3 MiB 1.33 9358 36727 8203 26236 2288 79.6 MiB 0.70 0.01 13.9422 -2847.26 -13.9422 13.9422 0.59 0.0057032 0.00504453 0.365255 0.3232 46 17017 35 1.34605e+07 8.03021e+06 830882. 2875.03 4.35 1.59721 1.3833 28231 166010 -1 14224 16 4373 13089 440600 78841 14.6248 14.6248 -3199.06 -14.6248 0 0 1.06831e+06 3696.59 0.23 0.41 0.15 -1 -1 0.23 0.273543 0.245358 1458 1647 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml 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Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 261808 113 145 21669 19534 1 9921 1059 40 40 1600 mult_36 auto 151.3 MiB 8.85 84857 572929 187668 359255 26006 218.2 MiB 9.69 0.10 5.28341 -22594.6 -5.28341 5.28341 4.27 0.0329171 0.0273991 3.78077 3.17952 78 133452 45 9.16046e+07 5.82227e+07 8.23230e+06 5145.19 72.58 15.4019 13.0152 199776 1720042 -1 120901 15 32194 54580 8831164 1886670 5.47538 5.47538 -24275.7 -5.47538 0 0 1.04203e+07 6512.68 2.53 3.33 1.44 -1 -1 2.53 1.5499 1.3837 7327 9014 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml stereovision2.v common 635.75 vpr 996.02 MiB -1 -1 36.83 328740 16 70.21 -1 -1 133104 -1 -1 1876 149 0 179 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1019928 149 182 46661 38947 1 28355 2386 80 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80064 235 305 2600 2761 1 1433 664 19 19 361 io auto 37.7 MiB 2.02 12027 249634 86844 149473 13317 78.2 MiB 1.87 0.03 5.30864 -2648.81 -5.30864 5.30864 0.39 0.00799633 0.00740581 0.747518 0.688936 -1 -1 -1 -1 56 22630 21 1.72706e+07 9.2296e+06 1.27879e+06 3542.35 8.20 2.88004 2.62374 38159 255829 -1 20346 20 5608 15965 1386935 355889 5.35066 5.35066 -2866.8 -5.35066 -8.65745 -0.196482 1.63234e+06 4521.70 0.05 0.66 0.22 -1 -1 0.05 0.385253 0.355995 1041 1300 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml sha.v common 17.48 vpr 78.97 MiB -1 -1 4.21 48012 21 2.24 -1 -1 40584 -1 -1 150 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80868 38 36 2570 2606 1 1074 224 17 17 289 clb auto 38.2 MiB 1.44 9206 36264 8126 25763 2375 79.0 MiB 0.76 0.01 13.8191 -2630.52 -13.8191 13.8191 0.30 0.00635308 0.00568636 0.379903 0.337131 -1 -1 -1 -1 48 15632 40 1.34605e+07 8.0841e+06 864508. 2991.38 5.47 2.34496 2.023 28519 171069 -1 13363 20 4013 11904 355523 67720 14.9903 14.9903 -2979.62 -14.9903 0 0 1.10659e+06 3829.03 0.03 0.31 0.11 -1 -1 0.03 0.228029 0.208867 1457 1647 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml stereovision0.v common 114.12 vpr 221.60 MiB -1 -1 11.00 122760 5 42.78 -1 -1 65056 -1 -1 749 169 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 226920 169 197 21117 21314 1 6554 1115 34 34 1156 clb auto 126.4 MiB 9.77 46234 579015 188806 368341 21868 178.3 MiB 8.09 0.09 3.53206 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-1 -1 -1 + k6_frac_N10_mem32K_40nm.xml stereovision3.v common 2.83 vpr 63.49 MiB -1 -1 0.96 22952 5 0.13 -1 -1 33376 -1 -1 7 10 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65016 10 2 181 183 1 37 19 6 6 36 clb auto 24.0 MiB 0.06 125 94 37 54 3 63.5 MiB 0.01 0.00 2.09443 -87.946 -2.09443 2.09443 0.02 0.000491328 0.000453678 0.00392453 0.0037192 -1 -1 -1 -1 26 127 8 646728 377258 45676.2 1268.78 0.25 0.10472 0.0875195 2356 7902 -1 119 8 72 98 1263 541 1.98035 1.98035 -90.0206 -1.98035 0 0 56047.2 1556.87 0.00 0.02 0.01 -1 -1 0.00 0.0122617 0.0109864 52 90 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml LU8PEEng.v common 335.48 vpr 446.37 MiB -1 -1 85.53 350812 123 57.25 -1 -1 78588 -1 -1 1354 114 45 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 457080 114 102 21994 21904 1 11067 1623 50 50 2500 memory auto 169.9 MiB 25.36 151955 1021761 356538 644113 21110 446.4 MiB 24.23 0.20 79.7251 -52220.5 -79.7251 79.7251 9.68 0.0602828 0.0526636 7.23374 6.03628 -1 -1 -1 -1 88 230345 35 1.47946e+08 1.00803e+08 1.46563e+07 5862.50 97.97 27.3303 22.5517 331272 3068748 -1 205366 19 40592 161935 9797150 1881837 81.0471 81.0471 -67091 -81.0471 -7.13348 -0.293253 1.83775e+07 7351.00 0.80 5.76 2.82 -1 -1 0.80 3.27315 2.80685 12609 14234 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml LU32PEEng.v common 2442.52 vpr 1.73 GiB -1 -1 258.68 1026588 124 552.80 -1 -1 233444 -1 -1 4481 114 168 32 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1813676 114 102 72759 72093 1 37610 4897 92 92 8464 memory auto 510.6 MiB 96.92 754623 5076071 2040814 3006065 29192 1442.0 MiB 220.81 1.57 80.7548 -305716 -80.7548 80.7548 37.06 0.237208 0.205198 30.9063 25.5114 -1 -1 -1 -1 122 1020904 46 5.19428e+08 3.46213e+08 6.75417e+07 7979.88 1138.60 133.192 108.89 1314002 14600600 -1 937208 19 140677 611398 44735088 7699678 80.7275 80.7275 -415911 -80.7275 -29.9669 -0.17368 8.47015e+07 10007.3 4.65 24.60 14.85 -1 -1 4.65 12.2915 10.5138 42648 47397 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml mcml.v common 4904.44 vpr 1.68 GiB -1 -1 681.62 1428456 64 3460.75 -1 -1 347276 -1 -1 4906 36 159 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1762484 36 356 125423 124208 1 32010 5484 92 92 8464 memory auto 675.0 MiB 73.34 379984 6144664 2439048 3655799 49817 1599.2 MiB 177.06 1.20 63.3831 -263362 -63.3831 63.3831 40.06 0.258391 0.224397 35.9954 30.3596 -1 -1 -1 -1 80 535404 46 5.19428e+08 3.62204e+08 4.63837e+07 5480.11 333.49 155.427 127.989 1085502 9765414 -1 503795 17 105029 333178 19086430 3883087 64.399 64.399 -305691 -64.399 -0.590352 -0.0337239 5.84708e+07 6908.18 2.83 17.10 9.03 -1 -1 2.83 12.3477 10.6541 47698 74153 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt index e665c066fed..5fc9ae47bce 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt @@ -1,22 +1,22 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 255.87 vpr 266.12 MiB -1 -1 33.21 121108 20 51.66 -1 -1 67420 -1 -1 852 133 25 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 272504 133 179 14228 14085 1 7083 1189 37 37 1369 clb auto 124.1 MiB 55.24 118769 611901 198399 390860 22642 182.9 MiB 12.74 0.12 23.082 -209424 -23.082 23.082 4.18 0.0401013 0.0351966 4.51768 3.8456 110 180467 24 7.54166e+07 5.96187e+07 9.46577e+06 6914.37 70.64 15.6471 13.0594 201652 2027183 -1 164262 14 29902 115834 9220015 1621549 24.3564 24.3564 -221310 -24.3564 0 0 1.20852e+07 8827.75 3.46 5.39 1.97 -1 -1 3.46 2.40428 2.08959 -k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 525.83 vpr 710.25 MiB -1 -1 69.20 614744 14 71.56 -1 -1 121924 -1 -1 2715 257 0 11 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 727296 257 32 36080 33722 1 19553 3015 63 63 3969 clb auto 301.2 MiB 92.74 248033 2180215 773829 1379285 27101 710.2 MiB 60.47 0.53 19.0622 -25745.4 -19.0622 19.0622 36.12 0.105944 0.0877618 11.3985 9.52259 74 394698 40 2.36641e+08 1.5068e+08 2.02178e+07 5093.92 113.40 35.3604 29.3374 502298 4195434 -1 380376 21 97229 438645 20887764 3077897 19.7741 19.7741 -26305.4 -19.7741 0 0 2.53694e+07 6391.88 9.43 13.49 3.91 -1 -1 9.43 6.66179 5.7969 -k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 88.16 parmys 244.68 MiB -1 -1 15.96 250556 5 3.94 -1 -1 54952 -1 -1 487 36 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 141756 36 100 10178 7632 1 2732 623 28 28 784 clb auto 89.6 MiB 21.09 41236 216002 63618 139932 12452 136.6 MiB 4.12 0.05 15.0315 -2401.76 -15.0315 15.0315 2.01 0.0200758 0.0181589 1.82478 1.61386 70 69778 28 4.25198e+07 2.62464e+07 3.59791e+06 4589.17 25.18 6.26144 5.39126 94322 733910 -1 61041 13 12371 63921 2526758 365216 15.5884 15.5884 -2563.65 -15.5884 0 0 4.52633e+06 5773.37 1.61 2.02 0.72 -1 -1 1.61 1.14017 1.00737 -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 28.72 vpr 70.14 MiB -1 -1 19.91 45044 3 0.67 -1 -1 35452 -1 -1 44 196 1 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71828 196 193 1201 1346 1 607 434 15 15 225 io auto 31.5 MiB 0.79 2924 143288 42391 88468 12429 70.1 MiB 0.70 0.01 2.18307 -1105.54 -2.18307 2.18307 0.47 0.00366212 0.00341729 0.333891 0.310594 40 5977 15 1.03862e+07 2.91934e+06 568276. 2525.67 3.57 1.23727 1.13314 21782 113316 -1 5329 11 1700 2587 187113 48920 2.5066 2.5066 -1182.04 -2.5066 0 0 712852. 3168.23 0.17 0.16 0.11 -1 -1 0.17 0.113224 0.105684 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 3.56 vpr 65.28 MiB -1 -1 0.48 18496 3 0.09 -1 -1 33264 -1 -1 68 99 1 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66844 99 130 344 474 1 227 298 12 12 144 clb auto 26.4 MiB 0.28 665 70943 20214 37821 12908 65.3 MiB 0.26 0.00 1.89985 -118.566 -1.89985 1.89985 0.28 0.00130138 0.00123193 0.101489 0.0957523 34 1540 15 5.66058e+06 4.21279e+06 293035. 2034.97 0.82 0.368758 0.33821 12374 55836 -1 1457 10 403 605 42523 12642 1.99363 1.99363 -143.624 -1.99363 0 0 360780. 2505.42 0.08 0.06 0.06 -1 -1 0.08 0.0350922 0.0325653 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 9.67 vpr 68.42 MiB -1 -1 0.56 21980 5 0.19 -1 -1 33884 -1 -1 32 162 0 5 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70060 162 96 1075 892 1 666 295 16 16 256 mult_36 auto 29.5 MiB 0.27 4888 98395 35924 54623 7848 68.4 MiB 0.68 0.01 15.9849 -1245.5 -15.9849 15.9849 0.53 0.00320112 0.00300688 0.336242 0.316142 52 12010 41 1.21132e+07 3.70461e+06 805949. 3148.24 4.85 1.09429 1.01247 26552 162987 -1 9148 19 3314 5627 1080193 297034 17.378 17.378 -1353.55 -17.378 0 0 1.06067e+06 4143.25 0.24 0.43 0.16 -1 -1 0.24 0.156249 0.145747 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 15.75 vpr 67.16 MiB -1 -1 0.40 21156 5 0.12 -1 -1 33328 -1 -1 22 66 0 5 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68768 66 96 778 595 1 467 189 16 16 256 mult_36 auto 28.4 MiB 0.56 3517 47885 16325 27094 4466 67.2 MiB 0.40 0.01 12.1762 -748.789 -12.1762 12.1762 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 626424 114 102 35834 31925 1 16897 2420 56 56 3136 clb auto 279.1 MiB 70.81 224666 1805060 668533 1109456 27071 611.7 MiB 64.72 0.55 75.1122 -53345.7 -75.1122 75.1122 13.40 0.101362 0.0900982 12.5616 10.6146 -1 -1 -1 -1 88 335261 49 1.8697e+08 1.43756e+08 1.84122e+07 5871.24 134.02 47.1194 39.1334 423474 3861999 -1 307396 22 65997 258491 13780558 2468289 76.0017 76.0017 -64554.6 -76.0017 0 0 2.30976e+07 7365.31 1.10 10.19 3.64 -1 -1 1.10 6.17356 5.28565 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 2692.08 vpr 2.42 GiB -1 -1 242.89 1496112 97 858.98 -1 -1 355104 -1 -1 7513 114 168 32 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2535652 114 102 120350 108159 1 57345 7929 103 103 10609 clb auto 892.1 MiB 262.75 1003045 9728742 4018902 5663791 46049 2004.2 MiB 480.49 3.14 72.4024 -329114 -72.4024 72.4024 47.02 0.346214 0.301919 48.3359 40.4685 -1 -1 -1 -1 124 1323068 31 6.46441e+08 5.09602e+08 8.61045e+07 8116.18 587.22 199.076 163.111 1699828 18865638 -1 1270470 22 208280 903882 50603811 8413337 73.1548 73.1548 -457667 -73.1548 0 0 1.09063e+08 10280.2 5.97 39.87 20.11 -1 -1 5.97 22.9615 19.528 + k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 5532.81 vpr 2.11 GiB -1 -1 301.74 1243688 25 2880.43 -1 -1 369296 -1 -1 6763 36 159 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2217356 36 356 185159 159806 1 63309 7341 98 98 9604 clb auto 1056.9 MiB 254.50 722860 10062756 3907097 5967087 188572 2054.1 MiB 616.55 3.41 47.3986 -303024 -47.3986 47.3986 45.23 0.338735 0.29516 55.1437 45.9685 -1 -1 -1 -1 126 949879 27 5.9175e+08 4.62277e+08 7.90658e+07 8232.59 1240.96 214.222 174.297 1551988 17290692 -1 919494 20 208733 484691 28296676 5077184 47.6251 47.6251 -321060 -47.6251 0 0 9.99791e+07 10410.1 5.20 27.91 18.77 -1 -1 5.20 19.465 16.7334 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt index 87e9637f9ad..f1eeb0d6e78 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt @@ -1,22 +1,22 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml arm_core.v common 277.11 vpr 289.11 MiB -1 -1 16.67 124648 20 39.27 -1 -1 72328 -1 -1 679 133 25 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 296044 133 179 14228 14085 1 6986 1016 36 36 1296 memory auto 149.9 MiB 23.02 111869 506411 160230 326278 19903 181.8 MiB 9.47 0.08 19.5094 -192112 -19.5094 19.5094 4.12 0.0160466 0.0136643 1.86358 1.55727 154 199903 32 7.21828e+07 5.02946e+07 1.28857e+07 9942.66 153.26 8.23573 7.08873 239994 2946416 -1 183903 16 33799 138265 51564315 11944708 22.41 22.41 -214787 -22.41 -3.1378 -0.29436 1.62481e+07 12537.1 5.26 10.90 2.38 -1 -1 5.26 1.4659 1.3784 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bgm.v common 434.85 vpr 712.33 MiB -1 -1 33.46 637524 14 62.12 -1 -1 123408 -1 -1 2287 257 0 11 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 729428 257 32 36080 33722 1 18672 2587 58 58 3364 clb auto 366.8 MiB 41.13 238750 1777787 613628 1135373 28786 691.6 MiB 44.36 0.36 16.9078 -22798.4 -16.9078 16.9078 38.14 0.0417663 0.0365797 5.01023 4.34011 114 489515 43 2.00088e+08 1.27615e+08 2.67492e+07 7951.60 147.45 22.3155 19.5798 548026 6020043 -1 456285 20 103684 494058 43713903 7882929 19.3528 19.3528 -25719.6 -19.3528 0 0 3.36466e+07 10002.0 12.44 11.94 4.53 -1 -1 12.44 3.97353 3.71849 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml blob_merge.v common 87.69 parmys 262.07 MiB -1 -1 8.08 268356 5 3.85 -1 -1 58680 -1 -1 447 36 0 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 179696 36 100 10178 7632 1 2978 583 27 27 729 clb auto 104.4 MiB 16.70 43318 219643 62652 141928 15063 140.1 MiB 3.02 0.03 13.6111 -2272.14 -13.6111 13.6111 2.20 0.00651588 0.00551055 0.768924 0.662803 110 84751 33 3.93038e+07 2.40906e+07 5.33614e+06 7319.81 41.58 4.4518 3.87219 114714 1189977 -1 77052 17 14017 69317 4925517 913768 15.4853 15.4853 -2667.39 -15.4853 0 0 6.77266e+06 9290.34 1.99 1.35 0.86 -1 -1 1.99 0.624448 0.586094 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml boundtop.v common 17.08 vpr 71.96 MiB -1 -1 9.15 48936 3 0.67 -1 -1 39220 -1 -1 45 196 1 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 73692 196 193 1201 1346 1 604 435 15 15 225 io auto 33.8 MiB 0.47 2981 150312 44495 93614 12203 72.0 MiB 0.47 0.01 2.05507 -979.869 -2.05507 2.05507 0.57 0.00161266 0.00148292 0.165224 0.151168 40 7176 44 1.03862e+07 2.97323e+06 618415. 2748.51 3.52 0.779086 0.725008 23732 127356 -1 6238 14 2121 3542 344117 91418 2.57674 2.57674 -1194.23 -2.57674 -0.478269 -0.152189 773047. 3435.76 0.25 0.14 0.09 -1 -1 0.25 0.0824519 0.078801 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 3.66 vpr 66.66 MiB -1 -1 0.24 21888 3 0.09 -1 -1 36920 -1 -1 65 99 1 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 68260 99 130 344 474 1 221 295 12 12 144 clb auto 28.3 MiB 0.10 584 75832 24915 37314 13603 66.7 MiB 0.14 0.00 1.60782 -108.554 -1.60782 1.60782 0.30 0.000408101 0.000365301 0.032699 0.0291703 46 1375 14 5.66058e+06 4.05111e+06 408669. 2837.98 1.60 0.165947 0.151987 14568 82464 -1 1241 9 501 815 42163 14297 1.90052 1.90052 -138.848 -1.90052 -0.522528 -0.192271 525203. 3647.24 0.16 0.02 0.06 -1 -1 0.16 0.0164117 0.0156824 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diffeq1.v common 13.23 vpr 69.73 MiB -1 -1 0.30 25348 5 0.16 -1 -1 38040 -1 -1 26 162 0 5 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 71408 162 96 1075 892 1 662 289 16 16 256 mult_36 auto 31.7 MiB 0.29 5020 87194 31634 49300 6260 69.7 MiB 0.37 0.01 15.5513 -1198.01 -15.5513 15.5513 0.60 0.00108968 0.00087173 0.117896 0.106419 62 11041 23 1.21132e+07 3.38124e+06 1.04918e+06 4098.38 9.27 0.629926 0.579055 30184 211102 -1 9365 22 3684 6482 1932785 501322 17.3515 17.3515 -1402.06 -17.3515 0 0 1.29183e+06 5046.22 0.37 0.35 0.14 -1 -1 0.37 0.0801783 0.0761602 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diffeq2.v common 16.37 vpr 68.38 MiB -1 -1 0.22 24472 5 0.12 -1 -1 37504 -1 -1 16 66 0 5 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 70016 66 96 778 595 1 452 183 16 16 256 mult_36 auto 30.2 MiB 0.25 3796 47931 18238 24999 4694 68.4 MiB 0.23 0.01 11.6653 -721.689 -11.6653 11.6653 0.61 0.0021724 0.000634322 0.0820875 0.0733953 54 8985 24 1.21132e+07 2.8423e+06 903890. 3530.82 12.65 0.47082 0.431882 28908 188420 -1 7667 19 3422 6989 2894348 736724 13.1378 13.1378 -884.515 -13.1378 0 0 1.17254e+06 4580.24 0.33 0.47 0.12 -1 -1 0.33 0.054892 0.0522077 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml LU8PEEng.v common 453.19 vpr 634.28 MiB -1 -1 40.35 458136 97 67.61 -1 -1 116280 -1 -1 1817 114 45 8 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 649504 114 102 35834 31925 1 16655 2086 52 52 2704 clb auto 338.8 MiB 38.84 215398 1480939 529962 920626 30351 592.6 MiB 35.90 0.30 63.9023 -51832.3 -63.9023 63.9023 29.27 0.0365643 0.0313887 4.72225 3.98955 118 403134 41 1.58905e+08 1.25757e+08 2.19720e+07 8125.73 179.07 22.5222 19.4447 445196 4945367 -1 365440 26 84812 347712 59122473 12667064 72.9598 72.9598 -67594.2 -72.9598 -22.3536 -0.293253 2.76197e+07 10214.4 10.15 15.98 3.68 -1 -1 10.15 3.82828 3.51735 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml LU32PEEng.v common 4545.11 vpr 2.15 GiB -1 -1 128.48 1499332 97 635.41 -1 -1 358708 -1 -1 6264 114 168 32 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 2253068 114 102 120350 108159 1 57393 6680 94 94 8836 clb auto 1099.3 MiB 142.33 1002377 7741412 3101845 4587037 52530 1910.5 MiB 279.40 2.10 61.1772 -294786 -61.1772 61.1772 110.76 0.150743 0.129744 22.1123 18.9696 164 1599216 47 5.40921e+08 4.42296e+08 9.81028e+07 11102.6 2935.70 80.2872 69.5089 1741328 23094485 -1 1497489 23 245053 1111111 345304904 91442091 72.177 72.177 -449510 -72.177 -38.9067 -0.292146 1.25175e+08 14166.5 51.93 126.42 20.24 -1 -1 51.93 14.3855 13.1443 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mcml.v common 4052.63 vpr 2.22 GiB -1 -1 164.66 1254260 25 2216.02 -1 -1 373144 -1 -1 6092 36 159 27 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 2323188 36 356 185159 159806 1 63968 6670 93 93 8649 clb auto 1312.7 MiB 122.70 764984 9043966 3452533 5377457 213976 2034.1 MiB 415.93 2.64 44.0249 -277627 -44.0249 44.0249 108.37 0.156207 0.128577 24.3516 20.2318 154 1118635 43 5.27943e+08 4.26118e+08 9.06356e+07 10479.3 795.63 98.3709 83.4586 1641104 21087044 -1 1050884 22 254701 613161 130623601 28909159 47.7077 47.7077 -351690 -47.7077 -0.240863 -0.0215478 1.14427e+08 13230.1 50.66 42.81 17.78 -1 -1 50.66 12.7798 11.6449 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkDelayWorker32B.v common 81.80 vpr 381.34 MiB -1 -1 8.92 121524 5 3.40 -1 -1 48636 -1 -1 465 506 44 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 390492 506 553 3236 3734 1 2854 1568 50 50 2500 memory auto 59.1 MiB 3.82 16229 1176113 568893 419592 187628 381.3 MiB 3.45 0.04 6.96637 -2056.03 -6.96637 6.96637 26.67 0.0110014 0.0102196 1.51912 1.39252 38 25725 17 1.47946e+08 4.91733e+07 7.51727e+06 3006.91 17.42 4.40965 4.1239 284136 1605944 -1 24262 17 4753 6161 4413542 1107869 7.71942 7.71942 -2574.22 -7.71942 -2.60855 -0.216197 9.46795e+06 3787.18 3.63 1.26 1.04 -1 -1 3.63 0.594962 0.567469 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkPktMerge.v common 25.63 vpr 72.07 MiB -1 -1 0.91 29184 2 0.11 -1 -1 37840 -1 -1 27 311 15 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 73804 311 156 1015 1158 1 965 509 28 28 784 memory auto 34.2 MiB 0.53 8982 197516 69517 118417 9582 72.1 MiB 0.65 0.01 4.2275 -4143.2 -4.2275 4.2275 2.35 0.00294516 0.00258436 0.247937 0.21669 36 16496 41 4.25198e+07 9.67514e+06 2.12999e+06 2716.82 15.87 1.26374 1.13519 83724 436647 -1 14920 15 3351 3803 2953163 794022 4.6504 4.6504 -4999.11 -4.6504 -9.7666 -0.29768 2.61523e+06 3335.75 0.93 0.60 0.28 -1 -1 0.93 0.120155 0.111439 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 30.85 vpr 83.23 MiB -1 -1 4.12 55588 5 1.66 -1 -1 42932 -1 -1 149 193 5 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 85224 193 205 2718 2652 1 1332 552 20 20 400 memory auto 45.8 MiB 1.29 10421 235904 85730 126610 23564 83.2 MiB 1.30 0.02 4.51877 -2546.56 -4.51877 4.51877 1.07 0.00365451 0.00316066 0.355002 0.307152 70 21547 47 2.07112e+07 1.07702e+07 1.91061e+06 4776.53 16.53 1.28063 1.14003 50878 398303 -1 18601 27 5203 13861 2099937 567638 5.29174 5.29174 -3059.47 -5.29174 -15.9103 -0.360359 2.38830e+06 5970.76 0.71 0.66 0.29 -1 -1 0.71 0.266539 0.248322 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml or1200.v common 154.07 vpr 112.54 MiB -1 -1 3.35 66424 8 3.17 -1 -1 44760 -1 -1 197 385 2 1 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 115244 385 362 4415 4299 1 2339 947 26 26 676 io auto 60.2 MiB 2.89 28988 521523 209405 290824 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k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 27.67 vpr 81.39 MiB -1 -1 8.40 52340 5 1.67 -1 -1 39184 -1 -1 153 193 5 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83348 193 205 2718 2652 1 1312 556 20 20 400 memory auto 40.5 MiB 1.63 10418 229056 84448 119534 25074 81.4 MiB 1.94 0.02 4.83454 -2775.8 -4.83454 4.83454 0.46 0.00747105 0.00675587 0.803493 0.724427 -1 -1 -1 -1 70 21360 50 2.07112e+07 1.09858e+07 1.91061e+06 4776.53 9.06 2.90045 2.57962 50878 398303 -1 18326 19 5117 13726 1090691 249377 5.12414 5.12414 -2964.88 -5.12414 -9.06217 -0.29768 2.38830e+06 5970.76 0.08 0.60 0.34 -1 -1 0.08 0.364174 0.332881 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml or1200.v common 59.32 vpr 146.60 MiB -1 -1 6.80 62912 8 3.09 -1 -1 40812 -1 -1 204 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 150116 385 362 4415 4299 1 2326 954 26 26 676 io auto 51.4 MiB 3.83 30125 531376 214642 295474 21260 95.4 MiB 5.55 0.06 8.97942 -9890.27 -8.97942 8.97942 0.83 0.0158337 0.0147615 1.8938 1.73964 -1 -1 -1 -1 114 54501 40 3.69863e+07 1.24864e+07 5.08094e+06 7516.19 31.17 8.59193 7.86741 107668 1126034 -1 49619 16 11645 40890 3693110 712663 9.15851 9.15851 -10214.8 -9.15851 0 0 6.39786e+06 9464.29 0.24 1.46 1.02 -1 -1 0.24 0.68108 0.635331 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 25.96 vpr 82.90 MiB -1 -1 4.81 42388 3 0.69 -1 -1 37636 -1 -1 119 236 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84888 236 305 3199 3011 1 1524 667 19 19 361 io auto 42.1 MiB 2.05 12644 286141 98277 171517 16347 82.9 MiB 2.21 0.03 4.5478 -2822.52 -4.5478 4.5478 0.42 0.00865554 0.00800574 0.905484 0.832826 -1 -1 -1 -1 80 25223 29 1.72706e+07 9.33739e+06 1.90610e+06 5280.05 11.52 3.79468 3.45284 48118 405907 -1 22830 19 6383 17788 1956842 481346 4.7575 4.7575 -3031.05 -4.7575 -1.54347 -0.0248686 2.39503e+06 6634.44 0.08 0.78 0.34 -1 -1 0.08 0.409568 0.378879 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml sha.v common 18.13 vpr 80.55 MiB -1 -1 3.45 44440 3 1.25 -1 -1 39768 -1 -1 121 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82488 38 36 2739 2488 1 984 195 15 15 225 clb auto 39.8 MiB 1.29 8617 34660 8559 23743 2358 80.6 MiB 0.86 0.01 10.0462 -2585.64 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10.3557 10.3557 -7116.46 -10.3557 -31.3027 -0.291039 1.25485e+06 6402.29 0.04 0.32 0.18 -1 -1 0.04 0.147208 0.133753 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision0.v common 71.25 vpr 232.06 MiB -1 -1 13.84 99732 5 5.91 -1 -1 66224 -1 -1 683 169 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 237628 169 197 23225 21365 1 6228 1049 33 33 1089 clb auto 145.1 MiB 8.78 39077 555161 184104 348094 22963 204.6 MiB 7.06 0.07 3.40795 -14164.9 -3.40795 3.40795 1.21 0.0300798 0.025615 3.1673 2.69001 -1 -1 -1 -1 62 66511 37 6.0475e+07 3.68097e+07 4.96186e+06 4556.35 18.00 12.1219 10.1215 136702 1027405 -1 58701 14 16735 29853 1708107 404784 3.86533 3.86533 -15733.8 -3.86533 0 0 6.10319e+06 5604.39 0.24 1.75 0.82 -1 -1 0.24 1.48602 1.32181 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision1.v common 161.44 vpr 284.95 MiB -1 -1 11.10 122472 3 10.03 -1 -1 73980 -1 -1 735 115 0 40 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 291788 115 145 22864 19301 1 9598 1035 40 40 1600 mult_36 auto 143.0 MiB 8.97 82595 545267 173911 346139 25217 218.4 MiB 7.65 0.07 5.87645 -23504 -5.87645 5.87645 2.13 0.0172846 0.0150048 2.60308 2.21352 -1 -1 -1 -1 90 140847 35 9.16046e+07 5.54529e+07 1.01064e+07 6316.51 99.93 17.3403 14.5121 231184 2180983 -1 126035 16 32563 55258 9268189 2118021 5.97657 5.97657 -26242 -5.97657 0 0 1.25697e+07 7856.08 0.53 3.38 1.90 -1 -1 0.53 1.62332 1.44597 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision2.v common 399.39 vpr 1.18 GiB -1 -1 14.77 195404 3 4.42 -1 -1 152116 -1 -1 1699 149 0 179 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1238432 149 182 55415 37074 1 28457 2209 80 80 6400 mult_36 auto 291.4 MiB 30.42 282130 2015409 700203 1241042 74164 1209.4 MiB 50.25 0.38 13.0924 -51849.3 -13.0924 13.0924 35.54 0.0801169 0.0709152 12.035 10.4119 -1 -1 -1 -1 98 402851 42 3.90281e+08 1.62448e+08 4.51112e+07 7048.62 201.61 57.5437 48.7486 982540 10083220 -1 377967 20 98609 121118 18647821 4175431 13.5095 13.5095 -57446.5 -13.5095 0 0 5.68725e+07 8886.33 2.78 8.88 9.38 -1 -1 2.78 4.65647 4.05835 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision3.v common 2.77 vpr 65.82 MiB -1 -1 0.95 22856 4 0.13 -1 -1 32576 -1 -1 13 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67400 11 2 303 283 2 70 26 7 7 49 clb auto 26.2 MiB 0.11 226 786 179 539 68 65.8 MiB 0.04 0.00 2.04209 -156.405 -2.04209 1.90335 0.04 0.000811437 0.000734582 0.0207311 0.0191518 -1 -1 -1 -1 26 591 13 1.07788e+06 700622 75813.7 1547.22 0.37 0.188328 0.159692 3816 13734 -1 488 13 265 523 16601 6739 2.12916 1.93187 -166.884 -2.12916 0 0 91376.6 1864.83 0.00 0.04 0.01 -1 -1 0.00 0.0283251 0.0252471 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt index 7fc0b70f933..cf218b6f42d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt @@ -1,20 +1,20 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 764024 257 32 36080 33722 1 19553 3015 63 63 3969 clb auto 301.6 MiB 92.59 246763 2158443 772925 1359244 26274 746.1 MiB 59.23 0.53 19.4596 -25520.8 -19.4596 19.4596 43.69 0.0991431 0.0880274 11.4343 9.85355 -1 -1 -1 -1 74 397392 33 2.36641e+08 1.5068e+08 2.02178e+07 5093.92 116.44 33.3094 28.6876 502298 4195434 -1 378911 20 104646 475755 22175267 3259151 19.4991 19.4991 -26097.4 -19.4991 0 0 2.53694e+07 6391.88 8.94 10.08 4.11 -1 -1 8.94 4.89274 4.39544 -k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 88.72 parmys 272.51 MiB -1 -1 13.84 279048 5 4.67 -1 -1 58908 -1 -1 487 36 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om 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39.2846 32.3608 494362 4028736 -1 366303 20 98427 446372 17944375 2776232 18.5784 18.5784 -26041.2 -18.5784 0 0 2.43753e+07 6141.41 1.21 11.43 3.66 -1 -1 1.21 5.85046 5.10781 + k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 78.97 parmys 261.77 MiB -1 -1 15.49 268052 5 3.27 -1 -1 55068 -1 -1 499 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 151748 36 100 10178 7632 1 2726 635 29 29 841 clb auto 89.3 MiB 20.97 41290 240699 69942 155074 15683 136.3 MiB 4.72 0.05 15.0315 -2426.67 -15.0315 15.0315 0.96 0.0200853 0.0181387 1.92947 1.71159 -1 -1 -1 -1 68 72348 36 4.4999e+07 2.68931e+07 3.78783e+06 4503.96 21.04 7.0819 6.06747 99460 760244 -1 61879 16 12452 65489 2491571 367156 14.9612 14.9612 -2605.63 -14.9612 0 0 4.70015e+06 5588.76 0.17 1.60 0.65 -1 -1 0.17 0.96287 0.854503 + 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3.69863e+07 1.49655e+07 4.42570e+06 6546.89 20.29 8.10528 7.4405 97812 938682 -1 40817 16 8863 29554 1529165 270024 9.38639 9.38639 -10275 -9.38639 0 0 5.60562e+06 8292.34 0.21 1.07 0.90 -1 -1 0.21 0.671683 0.625212 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 20.40 vpr 83.15 MiB -1 -1 4.95 42652 3 0.69 -1 -1 37712 -1 -1 129 236 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85144 236 305 3199 3011 1 1520 677 19 19 361 io auto 42.3 MiB 2.96 12613 265096 95493 155775 13828 83.1 MiB 2.04 0.03 4.87079 -2867.74 -4.87079 4.87079 0.39 0.00874694 0.00809124 0.837199 0.769496 -1 -1 -1 -1 60 22507 29 1.72706e+07 9.87633e+06 1.37250e+06 3801.94 5.31 2.82995 2.58049 40123 275431 -1 20290 17 5897 15357 1368544 349388 4.89215 4.89215 -3057.94 -4.89215 0 0 1.72840e+06 4787.81 0.06 0.66 0.24 -1 -1 0.06 0.37961 0.351635 + k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 18.68 vpr 81.04 MiB -1 -1 3.48 45112 3 1.23 -1 -1 39672 -1 -1 141 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82988 38 36 2739 2488 1 1022 215 17 17 289 clb auto 40.1 MiB 1.97 8958 42653 11395 28389 2869 81.0 MiB 0.93 0.01 10.0306 -2595.46 -10.0306 10.0306 0.30 0.00563668 0.00499161 0.411349 0.362575 -1 -1 -1 -1 58 15080 45 1.34605e+07 7.59905e+06 1.03370e+06 3576.80 7.09 3.0793 2.62682 31195 207102 -1 12819 22 4248 9862 350375 63434 10.8941 10.8941 -2909.82 -10.8941 0 0 1.31783e+06 4559.95 0.04 0.45 0.18 -1 -1 0.04 0.322361 0.28551 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 14.62 vpr 72.09 MiB -1 -1 3.90 32592 16 0.46 -1 -1 34784 -1 -1 60 45 3 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73824 45 32 1192 1151 1 782 141 14 14 196 memory auto 32.6 MiB 2.64 6823 26859 7335 15944 3580 72.1 MiB 0.56 0.01 10.958 -7233.76 -10.958 10.958 0.20 0.00348886 0.00309362 0.282542 0.250806 -1 -1 -1 -1 66 13449 49 9.20055e+06 5.27364e+06 787562. 4018.17 4.34 1.29546 1.12707 22236 154735 -1 10952 14 3335 8795 693161 168301 11.3764 11.3764 -7707.18 -11.3764 0 0 978561. 4992.66 0.03 0.31 0.14 -1 -1 0.03 0.156586 0.142149 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 70.08 vpr 230.16 MiB -1 -1 13.83 100176 5 5.66 -1 -1 66176 -1 -1 721 169 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 235688 169 197 23225 21365 1 6061 1087 34 34 1156 clb auto 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5.72315e+07 8.06023e+06 5037.64 224.38 20.2923 16.9388 200832 1659634 -1 114258 16 31257 49053 7202028 1662365 5.39064 5.39064 -25594 -5.39064 0 0 1.00808e+07 6300.50 0.41 3.41 1.46 -1 -1 0.41 1.81066 1.60735 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 283.85 vpr 1.02 GiB -1 -1 16.34 195452 3 5.92 -1 -1 152084 -1 -1 1699 149 0 179 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1072748 149 182 55415 37074 1 28414 2209 80 80 6400 mult_36 auto 290.2 MiB 30.79 283700 2029789 714222 1242257 73310 1047.6 MiB 50.81 0.36 13.4478 -51665.2 -13.4478 13.4478 27.71 0.0798307 0.0706002 12.5716 10.7877 -1 -1 -1 -1 90 390411 49 3.90281e+08 1.62448e+08 3.88106e+07 6064.16 94.93 41.9844 35.7412 876284 8162653 -1 372587 18 96713 115717 14180687 3026082 14.5611 14.5611 -57854.4 -14.5611 0 0 4.85641e+07 7588.14 2.99 7.91 7.71 -1 -1 2.99 4.41036 3.90021 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.78 vpr 65.62 MiB -1 -1 0.94 23248 4 0.13 -1 -1 32564 -1 -1 15 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67192 11 2 303 283 2 78 28 7 7 49 clb auto 26.0 MiB 0.21 280 994 173 731 90 65.6 MiB 0.04 0.00 2.0401 -164.361 -2.0401 1.90163 0.03 0.000802622 0.000736286 0.0231253 0.0212941 -1 -1 -1 -1 22 397 12 1.07788e+06 808410 57331.5 1170.03 0.32 0.150968 0.128977 3372 10412 -1 355 11 172 254 4023 1475 2.14906 1.91429 -169.055 -2.14906 0 0 72669.7 1483.05 0.00 0.02 0.01 -1 -1 0.00 0.0172996 0.0159743 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/complex_switch/config/golden_results.txt index 26f35c0cb09..0f7c6adf9a1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/complex_switch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/complex_switch/config/golden_results.txt @@ -1,15 +1,15 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml bgm.v common 1007.56 61.80 380120 33 527.79 -1 -1 155856 -1 -1 5518 257 0 11 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 740824 257 32 44336 43851 1 42630 5818 80 80 6400 clb auto 12.21 380622 220.45 1.55 11.7092 -17497.4 -11.7092 11.7092 2.55 0.144862 0.12537 17.4904 15.2114 629302 264104 928789 157555407 31822408 3.53436e+07 2.2827e+07 7.29424e+07 11397.2 22 13.5217 13.5217 -20134.9 -13.5217 0 0 45.19 25.7888 22.6024 92.57 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml blob_merge.v common 173.12 1.10 63176 29 108.95 -1 -1 71316 -1 -1 1320 36 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 191492 36 100 10431 10531 1 9865 1456 41 41 1681 clb auto 1.99 86784 22.95 0.16 8.5404 -2112.82 -8.5404 8.5404 0.47 0.0301432 0.0276364 4.04612 3.56933 133541 32265 117599 16941686 3415266 8.95136e+06 5.148e+06 1.84779e+07 10992.2 17 9.80674 9.80674 -2510.99 -9.80674 0 0 5.59 5.6366 5.01098 20.62 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml boundtop.v common 5.68 1.71 47500 3 0.48 -1 -1 41592 -1 -1 95 114 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 48688 114 193 467 660 1 374 402 13 13 169 clb auto 0.06 924 0.58 0.01 0.986465 -136.23 -0.986465 0.986465 0.02 0.00103145 0.000965443 0.15685 0.14477 1391 652 1684 191231 53291 666600 370500 1.59550e+06 9440.85 10 1.24204 1.24204 -162.021 -1.24204 0 0 0.07 0.185245 0.171535 0.90 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml LU8PEEng.v common 754.34 53.97 218988 206 316.61 -1 -1 103528 -1 -1 4460 114 83 8 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 796396 114 102 38946 38672 1 36247 4767 86 86 7396 memory auto 11.71 361378 161.21 1.05 64.8355 -42040.9 -64.8355 64.8355 2.82 0.114274 0.102112 16.3456 14.0063 512938 127210 434360 149093030 54728319 4.18276e+07 2.52125e+07 8.44414e+07 11417.2 22 72.5688 72.5688 -74126.1 -72.5688 -91.783 -0.36083 62.77 23.6657 20.4208 103.26 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mkDelayWorker32B.v common 132.24 2.33 70980 6 8.96 -1 -1 56172 -1 -1 556 506 80 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 568592 506 553 3331 3884 1 3325 1695 82 82 6724 memory auto 1.85 19665 8.00 0.05 5.41315 -1403.25 -5.41315 5.41315 2.41 0.0174197 0.0158973 3.90301 3.54119 22244 5019 6192 6593679 2064896 3.85878e+07 8.78824e+06 7.66484e+07 11399.2 22 5.80412 5.80412 -1685.69 -5.80412 -22.0148 -0.295672 2.56 4.86192 4.43996 84.17 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mkSMAdapter4B.v common 29.64 0.65 30420 11 3.49 -1 -1 41004 -1 -1 290 193 10 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 127912 193 205 2764 2969 1 2139 698 37 37 1369 memory auto 0.51 15446 4.42 0.03 3.89872 -2235.27 -3.89872 3.89872 0.32 0.00590474 0.00534424 1.20788 1.0808 23806 7872 25612 4281475 1054152 7.45627e+06 1.95848e+06 1.49196e+07 10898.2 17 4.18699 4.18699 -2538.95 -4.18699 -21.4015 -0.375057 1.25 1.52081 1.37113 14.09 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml or1200.v common 32.90 1.07 41300 45 6.40 -1 -1 45596 -1 -1 537 385 4 1 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 92804 385 394 5238 5569 1 4569 1321 27 27 729 io clb auto 1.11 44444 9.30 0.08 12.7514 -9719.77 -12.7514 12.7514 0.15 0.0159747 0.0147929 2.05202 1.88151 64764 15911 59477 9238454 2259188 4.06709e+06 2.54409e+06 7.75339e+06 10635.7 18 13.7756 13.7756 -11602 -13.7756 0 0 3.06 2.89076 2.66235 7.23 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 17.99 0.91 33104 12 1.88 -1 -1 44080 -1 -1 238 214 0 9 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 77060 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 0.54 16418 3.03 0.03 3.92422 -1914.18 -3.92422 3.92422 0.14 0.00656181 0.00608415 0.846401 0.77718 24730 7679 24738 7723180 2175690 3.88769e+06 1.9974e+06 7.17610e+06 10615.5 17 4.06116 4.06116 -2255.58 -4.06116 0 0 1.92 1.16466 1.07723 6.24 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml sha.v common 1056.11 1.67 39192 31 1031.42 -1 -1 100716 -1 -1 415 38 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 75364 38 36 4183 4219 1 3300 489 24 24 576 clb auto 0.77 25354 4.42 0.04 9.82213 -3175.08 -9.82213 9.82213 0.11 0.00968855 0.00863616 1.1447 1.02024 42061 13032 51882 6455399 1522523 2.72374e+06 1.6185e+06 6.03346e+06 10474.8 21 11.2064 11.2064 -3705.85 -11.2064 0 0 2.08 1.71248 1.5389 5.33 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision0.v common 184.76 4.38 126752 7 107.05 -1 -1 68844 -1 -1 1804 157 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 271352 157 197 22240 22437 1 13748 2158 47 47 2209 clb auto 2.96 84220 26.17 0.21 2.22026 -8656.91 -2.22026 2.22026 0.59 0.037802 0.0340611 4.73764 4.08936 117937 41975 124776 15267155 3638031 1.16296e+07 7.0356e+06 2.45588e+07 11117.6 20 2.72481 2.72481 -10955.7 -2.72481 0 0 5.44 6.87096 6.02615 24.11 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision1.v common 175.37 5.77 113240 10 58.42 -1 -1 82300 -1 -1 1727 113 0 44 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 414756 113 145 23279 21144 1 16131 2029 62 62 3844 mult_36 auto 3.45 135603 29.79 0.23 4.15694 -16481.2 -4.15694 4.15694 1.23 0.0416329 0.0377454 5.68248 5.00686 178625 53804 143259 49277285 13572124 2.17057e+07 1.19625e+07 4.33614e+07 11280.3 14 4.46736 4.46736 -20025.7 -4.46736 0 0 12.50 7.51511 6.69767 44.30 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision2.v common 1241.54 5.79 173160 26 378.79 -1 -1 192276 -1 -1 5847 149 0 324 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 2498204 149 182 65520 55100 1 55662 6502 166 166 27556 mult_36 auto 15.45 721467 233.85 1.48 13.2018 -50280.1 -13.2018 13.2018 15.46 0.193755 0.179179 26.8642 23.8392 869347 249438 647829 149956053 38940076 1.58074e+08 6.12945e+07 3.19849e+08 11607.2 22 14.654 14.654 -65353.5 -14.654 0 0 49.45 38.371 34.2708 431.65 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml LU32PEEng.v common 3706.42 386.10 734200 205 1515.98 -1 -1 302652 -1 -1 15736 114 299 32 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 2969444 114 102 136917 135515 1 128781 16283 169 169 28561 memory auto 43.66 1655811 967.80 5.86 64.0741 -218355 -64.0741 64.0741 14.97 0.492406 0.419883 67.1686 57.7487 2154289 413940 1453578 564216810 202871066 1.64515e+08 8.9937e+07 3.31299e+08 11599.7 23 72.8832 72.8832 -433622 -72.8832 -167.502 -0.303936 215.96 94.8038 81.9137 404.70 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mcml.v common 10344.00 161.82 928172 119 8767.92 -1 -1 451996 -1 -1 12886 36 318 27 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 2934052 36 356 149309 148090 1 102868 13623 169 169 28561 memory auto 47.64 1306112 660.75 4.13 56.2791 -228686 -56.2791 56.2791 15.61 0.339155 0.289446 51.8499 44.2375 1254088 403135 1597976 260478491 64570437 1.64515e+08 7.97899e+07 3.31299e+08 11599.7 22 60.6003 60.6003 -331298 -60.6003 -2.30303 -0.226637 91.90 72.7285 62.7953 420.32 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml bgm.v common 820.31 vpr 818.98 MiB 22.94 379780 -1 -1 32 493.71 -1 -1 153968 -1 -1 5640 257 0 11 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 838636 257 32 45172 44687 1 43466 5940 82 82 6724 clb auto 274.6 MiB 11.17 384723 5705772 2258487 3417250 30035 819.0 MiB 186.67 1.36 13.3718 -18525.1 -13.3718 13.3718 0.03 0.110171 0.0987148 13.7144 11.3248 -1 -1 -1 -1 628874 14.4698 281218 6.47058 231943 834736 117799524 24198893 3.85878e+07 2.33028e+07 7.66484e+07 11399.2 22 1605176 15314284 -1 14.2738 14.2738 -20331.9 -14.2738 0 0 26.63 -1 -1 819.0 MiB 33.05 20.0089 16.6262 819.0 MiB -1 12.97 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml blob_merge.v common 117.17 vpr 229.33 MiB 0.80 62680 -1 -1 29 80.45 -1 -1 65976 -1 -1 1320 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 234836 36 100 10431 10531 1 9865 1456 41 41 1681 clb auto 79.6 MiB 1.19 88362 785111 276498 487029 21584 229.3 MiB 16.45 0.15 9.43813 -2197.84 -9.43813 9.43813 0.01 0.0259222 0.0233317 2.9831 2.58521 -1 -1 -1 -1 133197 13.5542 61268 6.23466 32071 117257 15958817 3230932 8.95136e+06 5.148e+06 1.84779e+07 10992.2 21 392750 3677203 -1 10.0034 10.0034 -2460.5 -10.0034 0 0 3.43 -1 -1 229.3 MiB 5.22 4.39364 3.77499 229.3 MiB -1 2.19 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml boundtop.v common 5.40 vpr 61.29 MiB 1.00 47020 -1 -1 3 0.73 -1 -1 36304 -1 -1 95 114 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62760 114 193 467 660 1 374 402 13 13 169 clb auto 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 92288 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 34.0 MiB 0.55 17879 291515 96968 176018 18529 90.1 MiB 2.35 0.03 4.04097 -2026.17 -4.04097 4.04097 0.00 0.00818863 0.00758309 0.716958 0.660563 -1 -1 -1 -1 25655 11.8335 11525 5.31596 7010 22783 3120920 787237 3.88769e+06 1.9974e+06 7.17610e+06 10615.5 17 154908 1423382 -1 4.23901 4.23901 -2367.29 -4.23901 0 0 2.27 -1 -1 90.1 MiB 0.98 1.04854 0.966038 90.1 MiB -1 0.80 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml sha.v common 507.60 abc 94.12 MiB 2.17 38620 -1 -1 31 490.25 -1 -1 96384 -1 -1 415 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 90192 38 36 4183 4219 1 3300 489 24 24 576 clb auto 42.1 MiB 0.67 25112 129464 32825 91043 5596 88.1 MiB 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2.45588e+07 11117.6 17 519358 4899383 -1 2.78227 2.78227 -10971.6 -2.78227 0 0 8.05 -1 -1 299.5 MiB 4.74 5.585 4.74193 299.5 MiB -1 3.06 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision1.v common 133.27 vpr 456.01 MiB 2.84 112712 -1 -1 10 59.54 -1 -1 78852 -1 -1 1727 113 0 44 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 466952 113 145 23279 21144 1 16131 2029 62 62 3844 mult_36 auto 128.9 MiB 3.17 140319 1388749 540237 823922 24590 456.0 MiB 27.34 0.30 4.23653 -17527.9 -4.23653 4.23653 0.01 0.0402543 0.0340353 4.47252 3.79948 -1 -1 -1 -1 184868 11.4640 78781 4.88534 55253 150418 23440921 5522616 2.17057e+07 1.19625e+07 4.33614e+07 11280.3 18 911886 8653859 -1 4.41908 4.41908 -20082.8 -4.41908 0 0 14.29 -1 -1 456.0 MiB 6.84 6.33271 5.40445 456.0 MiB -1 5.77 + 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15714 114 299 32 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3232424 114 102 136826 135424 1 128691 16261 169 169 28561 memory auto 800.1 MiB 40.90 1648550 26579554 11638314 14888034 53206 3156.7 MiB 1171.83 7.03 68.7296 -221934 -68.7296 68.7296 0.11 0.405372 0.35607 60.6857 50.9192 -1 -1 -1 -1 2147445 16.6973 966035 7.51135 404100 1427772 190149727 42382132 1.64515e+08 8.98512e+07 3.31299e+08 11599.7 24 6883162 66233393 -1 72.585 72.585 -429947 -72.585 -155.254 -0.302614 84.55 -1 -1 3156.7 MiB 77.49 84.8887 70.8614 3156.7 MiB -1 53.53 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mcml.v common 8788.85 vpr 3.04 GiB 79.87 925408 -1 -1 126 7881.76 -1 -1 448912 -1 -1 12851 36 318 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3192572 36 356 149244 148025 1 102799 13588 169 169 28561 memory auto 753.1 MiB 34.19 1266788 22541457 10109273 12375850 56334 3117.7 MiB 496.30 3.25 57.3765 -244260 -57.3765 57.3765 0.10 0.277208 0.238866 42.0788 34.9139 -1 -1 -1 -1 1214744 11.8214 565313 5.50140 378455 1542517 186457172 43247061 1.64515e+08 7.96532e+07 3.31299e+08 11599.7 22 6883162 66233393 -1 60.677 60.677 -381776 -60.677 -0.394532 -0.113558 111.64 -1 -1 3117.7 MiB 58.29 57.4924 47.84 3117.7 MiB -1 41.52 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor/config/golden_results.txt index 75973eec4cc..1ee7575e46d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor/config/golden_results.txt @@ -1,21 +1,21 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_mem32K_40nm.xml arm_core.v common 331.03 vpr 352.79 MiB 3.43 127948 -1 -1 25 78.58 -1 -1 67016 -1 -1 988 133 24 0 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 361256 133 179 17481 17660 1 8826 1324 39 39 1521 clb auto 160.6 MiB 14.98 140724 706223 235986 453985 16252 217.7 MiB 15.98 0.16 18.2294 -157339 -18.2294 18.2294 4.31 0.0518175 0.0450103 5.48347 4.5904 110 202350 37 8.65315e+07 6.64005e+07 1.06449e+07 6998.62 154.54 29.2861 24.3174 222560 2289922 -1 184414 17 36765 135743 9204794 1475613 18.3923 18.3923 -165829 -18.3923 0 0 1.35876e+07 8933.31 4.13 5.35 2.21 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v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 164148 36 100 6600 6700 1 2804 708 30 30 900 clb auto 85.7 MiB 5.72 45721 268798 80554 171964 16280 124.6 MiB 4.99 0.05 10.4727 -2786.41 -10.4727 10.4727 2.75 0.0200331 0.0180885 1.99302 1.75483 70 68828 17 4.8774e+07 3.08274e+07 4.18297e+06 4647.75 38.18 9.47628 8.14735 106732 854442 -1 63223 13 11344 57272 2422333 307988 10.6677 10.6677 -2866.66 -10.6677 0 0 5.26086e+06 5845.40 1.45 1.65 0.78 -1 -1 1.45 0.939592 0.842842 4998 5998 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml boundtop.v common 8.26 vpr 65.03 MiB 0.87 47140 -1 -1 2 0.48 -1 -1 36316 -1 -1 82 114 0 0 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca 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-0.442561 -0.200829 6.13894e+07 7253.00 2.94 22.83 9.40 -1 -1 2.94 16.5586 14.3201 54006 83427 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt index 5ac538a2499..f01850ef9aa 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt @@ -1,22 +1,22 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 308.61 vpr 305.05 MiB 3.27 126928 -1 -1 18 66.85 -1 -1 66760 -1 -1 1012 133 24 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 312376 133 179 18379 18161 1 8999 1348 39 39 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-k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 9.83 vpr 70.61 MiB 0.78 45096 -1 -1 3 0.57 -1 -1 37852 -1 -1 92 142 0 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72304 142 193 1069 1140 1 565 427 14 14 196 clb auto 32.6 MiB 0.80 1818 153092 57142 75216 20734 70.6 MiB 0.62 0.01 2.94229 -453.47 -2.94229 2.94229 0.44 0.00272405 0.00251166 0.275175 0.256617 36 4119 16 9.20055e+06 4.95825e+06 447080. 2281.02 2.64 1.06006 0.974555 18336 87587 -1 3545 13 1258 1911 94099 25244 3.69367 3.69367 -542.415 -3.69367 0 0 553089. 2821.88 0.13 0.13 0.09 -1 -1 0.13 0.0988352 0.0924831 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 4.53 vpr 65.50 MiB 0.05 9484 -1 -1 3 0.26 -1 -1 34496 -1 -1 65 99 1 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 67072 99 130 363 493 1 251 295 12 12 144 clb auto 27.2 MiB 0.20 638 73870 25767 36592 11511 65.5 MiB 0.24 0.00 2.16091 -202.101 -2.16091 2.16091 0.29 0.00118083 0.00111179 0.093124 0.0877216 50 1437 12 5.66058e+06 4.05111e+06 406307. 2821.58 1.89 0.405518 0.373885 13806 78043 -1 1327 8 569 730 52502 16881 2.61821 2.61821 -233.044 -2.61821 0 0 520805. 3616.70 0.11 0.05 0.08 -1 -1 0.11 0.0284497 0.026703 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 13.99 vpr 69.25 MiB 0.06 9280 -1 -1 6 0.19 -1 -1 33940 -1 -1 32 162 0 5 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70916 162 96 1075 884 1 667 295 16 16 256 mult_36 auto 31.2 MiB 0.46 4874 89566 32886 48812 7868 69.3 MiB 0.63 0.01 15.5719 -1192.19 -15.5719 15.5719 0.58 0.00327511 0.00307934 0.313023 0.294075 56 10920 33 1.21132e+07 3.70461e+06 870502. 3400.40 9.22 1.43467 1.33244 27064 172478 -1 8779 20 3096 5045 1985336 525030 17.2923 17.2923 -1368.07 -17.2923 0 0 1.11200e+06 4343.75 0.25 0.56 0.17 -1 -1 0.25 0.152842 0.143207 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 14.41 vpr 68.06 MiB 0.03 8460 -1 -1 6 0.15 -1 -1 34036 -1 -1 20 66 0 7 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69696 66 96 866 607 1 547 189 18 18 324 mult_36 auto 30.0 MiB 0.52 4724 52221 19081 29168 3972 68.1 MiB 0.51 0.01 12.2609 -733.741 -12.2609 12.2609 0.81 0.00272171 0.00257763 0.273527 0.259203 56 9880 19 1.57076e+07 3.84988e+06 1.13764e+06 3511.25 9.37 1.08023 1.01222 34996 227580 -1 9332 18 2524 4965 2261378 561627 13.3921 13.3921 -853.374 -13.3921 0 0 1.45243e+06 4482.80 0.33 0.57 0.21 -1 -1 0.33 0.121498 0.114731 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 107.53 vpr 361.92 MiB 1.42 69584 -1 -1 5 7.33 -1 -1 52920 -1 -1 456 506 45 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 370608 506 553 3519 4017 1 3099 1560 50 50 2500 memory auto 59.9 MiB 6.56 16861 1186324 579266 419415 187643 361.9 MiB 5.63 0.06 6.76827 -1937.28 -6.76827 6.76827 23.26 0.0224339 0.020226 3.05307 2.73026 40 24703 14 1.47946e+08 4.92362e+07 7.18436e+06 2873.75 43.14 9.49117 8.61044 260716 1475984 -1 23814 15 3905 5017 3925951 988139 7.57899 7.57899 -2448.16 -7.57899 0 0 8.97548e+06 3590.19 2.90 1.66 1.29 -1 -1 2.90 0.845545 0.785123 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 24.15 vpr 80.12 MiB 0.21 16748 -1 -1 2 0.14 -1 -1 33692 -1 -1 29 311 15 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82048 311 156 1019 1160 1 965 511 28 28 784 memory auto 33.3 MiB 0.68 8151 208795 74211 123852 10732 71.9 MiB 1.19 0.02 3.77691 -4038.98 -3.77691 3.77691 2.27 0.00554843 0.00487833 0.592245 0.51467 38 14576 26 4.25198e+07 9.78293e+06 2.03941e+06 2601.29 13.75 2.26322 1.99752 77878 418209 -1 13284 16 2916 3289 2664079 748370 4.13763 4.13763 -4801.24 -4.13763 0 0 2.58563e+06 3298.00 0.75 0.81 0.40 -1 -1 0.75 0.21968 0.198761 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 24.53 vpr 84.20 MiB 0.47 29304 -1 -1 4 1.88 -1 -1 37936 -1 -1 188 193 5 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86216 193 205 2863 2789 1 1455 591 20 20 400 memory auto 47.0 MiB 3.22 11478 258407 87714 143045 27648 84.2 MiB 1.97 0.02 4.57371 -2508.98 -4.57371 4.57371 1.04 0.00749779 0.0067406 0.85769 0.766693 56 20077 20 2.07112e+07 1.28721e+07 1.41661e+06 3541.53 10.45 3.10742 2.77127 43380 284034 -1 18046 16 5181 12425 986328 207359 4.99636 4.99636 -2921.82 -4.99636 0 0 1.80858e+06 4521.44 0.43 0.58 0.26 -1 -1 0.43 0.344018 0.316306 -k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 53.67 vpr 114.27 MiB 0.89 39788 -1 -1 8 4.31 -1 -1 41912 -1 -1 258 385 2 1 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 117016 385 394 4673 4537 1 2422 1040 27 27 729 io auto 62.8 MiB 9.22 31099 601478 234916 341577 24985 99.9 MiB 5.48 0.06 7.91028 -9390.87 -7.91028 7.91028 2.23 0.0167783 0.0155898 2.01423 1.8284 98 45582 18 3.93038e+07 1.53967e+07 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-k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 256.85 abc 92.51 MiB 2.09 38272 -1 -1 3 232.89 -1 -1 94728 -1 -1 156 38 0 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85824 38 36 2995 2744 1 1210 230 17 17 289 clb auto 47.2 MiB 2.42 11187 48102 12239 32898 2965 83.8 MiB 0.97 0.01 8.50665 -2425.54 -8.50665 8.50665 0.67 0.00570774 0.00499034 0.454841 0.394038 86 15535 20 1.34605e+07 8.40746e+06 1.47169e+06 5092.36 8.49 2.53112 2.17062 36379 299185 -1 14997 15 3639 10555 369332 60267 10.0216 10.0216 -2922.92 -10.0216 0 0 1.86203e+06 6443.01 0.42 0.39 0.32 -1 -1 0.42 0.285356 0.258031 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 15.68 vpr 73.31 MiB 0.29 20588 -1 -1 15 0.71 -1 -1 35832 -1 -1 65 45 3 1 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic 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8.64458 8.64458 -10958.4 -8.64458 0 0 5.38988e+06 7393.52 0.25 1.42 0.81 -1 -1 0.25 0.868994 0.807211 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 18.99 vpr 83.97 MiB 0.47 31632 -1 -1 3 1.30 -1 -1 40388 -1 -1 123 214 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85988 214 305 2963 2869 1 1444 650 19 19 361 io auto 42.9 MiB 2.34 11237 214514 71103 131344 12067 84.0 MiB 1.68 0.03 4.53 -2651.41 -4.53 4.53 0.30 0.0081428 0.00752702 0.697544 0.644697 -1 -1 -1 -1 58 21099 31 1.72706e+07 9.79696e+06 1.32779e+06 3678.09 8.10 3.22447 2.94147 39763 268823 -1 18983 16 5722 13316 1766310 456164 4.74311 4.74311 -2886.77 -4.74311 0 0 1.69263e+06 4688.74 0.06 0.69 0.28 -1 -1 0.06 0.345386 0.321329 + k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 272.73 abc 92.77 MiB 2.09 38268 -1 -1 3 250.47 -1 -1 94996 -1 -1 155 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85432 38 36 2995 2744 1 1203 229 17 17 289 clb auto 42.4 MiB 2.62 11670 42229 10578 28453 3198 83.4 MiB 1.05 0.02 9.56668 -2644.49 -9.56668 9.56668 0.30 0.00656702 0.00586724 0.468925 0.409101 -1 -1 -1 -1 68 16961 39 1.34605e+07 8.35357e+06 1.21205e+06 4193.96 7.72 3.3871 2.92303 32923 238265 -1 15449 21 4262 11796 386501 67599 10.0346 10.0346 -2927.77 -10.0346 0 0 1.50552e+06 5209.41 0.05 0.51 0.21 -1 -1 0.05 0.381624 0.341924 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 10.21 vpr 73.09 MiB 0.28 20756 -1 -1 15 0.70 -1 -1 35888 -1 -1 64 45 3 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74840 45 32 1275 1232 1 833 145 14 14 196 memory auto 33.5 MiB 3.02 7318 32445 8399 21096 2950 73.1 MiB 0.73 0.01 10.858 -7202.1 -10.858 10.858 0.20 0.00401825 0.00358124 0.372462 0.331214 -1 -1 -1 -1 62 14199 22 9.20055e+06 5.48922e+06 735792. 3754.04 2.60 1.09318 0.957143 21652 143691 -1 12039 14 3799 10270 769415 195252 11.2813 11.2813 -7721.94 -11.2813 0 0 913676. 4661.61 0.03 0.33 0.13 -1 -1 0.03 0.167019 0.15166 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 77.15 vpr 237.29 MiB 2.19 122604 -1 -1 5 8.30 -1 -1 70708 -1 -1 725 157 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 242980 157 197 23846 21799 1 6113 1079 34 34 1156 clb auto 153.0 MiB 11.42 40349 554279 179120 354733 20426 212.2 MiB 8.17 0.10 3.44133 -14164.6 -3.44133 3.44133 1.41 0.0419871 0.0368812 3.82221 3.26092 -1 -1 -1 -1 48 64709 42 6.50233e+07 3.90734e+07 3.79520e+06 3283.05 25.00 13.2504 11.1208 124420 775892 -1 55531 14 16382 26779 951067 191033 3.60577 3.60577 -14927 -3.60577 0 0 4.86353e+06 4207.21 0.21 1.74 0.66 -1 -1 0.21 1.638 1.46031 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 156.27 vpr 277.42 MiB 2.09 108040 -1 -1 3 48.42 -1 -1 84944 -1 -1 770 115 0 40 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 284076 115 145 23133 19546 1 9694 1070 40 40 1600 mult_36 auto 154.6 MiB 12.62 79581 586360 191379 370364 24617 221.6 MiB 10.93 0.12 5.13017 -22530.1 -5.13017 5.13017 2.15 0.0351572 0.0292193 4.14895 3.53646 -1 -1 -1 -1 80 127150 44 9.16046e+07 5.73393e+07 8.41679e+06 5260.49 54.58 16.4025 13.7039 205632 1754580 -1 114217 13 29778 46242 7115265 1603973 5.57953 5.57953 -24422.4 -5.57953 0 0 1.06125e+07 6632.80 0.42 3.05 1.43 -1 -1 0.42 1.6584 1.47502 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 651.40 vpr 1.60 GiB 2.63 156012 -1 -1 3 8.81 -1 -1 202312 -1 -1 1977 149 0 324 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1678240 149 182 65737 42630 1 35715 2632 104 104 10816 mult_36 auto 374.2 MiB 40.04 311596 2454907 884079 1495837 74991 1638.9 MiB 70.37 0.48 14.6044 -61020 -14.6044 14.6044 49.60 0.117008 0.105376 17.0093 14.9395 -1 -1 -1 -1 68 450703 48 6.67561e+08 2.34845e+08 5.23589e+07 4840.87 395.44 72.2092 62.3025 1334630 10731989 -1 422434 19 118711 141570 15462485 3411624 15.8253 15.8253 -68233.2 -15.8253 0 0 6.49608e+07 6005.99 3.14 9.68 9.88 -1 -1 3.14 6.01093 5.31531 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.51 vpr 66.34 MiB 0.09 10100 -1 -1 5 0.14 -1 -1 33148 -1 -1 14 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67928 11 30 313 321 2 115 55 7 7 49 clb auto 26.7 MiB 0.30 456 2239 413 1740 86 66.3 MiB 0.05 0.00 2.65898 -171.948 -2.65898 2.30209 0.04 0.000886162 0.000807618 0.0241056 0.022178 -1 -1 -1 -1 30 934 29 1.07788e+06 754516 77114.5 1573.76 0.50 0.245302 0.207397 3660 13876 -1 783 19 469 889 29198 10184 2.65817 2.36697 -188.291 -2.65817 0 0 95414.1 1947.23 0.00 0.06 0.01 -1 -1 0.00 0.0401555 0.0354168 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 424.13 vpr 654.30 MiB 5.41 206884 -1 -1 101 90.71 -1 -1 104380 -1 -1 2232 114 44 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 670004 114 102 38224 33865 1 17936 2500 57 57 3249 clb auto 296.0 MiB 88.56 238874 1969860 742285 1191850 35725 654.3 MiB 73.26 0.61 75.9908 -52848.4 -75.9908 75.9908 13.94 0.119995 0.0990419 13.9371 11.5851 -1 -1 -1 -1 92 346294 24 1.92089e+08 1.47573e+08 1.98119e+07 6097.84 92.04 46.6101 38.3968 448119 4205394 -1 325298 22 78986 295129 14718681 2597490 76.1097 76.1097 -61489.2 -76.1097 0 0 2.51903e+07 7753.25 1.12 11.41 4.01 -1 -1 1.12 6.75644 5.7346 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 2794.92 vpr 2.15 GiB 27.20 702236 -1 -1 101 880.69 -1 -1 313852 -1 -1 7600 114 167 32 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2255188 114 102 124851 111146 1 58871 8015 103 103 10609 clb auto 934.7 MiB 293.36 1043923 10110191 4211863 5843486 54842 2044.4 MiB 496.28 3.13 76.166 -325620 -76.166 76.166 46.17 0.380796 0.319544 52.0019 43.437 -1 -1 -1 -1 124 1367703 42 6.46441e+08 5.13746e+08 8.61045e+07 8116.18 832.38 166.433 135.976 1699828 18865638 -1 1310007 22 217059 913739 52502988 8651301 76.2861 76.2861 -462427 -76.2861 0 0 1.09063e+08 10280.2 5.97 42.07 19.66 -1 -1 5.97 24.2946 20.4139 + k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 5521.11 vpr 2.21 GiB 66.02 890848 -1 -1 26 3208.51 -1 -1 375960 -1 -1 7302 36 159 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2318968 36 356 190343 166383 1 60659 7880 101 101 10201 clb auto 1094.9 MiB 354.20 718639 11686500 4557070 6682417 447013 2151.0 MiB 494.38 3.08 47.0709 -322999 -47.0709 47.0709 43.14 0.339115 0.29521 56.3357 46.8416 -1 -1 -1 -1 124 957569 42 6.22828e+08 4.91323e+08 8.26363e+07 8100.80 1146.80 253.769 207.967 1632490 18090185 -1 921573 21 221603 569140 33110457 5760400 46.3566 46.3566 -361674 -46.3566 0 0 1.04691e+08 10262.8 4.87 27.77 18.47 -1 -1 4.87 19.8348 17.1642 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_depop/config/golden_results.txt index 1a2d7cfe27e..26cbed08b92 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_depop/config/golden_results.txt @@ -1,22 +1,22 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml arm_core.v common 366.18 3.53 128232 18 85.76 -1 -1 72148 -1 -1 844 133 24 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 279720 133 179 18339 18121 1 8939 1180 36 36 1296 clb memory auto 17.97 133843 22.52 0.15 18.4184 -141279 -18.4184 18.4184 4.69 0.0517384 0.045552 7.30796 6.28578 146 224959 37 7.21828e+07 5.86395e+07 1.23606e+07 9537.51 162.12 27.1627 23.7865 207535 16 38497 147575 36095601 8273636 20.0278 20.0278 -158267 -20.0278 0 0 1.55729e+07 12016.1 4.98 11.95 3.08151 2.82269 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bgm.v common 991.52 11.78 375836 14 288.16 -1 -1 150616 -1 -1 2305 257 0 11 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 740404 257 32 36518 33906 1 19046 2605 58 58 3364 clb auto 54.16 247747 99.40 0.70 17.1218 -23175.7 -17.1218 17.1218 47.00 0.12732 0.115715 16.2724 14.0282 116 491009 49 2.00088e+08 1.28585e+08 2.71672e+07 8075.87 394.04 94.3203 82.2886 462659 23 111035 519425 47964581 8402128 19.6696 19.6696 -26147.4 -19.6696 0 0 3.40353e+07 10117.5 13.44 20.98 8.74929 7.88966 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml blob_merge.v common 193.24 1.09 58604 5 57.92 -1 -1 68924 -1 -1 539 36 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 152832 36 100 14036 11283 1 3780 675 29 29 841 clb auto 14.61 47553 10.67 0.07 12.9252 -2650.36 -12.9252 12.9252 2.93 0.0311144 0.0273874 4.25977 3.76907 98 99647 41 4.4999e+07 2.90489e+07 5.54665e+06 6595.30 86.90 15.1417 13.4298 87659 18 16525 73018 5640392 977319 14.2116 14.2116 -3076.05 -14.2116 0 0 6.99642e+06 8319.17 2.27 2.98 1.70896 1.57933 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml boundtop.v common 10.24 1.31 45200 3 0.54 -1 -1 41320 -1 -1 89 142 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 59272 142 193 1069 1140 1 530 424 14 14 196 clb auto 0.64 1531 0.95 0.01 2.94005 -452.908 -2.94005 2.94005 0.52 0.00225564 0.0021036 0.393919 0.363586 40 3930 14 9.20055e+06 4.79657e+06 529800. 2703.06 3.23 1.15439 1.07156 3532 10 1272 2291 141758 41077 3.56317 3.56317 -566.913 -3.56317 0 0 662635. 3380.79 0.20 0.12 0.0875529 0.0837756 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 3.25 0.09 9780 3 0.31 -1 -1 39504 -1 -1 64 99 1 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 39260 99 130 363 493 1 261 294 12 12 144 clb auto 0.16 697 0.37 0.00 2.11495 -207.011 -2.11495 2.11495 0.33 0.000674017 0.00061544 0.111707 0.101902 42 1903 12 5.66058e+06 3.99722e+06 373597. 2594.42 0.79 0.266683 0.245564 1800 12 675 938 87522 29405 2.95628 2.95628 -261.888 -2.95628 0 0 468675. 3254.69 0.14 0.05 0.0280509 0.0265793 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diffeq1.v common 11.56 0.07 9564 6 0.20 -1 -1 38684 -1 -1 26 162 0 5 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 56408 162 96 1075 884 1 667 289 16 16 256 mult_36 auto 0.50 5078 0.88 0.01 15.3726 -1203.18 -15.3726 15.3726 0.69 0.00332607 0.00315459 0.443145 0.418579 60 11156 33 1.21132e+07 3.38124e+06 1.01260e+06 3955.47 6.53 1.39261 1.32314 9613 24 3616 6215 1828440 447202 17.5186 17.5186 -1462.9 -17.5186 0 0 1.26536e+06 4942.82 0.37 0.56 0.203639 0.19536 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diffeq2.v common 14.18 0.05 8820 6 0.12 -1 -1 37868 -1 -1 16 66 0 7 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 50700 66 96 866 607 1 533 185 18 18 324 mult_36 auto 0.34 4735 0.79 0.01 12.0481 -714.751 -12.0481 12.0481 0.97 0.00333463 0.00317376 0.459311 0.436907 52 11667 29 1.57076e+07 3.6343e+06 1.14165e+06 3523.62 8.28 1.3168 1.26106 10315 22 4558 9816 5259633 1258198 13.5233 13.5233 -870.647 -13.5233 0 0 1.50318e+06 4639.44 0.46 1.24 0.172405 0.166447 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml LU8PEEng.v common 766.66 14.64 210096 101 114.35 -1 -1 107972 -1 -1 1851 114 44 8 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 600612 114 102 38224 33865 1 17424 2119 53 53 2809 clb auto 71.39 224050 83.22 0.59 66.8715 -51660.4 -66.8715 66.8715 38.17 0.129414 0.108857 17.3431 14.5804 124 411569 38 1.63647e+08 1.27041e+08 2.38080e+07 8475.60 354.88 74.7883 64.1041 376538 25 80780 317832 56593788 12162753 74.6606 74.6606 -65414.8 -74.6606 -28.8437 -0.20415 3.00291e+07 10690.3 11.73 25.38 8.85759 7.88032 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml LU32PEEng.v common 4509.90 62.45 709160 101 1034.68 -1 -1 317808 -1 -1 6269 114 167 32 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 2426076 114 102 124851 111146 1 58394 6684 94 94 8836 clb auto 233.08 1032133 522.71 2.89 66.4852 -332544 -66.4852 66.4852 133.48 0.425542 0.37957 64.5818 55.4437 172 1599600 42 5.40921e+08 4.4202e+08 1.03144e+08 11673.2 2170.22 308.629 265.121 1517775 23 238646 1029395 273863959 63708210 77.2438 77.2438 -489390 -77.2438 -29.2742 -0.172573 1.30092e+08 14722.9 50.71 112.15 28.4487 25.2671 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mcml.v common 6426.13 123.41 897628 26 3730.31 -1 -1 376940 -1 -1 6697 36 159 27 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 2551024 36 356 190343 166383 1 60345 7275 97 97 9409 clb auto 271.63 729788 715.92 3.10 40.1533 -303194 -40.1533 40.1533 130.72 0.369181 0.328539 77.2606 65.5418 160 1078522 36 5.71422e+08 4.58721e+08 1.01844e+08 10824.1 1168.73 286.245 247.747 1023525 21 252001 682213 135772294 30665549 42.8992 42.8992 -363536 -42.8992 0 0 1.29602e+08 13774.3 41.27 52.44 22.4858 20.3437 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkDelayWorker32B.v common 101.95 2.12 71084 5 8.50 -1 -1 56628 -1 -1 453 506 45 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 367804 506 553 3519 4017 1 3086 1557 50 50 2500 memory auto 6.04 15906 7.85 0.06 6.63464 -1807.67 -6.63464 6.63464 33.19 0.0190454 0.0175723 4.04596 3.69702 40 24763 18 1.47946e+08 4.90746e+07 7.85310e+06 3141.24 22.40 9.11031 8.44651 23665 16 4699 6227 4255095 1086941 7.29496 7.29496 -2223.41 -7.29496 -5.03631 -0.193229 9.77405e+06 3909.62 4.02 1.79 0.908857 0.861995 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkPktMerge.v common 18.64 0.27 17032 2 0.10 -1 -1 39696 -1 -1 25 311 15 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 58432 311 156 1019 1160 1 954 507 28 28 784 memory auto 0.70 7932 1.32 0.02 3.65703 -4338.92 -3.65703 3.65703 2.60 0.00445569 0.00397936 0.641896 0.568983 40 14723 37 4.25198e+07 9.56735e+06 2.32339e+06 2963.51 7.86 1.97475 1.78872 13500 17 3399 3683 2547833 716874 4.00095 4.00095 -5037.99 -4.00095 -15.6433 -0.322548 2.89875e+06 3697.39 1.03 0.76 0.215687 0.201099 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 31.99 0.62 30404 4 2.26 -1 -1 42960 -1 -1 165 193 5 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 75044 193 205 2863 2789 1 1379 568 20 20 400 memory auto 1.85 11348 3.19 0.02 4.02531 -2513.1 -4.02531 4.02531 1.17 0.00644756 0.00579169 1.25044 1.11965 78 22965 36 2.07112e+07 1.16325e+07 2.06176e+06 5154.39 17.43 4.00817 3.64129 20086 16 5564 15748 1823107 397997 4.53843 4.53843 -2890.18 -4.53843 -7.37934 -0.298787 2.60035e+06 6500.87 0.74 0.74 0.372287 0.350206 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml or1200.v common 94.88 1.04 40356 8 6.19 -1 -1 45260 -1 -1 205 385 2 1 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 125560 385 394 4673 4537 1 2360 987 27 27 729 io auto 5.43 30254 7.09 0.08 8.05283 -9285.19 -8.05283 8.05283 2.53 0.01604 0.0150071 2.35096 2.17604 114 55965 25 3.93038e+07 1.25403e+07 5.50397e+06 7550.03 60.09 10.3708 9.63043 50867 20 11261 40543 5771240 1124941 8.79936 8.79936 -10123.8 -8.79936 0 0 6.92971e+06 9505.78 2.34 2.27 0.939816 0.886385 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 28.13 0.86 32028 3 1.28 -1 -1 44032 -1 -1 100 214 0 8 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 75072 214 305 2963 2869 1 1464 627 19 19 361 io auto 2.03 10704 2.27 0.03 4.29962 -2466.29 -4.29962 4.29962 1.13 0.00731701 0.00680645 0.95926 0.888097 64 26676 46 1.72706e+07 8.5574e+06 1.60702e+06 4451.57 14.42 3.71517 3.46917 21800 23 7166 16966 4782812 1073669 5.04074 5.04074 -3013.22 -5.04074 0 0 1.98721e+06 5504.73 0.60 1.47 0.489947 0.465483 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml sha.v common 336.02 1.83 39076 3 311.80 -1 -1 95840 -1 -1 138 38 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 63968 38 36 2995 2744 1 1208 212 16 16 256 clb auto 2.24 11256 1.96 0.02 8.87371 -2382.95 -8.87371 8.87371 0.63 0.00574619 0.00517374 0.816572 0.721565 80 21797 26 1.21132e+07 7.43737e+06 1.29183e+06 5046.22 8.75 2.7517 2.45615 19351 22 5540 18113 1095161 241229 10.3694 10.3694 -2917.57 -10.3694 0 0 1.62458e+06 6346.00 0.42 0.73 0.488978 0.452337 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml spree.v common 16.08 0.43 21076 15 0.90 -1 -1 39404 -1 -1 49 45 3 1 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 61968 45 32 1275 1232 1 822 130 14 14 196 memory auto 1.25 6630 1.02 0.01 9.55177 -6480.8 -9.55177 9.55177 0.53 0.003215 0.00286306 0.531553 0.469804 100 14267 33 9.20055e+06 4.68081e+06 1.19340e+06 6088.79 8.66 1.84126 1.64944 12397 14 3745 10984 1853298 463403 10.4092 10.4092 -7370.27 -10.4092 -17.8589 -0.318417 1.49920e+06 7648.97 0.40 0.58 0.193835 0.181911 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision0.v common 82.00 3.90 122720 5 9.54 -1 -1 74484 -1 -1 684 157 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 215576 157 197 23846 21799 1 6801 1038 33 33 1089 clb auto 9.15 40314 10.39 0.08 2.95855 -13303.1 -2.95855 2.95855 3.75 0.0355087 0.0318712 4.99483 4.32205 64 68056 41 6.0475e+07 3.68636e+07 5.14656e+06 4725.95 23.14 16.0714 14.2441 64167 14 19652 32945 2075106 479443 3.72591 3.72591 -16028.1 -3.72591 0 0 6.36035e+06 5840.54 2.14 2.15 1.91861 1.77768 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision1.v common 219.37 3.83 108224 3 44.46 -1 -1 88564 -1 -1 642 115 0 40 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 250728 115 145 23133 19546 1 9748 942 40 40 1600 mult_36 auto 8.25 76270 12.86 0.10 4.99955 -21585.1 -4.99955 4.99955 5.73 0.0345488 0.0302806 5.44775 4.79445 88 140299 45 9.16046e+07 5.04406e+07 9.92704e+06 6204.40 110.77 19.7099 17.5419 123303 21 39408 63999 27118412 5502186 5.37438 5.37438 -25122.8 -5.37438 0 0 1.23763e+07 7735.20 4.04 7.66 2.4484 2.25387 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision2.v common 724.91 4.83 155612 3 8.43 -1 -1 206404 -1 -1 1650 149 0 324 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 1739948 149 182 65737 42630 1 35997 2305 104 104 10816 mult_36 auto 37.71 335815 72.99 0.46 14.4526 -61711 -14.4526 14.4526 150.35 0.147959 0.138663 24.3248 22.1024 74 514709 36 6.67561e+08 2.17223e+08 6.06274e+07 5605.34 305.65 72.9675 66.743 498077 20 143781 170712 57264364 11639493 16.5372 16.5372 -74959.5 -16.5372 0 0 7.58441e+07 7012.22 31.42 20.46 8.60695 7.98987 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision3.v common 1.84 0.11 10352 5 0.14 -1 -1 37956 -1 -1 15 11 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 39304 11 30 313 321 2 108 56 7 7 49 clb auto 0.22 395 0.11 0.00 2.36605 -152.494 -2.36605 1.9999 0.07 0.000476264 0.000407281 0.0613289 0.0518885 30 1169 31 1.07788e+06 808410 84241.2 1719.21 0.29 0.152431 0.131534 944 17 532 1516 56407 21898 3.07845 2.37233 -183.444 -3.07845 0 0 103128. 2104.65 0.02 0.04 0.0304834 0.0280591 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml arm_core.v common 291.79 vpr 347.77 MiB 3.33 127036 -1 -1 18 74.78 -1 -1 67044 -1 -1 872 133 24 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 356120 133 179 18379 18161 1 8747 1208 37 37 1369 clb auto 145.3 MiB 15.93 137022 644308 210792 408526 24990 210.7 MiB 18.69 0.17 18.7 -143058 -18.7 18.7 1.99 0.0513907 0.0451283 5.97214 5.04592 -1 -1 -1 -1 144 231078 40 7.54166e+07 6.01486e+07 1.29396e+07 9451.85 123.77 29.648 24.5435 245398 2948354 -1 212508 17 38157 152893 14612869 2727745 18.7504 18.7504 -151687 -18.7504 0 0 1.63545e+07 11946.3 0.70 6.32 2.90 -1 -1 0.70 2.70475 2.36868 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bgm.v common 702.65 vpr 776.92 MiB 8.38 372860 -1 -1 14 292.94 -1 -1 148272 -1 -1 2367 257 0 11 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 795564 257 32 36518 33906 1 18590 2667 59 59 3481 clb auto 295.1 MiB 48.10 232761 1851367 648559 1173107 29701 776.9 MiB 80.06 0.71 19.6105 -25503 -19.6105 19.6105 19.00 0.119316 0.0995551 12.6353 10.6839 -1 -1 -1 -1 116 474814 37 2.05423e+08 1.31927e+08 2.81418e+07 8084.40 174.27 58.363 48.4476 570456 6327992 -1 447334 22 105897 511864 38703318 7252307 20.1588 20.1588 -26078.4 -20.1588 0 0 3.52566e+07 10128.3 1.65 19.56 5.93 -1 -1 1.65 7.38155 6.28162 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml blob_merge.v common 111.67 vpr 184.46 MiB 0.80 57480 -1 -1 5 43.53 -1 -1 60652 -1 -1 558 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 188888 36 100 14036 11283 1 3586 694 30 30 900 clb auto 100.3 MiB 14.56 46175 277084 82401 176673 18010 152.1 MiB 6.40 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-3.14227 0 0 106806. 2179.72 0.00 0.06 0.01 -1 -1 0.00 0.0336665 0.0299623 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt index 824194a6ab7..157e870f862 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt @@ -1,21 +1,21 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 251.29 vpr 303.75 MiB 3.28 127012 -1 -1 18 65.68 -1 -1 66884 -1 -1 1007 133 24 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 311040 133 179 18379 18161 1 9013 1343 39 39 1521 clb auto 152.8 MiB 31.39 140193 682695 221032 446886 14777 210.8 MiB 14.72 0.14 18.176 -144006 -18.176 18.176 4.29 0.0467304 0.0408974 5.01063 4.16549 106 200122 36 8.65315e+07 6.74245e+07 1.02794e+07 6758.33 76.41 24.1645 19.9956 222144 2202216 -1 184785 15 34752 126432 8486145 1348247 18.6662 18.6662 -149802 -18.6662 0 0 1.30215e+07 8561.12 3.97 4.51 2.13 -1 -1 3.97 2.36837 2.09021 -k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 711.33 vpr 742.11 MiB 8.37 372936 -1 -1 14 252.96 -1 -1 148516 -1 -1 2733 257 0 11 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 759924 257 32 36518 33906 1 19753 3033 63 63 3969 clb auto 305.2 MiB 77.43 251640 2197533 785535 1383157 28841 711.8 MiB 56.39 0.46 22.0986 -25607.7 -22.0986 22.0986 35.61 0.097897 0.0873488 10.8107 9.09204 76 386174 24 2.36641e+08 1.5165e+08 2.05973e+07 5189.55 198.88 48.3847 40.1382 506266 4280222 -1 369691 17 89404 400289 17805551 2620128 21.9711 21.9711 -26032.3 -21.9711 0 0 2.57532e+07 6488.59 8.27 10.52 3.93 -1 -1 8.27 5.3122 4.6658 -k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 148.52 vpr 160.05 MiB 0.82 57516 -1 -1 5 38.40 -1 -1 60452 -1 -1 609 36 0 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 163892 36 100 14036 11283 1 3163 745 31 31 961 clb auto 102.2 MiB 20.95 46654 280953 83651 183127 14175 151.0 MiB 5.41 0.06 15.0401 -2810.04 -15.0401 15.0401 2.68 0.0248194 0.0222841 2.3908 2.09588 64 75521 30 5.14688e+07 3.28214e+07 4.14665e+06 4314.93 62.14 8.74606 7.4094 112594 842736 -1 69312 18 13194 61399 2737755 355281 15.4757 15.4757 -3153.97 -15.4757 0 0 5.17798e+06 5388.12 1.46 2.04 0.73 -1 -1 1.46 1.28924 1.13534 -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 8.62 vpr 70.13 MiB 0.79 45160 -1 -1 3 0.52 -1 -1 37624 -1 -1 93 142 0 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71812 142 193 1069 1140 1 564 428 14 14 196 clb auto 31.1 MiB 0.86 1785 155180 53402 81741 20037 70.1 MiB 0.64 0.01 3.40722 -519.076 -3.40722 3.40722 0.40 0.00295831 0.00277456 0.29625 0.277905 38 3853 13 9.20055e+06 5.01214e+06 467348. 2384.43 1.47 0.899196 0.827427 18724 93853 -1 3532 13 1201 1810 86141 22375 3.56925 3.56925 -566.287 -3.56925 0 0 593372. 3027.41 0.14 0.14 0.09 -1 -1 0.14 0.102861 0.0959338 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 4.34 vpr 65.18 MiB 0.09 9376 -1 -1 3 0.27 -1 -1 34460 -1 -1 65 99 1 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66748 99 130 363 493 1 251 295 12 12 144 clb auto 26.5 MiB 0.21 684 70927 26093 33715 11119 65.2 MiB 0.24 0.00 2.16753 -221.96 -2.16753 2.16753 0.27 0.00128722 0.00121798 0.0980525 0.0928592 48 1590 12 5.66058e+06 4.05111e+06 394078. 2736.65 1.65 0.318924 0.293792 13662 75965 -1 1464 10 579 744 48078 14435 2.53703 2.53703 -236.896 -2.53703 0 0 503203. 3494.47 0.11 0.06 0.08 -1 -1 0.11 0.0346272 0.0321752 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 9.14 vpr 68.76 MiB 0.06 9328 -1 -1 6 0.19 -1 -1 33860 -1 -1 32 162 0 5 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70412 162 96 1075 884 1 667 295 16 16 256 mult_36 auto 29.7 MiB 0.46 5073 90547 34495 49420 6632 68.8 MiB 0.66 0.01 15.7804 -1282.87 -15.7804 15.7804 0.54 0.00344845 0.00325196 0.335594 0.31644 50 10999 25 1.21132e+07 3.70461e+06 780532. 3048.95 4.56 1.13443 1.05201 26044 153858 -1 9441 23 3578 6220 1122545 304860 17.3814 17.3814 -1445.82 -17.3814 0 0 1.00276e+06 3917.05 0.22 0.40 0.14 -1 -1 0.22 0.16867 0.156716 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 8.75 vpr 67.72 MiB 0.05 8412 -1 -1 6 0.11 -1 -1 34004 -1 -1 20 66 0 7 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69344 66 96 866 607 1 547 189 18 18 324 mult_36 auto 28.7 MiB 0.53 4838 50053 18112 27527 4414 67.7 MiB 0.49 0.01 12.8146 -774.958 -12.8146 12.8146 0.70 0.00286604 0.00272622 0.274795 0.261333 50 10773 26 1.57076e+07 3.84988e+06 1.01955e+06 3146.77 3.98 0.818492 0.765277 33704 203160 -1 9373 17 2969 6034 1588307 392502 13.3571 13.3571 -857.233 -13.3571 0 0 1.31112e+06 4046.65 0.32 0.45 0.19 -1 -1 0.32 0.12041 0.113131 -k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 486.28 vpr 647.63 MiB 4.97 206932 -1 -1 101 83.52 -1 -1 104732 -1 -1 2199 114 44 8 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 663176 114 102 38224 33865 1 17989 2467 57 57 3249 clb auto 297.2 MiB 84.76 227277 1885273 706303 1153591 25379 647.6 MiB 53.07 0.44 77.0036 -54799.5 -77.0036 77.0036 29.03 0.101882 0.0902043 12.9534 10.9689 90 342868 50 1.92089e+08 1.45795e+08 1.94366e+07 5982.34 159.71 49.9328 41.2187 441623 4070163 -1 316684 22 71362 268219 14425695 2440308 75.9872 75.9872 -66532.1 -75.9872 0 0 2.43249e+07 7486.90 7.96 10.67 3.93 -1 -1 7.96 6.34937 5.40817 -k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 3371.54 vpr 2.18 GiB 25.62 702172 -1 -1 101 753.58 -1 -1 313596 -1 -1 7552 114 167 32 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2285976 114 102 124851 111146 1 58906 7967 103 103 10609 clb auto 932.5 MiB 276.34 1006475 9870431 4090428 5732521 47482 2124.1 MiB 291.99 2.06 76.3766 -329212 -76.3766 76.3766 95.41 0.331227 0.286267 46.2628 38.3296 122 1362422 39 6.46441e+08 5.11157e+08 8.50538e+07 8017.14 1667.77 174.578 141.534 1678612 18422568 -1 1285265 23 216810 910698 54424616 8669592 76.9472 76.9472 -462152 -76.9472 0 0 1.06559e+08 10044.2 36.54 37.26 19.11 -1 -1 36.54 21.793 18.3927 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 102.09 vpr 346.82 MiB 1.39 69476 -1 -1 5 7.46 -1 -1 52940 -1 -1 455 506 45 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 355148 506 553 3519 4017 1 3098 1559 50 50 2500 memory auto 52.9 MiB 6.91 15738 1167203 573865 408695 184643 346.8 MiB 5.62 0.06 8.15634 -2061.78 -8.15634 8.15634 22.07 0.0230057 0.0207868 3.09735 2.77898 40 23618 12 1.47946e+08 4.91823e+07 7.18436e+06 2873.75 38.79 9.28894 8.42624 260716 1475984 -1 22655 13 3528 4688 1066656 244291 8.5462 8.5462 -2299.68 -8.5462 0 0 8.97548e+06 3590.19 2.87 1.07 1.31 -1 -1 2.87 0.851835 0.787338 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 20.06 vpr 71.95 MiB 0.20 16756 -1 -1 2 0.14 -1 -1 33788 -1 -1 29 311 15 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73676 311 156 1019 1160 1 965 511 28 28 784 memory auto 31.2 MiB 0.68 8035 202669 69067 122737 10865 71.6 MiB 1.10 0.01 4.10149 -4326.24 -4.10149 4.10149 1.84 0.00557566 0.0049467 0.576345 0.510587 36 14965 37 4.25198e+07 9.78293e+06 1.94918e+06 2486.20 11.50 2.77766 2.44983 76314 389223 -1 13484 16 3019 3398 733958 195651 4.26998 4.26998 -4913.56 -4.26998 0 0 2.40571e+06 3068.51 0.59 0.21 0.24 -1 -1 0.59 0.116413 0.107369 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 27.04 vpr 83.75 MiB 0.44 29296 -1 -1 4 1.86 -1 -1 37936 -1 -1 188 193 5 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85756 193 205 2863 2789 1 1453 591 20 20 400 memory auto 43.1 MiB 3.32 11779 260886 94839 139163 26884 83.7 MiB 2.04 0.02 4.8458 -2825.08 -4.8458 4.8458 0.89 0.0087501 0.00794583 0.897826 0.808388 56 21068 24 2.07112e+07 1.28721e+07 1.41661e+06 3541.53 13.13 3.63749 3.22428 43380 284034 -1 18265 16 5239 12681 720235 141227 5.24613 5.24613 -2968.77 -5.24613 0 0 1.80858e+06 4521.44 0.41 0.49 0.26 -1 -1 0.41 0.332556 0.303997 -k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 67.72 vpr 131.64 MiB 0.86 39800 -1 -1 8 4.23 -1 -1 41976 -1 -1 259 385 2 1 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 134804 385 394 4673 4537 1 2433 1041 27 27 729 io auto 55.2 MiB 10.57 30554 596890 229640 341672 25578 99.3 MiB 5.51 0.06 8.56969 -10033.6 -8.56969 8.56969 1.91 0.017043 0.0159102 2.03907 1.87536 86 47938 49 3.93038e+07 1.54505e+07 3.99564e+06 5480.99 34.06 10.2417 9.40982 95941 833781 -1 44029 16 10606 36784 2224832 374938 9.06418 9.06418 -10476.9 -9.06418 0 0 5.05392e+06 6932.68 1.32 1.30 0.76 -1 -1 1.32 0.725604 0.677829 -k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 21.80 vpr 83.66 MiB 0.46 31556 -1 -1 3 1.08 -1 -1 40384 -1 -1 111 214 0 8 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85672 214 305 2963 2869 1 1447 638 19 19 361 io auto 42.6 MiB 1.92 10418 247688 84171 150756 12761 83.7 MiB 1.67 0.02 4.42375 -2655.65 -4.42375 4.42375 0.80 0.00798008 0.00737723 0.762737 0.704597 56 23860 44 1.72706e+07 9.15023e+06 1.27879e+06 3542.35 9.76 3.27062 2.98117 39043 256479 -1 19879 21 6749 14800 2385939 557556 5.10564 5.10564 -2970.78 -5.10564 0 0 1.63234e+06 4521.70 0.38 0.93 0.23 -1 -1 0.38 0.424617 0.392906 -k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 251.55 abc 92.76 MiB 2.17 38236 -1 -1 3 225.30 -1 -1 94988 -1 -1 156 38 0 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85160 38 36 2995 2744 1 1210 230 17 17 289 clb auto 42.3 MiB 2.48 11201 48102 12472 32994 2636 83.2 MiB 0.97 0.02 9.47702 -2554.42 -9.47702 9.47702 0.61 0.0063397 0.00562943 0.447857 0.393122 76 15652 22 1.34605e+07 8.40746e+06 1.31783e+06 4559.95 10.18 3.3249 2.84916 34363 263318 -1 15129 21 4392 11758 429882 72221 10.5367 10.5367 -2771.23 -10.5367 0 0 1.64970e+06 5708.31 0.38 0.50 0.26 -1 -1 0.38 0.360128 0.321557 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 12.68 vpr 72.22 MiB 0.27 20592 -1 -1 15 0.71 -1 -1 36136 -1 -1 66 45 3 1 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73956 45 32 1275 1232 1 824 147 14 14 196 memory auto 32.7 MiB 2.97 6859 19497 5084 12799 1614 72.2 MiB 0.40 0.01 10.7449 -6919.42 -10.7449 10.7449 0.40 0.00363787 0.0032179 0.210155 0.186402 64 13021 35 9.20055e+06 5.597e+06 762053. 3888.03 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stereovision1.v common 510.49 vpr 283.80 MiB 2.13 108044 -1 -1 3 38.46 -1 -1 85052 -1 -1 678 115 0 40 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 290612 115 145 23133 19546 1 9709 978 40 40 1600 mult_36 auto 154.1 MiB 9.54 77055 505586 160836 322573 22177 219.6 MiB 8.75 0.09 5.14456 -22824.9 -5.14456 5.14456 4.14 0.0328707 0.0285435 3.72216 3.17758 82 126675 47 9.16046e+07 5.23808e+07 8.58295e+06 5364.35 417.83 20.4189 16.9525 207228 1787768 -1 113536 16 33307 52542 8887375 1849878 5.45065 5.45065 -24933.1 -5.45065 0 0 1.07702e+07 6731.38 2.57 3.31 1.58 -1 -1 2.57 1.56913 1.39099 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 2861.32 vpr 1.55 GiB 2.81 155972 -1 -1 3 8.15 -1 -1 202304 -1 -1 1651 149 0 324 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on 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9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85724 38 36 2995 2744 1 1203 229 17 17 289 clb auto 42.7 MiB 2.57 11167 52729 13839 35434 3456 83.7 MiB 1.24 0.02 9.59018 -2500.97 -9.59018 9.59018 0.30 0.00667277 0.00596243 0.5591 0.492955 -1 -1 -1 -1 82 15259 20 1.34605e+07 8.35357e+06 1.40210e+06 4851.55 6.49 2.96999 2.56897 35515 283594 -1 14972 18 3872 10498 343968 59662 9.98784 9.98784 -2667.34 -9.98784 0 0 1.76468e+06 6106.15 0.06 0.47 0.26 -1 -1 0.06 0.362081 0.327087 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 13.05 vpr 72.99 MiB 0.29 20668 -1 -1 15 0.70 -1 -1 35812 -1 -1 64 45 3 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74744 45 32 1275 1232 1 833 145 14 14 196 memory auto 33.7 MiB 3.01 7652 27505 7618 16255 3632 73.0 MiB 0.62 0.01 10.691 -7011.57 -10.691 10.691 0.20 0.00407573 0.00364622 0.321464 0.28675 -1 -1 -1 -1 62 15473 48 9.20055e+06 5.48922e+06 735792. 3754.04 5.46 1.62663 1.41102 21652 143691 -1 12219 13 3871 10505 808512 198580 11.0765 11.0765 -7405.88 -11.0765 0 0 913676. 4661.61 0.03 0.32 0.13 -1 -1 0.03 0.157056 0.142388 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 66.34 vpr 236.52 MiB 2.39 122680 -1 -1 5 8.93 -1 -1 70664 -1 -1 725 157 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 242196 157 197 23846 21799 1 6113 1079 34 34 1156 clb auto 153.2 MiB 11.54 37343 548747 178166 350972 19609 212.3 MiB 8.04 0.08 3.49124 -14535.8 -3.49124 3.49124 1.42 0.0327851 0.0281188 3.66298 3.11758 -1 -1 -1 -1 48 57477 42 6.50233e+07 3.90734e+07 3.79520e+06 3283.05 13.55 11.3359 9.50466 124420 775892 -1 51658 15 14989 25110 795733 164333 3.60577 3.60577 -15598.6 -3.60577 0 0 4.86353e+06 4207.21 0.19 1.69 0.65 -1 -1 0.19 1.62548 1.44591 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 155.80 vpr 280.15 MiB 2.07 108084 -1 -1 3 41.43 -1 -1 85040 -1 -1 770 115 0 40 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 286876 115 145 23133 19546 1 9694 1070 40 40 1600 mult_36 auto 155.7 MiB 12.68 85346 569950 187665 359942 22343 223.0 MiB 10.74 0.11 5.55558 -22870.2 -5.55558 5.55558 2.00 0.0333171 0.0289197 4.0955 3.47462 -1 -1 -1 -1 80 136599 42 9.16046e+07 5.73393e+07 8.41679e+06 5260.49 60.65 16.774 14.0251 205632 1754580 -1 121367 14 31850 50930 8085714 1789124 5.72554 5.72554 -24797.3 -5.72554 0 0 1.06125e+07 6632.80 0.42 3.47 1.56 -1 -1 0.42 1.74483 1.54499 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 445.99 vpr 1.59 GiB 2.63 156000 -1 -1 3 9.33 -1 -1 202412 -1 -1 1977 149 0 324 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1671480 149 182 65737 42630 1 35715 2632 104 104 10816 mult_36 auto 374.6 MiB 47.00 310719 2454907 886319 1494591 73997 1632.3 MiB 60.07 0.43 14.7463 -61160.2 -14.7463 14.7463 47.78 0.118274 0.101341 16.6524 14.322 -1 -1 -1 -1 82 428353 18 6.67561e+08 2.34845e+08 6.06625e+07 5608.59 189.46 61.0549 52.5839 1431962 12793479 -1 415735 19 110977 130643 13538006 2940585 15.6742 15.6742 -67719.7 -15.6742 0 0 7.60166e+07 7028.16 5.73 9.74 11.93 -1 -1 5.73 6.36463 5.6674 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.45 vpr 66.30 MiB 0.10 10100 -1 -1 5 0.14 -1 -1 33352 -1 -1 14 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67888 11 30 313 321 2 115 55 7 7 49 clb auto 26.6 MiB 0.29 442 2239 416 1756 67 66.3 MiB 0.05 0.00 2.68099 -175.84 -2.68099 2.3116 0.03 0.000896631 0.000814667 0.0241545 0.0222358 -1 -1 -1 -1 34 820 13 1.07788e+06 754516 84249.8 1719.38 0.50 0.250037 0.211786 3756 15224 -1 668 12 330 657 15383 5482 2.64229 2.29364 -186.64 -2.64229 0 0 103542. 2113.11 0.00 0.04 0.01 -1 -1 0.00 0.0303299 0.0271649 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/golden_results.txt index 35fdb3b3809..1618cfa66c0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/golden_results.txt @@ -1,13 +1,13 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 626.87 vpr 2.66 GiB -1 -1 24.67 191020 5 89.67 -1 -1 105608 -1 -1 495 355 32 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2792576 355 289 25456 18471 2 12407 1436 136 136 18496 dsp_top auto 180.7 MiB 13.83 368135 1183744 493906 488436 201402 2727.1 MiB 35.16 0.42 5.73066 -86703.7 -5.73066 2.25058 0.11 0.0983282 0.0890725 15.1492 13.7417 -1 399829 14 5.92627e+08 8.54694e+07 4.08527e+08 22087.3 7.31 19.1592 17.4802 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 799.06 vpr 2.68 GiB -1 -1 30.89 236424 5 69.76 -1 -1 112992 -1 -1 691 357 58 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2813040 357 289 25618 20285 2 12722 1661 136 136 18496 dsp_top auto 197.5 MiB 55.89 213644 1506110 545980 704875 255255 2747.1 MiB 49.90 0.35 8.83586 -77757.5 -8.83586 2.86849 0.11 0.105103 0.090362 16.4628 14.294 -1 283893 19 5.92627e+08 9.47716e+07 4.08527e+08 22087.3 8.40 21.5402 18.8962 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 3237.76 vpr 1.75 GiB -1 -1 126.10 731412 6 929.01 -1 -1 385924 -1 -1 3877 206 132 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1833128 206 13 164958 139473 1 69399 4340 88 88 7744 dsp_top auto 871.7 MiB 1763.83 586613 4179888 1553321 2546374 80193 1784.5 MiB 159.68 1.39 6.29198 -174132 -6.29198 6.29198 0.04 0.263075 0.225128 34.3779 28.6399 -1 859908 16 2.4541e+08 1.54779e+08 1.69370e+08 21871.2 23.49 48.5031 40.9766 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 918.71 vpr 2.01 GiB -1 -1 112.54 721200 3 53.45 -1 -1 407272 -1 -1 6192 260 0 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2104752 260 122 206293 154384 1 87490 6637 87 87 7569 clb auto 1055.8 MiB 200.86 911610 7737417 3028323 4214852 494242 1900.1 MiB 277.91 1.72 7.9787 -159676 -7.9787 7.9787 0.06 0.341965 0.297905 48.7798 40.5529 -1 1218227 15 2.37162e+08 1.8877e+08 1.65965e+08 21927.0 30.12 65.5345 55.1217 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 1191.18 vpr 3.18 GiB -1 -1 47.78 306884 5 13.75 -1 -1 130992 -1 -1 1017 1052 689 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 3339012 1052 32 45949 36457 1 23546 2888 148 148 21904 memory auto 263.0 MiB 454.46 385837 3230494 1321380 1766067 143047 3260.8 MiB 52.88 0.34 5.87433 -113350 -5.87433 5.87433 0.24 0.111118 0.0973142 18.7476 15.9101 -1 553277 14 7.00618e+08 1.48101e+08 4.83549e+08 22075.8 11.90 23.3539 19.9146 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 438.38 vpr 1.58 GiB -1 -1 34.58 250276 3 10.72 -1 -1 57100 -1 -1 1736 1016 21 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1661604 1016 2244 12839 14381 1 7080 5029 104 104 10816 io auto 118.5 MiB 54.63 69414 5776141 2967220 2032347 776574 1622.7 MiB 33.15 0.30 5.80519 -19744.2 -5.80519 5.80519 0.06 0.114 0.109937 15.6713 15.1362 -1 95582 12 3.44415e+08 5.43781e+07 2.37404e+08 21949.3 4.19 19.3247 18.6816 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 224.40 vpr 636.46 MiB -1 -1 19.66 145672 4 78.57 -1 -1 78688 -1 -1 822 91 56 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 651736 91 65 33180 28067 2 12875 1076 56 56 3136 dsp_top auto 204.4 MiB 13.58 151571 552176 183815 346994 21367 636.5 MiB 17.47 0.16 4.40509 -58703.1 -4.40509 1.89924 0.02 0.0783544 0.0686597 8.59202 7.37464 -1 224439 15 9.76016e+07 4.13053e+07 6.79229e+07 21659.1 6.09 12.1898 10.5564 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 116.04 vpr 569.43 MiB -1 -1 8.18 81248 4 6.69 -1 -1 53088 -1 -1 347 152 72 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 583100 152 97 14409 12199 2 6807 715 56 56 3136 dsp_top auto 117.4 MiB 7.36 124818 317119 107522 190476 19121 569.4 MiB 8.89 0.08 4.4815 -25326.7 -4.4815 1.84186 0.02 0.0480688 0.0422026 5.14069 4.43436 -1 186870 15 9.76016e+07 3.15225e+07 6.79229e+07 21659.1 4.38 7.18579 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 358788 37 17 16391 14146 1 8915 818 38 38 1444 memory auto 137.3 MiB 14.11 105295 279970 72756 197091 10123 350.4 MiB 10.45 0.13 7.06442 -39775.7 -7.06442 7.06442 0.01 0.0494477 0.0400803 3.91592 3.25677 -1 170768 15 4.31434e+07 2.70267e+07 3.09543e+07 21436.5 5.08 6.15937 5.24586 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 246.16 vpr 1.09 GiB -1 -1 14.70 182348 6 12.93 -1 -1 65636 -1 -1 640 82 232 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1146036 82 17 16311 14407 1 9001 1003 84 84 7056 memory auto 131.9 MiB 18.91 164110 517857 170628 329215 18014 1119.2 MiB 10.31 0.09 5.96682 -42713.4 -5.96682 5.96682 0.04 0.0429465 0.0371059 4.93488 4.13355 -1 221993 13 2.2198e+08 5.79185e+07 1.54484e+08 21894.0 3.85 6.78436 5.76686 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 126.95 vpr 532.81 MiB -1 -1 18.55 274480 10 7.84 -1 -1 54340 -1 -1 509 402 0 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 545596 402 150 12958 11781 1 7797 1098 54 54 2916 dsp_top auto 111.8 MiB 12.34 77765 759806 267210 447457 45139 532.8 MiB 11.70 0.09 9.87808 -14325.3 -9.87808 9.87808 0.02 0.0314036 0.0282571 4.5226 3.98994 -1 127390 16 8.95105e+07 2.35932e+07 6.32721e+07 21698.2 3.35 6.16259 5.47084 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params 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ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 403.97 vpr 2.65 GiB -1 -1 27.04 195044 5 106.86 -1 -1 105652 -1 -1 495 355 32 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2775544 355 289 25456 18471 2 12407 1436 136 136 18496 dsp_top auto 181.9 MiB 14.33 368181 1183744 474183 500499 209062 2710.5 MiB 50.60 0.36 6.27285 -87227.7 -6.27285 2.41691 0.16 0.0944157 0.083473 15.1293 13.4111 -1 -1 -1 -1 -1 397143 14 5.92627e+08 8.54694e+07 4.06343e+08 21969.2 7.49 19.5196 17.4915 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 485.95 vpr 2.66 GiB -1 -1 32.96 239408 5 93.21 -1 -1 112976 -1 -1 692 357 58 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2794012 357 289 25618 20285 2 12707 1662 136 136 18496 dsp_top auto 196.6 MiB 74.03 204219 1477662 530714 687623 259325 2728.5 MiB 65.29 0.50 8.71579 -77765.6 -8.71579 2.84893 0.14 0.106621 0.0894359 17.147 14.7028 -1 -1 -1 -1 -1 272598 15 5.92627e+08 9.47995e+07 4.06343e+08 21969.2 8.67 22.1078 19.1507 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 3187.00 vpr 1.76 GiB -1 -1 135.92 741364 6 1100.21 -1 -1 386172 -1 -1 3883 206 132 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1843948 206 13 164958 139473 1 69077 4346 88 88 7744 dsp_top auto 864.0 MiB 1603.34 598826 4152113 1544840 2523381 83892 1782.2 MiB 192.92 1.61 6.17742 -176710 -6.17742 6.17742 0.07 0.280575 0.239482 35.9089 29.7338 -1 -1 -1 -1 -1 874166 15 2.4541e+08 1.54946e+08 1.68961e+08 21818.3 23.70 50.4751 42.3862 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 980.53 vpr 2.01 GiB -1 -1 121.38 724396 3 65.16 -1 -1 413088 -1 -1 6188 260 0 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2111292 260 122 206293 154384 1 87503 6633 87 87 7569 clb auto 1048.9 MiB 248.33 933232 7793508 3012748 4270571 510189 1893.4 MiB 363.87 2.02 8.4354 -165730 -8.4354 8.4354 0.18 0.380851 0.332948 58.9838 49.134 -1 -1 -1 -1 -1 1241876 17 2.37162e+08 1.88658e+08 1.65555e+08 21872.8 35.08 80.5452 67.6492 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 1019.17 vpr 3.17 GiB -1 -1 50.11 309328 5 18.79 -1 -1 130796 -1 -1 1014 1052 689 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3321220 1052 32 45949 36457 1 23546 2885 148 148 21904 memory auto 265.1 MiB 621.52 376641 3225938 1321836 1766785 137317 3243.4 MiB 76.56 0.45 5.99366 -116290 -5.99366 5.99366 0.19 0.11632 0.101899 21.137 17.8618 -1 -1 -1 -1 -1 544069 15 7.00618e+08 1.48017e+08 4.81367e+08 21976.2 12.72 26.4051 22.4726 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 271.02 vpr 1.57 GiB -1 -1 34.97 254660 3 15.43 -1 -1 57052 -1 -1 1736 1016 21 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1650312 1016 2244 12839 14381 1 7081 5029 104 104 10816 io auto 117.8 MiB 63.44 68346 5733073 2929241 2032735 771097 1611.6 MiB 32.98 0.35 5.38086 -19733 -5.38086 5.38086 0.10 0.0995445 0.0938666 11.2455 10.5313 -1 -1 -1 -1 -1 92607 12 3.44415e+08 5.43781e+07 2.36688e+08 21883.2 3.62 14.072 13.2228 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 213.84 vpr 632.73 MiB -1 -1 20.39 146052 4 104.38 -1 -1 78744 -1 -1 822 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 647920 91 65 33180 28067 2 12875 1076 56 56 3136 dsp_top auto 201.5 MiB 15.44 158826 574220 192944 356720 24556 632.7 MiB 22.31 0.22 4.75154 -59481.6 -4.75154 1.95632 0.02 0.0860187 0.071022 9.6672 8.16677 -1 -1 -1 -1 -1 232357 14 9.76016e+07 4.13053e+07 6.76749e+07 21580.0 7.21 14.0547 12.1109 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 73.95 vpr 566.66 MiB -1 -1 8.53 82624 4 9.77 -1 -1 52912 -1 -1 347 152 72 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 580264 152 97 14409 12199 2 6807 715 56 56 3136 dsp_top auto 116.7 MiB 7.82 130332 301139 98285 185179 17675 566.7 MiB 10.85 0.09 4.58313 -25716.3 -4.58313 1.83211 0.02 0.0509694 0.0448212 4.90516 4.21666 -1 -1 -1 -1 -1 192276 17 9.76016e+07 3.15225e+07 6.76749e+07 21580.0 4.60 7.25998 6.31837 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 141.86 vpr 554.43 MiB -1 -1 27.53 239804 5 12.19 -1 -1 73308 -1 -1 879 3 84 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 567732 3 384 24647 23015 1 12378 1368 52 52 2704 memory auto 178.3 MiB 32.27 104695 783241 253492 461340 68409 554.4 MiB 22.37 0.20 6.19687 -42215.9 -6.19687 6.19687 0.02 0.0595205 0.0515804 6.95887 5.87936 -1 -1 -1 -1 -1 173357 15 8.30642e+07 4.06598e+07 5.83674e+07 21585.6 5.81 10.5413 8.96615 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 93.71 vpr 350.35 MiB -1 -1 25.19 304144 6 10.96 -1 -1 71232 -1 -1 712 37 52 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 358756 37 17 16391 14146 1 8915 818 38 38 1444 memory auto 138.1 MiB 16.31 103074 283794 73510 200452 9832 350.3 MiB 13.72 0.18 7.80678 -46783.6 -7.80678 7.80678 0.01 0.0569771 0.046255 4.57139 3.84797 -1 -1 -1 -1 -1 168838 15 4.31434e+07 2.70267e+07 3.08517e+07 21365.5 5.31 7.24145 6.19502 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 150.73 vpr 1.09 GiB -1 -1 15.53 192572 6 17.60 -1 -1 65652 -1 -1 640 82 232 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1139224 82 17 16311 14407 1 9001 1003 84 84 7056 memory auto 131.2 MiB 24.12 161654 512839 166422 330721 15696 1112.5 MiB 14.74 0.14 5.92411 -42285.5 -5.92411 5.92411 0.04 0.0545381 0.0484051 5.9995 4.95943 -1 -1 -1 -1 -1 221106 13 2.2198e+08 5.79185e+07 1.54074e+08 21835.9 5.32 8.85254 7.45605 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 97.02 vpr 529.11 MiB -1 -1 18.64 282652 10 10.36 -1 -1 54676 -1 -1 509 402 0 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 541812 402 150 12958 11781 1 7797 1098 54 54 2916 dsp_top auto 110.3 MiB 14.87 77639 782454 270167 471812 40475 529.1 MiB 16.11 0.11 9.76271 -14362.7 -9.76271 9.76271 0.02 0.0338217 0.030505 5.28917 4.58948 -1 -1 -1 -1 -1 127260 18 8.95105e+07 2.35932e+07 6.30449e+07 21620.3 3.66 7.21419 6.31064 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_multi_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_multi_arch/config/golden_results.txt index 4ea32240074..151af3ae337 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_multi_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_multi_arch/config/golden_results.txt @@ -1,12 +1,12 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 201.27 vpr 538.53 MiB -1 -1 14.22 148148 4 99.16 -1 -1 82672 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 551452 91 65 33165 28052 2 12600 1073 56 56 3136 dsp_top auto 244.3 MiB 9.12 161313 538.5 MiB 10.25 0.09 4.50414 -54857.1 -4.50414 1.86763 0.63 0.0333838 0.0282316 4.09029 3.44363 -1 232302 15 9.76016e+07 4.12216e+07 6.79229e+07 21659.1 4.09 6.05253 5.21178 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.mem_heavy.xml conv_layer.v common 145.29 vpr 432.02 MiB -1 -1 14.29 148156 4 71.59 -1 -1 82796 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 442384 91 65 33165 28052 2 12600 1073 43 43 1849 clb auto 243.1 MiB 9.11 141700 374.5 MiB 9.13 0.07 5.05127 -54802.7 -5.05127 1.99938 0.52 0.0334928 0.0286294 3.82869 3.23515 -1 215950 13 7.83573e+07 4.12216e+07 3.65050e+07 19743.1 3.80 5.6478 4.90047 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.dsp_heavy.xml conv_layer.v common 175.29 vpr 425.96 MiB -1 -1 14.26 148180 4 104.45 -1 -1 82784 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 436188 91 65 33165 28052 2 12600 1073 41 41 1681 clb auto 243.0 MiB 9.14 135366 360.1 MiB 9.58 0.08 4.81704 -54070.3 -4.81704 1.94407 0.52 0.0355404 0.0290583 4.00237 3.37018 -1 205971 13 6.86832e+07 4.12216e+07 3.32309e+07 19768.5 3.68 5.83621 5.04962 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.densest.xml conv_layer.v common 215.08 vpr 435.70 MiB -1 -1 14.07 148580 4 104.84 -1 -1 82748 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 446152 91 65 33165 28052 2 12600 1073 43 43 1849 clb auto 244.4 MiB 14.51 126010 378.6 MiB 17.73 0.14 4.60704 -53858.4 -4.60704 1.89311 0.99 0.0685799 0.0604241 7.88606 6.71765 -1 195885 13 7.74951e+07 4.12216e+07 3.64482e+07 19712.4 6.00 11.2599 9.77571 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.denser.xml conv_layer.v common 218.67 vpr 423.79 MiB -1 -1 14.11 148508 4 111.37 -1 -1 82700 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 433964 91 65 33165 28052 2 12600 1073 40 40 1600 dsp_top auto 244.3 MiB 14.50 127133 355.4 MiB 20.64 0.16 4.71204 -54567.2 -4.71204 1.91876 0.65 0.0660653 0.0576505 8.12915 6.95627 -1 197695 16 5.44678e+07 4.12216e+07 3.33594e+07 20849.6 6.51 11.6791 10.1644 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.xml conv_layer.v common 257.52 vpr 512.15 MiB -1 -1 14.06 148284 4 108.02 -1 -1 82780 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 524444 91 65 33165 28052 2 12600 1073 54 54 2916 dsp_top auto 244.3 MiB 14.39 165043 512.2 MiB 19.60 0.16 4.39914 -54861.3 -4.39914 1.84126 0.93 0.0635112 0.0550858 7.86487 6.68671 -1 235087 12 9.13586e+07 4.12216e+07 6.28961e+07 21569.3 6.53 10.879 9.43508 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.densest.xml conv_layer.v common 214.78 vpr 435.76 MiB -1 -1 14.42 148560 4 104.84 -1 -1 82804 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 446216 91 65 33165 28052 2 12600 1073 43 43 1849 clb auto 244.4 MiB 14.65 132661 377.4 MiB 17.65 0.17 4.84337 -57232 -4.84337 1.95037 0.91 0.0658165 0.0552913 6.93384 5.85998 -1 204199 14 7.74951e+07 4.12216e+07 3.63440e+07 19656.1 6.58 10.3395 8.94833 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.denser.xml conv_layer.v common 203.03 vpr 414.21 MiB -1 -1 14.15 148332 4 100.89 -1 -1 82752 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 424152 91 65 33165 28052 2 12600 1073 38 38 1444 dsp_top auto 244.3 MiB 14.63 131741 336.6 MiB 19.00 0.15 4.50414 -52753 -4.50414 1.86763 0.48 0.0615869 0.0512102 7.35096 6.22334 -1 201138 16 4.99286e+07 4.12216e+07 2.98368e+07 20662.6 6.51 10.7131 9.26785 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml conv_layer.v common 229.69 vpr 457.61 MiB -1 -1 14.36 148192 4 105.38 -1 -1 82732 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 468592 91 65 33165 28052 2 12600 1073 46 46 2116 dsp_top auto 244.2 MiB 14.35 163742 418.6 MiB 23.01 0.17 4.50414 -52223.7 -4.50414 1.86763 0.62 0.0692745 0.060974 9.21163 7.80464 -1 237659 14 6.74812e+07 4.12216e+07 4.51462e+07 21335.7 7.66 12.7137 10.978 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml conv_layer.v common 223.46 vpr 434.53 MiB -1 -1 14.27 147984 4 110.55 -1 -1 82748 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 444960 91 65 33165 28052 2 12600 1073 43 43 1849 clb auto 244.4 MiB 14.55 140324 375.6 MiB 19.88 0.18 4.39914 -53821.5 -4.39914 1.89924 0.92 0.0777626 0.0643673 8.28879 7.01624 -1 212267 13 7.79261e+07 4.12216e+07 3.65205e+07 19751.5 6.55 11.6902 10.082 -1 -1 -1 -1 -1 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vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 209.39 vpr 631.56 MiB -1 -1 21.81 147220 4 105.31 -1 -1 78736 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 646716 91 65 33168 28055 2 12932 1078 56 56 3136 dsp_top auto 201.1 MiB 14.31 161575 559103 183940 351790 23373 631.6 MiB 18.59 0.17 5.33784 -59139.7 -5.33784 2.07067 0.02 0.0802153 0.0702089 8.81529 7.5847 -1 -1 -1 -1 -1 237007 12 9.76016e+07 4.13612e+07 6.76749e+07 21580.0 5.30 11.9957 10.4294 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.mem_heavy.xml conv_layer.v common 210.23 vpr 434.48 MiB -1 -1 21.00 147272 4 120.27 -1 -1 78800 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 444908 91 65 33168 28055 2 12932 1078 43 43 1849 clb auto 201.3 MiB 13.95 131693 498328 148173 256931 93224 422.0 MiB 17.93 0.15 5.12994 -60661.1 -5.12994 2.02943 0.01 0.081656 0.0717278 8.66324 7.42728 -1 -1 -1 -1 -1 203979 14 7.83573e+07 4.13612e+07 3.63938e+07 19683.0 5.78 12.5079 10.8632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.dsp_heavy.xml conv_layer.v common 200.01 vpr 438.69 MiB -1 -1 19.66 147244 4 108.43 -1 -1 78680 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 449220 91 65 33168 28055 2 12932 1078 43 43 1849 clb auto 201.7 MiB 13.91 130722 492803 145153 258559 89091 425.8 MiB 19.17 0.16 5.22466 -59384.8 -5.22466 2.0229 0.01 0.0853547 0.0727941 7.86128 6.69514 -1 -1 -1 -1 -1 202633 12 7.68484e+07 4.13612e+07 3.62938e+07 19628.9 5.23 11.2863 9.7608 -1 -1 -1 -1 -1 -1 -1 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 434900 91 65 33168 28055 2 12932 1078 40 40 1600 dsp_top auto 200.7 MiB 14.04 127736 509378 152596 327280 29502 400.8 MiB 23.84 0.25 5.06525 -61364.6 -5.06525 2.00263 0.01 0.0876528 0.0722766 9.94011 8.43019 -1 -1 -1 -1 -1 198670 13 5.44678e+07 4.13612e+07 3.32516e+07 20782.2 6.69 13.8135 11.9182 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.xml conv_layer.v common 226.86 vpr 600.96 MiB -1 -1 22.15 147472 4 111.28 -1 -1 78832 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 615380 91 65 33168 28055 2 12932 1078 54 54 2916 dsp_top auto 200.8 MiB 15.79 163528 553578 180391 355481 17706 601.0 MiB 26.41 0.25 5.02494 -57585.7 -5.02494 1.99324 0.02 0.0961703 0.084176 9.91747 8.40538 -1 -1 -1 -1 -1 234187 13 9.13586e+07 4.13612e+07 6.26714e+07 21492.2 7.55 14.5116 12.5104 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.densest.xml conv_layer.v common 210.02 vpr 436.44 MiB -1 -1 22.14 147456 4 115.07 -1 -1 78656 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 446912 91 65 33168 28055 2 12932 1078 43 43 1849 clb auto 201.0 MiB 14.38 128673 525953 163254 311082 51617 423.9 MiB 21.60 0.23 4.91861 -57626.8 -4.91861 2.05887 0.01 0.0905403 0.0740438 8.94751 7.68095 -1 -1 -1 -1 -1 198326 14 7.74951e+07 4.13612e+07 3.62324e+07 19595.7 6.79 13.2038 11.4954 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 502744 91 65 33168 28055 2 12932 1078 46 46 2116 dsp_top auto 201.2 MiB 17.81 162148 564628 179853 365105 19670 491.0 MiB 29.12 0.24 4.74738 -55411.9 -4.74738 1.94955 0.02 0.082836 0.0734304 10.6462 8.98053 -1 -1 -1 -1 -1 236584 13 6.74812e+07 4.13612e+07 4.49964e+07 21264.8 7.17 14.3438 12.3068 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml conv_layer.v common 211.57 vpr 436.31 MiB -1 -1 21.32 147164 4 112.58 -1 -1 78640 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 446784 91 65 33168 28055 2 12932 1078 43 43 1849 clb auto 201.3 MiB 13.94 139418 531478 168663 322209 40606 423.4 MiB 23.75 0.20 4.8408 -58901.8 -4.8408 2.09368 0.02 0.0868457 0.0736702 9.1076 7.7586 -1 -1 -1 -1 -1 212208 14 7.79261e+07 4.13612e+07 3.64091e+07 19691.3 7.18 13.2356 11.4653 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.denser.xml conv_layer.v common 225.91 vpr 469.19 MiB -1 -1 21.45 147472 4 119.88 -1 -1 78956 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 480448 91 65 33168 28055 2 12932 1078 46 46 2116 dsp_top auto 201.3 MiB 15.84 142797 525953 163424 346380 16149 469.2 MiB 24.56 0.24 4.81704 -59254.1 -4.81704 2.0052 0.02 0.0994928 0.0874458 9.51869 8.05165 -1 -1 -1 -1 -1 215462 14 7.46848e+07 4.13612e+07 4.40267e+07 20806.6 7.57 14.1277 12.1525 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/golden_results.txt index 3415ce7747b..75076555a7a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/golden_results.txt @@ -1,13 +1,13 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 1163.23 vpr 2.73 GiB -1 -1 54.60 238712 5 135.74 -1 -1 136304 -1 -1 1086 355 32 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2859304 355 289 47773 39460 2 23092 2027 136 136 18496 dsp_top auto 259.8 MiB 421.52 425875 2028061 758608 1141225 128228 2792.3 MiB 37.94 0.25 7.49309 -111546 -7.49309 2.64155 0.10 0.0843162 0.070416 13.7807 11.5012 -1 535248 15 5.92627e+08 1.01961e+08 4.08527e+08 22087.3 8.61 17.6417 14.9058 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 1027.32 vpr 2.77 GiB -1 -1 46.58 296972 5 239.34 -1 -1 136156 -1 -1 1474 357 58 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2904916 357 289 56200 49059 2 22147 2444 136 136 18496 dsp_top auto 320.6 MiB 116.79 449929 2454388 935803 1390028 128557 2836.8 MiB 54.75 0.34 8.9901 -151330 -8.9901 2.89342 0.11 0.11259 0.0932 17.975 14.9021 -1 579981 15 5.92627e+08 1.1662e+08 4.08527e+08 22087.3 11.65 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v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2104736 260 122 206293 154384 1 87490 6637 87 87 7569 clb auto 1055.9 MiB 203.84 911610 7737417 3028323 4214852 494242 1900.2 MiB 254.43 1.57 7.9787 -159676 -7.9787 7.9787 0.07 0.317118 0.27396 46.0589 38.1983 -1 1218227 15 2.37162e+08 1.8877e+08 1.65965e+08 21927.0 29.18 62.4246 52.4257 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 1284.17 vpr 3.19 GiB -1 -1 55.27 306820 5 18.14 -1 -1 131152 -1 -1 1004 1052 690 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 3343432 1052 32 45960 36468 1 23568 2876 148 148 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9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 547812 151 97 23552 20376 2 11485 992 50 50 2500 memory auto 167.0 MiB 95.85 132973 525162 172354 326675 26133 535.0 MiB 14.60 0.15 4.78754 -25459.2 -4.78754 2.11147 0.01 0.0614346 0.0518776 6.9681 5.89089 -1 202188 14 7.5303e+07 3.00192e+07 5.42358e+07 21694.3 5.07 9.64823 8.26979 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 145.43 vpr 556.78 MiB -1 -1 24.72 234660 5 7.94 -1 -1 73196 -1 -1 873 3 84 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 570144 3 384 24672 23040 1 12367 1362 52 52 2704 memory auto 180.3 MiB 16.79 107156 771054 245311 455922 69821 556.8 MiB 19.27 0.16 6.07065 -42231.5 -6.07065 6.07065 0.02 0.056264 0.0478382 6.36102 5.35137 -1 174187 17 8.30642e+07 4.04924e+07 5.85728e+07 21661.5 5.28 9.30432 7.95656 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 107.13 vpr 351.39 MiB -1 -1 24.54 301764 6 7.81 -1 -1 70444 -1 -1 685 37 52 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 359824 37 17 16480 14235 1 8948 791 38 38 1444 memory auto 137.2 MiB 16.34 99313 271335 68101 193947 9287 351.4 MiB 10.82 0.13 6.55728 -42171.5 -6.55728 6.55728 0.01 0.0475515 0.041839 4.04663 3.44216 -1 162861 15 4.31434e+07 2.62733e+07 3.09543e+07 21436.5 5.13 6.43177 5.54111 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 241.53 vpr 1.09 GiB -1 -1 15.16 184108 6 12.35 -1 -1 64108 -1 -1 644 82 232 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1144196 82 17 16166 14262 1 8933 1007 84 84 7056 memory auto 130.1 MiB 17.36 163629 520642 168550 336267 15825 1117.4 MiB 10.40 0.09 6.14502 -42576.1 -6.14502 6.14502 0.04 0.0428761 0.0372263 4.90675 4.12616 -1 220423 14 2.2198e+08 5.80301e+07 1.54484e+08 21894.0 3.82 6.86146 5.84708 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 459.25 parmys 476.39 MiB -1 -1 62.80 487828 10 78.33 -1 -1 98584 -1 -1 1387 402 0 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 481464 402 150 35614 32642 1 17791 1947 43 43 1849 clb auto 243.7 MiB 211.58 124459 1192843 403919 739552 49372 469.4 MiB 33.95 0.29 10.2966 -28481.7 -10.2966 10.2966 0.01 0.0767148 0.0684923 8.56138 7.35741 -1 202624 16 5.60835e+07 4.07336e+07 3.97519e+07 21499.1 6.47 12.7366 11.0245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 482536 402 150 35614 32642 1 17785 1947 43 43 1849 clb auto 242.3 MiB 257.80 130074 1217147 415758 751584 49805 467.6 MiB 32.25 0.31 10.827 -28928.1 -10.827 10.827 0.01 0.0811184 0.0723576 8.76544 7.51492 -1 -1 -1 -1 -1 210517 16 5.60835e+07 4.07336e+07 3.96192e+07 21427.4 6.82 13.2832 11.4498 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt index 9b489cb8f38..ad3d51601b9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt @@ -1,15 +1,15 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength 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100 36 285842 271283 4 258743 11467 180 133 23940 M20K auto 2537.0 MiB 635.05 3438864 16426344 6351589 9654498 420257 4682.3 MiB 836.17 5.64 5.57216 -640841 -4.57216 4.33502 0.15 1.33213 1.04738 180.166 143.354 4193740 16.2086 887855 3.43152 848838 1626270 3464380030 716819176 0 0 4.25346e+08 17767.2 41 7099044 74943478 -1 5.713 4.31521 -1.12447e+06 -4.713 0 0 166.62 -1 -1 5231.1 MiB 957.21 290.023 234.525 4682.3 MiB -1 620.98 -stratix10_arch.timing.xml mes_noc_stratix10_arch_timing.blif common 7039.56 vpr 9.03 GiB 5 26001 0 64 736 8 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 9466652 3 2 594103 567321 9 550449 26814 206 153 31518 LAB auto 4791.3 MiB 1557.81 4892389 47362160 17896376 28168353 1297431 7205.1 MiB 3476.21 33.65 9.295 -2.17146e+06 -8.295 7.77804 0.25 2.24529 1.76453 287.641 225.909 5339983 9.70812 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neuron_stratix10_arch_timing.blif common 833.04 vpr 2.00 GiB 133 5234 0 243 108 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2093464 40 93 140673 125393 2 123625 5719 94 70 6580 LAB auto 1201.5 MiB 289.44 634340 6191360 2301274 3623602 266484 1729.3 MiB 370.55 2.45 5.84744 -64925.2 -4.84744 3.3402 0.04 0.387587 0.340417 48.3195 39.815 517953 4.19141 138793 1.12315 268394 383043 84540966 19817319 0 0 1.15552e+08 17561.0 18 1898072 20093317 -1 5.799 3.20378 -122888 -4.799 0 0 43.46 -1 -1 1880.4 MiB 41.18 67.4246 56.3964 1729.3 MiB -1 33.19 + stratix10_arch.timing.xml sparcT1_core_stratix10_arch_timing.blif common 1320.68 vpr 3.03 GiB 309 4982 0 6 154 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3176516 172 137 98039 97359 1 91845 5451 163 121 19723 io_cell auto 1048.7 MiB 416.44 1174053 5471979 2094519 3176216 201244 3102.1 MiB 483.40 4.56 7.15 -378395 -6.15 7.15 0.24 0.484867 0.374331 56.8899 45.3278 1526584 16.6220 347043 3.77874 324019 943132 297819952 53503048 0 0 3.51754e+08 17834.7 17 5914532 61913217 -1 6.938 6.938 -458652 -5.938 0 0 133.69 -1 -1 3102.1 MiB 111.14 80.1902 65.1665 3102.1 MiB -1 117.12 + stratix10_arch.timing.xml stereo_vision_stratix10_arch_timing.blif common 1336.40 vpr 7.73 GiB 506 5363 0 76 83 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 8102372 172 334 150507 118033 3 110735 6028 287 213 61131 io_cell auto 1114.7 MiB 159.83 546089 6696142 2566220 3885626 244296 7912.5 MiB 322.65 2.23 7.71363 -39076.7 -6.71363 7.71363 0.65 0.328993 0.270482 46.9904 37.5447 427507 3.86091 120235 1.08587 235293 320005 60687000 12277011 0 0 1.10789e+09 18123.3 15 18464012 193849399 -1 6.984 6.984 -51229.8 -5.984 0 0 404.36 -1 -1 7912.5 MiB 33.81 63.8841 51.9403 7912.5 MiB -1 343.62 + stratix10_arch.timing.xml cholesky_mc_stratix10_arch_timing.blif common 998.97 vpr 2.81 GiB 262 4835 115 131 382 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2944676 111 151 145547 131782 1 127404 5725 147 109 16023 io_cell auto 1301.4 MiB 282.50 801498 5790534 2145233 3342854 302447 2875.7 MiB 400.69 3.54 5.008 -92090.6 -4.008 4.559 0.09 0.537432 0.455738 62.8576 51.5026 805259 6.32071 212196 1.66559 300273 509257 150845866 34700709 0 0 2.85989e+08 17848.6 13 4788948 50134206 -1 4.488 4.083 -213947 -3.488 0 0 101.11 -1 -1 2875.7 MiB 61.86 84.7937 70.3971 2875.7 MiB -1 81.78 + stratix10_arch.timing.xml LU_Network_stratix10_arch_timing.blif common 8279.37 vpr 17.68 GiB 748 30526 826 224 1026 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 18535564 325 423 817452 760174 3 681111 33351 406 301 122206 io_cell auto 5546.8 MiB 1827.39 4732164 74080701 31510919 39435236 3134546 18101.1 MiB 4227.97 28.65 4.76071 -319191 -3.76071 4.69287 0.96 2.78373 2.33996 398.847 330.305 4439564 6.52395 1123896 1.65157 1562719 2598341 607571135 128284629 0 0 2.23450e+09 18284.7 12 36989044 388958102 -1 4.7 4.64063 -440709 -3.7 0 0 899.60 -1 -1 18101.1 MiB 247.43 493.191 412.334 18101.1 MiB -1 737.58 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium/config/golden_results.txt index 5301c84b184..5351d6583d8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium/config/golden_results.txt @@ -1,13 +1,13 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 1005.52 vpr 2.71 GiB 226.57 236200 -1 -1 5 152.30 -1 -1 116652 -1 -1 536 355 32 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2837056 355 289 26113 19088 2 12674 1488 136 136 18496 dsp_top auto 269.1 MiB 18.30 370957 1207210 471810 528572 206828 2770.6 MiB 52.32 0.57 5.98706 -87526.7 -5.98706 2.21181 0.11 0.161567 0.147397 23.7018 21.6403 -1 407074 13 5.92627e+08 8.94049e+07 4.08527e+08 22087.3 8.08 29.7625 27.3592 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 1195.09 vpr 2.73 GiB 342.13 302328 -1 -1 7 164.42 -1 -1 127540 -1 -1 1029 357 58 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2861412 357 289 30369 24839 2 17327 2011 136 136 18496 dsp_top auto 260.2 MiB 65.60 221282 1943275 763450 845285 334540 2794.3 MiB 60.29 0.43 9.44576 -79017.3 -9.44576 2.96583 0.11 0.145986 0.128353 23.0491 20.2846 -1 291408 15 5.92627e+08 1.07248e+08 4.08527e+08 22087.3 9.05 29.0776 25.7841 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 3054.95 vpr 2.07 GiB 22.84 653108 -1 -1 5 1540.96 -1 -1 567504 -1 -1 4756 206 132 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2172736 206 13 208395 166387 1 84813 5235 90 90 8100 dsp_top auto 1096.5 MiB 1034.75 662081 5321247 1974867 3264938 81442 2013.0 MiB 170.41 1.37 4.84922 -185838 -4.84922 4.84922 0.06 0.316161 0.272947 41.3931 34.2165 -1 964636 16 2.56465e+08 1.83367e+08 1.77260e+08 21883.9 25.11 57.5569 48.2341 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 1083.89 vpr 2.10 GiB 27.69 498048 -1 -1 3 134.73 -1 -1 495220 -1 -1 5693 260 0 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2205660 260 122 231647 179602 1 86860 6138 83 83 6889 clb auto 1178.5 MiB 302.54 908164 6522438 2525997 3694260 302181 1905.2 MiB 256.57 1.79 7.71077 -154889 -7.71077 7.71077 0.06 0.394039 0.34347 50.9118 42.0537 -1 1204095 18 2.13666e+08 1.74846e+08 1.51189e+08 21946.4 35.45 71.703 59.874 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 1348.58 vpr 3.25 GiB 8.87 584856 -1 -1 7 33.82 -1 -1 285544 -1 -1 1929 1057 690 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 3411020 1057 32 57517 46908 1 31258 3845 148 148 21904 memory auto 354.4 MiB 506.08 410126 4971995 2186012 2431068 354915 3331.1 MiB 93.36 0.54 8.74294 -119537 -8.74294 8.74294 0.13 0.137611 0.121189 24.2699 20.8366 -1 593896 15 7.00618e+08 1.83584e+08 4.83549e+08 22075.8 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v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 672488 91 65 36754 30551 2 13677 1194 56 56 3136 dsp_top auto 229.0 MiB 17.73 168550 665949 228412 410610 26927 656.7 MiB 17.90 0.16 4.73837 -61660.6 -4.73837 2.04692 0.02 0.0838265 0.0708925 9.27571 7.93974 -1 242849 14 9.76016e+07 4.45981e+07 6.79229e+07 21659.1 5.79 12.8334 11.1116 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 139.99 vpr 570.45 MiB 2.30 82748 -1 -1 4 42.87 -1 -1 68740 -1 -1 358 152 72 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 584136 152 97 14052 11986 2 6814 729 56 56 3136 dsp_top auto 118.8 MiB 6.82 128735 345024 117764 203974 23286 570.4 MiB 9.34 0.09 4.47241 -24858.2 -4.47241 1.84076 0.02 0.0495891 0.042571 5.39741 4.63942 -1 191960 19 9.76016e+07 3.25907e+07 6.79229e+07 21659.1 4.98 7.73343 6.71312 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 279.44 vpr 594.62 MiB 101.07 368044 -1 -1 6 34.48 -1 -1 150452 -1 -1 1279 3 96 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 608892 3 384 30303 28383 1 14742 1780 52 52 2704 memory auto 226.7 MiB 25.40 135654 1133995 376682 677395 79918 594.6 MiB 24.95 0.23 6.41197 -44163.1 -6.41197 6.41197 0.01 0.0699692 0.0608779 8.037 6.84238 -1 223038 16 8.30642e+07 5.34735e+07 5.85728e+07 21661.5 6.19 11.6692 10.061 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 110.67 vpr 362.37 MiB 1.69 80180 -1 -1 6 24.58 -1 -1 68036 -1 -1 804 37 52 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 371068 37 17 18215 15970 1 9561 910 38 38 1444 memory auto 151.6 MiB 16.24 109644 344734 93069 242280 9385 362.4 MiB 16.22 0.17 6.86392 -40596.4 -6.86392 6.86392 0.01 0.0544984 0.0479428 5.76733 4.90569 -1 179767 16 4.31434e+07 2.95939e+07 3.09543e+07 21436.5 6.19 8.49981 7.32043 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 295.41 vpr 1.10 GiB 23.59 694880 -1 -1 6 23.24 -1 -1 253836 -1 -1 506 82 232 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1150664 82 17 16284 14380 1 8446 869 84 84 7056 memory auto 137.0 MiB 16.59 155490 423659 134240 273173 16246 1123.7 MiB 10.22 0.09 6.1436 -40944.1 -6.1436 6.1436 0.04 0.0467929 0.0405177 5.46221 4.52238 -1 210725 14 2.2198e+08 5.41794e+07 1.54484e+08 21894.0 4.14 7.55015 6.35415 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 131.32 vpr 595.07 MiB 1.96 102800 -1 -1 10 9.50 -1 -1 52060 -1 -1 513 402 0 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 609352 402 150 13003 11825 1 7723 1118 58 58 3364 dsp_top auto 113.2 MiB 12.34 74102 778318 278328 454520 45470 595.1 MiB 12.61 0.10 9.53955 -14550.9 -9.53955 9.53955 0.02 0.0332241 0.0286889 4.82541 4.17824 -1 122561 16 1.04637e+08 2.77652e+07 7.29687e+07 21691.1 3.40 6.5043 5.68128 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est 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7.42118 -1 -1 -1 -1 -1 224233 20 8.30642e+07 5.35851e+07 5.83674e+07 21585.6 7.14 13.233 11.3173 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 78.85 vpr 361.96 MiB 1.67 80272 -1 -1 6 20.55 -1 -1 68072 -1 -1 804 37 52 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 370644 37 17 18215 15970 1 9561 910 38 38 1444 memory auto 151.2 MiB 14.13 110676 331510 86677 232626 12207 362.0 MiB 12.77 0.15 6.68572 -41665.7 -6.68572 6.68572 0.01 0.046345 0.0403322 4.00773 3.36654 -1 -1 -1 -1 -1 185110 15 4.31434e+07 2.95939e+07 3.08517e+07 21365.5 4.82 6.23238 5.33371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 169.07 vpr 1.09 GiB 22.30 694892 -1 -1 6 22.40 -1 -1 253836 -1 -1 506 82 232 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1143196 82 17 16284 14380 1 8446 869 84 84 7056 memory auto 136.0 MiB 16.96 154702 407079 126171 268174 12734 1116.4 MiB 9.30 0.09 5.66212 -41728 -5.66212 5.66212 0.04 0.0408504 0.0349241 4.46319 3.68799 -1 -1 -1 -1 -1 213813 13 2.2198e+08 5.41794e+07 1.54074e+08 21835.9 3.29 6.26987 5.27694 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 85.45 vpr 591.82 MiB 3.32 102836 -1 -1 10 10.53 -1 -1 51956 -1 -1 513 402 0 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 606028 402 150 13003 11825 1 7723 1118 58 58 3364 dsp_top auto 112.2 MiB 12.65 78213 784118 280792 458671 44655 591.8 MiB 13.64 0.10 9.87074 -14553.8 -9.87074 9.87074 0.02 0.0323667 0.0289675 4.75222 4.19081 -1 -1 -1 -1 -1 125779 16 1.04637e+08 2.77652e+07 7.26973e+07 21610.4 3.19 6.43415 5.71727 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_multi_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_multi_arch/config/golden_results.txt index 6dfb7ea9826..fbc506a606b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_multi_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_multi_arch/config/golden_results.txt @@ -1,12 +1,12 @@ - arch circuit script_params vtr_flow_elapsed_time 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91 56 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 537920 91 65 41142 34939 2 16599 1337 48 48 2304 clb auto 305.0 MiB 38.98 163179 471.4 MiB 18.53 0.16 4.81221 -66909.8 -4.81221 2.86497 1.13 0.0776173 0.0661688 8.38542 7.23676 -1 247004 14 9.6957e+07 4.85884e+07 4.55250e+07 19759.1 5.95 11.8313 10.3727 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.denser.xml conv_layer.v common 539.93 vpr 491.85 MiB 9.97 221724 -1 -1 4 349.08 -1 -1 115896 -1 -1 1083 91 56 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 503652 91 65 41142 34939 2 16599 1337 41 41 1681 clb auto 305.3 MiB 45.84 158804 405.7 MiB 26.80 0.17 4.53047 -58733.1 -4.53047 2.63958 0.42 0.0800797 0.0678513 11.0399 9.54718 -1 241163 14 5.66164e+07 4.85884e+07 3.51492e+07 20909.7 8.36 15.3368 13.416 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml conv_layer.v common 552.23 vpr 520.43 MiB 10.18 221740 -1 -1 4 358.01 -1 -1 115896 -1 -1 1083 91 56 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 532916 91 65 41142 34939 2 16599 1337 46 46 2116 dsp_top auto 305.1 MiB 34.17 184689 460.1 MiB 29.94 0.17 4.63337 -57913.5 -4.63337 2.41469 0.50 0.07569 0.067726 12.3739 10.6816 -1 272497 15 6.74812e+07 4.85884e+07 4.51462e+07 21335.7 8.61 17.2022 14.9931 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml conv_layer.v common 550.75 vpr 519.12 MiB 10.54 221572 -1 -1 4 348.65 -1 -1 115800 -1 -1 1083 91 56 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 531584 91 65 41142 34939 2 16599 1337 47 47 2209 clb auto 304.8 MiB 48.64 178357 460.2 MiB 24.25 0.18 4.84337 -59160.5 -4.84337 2.55397 0.93 0.079042 0.066954 10.2961 8.81958 -1 265197 21 9.21907e+07 4.85884e+07 4.39475e+07 19894.7 9.90 16.6973 14.4877 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.denser.xml conv_layer.v common 622.19 vpr 516.96 MiB 8.22 221740 -1 -1 4 461.76 -1 -1 115856 -1 -1 1083 91 56 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 529372 91 65 41142 34939 2 16599 1337 46 46 2116 dsp_top auto 305.1 MiB 37.01 172015 455.7 MiB 21.46 0.17 4.49931 -59023.2 -4.49931 2.85425 0.66 0.0776131 0.0663591 9.31061 8.05832 -1 256997 15 7.46848e+07 4.85884e+07 4.41698e+07 20874.2 6.79 12.9038 11.3254 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 352.51 vpr 672.43 MiB 4.76 215088 -1 -1 4 212.03 -1 -1 115768 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 688568 91 65 41142 34939 2 16392 1336 56 56 3136 dsp_top auto 252.0 MiB 41.39 185989 788321 264351 491679 32291 672.4 MiB 23.41 0.24 5.1805 -69731.6 -5.1805 2.99286 0.03 0.106537 0.0943177 10.5152 8.9603 -1 -1 -1 -1 -1 272192 13 9.76016e+07 4.85605e+07 6.76749e+07 21580.0 6.74 14.526 12.573 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.mem_heavy.xml conv_layer.v common 366.41 vpr 548.82 MiB 7.70 215196 -1 -1 4 234.35 -1 -1 115928 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 561996 91 65 41142 34939 2 16392 1336 49 49 2401 clb auto 252.1 MiB 42.27 171761 714771 223295 366878 124598 548.8 MiB 19.99 0.17 5.36417 -65640.6 -5.36417 2.69709 0.01 0.0879771 0.0748201 9.14144 7.79307 -1 -1 -1 -1 -1 257693 13 1.02711e+08 4.85605e+07 4.74635e+07 19768.2 5.56 12.7444 11.0222 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + 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-1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.densest.xml conv_layer.v common 388.30 vpr 525.20 MiB 7.03 215020 -1 -1 4 244.58 -1 -1 115972 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 537808 91 65 41142 34939 2 16392 1336 48 48 2304 clb auto 251.2 MiB 41.38 168856 729481 233033 429510 66938 522.9 MiB 26.06 0.23 5.57207 -68353.3 -5.57207 2.79807 0.01 0.0981234 0.0838068 10.5056 8.98586 -1 -1 -1 -1 -1 251682 13 9.6957e+07 4.85605e+07 4.53839e+07 19697.9 6.45 14.4956 12.5587 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.denser.xml conv_layer.v common 396.82 vpr 493.34 MiB 7.41 215104 -1 -1 4 257.13 -1 -1 115940 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 505180 91 65 41142 34939 2 16392 1336 41 41 1681 clb auto 251.2 MiB 42.40 159936 729481 233674 452058 43749 454.7 MiB 25.78 0.22 5.12784 -65245 -5.12784 2.64326 0.01 0.0973349 0.0824972 10.3536 8.83427 -1 -1 -1 -1 -1 244692 15 5.66164e+07 4.85605e+07 3.50349e+07 20841.7 6.84 14.6337 12.6436 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml conv_layer.v common 373.28 vpr 531.82 MiB 7.65 215144 -1 -1 4 227.23 -1 -1 115832 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 544584 91 65 41142 34939 2 16392 1336 46 46 2116 dsp_top auto 251.8 MiB 42.06 179779 788321 265913 498199 24209 531.8 MiB 27.49 0.24 4.91721 -63756.1 -4.91721 2.8055 0.01 0.0985794 0.0827707 11.0738 9.46404 -1 -1 -1 -1 -1 266992 15 6.74812e+07 4.85605e+07 4.49964e+07 21264.8 7.05 15.3643 13.283 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml conv_layer.v common 363.98 vpr 519.44 MiB 7.51 215156 -1 -1 4 221.45 -1 -1 115824 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 531904 91 65 41142 34939 2 16392 1336 47 47 2209 clb auto 251.7 MiB 42.06 177363 751546 238898 455950 56698 511.2 MiB 26.88 0.25 5.74439 -66669.2 -5.74439 2.74926 0.01 0.0976305 0.0834431 10.6585 9.11403 -1 -1 -1 -1 -1 261596 14 9.21907e+07 4.85605e+07 4.38118e+07 19833.3 6.58 14.768 12.7775 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.denser.xml conv_layer.v common 367.47 vpr 517.34 MiB 7.31 215140 -1 -1 4 226.59 -1 -1 115900 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 529760 91 65 41142 34939 2 16392 1336 46 46 2116 dsp_top auto 251.9 MiB 42.40 164706 758901 240199 496773 21929 509.8 MiB 24.50 0.23 5.0259 -67286.9 -5.0259 3.01666 0.01 0.0942614 0.0802815 10.2047 8.7176 -1 -1 -1 -1 -1 250051 15 7.46848e+07 4.85605e+07 4.40267e+07 20806.6 6.53 14.2812 12.3585 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/golden_results.txt index 11c2ef07254..8578fd23aeb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/golden_results.txt @@ -1,13 +1,13 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 1104.28 vpr 2.74 GiB 8.74 244108 -1 -1 5 297.77 -1 -1 157688 -1 -1 1178 355 32 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2878052 355 289 49464 41111 2 23907 2130 136 136 18496 dsp_top auto 281.5 MiB 311.65 435995 1714505 687626 949597 77282 2810.6 MiB 27.83 0.21 7.35242 -116388 -7.35242 2.95155 0.10 0.0834697 0.0680869 11.0641 9.1222 -1 549370 16 5.92627e+08 1.0732e+08 4.08527e+08 22087.3 8.77 15.1062 12.6676 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 946.59 vpr 2.73 GiB 45.54 310812 -1 -1 6 239.52 -1 -1 130016 -1 -1 1360 357 58 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2858436 357 289 42535 35250 2 20674 2341 136 136 18496 dsp_top auto 263.7 MiB 81.22 258365 2503798 912690 1363844 227264 2791.4 MiB 39.95 0.25 9.41317 -93875.2 -9.41317 3.62083 0.11 0.0885806 0.077004 15.1656 12.8314 -1 352592 15 5.92627e+08 1.16231e+08 4.08527e+08 22087.3 7.12 19.1834 16.3728 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 3217.39 vpr 2.18 GiB 28.60 695084 -1 -1 5 1560.40 -1 -1 610904 -1 -1 5655 206 120 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2282904 206 13 227613 180877 1 96129 6122 90 90 8100 dsp_top auto 1187.9 MiB 1109.94 702117 7283522 2749583 4223771 310168 2056.0 MiB 220.80 1.60 8.302 -169079 -8.302 8.302 0.06 0.341171 0.278004 46.9752 39.1979 -1 1004001 20 2.56465e+08 2.06801e+08 1.77260e+08 21883.9 28.39 66.1255 55.7608 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 1047.76 vpr 2.10 GiB 28.88 498080 -1 -1 3 140.62 -1 -1 495040 -1 -1 5693 260 0 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2205640 260 122 231647 179602 1 86860 6138 83 83 6889 clb auto 1178.3 MiB 300.36 908164 6522438 2525997 3694260 302181 1905.0 MiB 230.15 1.64 7.71077 -154889 -7.71077 7.71077 0.06 0.377722 0.328092 49.8268 40.9656 -1 1204095 18 2.13666e+08 1.74846e+08 1.51189e+08 21946.4 34.10 69.5248 57.8328 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 1979.21 vpr 5.52 GiB 9.31 622444 -1 -1 8 52.62 -1 -1 296696 -1 -1 2585 1048 1166 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5787156 1048 32 64005 53342 1 37416 4967 196 196 38416 memory auto 399.5 MiB 726.19 576620 7121615 3271863 3293671 556081 5651.5 MiB 80.75 0.52 9.33408 -152227 -9.33408 9.33408 0.41 0.140445 0.113396 24.2142 20.0817 -1 762815 13 1.23531e+09 2.67163e+08 8.45266e+08 22003.0 13.94 29.7133 24.9109 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 843.36 odin 3.93 GiB 126.10 4122888 -1 -1 7 45.84 -1 -1 1641428 -1 -1 1890 1016 21 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1776404 1016 2283 16425 17373 1 9249 5212 106 106 11236 io auto 146.6 MiB 83.53 74673 6193502 3147425 2242332 803745 1734.8 MiB 37.16 0.36 13.5303 -24849.4 -13.5303 13.5303 0.06 0.122239 0.118475 17.0221 16.3404 -1 107886 17 3.5748e+08 5.61376e+07 2.46822e+08 21967.1 6.15 22.279 21.3779 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 613.28 vpr 997.71 MiB 7.57 229260 -1 -1 4 300.66 -1 -1 135308 -1 -1 1377 91 56 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1021656 91 65 51897 44206 2 22450 1673 72 72 5184 dsp_top auto 308.4 MiB 72.85 233523 1103570 376406 686486 40678 997.7 MiB 37.99 0.31 5.75091 -95999.9 -5.75091 3.49463 0.03 0.116483 0.0978631 13.6034 11.5102 -1 328320 15 1.63139e+08 6.74509e+07 1.13044e+08 21806.4 8.55 18.6242 15.9639 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 719.12 vpr 606.31 MiB 19.99 354312 -1 -1 5 168.14 -1 -1 123840 -1 -1 1413 152 72 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 620864 152 97 41796 36054 2 19766 1740 50 50 2500 memory auto 279.1 MiB 388.21 177823 1413975 463973 858189 91813 606.3 MiB 37.09 0.26 5.657 -34829.9 -5.657 3.0521 0.01 0.0907473 0.0792665 13.8393 11.6985 -1 266013 16 7.5303e+07 5.08635e+07 5.42358e+07 21694.3 7.83 18.3398 15.6629 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 567.27 vpr 607.77 MiB 175.53 368912 -1 -1 6 52.01 -1 -1 159520 -1 -1 1317 3 96 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 622360 3 384 32137 30217 1 16402 1818 52 52 2704 memory auto 242.0 MiB 212.45 148363 1144191 372510 692675 79006 607.8 MiB 27.66 0.25 6.51487 -55563.8 -6.51487 6.51487 0.01 0.0761583 0.0664108 8.73148 7.46125 -1 239481 19 8.30642e+07 5.45339e+07 5.85728e+07 21661.5 7.63 13.2929 11.446 -1 -1 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1130640 61 17 22163 20259 1 12984 1103 82 82 6724 memory auto 171.1 MiB 342.05 164941 770063 247069 479249 43745 1104.1 MiB 14.47 0.10 5.93366 -38288.7 -5.93366 5.93366 0.04 0.0461013 0.039822 6.95092 5.71641 -1 219396 14 2.09174e+08 5.75629e+07 1.47429e+08 21925.8 4.08 9.24081 7.71683 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 420.46 vpr 507.89 MiB 9.71 331692 -1 -1 10 97.61 -1 -1 108204 -1 -1 1452 402 0 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 520080 402 150 39533 35581 1 18244 2012 44 44 1936 clb auto 266.4 MiB 221.27 128967 1271612 435167 794322 42123 501.0 MiB 25.69 0.24 9.7645 -28088.4 -9.7645 9.7645 0.01 0.0759782 0.0621098 8.12017 6.77196 -1 211193 15 5.86452e+07 4.25474e+07 4.16874e+07 21532.7 5.88 11.9476 10.1852 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 824.78 vpr 2.73 GiB 9.30 244232 -1 -1 5 260.22 -1 -1 157748 -1 -1 1192 355 32 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2859788 355 289 49464 41111 2 23764 2144 136 136 18496 dsp_top auto 279.7 MiB 295.81 418901 1701881 672511 951428 77942 2792.8 MiB 37.25 0.28 7.18019 -112184 -7.18019 3.27937 0.10 0.0928828 0.0762025 12.0598 9.97865 -1 -1 -1 -1 -1 532162 15 5.92627e+08 1.0771e+08 4.06343e+08 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0.22 0.14375 0.125397 26.449 22.1984 -1 -1 -1 -1 -1 761348 13 1.23531e+09 2.67861e+08 8.43084e+08 21946.2 12.71 32.4298 27.4366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 672.06 odin 3.93 GiB 129.42 4122772 -1 -1 7 42.43 -1 -1 1641328 -1 -1 1889 1016 21 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1764592 1016 2283 16425 17373 1 9246 5211 106 106 11236 io auto 145.9 MiB 84.88 74748 6237015 3200275 2226899 809841 1723.2 MiB 38.03 0.41 13.4488 -25176.8 -13.4488 13.4488 0.08 0.124806 0.120975 16.9313 16.2814 -1 -1 -1 -1 -1 105692 19 3.5748e+08 5.61097e+07 2.46019e+08 21895.6 6.63 22.7872 21.9276 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 509.40 vpr 994.21 MiB 7.63 229352 -1 -1 4 291.50 -1 -1 135308 -1 -1 1384 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1018076 91 65 51897 44206 2 22455 1680 72 72 5184 dsp_top auto 306.6 MiB 73.16 228853 1089827 378190 671197 40440 994.2 MiB 34.83 0.26 5.70153 -99928.4 -5.70153 3.13057 0.03 0.106655 0.0885957 12.4295 10.5046 -1 -1 -1 -1 -1 326314 16 1.63139e+08 6.76462e+07 1.12634e+08 21727.3 7.66 17.2977 14.7855 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 639.48 vpr 604.25 MiB 18.92 354340 -1 -1 5 163.25 -1 -1 123992 -1 -1 1341 152 72 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 618756 152 97 41796 36054 2 19741 1668 50 50 2500 memory auto 276.5 MiB 353.29 182641 1138788 375858 705982 56948 604.3 MiB 34.19 0.28 5.26502 -34149.4 -5.26502 3.08759 0.01 0.0964297 0.0809839 11.7416 9.89389 -1 -1 -1 -1 -1 272498 15 7.5303e+07 4.88544e+07 5.40494e+07 21619.8 6.94 15.9939 13.6389 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 546.92 vpr 605.04 MiB 154.33 369052 -1 -1 6 48.81 -1 -1 159492 -1 -1 1317 3 96 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 619556 3 384 32137 30217 1 16367 1818 52 52 2704 memory auto 242.8 MiB 239.93 144112 1133100 365554 689391 78155 605.0 MiB 35.61 0.31 6.41197 -56602.2 -6.41197 6.41197 0.02 0.0848867 0.0696734 9.19789 7.83126 -1 -1 -1 -1 -1 236714 16 8.30642e+07 5.45339e+07 5.83674e+07 21585.6 6.70 13.3346 11.5003 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 98.78 vpr 363.29 MiB 1.84 89352 -1 -1 6 26.10 -1 -1 76656 -1 -1 919 37 52 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 372012 37 17 22150 19905 1 11787 1025 38 38 1444 memory auto 170.0 MiB 16.96 135894 398807 104287 286810 7710 363.3 MiB 19.99 0.23 7.06559 -49254.7 -7.06559 7.06559 0.01 0.0623857 0.0549943 5.52111 4.6572 -1 -1 -1 -1 -1 207543 14 4.31434e+07 3.28029e+07 3.08517e+07 21365.5 5.40 8.56273 7.34463 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 494.03 vpr 1.07 GiB 22.80 719364 -1 -1 6 32.64 -1 -1 262680 -1 -1 803 61 198 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1124736 61 17 22163 20259 1 12877 1111 82 82 6724 memory auto 170.8 MiB 318.30 161978 720111 230341 449967 39803 1098.4 MiB 16.20 0.11 5.96789 -38891.9 -5.96789 5.96789 0.04 0.0460451 0.0397049 7.16927 6.05082 -1 -1 -1 -1 -1 215986 16 2.09174e+08 5.77861e+07 1.47019e+08 21864.8 4.01 9.6201 8.19901 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 421.69 vpr 509.21 MiB 10.11 331792 -1 -1 10 107.99 -1 -1 107828 -1 -1 1454 402 0 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 521432 402 150 39533 35581 1 18242 2014 44 44 1936 clb auto 264.4 MiB 222.03 128276 1298740 437176 815390 46174 499.3 MiB 33.29 0.31 9.64776 -28385.1 -9.64776 9.64776 0.01 0.0772257 0.0685146 9.05102 7.67437 -1 -1 -1 -1 -1 211161 16 5.86452e+07 4.26032e+07 4.15480e+07 21460.7 6.45 13.3481 11.4668 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/golden_results.txt index f404891e152..83cca486bd7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/golden_results.txt @@ -1,10 +1,10 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_IO num_CLB num_DSP num_BRAM vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time -ultrascale_ispd.xml FPGA-example1.blif common 101.39 vpr 5.30 GiB 72 220 2 2 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 5555300 51 20 3417 3407 1 3287 296 168 480 80640 -1 ultrascale_ispd 63.2 MiB 4.52 30370 5425.1 MiB 0.76 0.01 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml clk_design1.blif common 108.35 vpr 5.32 GiB 109 592 2 2 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 5579688 57 20 9969 9959 30 9711 705 168 480 80640 -1 ultrascale_ispd 103.1 MiB 8.18 68744 5448.9 MiB 3.20 0.02 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml clk_design2.blif common 311.90 vpr 5.64 GiB 244 5837 10 10 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 5911804 137 60 100115 100025 45 97978 6101 168 480 80640 -1 ultrascale_ispd 649.1 MiB 83.42 1215177 5773.2 MiB 119.64 0.75 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml clk_design3.blif common 1513.69 vpr 6.60 GiB 374 22993 50 96 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 6917624 217 120 400080 399454 35 390926 23513 168 480 80640 -1 ultrascale_ispd 2324.6 MiB 224.93 5853155 6755.5 MiB 1160.59 7.01 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml FPGA-example2.blif common 3568.91 vpr 7.24 GiB 456 39262 200 400 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 7590012 303 150 545542 542692 1 539559 40318 168 480 80640 -1 ultrascale_ispd 3455.9 MiB 691.18 13027684 7412.1 MiB 2732.16 15.13 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml FPGA-example3.blif common 3109.38 vpr 6.85 GiB 606 30856 200 500 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 7181808 403 200 431203 428403 1 429172 32162 168 480 80640 -1 ultrascale_ispd 2831.4 MiB 536.72 21109759 7013.5 MiB 2436.46 12.67 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml FPGA-example4.blif common 5438.58 vpr 3.00 GiB -1 -1 -1 -1 exited with return code 1 v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 3144676 403 200 850587 844787 1 -1 -1 168 480 -1 -1 -1 3070.7 MiB 5419.65 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -ultrascale_ispd.xml clk_design4.blif common 2858.50 vpr 7.52 GiB 484 39151 150 366 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 7888896 292 150 685438 683387 40 669318 40151 168 480 80640 -1 ultrascale_ispd 3874.8 MiB 371.06 11151371 7704.0 MiB 2335.46 13.46 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml clk_design5.blif common 5113.89 vpr 8.35 GiB 515 51693 420 885 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 8758016 307 150 948147 942073 56 928185 53513 168 480 80640 -1 ultrascale_ispd 5337.3 MiB 574.46 14748050 8552.8 MiB 4362.83 21.01 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_IO num_CLB num_DSP num_BRAM vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + ultrascale_ispd.xml FPGA-example1.blif common 152.30 vpr 5.45 GiB 72 220 2 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 5717652 51 20 3417 3407 1 3313 296 168 480 80640 -1 ultrascale_ispd 62.6 MiB 6.39 29127 70302 16135 47299 6868 5583.6 MiB 1.04 0.01 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 126.54 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml clk_design1.blif common 164.82 vpr 5.48 GiB 109 599 2 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 5741876 57 20 9969 9959 30 9749 712 168 480 80640 -1 ultrascale_ispd 92.1 MiB 16.35 65308 280376 87815 184229 8332 5607.3 MiB 4.96 0.05 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 126.01 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml clk_design2.blif common 510.92 vpr 5.79 GiB 244 5810 10 10 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 6072432 137 60 100115 100025 45 98520 6074 168 480 80640 -1 ultrascale_ispd 518.0 MiB 177.20 1236606 6376499 2732445 3580012 64042 5930.1 MiB 178.65 1.52 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 125.62 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml clk_design3.blif common 2252.28 vpr 6.74 GiB 374 22971 50 96 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 7062992 217 120 400080 399454 35 391886 23491 168 480 80640 -1 ultrascale_ispd 1851.9 MiB 456.68 6560103 43066435 19224310 23715269 126856 6897.5 MiB 1611.89 11.45 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 125.36 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml FPGA-example2.blif common 5275.69 vpr 7.41 GiB 456 39004 200 400 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 7770016 303 150 545542 542692 1 540776 40060 168 480 80640 -1 ultrascale_ispd 2692.2 MiB 1740.97 12437987 87734908 35678297 51734577 322034 7587.9 MiB 3320.54 22.50 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 124.18 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml FPGA-example3.blif common 4852.37 vpr 7.12 GiB 606 30951 200 500 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 7468696 403 200 431203 428403 1 429649 32257 168 480 80640 -1 ultrascale_ispd 2191.2 MiB 1101.87 21367578 74964859 33306309 41084396 574154 7293.6 MiB 3557.08 22.36 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 117.25 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml FPGA-example4.blif common 14784.90 vpr 2.60 GiB -1 -1 -1 -1 exited with return code 1 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2724036 403 200 850587 844787 1 -1 -1 168 480 -1 -1 -1 2660.2 MiB 14757.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + ultrascale_ispd.xml clk_design4.blif common 4467.28 vpr 8.02 GiB 484 39228 150 366 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 8408852 292 150 685438 683387 40 670732 40228 168 480 80640 -1 ultrascale_ispd 3075.9 MiB 761.10 12379630 88225828 36436209 51424919 364700 8211.8 MiB 3483.04 26.72 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 122.67 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml clk_design5.blif common 6947.59 vpr 9.35 GiB 515 51695 420 885 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9801036 307 150 948147 942073 56 927080 53515 168 480 80640 -1 ultrascale_ispd 4230.4 MiB 1092.95 15551057 129073291 53626410 75051110 395771 9571.3 MiB 5605.86 36.60 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 125.37 -1 -1 -1 -1 0 0 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_clique_topology/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_clique_topology/config/golden_results.txt index 120269160ff..25eafae243f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_clique_topology/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_clique_topology/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_clique.blif complex_64_noc_clique.flows common 8722.02 vpr 7.77 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8148772 2 64 249332 210540 1 129121 8146 220 162 35640 -1 EP4SE820 2824.5 MiB 402.18 1227222 7957.8 MiB 792.01 4.2 6.60816 -853447 -6.60816 6.60816 2267.92 0.667678 0.54378 90.027 73.7401 154 1426225 49 0 0 359543000 10088.2 4276.17 411.681 346.038 1425419 20 357462 849967 447693681 43661832 7.19548 7.19548 -1044830 -7.19548 0 0 457197000 12828.2 417.73 79.91 33.4499 29.4545 8462400000 8.0592E-05 + arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_clique.blif complex_64_noc_clique.flows common 6533.14 vpr 8.90 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9329352 2 64 249332 210540 1 128290 8215 220 162 35640 -1 EP4SE820 2512.4 MiB 465.27 1072519 9619279 3999578 5530016 89685 9110.7 MiB 2353.60 5.72 7.23069 -915062 -7.23069 7.23069 544.63 0.719936 0.567047 87.9168 69.331 156 1297420 33 0 0 3.63383e+08 10195.9 2597.61 423.092 343.789 8675854 77817419 -1 1299045 19 310556 747262 143100283 32926158 7.54339 7.54339 -1.11196e+06 -7.54339 0 0 4.60857e+08 12930.9 47.10 71.96 147.54 -1 -1 47.10 34.5748 29.7516 8.4448e+09 4.6256e-05 220 3.416e-05 8190.8 8190.8 254 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_nearest_neighbor_topology/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_nearest_neighbor_topology/config/golden_results.txt index 5f7100ff98f..f714849cf6f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_nearest_neighbor_topology/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_nearest_neighbor_topology/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_nearest_neighbor.blif complex_64_noc_nearest_neighbor.flows common 8560.06 vpr 7.77 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8144244 2 32 245317 207097 1 127846 7926 220 162 35640 -1 EP4SE820 2807.4 MiB 400.67 1238130 7953.4 MiB 769.07 5.03 6.71786 -823307 -6.71786 6.71786 2196.38 0.600359 0.532866 91.0284 76.9373 154 1432666 41 0 0 359543000 10088.2 4213.3 388.018 328.35 1435190 17 353532 839730 444668516 43599148 7.3303 7.3303 -1035530 -7.3303 0 0 457197000 12828.2 437.18 75.13 30.7833 27.281 74000000 6.28E-07 + arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_nearest_neighbor.blif complex_64_noc_nearest_neighbor.flows common 3587.02 vpr 8.89 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9318540 2 32 245317 207097 1 126094 8051 220 162 35640 -1 EP4SE820 2496.9 MiB 472.09 1113445 9686771 3913060 5693676 80035 9100.1 MiB 812.26 4.75 7.23069 -923307 -7.23069 7.23069 553.75 0.657025 0.559971 87.3962 70.1887 154 1342481 40 0 0 3.59543e+08 10088.2 1174.00 309.421 251.887 8640214 77173879 -1 1349276 15 299519 719789 139561804 32203257 7.43069 7.43069 -1.08369e+06 -7.43069 0 0 4.57197e+08 12828.2 58.07 63.01 143.33 -1 -1 58.07 30.7802 26.6489 4.48e+07 3.36e-07 112 4.63221e-23 0 0 0 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_star_topology/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_star_topology/config/golden_results.txt index 71c9b37465d..25bdaa253cc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_star_topology/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_star_topology/config/golden_results.txt @@ -1,6 +1,6 @@ -arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_no_constraints.flows common 9220.99 vpr 7.73 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-pchenry /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8108432 2 32 239118 200960 1 125464 7868 220 162 35640 -1 EP4SE820 2747.6 MiB 451.61 1045127 7918.4 MiB 842.47 4.96 7.29224 -793365 -7.29224 7.29224 2452.84 0.655239 0.571814 107.218 87.7599 154 1195521 42 0 0 359543000 10088.2 4553.02 410.733 344.98 1194844 18 337553 761991 386559130 36912927 7.62869 7.62869 -982536 -7.62869 0 0 457197000 12828.2 372.54 65.96 28.4745 25.3252 96000000 5.43E-07 -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_2_bandwidths.flows common 9063.36 vpr 7.73 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-pchenry /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8108084 2 32 239118 200960 1 125464 7868 220 162 35640 -1 EP4SE820 2747.4 MiB 442.55 1135803 7918.1 MiB 787.79 4.52 6.81554 -811789 -6.81554 6.81554 2376.12 0.650221 0.521368 100.126 80.0299 156 1282477 29 0 0 363383000 10195.9 4524 344.409 286.954 1284251 18 340249 763996 395948352 37975896 7.19262 7.19262 -1017660 -7.19262 0 0 460857000 12930.9 374.68 69.31 29.5326 26.1693 105600000 5.51E-07 -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_6_bandwidths.flows common 8608.75 vpr 7.73 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-pchenry /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8108236 2 32 239118 200960 1 125464 7868 220 162 35640 -1 EP4SE820 2747.7 MiB 426.92 1113432 7918.2 MiB 824.4 4.65 7.74124 -815509 -7.74124 7.74124 2331.45 0.653023 0.521789 103.46 83.6904 156 1266529 23 0 0 363383000 10195.9 4077.6 341.899 286.116 1270380 18 332509 742781 383975630 36523096 8.09967 8.09967 -988125 -8.09967 0 0 460857000 12930.9 407.61 68.56 30.06 26.6489 263600000 5.51E-07 -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_24_latency_constraints.flows common 9546.78 vpr 7.73 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-pchenry /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8108132 2 32 239118 200960 1 125464 7868 220 162 35640 -1 EP4SE820 2747.6 MiB 423.91 1068621 7918.1 MiB 811.89 4.04 7.72717 -803754 -7.72717 7.72717 2426.52 0.710002 0.571345 102.84 83.4583 154 1224191 48 0 0 359543000 10088.2 5008.21 405.36 340.486 1223376 17 334021 746747 382394575 36624473 7.87541 7.87541 -971559 -7.87541 0 0 457197000 12828.2 337.96 63.14 27.0181 24.0375 96000000 5.43E-07 -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_63_latency_constraints.flows common 8773.66 vpr 7.73 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-pchenry /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8108316 2 32 239118 200960 1 125464 7868 220 162 35640 -1 EP4SE820 2747.6 MiB 429.96 1059490 7918.3 MiB 784.75 4.56 7.39441 -807678 -7.39441 7.39441 2390.87 0.606083 0.527822 95.4872 77.8918 156 1207682 34 0 0 363383000 10195.9 4234.99 357.12 300.047 1211566 17 332447 741871 381156942 36122392 7.96259 7.96259 -1011780 -7.96259 0 0 460857000 12930.9 391.24 65.6 28.0846 24.9773 96000000 5.49E-07 \ No newline at end of file + arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_no_constraints.flows common 3640.32 vpr 8.86 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9287812 2 32 239118 200960 1 120794 7872 220 162 35640 -1 EP4SE820 2447.8 MiB 496.98 935318 9244204 3739459 5425044 79701 9070.1 MiB 723.22 4.11 7.25053 -847174 -7.25053 7.25053 541.90 0.584413 0.526328 86.2119 69.3516 154 1122905 42 0 0 3.59543e+08 10088.2 1337.24 333.111 271.579 8640214 77173879 -1 1130130 15 281926 654752 119322887 27628814 7.72979 7.72979 -977352 -7.72979 0 0 4.57197e+08 12828.2 56.43 61.68 120.78 -1 -1 56.43 29.7426 25.7592 9.64e+07 5.45e-07 63 0 47 47 31 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_2_bandwidths.flows common 3490.34 vpr 8.86 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9287760 2 32 239118 200960 1 120794 7872 220 162 35640 -1 EP4SE820 2447.8 MiB 497.41 932527 9244204 3750706 5412944 80554 9070.1 MiB 752.15 4.54 7.25053 -876785 -7.25053 7.25053 541.27 0.617458 0.522798 83.1626 67.1777 156 1118820 36 0 0 3.63383e+08 10195.9 1146.45 293.833 239.47 8675854 77817419 -1 1124333 18 291439 674171 123588076 28491228 7.26463 7.26463 -1.03507e+06 -7.26463 0 0 4.60857e+08 12930.9 52.45 63.92 143.56 -1 -1 52.45 33.3056 28.4835 1.044e+08 5.45e-07 63 0 55 55 31 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_6_bandwidths.flows common 3709.89 vpr 8.86 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9287780 2 32 239118 200960 1 120794 7872 220 162 35640 -1 EP4SE820 2447.8 MiB 488.97 952766 9322478 3766958 5480139 75381 9070.1 MiB 737.91 4.65 7.33661 -953349 -7.33661 7.33661 540.65 0.690479 0.534503 87.207 70.0253 154 1132487 44 0 0 3.59543e+08 10088.2 1383.98 347.748 283.963 8640214 77173879 -1 1138839 14 283064 656883 119841555 27746675 7.6573 7.6573 -1.12531e+06 -7.6573 0 0 4.57197e+08 12828.2 54.64 58.28 142.59 -1 -1 54.64 27.6077 23.9412 2.6e+08 5.43e-07 63 0 202.6 202.6 45 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_24_latency_constraints.flows common 3458.53 vpr 8.86 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9287800 2 32 239118 200960 1 120794 7872 220 162 35640 -1 EP4SE820 2447.9 MiB 451.90 961316 9322478 3764375 5470496 87607 9070.1 MiB 757.45 5.19 7.23069 -855825 -7.23069 7.23069 551.06 0.629897 0.534167 82.4935 66.9304 156 1151895 26 0 0 3.63383e+08 10195.9 1120.45 282.565 230.471 8675854 77817419 -1 1153410 20 293867 681535 125532955 28871891 7.35255 7.35255 -996899 -7.35255 0 0 4.60857e+08 12930.9 53.38 69.31 150.93 -1 -1 53.38 35.4824 30.1217 9.64e+07 5.45e-07 63 1.15805e-23 47 47 31 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_63_latency_constraints.flows common 3472.77 vpr 8.86 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9287976 2 32 239118 200960 1 120794 7872 220 162 35640 -1 EP4SE820 2448.1 MiB 468.20 978163 9087656 3721856 5286813 78987 9070.3 MiB 741.37 4.79 7.27106 -872324 -7.27106 7.27106 559.88 0.624354 0.529616 83.313 65.7244 156 1154394 23 0 0 3.63383e+08 10195.9 1124.03 279.056 226.133 8675854 77817419 -1 1158703 17 293445 680601 124608454 28649322 7.41757 7.41757 -972651 -7.41757 0 0 4.60857e+08 12930.9 53.23 64.72 150.44 -1 -1 53.23 31.9292 27.2724 9.6e+07 5.43e-07 62 2e-09 47.2 47.2 30 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt index 2228fe597c5..e381a9de6fe 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml 670.37 vpr 2.73 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 2864852 42 35 119888 86875 1 51827 3555 129 96 12384 -1 neuron 1830.2 MiB 172.36 594144 2717.0 MiB 138.71 0.74 7.46153 -74648.7 -6.46153 5.54155 51.28 0.274778 0.247975 53.2107 45.4545 -1 765239 22 0 0 2.28642e+08 18462.7 50.37 70.484 61.0725 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml 622.22 vpr 2.73 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 2860400 42 35 119888 86875 1 51282 3422 129 96 12384 -1 neuron 1826.3 MiB 90.78 596408 2713.4 MiB 167.88 0.80 8.25008 -74642.4 -7.25008 5.56231 58.54 0.306592 0.257358 58.1537 49.2936 -1 773864 29 0 0 2.28642e+08 18462.7 55.15 79.2702 68.3071 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml 651.75 vpr 2.73 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 2861964 42 35 119888 86875 1 51283 3425 129 96 12384 -1 neuron 1827.4 MiB 90.76 596968 2714.9 MiB 128.31 0.86 8.38198 -70951.7 -7.38198 5.24439 61.70 0.302423 0.255454 43.3562 36.7091 -1 770785 27 0 0 2.28642e+08 18462.7 56.26 63.006 54.3937 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml 521.09 vpr 2.86 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2999364 42 35 119888 86875 1 51488 3609 129 96 12384 -1 neuron 1754.5 MiB 201.53 588950 3296458 1251917 1696829 347712 2929.1 MiB 120.52 0.99 7.81281 -83697.4 -6.81281 5.17837 0.07 0.394336 0.331354 48.5767 41.2186 -1 -1 -1 -1 -1 774816 15 0 0 2.28639e+08 18462.4 38.71 65.6047 56.4158 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml 448.82 vpr 2.85 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2992528 42 35 119888 86875 1 50882 3437 129 96 12384 -1 neuron 1746.7 MiB 106.69 578743 3192458 1206112 1829273 157073 2922.4 MiB 136.43 1.09 8.30532 -83283.1 -7.30532 5.88288 0.07 0.398109 0.334174 50.9205 42.9915 -1 -1 -1 -1 -1 751914 17 0 0 2.28639e+08 18462.4 38.69 68.6074 58.8539 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml 453.84 vpr 2.86 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2994616 42 35 119888 86875 1 50816 3438 129 96 12384 -1 neuron 1748.6 MiB 106.43 587491 3064004 1147605 1894430 21969 2924.4 MiB 135.58 1.08 7.95276 -79743.8 -6.95276 5.25276 0.07 0.397692 0.334466 49.3461 41.6555 -1 -1 -1 -1 -1 765801 15 0 0 2.28639e+08 18462.4 38.72 65.6267 56.2745 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/golden_results.txt index 7b7954f2f05..42d46a4fbb9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/one_big_partition.xml 835.38 vpr 2.86 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success 16adbfa-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-07-15T00:59:58 gh-actions-runner-vtr-auto-spawned49 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2998168 42 35 119888 86875 1 50931 3418 92 68 12512 -1 neuron3d 1871.5 MiB 125.92 471295 2911586 1070954 1811088 29544 2883.9 MiB 225.67 2.10 7.73071 -71900.2 -6.73071 5.03261 0.22 0.369023 0.308324 43.731 35.9598 -1 672628 24 0 0 2.71622e+08 21708.9 79.02 68.1319 57.7539 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_right_left.xml 820.30 vpr 2.86 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success 16adbfa-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-07-15T00:59:58 gh-actions-runner-vtr-auto-spawned49 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2995656 42 35 119888 86875 1 50982 3427 92 68 12512 -1 neuron3d 1869.5 MiB 127.02 455014 2973417 1101001 1762977 109439 2881.6 MiB 223.03 1.76 7.42684 -70436.4 -6.42684 5.75387 0.23 0.367143 0.304401 44.7203 37.4852 -1 654498 28 0 0 2.71622e+08 21708.9 78.86 71.0006 61.0273 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_up_down.xml 812.45 vpr 2.86 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success 16adbfa-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-07-15T00:59:58 gh-actions-runner-vtr-auto-spawned49 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2995760 42 35 119888 86875 1 50982 3427 92 68 12512 -1 neuron3d 1869.6 MiB 125.77 465634 3050895 1119051 1501125 430719 2881.9 MiB 206.05 1.47 7.58328 -72552.7 -6.58328 5.5951 0.22 0.365879 0.300546 45.7365 37.5853 -1 663695 23 0 0 2.71622e+08 21708.9 79.71 69.6049 58.853 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + 3d_full_OPIN_inter_die_stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/one_big_partition.xml 451.38 vpr 3.00 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3144372 42 35 119888 86875 1 50816 3438 92 68 12512 -1 neuron3d 1748.3 MiB 107.01 466829 2934319 1083146 1824777 26396 3070.7 MiB 121.42 1.02 7.60476 -72127.1 -6.60476 5.56512 0.18 0.379505 0.318093 43.634 37.1671 -1 -1 -1 -1 -1 655727 15 0 0 2.71615e+08 21708.4 39.03 59.6901 51.5812 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + 3d_full_OPIN_inter_die_stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_right_left.xml 475.99 vpr 3.00 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3142992 42 35 119888 86875 1 50882 3437 92 68 12512 -1 neuron3d 1747.0 MiB 106.93 491824 2959115 1097287 1744521 117307 3069.3 MiB 138.63 1.02 7.70882 -73552.4 -6.70882 5.31116 0.19 0.374383 0.32362 46.5434 39.1779 -1 -1 -1 -1 -1 687615 23 0 0 2.71615e+08 21708.4 47.56 68.7335 58.9824 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + 3d_full_OPIN_inter_die_stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_up_down.xml 468.36 vpr 3.00 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3142568 42 35 119888 86875 1 50882 3437 92 68 12512 -1 neuron3d 1746.6 MiB 106.94 498184 3062823 1134124 1468642 460057 3068.9 MiB 137.72 0.97 7.864 -76728.1 -6.864 5.39064 0.16 0.391075 0.327661 48.2954 40.5989 -1 -1 -1 -1 -1 694746 16 0 0 2.71615e+08 21708.4 40.71 65.5361 56.0476 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/config.txt index 5c1b1d03abb..82cad9de83c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/config.txt @@ -14,6 +14,7 @@ includes_dir=benchmarks/verilog/koios # Add circuits to list to sweep circuit_list_add=bwave_like.float.small.v +circuit_list_add=bwave_like.fixed.small.v #Commenting out the following because of https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/2149 #circuit_list_add=bwave_like.fixed.large.v circuit_list_add=dnnweaver.v diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt index a3d58104f0a..76d710cde44 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt @@ -1,4 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bwave_like.float.small.v common 1068.21 vpr 1.88 GiB -1 -1 110.69 930728 6 445.27 -1 -1 199964 -1 -1 1998 114 356 -1 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 1971564 114 86 74339 64124 1 36263 2698 104 104 10816 memory auto 494.2 MiB 45.91 837299 2255578 853320 1293833 108425 1925.4 MiB 91.80 0.70 7.38685 -337841 -7.38685 7.38685 0.10 0.26105 0.226933 34.5308 28.5894 -1 -1 -1 -1 -1 1123690 16 3.44415e+08 1.41306e+08 2.36688e+08 21883.2 48.20 47.1429 39.4245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dnnweaver.v common 2948.82 vpr 5.90 GiB -1 -1 166.20 1233468 9 742.44 -1 -1 565628 -1 -1 5863 1428 1144 -1 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 6186936 1428 2108 167036 128693 1 100353 10831 194 194 37636 memory auto 1034.3 MiB 297.91 1911950 21092463 8889289 10615756 1587418 6041.9 MiB 570.71 3.42 13.7488 -1.49441e+06 -13.7488 13.7488 0.23 0.615123 0.537901 116.246 98.5856 -1 -1 -1 -1 -1 2690563 15 1.20484e+09 3.94177e+08 8.26603e+08 21963.1 61.79 142.653 121.696 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 13533.79 vpr 39.26 GiB -1 -1 386.60 1503068 4 2106.20 -1 -1 561408 -1 -1 4062 21 9017 -1 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 41169996 21 26 134109 127288 1 74703 13231 534 534 285156 memory auto 1344.1 MiB 1835.62 3633223 25196690 12025307 13086177 85206 40205.1 MiB 652.38 3.80 13.6669 -1.87459e+06 -13.6669 13.6669 1.86 0.863375 0.716443 163.799 128.72 -1 -1 -1 -1 -1 4235395 13 9.28675e+09 1.3814e+09 6.26030e+09 21953.9 81.75 196.429 156.233 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bwave_like.float.small.v common 931.50 vpr 1.87 GiB -1 -1 113.03 934296 6 457.86 -1 -1 197616 -1 -1 1998 114 356 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1964192 114 86 74339 64124 1 36263 2698 104 104 10816 memory auto 483.5 MiB 46.28 831504 2218030 841112 1278117 98801 1918.2 MiB 117.16 0.86 7.53856 -335399 -7.53856 7.53856 0.06 0.275108 0.238404 36.4626 30.0575 -1 -1 -1 -1 -1 1118355 17 3.44415e+08 1.41306e+08 2.36688e+08 21883.2 52.63 49.9496 41.6897 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bwave_like.fixed.small.v common 173.06 vpr 1.47 GiB -1 -1 20.75 168220 5 13.72 -1 -1 74548 -1 -1 398 112 170 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1538568 112 86 19811 12990 1 14000 910 98 98 9604 dsp_top auto 190.1 MiB 14.52 315052 481382 144974 259763 76645 1502.5 MiB 25.41 0.21 9.1598 -128842 -9.1598 9.1598 0.05 0.122528 0.108983 14.1795 12.3233 -1 -1 -1 -1 -1 421458 14 3.0121e+08 7.10536e+07 2.10570e+08 21925.2 10.49 19.0155 16.6364 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dnnweaver.v common 2386.29 vpr 5.91 GiB -1 -1 168.23 1230060 9 789.17 -1 -1 566932 -1 -1 6001 1428 1144 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 6193800 1428 2108 167036 128693 1 100353 10969 194 194 37636 memory auto 1037.8 MiB 298.98 1923516 21573286 9150178 10784276 1638832 6048.6 MiB 643.44 3.75 13.1466 -1.44995e+06 -13.1466 13.1466 0.22 0.657801 0.578118 121.534 102.623 -1 -1 -1 -1 -1 2730911 15 1.20484e+09 3.98028e+08 8.26603e+08 21963.1 69.39 148.757 126.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 7876.99 vpr 39.26 GiB -1 -1 375.65 1504352 4 2146.35 -1 -1 561476 -1 -1 4058 21 9017 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 41164592 21 26 134109 127288 1 74696 13227 534 534 285156 memory auto 1322.1 MiB 1808.38 3403261 25186382 12102792 12982264 101326 40199.8 MiB 612.86 4.44 13.7564 -1.83727e+06 -13.7564 13.7564 1.69 0.890769 0.747193 157.229 124.131 -1 -1 -1 -1 -1 4043804 14 9.28675e+09 1.38129e+09 6.26030e+09 21953.9 95.25 192.185 153.77 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_multi_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_multi_arch/config/golden_results.txt index 00fb3c94ebd..49bd0bf75c9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_multi_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_multi_arch/config/golden_results.txt @@ -1,12 +1,12 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bwave_like.fixed.small.v common 578.31 vpr 1.69 GiB -1 -1 15.98 171132 5 18.58 -1 -1 78452 -1 -1 400 112 170 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1777120 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 200.4 MiB 14.61 310763 1735.5 MiB 30.18 0.25 7.69903 -119062 -7.69903 7.69903 7.58 0.0954802 0.083918 11.5352 9.93367 -1 417153 14 4.27832e+08 7.11094e+07 2.96610e+08 22043.0 13.57 16.1651 14.117 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.mem_heavy.xml bwave_like.fixed.small.v common 475.11 vpr 1.61 GiB -1 -1 16.49 170496 5 17.74 -1 -1 78428 -1 -1 400 112 170 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1684784 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 200.6 MiB 14.47 204907 1645.3 MiB 16.66 0.14 7.6727 -98168.4 -7.6727 7.6727 8.22 0.0569728 0.0468006 6.45423 5.48972 -1 301401 17 6.15573e+08 7.11094e+07 2.68432e+08 19948.8 9.12 9.33955 8.09709 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.dsp_heavy.xml bwave_like.fixed.small.v common 363.94 vpr 1.64 GiB -1 -1 16.20 171172 5 17.80 -1 -1 78436 -1 -1 400 112 170 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1723580 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 200.4 MiB 9.51 205843 1683.2 MiB 14.79 0.12 7.38613 -102539 -7.38613 7.38613 9.73 0.0535513 0.0465826 6.23445 5.29446 -1 303118 15 6.02556e+08 7.11094e+07 2.67862e+08 19906.5 8.56 8.94102 7.74417 -1 -1 -1 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2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1753032 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 200.4 MiB 14.63 239009 1711.9 MiB 29.57 0.27 7.4648 -108625 -7.4648 7.4648 9.75 0.0996212 0.0874776 11.4443 9.82126 -1 340028 15 4.88358e+08 7.11094e+07 2.87136e+08 21338.9 13.25 16.1056 14.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.xml bwave_like.fixed.small.v common 601.12 vpr 1.69 GiB -1 -1 16.44 170424 5 19.52 -1 -1 78360 -1 -1 400 112 170 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1777036 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 200.3 MiB 14.52 309684 1735.4 MiB 25.32 0.19 7.69903 -117065 -7.69903 7.69903 7.34 0.0960045 0.0844204 12.1025 10.4924 -1 419702 17 4.23166e+08 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1749896 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 199.3 MiB 14.79 243033 1708.9 MiB 31.22 0.23 7.69903 -108391 -7.69903 7.69903 10.70 0.0929271 0.0812659 11.9434 10.3067 -1 343928 15 4.83692e+08 7.11094e+07 2.87370e+08 21356.3 13.43 16.719 14.5905 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml bwave_like.fixed.small.v common 609.08 vpr 1.69 GiB -1 -1 14.77 170416 5 15.43 -1 -1 78432 -1 -1 400 112 170 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1771252 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 200.1 MiB 14.41 323630 1729.7 MiB 36.26 0.24 7.49113 -120759 -7.49113 7.49113 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k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.denser.xml bwave_like.fixed.small.v common 226.36 vpr 1.94 GiB -1 -1 20.81 170888 5 13.70 -1 -1 74760 -1 -1 399 112 170 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2031452 112 86 19762 12941 1 13999 911 116 116 13456 -1 auto 190.6 MiB 14.84 246355 486451 153890 297699 34862 1983.8 MiB 31.60 0.26 8.8172 -121536 -8.8172 8.8172 0.07 0.120995 0.107853 14.1198 12.2459 -1 -1 -1 -1 -1 343853 13 4.83692e+08 7.10815e+07 2.86254e+08 21273.3 9.57 18.6375 16.2842 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml bwave_like.fixed.small.v common 233.93 vpr 1.98 GiB -1 -1 21.63 171276 5 13.86 -1 -1 74692 -1 -1 399 112 170 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2071140 112 86 19762 12941 1 13999 911 116 116 13456 -1 auto 190.5 MiB 15.50 331826 530591 171032 318763 40796 2022.6 MiB 35.98 0.25 9.7559 -130615 -9.7559 9.7559 0.08 0.121463 0.108223 15.2844 13.3472 -1 -1 -1 -1 -1 423548 14 4.31814e+08 7.10815e+07 2.94694e+08 21900.5 11.26 20.0898 17.6265 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml bwave_like.fixed.small.v common 221.57 vpr 1.85 GiB -1 -1 21.49 171068 5 14.87 -1 -1 74744 -1 -1 399 112 170 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1937008 112 86 19762 12941 1 13999 911 116 116 13456 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20.5511 17.9407 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/golden_results.txt index 4f8ca9d3650..63ab8871773 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay 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k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dnnweaver.v common 3222.53 vpr 5.21 GiB -1 -1 123.94 1231884 9 1003.75 -1 -1 571344 -1 -1 5865 1428 1144 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5466508 1428 2108 167060 128717 1 100354 10833 194 194 37636 memory auto 1290.9 MiB 282.28 1923492 5338.4 MiB 563.19 2.55 11.8807 -1.40186e+06 -11.8807 11.8807 23.26 0.324762 0.263642 82.6055 68.1074 -1 2737596 16 1.20484e+09 3.94233e+08 8.28785e+08 22021.1 77.10 98.7411 82.5923 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 12022.07 vpr 33.80 GiB -1 -1 375.15 1825460 9 2733.36 -1 -1 600716 -1 -1 4834 21 9017 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 35446888 21 26 151757 142444 1 82530 13915 534 534 285156 memory auto 1706.7 MiB 813.36 3582618 34616.1 MiB 391.34 2.29 18.4106 -1.77608e+06 -18.4106 18.4106 224.47 0.400339 0.326802 71.8404 56.0172 -1 4166999 13 9.28675e+09 1.38061e+09 6.26248e+09 21961.6 73.28 89.659 71.729 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources 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112.00 0.85 11.4354 -320958 -11.4354 11.4354 0.07 0.299925 0.236733 37.4509 30.4784 -1 -1 -1 -1 -1 1318559 17 3.44415e+08 1.56007e+08 2.36688e+08 21883.2 37.89 51.1057 42.2451 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dnnweaver.v common 2392.56 vpr 5.90 GiB -1 -1 179.79 1250160 9 741.95 -1 -1 567620 -1 -1 6015 1428 1144 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 6187376 1428 2108 167021 128678 1 100346 10983 194 194 37636 memory auto 1029.7 MiB 306.19 1918633 21488087 9068727 10808393 1610967 6042.4 MiB 631.77 4.23 11.6939 -1.4493e+06 -11.6939 11.6939 0.22 0.631809 0.542666 121.909 102.374 -1 -1 -1 -1 -1 2713088 16 1.20484e+09 3.98419e+08 8.26603e+08 21963.1 84.36 155.32 131.376 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 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b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt index 866c693e208..82805da6c73 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt @@ -1,24 +1,24 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est 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8.0033 6.5916 1240.3 MiB -1 12.36 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 416.55 vpr 1.76 GiB 445 2147 19 52 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1844148 131 314 57881 45152 1 32917 2663 49 36 3528 DSP auto 1362.5 MiB 86.85 289814 1976813 693410 1212996 70407 1709.7 MiB 176.27 1.72 218.423 -74978.2 -217.423 218.423 0.04 0.221041 0.187284 24.7923 21.1712 406108 12.3651 98471 2.99823 104154 327607 243738959 17645361 0 0 7.61281e+07 21578.3 31 1038076 13775176 -1 186.552 186.552 -77902.7 -185.552 0 0 29.48 -1 -1 1723.9 MiB 46.29 39.5945 34.0514 1709.7 MiB -1 40.60 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 72.45 vpr 1.18 GiB 42 752 0 0 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1240412 13 29 26295 20086 1 12536 794 29 21 1218 LAB auto 1061.5 MiB 12.01 63060 221294 37233 166811 17250 1211.3 MiB 13.99 0.21 4.9718 -5064.95 -3.9718 2.73193 0.02 0.0324766 0.0279228 2.25118 1.86401 74221 5.92157 18723 1.49378 27286 38567 29499580 2105965 0 0 2.60089e+07 21353.8 14 354380 4695504 -1 5.052 2.76895 -5085.43 -4.052 0 0 11.26 -1 -1 1211.3 MiB 4.96 3.68252 3.10887 1211.3 MiB -1 8.84 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 440.41 vpr 2.21 GiB 964 976 19 34 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2312848 542 422 37277 26038 1 20609 1993 78 58 9048 io auto 1147.2 MiB 53.94 204070 1443748 530591 842183 70974 2258.6 MiB 132.26 1.73 8.57113 -40060.5 -7.57113 8.57113 0.11 0.114346 0.0970879 14.4519 12.3212 298656 14.4936 68121 3.30588 78221 175730 190639053 28196714 0 0 1.96212e+08 21685.7 51 2627776 35616532 -1 7.6521 7.58988 -39168.5 -6.6521 0 0 69.57 -1 -1 2258.6 MiB 42.38 26.6138 23.1015 2258.6 MiB -1 112.64 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 352.19 vpr 2.44 GiB 1107 719 0 0 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2555856 403 704 15490 16194 1 8578 1826 88 65 11440 io auto 1059.1 MiB 45.27 130173 1273610 483501 754176 35933 2496.0 MiB 30.42 0.29 11.3244 -19683.2 -10.3244 5.27122 0.13 0.0543145 0.0483033 6.97282 5.8855 175112 20.4165 34706 4.04640 26241 103606 64495906 4320076 0 0 2.47902e+08 21669.7 14 3325632 44950250 -1 11.2948 5.14637 -21763.2 -10.2948 0 0 86.50 -1 -1 2496.0 MiB 10.71 9.42628 8.05816 2496.0 MiB -1 152.07 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 119.36 vpr 1.18 GiB 35 731 0 6 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1237480 18 17 16969 16357 1 6316 772 28 21 1176 LAB auto 1056.0 MiB 53.08 73005 241492 57735 179097 4660 1208.5 MiB 12.33 0.20 7.38599 -42310.7 -6.38599 7.38599 0.01 0.0365964 0.0308518 2.95968 2.35615 105687 16.7438 26315 4.16904 22845 117376 78439264 4259070 0 0 2.50919e+07 21336.6 34 342304 4528390 -1 7.17733 7.17733 -42131.3 -6.17733 0 0 10.78 -1 -1 1208.5 MiB 12.71 6.12373 5.01949 1208.5 MiB -1 8.71 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 28.18 vpr 990.12 MiB 35 78 0 8 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1013880 18 17 2291 2142 1 1502 121 13 10 260 LAB auto 951.4 MiB 5.55 9397 11184 1383 8541 1260 990.1 MiB 0.75 0.02 5.30894 -4071.84 -4.30894 4.56748 0.00 0.00643353 0.00532022 0.291101 0.250794 12844 8.56838 3461 2.30887 3750 8551 7007914 560366 0 0 5.17728e+06 19912.6 23 69776 911850 -1 5.37735 4.27489 -3719.74 -4.37735 0 0 2.93 -1 -1 990.1 MiB 1.23 0.669307 0.584049 990.1 MiB -1 0.74 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 244.09 vpr 1.63 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1710388 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1201.8 MiB 72.33 204820 846239 237450 497497 111292 1670.3 MiB 74.90 0.65 7.79489 -43439.9 -6.79489 3.28078 0.10 0.145044 0.126909 16.2828 14.2166 303821 13.2372 69243 3.01686 62436 131482 118528064 33642231 0 0 9.32900e+07 21594.9 16 1265168 16897716 -1 7.83099 3.2527 -39766.3 -6.83099 0 0 28.25 -1 -1 1670.3 MiB 34.12 23.3299 20.6779 1670.3 MiB -1 9.52 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 283.46 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1568820 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.9 MiB 100.65 250483 930441 270744 617644 42053 1427.9 MiB 105.66 1.16 88.0477 -77760.6 -87.0477 88.0477 0.04 0.138248 0.121195 14.6541 12.2965 344948 13.2210 84158 3.22556 78118 205246 82686512 15002058 0 0 5.14202e+07 21425.1 21 702232 9282330 -1 70.8752 70.8752 -96523.7 -69.8752 0 0 15.93 -1 -1 1478.1 MiB 30.26 22.7139 19.3696 1427.9 MiB -1 5.06 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 546.32 vpr 1.95 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2047732 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.8 MiB 197.71 509639 1864099 634981 1176586 52532 1902.3 MiB 202.15 1.98 13.0046 -365555 -12.0046 7.96311 0.08 0.240136 0.202587 26.0846 21.1277 742613 20.9997 172139 4.86777 125805 451636 168920802 27374866 0 0 1.14226e+08 21633.7 20 1553068 20716258 -1 12.6705 7.40682 -365097 -11.6705 0 0 34.41 -1 -1 1902.3 MiB 62.35 40.2332 33.4484 1902.3 MiB -1 12.28 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 585.36 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2009276 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.3 MiB 179.14 542870 2585506 917648 1577326 90532 1765.2 MiB 247.87 2.16 32.1444 -118378 -31.1444 6.23584 0.07 0.26061 0.217278 28.1774 23.7022 787384 20.0781 179841 4.58591 168930 665993 263454811 44272964 0 0 8.35478e+07 21555.2 21 1135740 15114436 -1 31.2519 6.12513 -116198 -30.2519 0 0 26.38 -1 -1 1858.7 MiB 86.58 43.2996 37.0968 1765.2 MiB -1 8.44 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 665.68 vpr 4.50 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4722308 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.9 MiB 143.60 659423 3667920 1455149 2188340 24431 4611.6 MiB 189.33 1.99 5.44974 -115422 -4.44974 3.12297 0.45 0.489655 0.429947 60.4384 53.4484 794955 11.5117 173671 2.51493 139983 173257 122973577 32392189 0 0 5.40274e+08 21813.4 12 7186500 97663758 -1 5.74024 3.40489 -147279 -4.74024 0 0 162.31 -1 -1 4611.6 MiB 45.39 79.3348 71.0438 4611.6 MiB -1 68.45 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 369.28 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1705764 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1276.4 MiB 132.64 278563 1870082 659393 1159933 50756 1577.3 MiB 148.04 1.40 223.632 -132177 -222.632 223.632 0.05 0.153184 0.136333 19.0846 16.0118 379374 13.4069 91772 3.24317 82642 255456 77638931 11638769 0 0 7.07061e+07 21491.2 20 956596 12773992 -1 190.135 190.135 -130112 -189.135 0 0 21.26 -1 -1 1598.5 MiB 30.66 28.1882 24.0263 1577.3 MiB -1 6.97 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 301.91 vpr 1.70 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1787064 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.6 MiB 111.07 267316 798034 216514 557130 24390 1745.2 MiB 83.83 0.97 17.6841 -330571 -16.6841 17.6841 0.08 0.142592 0.123421 13.5697 11.1733 388393 14.4100 90639 3.36285 77554 201450 104702784 19227779 0 0 1.03316e+08 21578.1 23 1396452 18714052 -1 16.8884 16.8884 -322143 -15.8884 0 0 31.36 -1 -1 1745.2 MiB 37.27 22.9987 19.4136 1745.2 MiB -1 9.87 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 129.79 vpr 1.23 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1288736 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.4 MiB 60.90 109402 531288 160105 346309 24874 1229.7 MiB 21.34 0.27 7.65386 -81772.1 -6.65386 7.65386 0.03 0.0542655 0.0415901 4.69487 3.74852 159807 19.3237 38947 4.70943 27112 111164 42415566 5550679 0 0 3.29272e+07 21437.0 15 447460 5950766 -1 7.62538 7.62538 -77759.3 -6.62538 0 0 10.12 -1 -1 1229.7 MiB 15.08 7.2902 6.0554 1229.7 MiB -1 2.80 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 294.21 vpr 1.53 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1605968 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.4 MiB 149.56 245617 1517216 535912 903537 77767 1503.4 MiB 67.74 0.64 12.3707 -91754.7 -11.3707 4.62772 0.04 0.123763 0.0993875 12.5521 10.1851 366533 18.0443 84029 4.13671 58196 217697 65258498 9131006 0 0 6.38257e+07 21490.1 17 866116 11532596 -1 12.1773 4.52077 -87689.2 -11.1773 0 0 19.45 -1 -1 1503.4 MiB 24.63 19.0845 15.7987 1503.4 MiB -1 5.86 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 373.27 vpr 2.31 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2418176 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.2 MiB 113.69 225912 2286656 861887 1362579 62190 2361.5 MiB 99.88 0.94 9.64748 -102230 -8.64748 9.64748 0.14 0.158799 0.128764 21.1153 17.3148 383721 19.4260 88332 4.47183 55000 174045 129359271 32477749 0 0 2.01410e+08 21605.9 18 2701980 36491882 -1 8.6078 8.6078 -177231 -7.6078 0 0 60.49 -1 -1 2361.5 MiB 43.58 29.7071 24.9856 2361.5 MiB -1 22.04 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 287.89 vpr 2.03 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2130704 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.2 MiB 94.47 222406 1491426 518693 900478 72255 2080.8 MiB 60.89 0.53 9.27552 -41609.1 -8.27552 3.17342 0.13 0.131124 0.103107 15.5709 12.4005 371010 17.4897 81992 3.86518 55375 161185 120683489 26150077 0 0 1.70845e+08 21669.8 17 2296616 31015204 -1 9.29871 3.26388 -44629 -8.29871 0 0 50.69 -1 -1 2080.8 MiB 36.84 22.1828 18.2794 2080.8 MiB -1 17.67 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 115.46 vpr 1.42 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1487204 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1035.3 MiB 45.32 98385 149036 34562 99301 15173 1452.3 MiB 10.21 0.11 5.55968 -32411 -4.55968 4.12503 0.05 0.05808 0.0509959 5.30612 4.48561 158711 21.0019 34047 4.50536 20479 45132 33648692 7897451 0 0 7.61223e+07 21576.6 14 1038076 13772104 -1 5.83812 3.95731 -37986.2 -4.83812 0 0 22.99 -1 -1 1452.3 MiB 10.69 8.06663 7.00321 1452.3 MiB -1 7.95 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 308.79 vpr 1.75 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1838356 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1276.3 MiB 90.95 215620 2002487 658856 1202364 141267 1795.3 MiB 112.04 0.92 42.7601 -66808.9 -41.7601 42.7601 0.09 0.161772 0.13883 20.582 17.6888 320121 12.3518 76529 2.95285 71977 215082 87258601 20096356 0 0 1.07584e+08 21568.7 22 1452444 19486512 -1 38.7113 38.7113 -63596.1 -37.7113 0 0 32.70 -1 -1 1795.3 MiB 31.75 30.3911 26.5086 1795.3 MiB -1 11.75 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 194.32 vpr 1.76 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1848104 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1132.2 MiB 67.11 123583 1109975 381766 683735 44474 1804.8 MiB 39.31 0.39 9.15523 -32316.9 -8.15523 9.15523 0.10 0.0795356 0.0699448 8.32413 7.00496 172751 13.5928 41221 3.24345 30616 114657 28576108 5137032 0 0 1.28005e+08 21615.1 15 1733724 23216534 -1 8.8255 8.62305 -32652.3 -7.8255 0 0 39.07 -1 -1 1804.8 MiB 12.08 12.4456 10.6768 1804.8 MiB -1 13.32 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 379.96 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1788552 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1329.9 MiB 152.43 244085 1624747 493620 1093099 38028 1607.0 MiB 139.05 1.16 10.4142 -184930 -9.41415 10.4142 0.05 0.16033 0.126535 18.0534 14.5425 331959 9.29987 79923 2.23905 99630 253842 70436166 10502572 0 0 7.07061e+07 21491.2 17 956596 12773992 -1 9.6278 9.6278 -188775 -8.6278 0 0 21.47 -1 -1 1660.8 MiB 28.25 26.8951 22.1285 1607.0 MiB -1 7.63 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 241.84 vpr 1.65 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1727976 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1289.3 MiB 91.18 155434 1168868 372786 754711 41371 1617.1 MiB 70.29 0.65 5.78947 -22744 -4.78947 5.78947 0.06 0.166564 0.140884 17.2708 14.567 220363 9.18294 52613 2.19248 52262 94777 51757158 12255510 0 0 7.61223e+07 21576.6 17 1038076 13772104 -1 6.13383 6.13383 -28632.3 -5.13383 0 0 23.67 -1 -1 1626.7 MiB 20.25 25.2854 21.7301 1617.1 MiB -1 7.50 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 123.74 vpr 1.21 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1272416 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1066.6 MiB 48.17 156959 264252 69818 174977 19457 1223.8 MiB 19.40 0.22 6.30018 -21278.5 -5.30018 5.08848 0.02 0.0625285 0.0502951 5.37481 4.40679 214370 17.8300 51439 4.27838 52424 159985 69493207 10252744 0 0 3.29272e+07 21437.0 19 447460 5950766 -1 6.55525 5.17583 -23692.3 -5.55525 0 0 10.23 -1 -1 1223.8 MiB 22.52 9.11353 7.72653 1223.8 MiB -1 2.91 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 378.16 vpr 1.77 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1853480 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1362.9 MiB 112.93 299223 1985810 694705 1211569 79536 1665.8 MiB 167.05 1.45 220.781 -74322.2 -219.781 220.781 0.07 0.200934 0.169269 24.1803 20.5128 416847 12.7247 100775 3.07625 94693 283672 85089101 14646952 0 0 7.61223e+07 21576.6 21 1038076 13772104 -1 190.574 190.574 -74796.5 -189.574 0 0 22.90 -1 -1 1729.6 MiB 34.84 36.1614 31.133 1665.8 MiB -1 7.44 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 60.08 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1240452 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1062.9 MiB 15.84 61122 230944 38935 173615 18394 1188.2 MiB 11.81 0.18 4.96737 -5434.49 -3.96737 2.8073 0.02 0.0387336 0.0317178 2.57184 2.12328 72725 5.84747 18233 1.46603 25673 34471 10834392 1619170 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.00956 2.55962 -5093.98 -4.00956 0 0 8.03 -1 -1 1188.2 MiB 4.50 4.29731 3.66237 1188.2 MiB -1 2.18 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 297.39 vpr 2.16 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2263120 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.4 MiB 73.81 204576 1445886 511132 869441 65313 2210.1 MiB 89.30 0.98 8.29539 -39922.7 -7.29539 8.29539 0.17 0.107171 0.0943286 12.3686 10.4512 291171 14.2731 67635 3.31544 59148 140903 91946515 22482953 0 0 1.96207e+08 21685.1 19 2627776 35613460 -1 7.77837 7.50651 -37244.2 -6.77837 0 0 58.79 -1 -1 2210.1 MiB 28.79 18.2832 15.7996 2210.1 MiB -1 21.60 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 209.37 vpr 2.38 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2494924 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.9 MiB 49.01 125640 1144742 417642 695010 32090 2436.4 MiB 27.60 0.29 12.1377 -20404.2 -11.1377 5.98066 0.18 0.0583692 0.0490098 6.35528 5.34844 169403 19.8527 34281 4.01746 23768 95388 22780638 3618006 0 0 2.47896e+08 21669.2 14 3325632 44947178 -1 12.3671 6.09382 -23278.4 -11.3671 0 0 74.30 -1 -1 2436.4 MiB 9.07 9.00673 7.74787 2436.4 MiB -1 27.37 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 116.44 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1231712 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1057.8 MiB 66.58 77598 237654 57043 175228 5383 1183.4 MiB 12.28 0.19 7.75636 -48829.2 -6.75636 7.75636 0.02 0.0387637 0.0330252 3.16043 2.55192 107783 17.1520 26590 4.23138 18971 91032 29347868 3748700 0 0 2.50861e+07 21331.7 15 342304 4525318 -1 7.25059 7.25059 -44231.5 -6.25059 0 0 7.74 -1 -1 1183.4 MiB 10.12 5.32204 4.46908 1183.4 MiB -1 2.14 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 23.94 vpr 993.17 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1017004 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.6 MiB 6.88 10123 9091 942 7112 1037 993.2 MiB 0.58 0.01 5.30858 -4060.6 -4.30858 4.62312 0.00 0.00627854 0.00548745 0.259054 0.223136 13428 9.29273 3606 2.49550 3290 8079 3159547 482733 0 0 5.17151e+06 19890.4 10 69776 908778 -1 5.28356 4.46405 -3916.13 -4.28356 0 0 1.74 -1 -1 993.2 MiB 1.11 0.547712 0.492658 993.2 MiB -1 0.20 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt index c82ecd830c2..46f57bf760a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt @@ -1,24 +1,24 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 262.54 vpr 1.67 GiB 274 985 36 59 0 2 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1751260 22 252 53001 29054 7 24677 1356 54 40 4320 DSP auto 1201.6 MiB 29.07 193351 856584 241304 515166 100114 1710.2 MiB 57.40 0.47 7.85588 -42871.3 -6.85589 3.25066 0.05 0.164012 0.144346 20.1769 17.6827 321085 13.0284 73107 2.96640 77217 159907 244975232 47657761 0 0 9.32956e+07 21596.2 51 1265168 16900788 -1 7.71858 3.05436 -39723.1 -6.71858 0 0 35.16 -1 -1 1710.2 MiB 58.56 36.785 32.606 1710.2 MiB -1 53.64 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 266.43 vpr 1.49 GiB 36 1571 10 10 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1563992 3 33 48977 39238 1 26076 1627 40 30 2400 LAB auto 1224.2 MiB 84.53 219644 900737 262240 597791 40706 1464.3 MiB 59.40 0.56 87.2663 -78342.6 -86.2663 87.2663 0.03 0.136963 0.113622 14.4066 12.1423 358074 13.7340 86107 3.30266 114584 318694 268050281 21927928 0 0 5.14259e+07 21427.5 25 702232 9285402 -1 70.0405 70.0405 -100596 -69.0405 0 0 20.03 -1 -1 1474.7 MiB 45.67 22.9811 19.484 1464.3 MiB -1 26.55 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 502.31 vpr 1.94 GiB 211 2249 3 210 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2037436 38 173 62892 59064 3 35496 2673 60 44 5280 M9K auto 1410.0 MiB 165.24 469808 1875516 643371 1181456 50689 1947.1 MiB 111.84 1.00 12.7266 -347397 -11.7266 7.76695 0.06 0.21795 0.188479 25.7283 20.759 761318 21.4516 174875 4.92744 146514 536546 425254345 33830656 0 0 1.14231e+08 21634.7 42 1553068 20719330 -1 12.751 7.43563 -359178 -11.751 0 0 42.27 -1 -1 1947.1 MiB 79.84 46.0754 37.7929 1947.1 MiB -1 61.86 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 510.28 vpr 1.91 GiB 574 2798 16 0 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2002052 4 570 66175 54803 2 39284 3388 51 38 3876 LAB auto 1448.3 MiB 155.18 480842 2546888 886276 1563516 97096 1812.7 MiB 134.18 1.24 29.1982 -116620 -28.1982 5.72994 0.05 0.279475 0.249568 28.0608 23.8653 835653 21.2748 189102 4.81433 189134 743856 723324517 67486197 0 0 8.35534e+07 21556.6 23 1135740 15117508 -1 29.3026 5.84212 -116980 -28.3026 0 0 30.38 -1 -1 1852.8 MiB 112.28 42.3369 36.2977 1812.7 MiB -1 38.66 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 867.83 vpr 4.60 GiB 40 3678 172 1 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 4821640 19 21 171111 96274 1 73403 3891 129 96 24768 DSP auto 1885.8 MiB 97.55 673610 3766584 1489345 2249664 27575 4708.6 MiB 146.85 1.66 6.29597 -125028 -5.29597 3.97866 0.29 0.540165 0.485534 68.9859 61.9344 848230 11.5563 178165 2.42732 147804 178663 227513169 41591039 0 0 5.40280e+08 21813.6 12 7186500 97666830 -1 6.65084 4.08305 -163510 -5.65084 0 0 181.11 -1 -1 4708.6 MiB 50.62 87.2479 78.818 4708.6 MiB -1 325.55 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 343.21 vpr 1.62 GiB 536 1956 7 4 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1698584 227 309 49176 40422 1 28426 2503 47 35 3290 io auto 1277.4 MiB 116.96 233056 1803125 631727 1120429 50969 1619.5 MiB 88.74 0.85 220.939 -126998 -219.939 220.939 0.04 0.166742 0.142156 19.3794 16.4143 379748 13.3611 92233 3.24513 99103 311914 224583690 13083987 0 0 7.07118e+07 21493.0 21 956596 12777064 -1 187.057 187.057 -123104 -186.057 0 0 27.10 -1 -1 1619.5 MiB 37.22 28.2116 24.0272 1619.5 MiB -1 38.39 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 315.38 vpr 1.74 GiB 36 1347 8 149 2 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1829548 3 33 52402 39411 1 28031 1542 57 42 4788 M9K auto 1243.2 MiB 86.72 244124 776277 216128 536517 23632 1786.7 MiB 52.34 0.52 17.0483 -326259 -16.0483 17.0483 0.07 0.138809 0.121469 14.0009 11.569 405781 14.4803 94699 3.37933 90589 226981 215520672 23742240 0 0 1.03322e+08 21579.3 36 1396452 18717124 -1 16.875 16.875 -325058 -15.875 0 0 36.75 -1 -1 1786.7 MiB 43.28 25.6581 21.481 1786.7 MiB -1 63.41 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 139.86 vpr 1.23 GiB 251 959 1 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1284536 55 196 20131 19956 1 8238 1228 32 24 1536 LAB auto 1088.0 MiB 53.11 91486 559933 175888 358521 25524 1248.2 MiB 15.79 0.19 7.71763 -76349.3 -6.71763 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v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1764996 79 38 66795 54922 1 36434 2280 46 34 3128 LAB auto 1327.7 MiB 94.53 193506 1442280 408990 987732 45558 1622.8 MiB 107.09 0.96 10.4896 -189466 -9.48956 10.4896 0.04 0.181193 0.143388 18.7619 15.1531 299015 8.20771 73882 2.02800 103402 216097 142829772 7784557 0 0 6.72076e+07 21485.8 60 910800 12142484 -1 10.3837 10.3837 -194478 -9.38372 0 0 26.33 -1 -1 1638.8 MiB 42.30 42.291 34.5762 1622.8 MiB -1 40.72 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 266.83 vpr 1.64 GiB 213 1563 26 4 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1720856 139 74 57121 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ucsb_152_tap_fir_stratixiv_arch_timing.blif common 72.91 vpr 1.18 GiB 42 752 0 0 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1240564 13 29 26295 20086 1 12536 794 29 21 1218 LAB auto 1062.3 MiB 12.25 60938 224969 39079 169148 16742 1211.5 MiB 8.86 0.14 4.98143 -5213.57 -3.98143 2.67558 0.02 0.0416776 0.0341297 2.6038 2.15581 76160 6.07627 19086 1.52274 27055 37715 33235953 2126435 0 0 2.60089e+07 21353.8 15 354380 4695504 -1 5.12425 2.73808 -5240.77 -4.12425 0 0 10.15 -1 -1 1211.5 MiB 5.50 4.50745 3.80146 1211.5 MiB -1 13.00 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 419.11 vpr 2.21 GiB 964 976 19 34 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2314204 542 422 37277 26038 1 20609 1993 78 58 9048 io auto 1148.8 MiB 54.92 195960 1431211 527491 836231 67489 2260.0 MiB 75.94 0.81 8.64801 -40234.9 -7.64801 8.64801 0.16 0.123859 0.105031 15.0886 12.8374 307874 14.9410 69309 3.36353 75615 168495 192889124 28407970 0 0 1.96212e+08 21685.7 49 2627776 35616532 -1 7.7876 7.7876 -39277.6 -6.7876 0 0 70.32 -1 -1 2260.0 MiB 47.47 28.8645 24.8552 2260.0 MiB -1 140.28 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 372.90 vpr 2.44 GiB 1107 719 0 0 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2556376 403 704 15490 16194 1 8578 1826 88 65 11440 io auto 1059.8 MiB 48.57 116298 1217830 465874 718697 33259 2496.5 MiB 20.86 0.20 11.5693 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agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1710616 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1201.9 MiB 75.60 184944 854209 237356 546771 70082 1670.5 MiB 72.88 0.69 7.97251 -43075.7 -6.97251 3.30339 0.08 0.146166 0.132698 17.0437 15.0301 301371 13.1305 69191 3.01460 59225 124430 116802792 31972323 0 0 9.32900e+07 21594.9 16 1265168 16897716 -1 8.04852 3.11041 -39249.7 -7.04852 0 0 28.37 -1 -1 1670.5 MiB 33.95 23.995 21.3968 1670.5 MiB -1 9.57 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 270.96 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1570676 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.8 MiB 102.33 228282 920766 279042 595583 46141 1429.0 MiB 88.59 0.94 88.2845 -80659 -87.2845 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11.90 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 567.58 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2010460 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.8 MiB 182.98 484271 2560191 884458 1582491 93242 1765.5 MiB 199.71 1.77 30.1698 -117772 -29.1698 6.32625 0.06 0.250873 0.209174 27.8047 23.3414 819023 20.8849 185777 4.73728 196681 798495 366587115 55913961 0 0 8.35478e+07 21555.2 22 1135740 15114436 -1 29.383 6.18561 -115406 -28.383 0 0 25.30 -1 -1 1859.5 MiB 114.24 42.8002 36.5375 1765.5 MiB -1 8.24 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 659.64 vpr 4.50 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4722024 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.9 MiB 143.54 633199 3760290 1490720 2235840 33730 4611.4 MiB 182.36 1.64 5.44974 -120174 -4.44974 3.48061 0.38 0.500711 0.446581 64.3668 57.2048 792964 11.4829 169052 2.44804 136130 168139 120657048 30423925 0 0 5.40274e+08 21813.4 11 7186500 97663758 -1 5.66375 3.85682 -156124 -4.66375 0 0 164.59 -1 -1 4611.4 MiB 43.21 81.7626 73.4249 4611.4 MiB -1 67.85 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 346.58 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1706888 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1277.2 MiB 130.96 235454 1785192 630171 1108259 46762 1578.0 MiB 123.59 1.24 223.973 -131867 -222.973 223.973 0.06 0.15399 0.137707 18.3847 15.5681 381869 13.4950 92844 3.28105 78342 247729 91337050 11782368 0 0 7.07061e+07 21491.2 19 956596 12773992 -1 184.913 184.913 -126417 -183.913 0 0 21.19 -1 -1 1599.2 MiB 34.88 27.0233 23.1993 1578.0 MiB -1 6.86 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 293.47 vpr 1.70 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1786932 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.4 MiB 111.19 242706 816556 231855 560850 23851 1745.1 MiB 73.99 0.84 17.4268 -331657 -16.4268 17.4268 0.09 0.152091 0.122991 14.1776 11.6814 398717 14.7930 92932 3.44793 77467 205644 117024334 20394306 0 0 1.03316e+08 21578.1 21 1396452 18714052 -1 16.917 16.917 -320368 -15.917 0 0 31.30 -1 -1 1745.1 MiB 38.71 22.7388 19.2113 1745.1 MiB -1 9.99 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 125.97 vpr 1.23 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1288384 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.4 MiB 59.12 92593 557464 169405 360888 27171 1229.7 MiB 20.18 0.28 7.84939 -78165.6 -6.8494 7.84939 0.02 0.0579092 0.0459609 5.05811 4.04769 159733 19.3148 38820 4.69408 24505 101419 42311105 5071555 0 0 3.29272e+07 21437.0 15 447460 5950766 -1 7.81851 7.81851 -71908.7 -6.81851 0 0 10.15 -1 -1 1229.7 MiB 14.27 7.7811 6.44817 1229.7 MiB -1 2.82 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 281.85 vpr 1.53 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1606428 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.5 MiB 149.46 215765 1517216 518543 921536 77137 1503.3 MiB 58.02 0.60 11.9872 -86085.7 -10.9872 4.67996 0.04 0.124604 0.100056 12.4857 10.1291 368614 18.1467 84927 4.18092 54529 192216 59535264 7516911 0 0 6.38257e+07 21490.1 16 866116 11532596 -1 12.0375 4.6146 -82845.8 -11.0375 0 0 19.13 -1 -1 1503.3 MiB 22.39 18.634 15.5175 1503.3 MiB -1 6.30 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 351.01 vpr 2.30 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2416864 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.1 MiB 113.80 191652 2198126 837039 1305954 55133 2360.2 MiB 85.43 0.84 9.95158 -103978 -8.95158 9.95158 0.14 0.157427 0.126297 20.3063 16.4066 380882 19.2822 88412 4.47588 48910 148956 112086751 26603030 0 0 2.01410e+08 21605.9 17 2701980 36491882 -1 9.01423 9.01423 -137565 -8.01423 0 0 60.43 -1 -1 2360.2 MiB 36.97 28.4438 23.7031 2360.2 MiB -1 21.63 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 283.30 vpr 2.03 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2130904 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.7 MiB 91.45 212379 1465966 513016 878305 74645 2081.0 MiB 57.22 0.51 9.02677 -43039.7 -8.02677 3.39009 0.15 0.130982 0.112127 16.0361 12.8184 388469 18.3128 85167 4.01485 54060 155006 126101728 25409947 0 0 1.70845e+08 21669.8 17 2296616 31015204 -1 9.33987 3.47782 -46390.5 -8.33987 0 0 50.94 -1 -1 2081.0 MiB 38.16 22.6708 18.6622 2081.0 MiB -1 18.21 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 116.04 vpr 1.42 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1487240 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1035.3 MiB 44.85 91640 143465 34428 97411 11626 1452.4 MiB 9.56 0.11 5.55968 -32627.3 -4.55968 4.03585 0.05 0.0580242 0.0511336 5.23009 4.40266 162858 21.5506 34640 4.58383 20772 47469 39442838 8696473 0 0 7.61223e+07 21576.6 17 1038076 13772104 -1 5.83812 3.81128 -37803.8 -4.83812 0 0 22.95 -1 -1 1452.4 MiB 12.55 8.31954 7.18554 1452.4 MiB -1 7.74 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 307.88 vpr 1.76 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1842824 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1280.9 MiB 92.83 193340 1985246 651294 1194899 139053 1799.6 MiB 104.91 0.90 42.817 -66341.8 -41.817 42.817 0.08 0.174464 0.149553 21.4513 18.52 318648 12.2949 76857 2.96551 72321 215661 101797360 20420450 0 0 1.07584e+08 21568.7 26 1452444 19486512 -1 38.0834 38.0834 -61419.7 -37.0834 0 0 32.89 -1 -1 1799.6 MiB 36.69 32.4273 28.3397 1799.6 MiB -1 11.41 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 191.13 vpr 1.76 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1848728 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1133.0 MiB 66.11 114187 1121763 389127 687964 44672 1805.4 MiB 36.03 0.35 9.10047 -33210.9 -8.10047 9.10047 0.10 0.0829476 0.0672165 8.6028 7.09879 180406 14.1951 42811 3.36856 29439 106878 36794843 4980523 0 0 1.28005e+08 21615.1 13 1733724 23216534 -1 8.86459 8.53756 -33502.4 -7.86459 0 0 39.09 -1 -1 1805.4 MiB 13.39 12.4192 10.5234 1805.4 MiB -1 13.65 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 365.42 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1789484 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1330.0 MiB 148.46 220034 1575085 472174 1056131 46780 1607.4 MiB 128.88 1.19 10.366 -185682 -9.366 10.366 0.05 0.166017 0.132704 17.7166 14.3298 340742 9.54593 82334 2.30660 86785 211666 72987830 8810844 0 0 7.07061e+07 21491.2 18 956596 12773992 -1 10.3348 10.3348 -186105 -9.33478 0 0 21.58 -1 -1 1659.8 MiB 29.02 26.9646 22.2301 1607.4 MiB -1 7.36 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 236.24 vpr 1.65 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1729420 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1290.4 MiB 89.13 143448 1223918 387573 791889 44456 1618.2 MiB 69.23 0.62 6.15923 -22935.6 -5.15923 6.15923 0.06 0.160924 0.134554 18.8103 16.0328 226941 9.45706 54238 2.26020 51698 93187 54990565 12041480 0 0 7.61223e+07 21576.6 16 1038076 13772104 -1 6.33927 6.33927 -28490.3 -5.33927 0 0 23.07 -1 -1 1627.8 MiB 19.85 26.0631 22.6082 1618.2 MiB -1 7.69 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 121.12 vpr 1.21 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1272616 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1066.8 MiB 48.71 145866 267719 70212 178005 19502 1223.6 MiB 17.33 0.21 6.32104 -21443.6 -5.32104 5.1317 0.02 0.0642369 0.0519236 5.54676 4.5538 218475 18.1714 52270 4.34750 52154 158487 72130661 9975959 0 0 3.29272e+07 21437.0 17 447460 5950766 -1 6.2459 4.96992 -24617.9 -5.2459 0 0 10.12 -1 -1 1223.6 MiB 22.65 9.07986 7.70719 1223.6 MiB -1 2.99 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 360.73 vpr 1.77 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1854860 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1363.2 MiB 112.86 262777 1930208 669923 1189043 71242 1666.5 MiB 145.10 1.38 223.441 -74881.2 -222.441 223.441 0.05 0.211297 0.180427 24.3293 20.7548 427696 13.0558 103553 3.16106 90894 273726 106018598 14702817 0 0 7.61223e+07 21576.6 21 1038076 13772104 -1 190.035 190.035 -73399.2 -189.035 0 0 23.08 -1 -1 1732.8 MiB 39.37 36.0725 31.1574 1666.5 MiB -1 7.54 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 60.38 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1239040 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1061.9 MiB 15.77 60924 230944 39979 176254 14711 1186.8 MiB 11.56 0.18 5.04063 -5430.36 -4.04063 2.87222 0.02 0.0364742 0.0318647 2.60212 2.17525 74753 6.01053 18783 1.51025 25814 34889 12202224 1634430 0 0 2.60031e+07 21349.0 17 354380 4692432 -1 5.24483 2.65773 -5067.06 -4.24483 0 0 8.10 -1 -1 1186.8 MiB 4.94 4.43218 3.80588 1186.8 MiB -1 2.32 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 296.54 vpr 2.16 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2262908 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.3 MiB 72.90 213411 1459636 524477 868204 66955 2209.9 MiB 84.09 0.87 8.12716 -41041.3 -7.12716 8.12716 0.14 0.11422 0.095868 12.9019 10.9024 322533 15.8104 73202 3.58833 58164 135585 115660664 26279570 0 0 1.96207e+08 21685.1 19 2627776 35613460 -1 7.60563 7.60563 -38875.6 -6.60563 0 0 58.66 -1 -1 2209.9 MiB 34.96 18.71 16.1454 2209.9 MiB -1 20.83 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 209.98 vpr 2.38 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2494688 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.9 MiB 49.31 117261 1200767 458957 708379 33431 2436.2 MiB 25.42 0.26 11.7854 -20675.2 -10.7854 5.73126 0.18 0.0562212 0.0465333 6.50332 5.46368 182292 21.3632 36297 4.25372 22684 88666 28845037 3461649 0 0 2.47896e+08 21669.2 14 3325632 44947178 -1 11.9953 5.82624 -23038.5 -10.9953 0 0 74.42 -1 -1 2436.2 MiB 10.82 9.12659 7.84634 2436.2 MiB -1 27.36 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 115.88 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1230928 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1057.5 MiB 66.57 64446 230476 54244 170900 5332 1183.1 MiB 10.85 0.17 7.74825 -47724 -6.74825 7.74825 0.02 0.0458274 0.0351245 3.17308 2.53234 105547 16.7961 26043 4.14433 16938 75501 27527280 3256994 0 0 2.50861e+07 21331.7 14 342304 4525318 -1 7.60467 7.60467 -45348.9 -6.60467 0 0 7.98 -1 -1 1183.1 MiB 9.47 5.27867 4.40168 1183.1 MiB -1 2.23 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 23.87 vpr 993.03 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1016864 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.3 MiB 6.57 8979 9091 989 7145 957 993.0 MiB 0.57 0.01 5.30858 -4141.38 -4.30858 4.67064 0.00 0.00654281 0.00572201 0.265779 0.231578 13865 9.59516 3702 2.56194 3278 7822 3354574 494732 0 0 5.17151e+06 19890.4 12 69776 908778 -1 5.46939 4.48287 -3903.7 -4.46939 0 0 1.75 -1 -1 993.0 MiB 1.23 0.606378 0.546433 993.0 MiB -1 0.21 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt index 1ab11fa8780..1a9fa971299 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt @@ -1,24 +1,24 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 520.61 vpr 1.72 GiB 274 987 36 59 0 2 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1803496 22 252 53001 29054 7 24609 1358 54 40 4320 DSP auto 1204.1 MiB 39.90 216521 888364 256649 520395 111320 1761.2 MiB 87.85 0.71 7.67021 -36041.3 -6.67021 3.10875 0.08 0.126381 0.112882 16.7124 14.1733 342154 13.9217 83084 3.38056 76883 151222 326194146 106749769 0 0 8.89497e+07 20590.2 56 1365594 16211305 -1 9.14969 3.16574 -43836.7 -8.14969 0 0 32.91 -1 -1 1761.2 MiB 138.38 31.7678 27.6452 1761.2 MiB -1 194.50 -3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 417.34 vpr 1.50 GiB 36 1580 10 10 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1572468 3 33 48977 39238 1 26329 1636 40 30 2400 LAB auto 1223.7 MiB 106.33 249698 955600 281109 638361 36130 1458.1 MiB 103.12 1.05 82.0766 -56743.3 -81.0766 82.0766 0.04 0.11202 0.0959451 12.7886 10.3669 398272 15.1290 101546 3.85740 95740 256181 200343144 42868641 0 0 4.91306e+07 20471.1 44 758110 8921656 -1 71.392 71.392 -126837 -70.392 0 0 18.37 -1 -1 1481.7 MiB 63.81 24.8111 20.6403 1458.1 MiB -1 98.71 -3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 888.33 vpr 1.97 GiB 211 2261 3 210 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2062840 38 173 62892 59064 3 35566 2685 60 44 5280 M9K auto 1410.9 MiB 217.72 478758 1942701 680573 1218059 44069 2014.5 MiB 176.36 1.51 11.7665 -297024 -10.7665 7.51698 0.09 0.202619 0.16947 25.2532 19.6817 772503 21.7245 195521 5.49850 143008 511949 475300762 109106753 0 0 1.08858e+08 20617.0 56 1675578 19868374 -1 14.2505 7.86617 -385289 -13.2505 0 0 41.27 -1 -1 2014.5 MiB 166.71 50.776 41.2384 2014.5 MiB -1 244.64 -3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 1114.78 vpr 1.92 GiB 574 2772 16 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2014640 4 570 66175 54803 2 39317 3362 51 38 3876 LAB auto 1449.1 MiB 196.88 499724 2671912 950738 1625402 95772 1861.6 MiB 224.11 1.77 27.5032 -105534 -26.5032 5.41511 0.06 0.199192 0.172892 26.8354 21.1953 803998 20.4517 200370 5.09692 177923 701320 1281304364 359064468 0 0 7.97022e+07 20563.0 20 1225854 14507865 -1 30.2412 6.45869 -119451 -29.2412 0 0 29.13 -1 -1 1864.8 MiB 453.83 38.7043 31.5496 1861.6 MiB -1 172.45 -3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 2049.90 vpr 4.79 GiB 40 3678 172 1 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5023844 19 21 171111 96274 1 73063 3891 129 96 24768 DSP auto 1882.9 MiB 124.90 684201 3735993 1501648 2208285 26060 4906.1 MiB 148.94 1.66 6.00962 -98830.8 -5.00962 3.45872 0.32 0.391796 0.341532 49.21 43.1537 833239 11.4049 184319 2.52284 146193 177078 507711122 213695314 0 0 5.14406e+08 20769.0 13 7758968 93673935 -1 5.92189 4.22813 -137430 -4.92189 0 0 182.05 -1 -1 4906.1 MiB 207.32 64.5253 57.3404 4906.1 MiB -1 1108.11 -3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 514.96 vpr 1.64 GiB 536 1953 7 4 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1718304 227 309 49176 40422 1 28164 2500 47 35 3290 io auto 1277.5 MiB 147.28 266723 1918980 725646 1136427 56907 1646.8 MiB 121.43 1.12 194.338 -109756 -193.338 194.338 0.06 0.111355 0.0960834 15.0867 12.0805 409856 14.5545 103143 3.66275 87257 277955 172520127 35585678 0 0 6.75216e+07 20523.3 21 1033138 12274942 -1 196.949 196.949 -148256 -195.949 0 0 25.10 -1 -1 1646.8 MiB 48.56 22.5017 18.5228 1646.8 MiB -1 139.81 -3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 637.08 vpr 1.80 GiB 36 1342 8 149 2 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1888764 3 33 52402 39411 1 28062 1537 57 42 4788 M9K auto 1243.0 MiB 103.75 273842 834941 243386 565684 25871 1844.5 MiB 86.68 0.82 15.7112 -289050 -14.7112 15.7112 0.08 0.119058 0.102615 13.4566 10.7905 420305 14.9820 105404 3.75718 100360 260743 546160418 129480870 0 0 9.85096e+07 20574.3 31 1507654 17957159 -1 18.1236 18.1236 -347845 -17.1236 0 0 36.57 -1 -1 1844.5 MiB 161.91 23.1123 19.1485 1844.5 MiB -1 216.44 -3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 204.89 vpr 1.28 GiB 251 954 1 17 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1341080 55 196 20131 19956 1 8282 1223 32 24 1536 LAB auto 1088.4 MiB 66.85 105468 576479 179756 366623 30100 1309.6 MiB 23.08 0.27 7.56709 -65136 -6.56709 7.56709 0.02 0.0500856 0.0384976 4.85645 3.72985 179329 21.6607 46312 5.59391 29504 122672 72003745 13823732 0 0 3.14199e+07 20455.7 25 483264 5705245 -1 8.81703 8.81703 -85275.7 -7.81703 0 0 12.37 -1 -1 1309.6 MiB 22.42 8.31826 6.6994 1309.6 MiB -1 59.44 -3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 589.98 vpr 1.54 GiB 255 2123 1 28 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1610260 84 171 36458 36247 3 20352 2407 45 33 2970 LAB auto 1231.2 MiB 174.99 241376 1598683 558192 952375 88116 1542.8 MiB 73.08 0.66 10.1083 -70133.7 -9.1083 4.12508 0.04 0.115981 0.0878 12.7489 9.8058 400083 19.6717 97548 4.79634 61046 216519 401222983 118385406 0 0 6.09438e+07 20519.8 15 935204 11078823 -1 12.436 4.7257 -87531.4 -11.436 0 0 22.73 -1 -1 1542.8 MiB 163.43 18.4518 14.7362 1542.8 MiB -1 127.22 -3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 876.17 vpr 2.42 GiB 69 2107 10 295 16 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2536200 36 33 57796 49182 1 20334 2497 79 59 9322 M144K auto 1353.5 MiB 112.44 207195 2136055 812529 1275642 47884 2476.8 MiB 85.13 0.73 8.88006 -82826.8 -7.88006 8.88006 0.14 0.117618 0.0988504 16.8798 13.4801 387054 19.0395 94434 4.64529 67787 213274 284083043 79148811 0 0 1.92002e+08 20596.6 76 2917968 35039980 -1 10.009 10.009 -164810 -9.00897 0 0 68.45 -1 -1 2476.8 MiB 114.92 38.9885 32.6103 2476.8 MiB -1 446.62 -3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 736.20 vpr 2.14 GiB 478 1231 1 300 4 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2247640 202 276 35125 30509 3 21728 2014 73 54 7884 M9K auto 1187.1 MiB 97.40 215797 1654704 587326 990918 76460 2195.0 MiB 74.14 0.51 9.19228 -26875.5 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-3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 569.26 vpr 1.82 GiB 693 1777 25 16 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1904396 35 658 51416 37539 1 27463 2511 58 43 4988 io auto 1278.1 MiB 99.65 212181 2083831 717693 1222429 143709 1859.8 MiB 106.25 0.84 40.5037 -60224.2 -39.5037 40.5037 0.09 0.128488 0.113425 18.2416 14.9291 330278 12.7260 81833 3.15312 94649 304701 197817782 44987282 0 0 1.02587e+08 20566.7 26 1568252 18700371 -1 39.261 39.261 -66616.1 -38.2609 0 0 38.02 -1 -1 1859.8 MiB 59.17 27.948 23.4447 1859.8 MiB -1 230.32 -3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 470.62 vpr 1.83 GiB 753 1108 5 32 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1915540 13 740 25173 25306 1 12781 1898 63 47 5922 io auto 1130.4 MiB 71.87 124962 1223482 428622 736669 58191 1870.6 MiB 40.32 0.32 8.57799 -25886.9 -7.57799 8.57799 0.09 0.0666816 0.0576129 8.22186 6.71409 184141 14.4153 45279 3.54462 32905 123041 47256325 10410499 0 0 1.22008e+08 20602.6 29 1871156 22275272 -1 8.85683 8.47371 -35058.8 -7.85683 0 0 44.24 -1 -1 1870.6 MiB 19.02 13.7447 11.5422 1870.6 MiB -1 265.30 -3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 665.26 vpr 1.70 GiB 117 2173 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1780732 79 38 66795 54922 1 36442 2290 46 34 3128 LAB auto 1332.5 MiB 118.39 223170 1465826 438868 989440 37518 1631.4 MiB 116.51 1.00 10.0034 -164441 -9.00345 10.0034 0.05 0.140615 0.10816 15.3551 12.0225 328872 9.02528 85242 2.33931 156751 378493 614757965 143147538 0 0 6.41689e+07 20514.4 66 983570 11662836 -1 10.4048 10.4048 -200702 -9.40483 0 0 23.96 -1 -1 1655.2 MiB 233.33 36.8481 30.0419 1631.4 MiB -1 139.49 -3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 407.83 vpr 1.66 GiB 213 1565 26 4 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1737656 139 74 57121 41054 1 24175 1808 49 36 3528 DSP auto 1290.3 MiB 89.57 147265 1212908 383568 790816 38524 1687.9 MiB 69.62 0.60 5.18803 -15564.9 -4.18803 4.69751 0.06 0.132355 0.115165 16.3281 13.6684 218052 9.02122 54686 2.26246 53635 97635 86433611 24558382 0 0 7.26079e+07 20580.5 22 1120110 13214470 -1 5.61308 5.61308 -32689.4 -4.61308 0 0 26.73 -1 -1 1687.9 MiB 33.82 24.3867 20.8618 1687.9 MiB -1 158.29 -3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 207.60 vpr 1.26 GiB 54 659 0 40 0 1 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1323644 2 52 16673 16662 2 12066 754 32 24 1536 M9K auto 1066.2 MiB 53.44 154124 275154 74667 179945 20542 1292.6 MiB 19.41 0.22 5.39679 -16155.6 -4.39679 4.49872 0.02 0.0602811 0.0465091 5.32106 4.24475 238163 19.7449 63975 5.30385 56894 169908 152382564 31381158 0 0 3.14199e+07 20455.7 17 483264 5705245 -1 6.73871 5.3677 -26489.1 -5.73871 0 0 11.94 -1 -1 1292.6 MiB 44.16 8.78802 7.31639 1292.6 MiB -1 58.83 -3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 633.14 vpr 1.77 GiB 445 2151 19 52 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1857528 131 314 57881 45152 1 32955 2667 49 36 3528 DSP auto 1363.0 MiB 124.71 294607 2054724 754821 1217361 82542 1716.5 MiB 175.07 1.59 191.584 -64615.7 -190.584 191.584 0.05 0.18745 0.150512 23.6039 19.2336 445934 13.5621 110207 3.35169 137218 430293 351839984 68634033 0 0 7.26079e+07 20580.5 40 1120110 13214470 -1 199.253 199.253 -80683.6 -198.253 0 0 29.02 -1 -1 1733.2 MiB 107.66 40.3599 33.6861 1716.5 MiB -1 162.17 -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 100.48 vpr 1.19 GiB 42 752 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1244324 13 29 26295 20086 1 12509 794 29 21 1218 LAB auto 1062.8 MiB 15.76 62891 261719 56222 191052 14445 1215.2 MiB 11.16 0.13 4.85572 -4225.92 -3.85572 2.52096 0.02 0.0230785 0.0193446 2.10304 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wb_conmax_stratixiv_arch_timing.blif common 841.75 vpr 2.52 GiB 1107 729 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2644060 403 704 15490 16194 1 8574 1836 88 65 11440 io auto 1060.4 MiB 54.40 122558 1384110 547152 796309 40649 2582.1 MiB 30.97 0.29 10.4549 -16402 -9.45487 4.73896 0.17 0.0533879 0.0433669 6.8282 5.61818 173895 20.2840 38605 4.50309 24038 94279 126191912 44771966 0 0 2.36204e+08 20647.2 14 3590540 43137666 -1 12.0851 5.88321 -24833.6 -11.0851 0 0 83.16 -1 -1 2582.1 MiB 63.98 9.36579 7.90327 2582.1 MiB -1 559.86 -3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 160.76 vpr 1.18 GiB 35 730 0 6 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1240184 18 17 16969 16357 1 6277 771 28 21 1176 LAB auto 1057.6 MiB 67.85 69205 265821 72177 187282 6362 1211.1 MiB 11.88 0.16 7.31748 -40693.1 -6.31748 7.31748 0.02 0.0306438 0.0257343 2.96374 2.35042 113779 18.1379 30059 4.79181 21341 106772 39406769 7295674 0 0 2.39639e+07 20377.5 31 369794 4343188 -1 8.79554 8.79554 -51620.5 -7.79554 0 0 8.95 -1 -1 1211.1 MiB 12.09 5.72142 4.74732 1211.1 MiB -1 40.12 -3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 29.75 vpr 994.02 MiB 35 73 0 8 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1017876 18 17 2291 2142 1 1500 116 13 10 260 LAB auto 953.8 MiB 7.30 9755 9704 1420 7286 998 994.0 MiB 0.48 0.01 5.28239 -3533.58 -4.28239 4.24487 0.00 0.00357156 0.00285794 0.176718 0.144844 15640 10.4476 4912 3.28123 4115 9431 4210567 862713 0 0 4.97530e+06 19135.8 17 75766 878809 -1 5.24221 4.56041 -4449.95 -4.24221 0 0 2.13 -1 -1 994.0 MiB 1.20 0.467896 0.409078 994.0 MiB -1 2.84 +3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 1172.59 vpr 1.65 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1734316 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1201.6 MiB 73.64 214653 894059 251005 559264 83790 1693.7 MiB 79.53 0.65 7.70472 -37826.5 -6.70472 3.17657 0.08 0.149615 0.135881 18.4856 16.2276 346942 15.1160 80330 3.49991 71500 157095 1535090931 789230213 0 0 8.89497e+07 20590.2 18 1365594 16211305 -1 7.67229 3.07739 -42724.4 -6.67229 0 0 29.57 -1 -1 1693.7 MiB 940.94 26.0477 23.0694 1693.7 MiB -1 23.96 +3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 329.77 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1576816 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.5 MiB 99.18 252169 969141 295922 624406 48813 1444.1 MiB 90.56 0.89 82.4495 -56586.4 -81.4495 82.4495 0.03 0.133831 0.117153 15.353 12.8639 420916 16.1326 105895 4.05868 118615 321172 291100673 58952034 0 0 4.91306e+07 20471.1 26 758110 8921656 -1 72.0146 72.0146 -132785 -71.0146 0 0 16.42 -1 -1 1484.9 MiB 85.29 24.7756 21.0909 1444.1 MiB -1 12.23 +3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 641.04 vpr 1.96 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2050760 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.2 MiB 203.13 510171 1939307 680820 1206280 52207 1927.9 MiB 173.07 1.61 11.2616 -300285 -10.2616 7.35058 0.09 0.251364 0.202792 27.6684 22.4451 799864 22.6187 198121 5.60249 142256 518619 474643655 110260894 0 0 1.08858e+08 20617.0 17 1675578 19868374 -1 14.7898 8.01616 -421363 -13.7898 0 0 36.05 -1 -1 1927.9 MiB 161.55 40.1269 33.3458 1927.9 MiB -1 29.72 +3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 991.70 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2018452 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.4 MiB 179.88 509692 2712081 968624 1648149 95308 1790.4 MiB 217.33 1.88 26.7071 -106583 -25.7071 4.92953 0.06 0.265658 0.222085 30.753 25.8577 822920 20.9843 201896 5.14831 185617 735052 1296414490 366645497 0 0 7.97022e+07 20563.0 20 1225854 14507865 -1 30.288 6.57341 -120054 -29.288 0 0 26.21 -1 -1 1867.6 MiB 509.93 45.4244 38.8563 1790.4 MiB -1 20.62 +3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 1067.25 vpr 4.62 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4842056 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.7 MiB 144.01 645363 3760290 1509060 2226895 24335 4728.6 MiB 196.62 2.32 6.72849 -100513 -5.72849 2.73028 0.43 0.510597 0.454713 66.2712 58.6699 801246 11.6028 176582 2.55708 136809 169565 554939068 253332108 0 0 5.14406e+08 20769.0 10 7758968 93673935 -1 6.25252 4.02616 -144264 -5.25252 0 0 173.36 -1 -1 4728.6 MiB 346.30 83.0597 74.3223 4728.6 MiB -1 149.18 +3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 397.31 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1713464 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1276.8 MiB 127.62 267729 1921016 704204 1175385 41427 1599.4 MiB 134.02 1.32 194.73 -111174 -193.73 194.73 0.05 0.16753 0.141447 20.6062 17.3755 409980 14.4885 103027 3.64092 98368 318292 234678586 45271456 0 0 6.75216e+07 20523.3 20 1033138 12274942 -1 196.841 196.841 -137573 -195.841 0 0 22.11 -1 -1 1604.7 MiB 66.77 29.7244 25.3562 1599.4 MiB -1 17.48 +3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 413.22 vpr 1.73 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1814172 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.2 MiB 110.44 272716 825817 229328 570617 25872 1771.7 MiB 82.01 0.93 15.8733 -287969 -14.8733 15.8733 0.07 0.156169 0.134842 15.1402 12.4708 427395 15.8570 107058 3.97203 83662 216621 348016314 94876303 0 0 9.85096e+07 20574.3 20 1507654 17957159 -1 18.2989 18.2989 -351435 -17.2989 0 0 32.91 -1 -1 1771.7 MiB 133.99 23.8154 20.073 1771.7 MiB -1 25.41 +3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 136.48 vpr 1.24 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1295860 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.4 MiB 59.84 106751 583640 180621 371614 31405 1246.6 MiB 21.31 0.25 7.0989 -65567.9 -6.0989 7.0989 0.02 0.0579001 0.0443717 5.41731 4.32489 176951 21.3967 45151 5.45961 29990 122737 58119884 11106318 0 0 3.14199e+07 20455.7 16 483264 5705245 -1 8.58513 8.58513 -82449.9 -7.58513 0 0 10.90 -1 -1 1246.6 MiB 18.17 8.28886 6.85025 1246.6 MiB -1 6.97 +3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 490.96 vpr 1.54 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1612568 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.2 MiB 149.78 250819 1565561 553633 923794 88134 1522.9 MiB 59.74 0.57 10.3141 -74446.1 -9.31412 4.16669 0.05 0.122453 0.0982616 12.7928 10.36 417504 20.5535 99339 4.89042 64295 236643 559755019 162046743 0 0 6.09438e+07 20519.8 16 935204 11078823 -1 14.1009 4.7173 -100461 -13.1009 0 0 19.72 -1 -1 1522.9 MiB 220.56 19.1309 15.8639 1522.9 MiB -1 14.15 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2167360 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.5 MiB 91.51 224050 1542346 541947 927260 73139 2116.6 MiB 59.94 0.50 9.32745 -27918.9 -8.32745 3.0761 0.12 0.131152 0.102135 16.6741 13.2554 393714 18.5600 91424 4.30981 54848 152461 310286597 88766009 0 0 1.62738e+08 20641.5 15 2479452 29744051 -1 9.42064 3.77724 -50913.7 -8.42064 0 0 53.44 -1 -1 2116.6 MiB 114.73 22.9686 18.8221 2116.6 MiB -1 44.42 +3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 148.74 vpr 1.44 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1511644 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1036.2 MiB 45.72 83064 154607 38752 101305 14550 1476.2 MiB 10.09 0.11 5.67702 -19756.2 -4.67702 3.74463 0.05 0.0597777 0.0527936 5.58527 4.74534 152254 20.1474 35176 4.65476 19877 43738 72454580 21374549 0 0 7.26079e+07 20580.5 14 1120110 13214470 -1 5.84516 4.10311 -39834.2 -4.84516 0 0 24.01 -1 -1 1476.2 MiB 28.04 8.35092 7.24512 1476.2 MiB -1 22.29 +3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 346.43 vpr 1.78 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1868112 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1276.9 MiB 93.13 219255 2157656 730879 1273796 152981 1824.3 MiB 109.67 0.89 40.2879 -60979.5 -39.2879 40.2879 0.08 0.170403 0.154539 23.7513 20.5481 349212 13.4742 85186 3.28688 77275 233364 143562765 36702160 0 0 1.02587e+08 20566.7 21 1568252 18700371 -1 38.5591 38.5591 -67167.5 -37.5591 0 0 34.79 -1 -1 1824.3 MiB 50.23 33.5444 29.3581 1824.3 MiB -1 28.83 +3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 218.13 vpr 1.79 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1877276 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1133.0 MiB 66.22 123520 1204279 427315 726664 50300 1833.3 MiB 39.61 0.36 9.02181 -27438.3 -8.02181 9.02181 0.09 0.0790484 0.0694683 9.30633 7.78111 180566 14.2077 43756 3.44291 31272 116811 38575938 8660251 0 0 1.22008e+08 20602.6 13 1871156 22275272 -1 10.1297 8.7558 -37422.6 -9.12975 0 0 40.27 -1 -1 1833.3 MiB 15.13 13.1986 11.2705 1833.3 MiB -1 33.84 +3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 395.83 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1795672 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1330.1 MiB 147.79 247450 1624747 516348 1068765 39634 1627.6 MiB 129.80 1.19 9.58554 -169343 -8.58554 9.58554 0.05 0.181629 0.143035 18.586 15.0291 368099 10.3123 95475 2.67474 86257 200403 122474916 27418708 0 0 6.75216e+07 20523.3 17 1033138 12274942 -1 10.0787 10.0787 -216795 -9.07872 0 0 22.36 -1 -1 1667.7 MiB 46.86 27.3022 22.6133 1627.6 MiB -1 18.57 +3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 251.39 vpr 1.66 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1735768 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1289.7 MiB 85.10 145328 1179878 360849 786061 32968 1640.5 MiB 69.36 0.64 5.18803 -16009.3 -4.18803 4.71553 0.06 0.152706 0.134393 18.4109 15.5777 214240 8.92778 54586 2.27470 53253 96856 65663526 17180534 0 0 7.26079e+07 20580.5 19 1120110 13214470 -1 5.62731 5.62731 -28524.3 -4.62731 0 0 23.91 -1 -1 1640.5 MiB 26.16 26.596 22.9352 1640.5 MiB -1 19.18 +3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 136.47 vpr 1.23 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1290392 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1065.8 MiB 47.70 152283 278120 75325 183121 19674 1260.1 MiB 18.99 0.21 5.35599 -16505.5 -4.35599 4.51559 0.02 0.0653283 0.0529731 5.96357 4.87661 239529 19.9226 64112 5.33245 57238 170600 111195486 21263938 0 0 3.14199e+07 20455.7 20 483264 5705245 -1 6.61831 5.4172 -26290.3 -5.61831 0 0 10.52 -1 -1 1260.1 MiB 32.71 9.93276 8.38713 1260.1 MiB -1 7.29 +3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 437.55 vpr 1.78 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1867528 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1362.4 MiB 112.91 292652 2022878 726716 1212218 83944 1695.6 MiB 151.83 1.37 193.523 -65237.6 -192.523 193.523 0.06 0.213557 0.18157 25.9931 22.1715 453070 13.8304 113197 3.45545 117143 365096 327048949 70274290 0 0 7.26079e+07 20580.5 21 1120110 13214470 -1 201.969 201.969 -83602 -200.969 0 0 23.94 -1 -1 1743.7 MiB 97.67 37.8603 32.6631 1695.6 MiB -1 18.81 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 67.95 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1235488 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1063.1 MiB 15.63 63489 256928 52638 188949 15341 1198.2 MiB 13.00 0.16 4.8555 -4307.79 -3.8555 2.47976 0.02 0.0366363 0.0322351 3.02693 2.52688 81757 6.57369 23123 1.85921 26483 36571 27721140 5378093 0 0 2.48366e+07 20391.3 14 382818 4502703 -1 4.99885 2.78104 -5808.83 -3.99885 0 0 8.34 -1 -1 1198.2 MiB 8.51 4.71161 4.0282 1198.2 MiB -1 5.30 +3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 447.54 vpr 2.19 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2300520 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.3 MiB 74.85 225689 1597136 573868 950177 73091 2246.6 MiB 97.02 0.89 7.40155 -34081.7 -6.40155 7.40155 0.16 0.121776 0.101863 14.3979 12.1212 339854 16.6595 81624 4.00118 64892 154040 296022532 107475224 0 0 1.86852e+08 20651.1 17 2837414 34147767 -1 8.54909 8.54909 -42257.7 -7.54909 0 0 62.88 -1 -1 2246.6 MiB 134.16 19.8788 17.0808 2246.6 MiB -1 53.46 +3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 304.70 vpr 2.43 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2550580 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.6 MiB 49.77 123671 1380047 554552 786292 39203 2490.8 MiB 31.02 0.26 10.5993 -16629.2 -9.59931 4.97242 0.18 0.0546677 0.0486849 7.77113 6.51315 175220 20.5344 38433 4.50404 23623 93265 107849323 36421682 0 0 2.36204e+08 20647.2 15 3590540 43137666 -1 12.8766 5.81047 -24731 -11.8766 0 0 79.59 -1 -1 2490.8 MiB 52.92 10.6013 9.06122 2490.8 MiB -1 68.45 +3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 117.22 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1225656 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1057.5 MiB 63.70 72669 252010 65056 180799 6155 1192.1 MiB 11.10 0.16 7.46032 -42922.1 -6.46033 7.46032 0.02 0.0386153 0.0330756 3.3215 2.67044 118105 18.7946 31588 5.02673 19732 92762 36148054 6649139 0 0 2.39639e+07 20377.5 15 369794 4343188 -1 7.99918 7.99918 -51485.8 -6.99918 0 0 8.05 -1 -1 1192.1 MiB 11.26 5.50251 4.59387 1192.1 MiB -1 5.21 +3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 24.11 vpr 992.77 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1016600 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.8 MiB 6.88 9528 9390 1205 7155 1030 992.8 MiB 0.57 0.01 5.30062 -3506.54 -4.30062 4.33661 0.00 0.00633989 0.00552195 0.266113 0.231235 16243 11.2408 5134 3.55294 3509 8574 4051674 833095 0 0 4.97530e+06 19135.8 10 75766 878809 -1 5.2881 4.86207 -4539.08 -4.2881 0 0 1.87 -1 -1 992.8 MiB 1.27 0.557486 0.502971 992.8 MiB -1 0.41 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt index 0ab160efdd9..08e1f46286a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt @@ -1,24 +1,24 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 582.16 vpr 1.72 GiB 274 987 36 59 0 2 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1803524 22 252 53001 29054 7 24609 1358 54 40 4320 DSP auto 1204.1 MiB 42.52 195330 858296 247287 495125 115884 1761.3 MiB 84.93 0.67 7.80788 -36648 -6.80788 3.12522 0.08 0.124521 0.103496 15.0607 12.6449 371346 15.1095 103610 4.21573 80566 160946 461930857 165593977 0 0 8.89497e+07 20590.2 51 1365594 16211305 -1 8.74368 3.32525 -48171.4 -7.74368 0 0 32.76 -1 -1 1761.3 MiB 195.95 29.1002 25.2738 1761.3 MiB -1 198.81 -3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 422.96 vpr 1.50 GiB 36 1580 10 10 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1573748 3 33 48977 39238 1 26329 1636 40 30 2400 LAB auto 1223.6 MiB 106.71 248841 888148 253476 594820 39852 1458.1 MiB 105.66 1.10 81.4784 -53835.8 -80.4784 81.4784 0.04 0.109711 0.0935788 11.8789 9.57793 411181 15.6194 116574 4.42826 92798 244546 220907410 47907010 0 0 4.91306e+07 20471.1 24 758110 8921656 -1 72.6227 72.6227 -121766 -71.6227 0 0 18.53 -1 -1 1483.2 MiB 63.69 19.757 16.3958 1458.1 MiB -1 101.16 -3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 930.36 vpr 1.97 GiB 211 2261 3 210 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2062768 38 173 62892 59064 3 35566 2685 60 44 5280 M9K auto 1410.8 MiB 217.85 527418 1961355 698273 1211201 51881 2014.4 MiB 213.62 1.87 11.5444 -297926 -10.5444 7.43875 0.09 0.221174 0.167818 25.4392 19.6023 799544 22.4850 206009 5.79344 140764 494647 491987729 117958703 0 0 1.08858e+08 20617.0 42 1675578 19868374 -1 14.3661 7.89936 -391318 -13.3661 0 0 40.95 -1 -1 2014.4 MiB 168.06 45.7164 36.8171 2014.4 MiB -1 248.05 -3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 1128.29 vpr 1.92 GiB 574 2772 16 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2014856 4 570 66175 54803 2 39317 3362 51 38 3876 LAB auto 1449.1 MiB 197.04 539555 2646737 936545 1618816 91376 1861.6 MiB 263.14 2.12 27.205 -106349 -26.205 5.36288 0.06 0.222737 0.17179 26.4811 20.5787 812545 20.6691 203996 5.18915 179839 704950 1238086925 342084780 0 0 7.97022e+07 20563.0 22 1225854 14507865 -1 30.7692 6.31053 -122652 -29.7692 0 0 28.44 -1 -1 1865.0 MiB 437.18 39.1867 31.6218 1861.6 MiB -1 162.84 -3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 2111.69 vpr 4.79 GiB 40 3678 172 1 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5023412 19 21 171111 96274 1 73063 3891 129 96 24768 DSP auto 1882.4 MiB 124.10 683749 3705402 1474779 2203663 26960 4905.7 MiB 149.84 1.99 4.90769 -102144 -3.90769 2.66229 0.32 0.333623 0.299825 45.1483 39.2326 943364 12.9122 246384 3.37235 150431 182369 732288583 298849219 0 0 5.14406e+08 20769.0 11 7758968 93673935 -1 5.35185 3.87959 -147181 -4.35185 0 0 181.00 -1 -1 4905.7 MiB 286.71 59.0156 52.1235 4905.7 MiB -1 1092.75 -3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 564.65 vpr 1.64 GiB 536 1953 7 4 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1718716 227 309 49176 40422 1 28164 2500 47 35 3290 io auto 1277.5 MiB 145.88 261565 1868100 672501 1151002 44597 1646.7 MiB 140.05 1.34 195.231 -110925 -194.231 195.231 0.06 0.12554 0.0992061 14.6571 11.6553 411249 14.6040 113307 4.02369 103543 325921 298122992 61172575 0 0 6.75216e+07 20523.3 20 1033138 12274942 -1 199.286 199.286 -155282 -198.286 0 0 25.18 -1 -1 1646.7 MiB 79.16 22.1044 18.1436 1646.7 MiB -1 142.30 -3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 695.10 vpr 1.80 GiB 36 1342 8 149 2 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1888536 3 33 52402 39411 1 28062 1537 57 42 4788 M9K auto 1243.2 MiB 103.70 273438 790611 224541 541418 24652 1844.3 MiB 92.12 0.90 15.273 -287167 -14.273 15.273 0.08 0.114449 0.0977109 12.57 10.0601 460533 16.4159 127882 4.55842 95816 245821 618088152 166535403 0 0 9.85096e+07 20574.3 47 1507654 17957159 -1 17.7356 17.7356 -355280 -16.7356 0 0 36.56 -1 -1 1844.3 MiB 212.41 25.6811 21.3256 1844.3 MiB -1 217.95 -3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 201.82 vpr 1.28 GiB 251 954 1 17 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1341092 55 196 20131 19956 1 8282 1223 32 24 1536 LAB auto 1088.4 MiB 65.74 108189 537257 161186 351024 25047 1309.7 MiB 24.49 0.28 7.63348 -66340.6 -6.63348 7.63348 0.02 0.0446494 0.0376164 4.56397 3.53477 173240 20.9252 49009 5.91968 28613 116746 69432612 13114190 0 0 3.14199e+07 20455.7 16 483264 5705245 -1 8.73313 8.73313 -81669.2 -7.73313 0 0 11.99 -1 -1 1309.7 MiB 20.35 7.28084 5.9123 1309.7 MiB -1 59.04 -3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 574.17 vpr 1.54 GiB 255 2123 1 28 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1610160 84 171 36458 36247 3 20352 2407 45 33 2970 LAB auto 1230.9 MiB 176.26 230253 1534187 537107 918935 78145 1542.6 MiB 80.31 0.73 10.3286 -73217.5 -9.32864 4.15911 0.04 0.109206 0.091457 12.2567 9.37699 386386 18.9982 105938 5.20887 59158 205458 343044614 94954046 0 0 6.09438e+07 20519.8 15 935204 11078823 -1 11.9822 4.48722 -86968.8 -10.9822 0 0 22.88 -1 -1 1542.6 MiB 135.83 18.0758 14.384 1542.6 MiB -1 130.74 -3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 895.60 vpr 2.42 GiB 69 2107 10 295 16 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2536012 36 33 57796 49182 1 20334 2497 79 59 9322 M144K auto 1353.6 MiB 114.46 211332 2152988 849915 1253916 49157 2476.6 MiB 97.43 0.82 9.56163 -84792.3 -8.56163 9.56163 0.14 0.126043 0.0984021 17.6076 13.911 393751 19.3689 103359 5.08431 69197 220461 288511556 81052098 0 0 1.92002e+08 20596.6 45 2917968 35039980 -1 9.93304 9.93304 -167341 -8.93304 0 0 69.52 -1 -1 2476.6 MiB 110.65 31.348 25.8958 2476.6 MiB -1 452.70 -3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 733.35 vpr 2.14 GiB 478 1231 1 300 4 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2246596 202 276 35125 30509 3 21728 2014 73 54 7884 M9K auto 1186.1 MiB 98.22 226155 1680130 581037 1021138 77955 2193.9 MiB 81.38 0.58 9.04734 -32184.9 -8.04734 3.17119 0.12 0.12349 0.0925998 16.6945 12.9764 376551 17.3350 90231 4.15390 60533 167938 291951174 74695878 0 0 1.62738e+08 20641.5 20 2479452 29744051 -1 9.34711 3.98413 -48329.1 -8.34711 0 0 58.73 -1 -1 2193.9 MiB 97.89 23.8118 19.2322 2193.9 MiB -1 359.25 -3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 303.46 vpr 1.46 GiB 5 330 31 105 0 2 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1536028 3 2 14862 10304 26 7620 473 49 36 3528 DSP auto 1035.1 MiB 49.34 86372 144149 35218 93920 15011 1500.0 MiB 9.09 0.10 5.35635 -20850.9 -4.35635 3.73741 0.06 0.0454616 0.0396929 4.33095 3.6643 150545 19.8242 37129 4.88925 20992 47091 119548029 36655524 0 0 7.26079e+07 20580.5 20 1120110 13214470 -1 5.84657 3.77061 -40487 -4.84657 0 0 26.93 -1 -1 1500.0 MiB 45.25 7.43604 6.47906 1500.0 MiB -1 151.75 -3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 585.18 vpr 1.82 GiB 693 1777 25 16 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1904188 35 658 51416 37539 1 27463 2511 58 43 4988 io auto 1277.9 MiB 98.57 206877 1998531 678358 1182926 137247 1859.6 MiB 115.66 0.95 40.5043 -60922.5 -39.5043 40.5043 0.09 0.122326 0.107203 16.9254 13.7612 342117 13.1822 91004 3.50649 77091 229186 193704618 53247878 0 0 1.02587e+08 20566.7 33 1568252 18700371 -1 39.0491 39.0491 -68044.3 -38.0491 0 0 37.83 -1 -1 1859.6 MiB 69.44 28.0298 23.4918 1859.6 MiB -1 227.84 -3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 484.44 vpr 1.83 GiB 753 1108 5 32 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1915040 13 740 25173 25306 1 12781 1898 63 47 5922 io auto 1130.4 MiB 72.36 122373 1223482 442946 725936 54600 1870.2 MiB 43.47 0.37 8.58151 -26013.6 -7.58151 8.58151 0.09 0.066611 0.0577751 8.09623 6.55743 181674 14.2222 45570 3.56740 33303 126130 60438024 14474337 0 0 1.22008e+08 20602.6 22 1871156 22275272 -1 9.64216 8.37594 -35791.4 -8.64216 0 0 44.59 -1 -1 1870.2 MiB 22.83 12.7955 10.6758 1870.2 MiB -1 273.45 -3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 623.34 vpr 1.70 GiB 117 2173 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1781144 79 38 66795 54922 1 36442 2290 46 34 3128 LAB auto 1333.0 MiB 118.38 223063 1496002 445875 1009592 40535 1631.3 MiB 130.59 1.12 10.298 -164963 -9.29802 10.298 0.05 0.147236 0.114284 15.8825 12.406 335721 9.21323 96583 2.65054 148171 339963 462293429 109838402 0 0 6.41689e+07 20514.4 61 983570 11662836 -1 11.0507 11.0507 -199170 -10.0507 0 0 24.26 -1 -1 1656.6 MiB 176.26 36.1483 29.4745 1631.3 MiB -1 139.48 -3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 434.07 vpr 1.65 GiB 213 1565 26 4 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1733820 139 74 57121 41054 1 24175 1808 49 36 3528 DSP auto 1291.2 MiB 90.16 142328 1212908 383501 795665 33742 1665.9 MiB 78.06 0.70 5.18054 -15486.2 -4.18054 4.55771 0.06 0.122967 0.105902 15.1532 12.538 255792 10.5826 76054 3.14650 55778 101786 129669669 38217209 0 0 7.26079e+07 20580.5 17 1120110 13214470 -1 5.89185 5.89185 -31809.1 -4.89185 0 0 27.24 -1 -1 1665.9 MiB 49.95 22.1936 18.8747 1665.9 MiB -1 159.11 -3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 203.83 vpr 1.26 GiB 54 659 0 40 0 1 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1324232 2 52 16673 16662 2 12066 754 32 24 1536 M9K auto 1066.4 MiB 53.90 155566 261434 69464 171581 20389 1293.2 MiB 20.41 0.23 5.61272 -16670 -4.61272 4.76097 0.02 0.058552 0.0457308 5.08816 4.03513 232798 19.3001 64048 5.30990 55982 170058 137168149 27075994 0 0 3.14199e+07 20455.7 17 483264 5705245 -1 6.79545 5.55783 -24965 -5.79545 0 0 12.04 -1 -1 1293.2 MiB 38.89 8.66706 7.15564 1293.2 MiB -1 59.00 -3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 605.13 vpr 1.77 GiB 445 2151 19 52 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1857416 131 314 57881 45152 1 32955 2667 49 36 3528 DSP auto 1362.9 MiB 121.73 289015 2017750 707990 1212909 96851 1716.4 MiB 185.57 1.75 193.424 -63656.5 -192.424 193.424 0.05 0.181205 0.144741 21.1471 16.9918 454441 13.8208 122774 3.73389 118181 360293 262822432 52549899 0 0 7.26079e+07 20580.5 21 1120110 13214470 -1 194.404 194.404 -85184.9 -193.404 0 0 27.34 -1 -1 1734.0 MiB 79.07 32.7617 27.124 1716.4 MiB -1 156.20 -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 99.58 vpr 1.19 GiB 42 752 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1244496 13 29 26295 20086 1 12509 794 29 21 1218 LAB auto 1062.7 MiB 15.63 61236 243344 47038 181714 14592 1215.3 MiB 10.40 0.15 5.00346 -4267.82 -4.00346 2.38962 0.02 0.0231436 0.0188542 1.7862 1.47025 95550 7.63972 32943 2.63397 28913 41935 41958000 8761950 0 0 2.48366e+07 20391.3 15 382818 4502703 -1 5.19398 2.70192 -5808.39 -4.19397 0 0 9.42 -1 -1 1215.3 MiB 11.07 3.16143 2.70178 1215.3 MiB -1 33.35 -3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 909.95 vpr 2.27 GiB 964 977 19 34 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2381096 542 422 37277 26038 1 20599 1994 78 58 9048 io auto 1149.6 MiB 67.08 196066 1482304 530853 872654 78797 2325.3 MiB 124.70 1.43 7.36978 -33273.5 -6.36978 7.36978 0.13 0.0925632 0.0749752 12.0148 9.72001 324180 15.7399 87235 4.23553 91508 211619 398061242 137241372 0 0 1.86852e+08 20651.1 51 2837414 34147767 -1 8.24329 7.76567 -42592.4 -7.24329 0 0 66.15 -1 -1 2325.3 MiB 174.89 22.8404 19.2662 2325.3 MiB -1 437.08 -3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 828.65 vpr 2.52 GiB 1107 729 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2643872 403 704 15490 16194 1 8574 1836 88 65 11440 io auto 1060.4 MiB 54.12 128760 1372872 549171 784185 39516 2581.9 MiB 33.58 0.32 10.7454 -16424.4 -9.74539 5.1543 0.17 0.0471481 0.041409 6.67367 5.49523 170198 19.8528 38778 4.52327 24095 94572 111221252 37508416 0 0 2.36204e+08 20647.2 15 3590540 43137666 -1 12.3144 5.56074 -24951.7 -11.3144 0 0 82.34 -1 -1 2581.9 MiB 53.56 9.31536 7.88036 2581.9 MiB -1 555.23 -3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 160.17 vpr 1.18 GiB 35 730 0 6 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1239888 18 17 16969 16357 1 6277 771 28 21 1176 LAB auto 1057.4 MiB 68.96 72908 258753 67776 184461 6516 1210.8 MiB 13.14 0.19 7.51407 -40222.8 -6.51407 7.51407 0.02 0.031379 0.0262939 2.92773 2.28009 115032 18.3376 32494 5.17998 21478 112529 39563291 7329073 0 0 2.39639e+07 20377.5 45 369794 4343188 -1 8.81565 8.81565 -49666.3 -7.81565 0 0 9.04 -1 -1 1210.8 MiB 13.32 6.56727 5.39667 1210.8 MiB -1 35.56 -3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 29.27 vpr 993.75 MiB 35 73 0 8 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1017596 18 17 2291 2142 1 1500 116 13 10 260 LAB auto 953.5 MiB 7.20 9940 8576 1032 6562 982 993.7 MiB 0.50 0.01 5.31743 -3552.51 -4.31743 4.26751 0.00 0.00438277 0.00337059 0.190292 0.160703 16521 11.0361 5707 3.81229 4108 9384 4537270 913138 0 0 4.97530e+06 19135.8 34 75766 878809 -1 5.39567 4.83189 -4585.23 -4.39567 0 0 2.12 -1 -1 993.7 MiB 1.43 0.596507 0.52271 993.7 MiB -1 2.56 +3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 536.55 vpr 1.66 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1736116 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1203.7 MiB 75.33 195509 902029 259905 557804 84320 1695.4 MiB 84.98 0.74 7.68567 -37648.9 -6.68567 3.28584 0.07 0.153024 0.133083 18.1163 15.7769 347393 15.1356 91110 3.96959 68562 144013 571183324 243523602 0 0 8.89497e+07 20590.2 16 1365594 16211305 -1 7.79531 3.22903 -48240.7 -6.79531 0 0 29.52 -1 -1 1695.4 MiB 297.68 25.2358 22.2605 1695.4 MiB -1 24.01 +3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 315.33 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1577588 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.4 MiB 101.58 259626 940116 279572 621693 38851 1444.2 MiB 104.57 1.20 82.1047 -56021.6 -81.1047 82.1047 0.03 0.137922 0.120416 14.543 12.1914 423885 16.2464 113939 4.36698 96228 253395 185059095 38347475 0 0 4.91306e+07 20471.1 24 758110 8921656 -1 72.5235 72.5235 -115556 -71.5235 0 0 16.27 -1 -1 1486.1 MiB 54.76 23.4199 19.9723 1444.2 MiB -1 12.10 +3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 679.10 vpr 1.96 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2051156 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.4 MiB 202.36 543821 1995713 704501 1236982 54230 1927.9 MiB 222.49 2.01 11.2639 -298285 -10.2639 7.34492 0.09 0.259679 0.207609 28.5947 23.0535 806716 22.8124 200624 5.67327 143147 517766 456418331 103863687 0 0 1.08858e+08 20617.0 18 1675578 19868374 -1 13.9133 7.76735 -393376 -12.9133 0 0 36.17 -1 -1 1927.9 MiB 150.24 41.7265 34.527 1927.9 MiB -1 29.72 +3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 1027.30 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2017832 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.1 MiB 179.29 547789 2661451 958041 1608713 94697 1789.9 MiB 260.36 2.34 27.0929 -106609 -26.0929 5.35183 0.06 0.27456 0.228129 29.5628 24.7422 829210 21.1447 207429 5.28940 184705 723383 1302091086 364260887 0 0 7.97022e+07 20563.0 18 1225854 14507865 -1 30.5677 6.54028 -121409 -29.5677 0 0 25.79 -1 -1 1868.9 MiB 503.91 43.0657 36.7123 1789.9 MiB -1 20.41 +3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 925.95 vpr 4.62 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4842080 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.6 MiB 147.82 619747 3698710 1495912 2184534 18264 4728.6 MiB 198.02 2.37 6.78648 -99082.3 -5.78648 3.44108 0.45 0.48725 0.430185 61.9462 54.5962 814845 11.7998 205031 2.96905 140099 173436 458459419 150453276 0 0 5.14406e+08 20769.0 14 7758968 93673935 -1 6.45787 3.53717 -145075 -5.45787 0 0 172.18 -1 -1 4728.6 MiB 193.32 83.1106 74.2663 4728.6 MiB -1 156.75 +3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 409.69 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1712060 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1276.6 MiB 131.22 276554 1921016 711963 1138812 70241 1598.4 MiB 145.73 1.42 195.512 -113504 -194.512 195.512 0.05 0.160338 0.134313 19.3452 16.1804 416656 14.7244 107078 3.78408 104021 334271 218912879 40948386 0 0 6.75216e+07 20523.3 20 1033138 12274942 -1 198.006 198.006 -143215 -197.006 0 0 22.05 -1 -1 1607.4 MiB 63.92 28.3971 24.123 1598.4 MiB -1 16.81 +3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 443.45 vpr 1.73 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1814380 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.5 MiB 110.53 271211 807295 220659 561442 25194 1771.9 MiB 87.02 0.90 15.8645 -293903 -14.8645 15.8645 0.07 0.137468 0.119486 13.9778 11.464 446897 16.5806 122453 4.54320 84683 217412 421161484 116638965 0 0 9.85096e+07 20574.3 19 1507654 17957159 -1 17.551 17.551 -341289 -16.551 0 0 33.12 -1 -1 1771.9 MiB 157.72 22.3148 18.7943 1771.9 MiB -1 26.51 +3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 141.26 vpr 1.24 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1296500 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.2 MiB 59.31 113956 557464 166863 359124 31477 1246.8 MiB 24.59 0.29 7.08326 -66257.5 -6.08326 7.08326 0.02 0.055314 0.0441799 5.26138 4.20946 182605 22.0804 50112 6.05949 29285 119606 66293828 12593582 0 0 3.14199e+07 20455.7 15 483264 5705245 -1 8.63522 8.63522 -90099.9 -7.63522 0 0 10.47 -1 -1 1246.8 MiB 20.00 8.06464 6.66092 1246.8 MiB -1 7.35 +3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 368.03 vpr 1.54 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1613076 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.2 MiB 152.28 248422 1517216 526978 905843 84395 1523.2 MiB 71.70 0.64 10.4991 -73576.7 -9.49906 4.26563 0.04 0.123293 0.0990031 12.7883 10.3856 402144 19.7974 109429 5.38714 60309 208858 232045575 52278765 0 0 6.09438e+07 20519.8 18 935204 11078823 -1 12.8865 4.78217 -92799.1 -11.8865 0 0 20.13 -1 -1 1523.2 MiB 81.81 19.2634 16.033 1523.2 MiB -1 15.82 +3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 464.20 vpr 2.35 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2461196 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.2 MiB 116.23 224613 2251244 886249 1326045 38950 2403.5 MiB 95.91 0.83 9.49151 -92147.5 -8.49151 9.49151 0.14 0.154631 0.123533 20.7936 16.7804 397126 20.1046 99400 5.03215 58343 180947 261415498 79896454 0 0 1.92002e+08 20596.6 16 2917968 35039980 -1 8.83504 8.83504 -160829 -7.83504 0 0 63.50 -1 -1 2403.5 MiB 101.27 28.5358 23.7007 2403.5 MiB -1 55.56 +3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 411.57 vpr 2.07 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2167564 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.7 MiB 93.64 225707 1580536 560957 948186 71393 2116.8 MiB 74.70 0.59 9.27529 -27528.6 -8.27529 3.13114 0.14 0.130328 0.10251 17.2693 13.6101 391848 18.4721 94302 4.44548 55624 156547 339484601 88142541 0 0 1.62738e+08 20641.5 16 2479452 29744051 -1 9.56018 3.68158 -50102.5 -8.56018 0 0 53.61 -1 -1 2116.8 MiB 117.38 23.7611 19.3642 2116.8 MiB -1 45.57 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1871392 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1280.5 MiB 91.15 211809 2071451 692754 1236953 141744 1827.5 MiB 125.31 1.09 40.9771 -61336.3 -39.9771 40.9771 0.07 0.171234 0.145898 21.8018 18.6515 342831 13.2280 87296 3.36829 76962 231011 136781567 33406286 0 0 1.02587e+08 20566.7 22 1568252 18700371 -1 39.0683 39.0683 -66985.6 -38.0683 0 0 34.25 -1 -1 1827.5 MiB 47.65 31.738 27.5672 1827.5 MiB -1 27.89 +3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 229.59 vpr 1.79 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1876484 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1132.6 MiB 66.93 129881 1180703 418671 705083 56949 1832.5 MiB 43.61 0.38 9.05339 -27832.3 -8.05339 9.05339 0.11 0.0813991 0.0719295 9.16919 7.64919 190989 15.0279 45936 3.61445 31437 116923 44250090 9507104 0 0 1.22008e+08 20602.6 13 1871156 22275272 -1 9.68529 8.62738 -38151.5 -8.68529 0 0 40.96 -1 -1 1832.5 MiB 16.73 13.1394 11.2088 1832.5 MiB -1 34.19 +3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 497.04 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1795972 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1330.1 MiB 155.39 246824 1707517 542100 1124665 40752 1627.5 MiB 155.77 1.28 9.48565 -168709 -8.48565 9.48565 0.05 0.168989 0.135904 19.3486 15.5394 380234 10.6523 107944 3.02407 107615 274456 330281609 74151890 0 0 6.75216e+07 20523.3 18 1033138 12274942 -1 10.455 10.455 -199956 -9.45504 0 0 22.28 -1 -1 1670.4 MiB 111.91 28.4097 23.3845 1627.5 MiB -1 17.60 +3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 327.67 vpr 1.66 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1742392 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1289.0 MiB 84.58 151125 1190888 390352 769055 31481 1646.6 MiB 73.69 0.67 5.16253 -15574.5 -4.16253 4.57572 0.06 0.14295 0.12611 17.3522 14.6159 255867 10.6625 71175 2.96600 55302 103707 208615694 72938344 0 0 7.26079e+07 20580.5 15 1120110 13214470 -1 5.91719 5.91719 -30815.6 -4.91719 0 0 23.62 -1 -1 1646.6 MiB 95.34 24.5543 21.0784 1646.6 MiB -1 19.49 +3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 139.09 vpr 1.23 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1291272 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1066.0 MiB 49.80 156611 278120 76189 183016 18915 1261.0 MiB 18.22 0.20 5.5971 -16655.2 -4.5971 4.5816 0.03 0.0587051 0.0472882 5.12731 4.2098 232871 19.3688 64465 5.36181 56972 170063 109738115 20757776 0 0 3.14199e+07 20455.7 17 483264 5705245 -1 6.60942 5.3536 -26554.6 -5.60942 0 0 10.35 -1 -1 1261.0 MiB 31.51 8.7766 7.46125 1261.0 MiB -1 6.22 +3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 468.75 vpr 1.78 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1866664 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1361.4 MiB 115.86 298766 2022878 721872 1209208 91798 1694.5 MiB 174.52 1.53 192.881 -65340.9 -191.881 192.881 0.06 0.202016 0.181173 25.4109 21.5614 461781 14.0963 121424 3.70658 122316 378159 341015575 70726261 0 0 7.26079e+07 20580.5 20 1120110 13214470 -1 198.296 198.296 -88522.8 -197.296 0 0 24.15 -1 -1 1743.6 MiB 98.43 37.004 31.8471 1694.5 MiB -1 19.45 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 66.67 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1237180 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1063.0 MiB 15.45 60926 230944 41654 173553 15737 1197.6 MiB 9.59 0.15 4.84629 -4259.39 -3.84629 2.46064 0.02 0.0310798 0.0251181 2.06236 1.71947 97856 7.86814 33858 2.72236 28683 39681 30714017 6195766 0 0 2.48366e+07 20391.3 17 382818 4502703 -1 5.05177 2.69405 -5674.91 -4.05177 0 0 8.19 -1 -1 1197.6 MiB 8.55 3.63438 3.14676 1197.6 MiB -1 4.10 +3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 544.98 vpr 2.19 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2300396 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.1 MiB 76.17 219742 1555886 562141 922870 70875 2246.5 MiB 103.91 1.05 7.36593 -33948.8 -6.36593 7.36593 0.16 0.106572 0.0952071 13.4562 11.2916 354299 17.3676 93322 4.57461 68078 159956 457518312 185590185 0 0 1.86852e+08 20651.1 17 2837414 34147767 -1 8.09599 7.40175 -42456.2 -7.09599 0 0 61.24 -1 -1 2246.5 MiB 222.11 18.7938 16.1322 2246.5 MiB -1 52.95 +3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 302.19 vpr 2.43 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2550728 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.8 MiB 47.82 130160 1380047 560321 782548 37178 2490.9 MiB 35.48 0.32 10.5854 -18606.9 -9.58537 4.72024 0.18 0.0600238 0.0497498 7.88269 6.58458 172969 20.2706 38383 4.49818 23174 90029 105109403 34944955 0 0 2.36204e+08 20647.2 15 3590540 43137666 -1 11.6218 5.22111 -24845.6 -10.6218 0 0 75.93 -1 -1 2490.9 MiB 48.99 10.7341 9.14711 2490.9 MiB -1 68.06 +3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 124.32 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1226084 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1058.1 MiB 67.46 76143 241243 58815 176856 5572 1192.4 MiB 11.31 0.19 7.29112 -42594.5 -6.29112 7.29112 0.02 0.0414227 0.0316342 2.95997 2.38508 119636 19.0382 33085 5.26496 19940 91849 40304260 7468528 0 0 2.39639e+07 20377.5 15 369794 4343188 -1 7.77921 7.77921 -50567.3 -6.77921 0 0 7.94 -1 -1 1192.4 MiB 12.02 5.00754 4.21584 1192.4 MiB -1 4.51 +3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 27.66 vpr 993.31 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1017148 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.6 MiB 6.88 10156 8194 784 6524 886 993.3 MiB 0.47 0.01 5.3048 -3531.01 -4.3048 4.2956 0.00 0.00511192 0.00432104 0.195587 0.167728 15985 11.0623 5210 3.60554 3642 8882 4445146 900786 0 0 4.97530e+06 19135.8 9 75766 878809 -1 5.28906 4.84614 -4691.92 -4.28906 0 0 1.76 -1 -1 993.3 MiB 1.25 0.451107 0.405755 993.3 MiB -1 0.36 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/config.txt new file mode 100644 index 00000000000..68d3b3c2d19 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/config.txt @@ -0,0 +1,78 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif/titan23/stratixiv + +# Path to directory of SDCs to use +sdc_dir=benchmarks/titan_blif/titan23/stratixiv + +# Path to directory of architectures to use +archs_dir=arch/titan + +# Add circuits to list to sweep +circuit_list_add=LU230_stratixiv_arch_timing.blif +circuit_list_add=LU_Network_stratixiv_arch_timing.blif +circuit_list_add=SLAM_spheric_stratixiv_arch_timing.blif +circuit_list_add=bitcoin_miner_stratixiv_arch_timing.blif +circuit_list_add=bitonic_mesh_stratixiv_arch_timing.blif +circuit_list_add=cholesky_bdti_stratixiv_arch_timing.blif +circuit_list_add=cholesky_mc_stratixiv_arch_timing.blif +circuit_list_add=dart_stratixiv_arch_timing.blif +circuit_list_add=denoise_stratixiv_arch_timing.blif +circuit_list_add=des90_stratixiv_arch_timing.blif +circuit_list_add=directrf_stratixiv_arch_timing.blif +circuit_list_add=gsm_switch_stratixiv_arch_timing.blif +circuit_list_add=mes_noc_stratixiv_arch_timing.blif +circuit_list_add=minres_stratixiv_arch_timing.blif +circuit_list_add=neuron_stratixiv_arch_timing.blif +circuit_list_add=openCV_stratixiv_arch_timing.blif +circuit_list_add=segmentation_stratixiv_arch_timing.blif +circuit_list_add=sparcT1_chip2_stratixiv_arch_timing.blif +circuit_list_add=sparcT1_core_stratixiv_arch_timing.blif +circuit_list_add=sparcT2_core_stratixiv_arch_timing.blif +circuit_list_add=stap_qrd_stratixiv_arch_timing.blif +circuit_list_add=stereo_vision_stratixiv_arch_timing.blif +# circuit_list_add=gaussianblur_stratixiv_arch_timing.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(sparcT1_core_stratixiv_arch_timing.blif, device=titan_extra_small) +circuit_constraint_list_add=(SLAM_spheric_stratixiv_arch_timing.blif, device=titan_extra_small) +circuit_constraint_list_add=(stereo_vision_stratixiv_arch_timing.blif, device=titan_small) +circuit_constraint_list_add=(cholesky_mc_stratixiv_arch_timing.blif, device=titan_small) +circuit_constraint_list_add=(neuron_stratixiv_arch_timing.blif, device=titan_small) +circuit_constraint_list_add=(segmentation_stratixiv_arch_timing.blif, device=titan_small) +circuit_constraint_list_add=(dart_stratixiv_arch_timing.blif, device=titan_small) +circuit_constraint_list_add=(denoise_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(sparcT2_core_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(stap_qrd_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(cholesky_bdti_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(des90_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(mes_noc_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(openCV_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(LU_Network_stratixiv_arch_timing.blif, device=titan_large) +circuit_constraint_list_add=(minres_stratixiv_arch_timing.blif, device=titan_large) +circuit_constraint_list_add=(bitcoin_miner_stratixiv_arch_timing.blif, device=titan_large) +circuit_constraint_list_add=(bitonic_mesh_stratixiv_arch_timing.blif, device=titan_large) +circuit_constraint_list_add=(gsm_switch_stratixiv_arch_timing.blif, device=titan_large) +circuit_constraint_list_add=(sparcT1_chip2_stratixiv_arch_timing.blif, device=titan_large) +circuit_constraint_list_add=(directrf_stratixiv_arch_timing.blif, device=titan_extra_large) +circuit_constraint_list_add=(LU230_stratixiv_arch_timing.blif, device=titan_extra_large) +# circuit_constraint_list_add=(gaussianblur_stratixiv_arch_timing.blif, device=titan_extra_large) + +# Add architectures to list to sweep +arch_list_add=stratixiv_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan.txt + +# Pass the script params while writing the vpr constraints. +# WL DRIVEN +script_params=-starting_stage vpr --analytical_place --route --route_chan_width 300 --max_router_iterations 400 --router_lookahead map -timeout 86400 --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --timing_analysis off diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt new file mode 100644 index 00000000000..37bf9a4b00b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt @@ -0,0 +1,23 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 5977.17 vpr 18.15 GiB 373 16802 116 5043 16 0 success v8.0.0-12397-gd42b93a83 release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-04-10T17:44:49 agent-2 /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan 19027644 178 195 583584 0 2 400505 22350 450 333 149850 -1 titan_extra_large -1 -1 8 13800219 48167472 20323894 27731780 111798 18581.7 MiB 4325.24 9.70 -1 -1 -1 -1 -1 -1 0 0 0 0 14590895 36.4326 2750092 6.86682 839764 1658253 951523382 215783707 0 0 2.82057e+09 18822.7 11 43073670 476336488 -1 -1 -1 -1 -1 -1 -1 786.18 -1 -1 18581.7 MiB 264.68 0 0 18581.7 MiB -1 431.81 +stratixiv_arch.timing.xml LU_Network_stratixiv_arch_timing.blif common 6231.23 vpr 12.33 GiB 446 31279 112 1175 0 2 success v8.0.0-12397-gd42b93a83 release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-04-10T17:44:49 agent-2 /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan 12931844 85 185 639752 0 28 383369 33014 300 222 66600 -1 titan_large -1 -1 5 4382970 73613776 28087356 45057103 469317 12628.8 MiB 5449.42 11.97 -1 -1 -1 -1 -1 -1 0 0 0 0 5412290 14.1365 1208865 3.15746 725653 1571351 484682465 110344144 0 0 1.23727e+09 18577.7 10 19158880 211389679 -1 -1 -1 -1 -1 -1 -1 337.84 -1 -1 12628.8 MiB 129.09 0 0 12628.8 MiB -1 172.57 +stratixiv_arch.timing.xml SLAM_spheric_stratixiv_arch_timing.blif common 978.21 vpr 2.83 GiB 479 5395 37 0 0 0 success v8.0.0-12397-gd42b93a83 release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-04-10T17:44:49 agent-2 /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan 2968776 323 156 114323 0 1 74722 5911 100 74 7400 -1 titan_extra_small -1 -1 5 952942 6042597 2451728 3507314 83555 2899.2 MiB 845.55 2.07 -1 -1 -1 -1 -1 -1 0 0 0 0 1227102 16.4227 285050 3.81491 174997 556519 135205758 28286969 0 0 1.36295e+08 18418.2 11 2149958 23360463 -1 -1 -1 -1 -1 -1 -1 36.88 -1 -1 2899.2 MiB 39.92 0 0 2899.2 MiB -1 16.65 +stratixiv_arch.timing.xml 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regression_tests/vtr_reg_nightly_test7/titan_other_run_flat #regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_run_flat #regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_depop_run_flat diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt index a425bc681fa..718952957d1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt @@ -1,17 +1,17 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks 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create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 428.95 vpr 5.69 GiB 274 985 36 59 0 2 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5971508 22 252 53001 29054 7 24677 1356 89 66 5874 DSP auto 1467.0 MiB 29.42 248371 954110 285143 562881 106086 2057.9 MiB 74.97 0.48 8.02184 -42397.1 -7.02184 3.20007 0.04 0.161633 0.140714 21.3998 18.8902 338955 6.39912 75485 1.42508 121441 289695 240594743 33482528 0 0 1.48105e+08 25213.7 39 3159283 31787115 49857 7.80104 2.93519 -40292.1 -6.80104 0 0 39.35 35.55 25.88 5831.3 MiB 166.75 33.3779 29.4514 2057.9 MiB 63.99 86.71 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 6267952 4 570 66175 54803 2 39284 3388 91 67 6097 io auto 1706.5 MiB 160.61 638374 2775803 1006957 1681672 87174 2241.8 MiB 163.90 1.29 30.5835 -120026 -29.5835 6.7874 0.04 0.263073 0.221418 30.5747 25.8293 932098 14.0864 206865 3.12627 313209 1690318 954117063 123613138 0 0 1.53690e+08 25207.4 27 4525410 53890031 131493 29.7513 6.85838 -125627 -28.7513 0 0 33.31 54.47 38.26 6120.8 MiB 327.83 43.1256 36.2726 2241.8 MiB 62.26 88.69 -stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 434.21 vpr 5.92 GiB 36 1347 8 149 2 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 6203740 3 33 52402 39411 1 28031 1542 73 54 3942 M9K auto 1506.8 MiB 95.28 323184 838612 237748 580980 19884 1853.6 MiB 66.53 0.68 17.7952 -334079 -16.7952 17.7952 0.03 0.154745 0.126064 15.9138 12.957 406168 7.75219 92691 1.76911 132469 475520 169127598 17802510 0 0 9.96430e+07 25277.3 38 3040453 30196243 80077 17.4909 17.4909 -335232 -16.4909 0 0 22.40 42.41 31.76 6058.3 MiB 168.17 27.0613 22.1224 1853.6 MiB 67.97 48.05 -stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 223.68 vpr 4.84 GiB 251 959 1 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5078096 55 196 20131 19956 1 8238 1228 44 33 1452 io auto 1355.0 MiB 51.43 120172 619090 201214 397879 19997 1469.9 MiB 15.63 0.17 8.13439 -80298.9 -7.13439 8.13439 0.01 0.0497327 0.0426725 5.13046 4.11514 171217 8.50641 39945 1.98455 53315 231814 61625526 5048493 0 0 3.65488e+07 25171.3 31 1360323 16115684 53903 8.22633 8.22633 -82640.4 -7.22633 0 0 10.79 18.71 13.33 4958.8 MiB 105.23 8.36643 6.63879 1463.0 MiB 66.70 15.62 -stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 431.82 vpr 5.47 GiB 255 2119 1 28 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5732792 84 171 36458 36247 3 20421 2403 62 46 2852 LAB auto 1495.6 MiB 121.86 290701 1595115 570423 937667 87025 1731.5 MiB 59.06 0.88 12.9798 -90874.5 -11.9798 4.66054 0.02 0.17766 0.134007 15.0676 12.1411 404601 11.1020 89060 2.44375 122881 589071 155442818 13359079 0 0 7.20371e+07 25258.4 18 2648236 32071807 68561 13.0244 4.46105 -93007.9 -12.0244 0 0 20.45 38.56 26.05 5598.4 MiB 152.24 20.3374 16.3586 1731.5 MiB 67.96 44.69 -stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 539.67 vpr 6.16 GiB 478 1247 1 300 4 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 6457104 202 276 35125 30509 3 21749 2030 106 79 8374 M9K auto 1451.1 MiB 75.73 260809 1697966 584525 1053901 59540 2326.5 MiB 69.69 0.42 9.41173 -47933.7 -8.41173 3.39967 0.05 0.134641 0.105417 19.7532 15.4741 313986 8.94063 65931 1.87736 96858 402480 121760850 21350695 0 0 2.11299e+08 25232.8 22 3960251 43027550 63662 8.19797 3.68858 -71562.1 -7.19797 0 0 54.52 55.09 40.21 6305.8 MiB 161.98 25.3227 19.9869 2326.5 MiB 66.34 144.43 -stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 321.41 vpr 5.38 GiB 5 331 31 105 0 2 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5636340 3 2 14862 10304 26 7580 474 89 66 5874 DSP auto 1300.6 MiB 52.12 119481 175939 46938 124613 4388 1941.1 MiB 10.79 0.10 5.88056 -30914.8 -4.88056 4.13266 0.03 0.0612334 0.0539792 6.49277 5.46245 146943 9.90449 29299 1.97486 42949 181573 51132764 5390460 0 0 1.48105e+08 25213.7 14 2293428 23912154 38101 4.50499 3.70819 -37430.5 -3.50499 0 0 39.27 24.81 17.74 5504.2 MiB 114.27 8.41206 7.05794 1941.1 MiB 73.15 80.30 -stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 604.42 vpr 5.88 GiB 693 1782 25 16 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 6163500 35 658 51416 37539 1 27489 2516 108 80 8640 io auto 1545.4 MiB 78.23 235688 2328796 788065 1390229 150502 2425.2 MiB 108.94 0.73 41.8548 -65336.7 -40.8548 41.8548 0.05 0.182563 0.166931 27.3116 23.6666 331843 6.64936 78001 1.56296 165823 675315 288495127 31315475 0 0 2.18145e+08 25248.3 25 4406446 50088530 83951 38.7687 38.7687 -62631.6 -37.7687 0 0 56.64 43.29 29.65 6019.0 MiB 179.17 35.858 30.9207 2425.2 MiB 66.65 145.87 -stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 490.19 vpr 5.49 GiB 753 1117 5 32 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5761892 13 740 25173 25306 1 12677 1907 117 87 10179 io auto 1397.7 MiB 56.69 158532 1337680 499407 780615 57658 2495.4 MiB 38.42 0.23 9.04712 -33408.1 -8.04712 8.7062 0.06 0.0593076 0.0526541 10.3875 8.4919 194524 7.72964 42258 1.67917 67248 314264 80325919 6195706 0 0 2.57091e+08 25257.0 16 4145714 46103256 60712 9.44565 8.02164 -41382.5 -8.44565 0 0 57.13 29.02 17.50 5626.8 MiB 125.09 13.501 10.9774 2495.4 MiB 68.37 185.29 -stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 207.70 vpr 5.16 GiB 54 661 0 40 0 1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5413568 2 52 16673 16662 2 12103 756 37 27 999 LAB auto 1332.8 MiB 39.94 182960 252022 64860 179647 7515 1435.5 MiB 11.93 0.15 6.11901 -21401.8 -5.11901 5.08095 0.01 0.0565371 0.0449556 4.69769 3.76454 240240 14.4124 55528 3.33121 73264 390943 149921058 16354331 0 0 2.50432e+07 25068.2 20 1108499 11576081 35204 6.84174 5.56247 -26781.1 -5.84174 0 0 7.65 15.28 11.31 5286.7 MiB 116.23 7.63028 6.11936 1392.9 MiB 61.87 7.85 -stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 145.06 vpr 4.71 GiB 42 752 0 0 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 4934812 13 29 26295 20086 1 12536 794 39 29 1131 LAB auto 1329.3 MiB 12.27 76015 258044 53765 191160 13119 1421.9 MiB 8.56 0.11 4.99496 -5275.28 -3.99496 2.88115 0.01 0.0346645 0.0283209 2.62579 2.18191 86766 3.29997 21050 0.800593 54834 71341 33867829 3195419 0 0 2.84345e+07 25141.0 17 1246323 12347232 14132 3.54641 2.89399 -5805.4 -2.54641 0 0 8.60 11.69 7.86 4819.2 MiB 83.22 3.9986 3.31593 1386.6 MiB 62.52 10.13 -stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 915.69 vpr 5.93 GiB 964 976 19 34 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 6215724 542 422 37277 26038 1 20609 1993 147 109 16023 io auto 1415.0 MiB 64.39 248974 1619266 607103 947945 64218 3187.8 MiB 75.54 0.68 8.38795 -43141.1 -7.38795 8.38795 0.09 0.115964 0.0986763 16.0502 13.7598 328246 8.80630 70845 1.90065 110233 335979 524318827 154462291 0 0 4.05153e+08 25285.7 64 5882994 65429817 45007 8.03999 7.98626 -51092.4 -7.03999 0 0 103.28 39.29 23.30 6070.0 MiB 349.45 29.8141 25.6449 3187.8 MiB 59.96 287.52 -stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 748.11 vpr 5.79 GiB 1107 719 0 0 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 6066732 403 704 15490 16194 1 8578 1826 167 124 20708 io auto 1326.2 MiB 59.68 191872 1351702 518260 795694 37748 3664.4 MiB 22.00 0.18 12.747 -23348.6 -11.747 5.87647 0.22 0.055378 0.0492417 7.51842 6.33745 234362 15.1309 39654 2.56014 41635 226559 55203082 4251380 0 0 5.23921e+08 25300.4 18 6720982 74598209 36896 11.745 5.81823 -32706.7 -10.745 0 0 136.86 30.11 13.54 5924.5 MiB 113.58 9.62012 8.10804 3664.4 MiB 61.24 384.70 -stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 199.44 vpr 4.72 GiB 35 731 0 6 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 4951472 18 17 16969 16357 1 6316 772 39 29 1131 LAB auto 1324.1 MiB 53.52 86613 255652 66755 185847 3050 1424.2 MiB 8.79 0.13 7.13037 -40670.7 -6.13037 7.13037 0.01 0.0390029 0.0309978 3.15152 2.51856 121385 7.15503 28025 1.65193 47865 258456 72672688 6504539 0 0 2.84345e+07 25141.0 37 1091666 12266607 43440 7.12455 7.12455 -43536.9 -6.12455 0 0 8.32 12.62 8.86 4835.4 MiB 93.40 6.0413 4.8334 1380.2 MiB 61.27 11.59 -stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 94.11 vpr 4.39 GiB 35 78 0 8 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 4605040 18 17 2291 2142 1 1502 121 16 12 192 LAB M9K auto 1221.1 MiB 5.74 10236 9390 1004 7372 1014 1290.4 MiB 0.82 0.01 5.31114 -4105.51 -4.31114 4.53509 0.00 0.00620249 0.00535395 0.259352 0.226533 13262 5.79633 3436 1.50175 7580 28332 7737888 644646 0 0 4.72128e+06 24590.0 42 153746 1493427 4612 4.44499 4.44499 -3952.72 -3.44499 0 0 1.88 2.19 1.68 4497.1 MiB 65.56 0.783495 0.672064 1259.5 MiB 60.88 0.58 +stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 430.27 vpr 7.22 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7572608 22 252 53001 29054 7 22984 1419 89 66 5874 DSP auto 2999.7 MiB 77.55 248316 1021579 298715 629192 93672 3552.4 MiB 75.43 0.60 7.79847 -44076.4 -6.79847 3.16357 0.04 0.145495 0.126331 19.1685 16.7404 337990 6.38090 73939 1.39589 113486 262947 123939600 20677912 0 0 1.48102e+08 25213.2 18 3168173 32237029 53333 8.13811 2.93957 -42084.8 -7.13811 0 0 30.24 37.78 22.78 7394.9 MiB 150.02 24.6012 21.633 3552.4 MiB 61.30 11.40 +stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 423.49 vpr 6.82 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7148500 3 33 48977 39238 1 26095 1641 54 40 2160 LAB auto 3019.2 MiB 103.15 286068 978816 295772 657268 25776 3171.0 MiB 80.85 0.83 87.9237 -89444.7 -86.9237 87.9237 0.02 0.133548 0.111652 14.7315 12.3725 377246 7.70314 89630 1.83019 136470 456181 107134305 13321542 0 0 5.45421e+07 25251.0 24 2489089 26482784 65639 72.0152 72.0152 -145316 -71.0152 0 0 10.89 30.08 16.61 6981.0 MiB 142.54 20.844 17.5112 3143.2 MiB 62.59 3.96 +stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 711.87 vpr 7.51 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7875556 4 570 66175 54803 2 39221 3376 91 67 6097 io auto 3239.4 MiB 185.13 637050 2737396 996225 1655508 85663 3733.5 MiB 161.80 1.29 31.0835 -120493 -30.0835 7.14678 0.06 0.211633 0.187447 26.5121 22.2855 899864 13.5993 200525 3.03045 250269 1330369 403832098 58432790 0 0 1.53687e+08 25207.0 23 4527063 53934418 131001 31.4743 7.04434 -123107 -30.4743 0 0 31.82 48.91 25.68 7690.6 MiB 229.13 35.3927 29.9033 3733.5 MiB 54.44 12.02 +stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 490.17 vpr 7.44 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7802588 3 33 52402 39411 1 26961 1588 73 54 3942 M9K auto 3038.9 MiB 115.22 308817 862861 247827 593176 21858 3344.5 MiB 70.28 0.75 18.2872 -344515 -17.2872 18.2872 0.04 0.144193 0.116967 14.4383 11.7329 388387 7.41281 89501 1.70823 127828 482181 86633732 10962711 0 0 9.96402e+07 25276.6 23 3049699 30612935 82279 18.1508 18.1508 -339276 -17.1508 0 0 19.96 46.42 29.95 7619.5 MiB 155.40 20.4894 16.7826 3344.5 MiB 62.62 7.54 +stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 264.87 vpr 6.35 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6658268 55 196 20131 19956 1 8273 1224 44 33 1452 io auto 2885.6 MiB 59.05 121891 590184 190135 382049 18000 3003.9 MiB 21.76 0.23 8.00991 -79285.3 -7.00991 8.00991 0.01 0.0550621 0.0436789 5.54087 4.43725 168265 8.35975 39603 1.96756 52203 214680 35422307 3611930 0 0 3.65459e+07 25169.4 13 1361186 16140321 53661 8.2494 8.2494 -80319.6 -7.2494 0 0 7.63 18.91 10.40 6502.2 MiB 101.02 6.87899 5.53912 2972.4 MiB 65.45 3.08 +stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 461.02 vpr 6.99 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7325496 84 171 36458 36247 3 20327 2406 62 46 2852 LAB auto 3026.4 MiB 149.19 282856 1613906 577988 956437 79481 3228.2 MiB 60.47 0.55 12.7635 -89890.6 -11.7635 4.81564 0.03 0.118349 0.0946709 13.1884 10.6839 385220 10.5702 85805 2.35443 120726 551439 87035965 8547461 0 0 7.20342e+07 25257.4 15 2649463 32096142 68009 12.7106 4.59591 -89170.4 -11.7106 0 0 14.69 35.95 19.46 7153.8 MiB 138.86 16.8557 13.6644 3228.2 MiB 62.61 5.90 +stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 536.44 vpr 7.68 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 8052732 202 276 35125 30509 3 21219 2016 106 79 8374 M9K auto 2979.7 MiB 92.45 275268 1593266 551386 986614 55266 3817.0 MiB 63.87 0.46 9.2665 -49067 -8.2665 3.57275 0.06 0.128588 0.0997349 17.2665 13.8123 330934 9.42322 69644 1.98309 96626 409213 76592480 17612840 0 0 2.11296e+08 25232.4 22 3960168 43100363 65824 7.92317 3.74791 -72552.8 -6.92317 0 0 43.69 57.06 35.19 7864.0 MiB 168.53 22.5205 18.1449 3817.0 MiB 63.34 20.57 +stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 316.30 vpr 6.89 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7222344 3 2 14862 10304 26 7583 476 89 66 5874 DSP auto 2832.3 MiB 45.71 124138 182462 49732 129080 3650 3434.9 MiB 11.57 0.11 5.88079 -31819.8 -4.88079 4.5134 0.05 0.0575387 0.0481419 6.23293 5.24991 151302 10.1983 29977 2.02056 41602 169090 28196463 3392334 0 0 1.48102e+08 25213.2 14 2293667 23918971 38105 5.43555 4.34297 -36900.7 -4.43555 0 0 31.66 30.81 19.91 7053.1 MiB 114.27 8.0475 6.8139 3434.9 MiB 67.70 13.08 +stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 542.79 vpr 7.40 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7764172 35 658 51416 37539 1 27427 2531 108 80 8640 io auto 3075.8 MiB 93.41 241934 2243861 754419 1344439 145003 3917.1 MiB 110.58 0.77 41.8615 -66574.8 -40.8615 41.8615 0.09 0.160304 0.137258 23.4482 20.061 335308 6.71879 78438 1.57171 166276 681051 158387837 20955778 0 0 2.18142e+08 25247.9 25 4407721 50162159 84809 37.8945 37.8945 -63952.6 -36.8945 0 0 44.15 46.45 23.73 7582.2 MiB 178.57 31.4578 26.962 3917.1 MiB 63.71 20.46 +stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 387.65 vpr 7.01 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7354908 13 740 25173 25306 1 12716 1903 117 87 10179 io auto 2928.2 MiB 67.88 151917 1239643 452352 735278 52013 3981.2 MiB 35.57 0.31 9.32912 -33745.1 -8.32912 8.97758 0.07 0.0799309 0.0699705 9.04546 7.55642 187992 7.47008 41392 1.64476 64808 295441 45317315 4493718 0 0 2.57088e+08 25256.7 13 4146271 46119125 60560 9.51895 7.86886 -41989.5 -8.51895 0 0 53.18 36.15 16.47 7182.2 MiB 123.92 11.2875 9.41327 3981.2 MiB 65.19 23.64 +stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 286.07 vpr 6.67 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6992700 2 52 16673 16662 2 12027 760 37 27 999 LAB auto 2863.8 MiB 48.35 185817 260785 68816 184545 7424 2969.0 MiB 17.52 0.22 6.43593 -22019.6 -5.43593 5.34219 0.01 0.0671365 0.0537497 5.45437 4.46867 243748 14.6228 55949 3.35647 70980 378754 80104321 9851562 0 0 2.50403e+07 25065.4 18 1109643 11618783 35248 6.97929 5.65113 -27162.3 -5.97929 0 0 5.11 17.57 11.32 6828.4 MiB 118.26 7.83981 6.43355 2903.7 MiB 66.65 1.88 +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 191.95 vpr 6.21 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6512136 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 2859.5 MiB 15.81 72155 253216 50624 190930 11662 2954.0 MiB 12.28 0.16 5.18599 -5515.92 -4.18599 2.85104 0.01 0.0356803 0.031132 2.85133 2.36966 82362 3.13247 19973 0.759632 54490 69977 15062795 1948535 0 0 2.84316e+07 25138.5 15 1246468 12354669 14284 3.84664 2.85129 -5700.97 -2.84664 0 0 5.78 12.08 6.10 6359.5 MiB 88.58 3.91742 3.26807 2899.6 MiB 66.17 2.25 +stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 545.23 vpr 7.47 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7832592 542 422 37277 26038 1 20403 2136 147 109 16023 io auto 2946.3 MiB 79.74 272838 1734636 659517 1007756 67363 4655.4 MiB 94.94 0.83 8.43041 -42423.1 -7.43041 8.08995 0.12 0.108337 0.0956704 15.1499 12.7644 351764 9.43725 76208 2.04454 89867 266535 93690673 14464239 0 0 4.05150e+08 25285.5 17 5915256 66794449 49681 8.39022 7.49893 -50294.9 -7.39022 0 0 83.08 50.78 21.66 7649.0 MiB 158.81 18.8518 16.0306 4655.4 MiB 64.94 40.50 +stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 445.21 vpr 7.31 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7666364 403 704 15490 16194 1 8534 1832 167 124 20708 io auto 2857.1 MiB 56.44 187193 1324022 523278 764997 35747 5137.0 MiB 26.81 0.24 12.7682 -23323.6 -11.7682 6.27217 0.15 0.0586464 0.0483811 7.15433 5.97963 227077 14.6605 37744 2.43683 40915 222692 34388107 3312547 0 0 5.23918e+08 25300.3 17 6721105 74589014 36638 11.3367 5.96529 -32928.6 -10.3367 0 0 108.17 38.65 9.61 7486.7 MiB 125.03 9.2614 7.7773 5137.0 MiB 64.95 52.28 +stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 247.80 vpr 6.23 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6530136 18 17 16969 16357 1 6288 780 39 29 1131 LAB auto 2855.4 MiB 65.95 84377 244832 62116 178083 4633 2954.7 MiB 10.90 0.16 7.65805 -46422.6 -6.65805 7.65805 0.01 0.0380001 0.0324758 3.26975 2.63245 117354 6.91742 28009 1.65099 42731 188939 30663841 3241611 0 0 2.84316e+07 25138.5 16 1092397 12303174 43762 7.24996 7.24996 -46266.9 -6.24996 0 0 5.81 13.06 7.12 6376.9 MiB 93.57 4.60783 3.72572 2904.9 MiB 65.30 2.17 +stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 143.49 vpr 5.89 GiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6175112 18 17 2291 2142 1 1448 121 16 12 192 LAB M9K auto 2752.7 MiB 6.96 10189 9390 1103 7334 953 2822.6 MiB 0.78 0.01 5.3129 -4153.14 -4.3129 4.5918 0.00 0.00661338 0.00538061 0.265542 0.227477 13189 5.76442 3423 1.49607 7406 28929 4207039 458732 0 0 4.71840e+06 24575.0 16 154367 1513720 4558 4.32353 4.32353 -3831.79 -3.32353 0 0 1.05 2.34 1.56 6030.2 MiB 71.16 0.476743 0.411197 2791.2 MiB 66.66 0.13 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt index e09520ad1f6..f0282e9bf5e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_k6_frac_N8_22nm.xml single_wire.v common 1.82 vpr 73.57 MiB -1 -1 0.10 17092 1 0.02 -1 -1 30112 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 75340 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 73.6 MiB 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 73.6 MiB 0.24 73.6 MiB 0.20 8 16 1 6.79088e+06 0 166176. 575.005 0.38 0.00152779 0.00147101 20206 45088 -1 18 1 1 1 141 56 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.10 0.00 0.05 -1 -1 0.10 0.00136912 0.0013327 - fixed_k6_frac_N8_22nm.xml single_ff.v common 2.13 vpr 72.83 MiB -1 -1 0.11 17428 1 0.03 -1 -1 30100 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 74580 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 72.8 MiB 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72.8 MiB 0.19 72.8 MiB 0.17 20 31 1 6.79088e+06 13472 414966. 1435.87 0.48 0.00134713 0.0012663 22510 95286 -1 39 1 2 2 247 61 0.942216 0.942216 -1.68896 -0.942216 0 0 503264. 1741.40 0.21 0.00 0.09 -1 -1 0.21 0.00158671 0.0015335 - fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 3.81 vpr 73.68 MiB -1 -1 0.40 18964 3 0.12 -1 -1 33228 -1 -1 43 99 2 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 75444 99 130 240 229 1 247 274 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 73.7 MiB 0.36 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 73.7 MiB 0.36 73.7 MiB 0.34 32 3096 19 6.79088e+06 1.6753e+06 586450. 2029.24 1.11 0.122876 0.111163 24814 144142 -1 2911 28 730 1212 168873 64441 2.43138 2.43138 -153.888 -2.43138 0 0 744469. 2576.02 0.30 0.17 0.13 -1 -1 0.30 0.0795405 0.0727107 - fixed_k6_frac_N8_22nm.xml diffeq1.v common 14.42 vpr 75.12 MiB -1 -1 0.63 23572 15 0.47 -1 -1 34420 -1 -1 66 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76920 162 96 817 258 1 798 329 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 75.1 MiB 1.63 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.1 MiB 1.63 75.1 MiB 0.83 74 17094 47 6.79088e+06 2.86915e+06 1.22589e+06 4241.83 7.19 0.927094 0.854352 32590 314081 -1 14562 21 4154 11035 1472312 353034 22.5845 22.5845 -1896.41 -22.5845 0 0 1.52683e+06 5283.16 0.65 0.52 0.33 -1 -1 0.65 0.149256 0.138152 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + fixed_k6_frac_N8_22nm.xml single_wire.v common 1.34 vpr 75.71 MiB -1 -1 0.07 20608 1 0.01 -1 -1 33172 -1 -1 0 1 0 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77532 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 2 2 3 0 0 3 75.7 MiB 0.48 0.00 0.2714 0.2714 -0.2714 -0.2714 nan 0.40 1.4684e-05 9.512e-06 8.1482e-05 5.6821e-05 75.7 MiB 0.48 75.7 MiB 0.07 8 16 1 6.79088e+06 0 166176. 575.005 0.15 0.000912133 0.000836449 20206 45088 -1 18 1 1 1 141 56 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.01 0.00 0.04 -1 -1 0.01 0.000776852 0.0007249 + fixed_k6_frac_N8_22nm.xml single_ff.v common 1.51 vpr 75.95 MiB -1 -1 0.08 20852 1 0.02 -1 -1 33716 -1 -1 1 2 0 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77776 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 22 24 9 1 1 7 76.0 MiB 0.47 0.00 0.930505 0.74674 -1.43836 -0.74674 0.74674 0.39 1.1513e-05 7.851e-06 8.3564e-05 6.0773e-05 76.0 MiB 0.47 76.0 MiB 0.07 20 31 1 6.79088e+06 13472 414966. 1435.87 0.24 0.000928712 0.000851847 22510 95286 -1 32 1 2 2 231 42 0.74674 0.74674 -1.43836 -0.74674 0 0 503264. 1741.40 0.03 0.00 0.08 -1 -1 0.03 0.000833737 0.000775898 + fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 2.74 vpr 76.62 MiB -1 -1 0.26 22392 3 0.07 -1 -1 37308 -1 -1 67 99 1 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78456 99 130 240 229 1 225 297 17 17 289 -1 unnamed_device -1 -1 978 866 19107 2257 1105 15745 76.6 MiB 0.61 0.00 2.26688 1.84068 -122.242 -1.84068 1.84068 0.39 0.000595647 0.000527536 0.0138425 0.0123349 76.6 MiB 0.61 76.6 MiB 0.13 34 1974 43 6.79088e+06 1.45062e+06 618332. 2139.56 0.79 0.175076 0.154945 25102 150614 -1 1739 14 569 895 60631 18120 2.0466 2.0466 -143.082 -2.0466 -0.04337 -0.04337 787024. 2723.27 0.04 0.03 0.13 -1 -1 0.04 0.0355147 0.0319235 + fixed_k6_frac_N8_22nm.xml diffeq1.v common 9.26 vpr 78.62 MiB -1 -1 0.36 26868 15 0.31 -1 -1 37472 -1 -1 47 162 0 5 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 80512 162 96 817 258 1 691 310 17 17 289 -1 unnamed_device -1 -1 7341 6689 25462 269 7038 18155 78.6 MiB 1.27 0.01 22.1608 21.0485 -1573.19 -21.0485 21.0485 0.38 0.00201699 0.00177192 0.0590804 0.052726 78.6 MiB 1.27 78.6 MiB 0.26 54 12827 26 6.79088e+06 2.61318e+06 949917. 3286.91 5.15 0.794403 0.715337 28846 232421 -1 11184 19 3449 7611 967200 252634 20.9913 20.9913 -1571.36 -20.9913 0 0 1.17392e+06 4061.99 0.06 0.26 0.21 -1 -1 0.06 0.158612 0.144189 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt index 91bac1cf221..39aa722daca 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 10.66 vpr 75.07 MiB -1 -1 0.35 18416 1 0.08 -1 -1 32256 -1 -1 12 130 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76872 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.0 MiB 0.29 1916 35953 11702 19824 4427 75.1 MiB 0.33 0.00 5.12303 -634.784 -5.12303 5.12303 0.88 0.00199221 0.00189164 0.140924 0.132687 -1 -1 -1 -1 82 3595 10 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 4.92 0.71462 0.660858 33448 250998 -1 3301 8 676 703 150435 58622 4.57723 4.57723 -633.308 -4.57723 0 0 1.53308e+06 7821.82 0.49 0.15 0.48 -1 -1 0.49 0.0533478 0.0508037 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 10.40 vpr 75.02 MiB -1 -1 0.30 18440 1 0.07 -1 -1 32232 -1 -1 12 130 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76816 130 40 596 562 1 356 185 14 14 196 dsp_top auto 35.9 MiB 0.28 1916 35953 11702 19824 4427 75.0 MiB 0.32 0.00 5.12303 -634.784 -5.12303 5.12303 0.77 0.001372 0.00128332 0.125861 0.118102 -1 -1 -1 -1 82 3590 8 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 4.81 0.680937 0.627391 33448 250998 -1 3307 8 685 712 152508 59455 4.57723 4.57723 -633.101 -4.57723 0 0 1.53308e+06 7821.82 0.50 0.29 0.40 -1 -1 0.50 0.0712463 0.0684693 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 9.38 vpr 77.35 MiB -1 -1 0.36 22280 1 0.10 -1 -1 35580 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79208 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.5 MiB 0.18 1862 38583 13232 21153 4198 77.4 MiB 0.24 0.00 5.12303 -624.562 -5.12303 5.12303 0.45 0.00115671 0.00104931 0.13445 0.124537 -1 -1 -1 -1 64 3969 9 4.93594e+06 1.0962e+06 976140. 4980.31 5.77 0.971386 0.907233 31408 195022 -1 3606 8 821 857 201107 78801 4.57723 4.57723 -666.876 -4.57723 0 0 1.23909e+06 6321.90 0.06 0.12 0.38 -1 -1 0.06 0.0628918 0.0600921 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 7.77 vpr 77.61 MiB -1 -1 0.36 22212 1 0.08 -1 -1 35140 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79472 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.6 MiB 0.18 1862 38583 13232 21153 4198 77.6 MiB 0.37 0.00 5.12303 -624.562 -5.12303 5.12303 0.55 0.00210597 0.00194049 0.204405 0.191731 -1 -1 -1 -1 64 3993 10 4.93594e+06 1.0962e+06 976140. 4980.31 3.98 0.785401 0.735059 31408 195022 -1 3592 9 794 830 166912 64369 4.57723 4.57723 -658.916 -4.57723 0 0 1.23909e+06 6321.90 0.07 0.13 0.32 -1 -1 0.07 0.068841 0.0645644 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt index 85e095de4e0..4e167973fd7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 18.25 vpr 77.09 MiB -1 -1 0.78 20036 1 0.12 -1 -1 34336 -1 -1 23 130 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 78936 130 40 1147 997 1 585 196 14 14 196 dsp_top auto 38.0 MiB 0.70 2881 41164 12013 24103 5048 77.1 MiB 0.38 0.01 6.00943 -707.528 -6.00943 6.00943 0.74 0.00343703 0.00329093 0.145992 0.134216 -1 -1 -1 -1 110 5376 49 4.93594e+06 1.40315e+06 1.58123e+06 8067.52 11.44 1.37108 1.222 36820 330950 -1 4864 22 2349 2464 267041 89229 7.0711 7.0711 -772.235 -7.0711 0 0 1.96868e+06 10044.3 0.59 0.20 0.57 -1 -1 0.59 0.101693 0.0932648 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 9.61 vpr 79.62 MiB -1 -1 0.81 23308 1 0.11 -1 -1 37544 -1 -1 23 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 81536 130 40 1147 997 1 585 196 14 14 196 dsp_top auto 40.6 MiB 0.64 2711 47992 15247 26403 6342 79.6 MiB 0.47 0.01 6.04823 -699.558 -6.04823 6.04823 0.48 0.00203985 0.00179993 0.208906 0.186707 -1 -1 -1 -1 108 5255 25 4.93594e+06 1.40315e+06 1.55765e+06 7947.21 4.22 0.825967 0.736098 36552 325092 -1 4721 19 2233 2309 243533 83581 7.64092 7.64092 -760.756 -7.64092 0 0 1.93951e+06 9895.46 0.09 0.19 0.61 -1 -1 0.09 0.108869 0.100506 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/config.txt new file mode 100644 index 00000000000..245fb466a3d --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/config.txt @@ -0,0 +1,35 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif/other_benchmarks/stratixiv + +# Path to directory of SDC files to use +sdc_dir=benchmarks/titan_blif/other_benchmarks/stratixiv + +# Path to directory of architectures to use +archs_dir=arch/multi_die/stratixiv_3d + +# Add circuits to list to sweep +circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif + +# Add architectures to list to sweep +arch_list_add=3d_SB_inter_die_stratixiv_arch.timing.xml +arch_list_add=3d_full_OPIN_inter_die_stratixiv_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan.txt + +script_params=-starting_stage vpr -track_memory_usage --route_chan_width 300 --max_router_iterations 400 --router_lookahead map +script_params_list_add = --place_bounding_box_mode auto_bb +script_params_list_add = --place_bounding_box_mode cube_bb +script_params_list_add = --place_bounding_box_mode per_layer_bb + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt new file mode 100644 index 00000000000..22cc148a91e --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt @@ -0,0 +1,7 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_auto_bb 83.45 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421664 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.4 MiB 12.25 180137 58272 230944 40790 173771 16383 1388.3 MiB 10.48 0.15 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.0444933 0.0387879 3.15031 2.6241 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 12.21 -1 -1 1388.3 MiB 10.28 4.91142 4.17713 1388.3 MiB -1 16.75 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_cube_bb 85.51 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421424 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.5 MiB 12.33 180137 58272 230944 40790 173771 16383 1388.1 MiB 10.48 0.14 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.0434223 0.0377288 3.13504 2.6098 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 13.53 -1 -1 1388.1 MiB 10.72 4.93468 4.19984 1388.1 MiB -1 17.21 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_per_layer_bb 86.05 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421572 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.7 MiB 12.02 186170 63595 242080 43083 181450 17547 1388.3 MiB 12.05 0.17 5.04678 4.86192 -4242.28 -3.86192 2.41884 0.05 0.051916 0.0457829 3.35985 2.75261 103428 8.31615 32795 2.63689 27768 38066 44034475 9785894 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 5.18643 2.65983 -5392.13 -4.18642 0 0 13.06 -1 -1 1388.3 MiB 9.86 5.14157 4.32891 1388.3 MiB -1 18.69 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_auto_bb 57.03 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245688 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.9 MiB 11.85 186170 63157 219808 34278 166444 19086 1216.5 MiB 10.07 0.18 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.01 0.0545904 0.0489007 2.99902 2.51676 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 9.46 -1 -1 1216.5 MiB 4.58 4.95133 4.23051 1216.5 MiB -1 1.96 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_cube_bb 56.04 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245528 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.7 MiB 11.88 180137 61714 223520 36703 169137 17680 1216.3 MiB 10.63 0.16 5.41016 4.96403 -5546.44 -3.96403 2.84288 0.01 0.0440263 0.0385965 3.36781 2.8222 75346 6.05821 18897 1.51942 26061 36573 12725206 1711712 0 0 2.60031e+07 21349.0 14 354380 4692432 -1 5.08769 2.56235 -5100.1 -4.08769 0 0 7.77 -1 -1 1216.3 MiB 4.84 5.1781 4.41964 1216.3 MiB -1 1.92 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_per_layer_bb 58.79 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245324 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.5 MiB 11.84 186170 63157 219808 34278 166444 19086 1216.1 MiB 10.25 0.14 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.01 0.0422071 0.0368357 2.98723 2.48631 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 9.89 -1 -1 1216.1 MiB 4.79 4.83395 4.11932 1216.1 MiB -1 1.80 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt index 5e82ce20db9..abc45194ec7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 2.06 vpr 70.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71744 130 150 1169 1319 1 886 363 12 12 144 clb auto 29.9 MiB 1.33 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00617255 0.00566712 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 2.11 vpr 69.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71096 130 150 1216 1366 1 933 370 12 12 144 clb auto 29.7 MiB 1.36 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00673229 0.00602451 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 2.31 vpr 72.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74048 130 150 1169 1319 1 886 363 12 12 144 clb auto 32.2 MiB 1.59 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00628067 0.00572957 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.95 vpr 72.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73772 130 150 1216 1366 1 933 370 12 12 144 clb auto 32.4 MiB 1.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00606424 0.00546366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt index e7e15672aec..94e710b87f5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.59 vpr 63.68 MiB -1 -1 0.88 23332 5 0.19 -1 -1 33328 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65204 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.13 146 398 72 298 28 63.7 MiB 0.05 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.00056264 0.000520569 0.00752147 0.00699209 -1 -1 -1 -1 130 4.06250 54 1.68750 215 509 15144 2919 646728 646728 138825. 3856.24 24 3164 19284 -1 2.05191 2.05191 -93.8814 -2.05191 0 0 0.02 -1 -1 63.7 MiB 0.05 0.0383425 0.0343799 63.7 MiB -1 0.02 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.12 vpr 66.62 MiB -1 -1 0.87 22944 4 0.17 -1 -1 33248 -1 -1 15 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68220 11 2 303 283 2 78 28 7 7 49 clb auto 27.0 MiB 0.35 264 1036 209 767 60 66.6 MiB 0.05 0.00 2.03811 -163.536 -2.03811 1.90043 0.00 0.000979369 0.000882501 0.0285292 0.0262389 -1 -1 -1 -1 252 3.50000 103 1.43056 122 199 4265 1218 1.07788e+06 808410 219490. 4479.39 12 5100 32136 -1 2.11264 1.93889 -160.659 -2.11264 0 0 0.04 -1 -1 66.6 MiB 0.04 0.0622 0.0573011 66.6 MiB -1 0.05 + k6_N10_mem32K_40nm.xml stereovision3.v common 2.05 vpr 66.01 MiB -1 -1 0.86 26896 5 0.23 -1 -1 36624 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67592 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 152 432 67 335 30 66.0 MiB 0.02 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000412775 0.000360271 0.0136111 0.012803 -1 -1 -1 -1 138 4.31250 57 1.78125 181 343 11634 2077 646728 646728 138825. 3856.24 15 3164 19284 -1 2.14648 2.14648 -94.9192 -2.14648 0 0 0.04 -1 -1 66.0 MiB 0.03 0.0339384 0.0288063 66.0 MiB -1 0.00 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.21 vpr 69.14 MiB -1 -1 0.76 26288 4 0.18 -1 -1 36060 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70796 11 2 303 283 2 78 28 7 7 49 clb auto 29.6 MiB 0.27 285 784 175 539 70 69.1 MiB 0.05 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000707376 0.000615193 0.0194274 0.0173585 -1 -1 -1 -1 313 4.34722 112 1.55556 114 177 3842 1019 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.07112 1.86791 -165.31 -2.07112 0 0 0.05 -1 -1 69.1 MiB 0.03 0.0450009 0.0414951 69.1 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt index 36eb5abce3a..7f41d46c079 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 5.66 vpr 65.89 MiB -1 -1 0.43 18980 3 0.13 -1 -1 33368 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67472 99 130 344 474 1 227 298 12 12 144 clb auto 26.1 MiB 0.26 783 1293 269 877 147 65.9 MiB 0.17 0.00 1.86362 -117.589 -1.86362 1.86362 0.38 0.00100487 0.000938659 0.00647195 0.00625967 -1 -1 -1 -1 34 1729 21 5.66058e+06 4.21279e+06 293002. 2034.74 1.97 0.304859 0.274689 12094 55633 -1 1447 11 494 759 44038 15434 1.98889 1.98889 -143.496 -1.98889 -0.113193 -0.0844279 360780. 2505.42 0.12 0.08 0.06 -1 -1 0.12 0.0336886 0.0313908 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.75 vpr 67.64 MiB -1 -1 0.42 22416 3 0.08 -1 -1 36896 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69264 99 130 344 474 1 227 298 12 12 144 clb auto 28.8 MiB 0.22 846 1293 248 869 176 67.6 MiB 0.10 0.00 1.87518 -117.076 -1.87518 1.87518 0.33 0.000961535 0.000869555 0.00580355 0.00550747 -1 -1 -1 -1 38 1541 12 5.66058e+06 4.21279e+06 319130. 2216.18 1.43 0.231487 0.210357 12522 62564 -1 1321 9 430 670 30619 10041 1.9175 1.9175 -131.199 -1.9175 -0.126268 -0.104429 406292. 2821.48 0.02 0.04 0.09 -1 -1 0.02 0.0283489 0.0264305 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/config.txt new file mode 100644 index 00000000000..a8e217b51fd --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_detailed_placer annealer --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt new file mode 100644 index 00000000000..f90dc9de594 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.63 vpr 75.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77436 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.6 MiB 3.56 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00332256 0.00272635 0.0920151 0.0793873 75.6 MiB 3.56 75.6 MiB 2.42 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.33 -1 -1 75.6 MiB 0.47 0.288973 0.25613 75.6 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.81 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78036 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.93 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00365979 0.00331889 0.047619 0.043593 76.2 MiB 0.93 76.2 MiB 0.59 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.37 -1 -1 76.2 MiB 0.25 0.188446 0.174077 76.2 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 11.93 vpr 105.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108360 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.8 MiB 9.23 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.16 0.00660438 0.00519941 0.309592 0.257376 105.8 MiB 9.23 105.8 MiB 4.50 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.18 -1 -1 105.8 MiB 0.93 0.709043 0.615207 105.8 MiB -1 0.16 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.73 vpr 76.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78628 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.8 MiB 3.59 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.09 0.0040653 0.00347069 0.103188 0.0899686 76.8 MiB 3.59 76.8 MiB 2.31 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.37 -1 -1 76.8 MiB 0.47 0.321818 0.287107 76.8 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/config.txt new file mode 100644 index 00000000000..358e9022f78 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_full_legalizer appack --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt new file mode 100644 index 00000000000..91c3630a8a8 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.88 vpr 75.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77168 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.4 MiB 3.73 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00371221 0.00305644 0.097355 0.0840965 75.4 MiB 3.73 75.4 MiB 2.65 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.34 -1 -1 75.4 MiB 0.50 0.299102 0.265267 75.4 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.04 vpr 75.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77776 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.0 MiB 1.04 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00356373 0.00322411 0.0543939 0.0472155 76.0 MiB 1.04 76.0 MiB 0.69 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.39 -1 -1 76.0 MiB 0.32 0.22263 0.205375 76.0 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 14.50 vpr 105.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108280 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.7 MiB 11.89 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.16 0.0066784 0.00535245 0.30231 0.252682 105.7 MiB 11.89 105.7 MiB 7.07 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.11 -1 -1 105.7 MiB 0.94 0.707357 0.615217 105.7 MiB -1 0.16 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.83 vpr 76.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78264 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.4 MiB 3.68 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.11 0.00384755 0.00327555 0.103123 0.0900634 76.4 MiB 3.68 76.4 MiB 2.39 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.4 MiB 0.48 0.323332 0.288275 76.4 MiB -1 0.11 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/config.txt new file mode 100644 index 00000000000..914133ac93b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_partial_legalizer bipartitioning --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt new file mode 100644 index 00000000000..e03594be3ed --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.66 vpr 75.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77168 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.4 MiB 3.54 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00377685 0.0031064 0.0971738 0.0840095 75.4 MiB 3.54 75.4 MiB 2.44 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.35 -1 -1 75.4 MiB 0.49 0.299893 0.266532 75.4 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.87 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78040 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.95 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.12 0.00361228 0.00324116 0.0472811 0.0432415 76.2 MiB 0.95 76.2 MiB 0.63 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.40 -1 -1 76.2 MiB 0.27 0.192439 0.178374 76.2 MiB -1 0.12 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 15.92 vpr 105.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108344 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.8 MiB 13.27 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.27 0.0064285 0.00513075 0.474187 0.399734 105.8 MiB 13.27 105.8 MiB 7.54 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.15 -1 -1 105.8 MiB 0.91 0.870133 0.753188 105.8 MiB -1 0.27 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.70 vpr 76.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78576 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.7 MiB 3.57 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.10 0.00387961 0.00328771 0.108944 0.0952913 76.7 MiB 3.57 76.7 MiB 2.29 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.32 -1 -1 76.7 MiB 0.51 0.337895 0.301103 76.7 MiB -1 0.10 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/config.txt new file mode 100644 index 00000000000..75c1001ec87 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_partial_legalizer flow-based --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt new file mode 100644 index 00000000000..260e0e2c056 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 11.76 vpr 75.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77216 9 19 897 28 0 575 109 16 16 256 -1 mcnc_medium -1 -1 7102 6246 3749 356 2360 1033 75.4 MiB 10.60 0.01 5.59875 5.15754 -83.6777 -5.15754 nan 0.09 0.00367809 0.00303729 0.0800582 0.0701494 75.4 MiB 10.60 75.4 MiB 2.58 9765 17.0122 2613 4.55226 4147 20677 658214 114215 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.35541 nan -88.358 -5.35541 0 0 0.32 -1 -1 75.4 MiB 0.48 0.288075 0.253539 75.4 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.95 vpr 76.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 57 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77892 256 245 954 501 0 585 558 22 22 484 -1 mcnc_large -1 -1 7568 7468 23518 202 3225 20091 76.1 MiB 1.06 0.02 4.58215 4.06321 -789.076 -4.06321 nan 0.17 0.00395794 0.00352194 0.0546633 0.0494666 76.1 MiB 1.06 76.1 MiB 0.64 10448 17.8598 2871 4.90769 2610 5820 337031 73978 2.15576e+07 3.07196e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.29926 nan -860.162 -4.29926 0 0 0.37 -1 -1 76.1 MiB 0.29 0.21912 0.199431 76.1 MiB -1 0.17 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 34.79 vpr 105.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 284 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108284 10 10 2659 20 0 1371 304 22 22 484 -1 mcnc_large -1 -1 32736 26176 50333 12484 33100 4749 105.7 MiB 32.12 0.02 8.62387 6.83404 -65.9282 -6.83404 nan 0.15 0.0053571 0.00415525 0.333874 0.272699 105.7 MiB 32.12 105.7 MiB 4.39 39078 28.5033 10004 7.29686 9032 54400 2294214 310826 2.15576e+07 1.53059e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.03175 nan -67.1956 -7.03175 0 0 1.19 -1 -1 105.7 MiB 0.86 0.709263 0.607527 105.7 MiB -1 0.15 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 12.51 vpr 76.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78100 41 35 1006 76 0 566 161 16 16 256 -1 mcnc_medium -1 -1 7257 6649 5842 273 2922 2647 76.3 MiB 11.37 0.02 5.58018 4.9431 -137.944 -4.9431 nan 0.09 0.00696141 0.00638215 0.115593 0.094552 76.3 MiB 11.37 76.3 MiB 2.39 10043 17.7438 2739 4.83922 3885 20440 636556 113525 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.06598 nan -144.027 -5.06598 0 0 0.35 -1 -1 76.3 MiB 0.47 0.340764 0.297617 76.3 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/config.txt new file mode 100644 index 00000000000..48b5feea72d --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --route --ap_analytical_solver lp-b2b + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt new file mode 100644 index 00000000000..e9dd4dbf472 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.77 vpr 75.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77552 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.7 MiB 3.65 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00374471 0.00311178 0.0942637 0.0815881 75.7 MiB 3.65 75.7 MiB 2.54 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.34 -1 -1 75.7 MiB 0.49 0.296978 0.264335 75.7 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.88 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78040 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.98 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.14 0.0035648 0.00318679 0.0499558 0.0460383 76.2 MiB 0.98 76.2 MiB 0.63 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.38 -1 -1 76.2 MiB 0.27 0.197871 0.183716 76.2 MiB -1 0.14 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 16.47 vpr 105.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108040 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.5 MiB 12.86 0.04 9.04847 6.65923 -63.8387 -6.65923 nan 0.29 0.0116739 0.00965721 0.534688 0.455619 105.5 MiB 12.86 105.5 MiB 7.17 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.12 -1 -1 105.5 MiB 1.62 1.25142 1.10117 105.5 MiB -1 0.28 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.88 vpr 76.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78644 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.8 MiB 3.64 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.10 0.00418085 0.00352692 0.113479 0.0974767 76.8 MiB 3.64 76.8 MiB 2.34 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.8 MiB 0.56 0.365085 0.323172 76.8 MiB -1 0.10 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt index 97f45b6c51f..c179a99eb71 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 17.89 vpr 72.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 113 9 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 74000 9 19 897 28 0 861 141 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 72.3 MiB 7.61 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72.3 MiB 7.61 72.3 MiB 1.79 15611 18.1735 4293 4.99767 8307 35569 1513043 269803 1.05632e+07 6.09002e+06 1.26944e+06 4958.75 25 28900 206586 -1 6.2156 nan -103.761 -6.2156 0 0 0.25 -1 -1 72.3 MiB 0.57 0.174543 0.155743 72.3 MiB -1 0.31 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 5.93 vpr 73.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 168 256 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 75248 256 245 954 501 0 934 669 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 73.5 MiB 1.37 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 73.5 MiB 1.37 73.5 MiB 1.31 14674 15.7109 3946 4.22484 4204 10388 463073 94185 2.15576e+07 9.05419e+06 1.49107e+06 3080.73 15 47664 245996 -1 5.16547 nan -949.23 -5.16547 0 0 0.24 -1 -1 73.5 MiB 0.33 0.134699 0.127277 73.5 MiB -1 0.78 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 89.28 vpr 101.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 378 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 104144 10 10 2659 20 0 2595 398 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 101.7 MiB 38.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 101.7 MiB 38.46 101.7 MiB 4.76 69814 26.9033 18438 7.10520 21388 82112 8636123 1705637 2.15576e+07 2.03719e+07 3.51389e+06 7260.09 30 64568 594370 -1 8.65166 nan -83.0393 -8.65166 0 0 0.78 -1 -1 101.7 MiB 2.76 0.603303 0.529989 101.7 MiB -1 0.89 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 18.93 vpr 73.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 137 41 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 75200 41 35 1006 76 0 966 213 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 73.4 MiB 7.75 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 73.4 MiB 7.75 73.4 MiB 2.26 16234 16.8054 4428 4.58385 7333 31283 1130829 193699 1.05632e+07 7.38348e+06 1.26944e+06 4958.75 18 28900 206586 -1 6.06719 nan -179.594 -6.06719 0 0 0.29 -1 -1 73.4 MiB 0.59 0.225217 0.206578 73.4 MiB -1 0.44 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.02 vpr 75.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77392 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.6 MiB 3.80 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.10 0.00366255 0.00300248 0.0988722 0.0856346 75.6 MiB 3.80 75.6 MiB 2.67 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.33 -1 -1 75.6 MiB 0.58 0.329873 0.296269 75.6 MiB -1 0.10 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.88 vpr 76.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77908 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.1 MiB 0.98 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00361625 0.00323438 0.0481778 0.0440548 76.1 MiB 0.98 76.1 MiB 0.62 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.38 -1 -1 76.1 MiB 0.27 0.193703 0.179342 76.1 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 16.93 vpr 105.69 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108228 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.7 MiB 13.43 0.04 9.04847 6.65923 -63.8387 -6.65923 nan 0.25 0.0114469 0.00942196 0.523317 0.437298 105.7 MiB 13.43 105.7 MiB 7.67 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.08 -1 -1 105.7 MiB 1.54 1.21056 1.05802 105.7 MiB -1 0.25 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.95 vpr 76.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78780 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.9 MiB 3.70 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.11 0.00501429 0.0044287 0.113755 0.0975648 76.9 MiB 3.70 76.9 MiB 2.39 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.9 MiB 0.54 0.357802 0.31714 76.9 MiB -1 0.11 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/config.txt new file mode 100644 index 00000000000..dbc8f9dcd38 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_full_legalizer naive --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt new file mode 100644 index 00000000000..5bcf12189e9 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.03 vpr 75.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 114 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77596 9 19 897 28 0 606 142 16 16 256 -1 mcnc_medium -1 -1 6550 6536 3472 155 2648 669 75.8 MiB 3.88 0.01 5.7154 5.4597 -89.3112 -5.4597 nan 0.10 0.00370216 0.00307222 0.0661479 0.0591146 75.8 MiB 3.88 75.8 MiB 2.88 10481 17.3240 2782 4.59835 4539 23483 740476 125213 1.05632e+07 6.14392e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.72947 nan -94.1462 -5.72947 0 0 0.32 -1 -1 75.8 MiB 0.50 0.310788 0.282654 75.8 MiB -1 0.10 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 3.32 vpr 76.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 179 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78468 256 245 954 501 0 742 680 22 22 484 -1 mcnc_large -1 -1 9274 7572 60460 2284 20333 37843 76.6 MiB 2.36 0.02 5.23911 4.2903 -840.323 -4.2903 nan 0.13 0.00384619 0.00344153 0.09353 0.0842417 76.6 MiB 2.36 76.6 MiB 1.70 11049 14.8908 3078 4.14825 2733 6987 297544 68761 2.15576e+07 9.64703e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.65189 nan -884.263 -4.65189 0 0 0.41 -1 -1 76.6 MiB 0.28 0.244915 0.224675 76.6 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 18.12 vpr 106.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108712 10 10 2659 20 0 1430 382 22 22 484 -1 mcnc_large -1 -1 30097 26681 50242 8485 37651 4106 106.2 MiB 14.49 0.06 9.5895 7.11784 -67.5602 -7.11784 nan 0.29 0.0120588 0.0101618 0.577448 0.487406 106.2 MiB 14.49 106.2 MiB 8.21 40770 28.5105 10462 7.31608 8938 61030 2640427 332495 2.15576e+07 1.95096e+07 3.51389e+06 7260.09 17 64568 594370 -1 7.68543 nan -70.9452 -7.68543 0 0 1.09 -1 -1 106.2 MiB 1.70 1.23429 1.08029 106.2 MiB -1 0.29 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.65 vpr 76.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 124 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78780 41 35 1006 76 0 665 200 16 16 256 -1 mcnc_medium -1 -1 8699 7144 11296 577 6471 4248 76.9 MiB 4.33 0.02 6.42009 5.14527 -151.192 -5.14527 nan 0.09 0.0040038 0.00343256 0.111382 0.0964207 76.9 MiB 4.33 76.9 MiB 3.06 11808 17.7564 3134 4.71278 5035 27959 918932 152826 1.05632e+07 6.68286e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.4847 nan -160.203 -5.4847 0 0 0.34 -1 -1 76.9 MiB 0.64 0.362116 0.322037 76.9 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/config.txt new file mode 100755 index 00000000000..7678dea6b00 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/config.txt @@ -0,0 +1,51 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=boundtop.v +circuit_list_add=ch_intrinsics.v +circuit_list_add=or1200.v +circuit_list_add=spree.v +circuit_list_add=stereovision3.v + +# Constrain the circuits to their devices +circuit_constraint_list_add=(stereovision3.v, device=vtr_extra_small) +circuit_constraint_list_add=(ch_intrinsics.v, device=vtr_extra_small) +circuit_constraint_list_add=(spree.v, device=vtr_extra_small) +circuit_constraint_list_add=(boundtop.v, device=vtr_extra_small) +circuit_constraint_list_add=(or1200.v, device=vtr_small) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(stereovision3.v, route_chan_width=44) +circuit_constraint_list_add=(ch_intrinsics.v, route_chan_width=52) +circuit_constraint_list_add=(spree.v, route_chan_width=78) +circuit_constraint_list_add=(boundtop.v, route_chan_width=50) +circuit_constraint_list_add=(or1200.v, route_chan_width=118) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-track_memory_usage -crit_path_router_iterations 100 --analytical_place --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt new file mode 100644 index 00000000000..e8dd91ee6ae --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt @@ -0,0 +1,6 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 25.85 vpr 83.03 MiB -1 -1 18.57 47636 3 1.01 -1 -1 38980 -1 -1 48 196 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 85020 196 193 800 0 1 594 438 20 20 400 -1 vtr_extra_small -1 -1 4169 3142 106806 24519 69152 13135 83.0 MiB 3.45 0.01 2.78642 2.3599 -1119.38 -2.3599 2.3599 0.11 0.00336886 0.00290601 0.267623 0.235425 83.0 MiB 3.45 83.0 MiB 1.54 5164 8.82735 1542 2.63590 1808 2713 166829 48700 2.07112e+07 3.13491e+06 1.26946e+06 3173.65 11 38988 203232 -1 2.79177 2.79177 -1205.37 -2.79177 0 0 0.33 -1 -1 83.0 MiB 0.20 0.427611 0.384897 83.0 MiB -1 0.11 + k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.71 vpr 77.02 MiB -1 -1 0.44 22136 3 0.13 -1 -1 37044 -1 -1 68 99 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78864 99 130 264 0 1 227 298 20 20 400 -1 vtr_extra_small -1 -1 1534 732 61988 20558 27121 14309 77.0 MiB 1.17 0.01 1.84094 1.63182 -117.029 -1.63182 1.63182 0.10 0.00116098 0.00102609 0.0719437 0.0636329 77.0 MiB 1.17 77.0 MiB 0.48 1289 7.67262 408 2.42857 432 671 35594 10787 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 12 39388 210115 -1 2.0326 2.0326 -137.711 -2.0326 0 0 0.32 -1 -1 77.0 MiB 0.12 0.146262 0.115522 77.0 MiB -1 0.10 + k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 45.09 vpr 132.19 MiB -1 -1 6.50 65292 8 5.27 -1 -1 44656 -1 -1 246 385 2 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 135364 385 362 3324 0 1 2378 996 30 30 900 -1 vtr_small -1 -1 45961 31243 503168 167206 308523 27439 132.2 MiB 27.49 0.08 11.3485 9.24445 -10104.3 -9.24445 9.24445 0.52 0.0110533 0.00983869 1.90464 1.67809 132.2 MiB 27.49 132.2 MiB 14.11 42437 17.9590 11048 4.67541 10359 33405 1843617 333376 4.8774e+07 1.47499e+07 6.56785e+06 7297.61 17 120772 1084977 -1 9.50495 9.50495 -10508.2 -9.50495 0 0 2.27 -1 -1 132.2 MiB 0.99 2.49904 2.2274 132.2 MiB -1 0.52 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 13.73 vpr 86.61 MiB -1 -1 3.85 35472 16 0.66 -1 -1 39332 -1 -1 61 45 3 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 88684 45 32 936 0 1 764 142 20 20 400 -1 vtr_extra_small -1 -1 7941 6580 16792 4505 10418 1869 86.6 MiB 7.12 0.02 11.8934 10.8778 -6730.96 -10.8778 10.8778 0.15 0.00604523 0.0052746 0.299411 0.249607 86.6 MiB 7.12 86.6 MiB 4.84 11265 14.8029 2859 3.75690 3304 9224 705116 168424 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 16 44576 305072 -1 11.1238 11.1238 -7296.13 -11.1238 0 0 0.55 -1 -1 86.6 MiB 0.49 0.557197 0.483674 86.6 MiB -1 0.15 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.92 vpr 76.71 MiB -1 -1 0.85 26400 4 0.19 -1 -1 36732 -1 -1 15 11 0 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78556 11 2 140 0 2 80 28 20 20 400 -1 vtr_extra_small -1 -1 371 277 994 274 621 99 76.7 MiB 0.79 0.00 2.14417 2.10685 -170.205 -2.10685 1.95087 0.09 0.000829747 0.000696435 0.0253099 0.0218497 76.7 MiB 0.79 76.7 MiB 0.47 484 6.54054 125 1.68919 154 271 5642 1534 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.24362 1.99822 -177.023 -2.24362 0 0 0.28 -1 -1 76.7 MiB 0.04 0.058266 0.0520206 76.7 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/config.txt new file mode 100644 index 00000000000..bb79ed9f837 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif +# circuit_list_add=ex1010.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +# circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +# circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +# circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_detailed_placer none --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt new file mode 100644 index 00000000000..9155e1a0c29 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt @@ -0,0 +1,4 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.37 vpr 75.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77532 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 75.7 MiB 3.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.7 MiB 3.24 75.7 MiB 2.52 10470 18.5638 2823 5.00532 4441 21451 721238 120368 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.44204 nan -88.1999 -5.44204 0 0 0.32 -1 -1 75.7 MiB 0.45 0.190621 0.172257 75.7 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.70 vpr 76.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78028 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 -1 76.2 MiB 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 76.2 MiB 0.69 76.2 MiB 0.61 10067 17.2380 2785 4.76884 2224 4785 262051 58317 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 14 47664 245996 -1 5.09713 nan -915.356 -5.09713 0 0 0.38 -1 -1 76.2 MiB 0.25 0.146815 0.136123 76.2 MiB -1 0.13 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.28 vpr 76.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78496 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 76.7 MiB 3.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 76.7 MiB 3.09 76.7 MiB 2.27 10759 18.7766 2936 5.12391 3972 20025 643838 113062 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.52727 nan -151.75 -5.52727 0 0 0.34 -1 -1 76.7 MiB 0.46 0.206081 0.184898 76.7 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/config.txt new file mode 100644 index 00000000000..8e0fbf318b0 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --route --ap_analytical_solver qp-hybrid + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt new file mode 100644 index 00000000000..bd1a356f7b3 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.48 vpr 75.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 79 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77452 9 19 897 28 0 613 107 16 16 256 -1 mcnc_medium -1 -1 7227 6446 4661 444 2922 1295 75.6 MiB 3.30 0.01 5.83587 5.20235 -84.7514 -5.20235 nan 0.09 0.00365365 0.00308713 0.0953072 0.0828485 75.6 MiB 3.30 75.6 MiB 2.61 9964 16.2810 2709 4.42647 4690 20859 701687 124089 1.05632e+07 4.25763e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.47836 nan -87.8661 -5.47836 0 0 0.35 -1 -1 75.6 MiB 0.51 0.314162 0.28034 75.6 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.82 vpr 76.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78032 256 245 954 501 0 598 557 22 22 484 -1 mcnc_large -1 -1 8430 8247 28037 277 4264 23496 76.2 MiB 0.95 0.02 5.00844 4.05195 -786.983 -4.05195 nan 0.13 0.00372964 0.0033122 0.0643989 0.0586623 76.2 MiB 0.95 76.2 MiB 0.58 10883 18.1990 2937 4.91137 2442 5565 332488 69751 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 12 47664 245996 -1 4.40791 nan -837.951 -4.40791 0 0 0.37 -1 -1 76.2 MiB 0.26 0.206289 0.19121 76.2 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 15.95 vpr 105.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108108 10 10 2659 20 0 1500 308 22 22 484 -1 mcnc_large -1 -1 33647 26777 51219 12453 33951 4815 105.6 MiB 12.21 0.05 7.95426 6.65363 -64.7441 -6.65363 nan 0.32 0.01158 0.00952696 0.683148 0.577318 105.6 MiB 12.21 105.6 MiB 8.23 39550 26.3667 10138 6.75867 10136 56388 2554636 337283 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.10986 nan -67.2122 -7.10986 0 0 1.12 -1 -1 105.6 MiB 1.79 1.41673 1.23449 105.6 MiB -1 0.32 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 3.96 vpr 76.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78624 41 35 1006 76 0 665 161 16 16 256 -1 mcnc_medium -1 -1 7612 6958 7590 343 3947 3300 76.8 MiB 2.84 0.02 6.23108 5.15201 -145.389 -5.15201 nan 0.09 0.00454121 0.00387629 0.099122 0.086103 76.8 MiB 2.84 76.8 MiB 2.13 10685 16.0677 2885 4.33835 4384 18462 592965 106217 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.45169 nan -154.246 -5.45169 0 0 0.32 -1 -1 76.8 MiB 0.51 0.354223 0.314944 76.8 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/config.txt new file mode 100644 index 00000000000..a45e6a65de4 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --route --allow_unrelated_clustering on + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt new file mode 100644 index 00000000000..353d272ff5e --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.96 vpr 75.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77136 9 19 897 28 0 571 109 16 16 256 -1 mcnc_medium -1 -1 6849 6197 3749 306 2447 996 75.3 MiB 3.80 0.01 5.6777 5.15854 -84.4388 -5.15854 nan 0.12 0.00372518 0.00308527 0.0851251 0.0744623 75.3 MiB 3.80 75.3 MiB 2.72 9547 16.7491 2591 4.54561 4007 19117 612422 105847 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.57046 nan -89.3939 -5.57046 0 0 0.36 -1 -1 75.3 MiB 0.45 0.290389 0.260271 75.3 MiB -1 0.12 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.92 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78044 256 245 954 501 0 584 556 22 22 484 -1 mcnc_large -1 -1 7414 7336 16551 117 1750 14684 76.2 MiB 0.96 0.02 4.79868 3.95956 -780.296 -3.95956 nan 0.14 0.0037776 0.00334019 0.0431145 0.0394451 76.2 MiB 0.96 76.2 MiB 0.63 10156 17.3904 2785 4.76884 2499 5829 309976 67350 2.15576e+07 2.96417e+06 1.49107e+06 3080.73 17 47664 245996 -1 4.43922 nan -858.538 -4.43922 0 0 0.40 -1 -1 76.2 MiB 0.31 0.225991 0.20914 76.2 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 18.50 vpr 105.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 263 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108088 10 10 2659 20 0 1335 283 22 22 484 -1 mcnc_large -1 -1 29142 24368 34619 6112 24966 3541 105.6 MiB 14.79 0.04 8.99039 6.64595 -64.2305 -6.64595 nan 0.30 0.011351 0.00921126 0.534655 0.453947 105.6 MiB 14.79 105.6 MiB 8.92 36909 27.6472 9531 7.13933 8973 57196 2436221 318880 2.15576e+07 1.41741e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.07899 nan -66.0192 -7.07899 0 0 1.11 -1 -1 105.6 MiB 1.75 1.29851 1.13315 105.6 MiB -1 0.30 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.12 vpr 76.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78196 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7414 6419 7538 405 3643 3490 76.4 MiB 3.99 0.01 5.66659 5.10396 -142.048 -5.10396 nan 0.09 0.00395858 0.00331812 0.0974473 0.0845959 76.4 MiB 3.99 76.4 MiB 2.72 9920 17.3124 2710 4.72949 3957 20035 633461 111527 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.31293 nan -148.764 -5.31293 0 0 0.36 -1 -1 76.4 MiB 0.47 0.311907 0.278187 76.4 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/config.txt index 2f77b824751..f5bbc150963 100755 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/config.txt @@ -18,7 +18,7 @@ arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml # Add circuits to list to sweep circuit_list_add=boundtop.v circuit_list_add=ch_intrinsics.v -circuit_list_add=or1200.v +# circuit_list_add=or1200.v circuit_list_add=spree.v circuit_list_add=stereovision3.v @@ -27,14 +27,14 @@ circuit_constraint_list_add=(stereovision3.v, device=vtr_extra_small) circuit_constraint_list_add=(ch_intrinsics.v, device=vtr_extra_small) circuit_constraint_list_add=(spree.v, device=vtr_extra_small) circuit_constraint_list_add=(boundtop.v, device=vtr_extra_small) -circuit_constraint_list_add=(or1200.v, device=vtr_small) +# circuit_constraint_list_add=(or1200.v, device=vtr_small) # Constrain the IOs circuit_constraint_list_add=(stereovision3.v, constraints=../../../../constraints/stereovision3_io_constraint.xml) circuit_constraint_list_add=(ch_intrinsics.v, constraints=../../../../constraints/ch_intrinsics_io_constraint.xml) circuit_constraint_list_add=(spree.v, constraints=../../../../constraints/spree_io_constraint.xml) circuit_constraint_list_add=(boundtop.v, constraints=../../../../constraints/boundtop_io_constraint.xml) -circuit_constraint_list_add=(or1200.v, constraints=../../../../constraints/or1200_io_constraint.xml) +# circuit_constraint_list_add=(or1200.v, constraints=../../../../constraints/or1200_io_constraint.xml) # Constrain the circuits to their channel widths # 1.3 * minW @@ -42,7 +42,7 @@ circuit_constraint_list_add=(stereovision3.v, route_chan_width=44) circuit_constraint_list_add=(ch_intrinsics.v, route_chan_width=52) circuit_constraint_list_add=(spree.v, route_chan_width=78) circuit_constraint_list_add=(boundtop.v, route_chan_width=50) -circuit_constraint_list_add=(or1200.v, route_chan_width=118) +# circuit_constraint_list_add=(or1200.v, route_chan_width=118) # Parse info and how to parse parse_file=vpr_fixed_chan_width.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt index 01136ed182a..d7bb035e33d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt @@ -1,6 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 25.49 vpr 80.19 MiB -1 -1 18.42 46348 3 0.86 -1 -1 35680 -1 -1 79 196 2 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 82116 196 193 800 389 1 770 470 20 20 400 -1 vtr_extra_small -1 -1 -1 -1 -1 -1 -1 80.2 MiB 1.84 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80.2 MiB 1.84 80.2 MiB 1.78 9940 13.0618 2693 3.53876 2581 4860 309537 77921 2.07112e+07 5.35363e+06 1.26946e+06 3173.65 17 38988 203232 -1 3.97958 3.97958 -1577.97 -3.97958 0 0 0.21 -1 -1 80.2 MiB 0.27 0.168973 0.157491 80.2 MiB -1 0.35 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 4.99 vpr 74.65 MiB -1 -1 0.39 19048 3 0.16 -1 -1 33328 -1 -1 43 99 4 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76440 99 130 240 229 1 245 276 20 20 400 -1 vtr_extra_small -1 -1 -1 -1 -1 -1 -1 74.6 MiB 0.74 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 74.6 MiB 0.74 74.6 MiB 0.55 2337 12.5645 646 3.47312 478 786 47927 11655 2.07112e+07 4.50944e+06 1.31074e+06 3276.84 17 39388 210115 -1 2.7949 2.7949 -157.904 -2.7949 0 0 0.23 -1 -1 74.6 MiB 0.08 0.0477832 0.0442404 74.6 MiB -1 0.59 - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 98.01 vpr 129.75 MiB -1 -1 6.86 63268 8 3.92 -1 -1 41140 -1 -1 389 385 4 1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 132868 385 362 3324 747 1 3234 1141 30 30 900 -1 vtr_small -1 -1 -1 -1 -1 -1 -1 129.8 MiB 36.86 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 129.8 MiB 36.86 129.8 MiB 7.32 78006 24.2330 20094 6.24231 16800 53011 4072067 673498 4.8774e+07 2.35528e+07 6.56785e+06 7297.61 18 120772 1084977 -1 13.1891 13.1891 -14048.3 -13.1891 0 0 1.37 -1 -1 129.8 MiB 1.69 0.748616 0.698526 129.8 MiB -1 1.67 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 34.66 vpr 83.23 MiB -1 -1 3.83 32732 16 0.61 -1 -1 34984 -1 -1 81 45 5 1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 85228 45 32 936 77 1 909 164 20 20 400 -1 vtr_extra_small -1 -1 -1 -1 -1 -1 -1 83.2 MiB 12.99 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83.2 MiB 12.99 83.2 MiB 3.72 18303 20.2020 4779 5.27483 4457 12845 1130075 256506 2.07112e+07 7.50141e+06 1.91495e+06 4787.38 16 44576 305072 -1 16.4662 16.4662 -8382.09 -16.4662 0 0 0.35 -1 -1 83.2 MiB 0.43 0.172284 0.155775 83.2 MiB -1 0.53 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 5.78 vpr 73.51 MiB -1 -1 0.88 22948 4 0.18 -1 -1 33064 -1 -1 20 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 75272 11 2 140 13 2 126 33 20 20 400 -1 vtr_extra_small -1 -1 -1 -1 -1 -1 -1 73.5 MiB 0.89 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 73.5 MiB 0.89 73.5 MiB 0.66 927 7.72500 248 2.06667 341 586 12691 3249 2.07112e+07 1.07788e+06 1.12964e+06 2824.09 11 37792 180905 -1 2.27141 2.21904 -192.145 -2.27141 0 0 0.21 -1 -1 73.5 MiB 0.04 0.0291693 0.0268442 73.5 MiB -1 0.47 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 24.78 vpr 83.23 MiB -1 -1 18.50 47880 3 1.03 -1 -1 38848 -1 -1 50 196 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 85228 196 193 800 389 1 591 440 20 20 400 -1 vtr_extra_small -1 -1 3715 3554 3784 38 823 2923 83.2 MiB 2.24 0.02 2.85588 2.57265 -1175.96 -2.57265 2.57265 0.10 0.00362627 0.00313967 0.0281499 0.026191 83.2 MiB 2.24 83.2 MiB 1.59 5468 9.39519 1600 2.74914 1643 2642 175568 48502 2.07112e+07 3.2427e+06 1.26946e+06 3173.65 13 38988 203232 -1 2.92546 2.92546 -1279.3 -2.92546 0 0 0.33 -1 -1 83.2 MiB 0.23 0.194282 0.17603 83.2 MiB -1 0.10 + k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.30 vpr 77.05 MiB -1 -1 0.46 21648 3 0.11 -1 -1 36796 -1 -1 69 99 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78904 99 130 240 229 1 219 299 20 20 400 -1 vtr_extra_small -1 -1 897 855 16283 1900 1766 12617 77.1 MiB 0.85 0.01 1.95754 1.93615 -150.064 -1.93615 1.93615 0.10 0.00114824 0.00101953 0.0225391 0.0202679 77.1 MiB 0.85 77.1 MiB 0.55 1415 8.84375 420 2.62500 390 656 29567 8292 2.07112e+07 4.26669e+06 1.31074e+06 3276.84 10 39388 210115 -1 1.99132 1.99132 -170.793 -1.99132 0 0 0.34 -1 -1 77.1 MiB 0.05 0.0576019 0.0526431 77.1 MiB -1 0.10 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 12.74 vpr 86.56 MiB -1 -1 3.84 35864 16 0.69 -1 -1 39076 -1 -1 61 45 3 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 88636 45 32 936 77 1 765 142 20 20 400 -1 vtr_extra_small -1 -1 7990 6993 2362 101 1016 1245 86.6 MiB 6.20 0.02 12.1921 10.5297 -7133.55 -10.5297 10.5297 0.16 0.00556384 0.00434574 0.083545 0.0720334 86.6 MiB 6.20 86.6 MiB 4.77 11420 14.9869 2979 3.90945 3498 9480 737557 180691 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 14 44576 305072 -1 10.8282 10.8282 -7490.44 -10.8282 0 0 0.55 -1 -1 86.6 MiB 0.48 0.322984 0.290732 86.6 MiB -1 0.16 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.69 vpr 76.73 MiB -1 -1 0.87 26256 4 0.17 -1 -1 36604 -1 -1 15 11 0 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78576 11 2 140 13 2 79 28 20 20 400 -1 vtr_extra_small -1 -1 425 276 658 98 289 271 76.7 MiB 0.68 0.00 2.38519 2.10685 -169.375 -2.10685 1.95087 0.09 0.000833002 0.000701647 0.018572 0.0162134 76.7 MiB 0.68 76.7 MiB 0.44 404 5.53425 120 1.64384 174 291 5454 1630 2.07112e+07 808410 1.12964e+06 2824.09 11 37792 180905 -1 2.17742 1.95241 -171.997 -2.17742 0 0 0.30 -1 -1 76.7 MiB 0.04 0.0564754 0.0510591 76.7 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt index b41f3d15872..37ed89929f5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml styr.blif common 3.89 vpr 58.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60104 10 10 253 263 1 165 89 11 11 121 clb auto 19.0 MiB 0.24 1298 4445 695 3556 194 58.7 MiB 0.05 0.00 5.53812 -72.6437 -5.53812 5.53812 0.21 0.000597156 0.000536921 0.0176424 0.0161115 -1 -1 -1 -1 14 2029 36 2.43e+06 2.07e+06 -1 -1 2.05 0.317982 0.283185 3402 27531 -1 1944 19 1218 4569 249188 30978 7.47374 7.47374 -94.8537 -7.47374 0 0 -1 -1 0.07 0.29 0.02 -1 -1 0.07 0.060437 0.0554417 - k4_n4_v7_longline_bidir.xml styr.blif common 4.05 vpr 58.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59432 10 10 253 263 1 165 89 11 11 121 clb auto 18.9 MiB 0.06 1243 3851 530 3175 146 58.0 MiB 0.04 0.00 4.42129 -53.6285 -4.42129 4.42129 0.23 0.000663771 0.000596818 0.0176359 0.0161365 -1 -1 -1 -1 19 2381 26 2.43e+06 2.07e+06 -1 -1 2.10 0.266841 0.23096 3282 34431 -1 2331 24 1499 5264 384444 46394 8.40637 8.40637 -105.933 -8.40637 0 0 -1 -1 0.10 0.21 0.02 -1 -1 0.10 0.0424648 0.0379047 - k4_n4_v7_l1_bidir.xml styr.blif common 5.46 vpr 58.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60072 10 10 253 263 1 165 89 11 11 121 clb auto 18.9 MiB 0.24 1249 6821 1452 5028 341 58.7 MiB 0.08 0.00 6.30077 -80.949 -6.30077 6.30077 0.24 0.000749315 0.000681105 0.0293634 0.0269084 -1 -1 -1 -1 10 1483 31 2.43e+06 2.07e+06 -1 -1 3.45 0.313343 0.275769 4482 22551 -1 1280 20 1321 4798 303501 58064 7.52318 7.52318 -89.7629 -7.52318 0 0 -1 -1 0.05 0.22 0.02 -1 -1 0.05 0.041626 0.0374306 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 4.39 vpr 58.13 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59524 10 10 253 263 1 165 89 11 11 121 clb auto 18.9 MiB 0.07 1252 4247 601 3492 154 58.1 MiB 0.05 0.00 3.38007 -43.5291 -3.38007 3.38007 0.17 0.000689869 0.000623886 0.0174325 0.0159695 -1 -1 -1 -1 14 2047 30 2.43e+06 2.07e+06 -1 -1 2.73 0.325816 0.284563 3402 27531 -1 2099 29 1484 5383 889715 156716 22.7353 22.7353 -261.092 -22.7353 0 0 -1 -1 0.05 0.26 0.03 -1 -1 0.05 0.0496444 0.0442275 + k4_n4_v7_bidir.xml styr.blif common 1.86 vpr 61.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62636 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.05 1288 4445 682 3619 144 61.2 MiB 0.05 0.00 5.46014 -72.9505 -5.46014 5.46014 0.08 0.000682102 0.000589331 0.0191204 0.0168271 -1 -1 -1 -1 14 2036 29 2.43e+06 2.07e+06 -1 -1 0.92 0.219017 0.188624 3402 27531 -1 1911 15 1185 4098 215222 27160 6.9309 6.9309 -92.2142 -6.9309 0 0 -1 -1 0.01 0.09 0.03 -1 -1 0.01 0.0322472 0.0293972 + k4_n4_v7_longline_bidir.xml styr.blif common 1.71 vpr 60.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61932 10 10 253 263 1 165 89 11 11 121 clb auto 21.2 MiB 0.08 1219 4247 600 3483 164 60.5 MiB 0.06 0.00 4.42494 -53.3169 -4.42494 4.42494 0.10 0.000822212 0.000745517 0.0200899 0.0175819 -1 -1 -1 -1 18 2215 40 2.43e+06 2.07e+06 -1 -1 0.71 0.217702 0.191181 3282 34431 -1 2139 18 1151 3756 254207 31830 9.07319 9.07319 -108.035 -9.07319 0 0 -1 -1 0.02 0.11 0.03 -1 -1 0.02 0.0360271 0.0325274 + k4_n4_v7_l1_bidir.xml styr.blif common 2.28 vpr 61.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62500 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.06 1285 7613 1616 5547 450 61.0 MiB 0.11 0.00 6.9252 -85.9419 -6.9252 6.9252 0.14 0.00083663 0.000735935 0.0404209 0.0365528 -1 -1 -1 -1 10 1481 31 2.43e+06 2.07e+06 -1 -1 1.11 0.183783 0.164876 4482 22551 -1 1268 22 1168 4312 263452 47622 7.30329 7.30329 -93.8299 -7.30329 0 0 -1 -1 0.01 0.12 0.02 -1 -1 0.01 0.0404434 0.0363816 + k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.36 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61916 10 10 253 263 1 165 89 11 11 121 clb auto 21.3 MiB 0.09 1234 4643 666 3821 156 60.5 MiB 0.06 0.00 3.51175 -43.7413 -3.51175 3.51175 0.10 0.000796689 0.00069941 0.0254117 0.0229956 -1 -1 -1 -1 16 1911 27 2.43e+06 2.07e+06 -1 -1 2.14 0.308921 0.270668 3522 30407 -1 1965 30 1263 4698 759011 126866 28.7744 28.7744 -241.883 -28.7744 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0527885 0.0460513 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt index 0c895ef220e..99bb28a8269 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 4.17 vpr 63.71 MiB -1 -1 0.84 23508 5 0.18 -1 -1 33600 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65244 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.28 146 398 72 298 28 63.7 MiB 0.07 0.01 2.14643 -92.7521 -2.14643 2.14643 0.08 0.000419766 0.000385553 0.00743059 0.00689969 -1 -1 -1 -1 14 201 20 646728 646728 22986.6 638.518 0.77 0.1423 0.123972 1728 4488 -1 171 15 208 442 9451 2845 2.12882 2.12882 -98.7664 -2.12882 0 0 30529.5 848.041 0.01 0.17 0.01 -1 -1 0.01 0.0225812 0.0202157 - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 4.53 vpr 63.96 MiB -1 -1 0.88 23572 5 0.17 -1 -1 33336 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65496 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.05 146 398 72 298 28 64.0 MiB 0.02 0.00 2.14643 -92.7521 -2.14643 2.14643 0.04 0.000405627 0.000370918 0.00658648 0.00608268 -1 -1 -1 -1 14 201 20 646728 646728 22986.6 638.518 1.69 0.282025 0.245066 1728 4488 -1 171 15 208 442 9451 2845 2.12882 2.12882 -98.7664 -2.12882 0 0 30529.5 848.041 0.01 0.21 0.01 -1 -1 0.01 0.0221666 0.0200952 + k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 2.33 vpr 66.02 MiB -1 -1 0.85 26768 5 0.17 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 432 67 335 30 66.0 MiB 0.03 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000423798 0.000369821 0.00844968 0.00761151 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.19 0.07328 0.0645326 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.03 0.01 -1 -1 0.00 0.0168546 0.0152174 + k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 2.62 vpr 65.81 MiB -1 -1 0.84 26884 5 0.22 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67392 10 2 181 183 1 35 24 6 6 36 clb auto 26.8 MiB 0.05 152 432 67 335 30 65.8 MiB 0.02 0.00 2.14643 -92.8849 -2.14643 2.14643 0.05 0.000430785 0.000371967 0.00760808 0.00673261 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.40 0.162173 0.135998 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.05 0.01 -1 -1 0.00 0.0294148 0.0268014 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt index f677f127a88..5d7f440c1da 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_heap_binary 5.49 vpr 65.63 MiB -1 -1 0.41 18996 3 0.19 -1 -1 33284 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67204 99 130 344 474 1 227 298 12 12 144 clb auto 25.8 MiB 0.26 717 72933 22876 34411 15646 65.6 MiB 0.49 0.01 1.84343 -118.171 -1.84343 1.84343 0.32 0.00110711 0.00103861 0.0946179 0.0889931 -1 -1 -1 -1 38 1545 17 5.66058e+06 4.21279e+06 319130. 2216.18 1.31 0.310492 0.285139 12522 62564 -1 1253 9 393 600 24053 7065 1.90841 1.90841 -133.88 -1.90841 -1.28606 -0.31945 406292. 2821.48 0.16 0.13 0.07 -1 -1 0.16 0.032452 0.0305703 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_heap_binary 2.91 vpr 67.98 MiB -1 -1 0.40 22276 3 0.11 -1 -1 36796 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69616 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.20 0.00 1.86472 -118.834 -1.86472 1.86472 0.22 0.000979117 0.000879056 0.0638803 0.0581045 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.56 0.199818 0.181639 12522 62564 -1 1120 9 399 643 21323 6785 1.90702 1.90702 -133.259 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.10 -1 -1 0.02 0.0304906 0.0285332 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt index 48a022dd3d9..c1c20666920 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 5.84 vpr 65.10 MiB -1 -1 0.39 18876 3 0.10 -1 -1 33232 -1 -1 71 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66660 99 130 344 474 1 225 301 13 13 169 clb auto 25.4 MiB 0.12 670 76909 23210 36946 16753 65.1 MiB 0.32 0.00 2.16096 -124.917 -2.16096 2.16096 0.44 0.00120946 0.00114822 0.0881788 0.0826918 -1 -1 -1 -1 32 1294 10 6.63067e+06 4.37447e+06 323148. 1912.12 2.10 0.382628 0.350915 11612 59521 -1 1127 11 526 869 34973 10462 1.97404 1.97404 -140.169 -1.97404 -0.343814 -0.101108 396943. 2348.77 0.15 0.17 0.06 -1 -1 0.15 0.0412974 0.0388666 - k6_N10_mem32K_40nm.xml diffeq1.v common 15.40 vpr 67.93 MiB -1 -1 0.74 23840 15 0.44 -1 -1 34444 -1 -1 61 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69560 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 28.5 MiB 0.42 5631 94844 28473 58959 7412 67.9 MiB 1.03 0.01 21.7383 -1576.03 -21.7383 21.7383 0.79 0.00372085 0.0034284 0.379891 0.357576 -1 -1 -1 -1 44 10661 49 1.21132e+07 5.26753e+06 665287. 2598.78 8.62 1.79562 1.64394 20656 131250 -1 8667 20 3482 8436 990185 277410 22.0559 22.0559 -1674.9 -22.0559 0 0 864808. 3378.16 0.32 0.39 0.15 -1 -1 0.32 0.147219 0.137238 - k6_N10_mem32K_40nm.xml single_wire.v common 1.30 vpr 62.92 MiB -1 -1 0.10 17140 1 0.02 -1 -1 30180 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64428 1 1 1 2 0 1 2 3 3 9 -1 auto 24.1 MiB 0.04 2 3 0 3 0 62.9 MiB 0.03 0.00 0.18684 -0.18684 -0.18684 nan 0.01 2.6888e-05 2.0274e-05 0.000125894 9.4502e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.03 0.00164489 0.00155135 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.02 0.00 -1 -1 0.00 0.00173302 0.00169026 - k6_N10_mem32K_40nm.xml single_ff.v common 1.46 vpr 62.77 MiB -1 -1 0.11 17408 1 0.04 -1 -1 30188 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64272 2 1 3 4 1 3 4 3 3 9 -1 auto 24.0 MiB 0.04 6 9 3 5 1 62.8 MiB 0.06 0.00 0.55247 -0.90831 -0.55247 0.55247 0.02 3.4252e-05 2.6329e-05 0.000209418 0.000157449 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.03 0.00197162 0.00182923 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.01 0.04 0.00 -1 -1 0.01 0.00155682 0.0014869 - k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 9.61 vpr 64.97 MiB -1 -1 0.41 18928 3 0.13 -1 -1 33340 -1 -1 71 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66528 99 130 344 474 1 225 301 19 19 361 o auto 25.3 MiB 0.24 983 75901 19451 37817 18633 65.0 MiB 0.54 0.00 2.16871 -135.347 -2.16871 2.16871 2.86 0.00121773 0.00114162 0.0972287 0.0905415 -1 -1 -1 -1 32 1458 11 1.79173e+07 4.37447e+06 762679. 2112.68 1.51 0.219057 0.201389 24278 148653 -1 1307 11 602 931 46510 12471 2.09384 2.09384 -139.537 -2.09384 -0.328666 -0.186439 944445. 2616.19 0.44 0.06 0.18 -1 -1 0.44 0.031886 0.0295362 - k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 27.29 vpr 82.19 MiB -1 -1 0.67 23752 15 0.43 -1 -1 34460 -1 -1 61 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 84164 162 96 1009 950 1 665 324 24 24 576 i auto 28.5 MiB 0.54 7386 77052 23414 46790 6848 82.2 MiB 0.69 0.01 21.6223 -1621.01 -21.6223 21.6223 4.64 0.00332881 0.00312838 0.251065 0.233165 -1 -1 -1 -1 32 13635 42 3.08128e+07 5.26753e+06 1.24505e+06 2161.54 15.07 1.57866 1.45267 39974 242477 -1 10826 21 3915 8751 1239118 330681 22.6153 22.6153 -1715.7 -22.6153 0 0 1.54255e+06 2678.04 0.62 0.44 0.21 -1 -1 0.62 0.158783 0.147345 - k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 1.44 vpr 62.84 MiB -1 -1 0.11 17216 1 0.04 -1 -1 30128 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64352 1 1 1 2 0 1 2 4 4 16 i auto 24.1 MiB 0.00 3 3 0 0 3 62.8 MiB 0.00 0.00 0.280667 -0.280667 -0.280667 nan 0.01 1.1887e-05 7.554e-06 7.9236e-05 5.4291e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.01 0.00144545 0.00135883 324 600 -1 2 1 1 1 16 6 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.02 0.04 0.01 -1 -1 0.02 0.00203875 0.00199605 - k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 1.61 vpr 62.92 MiB -1 -1 0.09 17432 1 0.03 -1 -1 29964 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64432 2 1 3 4 1 3 4 4 4 16 i auto 24.1 MiB 0.05 7 9 0 0 9 62.9 MiB 0.00 0.00 0.647256 -1.07419 -0.647256 0.647256 0.01 1.7185e-05 1.2489e-05 0.000119925 9.2542e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.0016352 0.00153073 340 760 -1 3 2 3 3 71 25 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.02 0.03 0.01 -1 -1 0.02 0.00163658 0.00157466 + k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.54 vpr 67.39 MiB -1 -1 0.42 22156 3 0.16 -1 -1 36544 -1 -1 71 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69008 99 130 344 474 1 225 301 13 13 169 clb auto 27.8 MiB 0.09 709 69853 20089 36202 13562 67.4 MiB 0.23 0.00 2.16096 -124.938 -2.16096 2.16096 0.29 0.000913323 0.000821579 0.0687918 0.0619499 -1 -1 -1 -1 30 1301 10 6.63067e+06 4.37447e+06 308771. 1827.05 1.05 0.343222 0.313014 11444 57198 -1 1153 11 545 813 32907 9964 1.99803 1.99803 -136.313 -1.99803 -0.30784 -0.0857401 382024. 2260.50 0.04 0.06 0.10 -1 -1 0.04 0.0301423 0.0279655 + k6_N10_mem32K_40nm.xml diffeq1.v common 13.02 vpr 70.71 MiB -1 -1 0.61 26808 15 0.59 -1 -1 38128 -1 -1 61 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72412 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 31.1 MiB 0.36 5686 93732 25708 60129 7895 70.7 MiB 0.92 0.01 21.5854 -1586.88 -21.5854 21.5854 0.47 0.00359311 0.00328994 0.373845 0.344857 -1 -1 -1 -1 42 11019 36 1.21132e+07 5.26753e+06 637230. 2489.18 7.15 1.94736 1.79599 20148 122574 -1 9118 25 3874 8580 1140724 318272 22.5245 22.5245 -1660.58 -22.5245 0 0 799729. 3123.94 0.07 0.71 0.15 -1 -1 0.07 0.298338 0.280888 + k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 65.29 MiB -1 -1 0.11 20620 1 0.02 -1 -1 33040 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 1 1 1 2 0 1 2 3 3 9 -1 auto 27.0 MiB 0.00 2 3 0 3 0 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0264e-05 6.201e-06 6.8769e-05 4.6066e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00116982 0.00111262 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00106891 0.001042 + k6_N10_mem32K_40nm.xml single_ff.v common 0.54 vpr 65.06 MiB -1 -1 0.09 21000 1 0.02 -1 -1 33296 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66620 2 1 3 4 1 3 4 3 3 9 -1 auto 26.6 MiB 0.00 6 9 3 5 1 65.1 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.01 2.0617e-05 1.4741e-05 0.000141684 0.000107774 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00168512 0.00158841 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00172391 0.0016612 + k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 5.58 vpr 67.37 MiB -1 -1 0.39 22284 3 0.08 -1 -1 36712 -1 -1 71 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68984 99 130 344 474 1 225 301 19 19 361 o auto 27.9 MiB 0.07 850 78925 21699 38013 19213 67.4 MiB 0.30 0.00 2.16428 -129.737 -2.16428 2.16428 1.74 0.000907451 0.000818758 0.097179 0.0888059 -1 -1 -1 -1 36 1162 10 1.79173e+07 4.37447e+06 833707. 2309.44 1.42 0.329975 0.298327 24998 161561 -1 1074 10 581 868 36231 9318 1.99581 1.99581 -134.677 -1.99581 -0.182839 -0.0660558 1.02328e+06 2834.56 0.12 0.05 0.23 -1 -1 0.12 0.0286893 0.0266338 + k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 20.39 vpr 77.82 MiB -1 -1 0.54 26812 15 0.47 -1 -1 38260 -1 -1 61 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79688 162 96 1009 950 1 665 324 24 24 576 i auto 30.8 MiB 0.33 7393 99292 28927 58867 11498 77.8 MiB 1.03 0.02 21.7254 -1657.33 -21.7254 21.7254 3.05 0.00462453 0.00428627 0.416981 0.375188 -1 -1 -1 -1 38 12380 31 3.08128e+07 5.26753e+06 1.42563e+06 2475.05 11.34 2.12533 1.94729 42274 284153 -1 10868 19 3672 8078 1198132 301968 22.4983 22.4983 -1725.65 -22.4983 0 0 1.79535e+06 3116.93 0.13 0.60 0.50 -1 -1 0.13 0.215504 0.199648 + k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.51 vpr 65.29 MiB -1 -1 0.10 20720 1 0.02 -1 -1 33044 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 1 1 1 2 0 1 2 4 4 16 i auto 26.9 MiB 0.00 3 3 0 0 3 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.1044e-05 6.598e-06 7.3231e-05 5.0487e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.00113801 0.00107607 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.00158495 0.00154688 + k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.64 vpr 65.29 MiB -1 -1 0.10 20876 1 0.03 -1 -1 33324 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 2 1 3 4 1 3 4 4 4 16 i auto 27.0 MiB 0.00 7 9 0 1 8 65.3 MiB 0.00 0.00 0.55247 -0.955943 -0.55247 0.55247 0.00 1.4352e-05 9.526e-06 0.000103801 7.6571e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.00161569 0.00152133 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00155787 0.00150496 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt index 61bfbd9f7c3..278399cb6d8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 5.19 vpr 63.54 MiB -1 -1 0.72 23444 5 0.16 -1 -1 33404 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65060 10 2 181 183 1 35 24 6 6 36 clb auto 24.1 MiB 0.14 157 568 195 321 52 63.5 MiB 0.01 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 14 182 25 646728 646728 22986.6 638.518 1.78 0.168378 0.144307 1728 4488 -1 155 21 263 632 12700 3802 2.3029 2.3029 -99.5273 -2.3029 0 0 30529.5 848.041 0.01 0.20 0.01 -1 -1 0.01 0.0242495 0.021514 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.77 vpr 65.95 MiB -1 -1 0.64 26892 5 0.17 -1 -1 36964 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67536 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 568 210 329 29 66.0 MiB 0.00 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 12 168 36 646728 646728 19965.4 554.594 0.12 0.0658358 0.0559906 1696 3924 -1 165 24 236 544 12437 3707 2.26842 2.26842 -94.6601 -2.26842 0 0 25971.8 721.439 0.00 0.03 0.00 -1 -1 0.00 0.0200385 0.0180231 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt index 045d3fe7955..b44eab4cd1c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common_--check_route_full 8.20 vpr 56.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57704 6 7 19 26 0 19 26 3 3 9 -1 auto 17.6 MiB 0.01 51 216 43 63 110 56.4 MiB 0.04 0.00 3.682 -25.774 -3.682 nan 6.49 6.5121e-05 5.701e-05 0.000603112 0.000525304 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.25 0.00299547 0.00268387 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.02 0.04 -1 -1 0.00 0.0025833 0.00241723 - sub_tiles.xml sub_tiles.blif common_--check_route_quick 8.02 vpr 56.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57820 6 7 19 26 0 19 26 3 3 9 -1 auto 17.7 MiB 0.01 51 216 43 63 110 56.5 MiB 0.13 0.00 3.682 -25.774 -3.682 nan 6.21 6.8432e-05 5.8755e-05 0.000633201 0.00053959 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.25 0.00290908 0.00262232 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.01 0.03 0.04 -1 -1 0.01 0.00211606 0.00201309 - sub_tiles.xml sub_tiles.blif common_--check_route_off 8.13 vpr 56.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57860 6 7 19 26 0 19 26 3 3 9 -1 auto 17.8 MiB 0.01 51 216 43 63 110 56.5 MiB 0.09 0.00 3.682 -25.774 -3.682 nan 6.37 7.7326e-05 6.6753e-05 0.000634774 0.000545772 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.25 0.0037268 0.00328193 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.02 0.09 0.04 -1 -1 0.02 0.00205651 0.00193283 + sub_tiles.xml sub_tiles.blif common_--check_route_full 14.98 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 13.82 4.4449e-05 3.636e-05 0.000492339 0.000302558 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.14 0.00246861 0.00204917 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00171876 0.00162871 + sub_tiles.xml sub_tiles.blif common_--check_route_quick 17.28 vpr 59.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60472 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.88 4.5558e-05 3.7864e-05 0.000392587 0.000316954 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00226581 0.00204304 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00121674 0.00115171 + sub_tiles.xml sub_tiles.blif common_--check_route_off 16.44 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.5 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.05 6.9962e-05 5.8494e-05 0.000570046 0.000472887 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.09 0.00239105 0.00217713 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00134624 0.00127449 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index 53684d6cff9..124aaee2a04 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.90 vpr 63.76 MiB -1 -1 0.12 17788 1 0.03 -1 -1 30128 -1 -1 3 9 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65288 9 8 75 70 1 34 20 5 5 25 clb auto 24.4 MiB 0.65 94 74 30 43 1 63.8 MiB 0.01 0.00 2.64007 -29.0549 -2.64007 2.64007 0.02 0.000134569 0.000121726 0.00170312 0.00163516 -1 -1 -1 -1 20 213 13 151211 75605.7 29112.5 1164.50 0.06 0.0102057 0.00938622 1812 4729 -1 172 28 196 239 7256 3917 3.69111 3.69111 -41.2836 -3.69111 0 0 37105.9 1484.24 0.00 0.05 0.01 -1 -1 0.00 0.0114522 0.00994594 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 10.86 vpr 64.98 MiB -1 -1 0.15 18364 1 0.04 -1 -1 30524 -1 -1 6 19 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66540 19 18 308 249 1 134 43 5 5 25 clb auto 25.3 MiB 6.04 443 2443 654 1774 15 65.0 MiB 0.32 0.00 4.8546 -99.0126 -4.8546 4.8546 0.05 0.000624995 0.000577932 0.0282589 0.0262406 -1 -1 -1 -1 50 734 31 151211 151211 61632.8 2465.31 2.88 0.28247 0.251267 2268 9834 -1 572 18 574 959 28269 13700 5.68143 5.68143 -111.492 -5.68143 0 0 77226.2 3089.05 0.02 0.05 0.01 -1 -1 0.02 0.0287398 0.0263667 53 83 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.66 vpr 66.09 MiB -1 -1 0.12 21064 1 0.03 -1 -1 33388 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67676 9 8 75 70 1 34 20 5 5 25 clb auto 27.2 MiB 0.65 100 74 24 47 3 66.1 MiB 0.00 0.00 2.48207 -28.4593 -2.48207 2.48207 0.02 0.000164662 0.000145718 0.00164144 0.00155216 -1 -1 -1 -1 38 129 6 151211 75605.7 48493.3 1939.73 0.18 0.0548944 0.0466047 2100 8065 -1 122 13 105 125 3874 2046 2.74837 2.74837 -33.9524 -2.74837 0 0 61632.8 2465.31 0.00 0.01 0.01 -1 -1 0.00 0.00954243 0.00888996 13 18 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 7.16 vpr 67.19 MiB -1 -1 0.14 21572 1 0.04 -1 -1 34020 -1 -1 6 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68800 19 18 308 249 1 134 43 5 5 25 clb auto 27.7 MiB 5.80 445 2068 454 1604 10 67.2 MiB 0.04 0.00 4.5386 -91.3528 -4.5386 4.5386 0.02 0.000449316 0.000397091 0.0186893 0.0169167 -1 -1 -1 -1 50 721 33 151211 151211 61632.8 2465.31 0.30 0.144091 0.126311 2268 9834 -1 620 20 733 1185 38218 18241 5.03997 5.03997 -109.631 -5.03997 0 0 77226.2 3089.05 0.00 0.04 0.01 -1 -1 0.00 0.0288144 0.0262691 53 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt index ad248bb36be..e2bde77991f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.58 vpr 57.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58932 1 4 28 32 2 10 9 4 4 16 clb auto 18.6 MiB 0.01 21 27 11 8 8 57.6 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.1025e-05 6.2018e-05 0.00055486 0.00050444 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.06 0.00779734 0.00653696 672 1128 -1 13 8 23 23 458 156 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00306883 0.00282037 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.67 vpr 57.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58820 1 4 28 32 2 10 9 4 4 16 clb auto 18.4 MiB 0.02 21 27 11 8 8 57.4 MiB 0.02 0.00 2.44626 0 0 2.44626 0.01 6.4104e-05 5.5768e-05 0.000609665 0.000560857 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.10 0.0111366 0.00958283 672 1128 -1 13 8 23 23 458 156 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00675941 0.0056104 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.64 vpr 57.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58996 1 4 28 32 2 10 9 4 4 16 clb auto 18.7 MiB 0.02 21 27 11 8 8 57.6 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 0.000116601 0.000103254 0.000726354 0.000668277 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.03 0.00873381 0.00733762 672 1128 -1 13 8 23 23 458 156 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00321575 0.00294979 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.40 vpr 59.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61208 1 4 28 32 2 10 9 4 4 16 clb auto 21.3 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.9684e-05 6.8866e-05 0.000576703 0.000522527 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00940561 0.00796331 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00917782 0.00398665 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.34 vpr 59.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61228 1 4 28 32 2 10 9 4 4 16 clb auto 21.3 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.4384e-05 5.704e-05 0.000402489 0.000366894 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.0100179 0.00835542 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00286153 0.00265955 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.31 vpr 59.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61188 1 4 28 32 2 10 9 4 4 16 clb auto 21.1 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.4879e-05 5.7282e-05 0.000404422 0.000368079 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00971796 0.00808787 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00303232 0.00280678 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt index aa6222425e4..9d76eedbd00 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.48 vpr 57.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58752 2 2 22 24 2 4 6 4 4 16 clb auto 18.5 MiB 0.01 8 15 5 7 3 57.4 MiB 0.00 0.00 1.297 0 0 1.297 0.01 7.8807e-05 7.0658e-05 0.000416035 0.000372622 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.00270904 0.00251355 660 1032 -1 15 4 8 8 614 487 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00251275 0.00236334 + timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.31 vpr 59.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61216 2 2 22 24 2 4 6 4 4 16 clb auto 21.3 MiB 0.00 8 15 5 7 3 59.8 MiB 0.00 0.00 1.297 0 0 1.297 0.01 5.264e-05 4.5649e-05 0.000308634 0.000273818 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.002301 0.00212354 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00265986 0.00219441 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt index 82ec46d8b99..55f3e1dd3ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.66039 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt index 373e866a79a..948d09b747d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.61 vpr 57.25 MiB -1 -1 0.07 17368 1 0.03 -1 -1 29984 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58620 2 1 3 4 1 3 4 3 3 9 -1 auto 18.5 MiB 0.00 6 9 6 3 0 57.2 MiB 0.00 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 1.6807e-05 1.1824e-05 0.000119813 9.1115e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.0015798 0.00147928 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.59 vpr 57.21 MiB -1 -1 0.08 17320 1 0.03 -1 -1 30044 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58584 2 1 3 4 1 3 4 3 3 9 -1 auto 18.6 MiB 0.00 9 9 5 2 2 57.2 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.8256e-05 1.1481e-05 0.000119179 8.8895e-05 -1 -1 -1 -1 -1 4 1 18000 18000 15707.9 1745.32 0.00 0.00156657 0.00148701 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 38.32 parmys 205.31 MiB -1 -1 31.78 210240 2 1.22 -1 -1 54528 -1 -1 155 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60600 5 156 191 347 1 163 316 15 15 225 clb auto 19.7 MiB 0.04 31 86316 62145 3320 20851 59.2 MiB 0.16 0.00 1.49664 -15.0848 -1.49664 1.49664 0.00 0.000581684 0.000550637 0.0478501 0.0452811 -1 -1 -1 -1 -1 50 5 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0572937 0.0539594 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 38.38 parmys 205.27 MiB -1 -1 31.80 210196 2 1.48 -1 -1 54476 -1 -1 155 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60720 5 156 191 347 1 163 316 15 15 225 clb auto 19.7 MiB 0.04 33 86316 61936 3548 20832 59.3 MiB 0.13 0.00 1.51877 -14.6769 -1.51877 1.51877 0.00 0.00039327 0.000370069 0.0328101 0.030775 -1 -1 -1 -1 -1 59 7 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0420611 0.0392993 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.64 vpr 62.86 MiB -1 -1 0.10 17484 1 0.03 -1 -1 30080 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64368 2 1 3 4 1 3 4 3 3 9 -1 auto 24.2 MiB 0.00 6 9 6 2 1 62.9 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.8165e-05 1.317e-05 0.000125618 9.4159e-05 -1 -1 -1 -1 -1 2 2 53894 53894 12370.0 1374.45 0.00 0.00159727 0.00150396 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.64 vpr 62.82 MiB -1 -1 0.10 17360 1 0.02 -1 -1 29972 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64332 2 1 3 4 1 3 4 3 3 9 -1 auto 24.1 MiB 0.01 9 9 5 2 2 62.8 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.693e-05 1.0549e-05 0.000124748 8.9675e-05 -1 -1 -1 -1 -1 8 1 53894 53894 14028.3 1558.70 0.00 0.00264161 0.002541 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 7.90 vpr 70.32 MiB -1 -1 1.65 25700 2 0.23 -1 -1 33916 -1 -1 43 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 72008 311 156 972 1128 1 953 525 28 28 784 memory auto 29.8 MiB 0.49 8857 212225 75880 124970 11375 70.3 MiB 1.71 0.02 3.97422 -4305.11 -3.97422 3.97422 0.00 0.00572888 0.00511108 0.585707 0.519764 -1 -1 -1 -1 -1 12735 10 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.46 0.855078 0.77478 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 7.81 vpr 70.43 MiB -1 -1 1.46 26084 2 0.15 -1 -1 33892 -1 -1 43 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 72124 311 156 972 1128 1 953 525 28 28 784 memory auto 29.8 MiB 0.58 9179 216459 74948 128246 13265 70.4 MiB 1.73 0.01 3.98529 -3456.75 -3.98529 3.98529 0.00 0.00402513 0.00355029 0.622817 0.553567 -1 -1 -1 -1 -1 13300 12 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.44 0.790802 0.707413 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 + timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.26 vpr 59.66 MiB -1 -1 0.07 21096 1 0.02 -1 -1 33168 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61096 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 6 9 6 3 0 59.7 MiB 0.00 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 1.5934e-05 1.0639e-05 9.4808e-05 6.8481e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00119359 0.00110751 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 + timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.27 vpr 59.66 MiB -1 -1 0.08 20840 1 0.02 -1 -1 33340 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61096 2 1 3 4 1 3 4 3 3 9 -1 auto 21.2 MiB 0.00 9 9 5 2 2 59.7 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.6744e-05 1.0373e-05 9.4261e-05 6.634e-05 -1 -1 -1 -1 -1 4 1 18000 18000 15707.9 1745.32 0.00 0.00132946 0.0012632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 + timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 31.57 parmys 210.75 MiB -1 -1 25.18 215804 2 1.59 -1 -1 60048 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63168 5 156 191 347 1 163 316 15 15 225 clb auto 22.1 MiB 0.04 31 86316 62145 3320 20851 61.7 MiB 0.22 0.02 1.49664 -15.0848 -1.49664 1.49664 0.00 0.000537912 0.000491594 0.0397632 0.036381 -1 -1 -1 -1 -1 50 5 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0494991 0.045404 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 + timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 25.71 parmys 210.82 MiB -1 -1 22.20 215880 2 0.99 -1 -1 60300 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62916 5 156 191 347 1 163 316 15 15 225 clb auto 21.9 MiB 0.02 33 86316 61936 3548 20832 61.4 MiB 0.10 0.00 1.51877 -14.6769 -1.51877 1.51877 0.00 0.000236107 0.000213852 0.0263786 0.0239723 -1 -1 -1 -1 -1 59 7 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0328145 0.0299576 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 + timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.41 vpr 65.16 MiB -1 -1 0.11 20748 1 0.02 -1 -1 33304 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 6 9 6 2 1 65.2 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.6453e-05 1.1342e-05 0.000108728 7.9328e-05 -1 -1 -1 -1 -1 2 2 53894 53894 12370.0 1374.45 0.00 0.0015946 0.00150943 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 + timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.41 vpr 65.16 MiB -1 -1 0.11 21132 1 0.02 -1 -1 33192 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 9 9 5 2 2 65.2 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.8934e-05 1.2137e-05 0.000113982 8.1444e-05 -1 -1 -1 -1 -1 8 1 53894 53894 14028.3 1558.70 0.00 0.00161693 0.00153615 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 + timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 5.07 vpr 72.77 MiB -1 -1 1.12 29456 2 0.10 -1 -1 37868 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74516 311 156 972 1128 1 953 525 28 28 784 memory auto 32.5 MiB 0.54 8655 197406 67882 119014 10510 72.8 MiB 1.23 0.02 3.83315 -4315.62 -3.83315 3.83315 0.00 0.0052551 0.00459042 0.542684 0.463052 -1 -1 -1 -1 -1 12421 13 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.41 0.761716 0.663478 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 + timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 5.34 vpr 72.84 MiB -1 -1 1.44 29580 2 0.14 -1 -1 38000 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74592 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.55 8675 193172 64013 116396 12763 72.8 MiB 0.82 0.01 3.94715 -3504.6 -3.94715 3.94715 0.00 0.00308193 0.00262987 0.364549 0.310746 -1 -1 -1 -1 -1 12709 18 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.33 0.5457 0.474589 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt index 2c49254b706..9cebacaf785 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.85 vpr 63.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65156 8 4 25 28 5 19 19 6 6 36 clb auto 24.9 MiB 0.59 52 194 34 129 31 63.6 MiB 0.01 0.00 1.3678 -5.84519 -1.3678 0.545 0.00 7.3716e-05 5.9392e-05 0.000813182 0.000675871 -1 -1 -1 -1 94 6.71429 38 2.71429 16 16 1079 432 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.70371 0.545 -7.0897 -1.70371 -0.508975 -0.416549 0.01 -1 -1 63.6 MiB 0.00 0.00311706 0.00282227 63.6 MiB -1 0.01 - k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.07 vpr 18.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 19032 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.85 vpr 66.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67612 8 4 25 28 5 19 19 6 6 36 clb auto 27.5 MiB 0.60 51 194 39 119 36 66.0 MiB 0.01 0.00 1.41795 -5.85435 -1.41795 0.545 0.00 8.3509e-05 6.4713e-05 0.00086545 0.000699438 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 675 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.01 -1 -1 66.0 MiB 0.00 0.00307466 0.00275514 66.0 MiB -1 0.00 + k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.03 vpr 20.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 21296 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt index 15ed137557f..c751724ac21 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.57 vpr 62.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64448 -1 2 2 4 0 2 4 4 4 16 clb auto 24.2 MiB 0.01 0 9 0 2 7 62.9 MiB 0.00 0.00 nan 0 0 nan 0.01 1.5432e-05 9.947e-06 0.000103448 7.2917e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.01 0.00166706 0.00157906 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00153779 0.0014983 + k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.30 vpr 65.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66556 -1 2 2 4 0 2 4 4 4 16 clb auto 26.8 MiB 0.00 0 9 0 2 7 65.0 MiB 0.00 0.00 nan 0 0 nan 0.01 9.099e-06 4.802e-06 6.6245e-05 4.4664e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.00112148 0.00105568 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00152182 0.00148612 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt index f2f0bc32df9..19c7fb784a9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_grid.xml raygentop.v common 50.12 vpr 84.06 MiB -1 -1 4.92 42896 3 0.97 -1 -1 38096 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86076 236 305 3199 3011 1 1520 677 25 25 625 -1 25x25 43.6 MiB 4.09 14118 291835 98746 175385 17704 84.1 MiB 2.87 0.03 4.72973 -2868.1 -4.72973 4.72973 2.50 0.00934029 0.00870323 1.04526 0.953005 -1 -1 -1 -1 52 26464 27 3.19446e+07 9.87633e+06 2.10129e+06 3362.06 27.31 4.1956 3.78489 66867 433069 -1 22541 17 6135 15940 1459564 357995 4.91399 4.91399 -3142.67 -4.91399 0 0 2.76576e+06 4425.22 0.86 0.74 0.34 -1 -1 0.86 0.41451 0.387228 - column_io.xml raygentop.v common 52.53 vpr 84.01 MiB -1 -1 4.75 43120 3 0.95 -1 -1 38088 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86024 236 305 3199 3011 1 1520 677 25 25 625 io auto 43.3 MiB 3.89 13024 265096 92273 145957 26866 84.0 MiB 2.89 0.07 4.68781 -2886.38 -4.68781 4.68781 2.43 0.016091 0.0142909 1.032 0.939322 -1 -1 -1 -1 54 26434 28 2.82259e+07 9.87633e+06 2.01770e+06 3228.33 30.36 4.7011 4.2358 60384 399159 -1 22444 15 6172 15744 1649398 413722 4.80071 4.80071 -3243.79 -4.80071 0 0 2.61977e+06 4191.64 0.69 0.69 0.36 -1 -1 0.69 0.354307 0.329375 - multiwidth_blocks.xml raygentop.v common 28.57 vpr 84.04 MiB -1 -1 4.75 43076 3 0.88 -1 -1 37996 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86060 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 43.3 MiB 3.59 13048 259154 90005 148757 20392 84.0 MiB 2.45 0.03 4.71803 -2841.59 -4.71803 4.71803 0.97 0.00752803 0.00694478 0.875966 0.783393 -1 -1 -1 -1 68 23694 44 1.65001e+07 9.87633e+06 1.28755e+06 3566.63 9.85 3.54924 3.21845 36601 236909 -1 20599 14 5516 14268 1424917 397183 4.96129 4.96129 -3042.89 -4.96129 0 0 1.60474e+06 4445.26 0.53 0.88 0.31 -1 -1 0.53 0.465359 0.438075 - non_column.xml raygentop.v common 42.55 vpr 104.43 MiB -1 -1 5.31 43252 3 0.75 -1 -1 38476 -1 -1 125 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 106936 236 305 3188 3000 1 1523 673 33 33 1089 io auto 45.0 MiB 3.88 15120 277785 102957 155262 19566 101.8 MiB 2.72 0.04 4.88336 -2959.54 -4.88336 4.88336 4.12 0.0135356 0.0122621 1.04776 0.936225 -1 -1 -1 -1 54 27353 23 5.44432e+07 9.66075e+06 3.30487e+06 3034.77 14.70 2.8388 2.54814 100302 649205 -1 23944 23 6474 17454 1453295 386379 5.20545 5.20545 -3216.33 -5.20545 0 0 4.28921e+06 3938.67 1.71 0.82 0.92 -1 -1 1.71 0.475433 0.442218 - non_column_tall_aspect_ratio.xml raygentop.v common 50.32 vpr 113.80 MiB -1 -1 5.13 43092 3 0.78 -1 -1 38540 -1 -1 125 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 116536 236 305 3188 3000 1 1523 673 23 46 1058 io auto 45.1 MiB 3.75 14514 263045 93443 131443 38159 101.1 MiB 2.67 0.03 4.82017 -2930.26 -4.82017 4.82017 3.80 0.00828949 0.00744749 0.950815 0.857933 -1 -1 -1 -1 50 29578 44 5.05849e+07 9.66075e+06 3.07243e+06 2904.00 24.36 4.29725 3.87978 95149 595581 -1 24184 18 6943 17685 1630226 419654 5.16068 5.16068 -3258.77 -5.16068 0 0 3.91054e+06 3696.17 1.09 0.74 0.66 -1 -1 1.09 0.398171 0.369417 - non_column_wide_aspect_ratio.xml raygentop.v common 58.69 vpr 121.68 MiB -1 -1 4.91 42728 3 0.80 -1 -1 38520 -1 -1 125 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 124604 236 305 3188 3000 1 1523 673 53 27 1431 io auto 45.2 MiB 3.93 16209 316109 110737 181993 23379 121.4 MiB 2.93 0.03 4.68132 -2964.88 -4.68132 4.68132 4.96 0.0102309 0.00911393 1.15188 1.03477 -1 -1 -1 -1 46 33009 48 7.18852e+07 9.66075e+06 3.81039e+06 2662.74 29.85 4.41198 3.98344 125381 744275 -1 26452 19 7219 18561 1795297 455177 5.41811 5.41811 -3289.3 -5.41811 0 0 4.88937e+06 3416.75 1.36 0.79 0.79 -1 -1 1.36 0.408966 0.377897 - custom_sbloc.xml raygentop.v common 32.21 vpr 83.94 MiB -1 -1 4.78 43028 3 0.93 -1 -1 38248 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 85956 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 43.3 MiB 3.43 12849 268067 89827 155344 22896 83.9 MiB 2.79 0.03 4.97602 -2840.03 -4.97602 4.97602 0.92 0.0104771 0.00924771 1.01557 0.905812 -1 -1 -1 -1 64 23203 26 1.65001e+07 9.87633e+06 1.19565e+06 3312.06 13.62 4.4638 4.00556 35881 230269 -1 20371 13 5422 13885 1260364 333144 5.08018 5.08018 -3072.96 -5.08018 0 0 1.50465e+06 4168.01 0.50 0.66 0.28 -1 -1 0.50 0.368005 0.3451 - multiple_io_types.xml raygentop.v common 121.78 vpr 532.44 MiB -1 -1 4.07 43200 3 0.82 -1 -1 37944 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 545220 236 305 3199 3011 1 1520 677 70 70 4900 io_left auto 43.7 MiB 5.99 31458 107633 6752 25817 75064 532.4 MiB 0.91 0.03 4.99804 -3572.5 -4.99804 4.99804 35.22 0.00883048 0.00802454 0.360901 0.3315 -1 -1 -1 -1 56 45066 25 2.76175e+08 9.87633e+06 1.50822e+07 3078.00 42.79 2.92767 2.65794 455094 2833831 -1 41437 17 7663 19266 3190631 818724 5.20546 5.20546 -3898.3 -5.20546 0 0 1.92585e+07 3930.30 6.20 1.08 2.64 -1 -1 6.20 0.379077 0.35159 + fixed_grid.xml raygentop.v common 36.32 vpr 86.72 MiB -1 -1 4.05 45484 3 0.90 -1 -1 40972 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88800 236 305 3199 3011 1 1520 677 25 25 625 -1 25x25 45.9 MiB 3.77 14108 309661 104995 184095 20571 86.7 MiB 2.82 0.04 4.79923 -2884.9 -4.79923 4.79923 1.31 0.00890658 0.00798503 1.05545 0.927146 -1 -1 -1 -1 58 25094 44 3.19446e+07 9.87633e+06 2.35761e+06 3772.18 18.23 4.76599 4.25993 69363 480205 -1 22477 18 6375 16887 1571491 383129 5.01505 5.01505 -3124.26 -5.01505 0 0 3.00727e+06 4811.63 0.12 0.58 0.43 -1 -1 0.12 0.287158 0.267873 + column_io.xml raygentop.v common 21.72 vpr 86.87 MiB -1 -1 3.94 45412 3 0.59 -1 -1 40804 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88956 236 305 3199 3011 1 1520 677 25 25 625 io auto 46.1 MiB 2.22 12585 268067 93998 147700 26369 86.9 MiB 1.58 0.02 4.73901 -2866.75 -4.73901 4.73901 0.71 0.00580557 0.00496502 0.564483 0.497852 -1 -1 -1 -1 54 26673 50 2.82259e+07 9.87633e+06 2.01770e+06 3228.33 9.11 2.60416 2.32669 60384 399159 -1 22031 17 6221 15823 1566992 390050 4.92063 4.92063 -3214.76 -4.92063 0 0 2.61977e+06 4191.64 0.11 0.57 0.36 -1 -1 0.11 0.283045 0.264698 + multiwidth_blocks.xml raygentop.v common 24.35 vpr 86.45 MiB -1 -1 4.29 45400 3 0.88 -1 -1 40680 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88524 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.5 MiB 3.44 13659 253212 84696 147080 21436 86.4 MiB 2.39 0.03 4.97053 -2888.67 -4.97053 4.97053 0.57 0.0095941 0.00864195 0.904905 0.798443 -1 -1 -1 -1 70 23087 25 1.65001e+07 9.87633e+06 1.31889e+06 3653.42 9.29 3.5266 3.16984 37321 246261 -1 21189 14 5796 14717 1380152 383870 5.13329 5.13329 -3164.24 -5.13329 0 0 1.66774e+06 4619.77 0.06 0.50 0.26 -1 -1 0.06 0.248992 0.232939 + non_column.xml raygentop.v common 55.37 vpr 101.45 MiB -1 -1 4.51 45384 3 0.78 -1 -1 40740 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103880 236 305 3188 3000 1 1523 673 33 33 1089 io auto 46.9 MiB 3.81 15255 254201 81770 140693 31738 97.7 MiB 2.36 0.03 4.86131 -2900.08 -4.86131 4.86131 2.27 0.00977579 0.00884174 0.917497 0.805822 -1 -1 -1 -1 48 30162 49 5.44432e+07 9.66075e+06 2.98548e+06 2741.49 34.00 4.50443 4.0188 95950 575791 -1 25045 20 6804 18118 1664218 433730 5.45028 5.45028 -3158.16 -5.45028 0 0 3.81303e+06 3501.40 0.21 0.95 0.95 -1 -1 0.21 0.482241 0.44347 + non_column_tall_aspect_ratio.xml raygentop.v common 44.05 vpr 108.02 MiB -1 -1 4.73 45644 3 0.86 -1 -1 40856 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 110616 236 305 3188 3000 1 1523 673 23 46 1058 io auto 47.3 MiB 3.74 14790 242409 83942 122709 35758 98.8 MiB 2.21 0.03 4.6713 -2947.44 -4.6713 4.6713 2.10 0.00881355 0.00803567 0.866396 0.762137 -1 -1 -1 -1 54 27998 49 5.05849e+07 9.66075e+06 3.28516e+06 3105.07 22.44 5.06657 4.53255 98319 656086 -1 23970 19 6505 16966 1638977 432992 5.05886 5.05886 -3281.32 -5.05886 0 0 4.26512e+06 4031.31 0.30 0.98 1.19 -1 -1 0.30 0.480325 0.442198 + non_column_wide_aspect_ratio.xml raygentop.v common 55.14 vpr 115.98 MiB -1 -1 4.85 45536 3 0.89 -1 -1 40604 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 118764 236 305 3188 3000 1 1523 673 53 27 1431 io auto 47.2 MiB 4.13 15438 292525 96949 170972 24604 116.0 MiB 2.79 0.04 4.87363 -3002.95 -4.87363 4.87363 2.83 0.00999099 0.00902684 1.12807 0.98489 -1 -1 -1 -1 46 32183 50 7.18852e+07 9.66075e+06 3.81039e+06 2662.74 30.50 4.16688 3.69158 125381 744275 -1 26057 24 7716 19635 2034521 534369 5.1816 5.1816 -3336.75 -5.1816 0 0 4.88937e+06 3416.75 0.38 1.34 1.15 -1 -1 0.38 0.614347 0.564321 + custom_sbloc.xml raygentop.v common 26.06 vpr 86.32 MiB -1 -1 4.50 45448 3 1.04 -1 -1 40804 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88392 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.3 MiB 4.20 13741 271038 86813 158916 25309 86.3 MiB 2.67 0.04 4.66207 -2945.67 -4.66207 4.66207 0.62 0.0101306 0.00867476 0.964821 0.865378 -1 -1 -1 -1 68 24218 46 1.65001e+07 9.87633e+06 1.26689e+06 3509.39 7.14 3.30943 2.96886 36601 241349 -1 21082 17 5846 15055 1419293 377571 4.86127 4.86127 -3204.17 -4.86127 0 0 1.57833e+06 4372.12 0.09 0.93 0.49 -1 -1 0.09 0.46499 0.431595 + multiple_io_types.xml raygentop.v common 162.68 vpr 512.77 MiB -1 -1 4.59 44868 3 0.91 -1 -1 40632 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 525072 236 305 3199 3011 1 1520 677 70 70 4900 io_left auto 46.0 MiB 4.88 29540 98720 5114 25125 68481 512.8 MiB 0.75 0.03 4.77694 -3775.91 -4.77694 4.77694 29.11 0.00955143 0.00822118 0.265489 0.23233 -1 -1 -1 -1 46 47171 45 2.76175e+08 9.87633e+06 1.25363e+07 2558.43 103.39 4.74809 4.24216 425698 2387761 -1 40627 18 8645 22202 3622069 899914 5.14884 5.14884 -4109.51 -5.14884 0 0 1.61910e+07 3304.29 1.21 1.53 3.08 -1 -1 1.21 0.445697 0.411568 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt index d908d4ed0df..9ad80c43a91 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 4.08 vpr 65.78 MiB -1 -1 0.40 19048 3 0.11 -1 -1 33284 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67356 99 130 344 474 1 227 298 12 12 144 clb auto 26.1 MiB 0.25 717 72933 22876 34411 15646 65.8 MiB 0.24 0.00 1.84343 -118.171 -1.84343 1.84343 0.43 0.000943281 0.00088635 0.0770799 0.0722149 -1 -1 -1 -1 38 1552 14 5.66058e+06 4.21279e+06 328943. 2284.32 0.86 0.213472 0.195926 12522 66188 -1 1256 9 393 600 24051 7073 1.90841 1.90841 -134.177 -1.90841 -1.28606 -0.31945 418267. 2904.63 0.16 0.04 0.09 -1 -1 0.16 0.0289584 0.0270731 + k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 3.10 vpr 67.93 MiB -1 -1 0.36 22040 3 0.12 -1 -1 36928 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69560 99 130 344 474 1 227 298 12 12 144 clb auto 28.6 MiB 0.23 673 63978 19550 30341 14087 67.9 MiB 0.25 0.01 1.86472 -118.834 -1.86472 1.86472 0.23 0.00124652 0.00114654 0.0791433 0.0725521 -1 -1 -1 -1 38 1384 9 5.66058e+06 4.21279e+06 328943. 2284.32 0.66 0.24355 0.222932 12522 66188 -1 1114 9 395 636 21516 6871 1.90702 1.90702 -133.439 -1.90702 -1.20917 -0.320482 418267. 2904.63 0.04 0.05 0.10 -1 -1 0.04 0.0351893 0.0324309 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt index 8f5f4a02727..88d0cc36263 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 75.27 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1221072 13 29 26295 20086 1 12439 800 40 32 1280 -1 EP4SGX110 1063.1 MiB 16.25 74701 260640 52935 201304 6401 1192.5 MiB 10.24 0.14 5.01005 -5474.24 -4.01005 2.78538 0.01 0.0384053 0.0310295 2.9187 2.44906 86606 6.96358 20705 1.66479 25778 34975 9286411 1665781 0 0 2.34683e+07 18334.6 14 375646 4004209 -1 5.31377 2.77336 -5554.53 -4.31377 0 0 7.20 -1 -1 1192.5 MiB 3.77 4.63873 3.95514 1192.5 MiB -1 15.10 + stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 65.74 vpr 1.17 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1222776 13 29 26295 20086 1 12439 800 40 32 1280 -1 EP4SGX110 1063.6 MiB 14.29 72376 238368 44187 187356 6825 1172.1 MiB 12.27 0.21 5.14869 -5574.19 -4.14869 2.7734 0.01 0.0513395 0.0444487 3.37672 2.67885 83490 6.71303 20017 1.60947 25863 35776 9229792 1644713 0 0 2.34683e+07 18334.6 15 375646 4004209 -1 5.37962 2.85331 -5732.11 -4.37962 0 0 7.55 -1 -1 1172.1 MiB 6.09 5.72718 4.67253 1172.1 MiB -1 3.79 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt index e1e3f31918d..f8dbe6d76d8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 4.18 vpr 62.35 MiB -1 -1 0.41 18976 3 0.11 -1 -1 33312 -1 -1 72 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63844 99 130 353 483 1 273 302 15 15 225 memory auto 22.6 MiB 0.05 852 74178 23994 32332 17852 62.3 MiB 0.23 0.00 1.52582 -80.4614 -1.52582 1.52582 0.00 0.00092711 0.000867428 0.0693377 0.06488 -1 -1 -1 -1 1170 5.46729 648 3.02804 652 1492 181450 49896 1.16234e+06 363548 2.18283e+06 9701.45 10 48952 428016 -1 1.67686 1.67686 -105.874 -1.67686 -2.09914 -0.312873 0.62 -1 -1 62.3 MiB 0.07 0.0963391 0.0897976 62.3 MiB -1 1.98 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 2.26 vpr 64.63 MiB -1 -1 0.36 22472 3 0.08 -1 -1 36672 -1 -1 72 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66184 99 130 353 483 1 273 302 15 15 225 memory auto 25.1 MiB 0.03 836 70130 21082 33527 15521 64.6 MiB 0.28 0.00 1.52582 -78.5706 -1.52582 1.52582 0.00 0.00103975 0.000940046 0.0805857 0.0730912 -1 -1 -1 -1 1163 5.43458 640 2.99065 663 1535 177334 49638 1.16234e+06 363548 2.18283e+06 9701.45 10 48952 428016 -1 1.65868 1.65868 -90.7494 -1.65868 -2.16982 -0.309514 0.64 -1 -1 64.6 MiB 0.08 0.105372 0.095866 64.6 MiB -1 0.38 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt index 843f979b3b0..01809a06f11 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 36.56 vpr 83.12 MiB -1 -1 1.49 26172 2 0.18 -1 -1 34220 -1 -1 32 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 85116 311 156 1015 1158 1 965 514 28 28 784 memory auto 32.4 MiB 0.98 8658 202198 68681 121559 11958 83.1 MiB 1.72 0.04 4.52468 -3467.97 -4.52468 4.52468 3.21 0.00929751 0.00872728 0.605238 0.537126 -1 -1 -1 -1 36 15288 36 4.25198e+07 9.94461e+06 1.97160e+06 2514.80 19.52 3.06547 2.77593 76483 392267 -1 13678 12 2942 3353 770564 257137 4.55307 4.55307 -4387.12 -4.55307 -358.532 -1.23434 2.42825e+06 3097.26 1.16 2.02 0.42 -1 -1 1.16 0.193225 0.179934 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 34.90 vpr 83.83 MiB -1 -1 1.47 25784 2 0.19 -1 -1 34296 -1 -1 32 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 85840 311 156 1015 1158 1 965 514 28 28 784 memory auto 32.4 MiB 0.98 8658 202198 68681 121559 11958 83.8 MiB 1.42 0.01 4.52468 -3467.97 -4.52468 4.52468 2.94 0.00393818 0.00343783 0.510989 0.454287 -1 -1 -1 -1 36 15409 27 4.25198e+07 9.94461e+06 2.00618e+06 2558.90 18.25 2.85623 2.58578 76483 403003 -1 13760 16 3067 3560 745826 226255 4.40123 4.40123 -4543.68 -4.40123 -178.96 -1.26307 2.47848e+06 3161.33 1.21 2.10 0.41 -1 -1 1.21 0.238381 0.220608 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 28.59 vpr 84.23 MiB -1 -1 1.56 25800 2 0.18 -1 -1 34208 -1 -1 32 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86256 311 156 1015 1158 1 965 514 28 28 784 memory auto 32.3 MiB 0.99 8666 202198 68103 120968 13127 84.2 MiB 1.54 0.02 4.38362 -3624.19 -4.38362 4.38362 3.07 0.00455316 0.00405324 0.525661 0.462249 -1 -1 -1 -1 40 15871 21 4.25198e+07 9.94461e+06 2.15085e+06 2743.43 10.76 2.02034 1.8204 78831 435812 -1 14774 15 2518 2894 1193668 708143 5.59605 5.59605 -4517.23 -5.59605 -1680.59 -3.37889 2.68809e+06 3428.68 1.36 3.08 0.49 -1 -1 1.36 0.410611 0.383265 15 950 + timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 22.14 vpr 81.82 MiB -1 -1 1.50 29500 2 0.12 -1 -1 37736 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83780 311 156 1015 1158 1 965 514 28 28 784 memory auto 35.0 MiB 0.98 9365 202198 74776 117229 10193 76.8 MiB 1.40 0.02 4.8046 -3913.87 -4.8046 4.8046 1.69 0.00610306 0.00535177 0.650008 0.562031 -1 -1 -1 -1 46 14326 15 4.25198e+07 9.94461e+06 2.42825e+06 3097.26 10.53 2.95135 2.62498 81963 495902 -1 13813 11 2359 2703 832718 314081 4.94363 4.94363 -4384.42 -4.94363 -367.864 -1.26276 3.12000e+06 3979.60 0.25 1.49 0.70 -1 -1 0.25 0.183604 0.168791 15 950 + timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 21.14 vpr 85.34 MiB -1 -1 1.46 29488 2 0.17 -1 -1 37984 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 87384 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.6 MiB 1.02 9365 202198 74776 117229 10193 77.2 MiB 1.49 0.03 4.8046 -3913.87 -4.8046 4.8046 1.72 0.00745529 0.00636204 0.709181 0.610899 -1 -1 -1 -1 46 14531 14 4.25198e+07 9.94461e+06 2.47848e+06 3161.33 10.27 3.22179 2.86209 81963 509322 -1 13895 10 2295 2641 564364 164225 5.2138 5.2138 -4583.26 -5.2138 -149.396 -1.20609 3.17357e+06 4047.92 0.16 0.89 0.46 -1 -1 0.16 0.127663 0.117099 15 950 + timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 25.61 vpr 78.92 MiB -1 -1 1.51 29244 2 0.15 -1 -1 37516 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80812 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.8 MiB 0.83 9442 200140 70475 118412 11253 78.1 MiB 1.44 0.02 4.10149 -3784.12 -4.10149 4.10149 1.51 0.00620655 0.00547017 0.672177 0.575194 -1 -1 -1 -1 40 16586 15 4.25198e+07 9.94461e+06 2.15085e+06 2743.43 14.64 1.95101 1.72006 78831 435812 -1 15579 11 2621 3012 1218850 719774 5.45816 5.45816 -4586.28 -5.45816 -1608.52 -3.17721 2.68809e+06 3428.68 0.23 1.76 0.54 -1 -1 0.23 0.216383 0.199419 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt index e7307c55606..6c7432d3e12 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 15.60 vpr 69.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70696 64 39 1935 1974 1 1077 541 23 23 529 clb auto 28.8 MiB 0.37 10085 137127 36539 98027 2561 69.0 MiB 1.24 0.02 7.41831 -1418.64 -7.41831 7.41831 0.89 0.00562414 0.00480176 0.355623 0.303324 -1 -1 -1 -1 22 12754 28 983127 976439 735934. 1391.18 7.61 1.13414 0.983828 35322 121345 -1 11109 19 6608 23845 1462488 382373 7.14816 7.14816 -1474.13 -7.14816 0 0 927497. 1753.30 0.18 1.15 0.16 -1 -1 0.18 0.319207 0.292209 + k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 16.52 vpr 71.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73256 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.4 MiB 0.33 10472 141533 36950 100839 3744 71.5 MiB 1.36 0.02 7.46482 -1369.01 -7.46482 7.46482 0.53 0.00499636 0.00433729 0.369387 0.30729 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 10.94 2.01193 1.71604 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.85 0.23 -1 -1 0.04 0.262211 0.23364 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt index 2ed54d22fd2..15d40a35dda 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 44.58 vpr 82.23 MiB -1 -1 8.38 52984 5 2.48 -1 -1 39568 -1 -1 153 193 5 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 84204 193 205 2718 2652 1 1312 556 20 20 400 memory auto 41.6 MiB 2.41 10365 229056 86247 118235 24574 82.2 MiB 2.50 0.03 4.93042 -2712.69 -4.93042 4.93042 1.52 0.00941947 0.00864017 1.00208 0.892514 -1 -1 -1 -1 82 19408 35 2.07112e+07 1.09858e+07 2.14661e+06 5366.52 20.26 4.55427 4.07475 53670 456392 -1 17785 15 4760 12593 961685 215487 5.25964 5.25964 -2873.25 -5.25964 -10.2812 -0.29768 2.68822e+06 6720.56 0.99 0.57 0.52 -1 -1 0.99 0.345857 0.321125 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 34.16 vpr 84.50 MiB -1 -1 7.12 54432 5 2.11 -1 -1 42788 -1 -1 153 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 86528 193 205 2718 2652 1 1312 556 20 20 400 memory auto 43.4 MiB 1.85 10543 233626 82676 126206 24744 84.5 MiB 2.72 0.04 4.85425 -2733.64 -4.85425 4.85425 0.66 0.00818288 0.00722228 1.06716 0.90034 -1 -1 -1 -1 76 20844 33 2.07112e+07 1.09858e+07 2.02110e+06 5052.76 15.57 4.03457 3.54046 52074 423490 -1 18742 16 4982 13549 1088379 246430 5.27071 5.27071 -2903.22 -5.27071 -6.49744 -0.292146 2.51807e+06 6295.18 0.11 0.47 0.38 -1 -1 0.11 0.260053 0.24125 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt index 218d776b173..d0e64cbc176 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.12 vpr 65.63 MiB -1 -1 0.43 18936 3 0.10 -1 -1 33276 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67208 99 130 344 474 1 227 298 12 12 144 clb auto 25.9 MiB 0.31 717 72933 22876 34411 15646 65.6 MiB 0.28 0.00 1.84343 -118.171 -1.84343 1.84343 0.41 0.00118638 0.00111707 0.0787144 0.0738877 -1 -1 -1 -1 38 1540 14 5.66058e+06 4.21279e+06 319130. 2216.18 0.79 0.216838 0.200184 12522 62564 -1 1261 9 399 607 24533 7188 1.90841 1.90841 -134.095 -1.90841 -1.28606 -0.31945 406292. 2821.48 0.13 0.04 0.07 -1 -1 0.13 0.0278788 0.0260572 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.94 vpr 67.99 MiB -1 -1 0.39 22036 3 0.12 -1 -1 36636 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69620 99 130 344 474 1 227 298 12 12 144 clb auto 28.6 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.21 0.00 1.86472 -118.834 -1.86472 1.86472 0.24 0.000996678 0.000900839 0.0648293 0.0586504 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.58 0.202532 0.183764 12522 62564 -1 1116 11 409 682 22304 6997 1.90702 1.90702 -133.281 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.06 0.09 -1 -1 0.02 0.0346978 0.0324594 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt index 4e81f397cb6..2abafbec4a3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_40nm.xml stereovision0.v common 151.84 vpr 271.81 MiB -1 -1 18.22 123192 5 52.14 -1 -1 65180 -1 -1 1352 169 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 278332 169 197 21117 21314 1 6442 1718 39 39 1521 clb auto 119.5 MiB 5.00 49106 989078 343367 618966 26745 271.8 MiB 10.45 0.10 3.87493 -15116.8 -3.87493 3.87493 9.42 0.0295107 0.0249862 3.37183 2.81407 -1 -1 -1 -1 38 61885 27 2.4642e+07 2.4336e+07 4.29790e+06 2825.71 35.67 14.1092 11.5867 119030 883757 -1 58128 20 30287 65526 2502097 448520 3.7865 3.7865 -15779.5 -3.7865 0 0 5.41627e+06 3561.00 1.70 2.36 0.73 -1 -1 1.70 1.66008 1.43692 - k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 138.53 vpr 269.16 MiB -1 -1 17.93 123432 5 52.13 -1 -1 65280 -1 -1 1342 169 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 275616 169 197 21117 21314 1 6530 1708 39 39 1521 clb auto 119.7 MiB 5.14 49426 991593 360564 611379 19650 269.2 MiB 10.35 0.10 3.57102 -14945.7 -3.57102 3.57102 9.54 0.0295319 0.0250555 3.23004 2.68449 -1 -1 -1 -1 38 62626 36 7.37824e+07 7.23272e+07 4.16760e+06 2740.04 21.59 11.6516 9.60196 119030 845795 -1 58726 26 31787 68726 2500109 471239 3.4196 3.4196 -15850.7 -3.4196 0 0 5.22668e+06 3436.35 1.71 2.83 0.65 -1 -1 1.71 2.09886 1.80153 + k6_N10_40nm.xml stereovision0.v common 151.16 vpr 252.22 MiB -1 -1 13.65 124444 5 69.06 -1 -1 68628 -1 -1 1352 169 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 258272 169 197 21117 21314 1 6442 1718 39 39 1521 clb auto 120.8 MiB 5.85 49865 999363 355164 624898 19301 252.2 MiB 12.58 0.10 3.94387 -15329.6 -3.94387 3.94387 5.65 0.0282487 0.0224608 3.71486 2.98245 -1 -1 -1 -1 38 62474 28 2.4642e+07 2.4336e+07 4.29790e+06 2825.71 27.54 18.235 14.9379 119030 883757 -1 58887 28 30785 67364 2647531 463217 3.72242 3.72242 -16216.3 -3.72242 0 0 5.41627e+06 3561.00 0.27 2.70 0.65 -1 -1 0.27 1.99577 1.72788 + k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 145.25 vpr 237.36 MiB -1 -1 13.92 124256 5 67.78 -1 -1 68500 -1 -1 1342 169 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 243060 169 197 21117 21314 1 6530 1708 39 39 1521 clb auto 120.5 MiB 3.79 49914 971183 338147 610049 22987 237.4 MiB 14.52 0.10 3.63479 -14732.8 -3.63479 3.63479 5.35 0.02794 0.0220913 4.48744 3.66675 -1 -1 -1 -1 40 62766 41 7.37824e+07 7.23272e+07 4.31957e+06 2839.95 22.87 16.3688 13.4703 120550 875283 -1 59263 24 31348 67380 2546099 475966 3.57863 3.57863 -15572.9 -3.57863 0 0 5.40678e+06 3554.75 0.57 4.00 1.03 -1 -1 0.57 2.85785 2.46864 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index 5a135fa5675..3a5d60de356 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.39 vpr 58.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59484 3 1 5 6 1 4 5 3 3 9 -1 auto 19.7 MiB 0.00 9 12 4 4 4 58.1 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.7269e-05 1.2376e-05 0.000128336 0.000101173 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00155195 0.0014541 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00163857 0.00158765 - k6_frac_N10_40nm.xml conn_order.eblif common 0.47 vpr 58.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59388 2 1 4 5 1 3 4 3 3 9 -1 auto 19.6 MiB 0.00 6 9 4 1 4 58.0 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 2.0764e-05 1.5673e-05 0.000154884 0.000113002 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.01 0.00171618 0.00160639 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00144513 0.00140629 + k6_frac_N10_40nm.xml test_eblif.eblif common 0.36 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 3 1 5 6 1 4 5 3 3 9 -1 auto 22.0 MiB 0.00 9 12 4 4 4 60.5 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.3168e-05 1.5881e-05 0.000156154 0.000121512 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00179937 0.00168173 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00151021 0.00147037 + k6_frac_N10_40nm.xml conn_order.eblif common 0.33 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 2 1 4 5 1 3 4 3 3 9 -1 auto 22.1 MiB 0.00 6 9 4 1 4 60.5 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.6567e-05 1.1555e-05 0.000123665 9.5691e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.00181279 0.00171778 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154282 0.00150229 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt index 9fe54ec14ab..6afcd280a0b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml eblif_write.eblif common 0.48 vpr 56.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57744 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 17.7 MiB 0.00 14 18 7 10 1 56.4 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 1.8648e-05 1.2503e-05 0.000127908 9.7495e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00173006 0.00162827 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00148908 0.0014446 + arch.xml eblif_write.eblif common 0.28 vpr 58.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60388 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 20.5 MiB 0.00 14 18 7 10 1 59.0 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 2.2578e-05 1.4571e-05 0.000133192 9.8031e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00167256 0.00156119 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00133191 0.00129055 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt index daf901cac9d..826beb46c2f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.56 vpr 63.62 MiB -1 -1 0.89 23616 5 0.15 -1 -1 33552 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65152 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.18 146 398 72 298 28 63.6 MiB 0.11 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.000445467 0.000411761 0.00801694 0.00746509 -1 -1 -1 -1 -1 136 16 646728 646728 60312.4 1675.34 0.11 0.0303214 0.027336 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.94 vpr 66.02 MiB -1 -1 0.82 27148 5 0.18 -1 -1 36836 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.09 152 432 67 335 30 66.0 MiB 0.04 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000434946 0.000380309 0.00759691 0.00679441 -1 -1 -1 -1 -1 145 18 646728 646728 60312.4 1675.34 0.03 0.0281069 0.0251327 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt index e9d9eeaa41e..106e5784d60 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - equivalent.xml equivalent.blif common 0.46 vpr 56.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57816 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 17.7 MiB 0.00 9 9 4 5 0 56.5 MiB 0.01 0.00 3.8649 -3.8649 -3.8649 nan 0.03 5.3982e-05 3.6833e-05 0.000300109 0.000216559 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00165523 0.00149952 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00144261 0.0014006 + equivalent.xml equivalent.blif common 0.33 vpr 58.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60324 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 20.4 MiB 0.00 9 9 3 6 0 58.9 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 1.5162e-05 1.0275e-05 0.00029282 0.000262472 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00144752 0.00135246 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00148764 0.00144592 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt index 05df18fd944..f0909e951de 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 3.12 vpr 63.56 MiB -1 -1 0.88 23644 5 0.18 -1 -1 33408 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65088 10 2 181 183 1 35 24 6 6 36 clb auto 24.1 MiB 0.14 146 398 73 297 28 63.6 MiB 0.03 0.00 2.15218 -93.1951 -2.15218 2.15218 0.05 0.000531567 0.000499904 0.0102703 0.00975502 -1 -1 -1 -1 8 178 24 646728 646728 33486.6 930.184 0.37 0.0711325 0.0621504 1588 8314 -1 187 26 302 650 19860 6525 2.46771 2.46771 -110.005 -2.46771 0 0 42482.2 1180.06 0.01 0.07 0.01 -1 -1 0.01 0.0278289 0.0226019 + k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 2.12 vpr 65.83 MiB -1 -1 0.80 26828 5 0.17 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67408 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.03 152 432 67 335 30 65.8 MiB 0.01 0.00 2.15218 -93.3318 -2.15218 2.15218 0.04 0.000541794 0.000472344 0.00646942 0.00583397 -1 -1 -1 -1 8 206 22 646728 646728 33486.6 930.184 0.18 0.0650705 0.0566044 1588 8314 -1 169 20 235 523 16218 5641 2.44258 2.44258 -104.337 -2.44258 0 0 42482.2 1180.06 0.00 0.03 0.01 -1 -1 0.00 0.0191215 0.0169186 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt index 35bd7aa8ea6..e41ab909d3a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fix_clusters_test_arch.xml apex2.blif common 24.18 vpr 72.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 74380 38 3 1916 1919 0 1054 173 7 7 49 clb auto 32.1 MiB 4.40 5572 10755 973 9191 591 72.6 MiB 0.34 0.01 5.10521 -15.0222 -5.10521 nan 0.24 0.00524309 0.00429013 0.156975 0.1351 -1 -1 -1 -1 162 7714 43 1.34735e+06 7.11401e+06 944075. 19266.8 15.81 3.57525 3.0646 18450 291720 -1 7029 18 5960 24809 1093324 352159 5.64405 nan -16.6537 -5.64405 0 0 1.17629e+06 24005.9 0.25 0.82 0.25 -1 -1 0.25 0.397625 0.36383 + fix_clusters_test_arch.xml apex2.blif common 14.77 vpr 75.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76916 38 3 1916 1919 0 1054 173 7 7 49 clb auto 34.4 MiB 4.62 5572 1135 0 0 1135 75.1 MiB 0.08 0.01 5.10521 -15.0504 -5.10521 nan 0.19 0.00530639 0.00465724 0.0561264 0.0529208 -1 -1 -1 -1 164 7542 34 1.34735e+06 7.11401e+06 957298. 19536.7 7.09 2.13567 1.82713 18546 296938 -1 6979 21 5560 22630 961929 323712 5.65021 nan -16.5347 -5.65021 0 0 1.19720e+06 24432.6 0.05 0.66 0.37 -1 -1 0.05 0.343651 0.311264 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt index 6e10a5ba903..c4013f9bc8c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 3.30 vpr 63.87 MiB -1 -1 0.94 23512 5 0.18 -1 -1 33344 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65404 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.11 148 364 32 317 15 63.9 MiB 0.05 0.00 2.14643 -90.773 -2.14643 2.14643 0.03 0.000335395 0.000285078 0.00639243 0.00590769 -1 -1 -1 -1 12 177 21 646728 646728 19965.4 554.594 0.61 0.149391 0.122522 1696 3924 -1 153 14 202 474 9884 3007 2.16575 2.16575 -96.6802 -2.16575 0 0 25971.8 721.439 0.01 0.03 0.00 -1 -1 0.01 0.0144768 0.0129004 + k6_N10_mem32K_40nm.xml stereovision3.v common 2.09 vpr 66.02 MiB -1 -1 0.81 27020 5 0.18 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67608 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.06 152 364 33 322 9 66.0 MiB 0.01 0.00 2.14643 -90.9948 -2.14643 2.14643 0.04 0.000424487 0.000372936 0.00685813 0.00616631 -1 -1 -1 -1 12 186 21 646728 646728 19965.4 554.594 0.11 0.0652242 0.0564867 1696 3924 -1 174 15 217 480 10553 3153 2.17275 2.17275 -93.6282 -2.17275 0 0 25971.8 721.439 0.00 0.02 0.01 -1 -1 0.00 0.0180304 0.016231 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/config.txt new file mode 100644 index 00000000000..68fc81625c3 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/config.txt @@ -0,0 +1,35 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=alu4.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(alu4.pre-vpr.blif, device=mcnc_small) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(alu4.pre-vpr.blif, route_chan_width=70) + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --read_flat_place ../../../../constraints/old_placement.fplace --write_flat_place placement.fplace + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt new file mode 100644 index 00000000000..ce66e9945a6 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt @@ -0,0 +1,2 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 1.95 vpr 67.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 79 14 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69432 14 8 926 934 0 494 101 11 11 121 -1 mcnc_small 28.1 MiB 0.87 4705 3156 292 2673 191 67.8 MiB 0.15 0.01 4.69669 -33.5098 -4.69669 nan 0.00 0.00334751 0.00291356 0.0814872 0.072816 -1 -1 -1 -1 -1 6609 17 4.36541e+06 4.25763e+06 511363. 4226.14 0.32 0.279395 0.254136 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/constraints/old_placement.fplace b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/constraints/old_placement.fplace new file mode 100644 index 00000000000..6104318972c --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/constraints/old_placement.fplace @@ -0,0 +1,941 @@ +# Flat Placement File +# Auto-generated by VPR 9.0.0-dev+v8.0.0-12075-g53e90e62b-dirty +# Created: 2025-01-28T09:59:25 +# +# This file prints the following information for each atom in the netlist: +# # + +n523 6 8 0 0 3 #0 lut +n522 6 8 0 0 5 #0 lut +n520 6 8 0 0 2 #0 lut +n518 6 8 0 0 16 #0 lut +n454 6 8 0 0 4 #0 lut +n298 6 8 0 0 14 #0 lut +n214 6 8 0 0 2 #0 lut +n517 6 8 0 0 0 #0 lut +n49 6 8 0 0 9 #0 lut +n516 6 8 0 0 6 #0 lut +n48 6 8 0 0 15 #0 lut +o_4_ 6 8 0 0 1 #0 lut +n47 6 8 0 0 17 #0 lut +o_3_ 3 2 0 0 17 #1 lut +n168 3 2 0 0 2 #1 lut +n158 3 2 0 0 3 #1 lut +n157 3 2 0 0 2 #1 lut +n156 3 2 0 0 4 #1 lut +n154 3 2 0 0 5 #1 lut +n165 3 2 0 0 0 #1 lut +n113 3 2 0 0 13 #1 lut +n112 3 2 0 0 16 #1 lut +n108 3 2 0 0 15 #1 lut +n159 3 2 0 0 12 #1 lut +n107 3 2 0 0 9 #1 lut +n292 6 9 0 0 12 #2 lut +n291 6 9 0 0 5 #2 lut +n288 6 9 0 0 3 #2 lut +n287 6 9 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+n659 3 3 0 0 2 #62 lut +n607 3 3 0 0 4 #62 lut +n855 3 3 0 0 5 #62 lut +n777 3 3 0 0 17 #62 lut +n62 3 3 0 0 6 #62 lut +n788 9 5 0 0 8 #63 lut +n787 9 5 0 0 9 #63 lut +n643 9 5 0 0 2 #63 lut +n642 9 5 0 0 4 #63 lut +n638 9 5 0 0 6 #63 lut +n90 9 5 0 0 0 #63 lut +n641 9 5 0 0 4 #63 lut +n56 9 5 0 0 6 #63 lut +n637 9 5 0 0 5 #63 lut +n52 9 5 0 0 7 #63 lut +n925 1 5 0 0 3 #64 lut +n795 1 5 0 0 8 #64 lut +n924 1 5 0 0 2 #64 lut +n794 1 5 0 0 9 #64 lut +n386 1 5 0 0 2 #64 lut +n385 1 5 0 0 5 #64 lut +n307 1 5 0 0 0 #64 lut +n306 1 5 0 0 6 #64 lut +n576 1 5 0 0 4 #64 lut +n303 1 5 0 0 7 #64 lut +n824 4 6 0 0 2 #65 lut +n813 4 6 0 0 9 #65 lut +n670 4 6 0 0 3 #65 lut +n384 4 6 0 0 5 #65 lut +n132 4 6 0 0 4 #65 lut +n443 4 6 0 0 4 #65 lut +n92 4 6 0 0 6 #65 lut +n814 4 6 0 0 17 #65 lut +n177 4 6 0 0 0 #65 lut +n60 4 6 0 0 15 #65 lut +n817 1 7 0 0 8 #66 lut +n672 1 7 0 0 3 #66 lut +n671 1 7 0 0 2 #66 lut +n816 1 7 0 0 9 #66 lut +n673 1 7 0 0 4 #66 lut +n530 1 7 0 0 2 #66 lut +n834 1 7 0 0 5 #66 lut +n301 1 7 0 0 13 #66 lut +n300 1 7 0 0 0 #66 lut +n299 1 7 0 0 15 #66 lut +n830 4 1 0 0 9 #67 lut +n653 4 1 0 0 0 #67 lut +n614 4 1 0 0 4 #67 lut +n611 4 1 0 0 4 #67 lut +n585 4 1 0 0 3 #67 lut +n652 4 1 0 0 5 #67 lut +n496 4 1 0 0 13 #67 lut +n539 4 1 0 0 7 #67 lut +n396 4 1 0 0 2 #67 lut +n155 4 1 0 0 17 #67 lut +n781 8 3 0 0 0 #68 lut +n841 8 3 0 0 9 #68 lut +n646 8 3 0 0 8 #68 lut +n640 8 3 0 0 15 #68 lut +n493 8 3 0 0 2 #68 lut +n362 8 3 0 0 3 #68 lut +n345 8 3 0 0 2 #68 lut +n160 8 3 0 0 13 #68 lut +n656 8 3 0 0 4 #68 lut +n58 8 3 0 0 5 #68 lut +n900 7 5 0 0 8 #69 lut +n887 7 5 0 0 7 #69 lut +n885 7 5 0 0 9 #69 lut +n883 7 5 0 0 6 #69 lut +n890 7 5 0 0 0 #69 lut +n487 7 5 0 0 2 #69 lut +n368 7 5 0 0 5 #69 lut +n335 7 5 0 0 4 #69 lut +n179 7 5 0 0 3 #69 lut +n34 7 5 0 0 2 #69 lut +n599 6 1 0 0 3 #70 lut +n603 6 1 0 0 4 #70 lut +n408 6 1 0 0 7 #70 lut +n403 6 1 0 0 13 #70 lut +n597 6 1 0 0 2 #70 lut +n402 6 1 0 0 5 #70 lut +n873 6 1 0 0 12 #70 lut +n340 6 1 0 0 2 #70 lut +n575 6 1 0 0 8 #70 lut +n211 6 1 0 0 9 #70 lut +n190 6 1 0 0 0 #70 lut +n667 1 1 0 0 0 #71 lut +n660 1 1 0 0 2 #71 lut +n593 1 1 0 0 5 #71 lut +n584 1 1 0 0 3 #71 lut +n594 1 1 0 0 4 #71 lut +n581 1 1 0 0 8 #71 lut +n525 1 1 0 0 4 #71 lut +n315 1 1 0 0 7 #71 lut +n314 1 1 0 0 6 #71 lut +n313 1 1 0 0 9 #71 lut +n878 9 8 0 0 6 #72 lut +n875 9 8 0 0 2 #72 lut +n874 9 8 0 0 0 #72 lut +n872 9 8 0 0 4 #72 lut +n389 9 8 0 0 8 #72 lut +n383 9 8 0 0 9 #72 lut +n97 9 8 0 0 5 #72 lut +n88 9 8 0 0 8 #72 lut +n879 9 8 0 0 7 #72 lut +n86 9 8 0 0 6 #72 lut +n451 9 9 0 0 8 #73 lut +n632 9 9 0 0 5 #73 lut +n450 9 9 0 0 7 #73 lut +n445 9 9 0 0 6 #73 lut +n436 9 9 0 0 9 #73 lut +n536 2 2 0 0 17 #74 lut +n535 2 2 0 0 9 #74 lut +n169 2 2 0 0 4 #74 lut +n528 2 2 0 0 13 #74 lut +n125 2 2 0 0 0 #74 lut +n116 2 2 0 0 5 #74 lut +n544 2 2 0 0 7 #74 lut +n167 2 2 0 0 2 #74 lut +n115 2 2 0 0 5 #74 lut +n110 2 2 0 0 6 #74 lut +n473 2 2 0 0 1 #74 lut +n109 2 2 0 0 4 #74 lut +n639 9 4 0 0 5 #75 lut +n798 9 4 0 0 6 #75 lut +n629 9 4 0 0 9 #75 lut +n361 9 4 0 0 15 #75 lut +n349 9 4 0 0 17 #75 lut +n527 8 2 0 0 6 #76 lut +n254 8 2 0 0 17 #76 lut +n176 8 2 0 0 15 #76 lut +n76 8 2 0 0 9 #76 lut +n923 1 9 0 0 17 #77 lut +n268 1 9 0 0 19 #77 lut +out:o_3_ 3 0 0 4 0 #78 outpad +out:o_4_ 10 8 0 7 0 #79 outpad +out:o_5_ 3 0 0 3 0 #80 outpad +out:o_7_ 5 0 0 5 0 #81 outpad +out:o_2_ 8 0 0 3 0 #82 outpad +out:o_6_ 10 3 0 6 0 #83 outpad +out:o_1_ 7 0 0 5 0 #84 outpad +out:o_0_ 7 0 0 2 0 #85 outpad +i_0_ 5 0 0 0 0 #86 inpad +i_10_ 5 0 0 1 0 #87 inpad +i_11_ 6 0 0 0 0 #88 inpad +i_12_ 5 0 0 3 0 #89 inpad +i_13_ 4 0 0 1 0 #90 inpad +i_1_ 3 0 0 0 0 #91 inpad +i_2_ 5 0 0 2 0 #92 inpad +i_3_ 4 0 0 3 0 #93 inpad +i_4_ 5 0 0 6 0 #94 inpad +i_5_ 5 10 0 0 0 #95 inpad +i_6_ 5 0 0 4 0 #96 inpad +i_7_ 4 0 0 6 0 #97 inpad +i_8_ 5 0 0 7 0 #98 inpad +i_9_ 6 0 0 4 0 #99 inpad diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index f954a2b1702..e37401667f7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 13.56 vpr 77.04 MiB -1 -1 3.92 32680 16 0.60 -1 -1 34972 -1 -1 60 45 3 1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 78892 45 32 1192 1151 1 782 141 14 14 196 memory auto 38.2 MiB 2.96 6987 30885 8485 19109 3291 77.0 MiB 1.25 0.02 10.7872 -7159.4 -10.7872 10.7872 0.01 0.00497106 0.00453777 0.461478 0.422614 -1 -1 -1 -1 -1 10741 14 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 2.03 0.580473 0.527495 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 13.38 vpr 77.06 MiB -1 -1 3.60 32516 16 0.58 -1 -1 34992 -1 -1 60 45 3 1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 78912 45 32 1192 1151 1 782 141 14 14 196 memory auto 38.2 MiB 2.94 6987 30885 8485 19109 3291 77.1 MiB 1.04 0.01 10.7872 -7159.4 -10.7872 10.7872 0.00 0.00222077 0.00193155 0.339907 0.301027 -1 -1 -1 -1 -1 10825 14 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 2.22 0.417402 0.352766 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 11.85 vpr 79.08 MiB -1 -1 3.58 35500 16 0.65 -1 -1 38580 -1 -1 60 45 3 1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80980 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.0 MiB 3.23 6742 28689 8224 17037 3428 79.1 MiB 0.65 0.01 10.7103 -7090.32 -10.7103 10.7103 0.00 0.00310914 0.00279648 0.314019 0.270375 -1 -1 -1 -1 -1 10349 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.50 0.423776 0.367585 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 12.82 vpr 78.98 MiB -1 -1 3.48 35500 16 0.73 -1 -1 38088 -1 -1 60 45 3 1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80880 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.1 MiB 3.28 6742 28689 8224 17037 3428 79.0 MiB 0.59 0.01 10.7103 -7090.32 -10.7103 10.7103 0.00 0.00230907 0.0018852 0.209392 0.171163 -1 -1 -1 -1 -1 10313 15 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 2.42 0.342057 0.287674 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt index 24daf2d2e35..120190057e8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - shorted_flyover_wires.xml raygentop.v common 32.00 vpr 84.00 MiB -1 -1 4.94 43052 3 0.95 -1 -1 38056 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86016 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 43.4 MiB 3.67 13419 262125 90999 150942 20184 84.0 MiB 2.78 0.03 4.69737 -2831.91 -4.69737 4.69737 1.01 0.00832504 0.00776365 0.932353 0.847983 -1 -1 -1 -1 66 27201 39 1.65001e+07 9.87633e+06 1.15238e+06 3192.19 11.80 3.82946 3.48711 36241 234685 -1 22898 17 6143 16341 1829326 503243 5.28065 5.28065 -3148.98 -5.28065 0 0 1.43513e+06 3975.42 0.58 0.95 0.26 -1 -1 0.58 0.436495 0.407813 - buffered_flyover_wires.xml raygentop.v common 32.17 vpr 84.02 MiB -1 -1 4.60 43460 3 0.83 -1 -1 38072 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86032 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 43.3 MiB 3.46 14176 262125 95409 146838 19878 84.0 MiB 2.60 0.03 5.30111 -3035.02 -5.30111 5.30111 0.96 0.0108245 0.0101036 0.99455 0.909375 -1 -1 -1 -1 68 26718 29 1.65001e+07 9.87633e+06 1.22105e+06 3382.40 12.62 4.02255 3.63163 36601 236909 -1 22839 20 6287 16443 1625103 418922 5.52369 5.52369 -3272.68 -5.52369 0 0 1.52022e+06 4211.15 0.57 1.21 0.35 -1 -1 0.57 0.599325 0.559459 + shorted_flyover_wires.xml raygentop.v common 28.09 vpr 86.75 MiB -1 -1 4.22 45380 3 0.89 -1 -1 40652 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88832 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.9 MiB 3.72 13488 259154 85177 151229 22748 86.8 MiB 1.98 0.02 4.96832 -2863.05 -4.96832 4.96832 0.58 0.00616009 0.0056108 0.73686 0.651724 -1 -1 -1 -1 70 25183 26 1.65001e+07 9.87633e+06 1.20853e+06 3347.73 11.82 3.63311 3.252 37321 249029 -1 22818 16 6009 15172 1561129 440571 5.14889 5.14889 -3166.68 -5.14889 0 0 1.52253e+06 4217.55 0.11 0.96 0.44 -1 -1 0.11 0.466679 0.43649 + buffered_flyover_wires.xml raygentop.v common 23.51 vpr 86.14 MiB -1 -1 4.32 45316 3 0.90 -1 -1 40936 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88212 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.3 MiB 3.23 13888 238357 80681 139370 18306 86.1 MiB 2.42 0.04 5.12299 -3013.43 -5.12299 5.12299 0.55 0.0104225 0.00890059 0.853806 0.753587 -1 -1 -1 -1 68 27200 39 1.65001e+07 9.87633e+06 1.22105e+06 3382.40 7.94 3.27933 2.93318 36601 236909 -1 22538 20 6241 16122 1654804 449740 5.13382 5.13382 -3162.81 -5.13382 0 0 1.52022e+06 4211.15 0.06 0.81 0.27 -1 -1 0.06 0.458331 0.421893 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt index d0dca393ab5..dabc7597d44 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - hard_fpu_arch_timing.xml mm3.v common 7.03 vpr 62.24 MiB -1 -1 0.19 18436 1 0.05 -1 -1 30832 -1 -1 0 193 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63736 193 32 545 422 1 386 228 22 22 484 block_FPU auto 22.7 MiB 4.82 4750 57300 25032 31924 344 62.2 MiB 0.33 0.00 2.985 -849.007 -2.985 2.985 0.00 0.00155598 0.00146459 0.152665 0.144051 -1 -1 -1 -1 6282 16.3169 1670 4.33766 556 556 206642 56826 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -872.623 -2.985 -13.6498 -0.0851 0.35 -1 -1 62.2 MiB 0.08 0.182075 0.172086 62.2 MiB -1 0.64 + hard_fpu_arch_timing.xml mm3.v common 6.82 vpr 64.38 MiB -1 -1 0.19 22024 1 0.04 -1 -1 33832 -1 -1 0 193 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 65924 193 32 545 422 1 386 228 22 22 484 block_FPU auto 25.0 MiB 5.38 4984 53124 22938 29850 336 64.4 MiB 0.31 0.00 2.985 -851.626 -2.985 2.985 0.00 0.00244064 0.00235262 0.159831 0.149979 -1 -1 -1 -1 6456 16.7688 1716 4.45714 553 553 191807 53335 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -877.692 -2.985 -13.5705 -0.0851 0.36 -1 -1 64.4 MiB 0.06 0.186546 0.175569 64.4 MiB -1 0.10 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt index 6ed66139c02..e0477400548 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 5.17 vpr 65.73 MiB -1 -1 0.40 18728 3 0.11 -1 -1 33272 -1 -1 67 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67312 99 130 344 474 1 216 297 13 13 169 clb auto 26.0 MiB 1.28 607 28017 3739 9020 15258 65.7 MiB 0.15 0.02 36 1079 9 0 0 481804. 2850.91 1.81 + k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 4.15 vpr 68.14 MiB -1 -1 0.41 22436 3 0.11 -1 -1 37108 -1 -1 67 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69772 99 130 344 474 1 216 297 13 13 169 clb auto 28.7 MiB 1.30 640 27027 4243 10587 12197 68.1 MiB 0.05 0.00 34 1346 6 0 0 460544. 2725.11 1.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt index 2c9a5886623..cf73f2ff4e0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.10 vpr 63.56 MiB -1 -1 0.72 23528 5 0.17 -1 -1 33348 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65088 10 2 181 183 1 35 24 6 6 36 clb auto 24.1 MiB 0.05 146 398 72 298 28 63.6 MiB 0.05 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.00155607 0.00152058 0.00827603 0.00776724 -1 -1 -1 -1 -1 136 16 646728 646728 60312.4 1675.34 0.04 0.0269483 0.0244827 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.78 vpr 66.14 MiB -1 -1 0.81 27148 5 0.18 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67724 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000401166 0.00034964 0.00709766 0.00632609 -1 -1 -1 -1 -1 145 18 646728 646728 60312.4 1675.34 0.03 0.027091 0.0241271 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt index f44d6074687..f56e6001d52 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.57 vpr 58.03 MiB -1 -1 -1 -1 0 0.02 -1 -1 30200 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59420 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.3 MiB 0.01 0 3 0 0 3 58.0 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2173e-05 7.189e-06 7.7955e-05 5.3274e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00145604 0.00138979 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.57 vpr 58.07 MiB -1 -1 -1 -1 0 0.02 -1 -1 30092 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59460 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.3 MiB 0.01 0 3 0 0 3 58.1 MiB 0.00 0.00 nan 0 0 nan 0.00 1.3368e-05 7.369e-06 8.1255e-05 5.3678e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00262216 0.00254632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.53 vpr 58.11 MiB -1 -1 -1 -1 0 0.02 -1 -1 30152 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59500 6 1 1 8 0 1 8 3 3 9 -1 auto 19.7 MiB 0.00 0 21 0 10 11 58.1 MiB 0.05 0.00 nan 0 0 nan 0.00 1.3668e-05 8.295e-06 0.000103636 7.3136e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00159632 0.00148892 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.50 vpr 58.05 MiB -1 -1 -1 -1 0 0.02 -1 -1 30136 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59444 6 1 1 8 0 1 8 3 3 9 -1 auto 19.6 MiB 0.00 0 21 0 10 11 58.1 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2503e-05 7.349e-06 8.2367e-05 5.6036e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.0011854 0.00111648 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and.blif common 0.51 vpr 57.86 MiB -1 -1 -1 -1 1 0.02 -1 -1 30056 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59248 2 1 3 4 0 3 4 3 3 9 -1 auto 19.4 MiB 0.00 9 9 3 3 3 57.9 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.5257e-05 1.0806e-05 0.000104525 7.8851e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00149985 0.00142771 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.62 vpr 58.23 MiB -1 -1 -1 -1 1 0.07 -1 -1 31688 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59624 5 1 6 7 0 6 7 3 3 9 -1 auto 19.8 MiB 0.00 18 18 13 5 0 58.2 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.178e-05 1.692e-05 0.000145091 0.000118424 -1 -1 -1 -1 -1 7 11 53894 53894 38783.3 4309.26 0.01 0.00188984 0.00172965 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.63 vpr 58.03 MiB -1 -1 -1 -1 1 0.05 -1 -1 31992 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59424 5 1 6 7 0 6 7 3 3 9 -1 auto 19.6 MiB 0.00 18 18 13 5 0 58.0 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.9821e-05 1.4657e-05 0.000155383 0.000123574 -1 -1 -1 -1 -1 7 11 53894 53894 38783.3 4309.26 0.00 0.00187385 0.00170894 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and_latch.blif common 0.50 vpr 58.12 MiB -1 -1 -1 -1 1 0.02 -1 -1 29964 -1 -1 1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59512 3 1 5 6 1 4 5 3 3 9 -1 auto 19.7 MiB 0.00 9 12 7 1 4 58.1 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.7793e-05 1.322e-05 0.000136996 0.00010784 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00148392 0.00140511 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml false_path_mux.blif common 0.73 vpr 58.16 MiB -1 -1 -1 -1 1 0.06 -1 -1 32060 -1 -1 1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca 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0.000106148 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00195643 0.00179437 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_2x2.blif common 0.50 vpr 60.48 MiB -1 -1 -1 -1 1 0.05 -1 -1 35232 -1 -1 1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61928 4 4 8 12 0 8 9 3 3 9 -1 auto 22.1 MiB 0.00 24 27 18 6 3 60.5 MiB 0.00 0.00 0.67231 -2.68924 -0.67231 nan 0.00 5.0286e-05 3.8471e-05 0.00028724 0.000243111 -1 -1 -1 -1 -1 10 10 53894 53894 38783.3 4309.26 0.00 0.00268807 0.00242566 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_3x3.blif common 0.52 vpr 60.40 MiB -1 -1 -1 -1 1 0.07 -1 -1 36088 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61848 6 6 12 18 0 12 13 3 3 9 -1 auto 22.1 MiB 0.01 36 43 32 7 4 60.4 MiB 0.00 0.00 0.69831 -4.13786 -0.69831 nan 0.00 5.0007e-05 4.1034e-05 0.000382344 0.000335402 -1 -1 -1 -1 -1 17 12 53894 53894 38783.3 4309.26 0.00 0.00342842 0.00312147 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_3x4.blif common 0.46 vpr 60.50 MiB -1 -1 -1 -1 2 0.06 -1 -1 35480 -1 -1 3 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61952 7 8 22 30 0 15 18 4 4 16 clb auto 22.0 MiB 0.01 51 64 26 37 1 60.5 MiB 0.00 0.00 1.24888 -7.62396 -1.24888 nan 0.00 9.577e-05 8.3665e-05 0.00076909 0.000710256 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.00462233 0.00417537 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_4x4.blif common 0.59 vpr 60.60 MiB -1 -1 -1 -1 4 0.09 -1 -1 35628 -1 -1 2 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62056 8 8 29 37 0 21 18 4 4 16 clb auto 22.1 MiB 0.02 74 64 20 44 0 60.6 MiB 0.00 0.00 2.04839 -11.7951 -2.04839 nan 0.00 0.000130354 0.000112521 0.00109012 0.00100934 -1 -1 -1 -1 -1 53 12 215576 107788 99039.1 6189.95 0.01 0.00751475 0.0068714 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_5x5.blif common 0.62 vpr 61.08 MiB -1 -1 -1 -1 4 0.10 -1 -1 36048 -1 -1 4 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62548 10 10 47 57 0 39 24 4 4 16 clb auto 22.1 MiB 0.02 149 92 35 57 0 61.1 MiB 0.00 0.00 2.73035 -18.1288 -2.73035 nan 0.00 0.000192825 0.000170363 0.0016493 0.0015433 -1 -1 -1 -1 -1 123 10 215576 215576 99039.1 6189.95 0.01 0.00945092 0.00871858 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_5x6.blif common 0.78 vpr 61.08 MiB -1 -1 -1 -1 5 0.12 -1 -1 36408 -1 -1 5 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62544 11 11 61 72 0 51 27 5 5 25 clb auto 22.1 MiB 0.04 192 547 116 431 0 61.1 MiB 0.01 0.00 3.17925 -21.2667 -3.17925 nan 0.00 0.000440575 0.000406236 0.00673609 0.00616031 -1 -1 -1 -1 -1 163 16 485046 269470 186194. 7447.77 0.02 0.0214973 0.0195896 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_1bit.blif common 0.44 vpr 60.18 MiB -1 -1 -1 -1 1 0.05 -1 -1 34452 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61628 3 2 5 7 0 5 6 3 3 9 -1 auto 22.0 MiB 0.00 15 15 9 5 1 60.2 MiB 0.00 0.00 0.67231 -1.34462 -0.67231 nan 0.00 1.5359e-05 1.1242e-05 0.000119111 9.5167e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00191506 0.00178438 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_2bit.blif common 0.51 vpr 60.47 MiB -1 -1 -1 -1 1 0.06 -1 -1 35224 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61920 5 3 8 11 0 8 9 3 3 9 -1 auto 22.0 MiB 0.00 24 27 21 6 0 60.5 MiB 0.00 0.00 0.67231 -2.01693 -0.67231 nan 0.00 5.5301e-05 4.4627e-05 0.000313259 0.000267198 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00296269 0.00261801 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_3bit.blif common 0.50 vpr 60.56 MiB -1 -1 -1 -1 2 0.05 -1 -1 35444 -1 -1 1 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62016 7 4 12 16 0 11 12 3 3 9 -1 auto 22.1 MiB 0.01 33 38 24 11 3 60.6 MiB 0.00 0.00 1.08437 -4.00246 -1.08437 nan 0.00 2.6083e-05 2.0859e-05 0.000215587 0.000188913 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00234895 0.0022029 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_4bit.blif common 0.54 vpr 60.64 MiB -1 -1 -1 -1 2 0.06 -1 -1 35364 -1 -1 1 9 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62096 9 5 15 20 0 14 15 3 3 9 -1 auto 22.1 MiB 0.01 42 51 29 17 5 60.6 MiB 0.00 0.00 1.00731 -4.36655 -1.00731 nan 0.00 0.000111332 9.9634e-05 0.000559539 0.000502391 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.00 0.00351338 0.00318651 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_5bit.blif common 0.52 vpr 60.46 MiB -1 -1 -1 -1 3 0.07 -1 -1 35520 -1 -1 1 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 11 6 19 25 0 17 18 3 3 9 -1 auto 22.0 MiB 0.01 51 64 33 24 7 60.5 MiB 0.00 0.00 1.34231 -6.71386 -1.34231 nan 0.00 0.000697205 8.3358e-05 0.00115444 0.000499005 -1 -1 -1 -1 -1 25 11 53894 53894 38783.3 4309.26 0.00 0.00500091 0.00398839 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt index e60168a24fc..b020b50a0e5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.48 vpr 58.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59516 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.4 MiB 0.01 0 3 0 0 3 58.1 MiB 0.03 0.00 nan 0 0 nan 0.00 2.8167e-05 2.1374e-05 0.000138034 0.000104949 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.02 0.00164424 0.00155782 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.44 vpr 58.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59464 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.4 MiB 0.02 0 3 0 0 3 58.1 MiB 0.01 0.00 nan 0 0 nan 0.00 1.4897e-05 9.304e-06 0.000144669 0.000111339 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.001404 0.00131834 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.50 vpr 58.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59556 6 1 7 8 0 7 8 3 3 9 -1 auto 19.7 MiB 0.04 21 21 14 7 0 58.2 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4462e-05 1.7786e-05 0.000174928 0.000147981 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00186761 0.00178528 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.36 vpr 58.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59504 6 1 7 8 0 7 8 3 3 9 -1 auto 19.7 MiB 0.01 21 21 14 7 0 58.1 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 3.4347e-05 2.5128e-05 0.000218139 0.000181445 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.01 0.00178448 0.00167632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.46 vpr 58.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59532 5 1 6 7 0 6 7 3 3 9 -1 auto 19.7 MiB 0.03 18 18 13 5 0 58.1 MiB 0.01 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.2294e-05 1.7287e-05 0.000170669 0.000137343 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00177813 0.00167987 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.46 vpr 57.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59356 5 1 6 7 0 6 7 3 3 9 -1 auto 19.5 MiB 0.01 18 18 13 5 0 58.0 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.6482e-05 2.0958e-05 0.000167987 0.000138916 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00184976 0.00175645 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml const_true.blif common 0.27 vpr 60.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61896 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.1 MiB 0.00 0 3 0 0 3 60.4 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1967e-05 6.442e-06 7.5021e-05 4.7762e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.0014839 0.00141592 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml const_false.blif common 0.27 vpr 60.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62024 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.3 MiB 0.00 0 3 0 0 3 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2368e-05 6.553e-06 8.0604e-05 5.2726e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00150763 0.00143643 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml always_true.blif common 0.26 vpr 60.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62040 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4901e-05 1.736e-05 0.000158286 0.000127589 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00189837 0.00180984 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml always_false.blif common 0.27 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.5 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4603e-05 1.7125e-05 0.000156465 0.000123185 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00157342 0.00148859 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.34 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 5 1 6 7 0 6 7 3 3 9 -1 auto 22.3 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.3071e-05 1.7468e-05 0.00015565 0.000122418 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00131998 0.0012364 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.34 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 5 1 6 7 0 6 7 3 3 9 -1 auto 22.0 MiB 0.00 18 18 13 5 0 60.5 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4504e-05 1.843e-05 0.0003637 0.000327179 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00295184 0.00278863 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt index f1456d39f78..0122eef07c9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - x_gaussian_y_uniform.xml stereovision3.v common 2.50 vpr 64.46 MiB -1 -1 0.75 23544 5 0.17 -1 -1 33432 -1 -1 7 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66008 10 2 181 183 1 37 19 6 6 36 clb auto 24.9 MiB 0.12 134 94 36 51 7 64.5 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000419945 0.000386338 0.00436349 0.00416636 -1 -1 -1 -1 8 103 5 646728 377258 -1 -1 0.16 0.0505805 0.044298 1804 2280 -1 90 3 63 87 2113 862 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0115138 0.0109218 - x_uniform_y_gaussian.xml stereovision3.v common 2.93 vpr 64.41 MiB -1 -1 0.95 23552 5 0.18 -1 -1 33464 -1 -1 7 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65960 10 2 181 183 1 37 19 6 6 36 clb auto 25.0 MiB 0.12 118 444 110 303 31 64.4 MiB 0.10 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000424537 0.000389976 0.0151343 0.0142881 -1 -1 -1 -1 6 94 8 646728 377258 -1 -1 0.27 0.0803322 0.0718366 1804 2280 -1 80 4 81 108 2550 1058 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.04 0.00 -1 -1 0.00 0.0129948 0.0121942 - x_gaussian_y_gaussian.xml stereovision3.v common 2.83 vpr 64.50 MiB -1 -1 0.72 23552 5 0.18 -1 -1 33328 -1 -1 7 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66048 10 2 181 183 1 37 19 6 6 36 clb auto 25.0 MiB 0.11 136 619 179 400 40 64.5 MiB 0.04 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000378245 0.00034659 0.012211 0.0113438 -1 -1 -1 -1 6 97 4 646728 377258 -1 -1 0.43 0.0657561 0.0581881 1804 2280 -1 98 4 73 101 2523 1078 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0125128 0.0117068 - x_delta_y_uniform.xml stereovision3.v common 2.97 vpr 64.45 MiB -1 -1 0.81 23464 5 0.16 -1 -1 33468 -1 -1 7 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66000 10 2 181 183 1 37 19 6 6 36 clb auto 25.0 MiB 0.11 134 594 154 411 29 64.5 MiB 0.04 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000357443 0.000325029 0.012514 0.0116263 -1 -1 -1 -1 10 110 10 646728 377258 -1 -1 0.50 0.0892176 0.0778872 1804 2280 -1 97 3 69 90 2241 1045 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0105891 0.0100407 - x_delta_y_delta.xml stereovision3.v common 3.05 vpr 64.40 MiB -1 -1 0.95 23336 5 0.17 -1 -1 33436 -1 -1 7 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65948 10 2 181 183 1 37 19 6 6 36 clb auto 24.8 MiB 0.13 134 719 153 522 44 64.4 MiB 0.03 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.00034865 0.000319263 0.012511 0.0115452 -1 -1 -1 -1 28 92 3 646728 377258 -1 -1 0.31 0.0600241 0.0529562 1804 2280 -1 92 3 65 87 2209 903 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00975621 0.00926591 - x_uniform_y_delta.xml stereovision3.v common 3.23 vpr 64.80 MiB -1 -1 0.91 23548 5 0.16 -1 -1 33324 -1 -1 7 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66352 10 2 181 183 1 37 19 6 6 36 clb auto 25.3 MiB 0.17 122 594 108 447 39 64.8 MiB 0.05 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000523952 0.000483044 0.0169912 0.0158055 -1 -1 -1 -1 8 96 8 646728 377258 -1 -1 0.55 0.0887084 0.0783823 1804 2280 -1 82 4 82 115 2881 1166 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0137495 0.0129694 + x_gaussian_y_uniform.xml stereovision3.v common 2.14 vpr 66.94 MiB -1 -1 0.82 26648 5 0.18 -1 -1 36964 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68548 10 2 181 183 1 37 19 6 6 36 clb auto 27.8 MiB 0.08 154 69 23 41 5 66.9 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.00 0.000368162 0.000336195 0.00306832 0.0028942 -1 -1 -1 -1 8 112 5 646728 377258 -1 -1 0.14 0.0630721 0.0541641 1804 2280 -1 112 3 60 81 2140 1007 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0123441 0.0115171 + x_uniform_y_gaussian.xml stereovision3.v common 2.28 vpr 66.56 MiB -1 -1 0.87 27028 5 0.18 -1 -1 36836 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68156 10 2 181 183 1 37 19 6 6 36 clb auto 27.6 MiB 0.06 139 119 44 63 12 66.6 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000434392 0.000379213 0.00478977 0.00443186 -1 -1 -1 -1 8 108 4 646728 377258 -1 -1 0.14 0.0614636 0.053576 1804 2280 -1 92 5 93 129 3144 1427 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0131686 0.0124064 + x_gaussian_y_gaussian.xml stereovision3.v common 1.95 vpr 66.73 MiB -1 -1 0.78 27032 5 0.16 -1 -1 36964 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68336 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.07 141 69 21 42 6 66.7 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000231421 0.000200473 0.00279286 0.00262007 -1 -1 -1 -1 6 107 4 646728 377258 -1 -1 0.13 0.0525266 0.046082 1804 2280 -1 105 4 77 102 2777 1152 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.01 -1 -1 0.00 0.0109087 0.0101911 + x_delta_y_uniform.xml stereovision3.v common 2.13 vpr 66.94 MiB -1 -1 0.67 26768 5 0.15 -1 -1 36648 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68548 10 2 181 183 1 37 19 6 6 36 clb auto 27.8 MiB 0.07 154 369 96 253 20 66.9 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000435432 0.00038302 0.00911423 0.00823072 -1 -1 -1 -1 24 117 4 646728 377258 -1 -1 0.31 0.174316 0.150618 1804 2280 -1 116 2 59 79 2150 954 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0153537 0.0147732 + x_delta_y_delta.xml stereovision3.v common 2.28 vpr 66.92 MiB -1 -1 0.81 26892 5 0.18 -1 -1 36968 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68524 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.10 140 544 127 376 41 66.9 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000465798 0.000412818 0.0124105 0.0110487 -1 -1 -1 -1 48 106 2 646728 377258 -1 -1 0.23 0.117282 0.102085 1804 2280 -1 106 2 57 77 1975 772 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00952273 0.00912406 + x_uniform_y_delta.xml stereovision3.v common 2.20 vpr 66.74 MiB -1 -1 0.80 27028 5 0.22 -1 -1 36648 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68344 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.07 127 494 89 373 32 66.7 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000426768 0.000373257 0.0117897 0.0105633 -1 -1 -1 -1 14 88 2 646728 377258 -1 -1 0.16 0.10372 0.0914305 1804 2280 -1 88 2 57 77 1819 773 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00845179 0.00814396 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt index 5deaea47b22..93fc1046440 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_mem32K_40nm.xml stereovision3.v common 3.07 vpr 63.59 MiB -1 -1 0.86 23288 5 0.17 -1 -1 33328 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65116 10 2 181 183 1 35 24 6 6 36 clb auto 24.1 MiB 0.19 146 296 74 208 14 63.6 MiB 0.05 0.00 1.83894 -73.7881 -1.83894 1.83894 0.01 0.000559275 0.000518705 0.00642835 0.00601498 -1 -1 -1 -1 6 101 15 646728 646728 -1 -1 0.25 0.0569513 0.0489151 1456 2040 -1 103 15 135 292 9517 3756 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.08 0.00 -1 -1 0.00 0.020878 0.0186817 - nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 3.02 vpr 63.67 MiB -1 -1 0.85 23532 5 0.17 -1 -1 33404 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65196 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.17 168 92 36 52 4 63.7 MiB 0.03 0.00 1.83894 -73.7881 -1.83894 1.83894 0.01 0.000555491 0.000512753 0.00380765 0.00362071 -1 -1 -1 -1 8 118 19 646728 646728 -1 -1 0.31 0.0661579 0.056778 1456 2040 -1 117 17 137 275 9561 3757 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.07 0.00 -1 -1 0.00 0.019218 0.0171455 - nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 3.34 vpr 63.68 MiB -1 -1 0.88 23640 5 0.17 -1 -1 33452 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65212 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.11 166 92 33 54 5 63.7 MiB 0.01 0.00 1.83894 -73.7881 -1.83894 1.83894 0.01 0.000388369 0.000355547 0.00307054 0.00291066 -1 -1 -1 -1 6 122 17 646728 646728 -1 -1 0.56 0.0873244 0.0750472 1456 2040 -1 119 17 156 331 12004 4413 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.01 0.09 0.00 -1 -1 0.01 0.0185307 0.0163935 + timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.95 vpr 65.89 MiB -1 -1 0.73 26760 5 0.17 -1 -1 36900 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67476 10 2 181 183 1 35 24 6 6 36 clb auto 26.8 MiB 0.04 153 500 90 382 28 65.9 MiB 0.02 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000660248 0.000574242 0.010203 0.00905969 -1 -1 -1 -1 6 103 13 646728 646728 -1 -1 0.12 0.059948 0.0525698 1456 2040 -1 101 16 136 266 9131 3659 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0191372 0.0164753 + nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.99 vpr 66.10 MiB -1 -1 0.79 27276 5 0.17 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67688 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 148 466 75 365 26 66.1 MiB 0.01 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000394392 0.000346251 0.00742774 0.00666175 -1 -1 -1 -1 8 100 16 646728 646728 -1 -1 0.14 0.0718777 0.0632492 1456 2040 -1 101 19 134 278 9113 3613 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0163481 0.014725 + nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 2.10 vpr 66.14 MiB -1 -1 0.85 26896 5 0.16 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67728 10 2 181 183 1 35 24 6 6 36 clb auto 27.1 MiB 0.05 142 500 108 364 28 66.1 MiB 0.02 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000538248 0.000486042 0.00902515 0.00805903 -1 -1 -1 -1 4 86 10 646728 646728 -1 -1 0.05 0.0281105 0.0249862 1456 2040 -1 87 9 108 188 5936 2196 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0153203 0.0141626 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt index e3c0e629bee..afb5b419a6b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 6.64 vpr 63.57 MiB -1 -1 0.94 23536 5 0.18 -1 -1 33400 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65096 10 2 181 183 1 35 24 6 6 36 clb auto 24.1 MiB 0.12 146 398 72 298 28 63.6 MiB 2.11 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.000561388 0.000519811 0.00818763 0.0076223 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 1.07 0.0306154 0.0272041 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 5.23 vpr 66.07 MiB -1 -1 0.81 27256 5 0.19 -1 -1 36672 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67656 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 1.88 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000389361 0.000337837 0.00712682 0.00635643 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.83 0.023313 0.0208517 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt index e14d1bfdf94..0cf367e9bdb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml stereovision3.v common 3.07 vpr 59.20 MiB -1 -1 0.88 23388 5 0.18 -1 -1 33556 -1 -1 7 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60616 10 2 181 183 1 37 19 5 5 25 clb auto 19.7 MiB 0.15 121 1025 805 184 36 59.2 MiB 0.09 0.00 2.09443 -87.1664 -2.09443 2.09443 0.03 0.000344616 0.000312911 0.0199094 0.0182425 -1 -1 -1 -1 26 127 8 485046 377258 31702.9 1268.11 0.17 0.0666235 0.0582058 1731 5512 -1 104 4 50 68 870 379 1.97939 1.97939 -86.3228 -1.97939 0 0 38596.5 1543.86 0.01 0.02 0.01 -1 -1 0.01 0.0131087 0.0124132 + k6_frac_N10_40nm.xml stereovision3.v common 1.89 vpr 61.52 MiB -1 -1 0.73 27008 5 0.16 -1 -1 36840 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63000 10 2 181 183 1 37 19 5 5 25 clb auto 22.0 MiB 0.06 123 1025 767 190 68 61.5 MiB 0.03 0.00 2.0306 -84.8829 -2.0306 2.0306 0.02 0.000393487 0.000346106 0.0203419 0.0179997 -1 -1 -1 -1 24 106 9 485046 377258 28445.8 1137.83 0.08 0.0705347 0.0617863 1707 5297 -1 110 10 80 114 1470 618 1.99984 1.99984 -90.3874 -1.99984 0 0 37126.9 1485.07 0.00 0.02 0.01 -1 -1 0.00 0.0158626 0.0146013 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt index 9aed323e6ef..891302c2b5a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm.xml diffeq.blif common 16.80 vpr 68.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70624 64 39 1935 1974 1 1077 541 23 23 529 clb auto 28.7 MiB 0.57 10085 137127 36539 98027 2561 69.0 MiB 1.34 0.02 7.41831 -1418.64 -7.41831 7.41831 0.90 0.00601444 0.00513019 0.406605 0.350409 -1 -1 -1 -1 22 12754 28 983127 976439 735934. 1391.18 8.73 1.26384 1.10229 35322 121345 -1 11109 19 6608 23845 1462488 382373 7.14816 7.14816 -1474.13 -7.14816 0 0 927497. 1753.30 0.22 1.14 0.18 -1 -1 0.22 0.297141 0.268933 - k4_N4_90nm.xml ex5p.blif common 33.10 vpr 64.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66128 8 63 1072 1135 0 894 437 22 22 484 clb auto 25.2 MiB 0.53 11802 104828 31007 71723 2098 64.6 MiB 1.03 0.01 6.54351 -290.193 -6.54351 nan 0.84 0.00302532 0.00273057 0.23164 0.202551 -1 -1 -1 -1 34 15886 35 891726 815929 1.00654e+06 2079.64 26.00 1.17739 1.02035 45600 169672 -1 13479 18 7616 26985 2968727 818222 6.43932 nan -293.77 -6.43932 0 0 1.27783e+06 2640.15 0.27 1.08 0.23 -1 -1 0.27 0.174257 0.159401 - k4_N4_90nm.xml s298.blif common 59.37 vpr 70.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 72572 4 6 1942 1948 1 1169 590 27 27 729 clb auto 30.8 MiB 0.71 13579 163808 47993 114862 953 70.9 MiB 1.54 0.02 12.0403 -94.3066 -12.0403 12.0403 1.19 0.00712795 0.00624279 0.42831 0.361816 -1 -1 -1 -1 24 19358 45 1.39333e+06 1.29301e+06 1.12265e+06 1539.99 49.71 2.08623 1.76329 54650 192211 -1 16862 23 9147 49878 4855038 894292 11.751 11.751 -96.5615 -11.751 0 0 1.47093e+06 2017.74 0.23 1.67 0.23 -1 -1 0.23 0.291349 0.252446 + k4_N4_90nm.xml diffeq.blif common 17.21 vpr 71.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72880 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.3 MiB 0.39 10472 141533 36950 100839 3744 71.2 MiB 1.37 0.02 7.46482 -1369.01 -7.46482 7.46482 0.56 0.00521343 0.00460525 0.3928 0.329697 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.35 2.1497 1.85535 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.84 0.19 -1 -1 0.04 0.261179 0.233132 + k4_N4_90nm.xml ex5p.blif common 19.31 vpr 67.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68632 8 63 1072 1135 0 894 437 22 22 484 clb auto 27.6 MiB 0.35 12004 99857 28319 69545 1993 67.0 MiB 0.94 0.02 6.86459 -313.968 -6.86459 nan 0.53 0.00337095 0.00291084 0.218826 0.187023 -1 -1 -1 -1 32 16530 34 891726 815929 949946. 1962.70 13.54 0.813128 0.698644 43920 162796 -1 14048 22 8455 31174 3329435 847924 6.8764 nan -316.234 -6.8764 0 0 1.22393e+06 2528.78 0.07 1.22 0.29 -1 -1 0.07 0.185657 0.165735 + k4_N4_90nm.xml s298.blif common 16.74 vpr 73.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 75068 4 6 1942 1948 1 1169 590 27 27 729 clb auto 33.1 MiB 0.44 13813 156389 45768 109723 898 73.3 MiB 1.71 0.02 12.2682 -96.384 -12.2682 12.2682 0.97 0.00611806 0.00498358 0.468986 0.387941 -1 -1 -1 -1 26 17490 32 1.39333e+06 1.29301e+06 1.22387e+06 1678.84 9.00 1.38473 1.15574 57250 204657 -1 16420 17 8603 42614 3232268 684840 12.0598 12.0598 -95.4975 -12.0598 0 0 1.55812e+06 2137.34 0.09 1.18 0.31 -1 -1 0.09 0.19019 0.169418 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt index 7488fc485ca..639ae9a9ce5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.06 vpr 66.74 MiB -1 -1 0.84 23300 4 0.16 -1 -1 33000 -1 -1 15 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68340 11 2 303 283 2 81 28 7 7 49 clb auto 27.1 MiB 0.31 332 112 32 50 30 66.7 MiB 0.08 0.00 4.11769 0 0 3.94108 0.00 0.000680828 0.000618524 0.00645732 0.00621036 -1 -1 -1 -1 376 5.01333 137 1.82667 145 200 4055 1170 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.1682 4.01568 0 0 -197.816 -1.707 0.03 -1 -1 66.7 MiB 0.25 0.145887 0.141249 66.7 MiB -1 0.06 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.46 vpr 69.17 MiB -1 -1 0.83 26540 4 0.20 -1 -1 36184 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70832 11 2 303 283 2 81 28 7 7 49 clb auto 29.7 MiB 0.25 337 112 35 48 29 69.2 MiB 0.02 0.00 4.0728 0 0 3.92737 0.00 0.00065953 0.000573934 0.00619824 0.00583905 -1 -1 -1 -1 399 5.32000 131 1.74667 151 217 4511 1215 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.15796 4.01977 0 0 -197.842 -1.707 0.05 -1 -1 69.2 MiB 0.12 0.1152 0.11141 69.2 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index d1daf36ffe7..7e566048732 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.07141 -1 1.37913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.30941 -1 -1.86724 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.07141 -1 1.37913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.30941 -1 -1.86724 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt index 3c39979a687..4db4b05c471 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 4.77 vpr 65.80 MiB -1 -1 0.46 18964 3 0.10 -1 -1 33220 -1 -1 65 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67380 99 130 344 474 1 215 295 12 12 144 clb auto 26.4 MiB 0.23 697 24820 2926 7450 14444 65.8 MiB 0.12 0.00 34 1759 11 5.66058e+06 4.05111e+06 317980. 2208.19 1.87 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 3.05 vpr 68.36 MiB -1 -1 0.39 22432 3 0.12 -1 -1 36928 -1 -1 65 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70000 99 130 344 474 1 215 295 12 12 144 clb auto 29.2 MiB 0.19 685 24820 3391 8404 13025 68.4 MiB 0.05 0.00 32 1772 8 5.66058e+06 4.05111e+06 305575. 2122.05 1.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt index 5c92701e534..59b02c3fd0e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links - stratixiv_arch.timing_small_with_a_embedded_mesh_noc_toplogy.xml complex_2_noc_1D_chain.blif complex_2_noc_1D_chain.flows common 136.64 vpr 1.09 GiB -1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1147416 2 32 2204 1661 1 1102 107 36 20 720 -1 EP4SGX110 953.4 MiB 4.30 6502 9974 2102 7079 793 1120.5 MiB 0.78 0.01 7.29374 -4454.07 -7.29374 7.29374 29.53 0.00640333 0.00571002 0.281115 0.249799 150 8929 16 0 0 6.74655e+06 9370.21 54.95 2.8097 2.42985 174956 1462490 -1 8744 15 2461 4687 960144 259555 7.40783 7.40783 -4699.44 -7.40783 0 0 8.72662e+06 12120.3 4.44 0.55 3.61 -1 -1 4.44 0.254443 0.230607 400000 3e-09 1 4.1359e-25 0 0 0 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch.timing_small_with_a_embedded_mesh_noc_toplogy.xml complex_2_noc_1D_chain.blif complex_2_noc_1D_chain.flows common 104.06 vpr 1.07 GiB -1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1126272 2 32 2204 1661 1 1102 107 36 20 720 -1 EP4SGX110 955.6 MiB 4.04 6649 10733 2374 7396 963 1099.9 MiB 0.85 0.01 7.22684 -4978.81 -7.22684 7.22684 14.03 0.00387297 0.00336653 0.329346 0.282395 154 8599 14 0 0 6.94291e+06 9642.93 42.85 2.6403 2.32523 176404 1494154 -1 8630 10 2443 4554 1083511 308854 7.50808 7.50808 -5329.84 -7.50808 0 0 8.91809e+06 12386.2 1.07 0.65 2.72 -1 -1 1.07 0.27806 0.251316 400000 3e-09 1 4.1359e-25 0 0 0 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt index 09ce4f7b64a..b67a185d189 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.38 vpr 63.50 MiB -1 -1 0.79 23456 5 0.18 -1 -1 33376 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65028 10 2 181 183 1 35 24 6 6 36 clb auto 24.1 MiB 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00186374 0.00181229 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.76 vpr 66.03 MiB -1 -1 0.86 26892 5 0.18 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67612 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00186164 0.0017947 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt index 2f29f949e72..153be88f8d6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.49 vpr 63.62 MiB -1 -1 0.85 23572 5 0.18 -1 -1 33320 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65152 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.25 146 398 72 298 28 63.6 MiB 0.11 0.00 2.14643 -92.7521 -2.14643 2.14643 0.05 0.000375851 0.000345018 0.00764954 0.00711987 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00935215 0.00877834 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.90 vpr 66.02 MiB -1 -1 0.83 26896 5 0.19 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 66.0 MiB 0.01 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000402396 0.000353615 0.00726063 0.00647248 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00909673 0.00824277 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt index 52d01e58538..6e6ab2e273c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml mult_5x6.blif common 2.12 vpr 58.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60124 11 11 59 70 0 48 26 4 4 16 clb auto 19.3 MiB 0.07 179 634 146 488 0 58.7 MiB 0.01 0.00 2.51353 -20.6332 -2.51353 nan 0.01 0.00020518 0.000188419 0.00473406 0.00439686 -1 -1 -1 -1 30 199 15 215576 215576 18771.3 1173.21 1.07 0.0644809 0.0550317 1016 3020 -1 198 17 257 591 8958 4396 2.73234 nan -23.1489 -2.73234 0 0 22855.5 1428.47 0.00 0.22 0.00 -1 -1 0.00 0.0209741 0.0195805 - k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.15 vpr 21.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 21948 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 19.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_5x6.blif common 0.60 vpr 60.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62244 11 11 59 70 0 48 26 4 4 16 clb auto 22.1 MiB 0.03 179 862 260 602 0 60.8 MiB 0.02 0.00 2.46139 -19.889 -2.46139 nan 0.01 0.000312912 0.000279273 0.00803541 0.00727675 -1 -1 -1 -1 28 244 41 215576 215576 17602.3 1100.14 0.11 0.0569851 0.0502764 984 2821 -1 165 13 220 476 6314 3099 2.61613 nan -21.1174 -2.61613 0 0 21084.5 1317.78 0.00 0.01 0.00 -1 -1 0.00 0.0102047 0.00933765 + k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.06 vpr 23.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 23944 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 22.3 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt index 1a1be87df70..12efb65ec8c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml reg_4x32.blif common 2.20 vpr 75.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 32 33 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 77140 33 32 161 193 1 65 97 34 34 1156 -1 32x32 18.7 MiB 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00189505 0.0018502 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml reg_4x32.blif common 2.54 vpr 77.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 32 33 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78852 33 32 161 193 1 65 97 34 34 1156 -1 32x32 21.4 MiB 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00178122 0.0017245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt index 93476cb3715..87ace76c192 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common 0.28 vpr 62.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63844 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 20 30 10 17 3 62.3 MiB 0.01 0.00 0.645658 -3.51726 -0.645658 0.571 0.02 7.06e-05 5.5105e-05 0.00193417 0.00186411 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00193417 0.00186411 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml multiclock.blif common 0.20 vpr 64.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66472 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 21 30 9 19 2 64.9 MiB 0.00 0.00 0.646042 -3.51892 -0.646042 0.571 0.01 4.3045e-05 2.9263e-05 0.00159366 0.001524 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00159366 0.001524 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt index 9c0fd9e92e6..8361bf1bfe6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 38.42 vpr 976.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999804 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.55 370 858 95 697 66 976.4 MiB 0.06 0.00 6.45248 -69.1493 -6.45248 6.45248 3.16 0.00053133 0.000484838 0.0148989 0.0138589 -1 -1 -1 -1 32 693 33 0 0 122746. 1394.84 1.72 0.145798 0.129504 11830 34246 -1 570 10 235 725 56242 26416 6.94346 6.94346 -73.9579 -6.94346 0 0 164688. 1871.45 0.06 0.06 0.09 -1 -1 0.06 0.0256172 0.0239212 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 37.07 vpr 976.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999876 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.61 369 812 82 656 74 976.4 MiB 0.07 0.00 6.45248 -69.2479 -6.45248 6.45248 3.14 0.000419744 0.000381717 0.0118947 0.0110676 -1 -1 -1 -1 32 691 29 0 0 153433. 1743.56 1.12 0.12258 0.110164 11830 34246 -1 553 12 224 697 51846 24062 6.94346 6.94346 -73.4811 -6.94346 0 0 205860. 2339.32 0.05 0.07 0.09 -1 -1 0.05 0.0274519 0.0254462 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 41.11 vpr 976.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999784 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.79 370 812 89 663 60 976.4 MiB 0.12 0.00 6.52191 -68.7563 -6.52191 6.52191 4.09 0.000672013 0.000608225 0.017378 0.0162156 -1 -1 -1 -1 22 809 21 0 0 110609. 1256.92 2.28 0.128845 0.11551 11258 24748 -1 663 14 329 1173 67735 35710 7.04515 7.04515 -76.4932 -7.04515 0 0 134428. 1527.59 0.03 0.08 0.06 -1 -1 0.03 0.0372941 0.0337267 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 42.24 vpr 976.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1000000 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.76 368 812 95 656 61 976.6 MiB 0.15 0.00 6.34478 -68.8031 -6.34478 6.34478 4.44 0.000492867 0.000449805 0.0183566 0.017188 -1 -1 -1 -1 28 753 22 0 0 134428. 1527.59 1.92 0.132649 0.118834 11590 29630 -1 624 15 260 959 55378 26467 6.64742 6.64742 -72.827 -6.64742 0 0 173354. 1969.93 0.03 0.07 0.08 -1 -1 0.03 0.0270531 0.0242418 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 38.75 vpr 978.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001760 10 10 168 178 1 68 30 11 8 88 io auto 955.3 MiB 0.46 364 858 131 680 47 978.3 MiB 0.06 0.00 6.37129 -69.6808 -6.37129 6.37129 1.81 0.000551403 0.000481676 0.0153225 0.013705 -1 -1 -1 -1 22 874 22 0 0 110609. 1256.92 1.54 0.247666 0.215864 11258 24748 -1 728 16 428 1746 95453 49745 6.73416 6.73416 -75.7525 -6.73416 0 0 134428. 1527.59 0.01 0.08 0.07 -1 -1 0.01 0.0332471 0.0304495 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 37.57 vpr 978.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001868 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.66 371 950 121 778 51 978.4 MiB 0.07 0.00 6.34606 -69.4373 -6.34606 6.34606 2.32 0.000744808 0.000651566 0.0166971 0.0148799 -1 -1 -1 -1 32 654 12 0 0 153433. 1743.56 0.90 0.149648 0.129506 11830 34246 -1 601 15 249 896 54680 24076 6.61838 6.61838 -74.0379 -6.61838 0 0 205860. 2339.32 0.01 0.07 0.09 -1 -1 0.01 0.0346715 0.0320467 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 34.09 vpr 978.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001652 10 10 168 178 1 68 30 11 8 88 io auto 955.4 MiB 0.44 376 582 74 468 40 978.2 MiB 0.07 0.00 6.26487 -68.7007 -6.26487 6.26487 2.74 0.000593656 0.000520243 0.0126605 0.0115382 -1 -1 -1 -1 28 858 45 0 0 134428. 1527.59 1.21 0.206409 0.180557 11590 29630 -1 614 14 305 1283 69506 33247 6.72367 6.72367 -73.5822 -6.72367 0 0 173354. 1969.93 0.01 0.08 0.06 -1 -1 0.01 0.0327372 0.0302784 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 41.01 vpr 978.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002252 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.60 352 582 88 454 40 978.8 MiB 0.05 0.00 6.37106 -69.2764 -6.37106 6.37106 3.17 0.000446168 0.000388088 0.0115458 0.0104844 -1 -1 -1 -1 22 778 22 0 0 110609. 1256.92 1.84 0.253098 0.220545 11258 24748 -1 690 15 386 1546 88347 46120 6.75259 6.75259 -75.6874 -6.75259 0 0 134428. 1527.59 0.01 0.08 0.06 -1 -1 0.01 0.0310233 0.0286671 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt index c5f45b0d4e3..10a6cf257aa 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 42.58 vpr 976.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999900 10 10 168 178 1 68 30 11 8 88 io auto 953.3 MiB 0.70 393 628 105 491 32 976.5 MiB 0.15 0.00 6.51193 -69.1178 -6.51193 6.51193 3.23 0.00078609 0.000724519 0.016967 0.01616 -1 -1 -1 -1 20 893 28 0 0 100248. 1139.18 2.16 0.139573 0.124569 11180 23751 -1 831 19 496 1987 121384 60113 6.91414 6.91414 -78.1319 -6.91414 0 0 150556. 1710.86 0.03 0.09 0.06 -1 -1 0.03 0.0325178 0.0296648 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 41.59 vpr 976.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999880 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.80 380 628 91 496 41 976.4 MiB 0.26 0.02 6.52338 -69.1003 -6.52338 6.52338 3.25 0.000777298 0.000711005 0.0177546 0.0168625 -1 -1 -1 -1 30 673 12 0 0 144567. 1642.81 1.66 0.128557 0.114566 11730 32605 -1 585 9 216 698 45031 21119 6.8993 6.8993 -73.7008 -6.8993 0 0 194014. 2204.70 0.05 0.06 0.09 -1 -1 0.05 0.0224124 0.0206008 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 36.65 vpr 978.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002024 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.61 385 628 76 517 35 978.5 MiB 0.06 0.00 6.37842 -68.9926 -6.37842 6.37842 2.33 0.000579422 0.00050489 0.0121495 0.01103 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.00 0.197686 0.174013 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.07 0.08 -1 -1 0.01 0.0316604 0.0292377 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 28.63 vpr 978.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001964 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.43 356 628 86 501 41 978.5 MiB 0.06 0.00 6.32784 -69.1369 -6.32784 6.32784 1.45 0.000300815 0.000260189 0.00775385 0.00704586 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 0.78 0.12183 0.106239 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.07 0.04 -1 -1 0.01 0.0278034 0.0259211 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt index 4d6fe9605d7..bee9bf5e15f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml ex5p.blif common_--place_effort_scaling_circuit 4.34 vpr 74.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76080 8 63 1072 1135 0 619 135 12 12 144 clb auto 34.4 MiB 2.45 6183 12245 2318 9041 886 74.3 MiB 0.46 0.01 4.99539 -218.829 -4.99539 nan 0.40 0.00339822 0.00308909 0.174455 0.155138 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.182343 0.1625 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 4.15 vpr 74.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76000 8 63 1072 1135 0 619 135 12 12 144 clb auto 34.1 MiB 2.35 6325 11326 2120 8412 794 74.2 MiB 0.45 0.01 4.96391 -216.681 -4.96391 nan 0.40 0.00300248 0.00261681 0.177754 0.159055 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.182191 0.163076 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 9.98 vpr 77.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 79808 8 63 1072 1135 0 619 135 27 27 729 -1 auto 34.4 MiB 2.36 6780 22625 6869 14375 1381 77.7 MiB 0.66 0.01 5.57619 -254.596 -5.57619 nan 3.15 0.00374551 0.00316871 0.28525 0.251728 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.292957 0.259025 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 10.88 vpr 77.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 79852 8 63 1072 1135 0 619 135 27 27 729 -1 auto 34.5 MiB 2.52 6916 70425 20372 45422 4631 77.9 MiB 1.04 0.02 5.61138 -254.037 -5.61138 nan 3.20 0.00355764 0.00324002 0.259461 0.229263 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.264477 0.233757 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_circuit 3.66 vpr 76.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78656 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.7 MiB 2.32 6246 12245 2336 8854 1055 76.8 MiB 0.39 0.01 4.93521 -218.151 -4.93521 nan 0.22 0.00367856 0.00299064 0.169598 0.144286 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.174334 0.148491 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 3.50 vpr 76.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78400 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.21 6248 12409 2316 9051 1042 76.6 MiB 0.36 0.01 5.00015 -217.921 -5.00015 nan 0.26 0.00350625 0.00296092 0.150187 0.130251 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.154752 0.13448 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 4.86 vpr 76.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78576 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.5 MiB 1.80 6557 16051 3559 11939 553 76.7 MiB 0.46 0.01 5.39652 -231.823 -5.39652 nan 1.19 0.00333577 0.00278218 0.186781 0.161087 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.19137 0.165152 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 7.27 vpr 76.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78592 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.7 MiB 2.48 6642 53385 10847 39555 2983 76.8 MiB 0.94 0.01 5.30857 -236.309 -5.30857 nan 1.66 0.00199214 0.00171649 0.207463 0.177518 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.212761 0.182102 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt index 8ddf2cd268a..344063856f9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 4.32 vpr 63.63 MiB -1 -1 0.91 23516 5 0.18 -1 -1 33320 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65160 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.14 146 398 72 298 28 63.6 MiB 0.15 0.00 2.14643 -92.7521 -2.14643 2.14643 0.05 0.000721287 0.000665617 0.0100883 0.00940276 -1 -1 -1 -1 14 201 20 646728 646728 22986.6 638.518 0.96 0.149763 0.124804 1728 4488 -1 171 15 208 442 9451 2845 2.12882 2.12882 -98.7664 -2.12882 0 0 30529.5 848.041 0.01 0.05 0.01 -1 -1 0.01 0.0189304 0.0169003 + k6_N10_mem32K_40nm.xml stereovision3.v common 2.31 vpr 66.14 MiB -1 -1 0.81 26892 5 0.20 -1 -1 36924 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67732 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 152 432 67 335 30 66.1 MiB 0.02 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000410176 0.000357432 0.00947888 0.00721552 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.10 0.0626682 0.052856 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.02 0.01 -1 -1 0.00 0.0168161 0.0151469 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt index 9a08c839075..a4fadd34b2c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.68 vpr 60.19 MiB -1 -1 -1 -1 0 0.02 -1 -1 30040 -1 -1 1 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61636 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.4 MiB 0.03 0 3 0 0 3 60.2 MiB 0.01 0.00 nan 0 0 nan 0.00 1.2311e-05 7.387e-06 0.000105834 7.5869e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00147816 0.00140463 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.71 vpr 60.08 MiB -1 -1 -1 -1 0 0.02 -1 -1 30088 -1 -1 1 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61524 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.4 MiB 0.04 0 3 0 0 3 60.1 MiB 0.03 0.00 nan 0 0 nan 0.00 3.6044e-05 2.4593e-05 0.000145604 0.000105582 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.02 0.00162472 0.00153314 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.73 vpr 60.18 MiB -1 -1 -1 -1 0 0.02 -1 -1 30176 -1 -1 1 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61624 6 1 1 8 0 1 8 3 3 9 -1 auto 21.4 MiB 0.04 0 21 0 11 10 60.2 MiB 0.04 0.00 nan 0 0 nan 0.00 3.8303e-05 2.7095e-05 0.000158699 0.000117087 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.02 0.00160603 0.0015131 -1 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2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61912 2 1 3 4 0 3 4 3 3 9 -1 auto 21.8 MiB 0.03 9 9 5 0 4 60.5 MiB 0.03 0.00 0.443777 -0.443777 -0.443777 nan 0.00 2.6924e-05 2.1285e-05 0.000155957 0.000124557 -1 -1 -1 -1 -1 6 9 3900 3900 7855.82 872.868 0.04 0.00180691 0.00163332 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.92 vpr 60.15 MiB -1 -1 -1 -1 2 0.06 -1 -1 31604 -1 -1 1 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61592 5 1 7 8 0 7 7 3 3 9 -1 auto 21.4 MiB 0.05 20 18 12 0 6 60.1 MiB 0.05 0.00 0.70303 -0.70303 -0.70303 nan 0.00 4.3879e-05 3.664e-05 0.000222358 0.000185667 -1 -1 -1 -1 -1 8 6 3900 3900 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3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64220 3 2 5 7 0 5 6 3 3 9 -1 auto 24.3 MiB 0.00 15 15 11 0 4 62.7 MiB 0.00 0.00 0.443777 -0.887553 -0.443777 nan 0.00 2.4709e-05 1.8183e-05 0.000141351 0.000109437 -1 -1 -1 -1 -1 12 16 3900 3900 7855.82 872.868 0.00 0.00207041 0.0018628 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.46 vpr 62.58 MiB -1 -1 -1 -1 2 0.06 -1 -1 35476 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64084 5 3 9 12 0 9 9 3 3 9 -1 auto 24.2 MiB 0.00 26 27 24 0 3 62.6 MiB 0.00 0.00 0.70303 -1.84984 -0.70303 nan 0.00 3.6085e-05 2.9105e-05 0.000215176 0.00018047 -1 -1 -1 -1 -1 19 17 3900 3900 7855.82 872.868 0.00 0.0027146 0.00242632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.58 vpr 62.59 MiB -1 -1 -1 -1 3 0.05 -1 -1 35528 -1 -1 1 7 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 7 4 13 17 0 13 12 3 3 9 -1 auto 24.2 MiB 0.01 37 38 34 0 4 62.6 MiB 0.00 0.00 0.962283 -3.07137 -0.962283 nan 0.00 5.1242e-05 4.3365e-05 0.000310909 0.00026784 -1 -1 -1 -1 -1 42 19 3900 3900 7855.82 872.868 0.01 0.00339296 0.00299342 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.56 vpr 62.59 MiB -1 -1 -1 -1 4 0.06 -1 -1 35528 -1 -1 1 9 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 9 5 17 22 0 17 15 3 3 9 -1 auto 24.2 MiB 0.01 48 51 43 0 8 62.6 MiB 0.00 0.00 1.22154 -4.55216 -1.22154 nan 0.00 5.8362e-05 4.9699e-05 0.000357643 0.000314843 -1 -1 -1 -1 -1 65 18 3900 3900 7855.82 872.868 0.01 0.00442103 0.00396409 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.68 vpr 62.61 MiB -1 -1 -1 -1 4 0.06 -1 -1 35388 -1 -1 2 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64108 11 6 24 30 0 24 19 4 4 16 clb auto 24.2 MiB 0.02 81 219 59 138 22 62.6 MiB 0.00 0.00 1.3375 -6.59285 -1.3375 nan 0.00 7.7083e-05 6.6497e-05 0.00098279 0.000856632 -1 -1 -1 -1 -1 132 15 7800 7800 17482.0 1092.63 0.01 0.00598903 0.00545622 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt index d710f9093cf..def1a137d22 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 7.34 vpr 66.08 MiB -1 -1 0.43 18936 3 0.11 -1 -1 33284 -1 53192 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67664 99 130 344 474 1 227 298 12 12 144 clb auto 26.4 MiB 0.38 717 72933 22876 34411 15646 66.1 MiB 0.54 0.01 1.84343 -118.171 -1.84343 1.84343 0.36 0.0010848 0.00101841 0.0913793 0.0860775 -1 -1 -1 -1 38 1552 14 5.66058e+06 4.21279e+06 319130. 2216.18 2.91 0.450493 0.414934 12522 62564 -1 1267 9 391 595 24204 7116 1.90841 1.90841 -134.254 -1.90841 -1.28606 -0.31945 406292. 2821.48 0.13 0.07 0.08 -1 -1 0.13 0.0328333 0.030834 0.0117 0.2242 0.06563 0.7102 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 17.64 vpr 68.80 MiB -1 -1 0.70 23848 15 0.45 -1 -1 34524 -1 54788 39 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70452 162 96 1009 950 1 701 302 16 16 256 mult_36 auto 29.4 MiB 0.77 5637 94418 33826 53640 6952 68.8 MiB 0.97 0.01 21.0535 -1600.99 -21.0535 21.0535 0.77 0.00355871 0.00332925 0.362999 0.339534 -1 -1 -1 -1 50 13462 45 1.21132e+07 4.08187e+06 780512. 3048.87 8.60 1.322 1.21904 25484 153448 -1 9971 18 3407 6810 971785 294758 22.3056 22.3056 -1729.57 -22.3056 0 0 1.00276e+06 3917.05 0.33 0.44 0.17 -1 -1 0.33 0.14631 0.136022 0.007875 0.3522 0.01635 0.6315 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.05 vpr 68.39 MiB -1 -1 0.40 21908 3 0.11 -1 -1 37048 -1 54888 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70028 99 130 344 474 1 227 298 12 12 144 clb auto 29.0 MiB 0.23 673 63978 19550 30341 14087 68.4 MiB 0.26 0.00 1.86472 -118.834 -1.86472 1.86472 0.28 0.000886976 0.000801272 0.0813306 0.0745016 -1 -1 -1 -1 38 1393 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.68 0.238994 0.21577 12522 62564 -1 1106 10 397 647 21454 6807 1.90702 1.90702 -131.595 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.03 0.05 0.11 -1 -1 0.03 0.0347348 0.0326652 0.01152 0.2117 0.0667 0.7216 + k6_frac_N10_mem32K_40nm.xml diffeq1.v common 11.51 vpr 71.63 MiB -1 -1 0.57 27156 15 0.44 -1 -1 38000 -1 56764 39 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73348 162 96 1009 950 1 701 302 16 16 256 mult_36 auto 32.3 MiB 0.47 5553 86322 27524 51152 7646 71.6 MiB 0.85 0.01 20.9417 -1607.93 -20.9417 20.9417 0.48 0.003704 0.00340296 0.38455 0.354826 -1 -1 -1 -1 50 10993 26 1.21132e+07 4.08187e+06 780512. 3048.87 3.85 1.2672 1.17071 25484 153448 -1 9617 17 3054 6060 825747 253645 22.1678 22.1678 -1734.75 -22.1678 0 0 1.00276e+06 3917.05 0.06 0.43 0.25 -1 -1 0.06 0.181388 0.170418 0.007894 0.3513 0.0164 0.6323 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt index 0b0e8c245c9..82620e51799 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.71 vpr 63.64 MiB -1 -1 0.89 23420 5 0.17 -1 -1 33392 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65172 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.10 146 398 72 298 28 63.6 MiB 0.06 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.000418181 0.00038256 0.0070167 0.00650899 -1 -1 -1 -1 130 4.06250 54 1.68750 215 509 15144 2919 646728 646728 138825. 3856.24 24 3164 19284 -1 2.05191 2.05191 -93.8814 -2.05191 0 0 0.02 -1 -1 63.6 MiB 0.24 0.0355426 0.0317424 63.6 MiB -1 0.03 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.97 vpr 66.65 MiB -1 -1 0.84 23052 4 0.17 -1 -1 33056 -1 -1 15 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68248 11 2 303 283 2 78 28 7 7 49 clb auto 27.1 MiB 0.31 264 1036 209 767 60 66.6 MiB 0.17 0.00 2.03811 -163.536 -2.03811 1.90043 0.00 0.0010174 0.000936861 0.0267115 0.0245008 -1 -1 -1 -1 252 3.50000 103 1.43056 122 199 4265 1218 1.07788e+06 808410 219490. 4479.39 12 5100 32136 -1 2.11264 1.93889 -160.659 -2.11264 0 0 0.04 -1 -1 66.6 MiB 0.15 0.0627365 0.0575288 66.6 MiB -1 0.04 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.71 vpr 65.87 MiB -1 -1 0.78 26896 5 0.18 -1 -1 36624 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67448 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 65.9 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.00039706 0.000346093 0.00713489 0.00637234 -1 -1 -1 -1 138 4.31250 57 1.78125 181 343 11634 2077 646728 646728 138825. 3856.24 15 3164 19284 -1 2.14648 2.14648 -94.9192 -2.14648 0 0 0.03 -1 -1 65.9 MiB 0.02 0.0245431 0.0219785 65.9 MiB -1 0.00 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.90 vpr 68.91 MiB -1 -1 0.73 26796 4 0.18 -1 -1 36100 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70560 11 2 303 283 2 78 28 7 7 49 clb auto 29.2 MiB 0.18 285 784 175 539 70 68.9 MiB 0.03 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000657098 0.000563918 0.0210266 0.0187872 -1 -1 -1 -1 313 4.34722 112 1.55556 114 177 3842 1019 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.07112 1.86791 -165.31 -2.07112 0 0 0.05 -1 -1 68.9 MiB 0.03 0.0456598 0.0418503 68.9 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt index 447a074d109..b3939ae8bad 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 46.36 vpr 82.59 MiB -1 -1 8.22 52832 5 2.16 -1 -1 39584 -1 -1 153 193 5 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 84572 193 205 2718 2652 1 1312 556 20 20 400 memory auto 41.4 MiB 2.16 10365 229056 86247 118235 24574 82.3 MiB 2.34 0.03 4.93042 -2712.69 -4.93042 4.93042 1.49 0.00671843 0.00610927 0.880709 0.785571 -1 -1 -1 -1 82 19408 37 2.07112e+07 1.09858e+07 2.14661e+06 5366.52 23.21 5.08072 4.56727 53670 456392 -1 17785 16 4760 12593 961685 215487 5.25964 5.25964 -2873.25 -5.25964 -10.2812 -0.29768 2.68822e+06 6720.56 0.74 0.58 0.45 -1 -1 0.74 0.348182 0.32009 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 40.08 vpr 84.36 MiB -1 -1 7.36 54308 5 2.17 -1 -1 42700 -1 -1 153 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 86380 193 205 2718 2652 1 1312 556 20 20 400 memory auto 43.4 MiB 2.10 10543 233626 82676 126206 24744 84.4 MiB 2.58 0.04 4.85425 -2733.64 -4.85425 4.85425 0.83 0.0094896 0.008538 0.955143 0.814553 -1 -1 -1 -1 76 20844 34 2.07112e+07 1.09858e+07 2.02110e+06 5052.76 19.63 4.86995 4.26704 52074 423490 -1 18742 17 4982 13549 1088379 246430 5.27071 5.27071 -2903.22 -5.27071 -6.49744 -0.292146 2.51807e+06 6295.18 0.11 0.70 0.57 -1 -1 0.11 0.429237 0.387696 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt index 3029284bb73..b2a77a6f0e1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 2.47 vpr 69.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70748 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.54 4989 14482 2605 10909 968 69.1 MiB 0.33 0.01 4.15324 -188.164 -4.15324 nan 0.00 0.00355218 0.00311968 0.123812 0.109233 -1 -1 -1 -1 6805 14.9560 1830 4.02198 3625 14263 570126 87469 9.20055e+06 4.79657e+06 867065. 4423.80 19 18088 133656 -1 4.17843 nan -185.467 -4.17843 0 0 0.15 -1 -1 69.1 MiB 0.41 0.278836 0.250118 69.1 MiB -1 0.28 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 2.71 vpr 69.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70728 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.58 4989 14482 2605 10909 968 69.1 MiB 0.30 0.01 4.15324 -188.164 -4.15324 nan 0.00 0.00262291 0.00213676 0.106954 0.095917 -1 -1 -1 -1 6877 15.1143 1848 4.06154 3712 14523 564432 88116 9.20055e+06 4.79657e+06 867065. 4423.80 19 18088 133656 -1 4.14924 nan -185.7 -4.14924 0 0 0.14 -1 -1 69.1 MiB 0.44 0.258375 0.232966 69.1 MiB -1 0.34 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.71 vpr 71.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73312 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.45 4992 14048 2664 10357 1027 71.6 MiB 0.29 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00333844 0.00278407 0.128199 0.109732 -1 -1 -1 -1 6642 14.5978 1787 3.92747 3214 12750 489499 77791 9.20055e+06 4.79657e+06 867065. 4423.80 16 18088 133656 -1 4.47188 nan -188.808 -4.47188 0 0 0.21 -1 -1 71.6 MiB 0.30 0.276888 0.244984 71.6 MiB -1 0.05 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 1.81 vpr 71.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73256 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.47 4992 14048 2664 10357 1027 71.5 MiB 0.31 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00291779 0.00252096 0.133598 0.1169 -1 -1 -1 -1 6701 14.7275 1794 3.94286 3137 12291 459530 73860 9.20055e+06 4.79657e+06 867065. 4423.80 18 18088 133656 -1 4.41143 nan -186.654 -4.41143 0 0 0.20 -1 -1 71.5 MiB 0.31 0.289515 0.258703 71.5 MiB -1 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt index 15eaa3bf41e..f0bed076f05 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 2.55 vpr 69.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70784 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.60 4981 18388 4106 12671 1611 69.1 MiB 0.49 0.01 3.67827 -162.703 -3.67827 nan 0.04 0.00317376 0.00278185 0.166614 0.146475 -1 -1 -1 -1 6929 15.2286 1856 4.07912 4031 16057 1191599 209386 9.20055e+06 4.79657e+06 701736. 3580.29 21 16332 105598 -1 4.26894 nan -186.127 -4.26894 0 0 0.09 -1 -1 69.1 MiB 0.54 0.351918 0.315357 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 2.62 vpr 69.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70684 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.61 4947 14048 2843 10376 829 69.0 MiB 0.36 0.01 4.36787 -194.851 -4.36787 nan 0.00 0.00347735 0.00296792 0.131799 0.115232 -1 -1 -1 -1 7013 15.4132 1882 4.13626 4368 18266 702728 114564 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.35011 nan -200.403 -4.35011 0 0 0.11 -1 -1 69.0 MiB 0.50 0.320884 0.285698 69.0 MiB -1 0.23 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 3.96 vpr 69.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70868 8 63 748 811 0 455 160 14 14 196 clb auto 29.7 MiB 0.63 4953 17954 4036 12536 1382 69.2 MiB 0.51 0.01 3.75278 -163.938 -3.75278 nan 0.07 0.00355287 0.00313746 0.160864 0.141994 -1 -1 -1 -1 7096 15.5956 1936 4.25495 3839 15635 1250449 222869 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.31984 nan -190.626 -4.31984 0 0 0.09 -1 -1 69.2 MiB 0.68 0.350893 0.31266 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.84 vpr 69.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70800 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.60 4953 17954 4036 12536 1382 69.1 MiB 0.45 0.01 3.75278 -163.938 -3.75278 nan 0.07 0.00233095 0.00207468 0.141454 0.125813 -1 -1 -1 -1 7096 15.5956 1936 4.25495 3839 15635 1250449 222869 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.31984 nan -190.626 -4.31984 0 0 0.12 -1 -1 69.1 MiB 0.66 0.321273 0.286755 -1 -1 -1 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.89 vpr 71.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73344 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.50 4993 17086 3593 12286 1207 71.6 MiB 0.32 0.01 3.65588 -160.421 -3.65588 nan 0.04 0.00302942 0.00252731 0.141328 0.121812 -1 -1 -1 -1 7077 15.5538 1900 4.17582 3821 15130 1125339 197021 9.20055e+06 4.79657e+06 701736. 3580.29 19 16332 105598 -1 4.24547 nan -186.357 -4.24547 0 0 0.15 -1 -1 71.6 MiB 0.43 0.306494 0.271472 -1 -1 -1 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.75 vpr 71.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73176 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.38 4933 15350 2970 11325 1055 71.5 MiB 0.31 0.01 4.27873 -192.837 -4.27873 nan 0.00 0.00317678 0.00277359 0.137596 0.118868 -1 -1 -1 -1 7099 15.6022 1898 4.17143 3600 14045 536072 90036 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.46795 nan -200.148 -4.46795 0 0 0.16 -1 -1 71.5 MiB 0.37 0.319312 0.282053 71.5 MiB -1 0.04 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 3.41 vpr 71.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73128 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.50 5048 17520 3917 12196 1407 71.4 MiB 0.28 0.01 3.77945 -168.167 -3.77945 nan 0.06 0.00517556 0.0043803 0.123856 0.107999 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.14 -1 -1 71.4 MiB 0.56 0.3503 0.312891 -1 -1 -1 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.58 vpr 71.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73184 8 63 748 811 0 455 160 14 14 196 clb auto 31.7 MiB 0.45 5048 17520 3917 12196 1407 71.5 MiB 0.35 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.00283082 0.00243406 0.152931 0.13159 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.10 -1 -1 71.5 MiB 0.60 0.372321 0.328664 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt index 85f2b790a31..2e384423539 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 2.44 vpr 69.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70664 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.60 5081 14916 3009 10977 930 69.0 MiB 0.47 0.01 4.4281 -198.501 -4.4281 nan 0.00 0.00389538 0.00357453 0.140004 0.12435 -1 -1 -1 -1 6741 14.8154 1803 3.96264 3315 13570 497205 81432 9.20055e+06 4.79657e+06 787177. 4016.21 19 17112 118924 -1 4.40099 nan -202.066 -4.40099 0 0 0.12 -1 -1 69.0 MiB 0.33 0.283749 0.254966 69.0 MiB -1 0.26 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 2.38 vpr 69.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70672 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.61 5081 14916 3009 10977 930 69.0 MiB 0.41 0.01 4.4281 -198.501 -4.4281 nan 0.00 0.00305314 0.00262997 0.138499 0.118452 -1 -1 -1 -1 6767 14.8725 1813 3.98462 3295 13377 489418 80231 9.20055e+06 4.79657e+06 787177. 4016.21 18 17112 118924 -1 4.40099 nan -201.997 -4.40099 0 0 0.13 -1 -1 69.0 MiB 0.39 0.297323 0.263941 69.0 MiB -1 0.24 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 1.81 vpr 71.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72996 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.46 5066 14916 2828 10927 1161 71.3 MiB 0.27 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00329282 0.00274638 0.115858 0.0987687 -1 -1 -1 -1 6988 15.3582 1874 4.11868 3892 16491 596262 97679 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.23403 nan -187.789 -4.23403 0 0 0.17 -1 -1 71.3 MiB 0.40 0.297064 0.262289 71.3 MiB -1 0.03 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 1.90 vpr 71.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72932 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.47 5066 14916 2828 10927 1161 71.2 MiB 0.34 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00295504 0.00249967 0.137157 0.115922 -1 -1 -1 -1 6949 15.2725 1858 4.08352 3794 15906 573229 94207 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.30087 nan -188.544 -4.30087 0 0 0.16 -1 -1 71.2 MiB 0.41 0.334676 0.294068 71.2 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt index cee3d6a8fdb..dda3cef9fb9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 4.82 vpr 64.82 MiB -1 -1 0.15 17544 1 0.06 -1 -1 32228 -1 -1 2 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66372 6 1 16 17 2 10 9 17 17 289 -1 auto 26.1 MiB 0.03 30 162 45 109 8 64.8 MiB 0.09 0.00 1.4327 -4.13089 -1.4327 0.805 0.87 0.000186474 0.000145053 0.00220998 0.00182998 -1 -1 -1 -1 20 95 2 1.34605e+07 107788 411619. 1424.29 0.70 0.00469902 0.00412949 24098 82050 -1 103 2 14 14 8039 3790 2.67718 0.805 -5.78255 -2.67718 -1.39285 -0.696976 535376. 1852.51 0.22 0.33 0.08 -1 -1 0.22 0.00213527 0.00203038 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 3.09 vpr 64.87 MiB -1 -1 0.11 17384 1 0.02 -1 -1 29996 -1 -1 1 3 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66428 3 1 5 6 1 4 5 13 13 169 -1 auto 26.1 MiB 0.03 35 12 3 8 1 64.9 MiB 0.01 0.00 1.12186 -1.54831 -1.12186 1.12186 0.48 2.8473e-05 2.3109e-05 0.000199018 0.000164788 -1 -1 -1 -1 20 62 1 6.63067e+06 53894 227243. 1344.63 0.37 0.00185586 0.00172162 13251 44387 -1 55 1 4 4 2056 1112 1.77078 1.77078 -1.77078 -1.77078 -0.365681 -0.365681 294987. 1745.49 0.10 0.18 0.05 -1 -1 0.10 0.00158341 0.00153323 0 4 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 4.83 vpr 64.72 MiB -1 -1 0.13 17592 1 0.07 -1 -1 32164 -1 -1 2 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66272 6 1 16 17 2 10 9 17 17 289 -1 auto 25.9 MiB 0.02 30 162 45 109 8 64.7 MiB 0.09 0.00 1.43377 -4.13192 -1.43377 0.805 0.93 6.1161e-05 4.7651e-05 0.00173334 0.0014267 -1 -1 -1 -1 20 96 2 1.34605e+07 107788 424167. 1467.71 0.63 0.00414802 0.00366881 24098 84646 -1 93 2 14 14 7618 3614 2.36211 0.805 -5.14799 -2.36211 -1.39063 -0.695869 547923. 1895.93 0.21 0.32 0.08 -1 -1 0.21 0.00216645 0.00203322 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 3.02 vpr 64.86 MiB -1 -1 0.13 17428 1 0.02 -1 -1 30016 -1 -1 1 3 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66416 3 1 5 6 1 4 5 13 13 169 -1 auto 26.2 MiB 0.03 35 12 3 8 1 64.9 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.48 2.3262e-05 1.8246e-05 0.000166554 0.000134906 -1 -1 -1 -1 20 58 1 6.63067e+06 53894 235789. 1395.20 0.40 0.00173302 0.00160946 13251 46155 -1 59 1 4 4 2248 1144 1.92085 1.92085 -1.92085 -1.92085 -0.365681 -0.365681 303533. 1796.05 0.09 0.18 0.05 -1 -1 0.09 0.00168955 0.00163685 0 4 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 4.88 vpr 64.75 MiB -1 -1 0.14 17432 1 0.06 -1 -1 32172 -1 -1 2 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66304 6 1 16 17 2 10 9 17 17 289 -1 auto 26.0 MiB 0.03 30 162 45 109 8 64.8 MiB 0.09 0.00 1.4327 -4.13089 -1.4327 0.805 0.92 0.000151459 0.00012099 0.0026464 0.00223102 -1 -1 -1 -1 20 573 2 1.34605e+07 107788 408865. 1414.76 0.67 0.00496297 0.0043779 24098 82150 -1 581 2 13 13 6255 3245 3.57936 0.805 -7.58692 -3.57936 -3.19721 -1.59916 532630. 1843.01 0.22 0.36 0.10 -1 -1 0.22 0.00223048 0.00210515 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 3.10 vpr 64.75 MiB -1 -1 0.15 17324 1 0.02 -1 -1 29932 -1 -1 1 3 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66308 3 1 5 6 1 4 5 13 13 169 -1 auto 26.0 MiB 0.03 35 12 3 8 1 64.8 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.46 2.059e-05 1.5632e-05 0.000148678 0.000118416 -1 -1 -1 -1 20 193 1 6.63067e+06 53894 225153. 1332.26 0.49 0.00184377 0.00171779 13251 44463 -1 186 1 4 4 914 327 2.39001 2.39001 -2.39001 -2.39001 -0.984912 -0.984912 292904. 1733.16 0.11 0.20 0.07 -1 -1 0.11 0.00185429 0.00178578 0 4 + timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.94 vpr 67.28 MiB -1 -1 0.14 21160 1 0.06 -1 -1 35568 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68892 6 1 16 17 2 10 9 17 17 289 -1 auto 28.8 MiB 0.03 30 162 45 109 8 67.3 MiB 0.00 0.00 1.4327 -4.13089 -1.4327 0.805 0.60 4.7388e-05 3.614e-05 0.00109694 0.000865862 -1 -1 -1 -1 20 95 2 1.34605e+07 107788 411619. 1424.29 0.37 0.00363015 0.00323679 24098 82050 -1 103 2 14 14 8045 3790 2.67718 0.805 -5.78255 -2.67718 -1.39285 -0.696976 535376. 1852.51 0.04 0.16 0.10 -1 -1 0.04 0.00205247 0.00194107 1 9 + timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.71 vpr 67.09 MiB -1 -1 0.11 20776 1 0.02 -1 -1 33508 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68696 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.1 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.29 2.6273e-05 2.0281e-05 0.000147698 0.000116195 -1 -1 -1 -1 20 62 1 6.63067e+06 53894 227243. 1344.63 0.21 0.00195838 0.00183532 13251 44387 -1 55 1 4 4 2060 1116 1.77078 1.77078 -1.77078 -1.77078 -0.365681 -0.365681 294987. 1745.49 0.02 0.09 0.06 -1 -1 0.02 0.00158307 0.00153637 0 4 + timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.80 vpr 67.12 MiB -1 -1 0.13 21160 1 0.05 -1 -1 35572 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68728 6 1 16 17 2 10 9 17 17 289 -1 auto 28.7 MiB 0.01 30 162 45 109 8 67.1 MiB 0.00 0.00 1.43377 -4.13192 -1.43377 0.805 0.60 4.8373e-05 3.7154e-05 0.00108209 0.000859607 -1 -1 -1 -1 20 96 2 1.34605e+07 107788 424167. 1467.71 0.36 0.00311589 0.00272737 24098 84646 -1 93 2 14 14 7618 3614 2.36211 0.805 -5.14799 -2.36211 -1.39063 -0.695869 547923. 1895.93 0.04 0.17 0.12 -1 -1 0.04 0.00220953 0.00209751 1 9 + timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.66 vpr 67.09 MiB -1 -1 0.12 20904 1 0.02 -1 -1 33532 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68696 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.1 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.23 2.2312e-05 1.624e-05 0.000140559 0.000108632 -1 -1 -1 -1 20 58 1 6.63067e+06 53894 235789. 1395.20 0.22 0.00172037 0.00159801 13251 46155 -1 59 1 4 4 2248 1144 1.92085 1.92085 -1.92085 -1.92085 -0.365681 -0.365681 303533. 1796.05 0.02 0.10 0.07 -1 -1 0.02 0.00161749 0.00156481 0 4 + timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.79 vpr 67.18 MiB -1 -1 0.14 20780 1 0.06 -1 -1 35568 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68788 6 1 16 17 2 10 9 17 17 289 -1 auto 28.9 MiB 0.02 30 162 45 109 8 67.2 MiB 0.00 0.00 1.4327 -4.13089 -1.4327 0.805 0.52 4.3023e-05 3.3348e-05 0.0010817 0.000870707 -1 -1 -1 -1 20 573 2 1.34605e+07 107788 408865. 1414.76 0.27 0.00353152 0.00316566 24098 82150 -1 581 2 13 13 6290 3262 3.57936 0.805 -7.58692 -3.57936 -3.19721 -1.59916 532630. 1843.01 0.04 0.17 0.11 -1 -1 0.04 0.00234323 0.00223031 1 9 + timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.63 vpr 67.17 MiB -1 -1 0.08 21164 1 0.02 -1 -1 33664 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68780 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.2 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.27 1.6733e-05 1.1353e-05 0.00024751 0.000102039 -1 -1 -1 -1 20 193 1 6.63067e+06 53894 225153. 1332.26 0.23 0.00204227 0.00181801 13251 44463 -1 186 1 4 4 914 327 2.39001 2.39001 -2.39001 -2.39001 -0.984912 -0.984912 292904. 1733.16 0.02 0.07 0.05 -1 -1 0.02 0.00162703 0.00157897 0 4 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt index b0a1541d4c4..5c6245f2fa3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - slicem.xml carry_chain.blif common 1.93 vpr 57.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58880 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 18.4 MiB 0.26 70 15 2 12 1 57.5 MiB 0.04 0.00 0.645672 -5.8162 -0.645672 0.645672 0.02 0.000258504 0.000238009 0.00107156 0.000998425 -1 -1 -1 -1 25 294 14 133321 74067 -1 -1 0.87 0.0364979 0.0304333 1252 5405 -1 287 14 116 116 21465 12891 1.98076 1.98076 -20.8107 -1.98076 0 0 -1 -1 0.01 0.05 0.01 -1 -1 0.01 0.00555954 0.00497644 + slicem.xml carry_chain.blif common 0.74 vpr 59.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61260 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 21.1 MiB 0.24 70 15 4 10 1 59.8 MiB 0.00 0.00 0.532448 -5.19346 -0.532448 0.532448 0.00 0.000194851 0.000170942 0.00110293 0.00100939 -1 -1 -1 -1 27 263 12 133321 74067 -1 -1 0.15 0.0230545 0.019405 1284 5874 -1 260 8 79 79 17257 10064 1.64234 1.64234 -16.7917 -1.64234 0 0 -1 -1 0.00 0.01 0.01 -1 -1 0.00 0.0047943 0.00439499 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt index ee663247acc..bcdd78ccdb6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml ndff.blif common 0.79 vpr 56.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58108 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 17.9 MiB 0.01 31 35 6 27 2 56.7 MiB 0.00 0.00 0.212927 -2.22016 -0.212927 0.212927 0.00 3.8012e-05 2.9599e-05 0.000219444 0.000180809 -1 -1 -1 -1 4 28 4 59253.6 44440.2 -1 -1 0.12 0.00506904 0.00414914 184 632 -1 29 2 13 18 795 367 0.309802 0.309802 -2.85512 -0.309802 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.00167546 0.00160294 + arch.xml ndff.blif common 0.33 vpr 58.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60252 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 20.2 MiB 0.00 31 59 13 43 3 58.8 MiB 0.00 0.00 0.247067 -2.25231 -0.247067 0.247067 0.00 3.7056e-05 2.9732e-05 0.000307367 0.000251846 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00402393 0.00331535 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00212051 0.00200433 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt index 71d0a37b2c3..07d413f9696 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.29 vpr 66.64 MiB -1 -1 0.68 22960 4 0.18 -1 -1 33204 -1 -1 15 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68244 11 2 303 283 2 81 28 7 7 49 clb auto 27.0 MiB 0.32 332 112 32 50 30 66.6 MiB 0.02 0.00 4.11769 0 0 3.94108 0.00 0.000730069 0.000683064 0.00633623 0.00608273 -1 -1 -1 -1 376 5.01333 137 1.82667 100 150 2999 863 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.1682 4.01568 0 0 -197.816 -1.707 0.04 -1 -1 66.6 MiB 0.02 0.0267422 0.0255335 66.6 MiB -1 0.04 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.89 vpr 69.17 MiB -1 -1 0.74 26544 4 0.19 -1 -1 36136 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70832 11 2 303 283 2 81 28 7 7 49 clb auto 29.7 MiB 0.19 337 112 35 48 29 69.2 MiB 0.02 0.00 4.0728 0 0 3.92737 0.00 0.000817884 0.000697618 0.00655739 0.00606976 -1 -1 -1 -1 398 5.30667 131 1.74667 104 164 3400 907 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.15796 4.01977 0 0 -197.842 -1.707 0.05 -1 -1 69.2 MiB 0.01 0.0209255 0.0197757 69.2 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/config.txt index 3aafacaeaa9..440149973b7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/config.txt @@ -24,7 +24,7 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt # Script parameters -script_params_common = -starting_stage vpr --seed 1 +script_params_common = -starting_stage vpr --seed 6 script_params_list_add = -sdc_file sdc/samples/A.sdc script_params_list_add = -sdc_file sdc/samples/B.sdc script_params_list_add = -sdc_file sdc/samples/C.sdc diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index b4860612047..4625b2401ff 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.62 vpr 62.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64392 5 3 11 14 2 9 10 4 4 16 clb auto 24.2 MiB 0.01 22 30 9 14 7 62.9 MiB 0.01 0.00 0.814339 -2.77068 -0.814339 0.571 0.01 3.5189e-05 2.7933e-05 0.00027775 0.00023103 -1 -1 -1 -1 8 18 2 107788 107788 4794.78 299.674 0.02 0.00211257 0.00195587 564 862 -1 18 4 10 10 199 87 0.757297 0.571 -2.63894 -0.757297 0 0 5401.54 337.596 0.01 0.05 0.00 -1 -1 0.01 0.00199426 0.00185344 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.74 vpr 62.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64480 5 3 11 14 2 9 10 4 4 16 clb auto 24.2 MiB 0.01 23 30 6 15 9 63.0 MiB 0.00 0.00 0.571 0 0 0.571 0.01 2.8611e-05 2.2607e-05 0.000202208 0.00017077 -1 -1 -1 -1 8 26 3 107788 107788 4794.78 299.674 0.01 0.0028111 0.00267833 564 862 -1 25 5 13 13 435 272 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.05 0.01 -1 -1 0.00 0.00202607 0.00188727 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.80 vpr 63.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64684 5 3 11 14 2 9 10 4 4 16 clb auto 24.5 MiB 0.05 20 30 10 18 2 63.2 MiB 0.01 0.00 0.645658 -2.18842 -0.645658 0.571 0.02 4.2927e-05 3.0224e-05 0.000271182 0.000205133 -1 -1 -1 -1 8 17 3 107788 107788 4794.78 299.674 0.01 0.00218974 0.00197452 564 862 -1 14 5 15 15 285 110 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.02 0.00 -1 -1 0.00 0.00202523 0.00186469 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.73 vpr 62.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64348 5 3 11 14 2 9 10 4 4 16 clb auto 24.1 MiB 0.04 20 30 12 17 1 62.8 MiB 0.05 0.00 1.64534 -5.31677 -1.64534 0.571 0.02 9.4962e-05 7.3986e-05 0.000396852 0.000314184 -1 -1 -1 -1 8 19 8 107788 107788 4794.78 299.674 0.06 0.00289715 0.00253727 564 862 -1 15 2 8 8 156 74 1.57153 0.571 -4.92067 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00169004 0.00159575 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 1.04 vpr 62.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64408 5 3 11 14 2 9 10 4 4 16 clb auto 24.1 MiB 0.04 20 30 8 18 4 62.9 MiB 0.05 0.00 1.44871 -2.90839 -1.44871 0.571 0.02 7.5837e-05 6.5211e-05 0.000364341 0.000304084 -1 -1 -1 -1 8 33 10 107788 107788 4794.78 299.674 0.16 0.00341365 0.00298684 564 862 -1 19 2 11 11 275 141 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.03 0.00 -1 -1 0.00 0.00194921 0.0018382 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.93 vpr 62.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64424 5 3 11 14 2 9 10 4 4 16 clb auto 24.2 MiB 0.02 20 110 34 46 30 62.9 MiB 0.08 0.00 0.145339 0 0 0.571 0.04 5.4987e-05 4.5804e-05 0.00111315 0.000934972 -1 -1 -1 -1 8 25 4 107788 107788 4794.78 299.674 0.02 0.00324582 0.00292657 564 862 -1 36 5 15 15 690 511 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.05 0.00 -1 -1 0.00 0.0020967 0.00194205 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.45 vpr 65.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66728 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 21 30 5 21 4 65.2 MiB 0.00 0.00 0.814658 -2.77132 -0.814658 0.571 0.03 3.7635e-05 2.9892e-05 0.000225074 0.00018278 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.02 0.00833787 0.0081741 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00218203 0.00181006 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.44 vpr 65.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66812 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 22 30 6 14 10 65.2 MiB 0.00 0.00 0.571 0 0 0.571 0.01 3.1854e-05 2.4534e-05 0.000226572 0.000187065 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.03 0.00709054 0.0068829 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00198245 0.00170015 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.39 vpr 65.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66832 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 21 30 5 22 3 65.3 MiB 0.00 0.00 0.646297 -2.19033 -0.646297 0.571 0.01 3.5201e-05 2.6601e-05 0.00022707 0.000179701 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00304545 0.00286146 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00175316 0.00162725 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.41 vpr 65.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66952 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 21 30 7 16 7 65.4 MiB 0.00 0.00 1.6463 -5.31965 -1.6463 0.571 0.01 4.0901e-05 3.1228e-05 0.000248936 0.000196898 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00216389 0.0019624 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00684314 0.00669963 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.43 vpr 65.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66876 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 22 30 8 15 7 65.3 MiB 0.00 0.00 1.44967 -2.9103 -1.44967 0.571 0.01 3.9504e-05 2.6238e-05 0.000255838 0.000203867 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00256208 0.00226692 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.01 0.00 -1 -1 0.00 0.00410374 0.00385942 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.30 vpr 65.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66632 5 3 11 14 2 9 10 4 4 16 clb auto 26.7 MiB 0.00 21 30 5 23 2 65.1 MiB 0.00 0.00 0.146298 0 0 0.571 0.01 2.4424e-05 1.8925e-05 0.00016567 0.000135551 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.00 0.00149783 0.00138533 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00190216 0.00178073 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt index 98fbf8c8bd7..3373ba9d87f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 3.08 vpr 63.73 MiB -1 -1 0.13 17836 1 0.04 -1 -1 30188 -1 -1 3 9 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65260 9 8 75 70 1 34 20 5 5 25 clb auto 24.3 MiB 0.77 86 452 135 313 4 63.7 MiB 0.06 0.00 2.64007 -28.8002 -2.64007 2.64007 0.04 0.000176675 0.000162569 0.00460188 0.00429403 -1 -1 -1 -1 26 211 21 151211 75605.7 37105.9 1484.24 0.81 0.0541272 0.0457299 1908 5841 -1 127 12 86 111 2724 1535 2.42625 2.42625 -30.8606 -2.42625 0 0 45067.1 1802.68 0.01 0.05 0.01 -1 -1 0.01 0.00806965 0.00737112 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.46 vpr 63.92 MiB -1 -1 0.11 17900 1 0.03 -1 -1 30160 -1 -1 2 11 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65452 11 10 108 97 1 49 23 4 4 16 clb auto 24.7 MiB 2.73 138 87 33 42 12 63.9 MiB 0.01 0.00 3.45122 -43.3524 -3.45122 3.45122 0.01 0.000201429 0.000183002 0.00257604 0.00248464 -1 -1 -1 -1 34 217 45 50403.8 50403.8 21558.4 1347.40 0.20 0.0492626 0.0420827 1020 3049 -1 176 15 182 199 5640 3466 3.92522 3.92522 -51.7346 -3.92522 0 0 26343.3 1646.46 0.01 0.15 0.00 -1 -1 0.01 0.0136853 0.0123259 15 27 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 8.63 vpr 64.31 MiB -1 -1 0.14 17828 1 0.03 -1 -1 30240 -1 -1 7 13 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65856 13 12 149 129 1 68 32 6 6 36 clb auto 24.9 MiB 5.01 198 932 296 626 10 64.3 MiB 0.07 0.00 3.49758 -52.5769 -3.49758 3.49758 0.05 0.000575762 0.000545987 0.00855835 0.00805083 -1 -1 -1 -1 40 371 22 403230 176413 88484.8 2457.91 1.86 0.1398 0.120669 3734 16003 -1 302 13 290 358 12780 5849 3.44595 3.44595 -57.0613 -3.44595 0 0 110337. 3064.92 0.03 0.04 0.02 -1 -1 0.03 0.0197264 0.0176 25 38 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 6.05 vpr 64.62 MiB -1 -1 0.14 18180 1 0.03 -1 -1 30148 -1 -1 7 15 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66176 15 14 196 165 1 92 36 6 6 36 clb auto 24.8 MiB 2.57 301 980 184 766 30 64.6 MiB 0.04 0.00 3.62628 -64.321 -3.62628 3.62628 0.05 0.000340747 0.000313302 0.00984916 0.00930715 -1 -1 -1 -1 52 612 36 403230 176413 110337. 3064.92 1.44 0.161491 0.139542 4014 20275 -1 519 17 441 623 24147 10156 4.0567 4.0567 -75.6699 -4.0567 0 0 143382. 3982.83 0.04 0.21 0.02 -1 -1 0.04 0.022191 0.0203236 37 51 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 9.18 vpr 64.91 MiB -1 -1 0.13 18156 1 0.03 -1 -1 30520 -1 -1 5 17 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66468 17 16 251 206 1 119 38 5 5 25 clb auto 25.1 MiB 6.50 399 2117 534 1560 23 64.9 MiB 0.09 0.00 4.01364 -77.6621 -4.01364 4.01364 0.03 0.000417359 0.000385331 0.0217452 0.020383 -1 -1 -1 -1 46 659 28 151211 126010 57775.2 2311.01 0.98 0.133566 0.118166 2220 9391 -1 557 21 689 1063 30471 14107 5.4787 5.4787 -101.9 -5.4787 0 0 73020.3 2920.81 0.01 0.10 0.01 -1 -1 0.01 0.0322818 0.0292918 44 66 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 8.82 vpr 65.02 MiB -1 -1 0.16 18400 1 0.04 -1 -1 30676 -1 -1 6 19 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66576 19 18 308 249 1 133 43 5 5 25 clb auto 25.4 MiB 5.91 453 1993 498 1475 20 65.0 MiB 0.14 0.00 4.85986 -99.1517 -4.85986 4.85986 0.04 0.000524482 0.000482714 0.0388578 0.0376049 -1 -1 -1 -1 48 705 25 151211 151211 59785.0 2391.40 0.96 0.168776 0.152151 2244 9614 -1 614 16 592 999 32515 15691 4.9757 4.9757 -106.674 -4.9757 0 0 75076.4 3003.05 0.01 0.17 0.01 -1 -1 0.01 0.0312715 0.028896 53 83 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.57 vpr 66.20 MiB -1 -1 0.12 21572 1 0.03 -1 -1 33720 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67792 9 8 75 70 1 34 20 5 5 25 clb auto 27.2 MiB 0.67 85 398 116 276 6 66.2 MiB 0.01 0.00 2.48207 -27.4234 -2.48207 2.48207 0.03 0.000168115 0.000148552 0.00382732 0.00348451 -1 -1 -1 -1 26 186 18 151211 75605.7 37105.9 1484.24 0.07 0.0274796 0.0239744 1908 5841 -1 144 14 104 128 3783 2136 2.42625 2.42625 -32.7566 -2.42625 0 0 45067.1 1802.68 0.00 0.01 0.01 -1 -1 0.00 0.00858616 0.00782966 13 18 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 2.85 vpr 66.12 MiB -1 -1 0.12 21064 1 0.03 -1 -1 33420 -1 -1 2 11 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67704 11 10 108 97 1 49 23 4 4 16 clb auto 26.9 MiB 2.02 135 87 35 39 13 66.1 MiB 0.00 0.00 3.45122 -42.4992 -3.45122 3.45122 0.01 0.000185565 0.000169189 0.00161119 0.00153779 -1 -1 -1 -1 34 225 26 50403.8 50403.8 21558.4 1347.40 0.10 0.0502132 0.0405962 1020 3049 -1 158 14 151 165 4063 2532 3.88646 3.88646 -47.5118 -3.88646 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.00719488 0.00664889 15 27 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 6.48 vpr 66.58 MiB -1 -1 0.14 21316 1 0.03 -1 -1 33560 -1 -1 7 13 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68180 13 12 149 129 1 68 32 6 6 36 clb auto 27.2 MiB 5.18 196 882 281 588 13 66.6 MiB 0.01 0.00 3.49758 -52.6333 -3.49758 3.49758 0.04 0.000188427 0.000167514 0.00680212 0.00627325 -1 -1 -1 -1 40 395 29 403230 176413 88484.8 2457.91 0.24 0.0901214 0.0785509 3734 16003 -1 328 14 283 356 13658 6213 3.44595 3.44595 -58.2463 -3.44595 0 0 110337. 3064.92 0.00 0.04 0.03 -1 -1 0.00 0.0323499 0.0245182 25 38 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 4.00 vpr 66.86 MiB -1 -1 0.14 21572 1 0.03 -1 -1 33512 -1 -1 7 15 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68460 15 14 196 165 1 92 36 6 6 36 clb auto 27.2 MiB 2.65 304 744 159 567 18 66.9 MiB 0.02 0.00 3.62628 -64.4645 -3.62628 3.62628 0.05 0.000406252 0.000363743 0.00800716 0.00737412 -1 -1 -1 -1 52 651 42 403230 176413 110337. 3064.92 0.29 0.109536 0.0955888 4014 20275 -1 496 16 373 551 19804 8423 3.5903 3.5903 -70.6456 -3.5903 0 0 143382. 3982.83 0.00 0.03 0.03 -1 -1 0.00 0.0200523 0.0184119 37 51 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.34 vpr 67.21 MiB -1 -1 0.16 21320 1 0.03 -1 -1 33716 -1 -1 5 17 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68824 17 16 251 206 1 119 38 5 5 25 clb auto 27.6 MiB 6.96 396 2495 611 1868 16 67.2 MiB 0.04 0.00 3.8369 -73.5721 -3.8369 3.8369 0.03 0.000487285 0.000432143 0.0227482 0.0204679 -1 -1 -1 -1 46 672 23 151211 126010 57775.2 2311.01 0.27 0.134818 0.118379 2220 9391 -1 565 21 712 1067 32893 15487 5.93712 5.93712 -106.904 -5.93712 0 0 73020.3 2920.81 0.00 0.04 0.01 -1 -1 0.00 0.0286301 0.0260985 44 66 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.49 vpr 67.34 MiB -1 -1 0.15 21572 1 0.03 -1 -1 33768 -1 -1 6 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68960 19 18 308 249 1 133 43 5 5 25 clb auto 27.8 MiB 6.09 448 2143 525 1607 11 67.3 MiB 0.04 0.00 4.70186 -94.0493 -4.70186 4.70186 0.03 0.000586405 0.000522924 0.0211391 0.0191781 -1 -1 -1 -1 46 706 50 151211 151211 57775.2 2311.01 0.36 0.18155 0.16007 2220 9391 -1 599 18 697 1112 32896 15750 4.84188 4.84188 -104.71 -4.84188 0 0 73020.3 2920.81 0.00 0.04 0.01 -1 -1 0.00 0.0301574 0.0276463 53 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt index b2a92d253ed..900ba99d8f4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common 7.44 vpr 56.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57804 6 7 19 26 0 19 26 3 3 9 -1 auto 17.7 MiB 0.04 51 216 43 63 110 56.4 MiB 0.19 0.01 3.682 -25.774 -3.682 nan 5.70 9.9275e-05 8.7239e-05 0.00080976 0.000700914 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.17 0.00664803 0.00634555 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.01 0.05 0.04 -1 -1 0.01 0.00241331 0.00228144 + sub_tiles.xml sub_tiles.blif common 17.03 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60480 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.49 3.9173e-05 3.1698e-05 0.000338068 0.000271828 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00193749 0.00171766 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00201882 0.00189534 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt index 7566db0b692..160cbfe1388 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - heterogeneous_tile.xml sub_tile_directs.blif common 0.62 vpr 56.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57764 2 2 4 5 0 4 5 3 3 9 -1 auto 17.7 MiB 0.04 8 12 0 0 12 56.4 MiB 0.03 0.00 1.899 -3.798 -1.899 nan 0.03 2.0146e-05 1.5134e-05 0.000136441 0.000104751 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.06 0.00289731 0.0027087 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00137522 0.00133686 + heterogeneous_tile.xml sub_tile_directs.blif common 0.33 vpr 59.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60416 2 2 4 5 0 4 5 3 3 9 -1 auto 20.7 MiB 0.00 8 12 0 0 12 59.0 MiB 0.00 0.00 1.899 -3.798 -1.899 nan 0.03 1.7245e-05 1.217e-05 9.686e-05 7.1239e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.01 0.0017081 0.00158045 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00139703 0.00135574 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt index df06df92e99..6303f27bd50 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 4.39 vpr 64.02 MiB -1 -1 0.45 18932 3 0.10 -1 -1 33272 -1 -1 19 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65552 99 73 292 365 1 173 192 8 8 64 io memory auto 24.8 MiB 0.19 683 14570 2226 10547 1797 64.0 MiB 0.07 0.00 2.10913 -115.89 -2.10913 2.10913 0.14 0.000747466 0.000694634 0.0201045 0.0187259 -1 -1 -1 -1 32 1229 14 2.23746e+06 1.57199e+06 106908. 1670.44 2.05 0.296954 0.265952 4378 18911 -1 1110 9 491 754 35474 12126 1.99714 1.99714 -132.662 -1.99714 -0.34191 -0.0876569 130676. 2041.82 0.05 0.13 0.03 -1 -1 0.05 0.027581 0.0256138 + k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.72 vpr 66.86 MiB -1 -1 0.36 22284 3 0.10 -1 -1 36712 -1 -1 19 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68460 99 73 292 365 1 173 192 8 8 64 io memory auto 27.1 MiB 0.06 704 10699 1176 8237 1286 66.9 MiB 0.06 0.00 2.09255 -114.438 -2.09255 2.09255 0.09 0.000494971 0.000445037 0.0176268 0.0158319 -1 -1 -1 -1 32 1440 34 2.23746e+06 1.57199e+06 106908. 1670.44 0.32 0.14258 0.127902 4378 18911 -1 1142 12 555 876 46439 15775 1.9226 1.9226 -129.963 -1.9226 -0.449924 -0.248875 130676. 2041.82 0.01 0.04 0.02 -1 -1 0.01 0.0280032 0.0259551 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt index e92c164cb11..9a4d84cf163 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml styr.blif common_--target_ext_pin_util_1 3.33 vpr 66.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67708 10 10 168 178 1 73 31 6 6 36 clb auto 26.5 MiB 0.25 396 511 91 400 20 66.1 MiB 0.09 0.00 2.39024 -27.2311 -2.39024 2.39024 0.06 0.000971201 0.000900811 0.0143984 0.0134813 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 1.65 0.234894 0.204034 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.17 0.01 -1 -1 0.01 0.0431247 0.0391487 - EArch.xml styr.blif common_--target_ext_pin_util_0.7 3.34 vpr 66.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67808 10 10 168 178 1 73 31 6 6 36 clb auto 26.6 MiB 0.22 396 511 91 400 20 66.2 MiB 0.08 0.00 2.39024 -27.2311 -2.39024 2.39024 0.06 0.00063912 0.000574742 0.0133256 0.0125205 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 1.99 0.279091 0.24285 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.08 0.01 -1 -1 0.01 0.0417208 0.0376776 - EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 6.02 vpr 66.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68128 10 10 168 178 1 162 111 14 14 196 clb auto 26.8 MiB 0.95 1456 5963 865 4880 218 66.5 MiB 0.13 0.00 3.05524 -37.9348 -3.05524 3.05524 0.59 0.000646566 0.000596261 0.02071 0.019112 -1 -1 -1 -1 26 2865 15 9.20055e+06 4.90435e+06 387483. 1976.95 2.42 0.211695 0.185383 18784 74779 -1 2696 13 472 1947 107713 24081 3.50167 3.50167 -42.0838 -3.50167 0 0 467681. 2386.13 0.16 0.11 0.07 -1 -1 0.16 0.0279753 0.0255829 - EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 2.84 vpr 66.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67764 10 10 168 178 1 75 33 7 7 49 clb auto 26.6 MiB 0.23 404 813 125 661 27 66.2 MiB 0.10 0.00 2.45517 -27.3027 -2.45517 2.45517 0.09 0.000647339 0.000599538 0.0197487 0.0185137 -1 -1 -1 -1 26 1116 28 1.07788e+06 700622 75813.7 1547.22 1.14 0.148701 0.13165 3816 13734 -1 925 18 487 1699 71725 25249 2.97305 2.97305 -35.2593 -2.97305 0 0 91376.6 1864.83 0.02 0.24 0.01 -1 -1 0.02 0.0460889 0.0423163 - EArch.xml styr.blif common_--target_ext_pin_util_0.0 5.34 vpr 66.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68236 10 10 168 178 1 163 124 14 14 196 clb auto 26.9 MiB 1.00 1516 7540 1142 6103 295 66.6 MiB 0.21 0.00 3.06133 -37.7953 -3.06133 3.06133 0.60 0.000630456 0.00057306 0.0281512 0.0261658 -1 -1 -1 -1 20 2911 18 9.20055e+06 5.60498e+06 354876. 1810.58 1.60 0.106074 0.094968 18004 60473 -1 2874 12 603 2265 131794 29163 3.74152 3.74152 -44.1586 -3.74152 0 0 387483. 1976.95 0.14 0.17 0.06 -1 -1 0.14 0.0262615 0.0240198 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 3.16 vpr 66.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67760 10 10 168 178 1 73 31 6 6 36 clb auto 26.5 MiB 0.20 396 511 91 400 20 66.2 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.05 0.000653728 0.000608322 0.012902 0.0121572 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 1.78 0.26636 0.230807 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.17 0.01 -1 -1 0.01 0.0463537 0.0422043 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 3.43 vpr 66.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67944 10 10 168 178 1 73 31 6 6 36 clb auto 26.8 MiB 0.22 396 511 91 400 20 66.4 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.04 0.000508161 0.000456687 0.0109247 0.0102847 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 1.85 0.27407 0.239119 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.27 0.01 -1 -1 0.01 0.0493788 0.0449139 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 6.33 vpr 66.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68212 10 10 168 178 1 162 111 14 14 196 clb auto 26.8 MiB 0.96 1456 5963 865 4880 218 66.6 MiB 0.14 0.00 3.05524 -37.9348 -3.05524 3.05524 0.62 0.000637905 0.00057522 0.0218552 0.0201449 -1 -1 -1 -1 26 2865 15 9.20055e+06 4.90435e+06 387483. 1976.95 2.71 0.215189 0.189178 18784 74779 -1 2696 13 472 1947 107713 24081 3.50167 3.50167 -42.0838 -3.50167 0 0 467681. 2386.13 0.18 0.11 0.06 -1 -1 0.18 0.0286783 0.0262735 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 3.51 vpr 66.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67772 10 10 168 178 1 73 31 6 6 36 clb auto 26.5 MiB 0.24 396 511 91 400 20 66.2 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.05 0.000503086 0.00045843 0.00994809 0.00934025 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 1.86 0.256569 0.222631 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.28 0.01 -1 -1 0.01 0.0490284 0.0446 - EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.19 vpr 27.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28592 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.6 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.19 vpr 27.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28608 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.5 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.13 vpr 27.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28604 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.6 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.26 vpr 28.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28700 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.6 MiB 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_1 1.36 vpr 68.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70192 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.18 399 703 140 536 27 68.5 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000585274 0.000508741 0.0133922 0.0121686 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.49 0.183472 0.161021 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0299915 0.0274705 + EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.08 vpr 68.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70320 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.19 399 703 140 536 27 68.7 MiB 0.01 0.00 2.34639 -26.9899 -2.34639 2.34639 0.02 0.000329127 0.000280288 0.00811479 0.00735661 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.35 0.13039 0.113608 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0216396 0.0198831 + EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 3.83 vpr 69.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70724 10 10 168 178 1 162 111 14 14 196 clb auto 29.5 MiB 0.87 1467 5165 686 4267 212 69.1 MiB 0.06 0.00 2.95542 -36.8348 -2.95542 2.95542 0.33 0.000607935 0.000523594 0.0180811 0.0161249 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.49 0.224715 0.196946 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.03 0.07 0.10 -1 -1 0.03 0.0292402 0.0269351 + EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.85 vpr 68.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69972 10 10 168 178 1 75 33 7 7 49 clb auto 28.8 MiB 0.15 414 605 98 486 21 68.3 MiB 0.01 0.00 2.40687 -27.3475 -2.40687 2.40687 0.04 0.000340986 0.000290037 0.00724905 0.00664099 -1 -1 -1 -1 26 1062 27 1.07788e+06 700622 75813.7 1547.22 0.16 0.0618811 0.0547109 3816 13734 -1 940 18 540 1691 67850 23781 2.86939 2.86939 -35.5441 -2.86939 0 0 91376.6 1864.83 0.00 0.03 0.01 -1 -1 0.00 0.0207833 0.0191052 + EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.40 vpr 69.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70700 10 10 168 178 1 163 124 14 14 196 clb auto 29.4 MiB 0.95 1526 7540 1144 6026 370 69.0 MiB 0.04 0.00 3.12689 -38.2571 -3.12689 3.12689 0.22 0.000345985 0.000292911 0.012717 0.0113191 -1 -1 -1 -1 20 3129 15 9.20055e+06 5.60498e+06 295730. 1508.82 0.21 0.0326189 0.0295477 18004 60473 -1 3052 13 680 3211 188673 40435 3.88935 3.88935 -46.4141 -3.88935 0 0 387483. 1976.95 0.03 0.08 0.08 -1 -1 0.03 0.0265139 0.024324 + EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.40 vpr 68.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70232 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.6 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000587109 0.000509454 0.0135198 0.0122638 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.49 0.183086 0.160678 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0347629 0.0319856 + EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.32 vpr 68.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70240 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.16 399 703 140 536 27 68.6 MiB 0.03 0.00 2.34639 -26.9899 -2.34639 2.34639 0.03 0.000756907 0.000658585 0.016978 0.0153763 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.44 0.169468 0.148387 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.03477 0.0320116 + EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 3.38 vpr 68.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70504 10 10 168 178 1 162 111 14 14 196 clb auto 29.2 MiB 0.88 1467 5165 686 4267 212 68.9 MiB 0.04 0.00 2.95542 -36.8348 -2.95542 2.95542 0.28 0.000322881 0.000275771 0.0115436 0.0102519 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.09 0.158857 0.137775 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.02 0.05 0.05 -1 -1 0.02 0.0172724 0.0158752 + EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.48 vpr 68.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70176 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.5 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000502609 0.00043998 0.0125423 0.0114378 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.54 0.190745 0.166737 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.07 0.02 -1 -1 0.00 0.0474457 0.0433946 + EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.10 vpr 30.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30760 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.10 vpr 29.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30632 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.09 vpr 30.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31144 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.09 vpr 30.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31272 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt index 070dd53f47f..b99a452bc00 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 9.14 vpr 72.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 74668 229 197 2152 2349 1 1013 576 16 16 256 io auto 33.4 MiB 3.18 8848 180201 52690 111830 15681 72.9 MiB 1.51 0.02 2.99388 -664.24 -2.99388 2.99388 0.00 0.00626795 0.00568046 0.542629 0.481854 -1 -1 -1 -1 -1 11423 9 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.27 0.752915 0.676781 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 8.05 vpr 75.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76868 229 197 2152 2349 1 1013 576 16 16 256 io auto 35.4 MiB 3.87 8858 177806 51921 111135 14750 75.1 MiB 1.04 0.02 2.93018 -671.396 -2.93018 2.93018 0.00 0.00614227 0.00545306 0.382618 0.335662 -1 -1 -1 -1 -1 11350 10 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.30 0.645332 0.579161 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt index 8576e7f7dc7..c7b87ad96d9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 -k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 -k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_tileable_90nm.xml diffeq.blif common 19.81 vpr 62.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-13020-g9db19397a Release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T14:55:09 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 63832 64 39 1935 1974 1 1077 541 23 23 529 clb auto 23.1 MiB 0.33 23383 10407 130518 33236 93921 3361 62.3 MiB 1.45 0.02 13.1424 7.01436 -1186.76 -7.01436 7.01436 0.50 0.00278506 0.0021586 0.190009 0.145283 -1 -1 -1 -1 30 18484 49 983127 976439 713134. 1348.08 14.21 1.06254 0.869067 34090 111051 -1 19671 23 8649 30686 3584279 1256529 7.46036 7.46036 -1487.87 -7.46036 0 0 855979. 1618.11 0.12 1.13 -1 -1 -1 0.12 0.186892 0.161913 +k4_N4_tileable_90nm.xml ex5p.blif common 24.85 vpr 58.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-13020-g9db19397a Release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T14:55:09 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59604 8 63 1072 1135 0 894 437 22 22 484 clb auto 19.0 MiB 0.26 20320 12148 81630 19773 60101 1756 58.1 MiB 0.95 0.02 7.91494 5.42874 -233.124 -5.42874 nan 0.46 0.00184499 0.00135252 0.103436 0.0807114 -1 -1 -1 -1 58 21250 25 891726 815929 1.11794e+06 2309.80 19.84 0.848059 0.694504 50136 186432 -1 21807 22 9790 33292 5274291 1466232 5.49118 nan -247.625 -5.49118 0 0 1.39817e+06 2888.78 0.20 1.26 -1 -1 -1 0.20 0.112893 0.0976021 +k4_N4_tileable_90nm.xml s298.blif common 37.04 vpr 68.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-13020-g9db19397a Release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T14:55:09 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 70248 4 6 1942 1948 1 1169 590 27 27 729 clb auto 25.2 MiB 0.34 27324 13487 148970 40500 107491 979 68.6 MiB 1.82 0.03 15.4416 9.90815 -77.1816 -9.90815 9.90815 0.71 0.0031275 0.00242 0.2127 0.16542 -1 -1 -1 -1 34 24602 39 1.39333e+06 1.29301e+06 1.12707e+06 1546.05 28.80 1.56376 1.28245 50282 172723 -1 28340 30 12129 58881 11129903 3411240 10.0924 10.0924 -86.1832 -10.0924 0 0 1.32680e+06 1820.03 0.17 2.63 -1 -1 -1 0.17 0.220331 0.186786 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt index 8576e7f7dc7..1ec53c07bd8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 -k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 -k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_tileable_perimeter_cb_90nm.xml diffeq.blif common 16.22 vpr 62.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 64028 64 39 1935 1974 1 1077 541 23 23 529 clb auto 23.3 MiB 0.32 23383 10252 119503 28618 87175 3710 62.5 MiB 1.34 0.02 13.2048 7.13924 -1172.08 -7.13924 7.13924 0.57 0.00281932 0.00216196 0.173313 0.133573 -1 -1 -1 -1 34 18135 26 983127 976439 897386. 1696.38 10.12 0.961872 0.787041 40002 146231 -1 21299 25 9235 32958 4733492 1780844 7.08492 7.08492 -1502.77 -7.08492 0 0 1.04845e+06 1981.94 0.15 1.39 -1 -1 -1 0.15 0.189526 0.162735 +k4_N4_tileable_perimeter_cb_90nm.xml ex5p.blif common 42.06 vpr 58.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59644 8 63 1072 1135 0 894 437 22 22 484 clb auto 19.0 MiB 0.26 20320 11946 86601 21898 63026 1677 58.2 MiB 1.03 0.02 7.95072 5.28278 -233.118 -5.28278 nan 0.52 0.00193544 0.00142786 0.111869 0.0866652 -1 -1 -1 -1 50 20745 26 891726 815929 1.11061e+06 2294.66 36.41 0.787577 0.645158 48048 178976 -1 23642 21 10261 34242 6998785 2421199 5.87736 nan -261.019 -5.87736 0 0 1.28980e+06 2664.87 0.17 1.62 -1 -1 -1 0.17 0.107382 0.0929134 +k4_N4_tileable_perimeter_cb_90nm.xml s298.blif common 53.44 vpr 72.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 74664 4 6 1942 1948 1 1169 590 27 27 729 clb auto 25.0 MiB 0.35 27324 13425 148970 41008 107008 954 72.9 MiB 1.84 0.03 15.2089 9.65839 -76.0928 -9.65839 9.65839 0.81 0.00340369 0.00261843 0.224099 0.175111 -1 -1 -1 -1 34 24976 25 1.39333e+06 1.29301e+06 1.24041e+06 1701.52 45.33 1.66978 1.36439 54994 199951 -1 28059 24 11455 54709 8763089 2638513 10.1962 10.1962 -84.1267 -10.1962 0 0 1.45188e+06 1991.60 0.18 2.10 -1 -1 -1 0.18 0.186815 0.160845 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt index 8576e7f7dc7..bb617d6fd9e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 -k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 -k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_tileable_90nm.xml diffeq.blif common 7.52 vpr 62.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 63840 64 39 1935 1974 1 1077 541 23 23 529 clb auto 23.1 MiB 0.32 23383 10407 130518 33236 93921 3361 62.3 MiB 1.44 0.02 13.1424 7.01436 -1186.76 -7.01436 7.01436 0.00 0.00273601 0.00211561 0.187595 0.143154 -1 -1 -1 -1 19245 17.8857 11150 10.3625 7421 25910 2845736 884425 983127 976439 1.22961e+06 2324.41 18 45530 160719 -1 7.37964 7.37964 -1373.48 -7.37964 0 0 -1 -1 -1 62.3 MiB 0.87 0.347277 0.281856 62.3 MiB -1 0.18 +k4_N4_tileable_90nm.xml ex5p.blif common 9.78 vpr 58.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59836 8 63 1072 1135 0 894 437 22 22 484 clb auto 18.8 MiB 0.26 20320 12148 81630 19773 60101 1756 58.4 MiB 0.96 0.02 7.91494 5.42874 -233.124 -5.42874 nan 0.00 0.00181633 0.00135353 0.102123 0.0792786 -1 -1 -1 -1 24636 27.5570 13596 15.2081 10695 36592 10880255 4591282 891726 815929 1.11756e+06 2309.00 31 41484 146288 -1 6.67754 nan -291.675 -6.67754 0 0 -1 -1 -1 58.4 MiB 2.78 0.258159 0.213053 58.4 MiB -1 0.17 +k4_N4_tileable_90nm.xml s298.blif common 11.27 vpr 65.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66640 4 6 1942 1948 1 1169 590 27 27 729 clb auto 25.0 MiB 0.35 27324 13487 148970 40500 107491 979 65.1 MiB 1.82 0.03 15.4416 9.90815 -77.1816 -9.90815 9.90815 0.00 0.00345442 0.0027131 0.213085 0.165433 -1 -1 -1 -1 28424 24.3356 15352 13.1438 11036 53711 8284367 2041058 1.39333e+06 1.29301e+06 1.73135e+06 2374.97 22 63594 225223 -1 9.88398 9.88398 -83.5517 -9.88398 0 0 -1 -1 -1 65.1 MiB 2.28 0.435186 0.358877 65.1 MiB -1 0.26 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt index 8576e7f7dc7..8a8cf8f4f29 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 -k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 -k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_tileable_90nm.xml diffeq.blif common 7.48 vpr 65.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 67540 64 39 1935 1974 1 1077 541 23 23 529 clb auto 22.9 MiB 0.32 23383 10873 130518 33024 93628 3866 66.0 MiB 1.45 0.02 13.0763 6.99652 -1162.99 -6.99652 6.99652 0.00 0.00285671 0.00221991 0.189815 0.145412 -1 -1 -1 -1 18849 17.5177 10317 9.58829 6567 21821 1854731 449487 983127 976439 2.00514e+06 3790.43 20 70170 268455 -1 7.25476 7.25476 -1304.75 -7.25476 0 0 -1 -1 -1 66.0 MiB 0.75 0.363502 0.296117 66.0 MiB -1 0.31 +k4_N4_tileable_90nm.xml ex5p.blif common 6.79 vpr 58.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 60028 8 63 1072 1135 0 894 437 22 22 484 clb auto 18.8 MiB 0.26 20320 12136 81630 20496 59555 1579 58.6 MiB 0.96 0.02 7.72232 5.21275 -226.687 -5.21275 nan 0.00 0.00182646 0.00137253 0.108622 0.0845891 -1 -1 -1 -1 21866 24.4586 10468 11.7092 8501 29146 3873168 891811 891726 815929 1.82197e+06 3764.41 19 63912 244296 -1 5.56516 nan -246.308 -5.56516 0 0 -1 -1 -1 58.6 MiB 1.05 0.222148 0.183769 58.6 MiB -1 0.28 +k4_N4_tileable_90nm.xml s298.blif common 9.95 vpr 85.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 87228 4 6 1942 1948 1 1169 590 27 27 729 clb auto 25.0 MiB 0.35 27324 13569 146497 39933 105616 948 85.2 MiB 1.82 0.03 15.2069 10.0243 -77.5741 -10.0243 10.0243 0.00 0.00351567 0.00274926 0.230835 0.183363 -1 -1 -1 -1 24793 21.2269 12639 10.8211 7296 37518 4021317 704688 1.39333e+06 1.29301e+06 2.82552e+06 3875.88 19 98122 376471 -1 10.1962 10.1962 -80.531 -10.1962 0 0 -1 -1 -1 85.2 MiB 1.40 0.430119 0.358207 85.2 MiB -1 0.45 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt index e837cb2407d..b003134057c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 6.33 vpr 65.84 MiB -1 -1 0.42 18744 3 0.10 -1 -1 33376 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67424 99 130 344 474 1 227 298 12 12 144 clb auto 26.1 MiB 0.24 717 72933 22876 34411 15646 65.8 MiB 0.50 0.01 1.84343 -118.171 -1.84343 1.84343 0.34 0.000999398 0.000934504 0.0982577 0.092362 -1 -1 -1 -1 38 1540 14 5.66058e+06 4.21279e+06 319130. 2216.18 2.76 0.374935 0.344885 12522 62564 -1 1261 9 399 607 24533 7188 1.90841 1.90841 -134.095 -1.90841 -1.28606 -0.31945 406292. 2821.48 0.14 0.13 0.07 -1 -1 0.14 0.0314453 0.0295015 - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 6.28 vpr 65.81 MiB -1 -1 0.35 18932 3 0.11 -1 -1 33264 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67392 99 130 344 474 1 227 298 12 12 144 clb auto 26.0 MiB 0.23 717 72933 22876 34411 15646 65.8 MiB 0.47 0.00 1.84343 -118.171 -1.84343 1.84343 0.37 0.000579812 0.000531042 0.0759736 0.0701905 -1 -1 -1 -1 38 1540 14 5.66058e+06 4.21279e+06 319130. 2216.18 2.68 0.230578 0.208922 12522 62564 -1 1261 9 399 607 24533 7188 1.90841 1.90841 -134.095 -1.90841 -1.28606 -0.31945 406292. 2821.48 0.13 0.14 0.07 -1 -1 0.13 0.0211432 0.0195748 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.63 vpr 68.02 MiB -1 -1 0.39 22168 3 0.11 -1 -1 36800 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69656 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.23 0.00 1.86472 -118.834 -1.86472 1.86472 0.15 0.000594963 0.000540506 0.0732034 0.0668337 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.54 0.213559 0.195205 12522 62564 -1 1116 11 409 682 22304 6997 1.90702 1.90702 -133.281 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.08 -1 -1 0.02 0.0300207 0.027912 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 2.86 vpr 68.12 MiB -1 -1 0.35 22168 3 0.11 -1 -1 36740 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69760 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.1 MiB 0.27 0.00 1.86472 -118.834 -1.86472 1.86472 0.21 0.000644886 0.000574461 0.100184 0.0946805 -1 -1 -1 -1 38 1379 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.64 0.202724 0.187418 12522 62564 -1 1115 10 390 630 21561 6939 1.90702 1.90702 -131.117 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.10 -1 -1 0.02 0.021384 0.0193317 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt index 0caf65de4b1..7b4fc76c6e6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 6.52 vpr 66.06 MiB -1 -1 0.44 19044 3 0.11 -1 -1 33268 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67644 99 130 344 474 1 225 298 12 12 144 clb auto 26.2 MiB 0.22 734 75918 23628 39360 12930 66.1 MiB 0.49 0.01 1.84343 -75.0087 -1.84343 1.84343 0.33 0.000857681 0.000789515 0.0812026 0.0751694 -1 -1 -1 -1 36 1518 6 5.66058e+06 4.21279e+06 305235. 2119.69 3.85 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.55 vpr 67.97 MiB -1 -1 0.42 22420 3 0.14 -1 -1 36800 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69600 99 130 344 474 1 225 298 12 12 144 clb auto 28.5 MiB 0.19 695 57013 16754 28454 11805 68.0 MiB 0.25 0.00 1.84453 -73.0907 -1.84453 1.84453 0.29 0.000572985 0.000494317 0.0593261 0.049655 -1 -1 -1 -1 32 1551 10 5.66058e+06 4.21279e+06 281316. 1953.58 1.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt index 120a1a483e0..50b6703de2b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 6.29 vpr 65.84 MiB -1 -1 0.44 18932 3 0.10 -1 -1 33272 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67416 99 130 344 474 1 218 298 12 12 144 clb auto 26.1 MiB 0.29 706 75918 21357 39248 15313 65.8 MiB 0.45 0.00 2.17824 0 0 2.17824 0.39 0.000858537 0.000799712 0.0715997 0.0663405 -1 -1 -1 -1 38 1473 11 5.66058e+06 4.21279e+06 319130. 2216.18 2.60 0.302049 0.26108 12522 62564 -1 1300 5 274 392 20827 6674 2.27647 2.27647 0 0 0 0 406292. 2821.48 0.14 0.10 0.06 -1 -1 0.14 0.0177896 0.0166081 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 3.13 vpr 67.88 MiB -1 -1 0.41 22284 3 0.13 -1 -1 36924 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69508 99 130 344 474 1 218 298 12 12 144 clb auto 28.4 MiB 0.23 632 70943 19608 36161 15174 67.9 MiB 0.23 0.00 2.24009 0 0 2.24009 0.25 0.000717536 0.00062496 0.0508972 0.0435443 -1 -1 -1 -1 32 1480 8 5.66058e+06 4.21279e+06 281316. 1953.58 0.55 0.227253 0.196073 11950 52952 -1 1327 7 304 419 24960 8371 2.42926 2.42926 0 0 0 0 345702. 2400.71 0.03 0.05 0.08 -1 -1 0.03 0.020098 0.0186968 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt index 2d3ef814bc3..a5bee947840 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.99 vpr 64.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66448 5 3 11 14 2 9 10 4 4 16 clb auto 26.2 MiB 0.03 20 30 10 17 3 64.9 MiB 0.05 0.00 0.619658 -3.41326 -0.619658 0.545 0.02 8.2559e-05 6.5087e-05 0.000398248 0.000321879 -1 -1 -1 -1 20 15 1 107788 107788 10441.3 652.579 0.06 0.00241051 0.0022076 750 1675 -1 15 1 7 7 94 62 0.562699 0.545 -3.33969 -0.562699 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00164607 0.00157893 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 1.08 vpr 64.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66508 5 3 11 14 2 9 10 4 4 16 clb auto 26.2 MiB 0.04 20 30 10 17 3 64.9 MiB 0.05 0.00 0.619658 -3.41326 -0.619658 0.545 0.03 4.7357e-05 3.5078e-05 0.000316498 0.00025661 -1 -1 -1 -1 20 15 1 107788 107788 10441.3 652.579 0.07 0.00236598 0.00217158 750 1675 -1 15 1 7 7 94 62 0.562699 0.545 -3.33969 -0.562699 0 0 13752.8 859.551 0.01 0.02 0.00 -1 -1 0.01 0.00296841 0.00285153 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.91 vpr 64.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66344 5 3 11 14 2 9 10 4 4 16 clb auto 26.0 MiB 0.03 20 30 10 17 3 64.8 MiB 0.05 0.00 0.619658 -3.41326 -0.619658 0.545 0.01 5.2206e-05 3.8166e-05 0.000401216 0.000334324 -1 -1 -1 -1 20 15 1 107788 107788 10441.3 652.579 0.08 0.003085 0.00285493 750 1675 -1 15 1 7 7 94 62 0.562699 0.545 -3.33969 -0.562699 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00168486 0.00161817 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.50 vpr 67.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68660 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.6443e-05 3.2529e-05 0.000274786 0.000214986 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00211509 0.0019009 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.0017763 0.00169895 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.49 vpr 67.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68680 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.8016e-05 3.4218e-05 0.000283686 0.000224427 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0022472 0.00206472 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00179634 0.00171755 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.51 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68932 5 3 11 14 2 9 10 4 4 16 clb auto 28.9 MiB 0.01 21 30 9 19 2 67.3 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 6.2523e-05 4.6425e-05 0.000366128 0.000294026 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00236124 0.00216436 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00189537 0.00181322 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt index f51e39ff90c..db634e1dc04 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 4.53 vpr 66.47 MiB -1 -1 0.88 23160 4 0.16 -1 -1 33060 -1 -1 15 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68068 11 2 303 283 2 78 28 7 7 49 clb auto 26.9 MiB 0.44 264 1036 209 767 60 66.5 MiB 0.10 0.00 2.03811 -163.536 -2.03811 1.90043 0.00 0.000562272 0.000493381 0.0211263 0.0192484 -1 -1 -1 -1 -1 252 12 1.07788e+06 808410 219490. 4479.39 0.11 0.0624165 0.0568117 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.81 vpr 69.01 MiB -1 -1 0.66 26668 4 0.21 -1 -1 35972 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70664 11 2 303 283 2 78 28 7 7 49 clb auto 29.4 MiB 0.25 285 784 175 539 70 69.0 MiB 0.04 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000759025 0.000652417 0.0254764 0.023241 -1 -1 -1 -1 -1 313 6 1.07788e+06 808410 219490. 4479.39 0.03 0.050656 0.046841 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt index 9362353dbf8..e65df342f6a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 2.80 vpr 63.72 MiB -1 -1 0.89 23420 5 0.16 -1 -1 33496 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65252 10 2 181 183 1 35 24 6 6 36 clb auto 24.3 MiB 0.18 146 398 72 298 28 63.7 MiB 0.11 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.000499863 0.00046066 0.00865418 0.0080588 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 0.24 0.0402973 0.0330423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 2.83 vpr 63.66 MiB -1 -1 0.80 23512 5 0.19 -1 -1 33392 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65184 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.21 146 398 72 298 28 63.7 MiB 0.10 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.000520313 0.000485956 0.0108727 0.0101292 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 0.21 0.0390899 0.0350474 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 2.77 vpr 63.91 MiB -1 -1 0.93 23472 5 0.18 -1 -1 33404 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65448 10 2 181 183 1 35 24 6 6 36 clb auto 24.4 MiB 0.20 146 398 72 298 28 63.9 MiB 0.09 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 2.0662e-05 7.982e-06 0.00379409 0.00346778 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 0.15 0.0197222 0.0139137 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 2.83 vpr 63.69 MiB -1 -1 0.94 23484 5 0.18 -1 -1 33404 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65220 10 2 181 183 1 35 24 6 6 36 clb auto 24.3 MiB 0.24 146 398 72 298 28 63.7 MiB 0.08 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.000152071 3.7143e-05 0.0036681 0.00317106 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 0.15 0.0186284 0.0137477 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 2.80 vpr 63.70 MiB -1 -1 0.90 23532 5 0.15 -1 -1 33352 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65228 10 2 181 183 1 35 24 6 6 36 clb auto 24.3 MiB 0.17 146 398 72 298 28 63.7 MiB 0.10 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 2.2661e-05 4.617e-06 0.00351006 0.00294492 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 0.25 0.0171787 0.012971 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 2.92 vpr 63.56 MiB -1 -1 0.89 23528 5 0.16 -1 -1 33396 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65088 10 2 181 183 1 35 24 6 6 36 clb auto 24.4 MiB 0.25 146 398 72 298 28 63.6 MiB 0.08 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.00212777 0.00209414 0.00814338 0.00754222 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 0.25 0.0344922 0.0314797 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.06 vpr 65.94 MiB -1 -1 0.49 27024 5 0.12 -1 -1 36972 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67520 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 152 432 67 335 30 65.9 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000242517 0.000210755 0.00440565 0.00392683 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.0164282 0.0146736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.57 vpr 66.14 MiB -1 -1 0.70 27020 5 0.18 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67732 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000439525 0.000384869 0.00748551 0.00667971 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.02 0.0256815 0.0230005 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.67 vpr 66.16 MiB -1 -1 0.82 27152 5 0.18 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67748 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.2 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 3.5959e-05 2.737e-05 0.00308117 0.00275747 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.0135928 0.0105523 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.25 vpr 66.16 MiB -1 -1 0.65 27036 5 0.12 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67748 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 152 432 67 335 30 66.2 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000221863 9.7941e-05 0.00222519 0.00187901 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.00928043 0.00694563 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 1.74 vpr 66.05 MiB -1 -1 0.84 26784 5 0.18 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67632 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 432 67 335 30 66.0 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 5.1198e-05 3.2395e-05 0.002938 0.00248994 -1 -1 -1 -1 -1 137 16 646728 646728 138825. 3856.24 0.02 0.0136494 0.00987341 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 2.01 vpr 66.03 MiB -1 -1 0.85 27040 5 0.19 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67616 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 66.0 MiB 0.03 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.00150082 0.00142957 0.0169996 0.0159511 -1 -1 -1 -1 -1 137 16 646728 646728 138825. 3856.24 0.07 0.0553928 0.0438556 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt index cbf1d188143..e84a1129700 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 79.71 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1213252 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1062.8 MiB 17.41 70903 253216 51547 191577 10092 1176.1 MiB 11.03 0.15 4.99319 -5223.26 -3.99319 2.64446 0.01 0.0404503 0.0335948 3.08815 2.57709 83183 6.68835 19827 1.59419 25954 36248 10076288 1815088 0 0 2.05929e+07 18207.7 15 331560 3499109 -1 5.28806 2.7363 -5589.94 -4.28806 0 0 7.56 -1 -1 1176.1 MiB 4.03 4.74901 4.02053 1176.1 MiB -1 19.41 + stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 66.79 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1215864 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1063.3 MiB 15.63 75097 245792 47628 188491 9673 1158.7 MiB 16.87 0.21 4.99421 -5497.03 -3.99421 2.87584 0.01 0.0552629 0.0482483 4.22516 3.43532 87123 7.00515 21186 1.70347 25964 36365 9630576 1720385 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.30154 2.77187 -5700.98 -4.30154 0 0 5.27 -1 -1 1158.7 MiB 5.35 6.14131 5.12726 1158.7 MiB -1 3.33 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt index 159ae69716e..7d3888ea0e0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratix10_arch.timing.xml murax_stratix10_arch_timing.blif common 20.78 vpr 383.20 MiB 35 93 0 0 8 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 392392 18 17 2338 2195 1 2035 136 17 13 221 io_cell auto 341.0 MiB 8.88 11702 14096 2182 10467 1447 383.2 MiB 0.99 0.02 3.767 -3201.39 -2.767 3.767 0.00 0.00771503 0.0062784 0.427042 0.368396 12703 6.25148 3920 1.92913 6529 15398 3929307 843439 0 0 3.37726e+06 15281.7 12 52540 541133 -1 3.447 3.447 -2841.9 -2.447 0 0 1.26 -1 -1 383.2 MiB 1.58 0.852394 0.762998 383.2 MiB -1 2.05 + stratix10_arch.timing.xml murax_stratix10_arch_timing.blif common 19.43 vpr 384.88 MiB 35 93 0 0 8 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 394112 18 17 2338 2195 1 2035 136 17 13 221 io_cell auto 342.6 MiB 9.23 11597 14096 2127 10583 1386 384.9 MiB 0.99 0.03 3.78594 -3334.96 -2.78594 3.78594 0.00 0.0127693 0.0106573 0.428449 0.35312 12754 6.27657 3971 1.95423 6857 16497 4298918 925978 0 0 3.37726e+06 15281.7 12 52540 541133 -1 3.215 3.215 -2910.24 -2.215 0 0 1.33 -1 -1 384.9 MiB 1.91 0.811838 0.706005 384.9 MiB -1 0.27 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt index 05a82915baf..6ff0e8d886f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 17.29 vpr 67.58 MiB -1 -1 0.41 22592 5 0.17 -1 -1 34192 -1 -1 17 66 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69200 66 96 983 697 1 557 191 16 16 256 mult_27 auto 28.6 MiB 2.01 4754 40817 12099 23524 5194 67.6 MiB 0.65 0.01 16.4391 -978.659 -16.4391 16.4391 0.88 0.00273549 0.00258048 0.232507 0.218951 -1 -1 -1 -1 64 11429 28 4.83877e+06 1.03328e+06 1.35562e+06 5295.38 9.13 0.948515 0.877899 40360 280887 -1 10218 18 3342 7052 1691763 500137 17.028 17.028 -1086.21 -17.028 0 0 1.67258e+06 6533.53 0.58 0.52 0.31 -1 -1 0.58 0.136104 0.128889 138 202 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 22.01 vpr 69.98 MiB -1 -1 0.42 25672 5 0.18 -1 -1 37676 -1 -1 17 66 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 71656 66 96 983 697 1 557 191 16 16 256 mult_27 auto 30.8 MiB 2.52 4520 41915 13784 24449 3682 70.0 MiB 0.47 0.01 16.7771 -983.813 -16.7771 16.7771 0.51 0.00380097 0.00356084 0.223806 0.20783 -1 -1 -1 -1 82 9891 30 4.83877e+06 1.03328e+06 1.63760e+06 6396.87 14.79 1.72784 1.60303 43164 348864 -1 8812 16 2703 5592 1100371 345017 16.7238 16.7238 -1023.47 -16.7238 0 0 2.03272e+06 7940.32 0.12 0.37 0.48 -1 -1 0.12 0.123499 0.117943 138 202 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt index c6d02a55f5a..8a9769fe6bb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 1.14 vpr 62.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64472 6 8 39 47 1 20 17 5 5 25 clb auto 24.5 MiB 0.06 69 227 71 153 3 63.0 MiB 0.06 0.00 1.42251 -15.9524 -1.42251 1.42251 0.00 0.00015298 0.000138828 0.00249541 0.00229004 -1 -1 -1 -1 86 4.52632 45 2.36842 140 253 6063 2435 323364 161682 20103.2 804.128 19 1140 2762 -1 1.32969 1.32969 -16.56 -1.32969 0 0 0.00 -1 -1 63.0 MiB 0.12 0.0136734 0.0121602 63.0 MiB -1 0.01 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 1.13 vpr 62.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64404 6 8 39 47 1 20 17 5 5 25 clb auto 24.5 MiB 0.06 69 227 71 153 3 62.9 MiB 0.07 0.00 1.42251 -15.9524 -1.42251 1.42251 0.00 0.000157491 0.000141647 0.00278966 0.00257008 -1 -1 -1 -1 86 4.52632 45 2.36842 140 253 6063 2435 323364 161682 20103.2 804.128 19 1140 2762 -1 1.32969 1.32969 -16.56 -1.32969 0 0 0.00 -1 -1 62.9 MiB 0.10 0.0124481 0.0108976 62.9 MiB -1 0.01 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.72 vpr 62.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64488 6 8 39 47 1 20 17 5 5 25 clb auto 24.6 MiB 0.06 69 227 71 153 3 63.0 MiB 0.07 0.00 1.42347 -15.9604 -1.42347 1.42347 0.00 0.000217166 0.000199351 0.00282597 0.00262228 -1 -1 -1 -1 -1 -1 -1 -1 723 1098 45498 29013 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 63.0 MiB 0.25 -1 -1 63.0 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.77 vpr 62.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64344 6 8 39 47 1 20 17 5 5 25 clb auto 24.4 MiB 0.08 69 227 71 153 3 62.8 MiB 0.05 0.00 1.42347 -15.9604 -1.42347 1.42347 0.00 0.000206522 0.000185386 0.00269457 0.0024909 -1 -1 -1 -1 142 7.47368 68 3.57895 723 1098 45498 29013 323364 161682 9037.03 361.481 -1 996 1634 -1 1.87665 1.87665 -21.7004 -1.87665 0 0 0.00 -1 -1 62.8 MiB 0.28 -1 -1 62.8 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.48 vpr 65.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66896 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.3 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000116029 0.000100823 0.0010942 0.00101432 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.3 MiB 0.01 0.00766251 0.00688033 65.3 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.51 vpr 65.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66796 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000165834 0.000146968 0.00119076 0.00110326 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.2 MiB 0.01 0.00909464 0.00816836 65.2 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.24 vpr 65.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66872 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.3 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000113726 9.7512e-05 0.00114825 0.00106423 -1 -1 -1 -1 -1 -1 -1 -1 654 1027 31303 15229 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 65.3 MiB 0.03 -1 -1 65.3 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.24 vpr 65.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66624 6 8 39 47 1 20 17 5 5 25 clb auto 26.8 MiB 0.02 88 59 31 28 0 65.1 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.00013832 0.000115541 0.000955845 0.00087775 -1 -1 -1 -1 142 7.47368 66 3.47368 654 1027 31303 15229 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9824 -1.84852 0 0 0.00 -1 -1 65.1 MiB 0.03 -1 -1 65.1 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt index 311f7681759..cb597e00427 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 4.21 vpr 57.70 MiB -1 -1 0.80 23328 6 0.19 -1 -1 33384 -1 -1 28 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59088 10 2 186 188 1 48 40 8 8 64 clb auto 17.8 MiB 0.19 230 1196 187 947 62 57.7 MiB 0.08 0.00 2.65254 -112.238 -2.65254 2.65254 0.00 0.000511628 0.000471787 0.00947363 0.00865334 -1 -1 -1 -1 214 4.75556 214 4.75556 166 391 15410 3128 80255.5 62421 276194. 4315.53 14 9480 40228 -1 2.5901 2.5901 -115.226 -2.5901 -0.0734 -0.0734 0.06 -1 -1 57.7 MiB 0.11 0.0294044 0.0261959 57.7 MiB -1 0.04 - k6_frac_N10_40nm.xml stereovision3.v common 3.65 vpr 59.24 MiB -1 -1 0.83 23296 5 0.20 -1 -1 33392 -1 -1 7 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60664 10 2 181 183 1 37 19 5 5 25 clb auto 19.7 MiB 0.25 118 444 83 324 37 59.2 MiB 0.10 0.00 2.09635 -87.6091 -2.09635 2.09635 0.00 0.000727323 0.000670846 0.0133214 0.0124002 -1 -1 -1 -1 93 2.73529 48 1.41176 48 64 1145 344 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97843 1.97843 -87.1605 -1.97843 0 0 0.02 -1 -1 59.2 MiB 0.05 0.0264495 0.0247146 59.2 MiB -1 0.01 + k4_N4_90nm.xml stereovision3.v common 2.77 vpr 60.00 MiB -1 -1 0.91 26856 6 0.21 -1 -1 36836 -1 -1 28 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61436 10 2 186 188 1 48 40 8 8 64 clb auto 20.5 MiB 0.04 230 992 145 785 62 60.0 MiB 0.03 0.00 2.71052 -113.21 -2.71052 2.71052 0.00 0.000447321 0.000382714 0.00843147 0.00745792 -1 -1 -1 -1 199 4.42222 199 4.42222 158 387 13661 2934 80255.5 62421 276194. 4315.53 9 9480 40228 -1 2.65254 2.65254 -117.366 -2.65254 -0.0734 -0.0734 0.09 -1 -1 60.0 MiB 0.03 0.0220189 0.0194464 60.0 MiB -1 0.01 + k6_frac_N10_40nm.xml stereovision3.v common 2.04 vpr 61.65 MiB -1 -1 0.81 26884 5 0.16 -1 -1 36968 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63132 10 2 181 183 1 37 19 5 5 25 clb auto 22.0 MiB 0.07 127 144 32 99 13 61.7 MiB 0.01 0.00 2.03188 -84.9427 -2.03188 2.03188 0.00 0.000403252 0.000354056 0.00494195 0.00440924 -1 -1 -1 -1 107 3.14706 52 1.52941 43 59 1032 320 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97747 1.97747 -86.276 -1.97747 0 0 0.03 -1 -1 61.7 MiB 0.01 0.0168116 0.0156639 61.7 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt index 108c515e439..0fde75bd1ed 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 3.18 vpr 57.75 MiB -1 -1 0.67 23320 6 0.16 -1 -1 33560 -1 -1 28 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59132 10 2 186 188 1 48 40 8 8 64 clb auto 17.9 MiB 0.03 230 1196 187 947 62 57.7 MiB 0.04 0.00 2.65254 -112.238 -2.65254 2.65254 0.00 0.00041108 0.00037781 0.00872984 0.0079342 -1 -1 -1 -1 214 4.75556 214 4.75556 166 391 15410 3128 80255.5 62421 276194. 4315.53 14 9480 40228 -1 2.5901 2.5901 -115.226 -2.5901 -0.0734 -0.0734 0.05 -1 -1 57.7 MiB 0.05 0.025576 0.0229291 57.7 MiB -1 0.05 - k6_frac_N10_40nm.xml stereovision3.v common 3.35 vpr 59.19 MiB -1 -1 0.94 23284 5 0.18 -1 -1 33436 -1 -1 7 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60608 10 2 181 183 1 37 19 5 5 25 clb auto 19.7 MiB 0.17 118 444 83 324 37 59.2 MiB 0.12 0.00 2.09635 -87.6091 -2.09635 2.09635 0.00 0.000568296 0.000529924 0.0148823 0.0140252 -1 -1 -1 -1 93 2.73529 48 1.41176 48 64 1145 344 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97843 1.97843 -87.1605 -1.97843 0 0 0.01 -1 -1 59.2 MiB 0.07 0.0262726 0.0248022 59.2 MiB -1 0.02 + k4_N4_90nm.xml stereovision3.v common 2.09 vpr 60.07 MiB -1 -1 0.81 26980 6 0.15 -1 -1 36756 -1 -1 28 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61512 10 2 186 188 1 48 40 8 8 64 clb auto 20.6 MiB 0.03 230 992 145 785 62 60.1 MiB 0.02 0.00 2.71052 -113.21 -2.71052 2.71052 0.00 0.000430706 0.00037483 0.00785446 0.00688801 -1 -1 -1 -1 199 4.42222 199 4.42222 158 387 13661 2934 80255.5 62421 276194. 4315.53 9 9480 40228 -1 2.65254 2.65254 -117.366 -2.65254 -0.0734 -0.0734 0.08 -1 -1 60.1 MiB 0.02 0.0211284 0.0188358 60.1 MiB -1 0.01 + k6_frac_N10_40nm.xml stereovision3.v common 1.94 vpr 61.65 MiB -1 -1 0.77 26880 5 0.18 -1 -1 36968 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63132 10 2 181 183 1 37 19 5 5 25 clb auto 22.1 MiB 0.06 127 144 32 99 13 61.7 MiB 0.01 0.00 2.03188 -84.9427 -2.03188 2.03188 0.00 0.000420371 0.000366917 0.00494209 0.00453968 -1 -1 -1 -1 107 3.14706 52 1.52941 43 59 1032 320 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97747 1.97747 -86.276 -1.97747 0 0 0.02 -1 -1 61.7 MiB 0.01 0.0164382 0.0153894 61.7 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt index 9a1ccef4106..9a8744d436c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml styr.blif common 35.89 vpr 976.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999840 10 10 168 178 1 68 30 11 8 88 io auto 953.2 MiB 0.64 354 536 67 434 35 976.4 MiB 0.09 0.00 6.57169 -72.0462 -6.57169 6.57169 0.00 0.000503078 0.000459561 0.0104853 0.00985191 -1 -1 -1 -1 586 8.74627 178 2.65672 259 971 58705 26468 0 0 194014. 2204.70 13 11730 32605 -1 6.82307 6.82307 -73.1617 -6.82307 0 0 0.07 -1 -1 976.4 MiB 0.07 0.0420166 0.0389946 976.4 MiB -1 0.08 + stratixiv_arch.timing.xml styr.blif common 32.55 vpr 978.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001924 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.50 371 490 69 397 24 978.4 MiB 0.08 0.00 6.66046 -72.2933 -6.66046 6.66046 0.00 0.000745164 0.00064564 0.0121362 0.0109717 -1 -1 -1 -1 549 8.19403 169 2.52239 264 964 62268 28521 0 0 194014. 2204.70 13 11730 32605 -1 6.70864 6.70864 -73.3171 -6.70864 0 0 0.08 -1 -1 978.4 MiB 0.14 0.0524157 0.0489871 978.4 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt index a3ceed7c14d..6c5af69e6a1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt @@ -24,4 +24,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt # Script parameters -script_params_common =-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --read_vpr_constraints ../../../../floor_plan.xml:../../../../route_constraint.xml --write_vpr_constraints vpr_constraints.xml --clock_modeling ideal +script_params_common =-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --read_vpr_constraints ../../../../vpr_constraints.xml --write_vpr_constraints vpr_constraints.xml --clock_modeling ideal diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml deleted file mode 100644 index 861adf40966..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml deleted file mode 100644 index ca3d794706b..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml +++ /dev/null @@ -1,7 +0,0 @@ - - - - - - - diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/vpr_constraints.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/vpr_constraints.xml new file mode 100644 index 00000000000..d9bc4ac9e3f --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/vpr_constraints.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 0301285b4ba..783b9bb6553 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -1,6 +1,16 @@ regression_tests/vtr_reg_strong/basic_ap regression_tests/vtr_reg_strong/strong_ap/mcnc regression_tests/vtr_reg_strong/strong_ap/vtr_chain +regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer +regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer +regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer +regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer +regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer +regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer +regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks +regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering +regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver +regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver regression_tests/vtr_reg_strong/strong_absorb_buffers regression_tests/vtr_reg_strong/strong_analysis_only regression_tests/vtr_reg_strong/strong_analytic_placer @@ -33,6 +43,7 @@ regression_tests/vtr_reg_strong/strong_equivalent_sites regression_tests/vtr_reg_strong/strong_fc_abs regression_tests/vtr_reg_strong/strong_fix_clusters regression_tests/vtr_reg_strong/strong_fix_pins_random +regression_tests/vtr_reg_strong/strong_flat_placement/read_write regression_tests/vtr_reg_strong/strong_flyover_wires regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch regression_tests/vtr_reg_strong/strong_fracturable_luts @@ -97,3 +108,4 @@ regression_tests/vtr_reg_strong/strong_noc regression_tests/vtr_reg_strong/strong_flat_router regression_tests/vtr_reg_strong/strong_routing_constraints regression_tests/vtr_reg_strong/strong_vib +regression_tests/vtr_reg_strong/strong_3d diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt index a5aa1efe307..7b5437463d7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 6.81 vpr 74.85 MiB 0.09 7796 -1 -1 1 0.08 -1 -1 32232 -1 -1 12 130 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76648 130 40 596 562 1 356 185 14 14 196 dsp_top auto 35.9 MiB 0.18 1873 36479 12233 19905 4341 74.9 MiB 0.21 0.00 5.12303 -652.04 -5.12303 5.12303 0.82 0.00140021 0.00130659 0.105265 0.098455 -1 -1 -1 -1 64 3939 11 4.93594e+06 1.0962e+06 976140. 4980.31 2.47 0.398489 0.366481 31408 195022 -1 3669 7 846 891 204483 79938 4.57723 4.57723 -704.235 -4.57723 0 0 1.23909e+06 6321.90 0.32 0.09 0.28 -1 -1 0.32 0.0391394 0.037187 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 5.51 vpr 77.59 MiB 0.04 8576 -1 -1 1 0.07 -1 -1 35240 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79456 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.5 MiB 0.13 1890 35427 11493 18934 5000 77.6 MiB 0.27 0.00 5.12303 -647.058 -5.12303 5.12303 0.48 0.00206617 0.00189672 0.14394 0.133207 -1 -1 -1 -1 64 3873 16 4.93594e+06 1.0962e+06 976140. 4980.31 2.20 0.636996 0.595296 31408 195022 -1 3500 9 851 887 209984 82943 4.57723 4.57723 -694.457 -4.57723 0 0 1.23909e+06 6321.90 0.09 0.15 0.39 -1 -1 0.09 0.0903946 0.0866517 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt index 314721e6341..23cf7b0b85f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 17.10 vpr 78.69 MiB 0.17 10856 -1 -1 1 0.12 -1 -1 34140 -1 -1 23 130 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 80580 130 40 1203 1030 1 586 196 14 14 196 dsp_top auto 38.7 MiB 0.49 2582 41733 12251 23272 6210 78.7 MiB 0.33 0.01 6.49756 -686.499 -6.49756 6.49756 0.76 0.00167814 0.00153244 0.158674 0.146165 -1 -1 -1 -1 108 5040 43 4.93594e+06 1.40315e+06 1.55765e+06 7947.21 11.29 1.3413 1.19961 36552 325092 -1 4509 22 2486 2554 274402 92406 6.62048 6.62048 -743.865 -6.62048 0 0 1.93951e+06 9895.46 0.56 0.19 0.69 -1 -1 0.56 0.107178 0.0988592 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 14.85 vpr 81.40 MiB 0.10 11392 -1 -1 1 0.12 -1 -1 37676 -1 -1 23 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83352 130 40 1203 1030 1 586 196 14 14 196 dsp_top auto 41.3 MiB 0.63 2691 46285 14724 25599 5962 81.4 MiB 0.45 0.01 6.58999 -703.566 -6.58999 6.58999 0.48 0.00220042 0.00200207 0.214554 0.193316 -1 -1 -1 -1 108 5210 35 4.93594e+06 1.40315e+06 1.55765e+06 7947.21 10.07 1.93637 1.74105 36552 325092 -1 4641 23 2669 2746 326887 113256 6.77766 6.77766 -770.287 -6.77766 0 0 1.93951e+06 9895.46 0.12 0.27 0.65 -1 -1 0.12 0.138318 0.125698 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt index 44b0c3fb49b..235e1da0107 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.85 vpr 70.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71840 130 150 1169 1319 1 886 363 12 12 144 clb auto 30.0 MiB 1.25 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00639293 0.00599457 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.78 vpr 69.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71156 130 150 1216 1366 1 933 370 12 12 144 clb auto 29.8 MiB 1.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0055812 0.00507678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.88 vpr 72.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74068 130 150 1169 1319 1 886 363 12 12 144 clb auto 32.4 MiB 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00708147 0.00640458 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 2.22 vpr 72.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73804 130 150 1216 1366 1 933 370 12 12 144 clb auto 32.3 MiB 1.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00920908 0.00830291 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt index 9750f0dd17a..d3c7d61af84 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.31 vpr 64.46 MiB 0.07 9980 -1 -1 4 0.20 -1 -1 33464 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66008 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.10 421 2049 269 1715 65 64.5 MiB 0.04 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 0.000669291 0.000596999 0.0160309 0.0145218 -1 -1 -1 -1 424 4.46316 163 1.71579 617 1399 45810 10033 1.07788e+06 1.02399e+06 207176. 4228.08 16 4440 29880 -1 2.36464 2.27781 -179.43 -2.36464 0 0 0.04 -1 -1 64.5 MiB 0.05 0.0483486 0.0432361 64.5 MiB -1 0.04 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.59 vpr 66.95 MiB 0.07 10224 -1 -1 5 0.19 -1 -1 33224 -1 -1 14 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68560 11 30 313 321 2 115 55 7 7 49 clb auto 27.2 MiB 0.33 466 2759 556 2108 95 67.0 MiB 0.05 0.00 2.67362 -172.647 -2.67362 2.30794 0.00 0.000721207 0.000645031 0.0268996 0.0245416 -1 -1 -1 -1 574 5.26606 231 2.11927 216 452 11450 3638 1.07788e+06 754516 219490. 4479.39 7 5100 32136 -1 2.71877 2.35385 -178.475 -2.71877 0 0 0.04 -1 -1 67.0 MiB 0.03 0.0557218 0.0513892 67.0 MiB -1 0.04 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.36 vpr 66.46 MiB 0.08 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68060 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.08 425 2283 406 1804 73 66.5 MiB 0.05 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000768694 0.000638603 0.0252644 0.022728 -1 -1 -1 -1 414 4.35789 166 1.74737 630 1427 58282 13907 1.07788e+06 1.02399e+06 207176. 4228.08 20 4440 29880 -1 2.3823 2.2863 -180.577 -2.3823 0 0 0.05 -1 -1 66.5 MiB 0.08 0.0775573 0.0705898 66.5 MiB -1 0.01 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.76 vpr 69.14 MiB 0.09 10368 -1 -1 5 0.19 -1 -1 36576 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70804 11 30 313 321 2 115 55 7 7 49 clb auto 29.7 MiB 0.40 448 1927 352 1502 73 69.1 MiB 0.07 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.000863635 0.000740182 0.0221309 0.0195205 -1 -1 -1 -1 595 5.45872 228 2.09174 234 449 14202 4622 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 2.70461 2.28805 -176.84 -2.70461 0 0 0.05 -1 -1 69.1 MiB 0.06 0.0568064 0.051944 69.1 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt index 297d9cc2e7d..df63a32e433 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.34 vpr 65.27 MiB 0.06 9400 -1 -1 3 0.30 -1 -1 34668 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66836 99 130 363 493 1 251 298 12 12 144 clb auto 26.0 MiB 0.14 973 1293 313 844 136 65.3 MiB 0.07 0.00 2.2425 -218.261 -2.2425 2.2425 0.39 0.000963196 0.000901211 0.00562254 0.00542751 -1 -1 -1 -1 36 1866 35 5.66058e+06 4.21279e+06 305235. 2119.69 1.87 0.362594 0.328428 12238 58442 -1 1566 9 567 738 58151 19831 2.59207 2.59207 -232.729 -2.59207 0 0 378970. 2631.74 0.12 0.05 0.07 -1 -1 0.12 0.0271537 0.0253871 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.27 vpr 67.81 MiB 0.06 9984 -1 -1 3 0.40 -1 -1 39908 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69436 99 130 363 493 1 251 298 12 12 144 clb auto 28.8 MiB 0.14 1080 1293 313 846 134 67.8 MiB 0.06 0.00 2.45187 -223.196 -2.45187 2.45187 0.31 0.000607122 0.000549979 0.00491114 0.00472929 -1 -1 -1 -1 34 2076 26 5.66058e+06 4.21279e+06 293002. 2034.74 1.92 0.386002 0.351306 12094 55633 -1 1662 10 540 720 43948 13958 2.71514 2.71514 -233.572 -2.71514 0 0 360780. 2505.42 0.02 0.06 0.08 -1 -1 0.02 0.0335019 0.0302667 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt index 75b4dc8cff1..c57ad9bdb40 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml styr.blif common 2.49 vpr 58.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59988 10 10 253 263 1 165 89 11 11 121 clb auto 18.8 MiB 0.05 1298 4445 695 3556 194 58.6 MiB 0.05 0.00 5.53812 -72.6437 -5.53812 5.53812 0.17 0.000586889 0.000523181 0.0184266 0.016854 -1 -1 -1 -1 14 2029 36 2.43e+06 2.07e+06 -1 -1 1.20 0.252134 0.219147 3402 27531 -1 1944 19 1218 4569 249188 30978 7.47374 7.47374 -94.8537 -7.47374 0 0 -1 -1 0.06 0.11 0.02 -1 -1 0.06 0.0414153 0.0362194 - k4_n4_v7_longline_bidir.xml styr.blif common 2.81 vpr 58.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59496 10 10 253 263 1 165 89 11 11 121 clb auto 18.9 MiB 0.06 1243 3851 530 3175 146 58.1 MiB 0.04 0.00 4.42129 -53.6285 -4.42129 4.42129 0.23 0.000610037 0.000548673 0.0158349 0.0144995 -1 -1 -1 -1 19 2381 26 2.43e+06 2.07e+06 -1 -1 1.40 0.224268 0.192635 3282 34431 -1 2331 24 1499 5264 384444 46394 8.40637 8.40637 -105.933 -8.40637 0 0 -1 -1 0.07 0.11 0.02 -1 -1 0.07 0.0377239 0.0326406 - k4_n4_v7_l1_bidir.xml styr.blif common 4.06 vpr 58.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60052 10 10 253 263 1 165 89 11 11 121 clb auto 18.9 MiB 0.06 1249 6821 1452 5028 341 58.6 MiB 0.06 0.00 6.30077 -80.949 -6.30077 6.30077 0.22 0.000518755 0.000463783 0.0228285 0.0206741 -1 -1 -1 -1 10 1483 31 2.43e+06 2.07e+06 -1 -1 2.61 0.268076 0.234279 4482 22551 -1 1280 20 1321 4798 303501 58064 7.52318 7.52318 -89.7629 -7.52318 0 0 -1 -1 0.04 0.12 0.02 -1 -1 0.04 0.037522 0.0333295 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.10 vpr 58.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59416 10 10 253 263 1 165 89 11 11 121 clb auto 18.8 MiB 0.05 1252 4247 601 3492 154 58.0 MiB 0.05 0.00 3.38007 -43.5291 -3.38007 3.38007 0.18 0.00064054 0.000577227 0.0176541 0.0161473 -1 -1 -1 -1 14 2047 30 2.43e+06 2.07e+06 -1 -1 1.68 0.248457 0.216641 3402 27531 -1 2099 29 1484 5383 889715 156716 22.7353 22.7353 -261.092 -22.7353 0 0 -1 -1 0.05 0.25 0.02 -1 -1 0.05 0.0493955 0.0438566 + k4_n4_v7_bidir.xml styr.blif common 1.89 vpr 61.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62636 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.06 1288 4445 682 3619 144 61.2 MiB 0.05 0.00 5.46014 -72.9505 -5.46014 5.46014 0.09 0.000707997 0.000614185 0.0204147 0.0180597 -1 -1 -1 -1 14 2036 29 2.43e+06 2.07e+06 -1 -1 0.97 0.236366 0.209157 3402 27531 -1 1911 15 1185 4098 215222 27160 6.9309 6.9309 -92.2142 -6.9309 0 0 -1 -1 0.01 0.10 0.02 -1 -1 0.01 0.0335803 0.0304927 + k4_n4_v7_longline_bidir.xml styr.blif common 1.77 vpr 60.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61816 10 10 253 263 1 165 89 11 11 121 clb auto 21.3 MiB 0.05 1219 4247 600 3483 164 60.4 MiB 0.05 0.00 4.42494 -53.3169 -4.42494 4.42494 0.10 0.000681666 0.000592315 0.0189188 0.016758 -1 -1 -1 -1 18 2215 40 2.43e+06 2.07e+06 -1 -1 0.80 0.256847 0.227018 3282 34431 -1 2139 18 1151 3756 254207 31830 9.07319 9.07319 -108.035 -9.07319 0 0 -1 -1 0.02 0.10 0.03 -1 -1 0.02 0.0370258 0.033411 + k4_n4_v7_l1_bidir.xml styr.blif common 2.35 vpr 61.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62632 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.05 1285 7613 1616 5547 450 61.2 MiB 0.12 0.00 6.9252 -85.9419 -6.9252 6.9252 0.14 0.000675324 0.000585254 0.0347554 0.0308708 -1 -1 -1 -1 10 1481 31 2.43e+06 2.07e+06 -1 -1 1.17 0.183607 0.16336 4482 22551 -1 1268 22 1168 4312 263452 47622 7.30329 7.30329 -93.8299 -7.30329 0 0 -1 -1 0.01 0.13 0.02 -1 -1 0.01 0.0396264 0.0357171 + k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.49 vpr 60.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61772 10 10 253 263 1 165 89 11 11 121 clb auto 21.2 MiB 0.05 1234 4643 666 3821 156 60.3 MiB 0.09 0.01 3.51175 -43.7413 -3.51175 3.51175 0.09 0.000766831 0.000671887 0.0247522 0.0222268 -1 -1 -1 -1 14 2053 42 2.43e+06 2.07e+06 -1 -1 2.23 0.282741 0.249953 3402 27531 -1 1991 28 1438 5059 778762 132220 26.9853 26.9853 -248.248 -26.9853 0 0 -1 -1 0.01 0.37 0.03 -1 -1 0.01 0.0480187 0.0429407 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt index 84fc98735c4..0bd2ba5a636 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.95 vpr 64.38 MiB 0.06 10036 -1 -1 4 0.21 -1 -1 33304 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65924 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.09 439 1932 239 1639 54 64.4 MiB 0.03 0.00 2.45489 -180.196 -2.45489 2.33213 0.07 0.000611032 0.000541625 0.0144591 0.0130681 -1 -1 -1 -1 20 684 34 1.07788e+06 1.02399e+06 49980.0 1020.00 0.25 0.116805 0.09949 2664 9102 -1 585 25 992 2191 68660 23567 2.62928 2.46785 -187.223 -2.62928 0 0 65453.8 1335.79 0.02 0.07 0.01 -1 -1 0.02 0.0375678 0.0325723 - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 2.27 vpr 64.50 MiB 0.06 9904 -1 -1 4 0.20 -1 -1 33384 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66052 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 439 1932 239 1639 54 64.5 MiB 0.04 0.00 2.45489 -180.196 -2.45489 2.33213 0.08 0.000680402 0.00060982 0.017209 0.0157151 -1 -1 -1 -1 20 684 34 1.07788e+06 1.02399e+06 49980.0 1020.00 0.55 0.238978 0.201081 2664 9102 -1 585 25 992 2191 68660 23567 2.62928 2.46785 -187.223 -2.62928 0 0 65453.8 1335.79 0.02 0.07 0.01 -1 -1 0.02 0.0406365 0.0353306 + k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.92 vpr 66.34 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36540 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67936 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 427 1815 293 1474 48 66.3 MiB 0.03 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.000749649 0.00064239 0.0161237 0.0140852 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.28 0.147245 0.127953 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.08 0.01 -1 -1 0.00 0.047308 0.0404063 + k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 2.40 vpr 66.13 MiB 0.07 10368 -1 -1 4 0.23 -1 -1 36792 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67716 11 30 262 292 2 99 60 7 7 49 clb auto 27.2 MiB 0.08 427 1815 293 1474 48 66.1 MiB 0.04 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.000744837 0.000636456 0.0185703 0.0149662 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.64 0.298818 0.25277 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.10 0.01 -1 -1 0.00 0.0500747 0.044978 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt index 46602a07176..7d75ebf7e22 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 4.95 vpr 65.09 MiB 0.05 9384 -1 -1 3 0.35 -1 -1 34600 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66648 99 130 363 493 1 255 305 13 13 169 clb auto 25.3 MiB 0.09 908 74177 24418 37403 12356 65.1 MiB 0.21 0.00 2.24932 -227.778 -2.24932 2.24932 0.43 0.000870718 0.000814627 0.0677126 0.0632932 -1 -1 -1 -1 32 1516 16 6.63067e+06 4.59005e+06 323148. 1912.12 2.19 0.456283 0.413595 11612 59521 -1 1275 27 730 1142 95340 32482 2.40779 2.40779 -232.565 -2.40779 0 0 396943. 2348.77 0.14 0.10 0.06 -1 -1 0.14 0.055174 0.0502939 - k6_N10_mem32K_40nm.xml diffeq1.v common 10.90 vpr 68.98 MiB 0.04 9404 -1 -1 15 0.48 -1 -1 34660 -1 -1 60 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70636 162 96 999 932 1 661 323 16 16 256 mult_36 auto 28.8 MiB 0.31 5495 75599 21207 48608 5784 69.0 MiB 0.55 0.01 21.6615 -1879.46 -21.6615 21.6615 0.70 0.00319094 0.00302093 0.229143 0.215114 -1 -1 -1 -1 44 10097 29 1.21132e+07 5.21364e+06 665287. 2598.78 6.02 1.39802 1.29282 20656 131250 -1 8720 22 3466 7443 973330 268208 22.2123 22.2123 -1936.09 -22.2123 0 0 864808. 3378.16 0.31 0.42 0.14 -1 -1 0.31 0.180893 0.168332 - k6_N10_mem32K_40nm.xml single_wire.v common 0.55 vpr 63.05 MiB 0.01 6576 -1 -1 1 0.02 -1 -1 30004 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64568 1 1 1 2 0 1 2 3 3 9 -1 auto 24.3 MiB 0.00 2 3 0 3 0 63.1 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.1357e-05 6.922e-06 7.8063e-05 5.3338e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.0015524 0.00147403 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00228467 0.00224801 - k6_N10_mem32K_40nm.xml single_ff.v common 0.54 vpr 62.95 MiB 0.01 6420 -1 -1 1 0.02 -1 -1 30176 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64464 2 1 3 4 1 3 4 3 3 9 -1 auto 24.2 MiB 0.00 6 9 5 1 3 63.0 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.4537e-05 1.0143e-05 0.00010139 7.6283e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00162892 0.00154661 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00170661 0.00165742 - k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 9.72 vpr 65.00 MiB 0.06 9380 -1 -1 3 0.32 -1 -1 34636 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66556 99 130 363 493 1 255 305 19 19 361 o auto 25.3 MiB 0.09 1017 84437 21849 44018 18570 65.0 MiB 0.27 0.00 2.33845 -237.624 -2.33845 2.33845 2.83 0.00101195 0.000938816 0.0893341 0.0836814 -1 -1 -1 -1 36 1395 26 1.79173e+07 4.59005e+06 833707. 2309.44 3.44 0.417472 0.379057 24998 161561 -1 1299 23 891 1465 81711 22668 2.61943 2.61943 -244.023 -2.61943 0 0 1.02328e+06 2834.56 0.39 0.08 0.14 -1 -1 0.39 0.042041 0.0384715 - k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 24.30 vpr 83.81 MiB 0.04 9376 -1 -1 15 0.46 -1 -1 34644 -1 -1 60 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 85820 162 96 999 932 1 661 323 24 24 576 i auto 28.7 MiB 0.31 7217 101060 28985 60644 11431 83.8 MiB 0.72 0.01 21.9602 -1888.96 -21.9602 21.9602 4.32 0.00297924 0.00279786 0.307712 0.28877 -1 -1 -1 -1 32 14521 46 3.08128e+07 5.21364e+06 1.24505e+06 2161.54 14.07 1.70494 1.57192 39974 242477 -1 11428 25 4677 10335 1474881 391876 23.1722 23.1722 -1992.17 -23.1722 0 0 1.54255e+06 2678.04 0.44 0.51 0.21 -1 -1 0.44 0.195655 0.181464 - k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.58 vpr 62.93 MiB 0.01 6452 -1 -1 1 0.02 -1 -1 30116 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64440 1 1 1 2 0 1 2 4 4 16 i auto 24.2 MiB 0.00 3 3 0 0 3 62.9 MiB 0.00 0.00 0.280667 -0.280667 -0.280667 nan 0.01 9.703e-06 5.942e-06 7.6566e-05 5.0557e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.01 0.00148096 0.00139624 324 600 -1 2 1 1 1 16 6 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.00141364 0.00138107 - k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.64 vpr 62.77 MiB 0.01 6452 -1 -1 1 0.04 -1 -1 29928 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64280 2 1 3 4 1 3 4 4 4 16 i auto 24.0 MiB 0.00 7 9 0 2 7 62.8 MiB 0.00 0.00 0.647256 -1.07419 -0.647256 0.647256 0.01 1.9097e-05 1.4095e-05 0.000118864 8.987e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.00164593 0.00153585 340 760 -1 3 2 3 3 71 25 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00152593 0.00147741 + k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.32 vpr 67.44 MiB 0.07 9856 -1 -1 3 0.36 -1 -1 39552 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69060 99 130 363 493 1 255 305 13 13 169 clb auto 27.9 MiB 0.11 817 73151 23083 37131 12937 67.4 MiB 0.30 0.01 2.36834 -235.63 -2.36834 2.36834 0.29 0.00233393 0.00223993 0.0738859 0.066584 -1 -1 -1 -1 32 1352 17 6.63067e+06 4.59005e+06 323148. 1912.12 0.52 0.196726 0.178694 11612 59521 -1 1138 16 719 1086 65347 22389 2.48507 2.48507 -238.178 -2.48507 0 0 396943. 2348.77 0.02 0.13 0.12 -1 -1 0.02 0.0517727 0.0472555 + k6_N10_mem32K_40nm.xml diffeq1.v common 10.12 vpr 70.60 MiB 0.03 9856 -1 -1 15 0.44 -1 -1 38380 -1 -1 60 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72292 162 96 999 932 1 661 323 16 16 256 mult_36 auto 31.3 MiB 0.38 5531 95525 26953 60139 8433 70.6 MiB 0.91 0.01 21.9361 -1891.35 -21.9361 21.9361 0.47 0.00396915 0.00366377 0.403824 0.374905 -1 -1 -1 -1 44 11294 43 1.21132e+07 5.21364e+06 665287. 2598.78 5.71 1.78116 1.66467 20656 131250 -1 8771 24 4066 8799 1047369 299882 22.5944 22.5944 -1935.68 -22.5944 0 0 864808. 3378.16 0.04 0.50 0.16 -1 -1 0.04 0.234899 0.221057 + k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 65.29 MiB 0.01 6912 -1 -1 1 0.02 -1 -1 32916 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 1 1 1 2 0 1 2 3 3 9 -1 auto 27.0 MiB 0.00 2 3 0 3 0 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0231e-05 6.013e-06 7.2755e-05 4.8573e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00153872 0.00147005 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00109157 0.00106485 + k6_N10_mem32K_40nm.xml single_ff.v common 0.49 vpr 65.16 MiB 0.01 7040 -1 -1 1 0.02 -1 -1 33280 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66728 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 6 9 5 1 3 65.2 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5008e-05 1.0331e-05 0.000105161 7.8059e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.0016194 0.0015365 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00112886 0.00109032 + k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 5.85 vpr 67.48 MiB 0.06 9856 -1 -1 3 0.36 -1 -1 39692 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69100 99 130 363 493 1 255 305 19 19 361 o auto 27.9 MiB 0.10 1043 75203 18688 40447 16068 67.5 MiB 0.27 0.00 2.5827 -243.865 -2.5827 2.5827 1.92 0.000939884 0.00084584 0.0725048 0.0652395 -1 -1 -1 -1 36 1432 20 1.79173e+07 4.59005e+06 833707. 2309.44 1.36 0.302543 0.27272 24998 161561 -1 1342 23 802 1298 88966 26229 2.93129 2.93129 -249.701 -2.93129 0 0 1.02328e+06 2834.56 0.07 0.10 0.15 -1 -1 0.07 0.0554021 0.0511266 + k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 12.40 vpr 79.29 MiB 0.04 9856 -1 -1 15 0.45 -1 -1 38032 -1 -1 60 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 81188 162 96 999 932 1 661 323 24 24 576 i auto 31.0 MiB 0.28 7114 95525 25526 57948 12051 79.3 MiB 0.94 0.01 21.4854 -1914.4 -21.4854 21.4854 3.35 0.00392701 0.00363416 0.415599 0.386608 -1 -1 -1 -1 32 12804 30 3.08128e+07 5.21364e+06 1.24505e+06 2161.54 3.94 1.18592 1.11276 39974 242477 -1 10817 26 4455 9936 1378660 349639 22.5193 22.5193 -2054.22 -22.5193 0 0 1.54255e+06 2678.04 0.12 0.65 0.37 -1 -1 0.12 0.246186 0.231211 + k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.47 vpr 65.28 MiB 0.02 6784 -1 -1 1 0.02 -1 -1 33172 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66848 1 1 1 2 0 1 2 4 4 16 i auto 26.9 MiB 0.00 3 3 0 0 3 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.1306e-05 5.604e-06 7.2139e-05 4.6493e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.00155951 0.00148904 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.0014785 0.00144447 + k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.49 vpr 65.16 MiB 0.02 7040 -1 -1 1 0.02 -1 -1 33288 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 4 4 16 i auto 26.9 MiB 0.00 7 9 0 2 7 65.2 MiB 0.00 0.00 0.55247 -0.955943 -0.55247 0.55247 0.00 1.6222e-05 1.0832e-05 0.00010458 7.8535e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.00166008 0.00157112 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00159511 0.00154443 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt index b913a54f802..a4f4578b4e4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.03 vpr 64.66 MiB 0.05 9936 -1 -1 4 0.20 -1 -1 33284 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66212 11 30 262 292 2 99 60 7 7 49 clb auto 24.9 MiB 0.09 440 2400 452 1846 102 64.7 MiB 0.01 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 18 660 35 1.07788e+06 1.02399e+06 45686.6 932.380 0.48 0.165713 0.138611 2616 8308 -1 541 24 785 1721 49987 17392 2.55392 2.37233 -184.833 -2.55392 0 0 59124.6 1206.62 0.01 0.07 0.01 -1 -1 0.01 0.0397954 0.0348173 + k6_N10_mem32K_40nm.xml stereovision3.v common 2.22 vpr 66.21 MiB 0.06 10368 -1 -1 4 0.23 -1 -1 36792 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67796 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 485 3687 781 2795 111 66.2 MiB 0.01 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 18 734 39 1.07788e+06 1.02399e+06 45686.6 932.380 0.65 0.239065 0.204044 2616 8308 -1 583 23 761 1801 50764 16568 2.52485 2.36559 -186.102 -2.52485 0 0 59124.6 1206.62 0.00 0.07 0.01 -1 -1 0.00 0.0486043 0.0430292 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt index eb38f9839e9..d3b62c629ad 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common_--check_route_full 6.55 vpr 56.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57924 6 7 19 26 0 19 26 3 3 9 -1 auto 17.8 MiB 0.01 51 216 43 63 110 56.6 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 5.46 4.4866e-05 3.8779e-05 0.000407849 0.000352025 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.09 0.0024538 0.00222966 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.04 -1 -1 0.00 0.00174299 0.00165115 - sub_tiles.xml sub_tiles.blif common_--check_route_quick 7.53 vpr 56.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58092 6 7 19 26 0 19 26 3 3 9 -1 auto 18.1 MiB 0.00 51 216 43 63 110 56.7 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 6.42 3.9294e-05 3.2838e-05 0.000360177 0.000299223 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.11 0.00240249 0.00218766 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.04 -1 -1 0.00 0.00179459 0.00169524 - sub_tiles.xml sub_tiles.blif common_--check_route_off 6.86 vpr 56.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57856 6 7 19 26 0 19 26 3 3 9 -1 auto 17.8 MiB 0.00 51 216 43 63 110 56.5 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 5.82 4.4091e-05 3.8299e-05 0.000449038 0.000394449 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.08 0.00230139 0.00207606 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.04 -1 -1 0.00 0.00164487 0.00155669 + sub_tiles.xml sub_tiles.blif common_--check_route_full 14.36 vpr 58.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60212 6 7 19 26 0 19 26 3 3 9 -1 auto 20.5 MiB 0.00 51 216 43 63 110 58.8 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 13.10 4.6187e-05 3.8396e-05 0.000395937 0.000323618 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00202221 0.00179313 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00173217 0.0016394 + sub_tiles.xml sub_tiles.blif common_--check_route_quick 16.94 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.28 4.6086e-05 3.7994e-05 0.000373556 0.000302701 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.13 0.00235088 0.00212378 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00221042 0.00197359 + sub_tiles.xml sub_tiles.blif common_--check_route_off 16.20 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60476 6 7 19 26 0 19 26 3 3 9 -1 auto 20.7 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 14.72 4.2295e-05 3.5105e-05 0.000363474 0.000296118 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00229484 0.00207762 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00174454 0.00165562 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt index 573110a1f9d..7b6b29fbf31 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.67 vpr 63.84 MiB 0.01 6676 -1 -1 1 0.03 -1 -1 30204 -1 -1 3 9 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65376 9 8 71 66 1 35 20 5 5 25 clb auto 24.5 MiB 0.59 106 155 56 98 1 63.8 MiB 0.01 0.00 2.68643 -28.4691 -2.68643 2.68643 0.03 0.000140881 0.000128293 0.00202868 0.00191784 -1 -1 -1 -1 24 237 22 151211 75605.7 33517.4 1340.70 0.18 0.041091 0.034289 1884 5578 -1 191 17 213 274 8835 4764 3.58807 3.58807 -39.9558 -3.58807 0 0 43252.0 1730.08 0.00 0.02 0.01 -1 -1 0.00 0.00832021 0.00744946 14 17 16 6 0 0 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 6.57 vpr 65.18 MiB 0.01 6688 -1 -1 1 0.04 -1 -1 30640 -1 -1 8 19 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66748 19 18 299 240 1 146 45 6 6 36 clb auto 25.6 MiB 4.69 492 845 209 626 10 65.2 MiB 0.02 0.00 4.85986 -99.0252 -4.85986 4.85986 0.05 0.000469766 0.000432273 0.00954877 0.00903161 -1 -1 -1 -1 50 1141 29 403230 201615 107229. 2978.57 0.79 0.20538 0.176607 3946 19047 -1 909 23 1044 1578 59654 24287 5.61482 5.61482 -122.009 -5.61482 0 0 134937. 3748.26 0.02 0.06 0.02 -1 -1 0.02 0.032608 0.0295156 62 82 85 13 0 0 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.50 vpr 66.18 MiB 0.01 6912 -1 -1 1 0.03 -1 -1 33524 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67768 9 8 71 66 1 35 20 5 5 25 clb auto 27.2 MiB 0.61 102 641 211 420 10 66.2 MiB 0.01 0.00 2.52843 -27.3721 -2.52843 2.52843 0.02 0.000162932 0.000142933 0.00487777 0.00439017 -1 -1 -1 -1 32 152 12 151211 75605.7 43252.0 1730.08 0.15 0.05219 0.0443549 2004 6761 -1 170 13 131 173 5906 3259 2.68643 2.68643 -34.5837 -2.68643 0 0 52324.5 2092.98 0.00 0.01 0.01 -1 -1 0.00 0.00766663 0.00704697 14 17 16 6 0 0 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 6.42 vpr 67.07 MiB 0.01 6912 -1 -1 1 0.04 -1 -1 33628 -1 -1 8 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68680 19 18 299 240 1 146 45 6 6 36 clb auto 27.6 MiB 4.94 477 2365 468 1860 37 67.1 MiB 0.04 0.00 4.92757 -99.6523 -4.92757 4.92757 0.05 0.000316619 0.0002807 0.0196432 0.0179661 -1 -1 -1 -1 54 1052 25 403230 201615 113905. 3164.04 0.53 0.17427 0.152991 4050 20995 -1 792 24 850 1349 48852 19559 4.89358 4.89358 -108.576 -4.89358 0 0 146644. 4073.44 0.00 0.05 0.03 -1 -1 0.00 0.0285954 0.0259387 62 82 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt index bd8837584d4..82e16e68c58 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.38 vpr 57.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58828 1 4 28 32 2 10 9 4 4 16 clb auto 18.5 MiB 0.01 21 27 11 8 8 57.4 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.9608e-05 6.1171e-05 0.000528542 0.000484521 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.03 0.00817962 0.0068183 672 1128 -1 13 8 23 23 458 156 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00303766 0.0027903 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.40 vpr 57.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58924 1 4 28 32 2 10 9 4 4 16 clb auto 18.6 MiB 0.01 21 27 11 8 8 57.5 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.7493e-05 5.9709e-05 0.00053006 0.00048841 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.03 0.00837217 0.00702901 672 1128 -1 13 8 23 23 458 156 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00268284 0.00246934 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.45 vpr 57.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58868 1 4 28 32 2 10 9 4 4 16 clb auto 18.4 MiB 0.01 21 27 11 8 8 57.5 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.8738e-05 6.0915e-05 0.000598804 0.000552999 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.03 0.00819817 0.00689289 672 1128 -1 13 8 23 23 458 156 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00319689 0.00291899 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.35 vpr 59.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61244 1 4 28 32 2 10 9 4 4 16 clb auto 21.2 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.9876e-05 6.8917e-05 0.000564474 0.000511898 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00933145 0.00790294 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0020437 0.00190467 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.33 vpr 60.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61444 1 4 28 32 2 10 9 4 4 16 clb auto 21.5 MiB 0.01 21 27 10 10 7 60.0 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 9.3379e-05 8.2596e-05 0.000566541 0.000512464 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00867291 0.00731794 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00253268 0.00233063 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.35 vpr 59.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61264 1 4 28 32 2 10 9 4 4 16 clb auto 21.4 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.8562e-05 6.7163e-05 0.000561289 0.000507136 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00963983 0.0081025 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00296634 0.00273132 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt index c24f6849f4e..17671e26cfa 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.46 vpr 57.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58704 2 2 22 24 2 4 6 4 4 16 clb auto 18.4 MiB 0.01 8 15 5 7 3 57.3 MiB 0.00 0.00 1.297 0 0 1.297 0.01 5.2494e-05 4.4634e-05 0.000448571 0.000405419 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.00281216 0.00261739 660 1032 -1 15 4 8 8 614 487 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00226716 0.00212992 + timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.35 vpr 59.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61088 2 2 22 24 2 4 6 4 4 16 clb auto 21.2 MiB 0.01 8 15 5 7 3 59.7 MiB 0.00 0.00 1.297 0 0 1.297 0.01 6.7393e-05 5.6956e-05 0.000402551 0.000351966 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.00291274 0.00268287 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00264613 0.00228889 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt index 82ec46d8b99..55f3e1dd3ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.66039 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt index cfd2d545cc8..c54c9279c53 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.41 vpr 57.28 MiB 0.00 6388 -1 -1 1 0.03 -1 -1 29960 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58652 2 1 3 4 1 3 4 3 3 9 -1 auto 18.6 MiB 0.00 6 9 3 5 1 57.3 MiB 0.04 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 2.1796e-05 1.6522e-05 0.000193754 0.00015861 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00168667 0.00157156 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.39 vpr 57.19 MiB 0.00 6340 -1 -1 1 0.03 -1 -1 29884 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58560 2 1 3 4 1 3 4 3 3 9 -1 auto 18.5 MiB 0.00 9 9 3 3 3 57.2 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.7329e-05 1.1723e-05 0.000120696 9.1803e-05 -1 -1 -1 -1 -1 4 3 18000 18000 15707.9 1745.32 0.00 0.00149934 0.00140654 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 5.17 vpr 59.21 MiB 0.36 59164 -1 -1 2 1.59 -1 -1 50532 -1 -1 155 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60628 5 156 191 347 1 163 316 15 15 225 clb auto 19.6 MiB 0.04 29 84166 60542 3208 20416 59.2 MiB 0.13 0.00 1.49664 -15.1312 -1.49664 1.49664 0.00 0.000406843 0.000383604 0.0325033 0.0306122 -1 -1 -1 -1 -1 40 7 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0416902 0.0390742 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 5.29 vpr 59.23 MiB 0.44 59264 -1 -1 2 1.66 -1 -1 50664 -1 -1 155 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60656 5 156 191 347 1 163 316 15 15 225 clb auto 19.6 MiB 0.04 36 74491 53339 3165 17987 59.2 MiB 0.11 0.00 1.49775 -14.6149 -1.49775 1.49775 0.00 0.000376659 0.000354057 0.027722 0.0260055 -1 -1 -1 -1 -1 54 6 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0361212 0.0337603 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.34 vpr 62.88 MiB 0.01 6524 -1 -1 1 0.03 -1 -1 30032 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64384 2 1 3 4 1 3 4 3 3 9 -1 auto 24.1 MiB 0.00 6 9 3 5 1 62.9 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.8462e-05 1.3116e-05 0.000143184 0.000107932 -1 -1 -1 -1 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.00154548 0.00142994 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.38 vpr 62.88 MiB 0.01 6520 -1 -1 1 0.02 -1 -1 29980 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64388 2 1 3 4 1 3 4 3 3 9 -1 auto 24.1 MiB 0.00 9 9 3 3 3 62.9 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.7389e-05 1.2439e-05 0.000110474 8.1262e-05 -1 -1 -1 -1 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.00162603 0.00153736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 4.85 vpr 69.68 MiB 0.15 16496 -1 -1 2 0.15 -1 -1 33692 -1 -1 43 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71352 311 156 972 1128 1 953 525 28 28 784 memory auto 30.0 MiB 0.53 9455 210108 77830 122308 9970 69.7 MiB 1.15 0.02 3.97422 -4336.45 -3.97422 3.97422 0.00 0.00487926 0.00437885 0.503553 0.447369 -1 -1 -1 -1 -1 13425 12 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.40 0.699755 0.628908 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 5.65 vpr 69.53 MiB 0.19 16512 -1 -1 2 0.16 -1 -1 33768 -1 -1 43 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71200 311 156 972 1128 1 953 525 28 28 784 memory auto 29.9 MiB 0.55 9870 203757 68308 124561 10888 69.5 MiB 1.17 0.02 3.91483 -3854.15 -3.91483 3.91483 0.00 0.00501054 0.00442487 0.50283 0.44465 -1 -1 -1 -1 -1 13822 12 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.47 0.720818 0.646017 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 + timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.26 vpr 59.67 MiB 0.00 6912 -1 -1 1 0.02 -1 -1 33484 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61100 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 6 9 3 5 1 59.7 MiB 0.00 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 1.4271e-05 9.019e-06 0.000105429 7.7044e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00167801 0.00157995 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 + timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.26 vpr 59.67 MiB 0.00 6912 -1 -1 1 0.02 -1 -1 33216 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61100 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 9 9 3 3 3 59.7 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.5585e-05 1.0104e-05 0.000105029 7.6023e-05 -1 -1 -1 -1 -1 4 3 18000 18000 15707.9 1745.32 0.00 0.00153942 0.00144868 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 + timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 4.33 abc 63.01 MiB 0.24 59520 -1 -1 2 1.56 -1 -1 64520 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63024 5 156 191 347 1 163 316 15 15 225 clb auto 22.0 MiB 0.04 29 82016 58904 3157 19955 61.5 MiB 0.15 0.00 1.49664 -15.1312 -1.49664 1.49664 0.00 0.000408132 0.000370067 0.0341355 0.031078 -1 -1 -1 -1 -1 32 6 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0428942 0.0391583 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 + timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 4.51 abc 63.14 MiB 0.34 59776 -1 -1 2 1.51 -1 -1 64652 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63260 5 156 191 347 1 163 316 15 15 225 clb auto 22.2 MiB 0.02 41 76641 54775 3226 18640 61.8 MiB 0.14 0.00 1.49775 -14.6172 -1.49775 1.49775 0.00 0.000395712 0.000358237 0.0299271 0.0269791 -1 -1 -1 -1 -1 63 5 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0377601 0.0341837 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 + timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.33 vpr 65.29 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33412 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 2 1 3 4 1 3 4 3 3 9 -1 auto 26.8 MiB 0.00 6 9 3 5 1 65.3 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5615e-05 1.0606e-05 0.000109326 8.0241e-05 -1 -1 -1 -1 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.00165784 0.00156601 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 + timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.25 vpr 65.38 MiB 0.01 7040 -1 -1 1 0.02 -1 -1 33208 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66952 2 1 3 4 1 3 4 3 3 9 -1 auto 27.1 MiB 0.00 9 9 3 3 3 65.4 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.6671e-05 1.1297e-05 0.000111494 8.1284e-05 -1 -1 -1 -1 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.00178932 0.0017001 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 + timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 4.46 vpr 71.98 MiB 0.15 16896 -1 -1 2 0.16 -1 -1 37600 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73704 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.58 8394 210108 78030 120895 11183 72.0 MiB 1.33 0.02 3.90475 -4339.03 -3.90475 3.90475 0.00 0.00537924 0.00456001 0.565099 0.476317 -1 -1 -1 -1 -1 12247 12 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.38 0.731735 0.628685 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 + timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 4.57 vpr 72.21 MiB 0.16 17152 -1 -1 2 0.16 -1 -1 37596 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73948 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.52 9639 203757 70988 121974 10795 72.2 MiB 1.36 0.02 4.05379 -3834.49 -4.05379 4.05379 0.00 0.00624609 0.00547423 0.627089 0.535493 -1 -1 -1 -1 -1 13797 11 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.48 0.824983 0.713955 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt index 0dd8c10602e..270c7d97d80 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.74 vpr 63.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65156 8 4 25 28 5 19 19 6 6 36 clb auto 24.9 MiB 0.49 52 194 34 129 31 63.6 MiB 0.00 0.00 1.3678 -5.84519 -1.3678 0.545 0.00 5.5961e-05 4.3116e-05 0.000686942 0.000559692 -1 -1 -1 -1 94 6.71429 38 2.71429 16 16 1079 432 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.70371 0.545 -7.0897 -1.70371 -0.508975 -0.416549 0.01 -1 -1 63.6 MiB 0.00 0.00293536 0.0026611 63.6 MiB -1 0.01 - k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.04 vpr 18.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 18748 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.68 vpr 66.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67792 8 4 25 28 5 19 19 6 6 36 clb auto 27.9 MiB 0.43 51 194 39 119 36 66.2 MiB 0.00 0.00 1.41795 -5.85435 -1.41795 0.545 0.00 6.5511e-05 4.9348e-05 0.000956967 0.000802791 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 675 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.01 -1 -1 66.2 MiB 0.00 0.00312006 0.00280809 66.2 MiB -1 0.01 + k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.03 vpr 20.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 21424 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt index 4ff0e8b463a..a8229d3cc5f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.50 vpr 62.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64284 -1 2 2 4 0 2 4 4 4 16 clb auto 24.1 MiB 0.01 0 9 0 2 7 62.8 MiB 0.00 0.00 nan 0 0 nan 0.01 1.5871e-05 9.709e-06 0.000102284 7.0143e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.00143641 0.00135809 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00160323 0.00154708 + k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.39 vpr 65.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 -1 2 2 4 0 2 4 4 4 16 clb auto 27.0 MiB 0.00 0 9 0 2 7 65.3 MiB 0.00 0.00 nan 0 0 nan 0.01 1.324e-05 7.342e-06 8.3458e-05 5.501e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.00154065 0.00146112 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00148898 0.00145049 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt index be7b1d7e3c9..dedf8b436ab 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_grid.xml raygentop.v common 33.90 vpr 92.21 MiB 0.48 31696 -1 -1 3 1.32 -1 -1 40548 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 94428 214 305 2963 2869 1 1444 650 25 25 625 -1 25x25 44.0 MiB 3.82 12566 298934 100179 176792 21963 84.9 MiB 2.12 0.03 4.48882 -2692.89 -4.48882 4.48882 2.29 0.00709216 0.00653764 0.858961 0.793235 -1 -1 -1 -1 56 23237 32 3.19446e+07 9.79696e+06 2.27235e+06 3635.76 16.01 3.41745 3.12097 68115 457904 -1 20684 16 5341 11970 1408411 380795 4.73758 4.73758 -2976.98 -4.73758 0 0 2.89946e+06 4639.14 0.78 0.63 0.39 -1 -1 0.78 0.342569 0.318423 - column_io.xml raygentop.v common 38.50 vpr 84.88 MiB 0.44 31584 -1 -1 3 1.32 -1 -1 40468 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86916 214 305 2963 2869 1 1444 650 25 25 625 io auto 44.1 MiB 3.74 11473 259538 92955 142257 24326 84.9 MiB 2.04 0.03 4.47884 -2622.54 -4.47884 4.47884 2.19 0.00782519 0.00725944 0.825246 0.760138 -1 -1 -1 -1 46 25888 44 2.82259e+07 9.79696e+06 1.74878e+06 2798.05 21.24 3.9598 3.60408 57264 344844 -1 20796 16 6055 13443 1912977 469313 4.80041 4.80041 -2970.49 -4.80041 0 0 2.25408e+06 3606.53 0.58 0.69 0.30 -1 -1 0.58 0.341447 0.317119 - multiwidth_blocks.xml raygentop.v common 25.55 vpr 84.75 MiB 0.46 31704 -1 -1 3 1.40 -1 -1 40456 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86780 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 44.0 MiB 3.78 11816 245468 79004 142595 23869 84.7 MiB 1.98 0.03 4.52802 -2725.19 -4.52802 4.52802 0.94 0.00949291 0.00850738 0.847864 0.781876 -1 -1 -1 -1 60 23563 42 1.65001e+07 9.79696e+06 1.13508e+06 3144.28 10.95 3.41073 3.11126 34801 210837 -1 19834 20 6107 14382 2085679 598371 5.05307 5.05307 -2966.13 -5.05307 0 0 1.43369e+06 3971.44 0.44 0.94 0.25 -1 -1 0.44 0.424155 0.39432 - non_column.xml raygentop.v common 47.61 vpr 105.35 MiB 0.62 32012 -1 -1 3 1.48 -1 -1 40516 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 107876 214 305 2963 2869 1 1444 650 33 33 1089 io auto 45.4 MiB 3.85 13747 248282 81945 142793 23544 103.0 MiB 1.76 0.02 4.81737 -2724.33 -4.81737 4.81737 3.97 0.0073023 0.00679977 0.722608 0.667884 -1 -1 -1 -1 44 27797 37 5.44432e+07 9.79696e+06 2.74036e+06 2516.40 25.74 3.75279 3.41577 93774 543488 -1 22309 17 5786 13251 1497600 404581 5.13958 5.13958 -3092.11 -5.13958 0 0 3.56397e+06 3272.70 1.02 0.65 0.61 -1 -1 1.02 0.349553 0.324591 - non_column_tall_aspect_ratio.xml raygentop.v common 49.55 vpr 102.16 MiB 0.66 31936 -1 -1 3 1.40 -1 -1 40480 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 104612 214 305 2963 2869 1 1444 650 23 46 1058 io auto 45.7 MiB 3.89 13776 239840 84223 119240 36377 99.2 MiB 1.69 0.03 4.68258 -2779.01 -4.68258 4.68258 3.29 0.00749757 0.00702299 0.684672 0.633229 -1 -1 -1 -1 42 31648 41 5.05849e+07 9.79696e+06 2.60561e+06 2462.77 28.66 3.51495 3.19945 89863 510592 -1 24152 20 7442 17660 2259951 590976 5.67716 5.67716 -3200.57 -5.67716 0 0 3.28516e+06 3105.07 0.91 0.87 0.58 -1 -1 0.91 0.399372 0.369203 - non_column_wide_aspect_ratio.xml raygentop.v common 41.85 vpr 98.60 MiB 0.69 31936 -1 -1 3 1.59 -1 -1 40616 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 100964 214 305 2963 2869 1 1444 650 43 22 946 io auto 45.4 MiB 3.73 14156 293306 98573 164570 30163 96.1 MiB 2.16 0.02 4.68152 -2812.57 -4.68152 4.68152 3.55 0.00724035 0.00673017 0.925677 0.848397 -1 -1 -1 -1 42 29613 38 4.55909e+07 9.79696e+06 2.29725e+06 2428.38 20.53 3.62206 3.28365 79978 445530 -1 24436 20 8003 18434 2464079 661230 4.86641 4.86641 -3242.4 -4.86641 0 0 2.89121e+06 3056.25 0.80 0.92 0.53 -1 -1 0.80 0.400872 0.370601 - custom_sbloc.xml raygentop.v common 22.72 vpr 84.88 MiB 0.60 31700 -1 -1 3 1.59 -1 -1 40544 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86920 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 44.0 MiB 3.96 11545 253910 83783 147052 23075 84.9 MiB 2.20 0.03 4.53013 -2682.92 -4.53013 4.53013 0.78 0.00994624 0.00941733 0.898398 0.823185 -1 -1 -1 -1 60 22190 29 1.65001e+07 9.79696e+06 1.11685e+06 3093.75 8.02 3.01302 2.74098 34801 214773 -1 19145 15 5739 13180 1453072 396713 4.70711 4.70711 -3011.51 -4.70711 0 0 1.41014e+06 3906.19 0.34 0.44 0.19 -1 -1 0.34 0.223232 0.212144 - multiple_io_types.xml raygentop.v common 134.08 vpr 493.00 MiB 0.37 31604 -1 -1 3 1.38 -1 -1 40464 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 504836 214 305 2963 2869 1 1444 650 67 67 4489 io_left auto 44.2 MiB 4.78 27628 90698 4403 23036 63259 493.0 MiB 0.77 0.02 4.46994 -3778.7 -4.46994 4.46994 30.74 0.00783736 0.0072251 0.300586 0.27767 -1 -1 -1 -1 56 40503 35 2.48753e+08 9.79696e+06 1.37773e+07 3069.12 66.77 3.49776 3.17473 415449 2586128 -1 37151 19 7409 16932 3284490 878151 5.12129 5.12129 -4069.29 -5.12129 0 0 1.75917e+07 3918.84 5.30 1.25 2.49 -1 -1 5.30 0.401056 0.370625 + fixed_grid.xml raygentop.v common 22.04 vpr 87.12 MiB 0.37 32000 -1 -1 3 1.37 -1 -1 43832 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89216 214 305 2963 2869 1 1444 650 25 25 625 -1 25x25 45.9 MiB 3.49 12196 290492 92452 176193 21847 87.1 MiB 1.73 0.04 4.70145 -2687.49 -4.70145 4.70145 0.77 0.009062 0.00821446 0.664489 0.598586 -1 -1 -1 -1 50 24072 42 3.19446e+07 9.79696e+06 2.03477e+06 3255.63 9.38 3.04543 2.74886 65619 409230 -1 20090 15 5518 12429 1427524 369655 4.84691 4.84691 -2936.69 -4.84691 0 0 2.61863e+06 4189.80 0.13 0.72 0.40 -1 -1 0.13 0.405468 0.382168 + column_io.xml raygentop.v common 30.34 vpr 87.28 MiB 0.43 32000 -1 -1 3 1.83 -1 -1 43888 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89376 214 305 2963 2869 1 1444 650 25 25 625 io auto 46.2 MiB 3.96 11325 239840 77339 132443 30058 87.3 MiB 2.09 0.03 4.40936 -2625.55 -4.40936 4.40936 1.20 0.0090281 0.0081843 0.836879 0.749323 -1 -1 -1 -1 48 24462 25 2.82259e+07 9.79696e+06 1.82181e+06 2914.90 14.53 3.9566 3.54503 57888 355703 -1 20518 17 5996 13599 1716937 426068 4.7409 4.7409 -2939.5 -4.7409 0 0 2.33544e+06 3736.71 0.17 0.92 0.52 -1 -1 0.17 0.442866 0.410518 + multiwidth_blocks.xml raygentop.v common 23.34 vpr 87.11 MiB 0.46 32000 -1 -1 3 1.66 -1 -1 43932 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89196 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.9 MiB 4.70 10825 234212 78128 135288 20796 87.1 MiB 2.20 0.03 4.45499 -2656.92 -4.45499 4.45499 0.58 0.00914429 0.00826611 0.84541 0.761865 -1 -1 -1 -1 60 22314 37 1.65001e+07 9.79696e+06 1.13508e+06 3144.28 8.15 3.5171 3.1499 34801 210837 -1 18718 16 6372 15066 2125910 636768 4.83864 4.83864 -2933.88 -4.83864 0 0 1.43369e+06 3971.44 0.09 1.02 0.34 -1 -1 0.09 0.423489 0.392785 + non_column.xml raygentop.v common 50.57 vpr 101.43 MiB 0.57 32128 -1 -1 3 1.64 -1 -1 43688 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103864 214 305 2963 2869 1 1444 650 33 33 1089 io auto 47.6 MiB 3.38 13852 267980 91761 149229 26990 98.5 MiB 2.25 0.03 4.81737 -2748.68 -4.81737 4.81737 2.25 0.00871345 0.00790536 0.883704 0.789723 -1 -1 -1 -1 46 27889 41 5.44432e+07 9.79696e+06 2.87196e+06 2637.24 31.91 4.82411 4.34906 94862 558952 -1 23226 19 7179 17098 2136481 565014 5.00295 5.00295 -3094.61 -5.00295 0 0 3.68462e+06 3383.49 0.29 1.11 0.95 -1 -1 0.29 0.492691 0.457205 + non_column_tall_aspect_ratio.xml raygentop.v common 41.13 vpr 107.46 MiB 0.65 32128 -1 -1 3 2.07 -1 -1 43888 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 110040 214 305 2963 2869 1 1444 650 23 46 1058 io auto 47.5 MiB 4.75 12924 225770 77986 115287 32497 98.0 MiB 1.99 0.02 4.68258 -2746.61 -4.68258 4.68258 2.17 0.00617553 0.00548634 0.751525 0.668955 -1 -1 -1 -1 50 24702 35 5.05849e+07 9.79696e+06 3.07243e+06 2904.00 20.48 4.80846 4.28853 95149 595581 -1 21346 17 5714 12751 1591343 424414 4.99583 4.99583 -3024.29 -4.99583 0 0 3.91054e+06 3696.17 0.39 1.00 1.06 -1 -1 0.39 0.462953 0.424532 + non_column_wide_aspect_ratio.xml raygentop.v common 40.58 vpr 101.39 MiB 0.68 32000 -1 -1 3 1.80 -1 -1 43696 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103820 214 305 2963 2869 1 1444 650 43 22 946 io auto 47.4 MiB 4.77 13982 276422 90498 164087 21837 95.1 MiB 2.48 0.03 4.68152 -2857.71 -4.68152 4.68152 2.06 0.0081203 0.0072676 0.94579 0.847056 -1 -1 -1 -1 50 26296 34 4.55909e+07 9.79696e+06 2.70028e+06 2854.41 19.21 5.11489 4.60481 84704 520009 -1 22872 18 6244 14195 1614167 427447 4.86473 4.86473 -3155.96 -4.86473 0 0 3.44953e+06 3646.44 0.30 1.16 1.00 -1 -1 0.30 0.501153 0.460019 + custom_sbloc.xml raygentop.v common 25.95 vpr 86.98 MiB 0.39 32000 -1 -1 3 1.58 -1 -1 43804 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89072 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.8 MiB 4.86 11696 245468 82823 140883 21762 87.0 MiB 2.50 0.04 4.53013 -2681.39 -4.53013 4.53013 0.61 0.00909806 0.00824441 0.931511 0.836258 -1 -1 -1 -1 62 22622 49 1.65001e+07 9.79696e+06 1.15634e+06 3203.15 10.71 4.10582 3.71488 35161 219597 -1 19429 17 6137 14618 1898349 506769 4.83748 4.83748 -2977.52 -4.83748 0 0 1.43990e+06 3988.64 0.05 0.92 0.41 -1 -1 0.05 0.399467 0.368878 + multiple_io_types.xml raygentop.v common 148.40 vpr 474.05 MiB 0.38 31872 -1 -1 3 1.46 -1 -1 43604 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 485424 214 305 2963 2869 1 1444 650 67 67 4489 io_left auto 46.2 MiB 5.36 26050 90698 4115 22648 63935 474.0 MiB 0.95 0.03 4.73667 -3563.79 -4.73667 4.73667 26.71 0.00792183 0.00702959 0.36772 0.321766 -1 -1 -1 -1 52 41451 45 2.48753e+08 9.79696e+06 1.27607e+07 2842.65 95.91 4.21007 3.80326 406473 2447650 -1 35770 21 7664 17455 3505363 891802 5.27395 5.27395 -3927.86 -5.27395 0 0 1.67786e+07 3737.72 0.99 1.06 2.69 -1 -1 0.99 0.318577 0.29589 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt index 348a34af9ba..032d95a320e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 5.22 vpr 65.48 MiB 0.07 9376 -1 -1 3 0.34 -1 -1 34576 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67052 99 130 363 493 1 251 298 12 12 144 clb auto 26.1 MiB 0.16 830 72933 24114 36385 12434 65.5 MiB 0.26 0.00 2.31523 -217.996 -2.31523 2.31523 0.32 0.00107013 0.00100915 0.0756674 0.0712994 -1 -1 -1 -1 38 1547 11 5.66058e+06 4.21279e+06 328943. 2284.32 2.50 0.428144 0.389705 12522 66188 -1 1392 8 487 648 34594 11334 2.74555 2.74555 -237.815 -2.74555 0 0 418267. 2904.63 0.13 0.05 0.07 -1 -1 0.13 0.0295936 0.0277122 + k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 3.10 vpr 67.66 MiB 0.06 9856 -1 -1 3 0.38 -1 -1 39496 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69284 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.15 804 66963 21682 33533 11748 67.7 MiB 0.23 0.00 2.23767 -220.613 -2.23767 2.23767 0.25 0.00122229 0.00116469 0.0742124 0.0677305 -1 -1 -1 -1 38 1639 12 5.66058e+06 4.21279e+06 328943. 2284.32 0.72 0.298961 0.271262 12522 66188 -1 1359 8 559 726 39339 13482 2.60043 2.60043 -237.265 -2.60043 0 0 418267. 2904.63 0.03 0.05 0.11 -1 -1 0.03 0.0322868 0.0303399 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt index 57ef852f6b8..a65248b7f30 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 4.48 vpr 62.46 MiB 0.06 9372 -1 -1 4 0.34 -1 -1 34600 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63964 99 130 378 508 1 307 305 15 15 225 memory auto 22.6 MiB 0.10 1111 75203 25546 36272 13385 62.5 MiB 0.26 0.00 1.73414 -174.802 -1.73414 1.73414 0.00 0.000976408 0.000916184 0.0779894 0.0732724 -1 -1 -1 -1 1512 6.17143 792 3.23265 713 1663 202968 51102 1.16234e+06 375248 2.18283e+06 9701.45 12 48952 428016 -1 1.89635 1.89635 -187.166 -1.89635 0 0 0.66 -1 -1 62.5 MiB 0.12 0.112709 0.105511 62.5 MiB -1 2.26 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 2.43 vpr 64.82 MiB 0.05 9728 -1 -1 4 0.35 -1 -1 39692 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66380 99 130 378 508 1 307 305 15 15 225 memory auto 25.3 MiB 0.06 1083 69047 24301 32567 12179 64.8 MiB 0.22 0.01 1.63577 -172.755 -1.63577 1.63577 0.00 0.00106212 0.000958102 0.0684136 0.0626923 -1 -1 -1 -1 1479 6.03673 767 3.13061 797 1865 235419 59319 1.16234e+06 375248 2.18283e+06 9701.45 16 48952 428016 -1 1.89463 1.89463 -188.601 -1.89463 -0.194976 -0.108352 0.68 -1 -1 64.8 MiB 0.11 0.107667 0.0986163 64.8 MiB -1 0.37 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt index d18183d9a08..c044fb36631 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 28.10 vpr 85.89 MiB 0.23 16788 -1 -1 2 0.16 -1 -1 33892 -1 -1 31 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 87952 311 156 1019 1160 1 965 513 28 28 784 memory auto 32.2 MiB 0.92 8945 195453 67462 117452 10539 83.1 MiB 1.14 0.02 4.24256 -3535.29 -4.24256 4.24256 3.03 0.0047266 0.00420892 0.495161 0.440444 -1 -1 -1 -1 46 14258 14 4.25198e+07 9.89071e+06 2.42825e+06 3097.26 14.01 2.26688 2.03164 81963 495902 -1 13674 12 2508 2888 1039968 435011 4.40824 4.40824 -4330.54 -4.40824 -371.448 -1.34258 3.12000e+06 3979.60 0.98 1.97 0.43 -1 -1 0.98 0.192689 0.174884 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 28.61 vpr 89.27 MiB 0.19 16912 -1 -1 2 0.16 -1 -1 33728 -1 -1 31 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 91412 311 156 1019 1160 1 965 513 28 28 784 memory auto 32.3 MiB 1.00 8945 195453 67462 117452 10539 83.9 MiB 1.09 0.02 4.24256 -3535.29 -4.24256 4.24256 3.23 0.00439673 0.00387964 0.464219 0.409008 -1 -1 -1 -1 46 14278 13 4.25198e+07 9.89071e+06 2.47848e+06 3161.33 14.05 2.05809 1.83585 81963 509322 -1 13687 11 2477 2842 628309 183554 4.6903 4.6903 -4253.53 -4.6903 -195.104 -1.3767 3.17357e+06 4047.92 1.31 2.14 0.43 -1 -1 1.31 0.196452 0.182983 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 28.86 vpr 86.38 MiB 0.18 16924 -1 -1 2 0.18 -1 -1 33688 -1 -1 31 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 88452 311 156 1019 1160 1 965 513 28 28 784 memory auto 32.4 MiB 0.86 9287 195453 66686 117509 11258 82.3 MiB 1.11 0.02 4.12801 -3603.7 -4.12801 4.12801 2.98 0.00506386 0.00456663 0.488102 0.431794 -1 -1 -1 -1 46 15578 14 4.25198e+07 9.89071e+06 2.42368e+06 3091.42 14.99 2.15465 1.92472 81963 496068 -1 14973 12 2225 2503 1188709 769601 5.70473 5.70473 -4410.99 -5.70473 -1643.75 -3.31884 3.11542e+06 3973.75 0.91 2.07 0.43 -1 -1 0.91 0.187032 0.169642 15 950 + timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 16.11 vpr 77.95 MiB 0.11 17024 -1 -1 2 0.10 -1 -1 37392 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79820 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.7 MiB 0.63 9390 201609 69489 120331 11789 76.8 MiB 1.40 0.02 4.09817 -3462.19 -4.09817 4.09817 1.75 0.00638402 0.00561878 0.639416 0.550497 -1 -1 -1 -1 36 15662 18 4.25198e+07 9.89071e+06 1.97160e+06 2514.80 6.39 2.29245 2.04057 76483 392267 -1 14444 15 3124 3650 1031496 356426 4.24327 4.24327 -4339.34 -4.24327 -405.202 -1.29702 2.42825e+06 3097.26 0.20 1.56 0.59 -1 -1 0.20 0.278119 0.255639 15 950 + timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 12.94 vpr 83.35 MiB 0.18 17024 -1 -1 2 0.12 -1 -1 37644 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 85352 311 156 1019 1160 1 965 513 28 28 784 memory auto 35.0 MiB 0.95 9390 201609 69489 120331 11789 83.4 MiB 0.81 0.01 4.09817 -3462.19 -4.09817 4.09817 1.06 0.00320533 0.00273182 0.351431 0.298654 -1 -1 -1 -1 36 15777 15 4.25198e+07 9.89071e+06 2.00618e+06 2558.90 4.74 1.57738 1.39763 76483 403003 -1 14373 10 2886 3379 762706 219312 4.3954 4.3954 -4595.94 -4.3954 -153.524 -1.32288 2.47848e+06 3161.33 0.22 1.20 0.50 -1 -1 0.22 0.199455 0.182428 15 950 + timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 20.64 vpr 78.23 MiB 0.14 17152 -1 -1 2 0.19 -1 -1 37392 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80112 311 156 1019 1160 1 965 513 28 28 784 memory auto 35.0 MiB 0.82 8956 201609 71778 118284 11547 78.2 MiB 1.41 0.02 3.73942 -3418.22 -3.73942 3.73942 1.71 0.00607733 0.00531502 0.647808 0.554869 -1 -1 -1 -1 36 16279 32 4.25198e+07 9.89071e+06 1.96702e+06 2508.96 9.86 2.33237 2.04039 76483 392433 -1 15198 14 2704 3167 1739681 1219090 5.58949 5.58949 -4496.49 -5.58949 -1697.62 -3.42836 2.42368e+06 3091.42 0.20 2.25 0.55 -1 -1 0.20 0.242641 0.222883 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt index b07d8e1e443..3e3e8b64dd5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 14.06 vpr 69.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70736 64 39 1935 1974 1 1077 541 23 23 529 clb auto 28.9 MiB 0.36 10085 137127 36539 98027 2561 69.1 MiB 1.18 0.02 7.41831 -1418.64 -7.41831 7.41831 0.87 0.00457621 0.0038989 0.327684 0.280049 -1 -1 -1 -1 22 12754 28 983127 976439 735934. 1391.18 7.82 1.0919 0.944895 35322 121345 -1 11109 19 6608 23845 1462488 382373 7.14816 7.14816 -1474.13 -7.14816 0 0 927497. 1753.30 0.17 0.70 0.15 -1 -1 0.17 0.211387 0.189904 + k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 16.94 vpr 71.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73360 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.5 MiB 0.26 10472 141533 36950 100839 3744 71.6 MiB 1.41 0.02 7.46482 -1369.01 -7.46482 7.46482 0.60 0.00534435 0.00471558 0.398834 0.330633 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.25 2.1497 1.834 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.76 0.21 -1 -1 0.04 0.209487 0.18755 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt index 58a35002d9a..57a8e16dad9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 34.24 vpr 86.90 MiB 0.42 29492 -1 -1 4 2.47 -1 -1 38196 -1 -1 169 193 5 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 88984 193 205 2863 2789 1 1374 572 20 20 400 memory auto 43.5 MiB 2.02 11201 252110 92751 131930 27429 84.6 MiB 2.85 0.03 4.45067 -2677.23 -4.45067 4.45067 1.22 0.0117307 0.0109776 1.3522 1.20596 -1 -1 -1 -1 80 22067 39 2.07112e+07 1.18481e+07 2.10510e+06 5262.74 18.77 4.81689 4.2918 53274 447440 -1 19298 16 5571 15462 1144445 252495 4.66289 4.66289 -2899.83 -4.66289 -11.7102 -0.360359 2.64606e+06 6615.15 0.68 0.61 0.38 -1 -1 0.68 0.361937 0.331231 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 26.42 vpr 86.55 MiB 0.39 29568 -1 -1 4 2.92 -1 -1 43300 -1 -1 169 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88632 193 205 2863 2789 1 1374 572 20 20 400 memory auto 45.3 MiB 1.96 10985 240245 81936 130873 27436 86.6 MiB 2.98 0.04 4.42447 -2617.73 -4.42447 4.42447 0.87 0.010731 0.00973575 1.17585 1.01795 -1 -1 -1 -1 78 21148 32 2.07112e+07 1.18481e+07 2.06176e+06 5154.39 12.21 3.92596 3.45972 52874 439520 -1 19015 16 5137 14374 1050969 231484 5.06231 5.06231 -2806.44 -5.06231 -11.1461 -0.341744 2.60035e+06 6500.87 0.19 0.81 0.45 -1 -1 0.19 0.495649 0.459932 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt index 8ee4a9abbe5..7d3c0c996a1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 5.07 vpr 65.37 MiB 0.06 9596 -1 -1 3 0.31 -1 -1 34612 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66936 99 130 363 493 1 251 298 12 12 144 clb auto 26.0 MiB 0.16 830 72933 24114 36385 12434 65.4 MiB 0.28 0.00 2.31523 -217.996 -2.31523 2.31523 0.35 0.00104781 0.000982566 0.0900921 0.0848773 -1 -1 -1 -1 38 1583 13 5.66058e+06 4.21279e+06 319130. 2216.18 2.23 0.432918 0.394254 12522 62564 -1 1389 8 493 651 37667 12430 2.73633 2.73633 -236.043 -2.73633 0 0 406292. 2821.48 0.13 0.05 0.07 -1 -1 0.13 0.0283815 0.0266422 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.83 vpr 67.63 MiB 0.09 9984 -1 -1 3 0.34 -1 -1 39772 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69252 99 130 363 493 1 251 298 12 12 144 clb auto 28.5 MiB 0.20 804 66963 21682 33533 11748 67.6 MiB 0.34 0.01 2.23767 -220.613 -2.23767 2.23767 0.27 0.000902266 0.000807045 0.0650955 0.0583605 -1 -1 -1 -1 38 1665 16 5.66058e+06 4.21279e+06 319130. 2216.18 1.19 0.319458 0.291293 12522 62564 -1 1367 8 564 725 39208 13509 2.60043 2.60043 -237.701 -2.60043 0 0 406292. 2821.48 0.03 0.06 0.09 -1 -1 0.03 0.0273369 0.0256329 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt index f32816621c9..ceb027e03e3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_40nm.xml stereovision0.v common 169.74 vpr 277.27 MiB 2.37 126048 -1 -1 5 83.26 -1 -1 75348 -1 -1 1337 157 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 283924 157 197 21024 21221 1 6369 1691 39 39 1521 clb auto 124.0 MiB 4.94 49118 978481 352716 605570 20195 277.3 MiB 10.50 0.11 3.82872 -14985.1 -3.82872 3.82872 9.61 0.030689 0.0261212 3.24668 2.69757 -1 -1 -1 -1 36 61735 32 2.4642e+07 2.4066e+07 4.11737e+06 2707.01 35.88 15.6221 12.8274 115990 821377 -1 57847 23 29862 63292 2473837 450954 3.66887 3.66887 -15765.9 -3.66887 0 0 5.03985e+06 3313.51 1.56 2.53 0.62 -1 -1 1.56 1.85817 1.5961 - k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 171.11 vpr 275.04 MiB 2.66 126004 -1 -1 5 87.20 -1 -1 75432 -1 -1 1356 157 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 281640 157 197 21024 21221 1 6467 1710 39 39 1521 clb auto 124.0 MiB 5.16 51290 993147 360680 608362 24105 275.0 MiB 10.32 0.11 3.26166 -14917.8 -3.26166 3.26166 9.34 0.0308111 0.0262182 3.21737 2.66176 -1 -1 -1 -1 42 62756 33 7.37824e+07 7.30817e+07 4.49269e+06 2953.77 32.95 14.6319 12.0222 122070 906769 -1 60178 20 29762 65352 2439585 446633 3.2534 3.2534 -15909.6 -3.2534 0 0 5.60675e+06 3686.23 1.70 2.67 0.70 -1 -1 1.70 1.88443 1.62 + k6_N10_40nm.xml stereovision0.v common 198.12 vpr 257.14 MiB 2.00 126464 -1 -1 5 139.65 -1 -1 78708 -1 -1 1337 157 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 263312 157 197 21024 21221 1 6369 1691 39 39 1521 clb auto 124.7 MiB 6.38 48812 948271 327778 599083 21410 257.1 MiB 9.39 0.13 3.8487 -15314.7 -3.8487 3.8487 8.33 0.0426525 0.0388129 3.00817 2.44576 -1 -1 -1 -1 38 60857 30 2.4642e+07 2.4066e+07 4.29790e+06 2825.71 13.17 9.3436 7.78726 119030 883757 -1 57009 24 29792 62484 2448958 439074 3.78459 3.78459 -15886.2 -3.78459 0 0 5.41627e+06 3561.00 0.27 2.25 0.65 -1 -1 0.27 1.68943 1.4738 + k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 201.99 vpr 255.40 MiB 2.14 126336 -1 -1 5 142.90 -1 -1 78972 -1 -1 1356 157 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 261528 157 197 21024 21221 1 6467 1710 39 39 1521 clb auto 124.6 MiB 7.21 49809 962484 334554 607807 20123 255.4 MiB 9.87 0.12 3.26114 -15027.4 -3.26114 3.26114 7.20 0.0351221 0.0281327 3.06287 2.48936 -1 -1 -1 -1 38 63075 34 7.37824e+07 7.30817e+07 4.16760e+06 2740.04 13.41 9.93144 8.27431 119030 845795 -1 59104 24 31762 70331 2621462 488165 3.1068 3.1068 -15929.2 -3.1068 0 0 5.22668e+06 3436.35 0.24 2.20 0.62 -1 -1 0.24 1.62443 1.4202 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt index f19ec3ad52a..53aa221bde0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.41 vpr 58.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59448 3 1 5 6 1 4 5 3 3 9 -1 auto 19.6 MiB 0.00 9 12 4 4 4 58.1 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.4994e-05 1.045e-05 0.000115391 8.7864e-05 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00160683 0.00150489 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.01 0.00 -1 -1 0.00 0.0017143 0.00166299 - k6_frac_N10_40nm.xml conn_order.eblif common 0.37 vpr 58.13 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59528 2 1 4 5 1 3 4 3 3 9 -1 auto 19.7 MiB 0.00 6 9 4 1 4 58.1 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.8474e-05 1.3622e-05 0.000123757 9.6624e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.01 0.00168156 0.00158496 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00150108 0.00146247 + k6_frac_N10_40nm.xml test_eblif.eblif common 0.35 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 3 1 5 6 1 4 5 3 3 9 -1 auto 22.0 MiB 0.00 9 12 4 4 4 60.6 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 6.5921e-05 4.9487e-05 0.000173999 0.000134314 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00172845 0.00161091 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.0015722 0.00153245 + k6_frac_N10_40nm.xml conn_order.eblif common 0.43 vpr 60.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61580 2 1 4 5 1 3 4 3 3 9 -1 auto 21.9 MiB 0.01 6 9 4 1 4 60.1 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.01 1.6713e-05 1.1905e-05 0.000118437 9.2123e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.01 0.00165899 0.00156225 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00153235 0.00149153 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt index cc7ced1ba94..c0c64f8d2c1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml eblif_write.eblif common 0.35 vpr 56.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57852 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 17.8 MiB 0.00 14 18 7 10 1 56.5 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 2.0474e-05 1.286e-05 0.000117644 8.503e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00148217 0.00137435 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00134946 0.00130933 + arch.xml eblif_write.eblif common 0.32 vpr 58.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60388 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 20.5 MiB 0.00 14 18 7 10 1 59.0 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 2.3959e-05 1.5869e-05 0.000131827 9.7152e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00165685 0.00154691 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00177312 0.00171917 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt index 87280012ec8..c750dd52020 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.90 vpr 63.89 MiB 0.07 9972 -1 -1 4 0.20 -1 -1 33336 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65424 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.22 439 1932 239 1639 54 63.9 MiB 0.17 0.00 2.45279 -180.032 -2.45279 2.33029 0.00 0.000657413 0.000584504 0.0150448 0.0136066 -1 -1 -1 -1 -1 515 20 1.07788e+06 1.02399e+06 90369.8 1844.28 0.06 0.0521894 0.0464461 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.53 vpr 66.67 MiB 0.08 10368 -1 -1 4 0.21 -1 -1 36920 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68272 11 30 262 292 2 99 60 7 7 49 clb auto 27.0 MiB 0.11 431 1932 256 1610 66 66.7 MiB 0.10 0.00 2.45279 -183.914 -2.45279 2.30526 0.00 0.000756181 0.000646522 0.0198618 0.0177275 -1 -1 -1 -1 -1 458 24 1.07788e+06 1.02399e+06 90369.8 1844.28 0.07 0.0693622 0.0613246 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt index 516b44c0fea..41d36d5dda6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - equivalent.xml equivalent.blif common 0.38 vpr 56.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57744 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 17.7 MiB 0.00 9 9 4 5 0 56.4 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 1.6528e-05 1.0245e-05 0.000103641 7.0812e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.01 0.00155316 0.00143742 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00496134 0.00490329 + equivalent.xml equivalent.blif common 0.40 vpr 58.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60148 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 20.5 MiB 0.00 9 9 3 6 0 58.7 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 2.1313e-05 1.5936e-05 0.000108787 8.0593e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00168168 0.00158747 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00146867 0.00143048 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt index dd9f37179ee..41bceae31db 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 2.34 vpr 63.85 MiB 0.08 9940 -1 -1 4 0.20 -1 -1 33440 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65384 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.14 439 1932 239 1639 54 63.9 MiB 0.04 0.00 2.45862 -180.487 -2.45862 2.33539 0.09 0.00077729 0.000695808 0.0176391 0.0160225 -1 -1 -1 -1 16 612 29 1.07788e+06 1.02399e+06 88828.2 1812.82 0.37 0.136394 0.116654 2520 24504 -1 539 24 882 1910 71912 23696 2.90651 2.60442 -203.665 -2.90651 0 0 104221. 2126.97 0.02 0.08 0.02 -1 -1 0.02 0.0427223 0.0370258 + k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 2.46 vpr 66.34 MiB 0.09 10240 -1 -1 4 0.25 -1 -1 36836 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67932 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.10 417 1932 303 1579 50 66.3 MiB 0.03 0.00 2.45862 -181.765 -2.45862 2.33618 0.06 0.000452546 0.000389719 0.0170733 0.0149049 -1 -1 -1 -1 14 566 30 1.07788e+06 1.02399e+06 81563.3 1664.56 0.67 0.279658 0.24196 2472 22196 -1 446 21 890 1897 62387 19776 2.78119 2.51931 -191.416 -2.78119 0 0 98201.7 2004.12 0.00 0.07 0.02 -1 -1 0.00 0.0396875 0.0352228 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt index 872db87890a..76744275cd6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fix_clusters_test_arch.xml apex2.blif common 18.65 vpr 72.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 74548 38 3 1916 1919 0 1054 173 7 7 49 clb auto 32.1 MiB 4.34 5783 1135 0 0 1135 72.8 MiB 0.08 0.01 5.07028 -15.1308 -5.07028 nan 0.25 0.0047809 0.00426017 0.0574249 0.0545498 -1 -1 -1 -1 164 7801 37 1.34735e+06 7.11401e+06 957298. 19536.7 11.19 2.64641 2.25522 18546 296938 -1 7371 18 5579 21538 954225 313419 5.58606 nan -16.4292 -5.58606 0 0 1.19720e+06 24432.6 0.16 0.49 0.20 -1 -1 0.16 0.251401 0.227559 + fix_clusters_test_arch.xml apex2.blif common 15.55 vpr 74.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76704 38 3 1916 1919 0 1054 173 7 7 49 clb auto 34.1 MiB 5.08 5783 1135 0 0 1135 74.9 MiB 0.08 0.01 5.08129 -15.1527 -5.08129 nan 0.20 0.00521387 0.00456397 0.054855 0.0516446 -1 -1 -1 -1 164 7880 41 1.34735e+06 7.11401e+06 957298. 19536.7 8.09 2.3336 2.00198 18546 296938 -1 7311 19 6308 26453 1146687 361661 5.58525 nan -16.6102 -5.58525 0 0 1.19720e+06 24432.6 0.03 0.49 0.23 -1 -1 0.03 0.228213 0.208678 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt index b572ada2e35..2735c09358a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.74 vpr 64.04 MiB 0.08 10112 -1 -1 4 0.22 -1 -1 33448 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65572 11 30 262 292 2 99 60 7 7 49 clb auto 24.9 MiB 0.12 500 1815 77 1659 79 64.0 MiB 0.04 0.00 2.45489 -182.961 -2.45489 2.31533 0.07 0.000651787 0.000580678 0.0147164 0.0132877 -1 -1 -1 -1 20 654 22 1.07788e+06 1.02399e+06 49980.0 1020.00 0.81 0.247093 0.207481 2664 9102 -1 555 29 713 1765 48495 15174 2.71208 2.45165 -189.124 -2.71208 0 0 65453.8 1335.79 0.01 0.10 0.01 -1 -1 0.01 0.046742 0.040451 + k6_N10_mem32K_40nm.xml stereovision3.v common 2.00 vpr 66.73 MiB 0.06 10368 -1 -1 4 0.21 -1 -1 36456 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68336 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.07 499 1698 69 1565 64 66.7 MiB 0.04 0.00 2.45489 -182.908 -2.45489 2.31533 0.06 0.000803566 0.000668095 0.0165762 0.0143795 -1 -1 -1 -1 18 719 39 1.07788e+06 1.02399e+06 45686.6 932.380 0.43 0.155736 0.134195 2616 8308 -1 605 32 901 2129 57619 17801 2.65666 2.40393 -192.483 -2.65666 0 0 59124.6 1206.62 0.00 0.09 0.01 -1 -1 0.00 0.062047 0.0552258 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt index fe1762c812f..03193b42990 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - shorted_flyover_wires.xml raygentop.v common 28.11 vpr 85.11 MiB 0.48 31828 -1 -1 3 1.48 -1 -1 40620 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 87156 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 44.1 MiB 3.89 11650 228584 75365 133281 19938 85.1 MiB 1.70 0.02 4.52591 -2650.49 -4.52591 4.52591 0.90 0.00694747 0.00642845 0.678406 0.627386 -1 -1 -1 -1 62 24826 45 1.65001e+07 9.79696e+06 1.07728e+06 2984.15 12.61 3.53011 3.21334 35161 217957 -1 20696 17 6141 14924 1916680 524150 5.05166 5.05166 -3006.03 -5.05166 0 0 1.33769e+06 3705.50 0.54 1.08 0.21 -1 -1 0.54 0.444555 0.407313 - buffered_flyover_wires.xml raygentop.v common 28.01 vpr 84.93 MiB 0.45 31828 -1 -1 3 1.40 -1 -1 40476 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86964 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 44.0 MiB 3.80 11698 253910 84523 146224 23163 84.9 MiB 1.92 0.03 4.66082 -2769.33 -4.66082 4.66082 0.91 0.00707593 0.00652878 0.742599 0.682762 -1 -1 -1 -1 62 26047 33 1.65001e+07 9.79696e+06 1.11546e+06 3089.92 12.71 3.5903 3.26464 35161 215557 -1 20655 16 5970 13512 1728683 469210 4.89641 4.89641 -3008.4 -4.89641 0 0 1.38748e+06 3843.44 0.40 0.76 0.26 -1 -1 0.40 0.354607 0.333482 + shorted_flyover_wires.xml raygentop.v common 26.23 vpr 87.18 MiB 0.37 31744 -1 -1 3 1.50 -1 -1 43564 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89276 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 46.2 MiB 4.36 11021 242654 80011 140532 22111 87.2 MiB 2.29 0.03 4.72515 -2651.47 -4.72515 4.72515 0.68 0.00870927 0.00789125 0.867466 0.775905 -1 -1 -1 -1 58 24978 46 1.65001e+07 9.79696e+06 1.00638e+06 2787.76 11.26 3.56546 3.21933 34441 208101 -1 21032 16 5966 14058 1826516 536884 5.22938 5.22938 -3010.82 -5.22938 0 0 1.28387e+06 3556.43 0.10 1.10 0.34 -1 -1 0.10 0.47794 0.447984 + buffered_flyover_wires.xml raygentop.v common 23.64 vpr 87.26 MiB 0.39 31872 -1 -1 3 1.51 -1 -1 43828 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89352 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.9 MiB 4.72 11369 231398 74152 135293 21953 87.3 MiB 2.16 0.03 4.81413 -2746.12 -4.81413 4.81413 0.60 0.00796315 0.00714187 0.791566 0.711054 -1 -1 -1 -1 64 23029 28 1.65001e+07 9.79696e+06 1.15406e+06 3196.84 8.51 3.3002 2.94744 35881 226057 -1 19740 15 5519 12704 1627954 469106 4.80072 4.80072 -2914.34 -4.80072 0 0 1.44847e+06 4012.38 0.10 0.92 0.36 -1 -1 0.10 0.422967 0.392398 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt index f7b51b17509..b90ac6049e3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - hard_fpu_arch_timing.xml mm3.v common 3.40 vpr 62.06 MiB 0.03 6628 -1 -1 1 0.04 -1 -1 30748 -1 -1 0 193 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63552 193 32 545 422 1 289 227 21 21 441 io auto 22.7 MiB 1.72 3760 44515 18630 25456 429 62.1 MiB 0.25 0.00 2.985 -824.754 -2.985 2.985 0.00 0.00161493 0.00152336 0.121894 0.115535 -1 -1 -1 -1 4680 16.2500 1223 4.24653 405 405 152557 41043 809148 68766.3 979092. 2220.16 4 24050 197379 -1 2.985 2.985 -815.015 -2.985 -21.7856 -0.0851 0.27 -1 -1 62.1 MiB 0.09 0.150499 0.142754 62.1 MiB -1 0.46 + hard_fpu_arch_timing.xml mm3.v common 3.31 vpr 64.39 MiB 0.03 7296 -1 -1 1 0.04 -1 -1 34228 -1 -1 0 193 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 65940 193 32 545 422 1 289 227 21 21 441 io auto 25.0 MiB 1.91 3735 46591 19762 26388 441 64.4 MiB 0.33 0.00 2.985 -824.634 -2.985 2.985 0.00 0.00288823 0.00269357 0.190083 0.178688 -1 -1 -1 -1 4590 15.9375 1212 4.20833 431 431 162323 43530 809148 68766.3 979092. 2220.16 5 24050 197379 -1 2.985 2.985 -813.802 -2.985 -21.7856 -0.0851 0.43 -1 -1 64.4 MiB 0.09 0.239729 0.22641 64.4 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt index 8d04367586b..356e91ccb39 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 5.28 vpr 65.87 MiB 0.06 9504 -1 -1 3 0.30 -1 -1 34508 -1 -1 69 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67448 99 130 363 493 1 251 299 13 13 169 clb auto 26.3 MiB 0.79 804 78221 18305 27577 32339 65.9 MiB 0.15 0.00 30 1517 12 0 0 423577. 2506.37 2.58 + k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 3.01 vpr 67.75 MiB 0.06 9728 -1 -1 3 0.26 -1 -1 39908 -1 -1 69 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69380 99 130 363 493 1 251 299 13 13 169 clb auto 28.2 MiB 0.66 756 79220 19640 31087 28493 67.8 MiB 0.16 0.00 36 1238 7 0 0 481804. 2850.91 0.62 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt index cb598477e98..a8ea9747374 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.50 vpr 64.39 MiB 0.06 9976 -1 -1 4 0.20 -1 -1 33252 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65940 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.08 439 1932 239 1639 54 64.4 MiB 0.03 0.00 2.45279 -180.032 -2.45279 2.33029 0.00 0.000720509 0.000652851 0.0155916 0.0141569 -1 -1 -1 -1 -1 515 20 1.07788e+06 1.02399e+06 90369.8 1844.28 0.13 0.0559681 0.0494905 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.21 vpr 66.19 MiB 0.08 10368 -1 -1 4 0.19 -1 -1 36516 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67780 11 30 262 292 2 99 60 7 7 49 clb auto 27.2 MiB 0.09 431 1932 256 1610 66 66.2 MiB 0.04 0.00 2.45279 -183.914 -2.45279 2.30526 0.00 0.000582727 0.000489391 0.0185537 0.0162573 -1 -1 -1 -1 -1 458 24 1.07788e+06 1.02399e+06 90369.8 1844.28 0.07 0.0660847 0.0581726 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt index fd632535e93..265af1c4b6f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.47 vpr 58.11 MiB -1 -1 -1 -1 0 0.02 -1 -1 30028 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59500 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.3 MiB 0.00 0 3 0 0 3 58.1 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1407e-05 6.644e-06 7.1183e-05 4.7157e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00151053 0.00144317 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.49 vpr 58.14 MiB -1 -1 -1 -1 0 0.02 -1 -1 30172 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59532 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.4 MiB 0.00 0 3 0 0 3 58.1 MiB 0.01 0.00 nan 0 0 nan 0.00 1.7072e-05 9.987e-06 0.000106416 7.4745e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00149324 0.00140851 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.53 vpr 58.27 MiB -1 -1 -1 -1 0 0.02 -1 -1 29980 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59668 6 1 1 8 0 1 8 3 3 9 -1 auto 19.9 MiB 0.01 0 21 0 10 11 58.3 MiB 0.01 0.00 nan 0 0 nan 0.00 1.3008e-05 7.386e-06 8.9652e-05 6.0451e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00174003 0.00165512 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.53 vpr 58.11 MiB -1 -1 -1 -1 0 0.02 -1 -1 29992 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59500 6 1 1 8 0 1 8 3 3 9 -1 auto 19.7 MiB 0.01 0 21 0 10 11 58.1 MiB 0.00 0.00 nan 0 0 nan 0.00 1.5792e-05 1.0252e-05 0.000103309 7.4098e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00156505 0.001486 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and.blif common 0.56 vpr 57.91 MiB -1 -1 -1 -1 1 0.02 -1 -1 30068 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59300 2 1 3 4 0 3 4 3 3 9 -1 auto 19.5 MiB 0.00 9 9 3 3 3 57.9 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.5498e-05 1.9252e-05 0.000160935 0.000125409 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.01 0.00168391 0.00159252 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.62 vpr 58.08 MiB -1 -1 -1 -1 1 0.06 -1 -1 31736 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59476 5 1 6 7 0 6 7 3 3 9 -1 auto 19.6 MiB 0.01 18 18 13 5 0 58.1 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.2311e-05 1.6717e-05 0.000157551 0.000125745 -1 -1 -1 -1 -1 7 11 53894 53894 38783.3 4309.26 0.01 0.00219389 0.00197302 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.66 vpr 58.25 MiB -1 -1 -1 -1 1 0.05 -1 -1 31952 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59648 5 1 6 7 0 6 7 3 3 9 -1 auto 19.8 MiB 0.01 18 18 13 5 0 58.2 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.9477e-05 1.46e-05 0.000163199 0.000132585 -1 -1 -1 -1 -1 7 11 53894 53894 38783.3 4309.26 0.01 0.00211569 0.00193 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and_latch.blif common 0.41 vpr 58.29 MiB -1 -1 -1 -1 1 0.03 -1 -1 29892 -1 -1 1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59684 3 1 5 6 1 4 5 3 3 9 -1 auto 19.9 MiB 0.00 9 12 7 1 4 58.3 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.9413e-05 1.4525e-05 0.000151541 0.000121539 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00156423 0.0014768 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml false_path_mux.blif common 0.56 vpr 58.16 MiB -1 -1 -1 -1 1 0.05 -1 -1 31904 -1 -1 1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59556 4 1 4 6 0 4 6 3 3 9 -1 auto 19.8 MiB 0.00 12 15 9 3 3 58.2 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.6085e-05 1.1811e-05 0.000113992 8.8678e-05 -1 -1 -1 -1 -1 6 11 53894 53894 38783.3 4309.26 0.00 0.00203847 0.00189567 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_2x2.blif common 0.61 vpr 58.12 MiB -1 -1 -1 -1 1 0.05 -1 -1 31660 -1 -1 1 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59512 4 4 8 12 0 8 9 3 3 9 -1 auto 19.7 MiB 0.04 24 27 18 6 3 58.1 MiB 0.01 0.00 0.67231 -2.68924 -0.67231 nan 0.00 4.7416e-05 3.8601e-05 0.000343952 0.00030105 -1 -1 -1 -1 -1 10 9 53894 53894 38783.3 4309.26 0.00 0.00246093 0.00226122 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x3.blif common 0.62 vpr 58.05 MiB -1 -1 -1 -1 1 0.06 -1 -1 32468 -1 -1 1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59440 6 6 12 18 0 12 13 3 3 9 -1 auto 19.3 MiB 0.01 36 43 32 7 4 58.0 MiB 0.02 0.00 0.69831 -4.13786 -0.69831 nan 0.00 4.0028e-05 3.3256e-05 0.000373397 0.000331328 -1 -1 -1 -1 -1 17 11 53894 53894 38783.3 4309.26 0.02 0.00325081 0.00295479 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x4.blif common 0.68 vpr 58.19 MiB -1 -1 -1 -1 2 0.06 -1 -1 32136 -1 -1 3 7 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59588 7 8 22 30 0 15 18 4 4 16 clb auto 19.3 MiB 0.01 55 64 20 42 2 58.2 MiB 0.01 0.00 1.29035 -7.83841 -1.29035 nan 0.00 9.5936e-05 8.43e-05 0.000897006 0.000832614 -1 -1 -1 -1 -1 46 5 215576 161682 99039.1 6189.95 0.01 0.00479868 0.00447043 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_4x4.blif common 0.69 vpr 58.24 MiB -1 -1 -1 -1 4 0.07 -1 -1 32308 -1 -1 2 8 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59640 8 8 29 37 0 21 18 4 4 16 clb auto 19.3 MiB 0.02 76 64 16 48 0 58.2 MiB 0.03 0.01 2.08631 -12.2832 -2.08631 nan 0.00 0.000311196 0.000286678 0.00152412 0.00143184 -1 -1 -1 -1 -1 58 14 215576 107788 99039.1 6189.95 0.03 0.00857602 0.00778066 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x5.blif common 0.76 vpr 58.57 MiB -1 -1 -1 -1 4 0.10 -1 -1 32724 -1 -1 4 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59976 10 10 47 57 0 39 24 4 4 16 clb auto 19.3 MiB 0.03 146 364 62 302 0 58.6 MiB 0.01 0.00 2.72561 -18.4747 -2.72561 nan 0.00 0.000163521 0.000149451 0.00302228 0.00280654 -1 -1 -1 -1 -1 114 16 215576 215576 99039.1 6189.95 0.06 0.012168 0.0109894 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x6.blif common 0.88 vpr 58.62 MiB -1 -1 -1 -1 5 0.12 -1 -1 33096 -1 -1 5 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60032 11 11 61 72 0 51 27 5 5 25 clb auto 19.4 MiB 0.04 211 227 56 171 0 58.6 MiB 0.02 0.00 3.36952 -22.7724 -3.36952 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2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 3 2 5 7 0 5 6 3 3 9 -1 auto 22.0 MiB 0.00 15 15 9 5 1 60.5 MiB 0.00 0.00 0.67231 -1.34462 -0.67231 nan 0.00 3.2064e-05 2.4155e-05 0.000200579 0.000160863 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00242941 0.00220554 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_2bit.blif common 0.46 vpr 60.28 MiB -1 -1 -1 -1 1 0.06 -1 -1 35352 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61728 5 3 8 11 0 8 9 3 3 9 -1 auto 21.9 MiB 0.00 24 27 21 6 0 60.3 MiB 0.00 0.00 0.67231 -2.01693 -0.67231 nan 0.00 3.5791e-05 2.5977e-05 0.000240831 0.000201092 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00270512 0.00243979 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_3bit.blif common 0.52 vpr 60.61 MiB -1 -1 -1 -1 2 0.06 -1 -1 35400 -1 -1 1 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62060 7 4 12 16 0 11 12 3 3 9 -1 auto 22.3 MiB 0.01 33 38 24 11 3 60.6 MiB 0.00 0.00 1.08437 -4.00246 -1.08437 nan 0.00 4.7612e-05 3.9433e-05 0.000326091 0.000287024 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00528941 0.00513278 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_4bit.blif common 0.64 vpr 60.55 MiB -1 -1 -1 -1 2 0.07 -1 -1 35520 -1 -1 1 9 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62008 9 5 15 20 0 14 15 3 3 9 -1 auto 22.2 MiB 0.01 42 51 29 17 5 60.6 MiB 0.00 0.00 1.00731 -4.36655 -1.00731 nan 0.00 8.1588e-05 7.0424e-05 0.000516653 0.000461489 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.01 0.00432254 0.00385687 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_5bit.blif common 0.56 vpr 60.67 MiB -1 -1 -1 -1 3 0.07 -1 -1 35440 -1 -1 1 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62124 11 6 19 25 0 17 18 3 3 9 -1 auto 22.1 MiB 0.01 51 64 33 24 7 60.7 MiB 0.00 0.00 1.34231 -6.71386 -1.34231 nan 0.00 5.6728e-05 4.4391e-05 0.000433977 0.000387108 -1 -1 -1 -1 -1 25 11 53894 53894 38783.3 4309.26 0.00 0.00412344 0.0036326 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt index 853ef78bd3a..33183dc0a9f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.29 vpr 58.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59448 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.6 MiB 0.00 0 3 0 0 3 58.1 MiB 0.00 0.00 nan 0 0 nan 0.00 1.35e-05 7.476e-06 9.9741e-05 6.9647e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00158 0.00150277 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.31 vpr 58.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59404 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.3 MiB 0.00 0 3 0 0 3 58.0 MiB 0.00 0.00 nan 0 0 nan 0.00 1.9235e-05 1.1306e-05 9.7577e-05 6.3163e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00153532 0.00145564 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.30 vpr 58.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59472 6 1 7 8 0 7 8 3 3 9 -1 auto 19.6 MiB 0.00 21 21 14 7 0 58.1 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.8514e-05 2.102e-05 0.000170414 0.00013803 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00176222 0.00167853 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.28 vpr 58.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59628 6 1 7 8 0 7 8 3 3 9 -1 auto 19.8 MiB 0.00 21 21 14 7 0 58.2 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.2171e-05 1.4899e-05 0.000148119 0.000118181 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00158746 0.00149915 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.35 vpr 58.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59444 5 1 6 7 0 6 7 3 3 9 -1 auto 19.6 MiB 0.00 18 18 13 5 0 58.1 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.235e-05 1.6891e-05 0.00016969 0.000139695 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.001707 0.00162633 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.36 vpr 57.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59328 5 1 6 7 0 6 7 3 3 9 -1 auto 19.5 MiB 0.00 18 18 13 5 0 57.9 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.3308e-05 1.8079e-05 0.000169741 0.000137603 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00174494 0.0016591 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml const_true.blif common 0.33 vpr 60.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62024 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.3 MiB 0.00 0 3 0 0 3 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.3821e-05 7.858e-06 8.9635e-05 6.0426e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00127569 0.00120513 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml const_false.blif common 0.27 vpr 60.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61760 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.0 MiB 0.00 0 3 0 0 3 60.3 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2203e-05 6.662e-06 7.9048e-05 5.258e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00167909 0.00160437 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml always_true.blif common 0.30 vpr 60.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61712 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.3 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 3.2696e-05 2.3426e-05 0.000197822 0.000159059 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.0018336 0.0017293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml always_false.blif common 0.27 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 6 1 7 8 0 7 8 3 3 9 -1 auto 22.3 MiB 0.00 21 21 14 7 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.7376e-05 1.9376e-05 0.000172772 0.000138442 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00173443 0.0016423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.26 vpr 60.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61804 5 1 6 7 0 6 7 3 3 9 -1 auto 22.1 MiB 0.00 18 18 13 5 0 60.4 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.1966e-05 1.6158e-05 0.000132177 0.000102284 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00191949 0.00184253 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.34 vpr 60.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62040 5 1 6 7 0 6 7 3 3 9 -1 auto 22.1 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.5373e-05 1.8911e-05 0.000175189 0.000138808 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00175813 0.00166803 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt index 34014839d66..eaf5555874c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - x_gaussian_y_uniform.xml stereovision3.v common 1.80 vpr 64.59 MiB 0.05 9920 -1 -1 4 0.20 -1 -1 33316 -1 -1 13 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66140 11 30 262 292 2 110 54 7 7 49 clb auto 25.5 MiB 0.13 437 1482 306 1120 56 64.6 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000643567 0.000574681 0.0143423 0.0131271 -1 -1 -1 -1 12 342 4 1.07788e+06 700622 -1 -1 0.19 0.089611 0.0789696 2680 3516 -1 329 3 168 254 12149 6156 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0184131 0.0175473 - x_uniform_y_gaussian.xml stereovision3.v common 1.90 vpr 64.60 MiB 0.07 10112 -1 -1 4 0.20 -1 -1 33352 -1 -1 13 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66152 11 30 262 292 2 110 54 7 7 49 clb auto 25.5 MiB 0.13 407 2196 418 1692 86 64.6 MiB 0.04 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000658043 0.000585568 0.0188587 0.0171531 -1 -1 -1 -1 12 297 4 1.07788e+06 700622 -1 -1 0.25 0.0992671 0.0872902 2680 3516 -1 290 2 161 238 9382 4536 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0180057 0.0172294 - x_gaussian_y_gaussian.xml stereovision3.v common 2.15 vpr 64.69 MiB 0.06 9984 -1 -1 4 0.20 -1 -1 33348 -1 -1 13 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66244 11 30 262 292 2 110 54 7 7 49 clb auto 25.6 MiB 0.13 454 1584 320 1205 59 64.7 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000634493 0.000563945 0.0146242 0.0133184 -1 -1 -1 -1 14 366 11 1.07788e+06 700622 -1 -1 0.52 0.179464 0.155257 2680 3516 -1 348 15 235 399 18124 8998 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.06 0.00 -1 -1 0.00 0.0336258 0.0306404 - x_delta_y_uniform.xml stereovision3.v common 2.15 vpr 65.34 MiB 0.06 10036 -1 -1 4 0.19 -1 -1 33492 -1 -1 13 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66908 11 30 262 292 2 110 54 7 7 49 clb auto 25.5 MiB 0.13 447 1584 304 1234 46 65.3 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.00060675 0.000538932 0.0145363 0.0132998 -1 -1 -1 -1 58 343 10 1.07788e+06 700622 -1 -1 0.55 0.240804 0.206885 2680 3516 -1 344 2 158 235 10766 5342 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.017128 0.0164094 - x_delta_y_delta.xml stereovision3.v common 2.08 vpr 64.78 MiB 0.07 10108 -1 -1 4 0.21 -1 -1 33260 -1 -1 13 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66336 11 30 262 292 2 110 54 7 7 49 clb auto 25.6 MiB 0.12 507 2196 485 1634 77 64.8 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000513893 0.000456075 0.0159956 0.0145097 -1 -1 -1 -1 54 397 16 1.07788e+06 700622 -1 -1 0.50 0.221994 0.188707 2680 3516 -1 391 16 432 703 33205 16363 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.06 0.00 -1 -1 0.00 0.0309187 0.0279413 - x_uniform_y_delta.xml stereovision3.v common 2.38 vpr 65.23 MiB 0.06 9988 -1 -1 4 0.20 -1 -1 33480 -1 -1 13 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66796 11 30 262 292 2 110 54 7 7 49 clb auto 25.5 MiB 0.11 434 2604 541 1982 81 65.2 MiB 0.04 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000790777 0.00071626 0.0195938 0.0177623 -1 -1 -1 -1 34 315 15 1.07788e+06 700622 -1 -1 0.64 0.293892 0.25135 2680 3516 -1 312 15 303 587 23249 9988 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.11 0.01 -1 -1 0.01 0.0358566 0.0326766 + x_gaussian_y_uniform.xml stereovision3.v common 1.83 vpr 66.90 MiB 0.07 10496 -1 -1 4 0.18 -1 -1 36452 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68504 11 30 262 292 2 110 54 7 7 49 clb auto 28.0 MiB 0.20 415 2196 413 1711 72 66.9 MiB 0.04 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.0007561 0.000646489 0.0218848 0.0192021 -1 -1 -1 -1 12 302 11 1.07788e+06 700622 -1 -1 0.20 0.128028 0.113742 2680 3516 -1 297 3 164 241 11232 5767 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0191965 0.0182163 + x_uniform_y_gaussian.xml stereovision3.v common 1.88 vpr 67.18 MiB 0.07 10624 -1 -1 4 0.21 -1 -1 36664 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68792 11 30 262 292 2 110 54 7 7 49 clb auto 28.1 MiB 0.13 404 2298 458 1774 66 67.2 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.00 0.000687045 0.000583062 0.0174363 0.0155371 -1 -1 -1 -1 12 308 8 1.07788e+06 700622 -1 -1 0.31 0.110517 0.0976349 2680 3516 -1 297 3 168 247 11340 5786 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0178597 0.0169935 + x_gaussian_y_gaussian.xml stereovision3.v common 1.87 vpr 66.84 MiB 0.06 10496 -1 -1 4 0.16 -1 -1 36536 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68444 11 30 262 292 2 110 54 7 7 49 clb auto 27.9 MiB 0.18 410 2298 443 1773 82 66.8 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000756768 0.000647761 0.0255781 0.0225686 -1 -1 -1 -1 14 303 4 1.07788e+06 700622 -1 -1 0.40 0.162052 0.141633 2680 3516 -1 295 3 165 244 11438 5780 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0211596 0.0200797 + x_delta_y_uniform.xml stereovision3.v common 1.95 vpr 67.15 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36504 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68764 11 30 262 292 2 110 54 7 7 49 clb auto 28.2 MiB 0.14 450 3012 620 2301 91 67.2 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000754694 0.000686961 0.028 0.0247412 -1 -1 -1 -1 48 342 3 1.07788e+06 700622 -1 -1 0.49 0.268135 0.232895 2680 3516 -1 342 3 170 251 11060 5468 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0196307 0.0186303 + x_delta_y_delta.xml stereovision3.v common 2.11 vpr 67.59 MiB 0.07 10496 -1 -1 4 0.22 -1 -1 36664 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69212 11 30 262 292 2 110 54 7 7 49 clb auto 28.0 MiB 0.13 519 3012 615 2292 105 67.6 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000782235 0.000651544 0.0273675 0.0237579 -1 -1 -1 -1 54 442 17 1.07788e+06 700622 -1 -1 0.52 0.268766 0.234157 2680 3516 -1 431 4 215 308 16404 8615 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.04 0.01 -1 -1 0.00 0.0214181 0.0202532 + x_uniform_y_delta.xml stereovision3.v common 2.05 vpr 67.14 MiB 0.07 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68756 11 30 262 292 2 110 54 7 7 49 clb auto 28.2 MiB 0.15 435 2502 457 1952 93 67.1 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000965335 0.000843275 0.027473 0.0239971 -1 -1 -1 -1 34 323 16 1.07788e+06 700622 -1 -1 0.51 0.30529 0.26214 2680 3516 -1 317 16 376 682 28098 12512 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.06 0.01 -1 -1 0.00 0.0352499 0.0319547 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt index 45783bae7b7..a4fce4cf22f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.81 vpr 63.86 MiB 0.06 9972 -1 -1 4 0.20 -1 -1 33444 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65396 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.09 425 2049 385 1607 57 63.9 MiB 0.03 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000539136 0.000477079 0.0137959 0.0125271 -1 -1 -1 -1 8 277 16 1.07788e+06 1.02399e+06 -1 -1 0.23 0.0995243 0.0866078 2100 3116 -1 273 21 567 1118 57694 28121 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.08 0.00 -1 -1 0.00 0.0377719 0.0335488 - nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.77 vpr 64.53 MiB 0.07 9928 -1 -1 4 0.20 -1 -1 33420 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66080 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.08 437 1698 295 1347 56 64.5 MiB 0.03 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000564734 0.000501615 0.0121215 0.0110071 -1 -1 -1 -1 12 311 21 1.07788e+06 1.02399e+06 -1 -1 0.20 0.103275 0.0897267 2100 3116 -1 280 16 541 967 52659 26082 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.07 0.00 -1 -1 0.00 0.0337495 0.0305254 - nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.73 vpr 64.50 MiB 0.07 9852 -1 -1 4 0.19 -1 -1 33472 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66048 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 458 2049 322 1664 63 64.5 MiB 0.04 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.00067398 0.000608186 0.0192321 0.0176286 -1 -1 -1 -1 14 304 18 1.07788e+06 1.02399e+06 -1 -1 0.18 0.09714 0.0842011 2100 3116 -1 308 19 560 1062 59748 29836 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.06 0.00 -1 -1 0.00 0.0318622 0.028394 + timing/k6_N10_mem32K_40nm.xml stereovision3.v common 2.02 vpr 67.00 MiB 0.08 10496 -1 -1 4 0.20 -1 -1 36452 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68608 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.11 419 1815 318 1436 61 67.0 MiB 0.04 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000706488 0.000606458 0.0228093 0.0209659 -1 -1 -1 -1 8 283 18 1.07788e+06 1.02399e+06 -1 -1 0.38 0.186498 0.171178 2100 3116 -1 280 18 572 1139 59841 29637 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.07 0.00 -1 -1 0.00 0.0346595 0.0310733 + nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 2.04 vpr 66.32 MiB 0.07 10496 -1 -1 4 0.26 -1 -1 36580 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67916 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 428 1698 248 1401 49 66.3 MiB 0.04 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000764131 0.000648712 0.0183265 0.0161998 -1 -1 -1 -1 10 297 21 1.07788e+06 1.02399e+06 -1 -1 0.45 0.176554 0.15406 2100 3116 -1 286 18 539 1058 53794 27022 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.08 0.00 -1 -1 0.00 0.0402826 0.0356284 + nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.99 vpr 66.21 MiB 0.09 10368 -1 -1 4 0.24 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67800 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.09 447 1815 292 1481 42 66.2 MiB 0.07 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.00090328 0.000782565 0.0181809 0.0161296 -1 -1 -1 -1 16 296 17 1.07788e+06 1.02399e+06 -1 -1 0.25 0.115099 0.100427 2100 3116 -1 300 17 545 1102 57605 27890 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.12 0.01 -1 -1 0.00 0.0397962 0.0356125 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt index 0367bfe7230..e6884fa004e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 5.37 vpr 63.99 MiB 0.10 9968 -1 -1 4 0.20 -1 -1 33400 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65528 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 421 2049 269 1715 65 64.0 MiB 1.89 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 0.00057386 0.000512781 0.0146636 0.0132498 -1 -1 -1 -1 -1 424 16 1.07788e+06 1.02399e+06 207176. 4228.08 1.13 0.0484194 0.0434429 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 6.17 vpr 66.89 MiB 0.08 10368 -1 -1 4 0.22 -1 -1 36612 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68492 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.11 425 2283 406 1804 73 66.9 MiB 2.36 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.00076202 0.000633481 0.0213386 0.0169977 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 1.35 0.0886305 0.079884 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt index acbedece480..b4a9052cd04 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml stereovision3.v common 1.99 vpr 60.15 MiB 0.06 9668 -1 -1 4 0.17 -1 -1 33476 -1 -1 13 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61592 11 30 262 292 2 110 54 6 6 36 clb auto 20.4 MiB 0.13 423 4182 3462 630 90 60.1 MiB 0.08 0.00 2.57043 -171.237 -2.57043 2.32238 0.05 0.00089131 0.000815522 0.0388204 0.0350413 -1 -1 -1 -1 32 775 32 862304 700622 60095.3 1669.31 0.30 0.160018 0.138863 2828 10782 -1 624 11 377 562 17524 7204 2.60136 2.32286 -183.634 -2.60136 0 0 72928.5 2025.79 0.01 0.04 0.01 -1 -1 0.01 0.0300283 0.0274063 + k6_frac_N10_40nm.xml stereovision3.v common 2.01 vpr 61.71 MiB 0.06 10112 -1 -1 4 0.22 -1 -1 36708 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63196 11 30 262 292 2 110 54 6 6 36 clb auto 22.9 MiB 0.13 442 4182 3410 664 108 61.7 MiB 0.07 0.00 2.55648 -171.707 -2.55648 2.31607 0.04 0.000697499 0.000590032 0.035108 0.0301305 -1 -1 -1 -1 36 688 16 862304 700622 64877.6 1802.15 0.32 0.199199 0.171554 2900 12076 -1 568 12 312 493 15436 6065 2.62572 2.28031 -177.78 -2.62572 0 0 80896.3 2247.12 0.00 0.04 0.02 -1 -1 0.00 0.0300653 0.0274931 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt index ce0ea8dc839..8d2903c2d48 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm.xml diffeq.blif common 14.82 vpr 69.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70652 64 39 1935 1974 1 1077 541 23 23 529 clb auto 28.8 MiB 0.46 10085 137127 36539 98027 2561 69.0 MiB 1.29 0.02 7.41831 -1418.64 -7.41831 7.41831 0.93 0.00542256 0.0043447 0.391364 0.336096 -1 -1 -1 -1 22 12754 28 983127 976439 735934. 1391.18 8.01 1.19718 1.03739 35322 121345 -1 11109 19 6608 23845 1462488 382373 7.14816 7.14816 -1474.13 -7.14816 0 0 927497. 1753.30 0.20 0.73 0.16 -1 -1 0.20 0.232845 0.209152 - k4_N4_90nm.xml ex5p.blif common 30.39 vpr 64.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66072 8 63 1072 1135 0 894 437 22 22 484 clb auto 25.1 MiB 0.32 11802 104828 31007 71723 2098 64.5 MiB 0.99 0.02 6.54351 -290.193 -6.54351 nan 0.80 0.00510866 0.00465601 0.247547 0.215944 -1 -1 -1 -1 34 15886 35 891726 815929 1.00654e+06 2079.64 24.52 1.13626 0.978644 45600 169672 -1 13479 18 7616 26985 2968727 818222 6.43932 nan -293.77 -6.43932 0 0 1.27783e+06 2640.15 0.20 0.82 0.22 -1 -1 0.20 0.123294 0.109373 - k4_N4_90nm.xml s298.blif common 53.24 vpr 70.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 72636 4 6 1942 1948 1 1169 590 27 27 729 clb auto 30.8 MiB 0.42 13579 163808 47993 114862 953 70.9 MiB 1.53 0.02 12.0403 -94.3066 -12.0403 12.0403 1.25 0.00553281 0.00453291 0.434948 0.364606 -1 -1 -1 -1 24 19358 45 1.39333e+06 1.29301e+06 1.12265e+06 1539.99 44.05 2.01627 1.70098 54650 192211 -1 16862 23 9147 49878 4855038 894292 11.751 11.751 -96.5615 -11.751 0 0 1.47093e+06 2017.74 0.26 1.56 0.23 -1 -1 0.26 0.263955 0.229636 + k4_N4_90nm.xml diffeq.blif common 18.17 vpr 71.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72740 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.4 MiB 0.53 10472 141533 36950 100839 3744 71.0 MiB 1.46 0.02 7.46482 -1369.01 -7.46482 7.46482 0.64 0.00605549 0.00528423 0.429203 0.364085 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.91 2.29628 1.96589 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.03 0.83 0.15 -1 -1 0.03 0.252853 0.225541 + k4_N4_90nm.xml ex5p.blif common 20.35 vpr 67.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68624 8 63 1072 1135 0 894 437 22 22 484 clb auto 27.6 MiB 0.32 12004 99857 28319 69545 1993 67.0 MiB 1.07 0.02 6.86459 -313.968 -6.86459 nan 0.52 0.0035933 0.00315668 0.2475 0.211473 -1 -1 -1 -1 32 16530 34 891726 815929 949946. 1962.70 14.36 0.89434 0.759948 43920 162796 -1 14048 22 8455 31174 3329435 847924 6.8764 nan -316.234 -6.8764 0 0 1.22393e+06 2528.78 0.08 1.43 0.30 -1 -1 0.08 0.237816 0.212077 + k4_N4_90nm.xml s298.blif common 19.44 vpr 73.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74984 4 6 1942 1948 1 1169 590 27 27 729 clb auto 33.0 MiB 0.49 13813 156389 45768 109723 898 73.2 MiB 1.80 0.03 12.2682 -96.384 -12.2682 12.2682 0.93 0.0106993 0.00945176 0.491739 0.389383 -1 -1 -1 -1 26 17490 32 1.39333e+06 1.29301e+06 1.22387e+06 1678.84 10.93 1.63745 1.34189 57250 204657 -1 16420 17 8603 42614 3232268 684840 12.0598 12.0598 -95.4975 -12.0598 0 0 1.55812e+06 2137.34 0.10 1.48 0.31 -1 -1 0.10 0.297955 0.263351 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt index 7b4d40ad61c..4db936a1dd3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.89 vpr 67.16 MiB 0.08 10336 -1 -1 5 0.21 -1 -1 33252 -1 -1 14 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68768 11 30 313 321 2 114 55 7 7 49 clb auto 27.4 MiB 0.33 439 1511 357 1028 126 67.2 MiB 0.07 0.00 4.62621 0 0 4.30823 0.00 0.00078995 0.00071828 0.0210334 0.0197012 -1 -1 -1 -1 639 5.91667 232 2.14815 379 726 16470 4839 1.07788e+06 754516 219490. 4479.39 10 5100 32136 -1 4.76665 4.41703 0 0 -164.948 -1.707 0.04 -1 -1 67.2 MiB 0.16 0.162181 0.155936 67.2 MiB -1 0.05 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.78 vpr 69.28 MiB 0.09 10496 -1 -1 5 0.19 -1 -1 36448 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70944 11 30 313 321 2 114 55 7 7 49 clb auto 29.8 MiB 0.39 459 2031 574 1374 83 69.3 MiB 0.03 0.00 4.6413 0 0 4.31525 0.00 0.000635584 0.000552586 0.0173645 0.0155707 -1 -1 -1 -1 570 5.27778 228 2.11111 239 439 10467 3202 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 4.62935 4.30491 0 0 -165.142 -1.707 0.05 -1 -1 69.3 MiB 0.14 0.147679 0.140851 69.3 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt index aa786b4ddf8..19fe5d4556f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.07141 -1 1.37913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.30941 -1 -1.86724 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt index 20374de3e27..8285cf5d7b5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 2.74 vpr 66.21 MiB 0.07 9628 -1 -1 3 0.35 -1 -1 34640 -1 -1 66 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67804 99 130 363 493 1 250 296 12 12 144 clb auto 27.0 MiB 0.19 914 65372 15140 25128 25104 66.2 MiB 0.10 0.00 34 2054 14 5.66058e+06 4.105e+06 317980. 2208.19 0.75 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 2.66 vpr 68.27 MiB 0.06 9984 -1 -1 3 0.36 -1 -1 39780 -1 -1 66 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69908 99 130 363 493 1 250 296 12 12 144 clb auto 29.2 MiB 0.21 805 57484 15208 21002 21274 68.3 MiB 0.11 0.00 40 1774 10 5.66058e+06 4.105e+06 360333. 2502.31 0.52 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt index 7d08de7d57f..735a18dab2b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.18 vpr 64.60 MiB 0.08 9968 -1 -1 4 0.19 -1 -1 33248 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66148 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00212704 0.00202414 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.45 vpr 66.93 MiB 0.09 10368 -1 -1 4 0.22 -1 -1 36756 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68532 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00571426 0.00556672 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt index a85975233a5..402ade22624 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.29 vpr 64.50 MiB 0.08 9892 -1 -1 4 0.20 -1 -1 33360 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66052 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 439 1932 239 1639 54 64.5 MiB 0.03 0.00 2.45489 -180.196 -2.45489 2.33213 0.07 0.000557675 0.000497069 0.0140116 0.0127239 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0161027 0.014718 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.29 vpr 66.33 MiB 0.06 10368 -1 -1 4 0.21 -1 -1 36632 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67920 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.08 427 1815 293 1474 48 66.3 MiB 0.04 0.00 2.45489 -180.219 -2.45489 2.30757 0.05 0.000892007 0.00076546 0.0179963 0.0157273 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0202445 0.0178347 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt index c26de4c60a8..8bf865796ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml mult_5x6.blif common 0.77 vpr 58.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59976 11 11 59 70 0 48 26 4 4 16 clb auto 19.2 MiB 0.04 179 634 146 488 0 58.6 MiB 0.01 0.00 2.51353 -20.6332 -2.51353 nan 0.01 0.000235015 0.000215515 0.00574618 0.00532029 -1 -1 -1 -1 30 199 15 215576 215576 18771.3 1173.21 0.19 0.061719 0.0519663 1016 3020 -1 198 17 257 591 8958 4396 2.73234 nan -23.1489 -2.73234 0 0 22855.5 1428.47 0.01 0.02 0.01 -1 -1 0.01 0.0122134 0.0110341 - k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.05 vpr 21.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 22068 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 19.1 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_5x6.blif common 0.57 vpr 60.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62456 11 11 59 70 0 48 26 4 4 16 clb auto 22.0 MiB 0.04 179 862 260 602 0 61.0 MiB 0.01 0.00 2.46139 -19.889 -2.46139 nan 0.01 0.000234107 0.000208327 0.0069198 0.00625105 -1 -1 -1 -1 28 244 41 215576 215576 17602.3 1100.14 0.10 0.0507337 0.0443992 984 2821 -1 165 13 220 476 6314 3099 2.61613 nan -21.1174 -2.61613 0 0 21084.5 1317.78 0.00 0.02 0.00 -1 -1 0.00 0.0119559 0.010883 + k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.07 vpr 23.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 23940 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 22.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt index 0266ed5293a..af7706738c0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common 0.29 vpr 62.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64140 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 20 30 10 17 3 62.6 MiB 0.00 0.00 0.645658 -3.51726 -0.645658 0.571 0.01 4.8438e-05 3.4201e-05 0.00152576 0.00147521 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00152576 0.00147521 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml multiclock.blif common 0.24 vpr 64.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66340 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 21 30 9 19 2 64.8 MiB 0.01 0.00 0.646042 -3.51892 -0.646042 0.571 0.01 6.4699e-05 4.5848e-05 0.00182479 0.00174439 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00182479 0.00174439 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt index 457652c3ee3..25609b75a68 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 38.59 vpr 976.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999904 10 10 168 178 1 68 30 11 8 88 io auto 953.3 MiB 0.63 393 628 105 491 32 976.5 MiB 0.06 0.00 6.51193 -69.1178 -6.51193 6.51193 3.11 0.000480842 0.000431377 0.0112949 0.0105397 -1 -1 -1 -1 20 893 28 0 0 100248. 1139.18 0.66 0.109748 0.0976349 11180 23751 -1 831 19 496 1987 121384 60113 6.91414 6.91414 -78.1319 -6.91414 0 0 150556. 1710.86 0.02 0.09 0.07 -1 -1 0.02 0.0302143 0.0267735 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 38.84 vpr 976.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1000004 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.62 380 628 91 496 41 976.6 MiB 0.06 0.00 6.52338 -69.1003 -6.52338 6.52338 3.24 0.000527135 0.000462877 0.0115671 0.0108087 -1 -1 -1 -1 30 673 12 0 0 144567. 1642.81 0.58 0.0925956 0.0823255 11730 32605 -1 585 9 216 698 45031 21119 6.8993 6.8993 -73.7008 -6.8993 0 0 194014. 2204.70 0.03 0.06 0.10 -1 -1 0.03 0.0207007 0.0188861 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 40.21 vpr 976.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999952 10 10 168 178 1 68 30 11 8 88 io auto 953.3 MiB 0.62 369 766 101 608 57 976.5 MiB 0.07 0.00 6.29548 -69.1499 -6.29548 6.29548 3.96 0.000642065 0.000578628 0.0144046 0.0134125 -1 -1 -1 -1 20 979 39 0 0 100248. 1139.18 1.54 0.210388 0.179459 11180 23751 -1 730 15 326 1149 70174 36157 6.70251 6.70251 -75.6785 -6.70251 0 0 125464. 1425.72 0.02 0.07 0.07 -1 -1 0.02 0.0262708 0.0234853 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 39.65 vpr 976.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999996 10 10 168 178 1 68 30 11 8 88 io auto 953.5 MiB 0.62 393 720 70 599 51 976.6 MiB 0.06 0.00 6.29266 -69.3194 -6.29266 6.29266 3.95 0.000492354 0.000450911 0.0121985 0.0113493 -1 -1 -1 -1 30 792 16 0 0 144567. 1642.81 0.52 0.0829003 0.0732049 11730 32605 -1 644 15 284 1326 83485 37502 6.72776 6.72776 -73.9475 -6.72776 0 0 194014. 2204.70 0.03 0.07 0.10 -1 -1 0.03 0.0265404 0.0237185 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 40.74 vpr 978.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001944 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.61 385 628 76 517 35 978.5 MiB 0.06 0.00 6.37842 -68.9926 -6.37842 6.37842 2.79 0.000585035 0.000506509 0.0125856 0.0113967 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.17 0.202681 0.177336 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.09 0.08 -1 -1 0.01 0.0322374 0.0298184 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 42.57 vpr 978.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001668 10 10 168 178 1 68 30 11 8 88 io auto 955.1 MiB 0.58 356 628 86 501 41 978.2 MiB 0.08 0.00 6.32784 -69.1369 -6.32784 6.32784 2.79 0.00106817 0.000941606 0.0173949 0.0157097 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 1.41 0.24274 0.212439 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.08 0.08 -1 -1 0.01 0.0393492 0.0368597 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 41.18 vpr 978.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001944 10 10 168 178 1 68 30 11 8 88 io auto 955.2 MiB 0.77 378 628 92 504 32 978.5 MiB 0.06 0.00 6.37842 -68.9795 -6.37842 6.37842 3.93 0.000461318 0.000398366 0.0135017 0.0123478 -1 -1 -1 -1 30 740 27 0 0 144567. 1642.81 1.27 0.212409 0.18717 11730 32605 -1 579 10 219 802 50034 22946 6.80801 6.80801 -73.0986 -6.80801 0 0 194014. 2204.70 0.01 0.06 0.10 -1 -1 0.01 0.0272644 0.0255028 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 43.49 vpr 978.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002044 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.67 353 582 71 475 36 978.6 MiB 0.10 0.00 6.2342 -69.2052 -6.2342 6.2342 4.26 0.00126519 0.00120018 0.0174025 0.0162066 -1 -1 -1 -1 22 762 19 0 0 110609. 1256.92 0.57 0.121021 0.108951 11258 24748 -1 710 14 413 1547 91286 47129 6.80216 6.80216 -76.023 -6.80216 0 0 134428. 1527.59 0.01 0.08 0.05 -1 -1 0.01 0.0301878 0.0279201 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt index 2d257ead4b6..de612c1c661 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 39.27 vpr 976.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999936 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.61 393 628 105 491 32 976.5 MiB 0.06 0.00 6.51193 -69.1178 -6.51193 6.51193 3.33 0.000569129 0.000496002 0.012275 0.0114625 -1 -1 -1 -1 20 893 28 0 0 100248. 1139.18 0.66 0.116406 0.101755 11180 23751 -1 831 19 496 1987 121384 60113 6.91414 6.91414 -78.1319 -6.91414 0 0 150556. 1710.86 0.02 0.09 0.07 -1 -1 0.02 0.0312385 0.0276729 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 36.90 vpr 976.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1000112 10 10 168 178 1 68 30 11 8 88 io auto 953.7 MiB 0.60 380 628 91 496 41 976.7 MiB 0.06 0.00 6.52338 -69.1003 -6.52338 6.52338 3.10 0.000501046 0.000450601 0.0117982 0.0109963 -1 -1 -1 -1 30 673 12 0 0 144567. 1642.81 0.47 0.0799941 0.0704629 11730 32605 -1 585 9 216 698 45031 21119 6.8993 6.8993 -73.7008 -6.8993 0 0 194014. 2204.70 0.03 0.06 0.10 -1 -1 0.03 0.0206622 0.0188402 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 41.99 vpr 978.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001688 10 10 168 178 1 68 30 11 8 88 io auto 955.2 MiB 0.85 385 628 76 517 35 978.2 MiB 0.09 0.00 6.37842 -68.9926 -6.37842 6.37842 2.49 0.000740479 0.000647957 0.0145497 0.0133659 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.45 0.22055 0.192568 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.11 0.10 -1 -1 0.01 0.0358167 0.033477 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 41.03 vpr 978.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001836 10 10 168 178 1 68 30 11 8 88 io auto 955.3 MiB 0.66 356 628 86 501 41 978.4 MiB 0.10 0.00 6.32784 -69.1369 -6.32784 6.32784 2.55 0.000491141 0.000429611 0.0148781 0.0136279 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 1.47 0.229896 0.203057 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.11 0.09 -1 -1 0.01 0.0316333 0.0293122 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt index 02e9ce0dfc9..be79764ceb1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml ex5p.blif common_--place_effort_scaling_circuit 4.11 vpr 74.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76128 8 63 1072 1135 0 619 135 12 12 144 clb auto 34.5 MiB 2.33 6183 12245 2318 9041 886 74.3 MiB 0.42 0.01 4.99539 -218.829 -4.99539 nan 0.40 0.00404212 0.00341765 0.184837 0.163351 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.189101 0.167214 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 4.01 vpr 74.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76144 8 63 1072 1135 0 619 135 12 12 144 clb auto 34.3 MiB 2.38 6325 11326 2120 8412 794 74.4 MiB 0.36 0.01 4.96391 -216.681 -4.96391 nan 0.38 0.00390508 0.00360049 0.150898 0.136289 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.155447 0.140327 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 9.78 vpr 78.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 79868 8 63 1072 1135 0 619 135 27 27 729 -1 auto 34.2 MiB 2.05 6780 22625 6869 14375 1381 77.8 MiB 0.53 0.01 5.57619 -254.596 -5.57619 nan 3.24 0.00298107 0.00257554 0.222411 0.19574 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.226597 0.199503 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 10.33 vpr 78.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 79920 8 63 1072 1135 0 619 135 27 27 729 -1 auto 34.4 MiB 2.32 6916 70425 20372 45422 4631 78.0 MiB 1.06 0.02 5.61138 -254.037 -5.61138 nan 3.32 0.00308249 0.00275482 0.219018 0.196554 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.223523 0.200574 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_circuit 4.26 vpr 76.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78288 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.83 6246 12245 2336 8854 1055 76.5 MiB 0.39 0.01 4.93521 -218.151 -4.93521 nan 0.27 0.00393519 0.00333322 0.167205 0.141172 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.170495 0.143929 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 3.34 vpr 76.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78408 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.32 6248 12409 2316 9051 1042 76.6 MiB 0.27 0.01 5.00015 -217.921 -5.00015 nan 0.18 0.00183948 0.00156955 0.109821 0.0973753 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.11472 0.101715 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 6.81 vpr 76.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78560 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.7 MiB 2.45 6557 16051 3559 11939 553 76.7 MiB 0.47 0.01 5.39652 -231.823 -5.39652 nan 1.67 0.00368316 0.00300979 0.191413 0.165252 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.196386 0.169658 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 7.69 vpr 76.65 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78492 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.4 MiB 2.51 6642 53385 10847 39555 2983 76.7 MiB 1.06 0.02 5.30857 -236.309 -5.30857 nan 1.91 0.00201874 0.00161249 0.24975 0.219272 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.258981 0.227848 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt index 894bbbd344b..b0056cc1abc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.45 vpr 64.46 MiB 0.06 10080 -1 -1 4 0.19 -1 -1 33316 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66004 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.08 439 1932 239 1639 54 64.5 MiB 0.03 0.00 2.45489 -180.196 -2.45489 2.33213 0.08 0.000661458 0.000589394 0.0146171 0.0132586 -1 -1 -1 -1 20 684 34 1.07788e+06 1.02399e+06 49980.0 1020.00 0.62 0.239102 0.203363 2664 9102 -1 585 25 992 2191 68660 23567 2.62928 2.46785 -187.223 -2.62928 0 0 65453.8 1335.79 0.02 0.09 0.01 -1 -1 0.02 0.0513972 0.044921 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.86 vpr 66.93 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68536 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 427 1815 293 1474 48 66.9 MiB 0.03 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.00072366 0.000614909 0.0157761 0.0136171 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.27 0.140412 0.11741 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.06 0.01 -1 -1 0.00 0.0578011 0.0529737 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt index d972ea27949..c15f8828261 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.51 vpr 60.07 MiB -1 -1 -1 -1 0 0.02 -1 -1 30028 -1 -1 1 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61512 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.3 MiB 0.00 0 3 0 0 3 60.1 MiB 0.01 0.00 nan 0 0 nan 0.00 1.7627e-05 1.1573e-05 0.000113513 8.1967e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.01 0.00151028 0.00142155 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.50 vpr 60.09 MiB -1 -1 -1 -1 0 0.02 -1 -1 30092 -1 -1 1 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61532 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.4 MiB 0.01 0 3 0 0 3 60.1 MiB 0.01 0.00 nan 0 0 nan 0.00 3.6083e-05 2.8637e-05 0.000127329 9.3377e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 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a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt index 6a4e552e822..1f6be016ab1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 5.32 vpr 65.56 MiB 0.06 9324 -1 -1 3 0.35 -1 -1 34640 -1 52944 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67136 99 130 363 493 1 251 298 12 12 144 clb auto 26.3 MiB 0.14 892 61988 19791 31117 11080 65.6 MiB 0.20 0.00 2.45187 -222.514 -2.45187 2.45187 0.36 0.000915265 0.000857739 0.0611213 0.0573235 -1 -1 -1 -1 42 1632 14 5.66058e+06 4.21279e+06 345702. 2400.71 1.98 0.420146 0.379604 12810 66778 -1 1532 10 491 638 43042 14380 2.64362 2.64362 -241.091 -2.64362 0 0 434679. 3018.61 0.14 0.06 0.07 -1 -1 0.14 0.0352631 0.033178 0.008708 0.223 0.06667 0.7103 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 13.86 vpr 69.06 MiB 0.04 9360 -1 -1 15 0.45 -1 -1 34776 -1 54676 38 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70720 162 96 999 932 1 689 301 16 16 256 mult_36 auto 29.7 MiB 0.41 5715 87997 27324 53359 7314 69.1 MiB 0.74 0.01 21.0193 -1891.98 -21.0193 21.0193 0.81 0.00444774 0.00422894 0.323103 0.304448 -1 -1 -1 -1 46 12696 36 1.21132e+07 4.02797e+06 727248. 2840.81 6.60 1.22942 1.13708 24972 144857 -1 9788 21 3242 6502 928862 268718 22.8323 22.8323 -2032.58 -22.8323 0 0 934704. 3651.19 0.32 0.43 0.16 -1 -1 0.32 0.182261 0.17068 0.007695 0.3421 0.01642 0.6414 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.79 vpr 67.81 MiB 0.06 9856 -1 -1 3 0.37 -1 -1 39772 -1 54808 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69436 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.13 821 70943 24958 34400 11585 67.8 MiB 0.24 0.00 2.51136 -219.195 -2.51136 2.51136 0.28 0.000896235 0.000803075 0.0731146 0.0664864 -1 -1 -1 -1 40 1499 25 5.66058e+06 4.21279e+06 333335. 2314.82 1.63 0.35542 0.319058 12666 64609 -1 1442 10 553 749 42115 14455 2.64494 2.64494 -235.699 -2.64494 0 0 419432. 2912.72 0.02 0.06 0.11 -1 -1 0.02 0.0374155 0.0350957 0.008441 0.2001 0.06777 0.7321 + k6_frac_N10_mem32K_40nm.xml diffeq1.v common 16.21 vpr 71.75 MiB 0.06 9856 -1 -1 15 0.50 -1 -1 38288 -1 56228 38 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73476 162 96 999 932 1 689 301 16 16 256 mult_36 auto 32.3 MiB 0.49 5426 96061 33445 54809 7807 71.8 MiB 1.03 0.02 21.3991 -1811.48 -21.3991 21.3991 0.51 0.00504368 0.00468153 0.493175 0.461597 -1 -1 -1 -1 56 11482 33 1.21132e+07 4.02797e+06 870502. 3400.40 8.42 2.47741 2.31569 26504 172068 -1 9223 22 3083 6041 811453 269172 22.8885 22.8885 -1951.66 -22.8885 0 0 1.11200e+06 4343.75 0.07 0.47 0.29 -1 -1 0.07 0.221232 0.208061 0.007874 0.3571 0.01689 0.626 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt index 84ecf217097..d6f9144a21f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.42 vpr 64.63 MiB 0.08 10092 -1 -1 4 0.21 -1 -1 33404 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66180 11 30 262 292 2 99 60 7 7 49 clb auto 24.9 MiB 0.09 421 2049 269 1715 65 64.6 MiB 0.04 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 0.000642825 0.000574377 0.0150724 0.0136437 -1 -1 -1 -1 424 4.46316 163 1.71579 617 1399 45810 10033 1.07788e+06 1.02399e+06 207176. 4228.08 16 4440 29880 -1 2.36464 2.27781 -179.43 -2.36464 0 0 0.03 -1 -1 64.6 MiB 0.06 0.0447701 0.039887 64.6 MiB -1 0.04 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.66 vpr 67.05 MiB 0.06 10172 -1 -1 5 0.18 -1 -1 33356 -1 -1 14 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68656 11 30 313 321 2 115 55 7 7 49 clb auto 27.3 MiB 0.32 466 2759 556 2108 95 67.0 MiB 0.06 0.00 2.67362 -172.647 -2.67362 2.30794 0.00 0.000887719 0.000807056 0.0300856 0.0276351 -1 -1 -1 -1 574 5.26606 231 2.11927 216 452 11450 3638 1.07788e+06 754516 219490. 4479.39 7 5100 32136 -1 2.71877 2.35385 -178.475 -2.71877 0 0 0.04 -1 -1 67.0 MiB 0.03 0.057894 0.0532276 67.0 MiB -1 0.04 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.32 vpr 66.34 MiB 0.08 10496 -1 -1 4 0.22 -1 -1 36740 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67936 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.07 425 2283 406 1804 73 66.3 MiB 0.04 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000792071 0.00065667 0.0233552 0.0207856 -1 -1 -1 -1 414 4.35789 166 1.74737 630 1427 58282 13907 1.07788e+06 1.02399e+06 207176. 4228.08 20 4440 29880 -1 2.3823 2.2863 -180.577 -2.3823 0 0 0.05 -1 -1 66.3 MiB 0.07 0.0694098 0.0624777 66.3 MiB -1 0.01 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.84 vpr 69.28 MiB 0.07 10496 -1 -1 5 0.19 -1 -1 36360 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70940 11 30 313 321 2 115 55 7 7 49 clb auto 29.8 MiB 0.48 448 1927 352 1502 73 69.3 MiB 0.05 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.00080657 0.000690329 0.0283624 0.0258806 -1 -1 -1 -1 595 5.45872 228 2.09174 234 449 14202 4622 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 2.70461 2.28805 -176.84 -2.70461 0 0 0.06 -1 -1 69.3 MiB 0.04 0.0633117 0.0585851 69.3 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt index e9f8c264924..9c4fd28b84b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 38.30 vpr 86.88 MiB 0.47 29360 -1 -1 4 2.33 -1 -1 37992 -1 -1 169 193 5 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 88968 193 205 2863 2789 1 1374 572 20 20 400 memory auto 43.4 MiB 1.96 11201 252110 92751 131930 27429 84.4 MiB 2.44 0.03 4.45067 -2677.23 -4.45067 4.45067 1.78 0.00740583 0.00674714 0.935753 0.830726 -1 -1 -1 -1 80 22067 51 2.07112e+07 1.18481e+07 2.10510e+06 5262.74 22.74 5.25463 4.68017 53274 447440 -1 19298 17 5571 15462 1144445 252495 4.66289 4.66289 -2899.83 -4.66289 -11.7102 -0.360359 2.64606e+06 6615.15 0.68 0.62 0.38 -1 -1 0.68 0.376497 0.344469 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 29.83 vpr 86.25 MiB 0.45 29568 -1 -1 4 2.98 -1 -1 43168 -1 -1 169 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88324 193 205 2863 2789 1 1374 572 20 20 400 memory auto 45.0 MiB 2.27 10985 240245 81936 130873 27436 86.3 MiB 2.86 0.03 4.42447 -2617.73 -4.42447 4.42447 0.89 0.00871072 0.007701 1.03653 0.893245 -1 -1 -1 -1 78 21148 33 2.07112e+07 1.18481e+07 2.06176e+06 5154.39 13.92 4.09327 3.61448 52874 439520 -1 19015 17 5137 14374 1050969 231484 5.06231 5.06231 -2806.44 -5.06231 -11.1461 -0.341744 2.60035e+06 6500.87 0.19 0.98 0.77 -1 -1 0.19 0.584807 0.525478 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt index 82ee8b5f85d..812f4d3bdb5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 2.28 vpr 69.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70720 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.53 4989 14482 2605 10909 968 69.1 MiB 0.29 0.01 4.15324 -188.164 -4.15324 nan 0.00 0.00281296 0.00243514 0.139942 0.124398 -1 -1 -1 -1 6805 14.9560 1830 4.02198 3625 14263 570126 87469 9.20055e+06 4.79657e+06 867065. 4423.80 19 18088 133656 -1 4.17843 nan -185.467 -4.17843 0 0 0.16 -1 -1 69.1 MiB 0.45 0.325496 0.291568 69.1 MiB -1 0.29 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 2.22 vpr 69.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70764 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.51 4989 14482 2605 10909 968 69.1 MiB 0.29 0.01 4.15324 -188.164 -4.15324 nan 0.00 0.00262456 0.00232451 0.12615 0.110723 -1 -1 -1 -1 6877 15.1143 1848 4.06154 3712 14523 564432 88116 9.20055e+06 4.79657e+06 867065. 4423.80 19 18088 133656 -1 4.14924 nan -185.7 -4.14924 0 0 0.15 -1 -1 69.1 MiB 0.40 0.298349 0.266584 69.1 MiB -1 0.30 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.96 vpr 71.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73224 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.52 4992 14048 2664 10357 1027 71.5 MiB 0.35 0.02 4.19211 -186.67 -4.19211 nan 0.00 0.00713555 0.00269028 0.139755 0.114328 -1 -1 -1 -1 6642 14.5978 1787 3.92747 3214 12750 489499 77791 9.20055e+06 4.79657e+06 867065. 4423.80 16 18088 133656 -1 4.47188 nan -188.808 -4.47188 0 0 0.22 -1 -1 71.5 MiB 0.32 0.294582 0.254721 71.5 MiB -1 0.05 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 2.24 vpr 71.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73336 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.64 4992 14048 2664 10357 1027 71.6 MiB 0.33 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00345084 0.002875 0.154792 0.13937 -1 -1 -1 -1 6701 14.7275 1794 3.94286 3137 12291 459530 73860 9.20055e+06 4.79657e+06 867065. 4423.80 18 18088 133656 -1 4.41143 nan -186.654 -4.41143 0 0 0.26 -1 -1 71.6 MiB 0.37 0.334856 0.303047 71.6 MiB -1 0.08 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt index 9e26968d0ac..ca94c478175 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 2.11 vpr 69.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70752 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.50 4981 18388 4106 12671 1611 69.1 MiB 0.33 0.01 3.67827 -162.703 -3.67827 nan 0.04 0.00316093 0.00267964 0.156067 0.137885 -1 -1 -1 -1 6929 15.2286 1856 4.07912 4031 16057 1191599 209386 9.20055e+06 4.79657e+06 701736. 3580.29 21 16332 105598 -1 4.26894 nan -186.127 -4.26894 0 0 0.12 -1 -1 69.1 MiB 0.45 0.320906 0.286349 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 2.11 vpr 69.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70696 8 63 748 811 0 455 160 14 14 196 clb auto 29.4 MiB 0.50 4947 14048 2843 10376 829 69.0 MiB 0.27 0.01 4.36787 -194.851 -4.36787 nan 0.00 0.00329553 0.00282923 0.129786 0.114331 -1 -1 -1 -1 7013 15.4132 1882 4.13626 4368 18266 702728 114564 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.35011 nan -200.403 -4.35011 0 0 0.12 -1 -1 69.0 MiB 0.41 0.312316 0.278054 69.0 MiB -1 0.23 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 3.39 vpr 69.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70752 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.50 4953 17954 4036 12536 1382 69.1 MiB 0.35 0.01 3.75278 -163.938 -3.75278 nan 0.07 0.0033402 0.00290592 0.147752 0.129486 -1 -1 -1 -1 7096 15.5956 1936 4.25495 3839 15635 1250449 222869 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.31984 nan -190.626 -4.31984 0 0 0.14 -1 -1 69.1 MiB 0.53 0.335395 0.295263 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.38 vpr 69.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70780 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.50 4953 17954 4036 12536 1382 69.1 MiB 0.33 0.01 3.75278 -163.938 -3.75278 nan 0.07 0.00358739 0.00315042 0.148074 0.130756 -1 -1 -1 -1 7096 15.5956 1936 4.25495 3839 15635 1250449 222869 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.31984 nan -190.626 -4.31984 0 0 0.14 -1 -1 69.1 MiB 0.56 0.339968 0.302409 -1 -1 -1 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 2.33 vpr 71.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73184 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.53 4993 17086 3593 12286 1207 71.5 MiB 0.39 0.01 3.65588 -160.421 -3.65588 nan 0.05 0.00324947 0.00265148 0.171741 0.145172 -1 -1 -1 -1 7077 15.5538 1900 4.17582 3821 15130 1125339 197021 9.20055e+06 4.79657e+06 701736. 3580.29 19 16332 105598 -1 4.24547 nan -186.357 -4.24547 0 0 0.19 -1 -1 71.5 MiB 0.65 0.403427 0.354208 -1 -1 -1 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 2.06 vpr 71.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72900 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.61 4933 15350 2970 11325 1055 71.2 MiB 0.33 0.01 4.27873 -192.837 -4.27873 nan 0.00 0.00354772 0.00306723 0.134491 0.114487 -1 -1 -1 -1 7099 15.6022 1898 4.17143 3600 14045 536072 90036 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.46795 nan -200.148 -4.46795 0 0 0.16 -1 -1 71.2 MiB 0.37 0.342443 0.304101 71.2 MiB -1 0.04 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 4.12 vpr 71.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73084 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.46 5048 17520 3917 12196 1407 71.4 MiB 0.41 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.0055915 0.00450451 0.174816 0.150375 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.22 -1 -1 71.4 MiB 0.70 0.438594 0.389856 -1 -1 -1 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.79 vpr 71.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73092 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.50 5048 17520 3917 12196 1407 71.4 MiB 0.34 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.00371073 0.00310746 0.151921 0.128885 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.16 -1 -1 71.4 MiB 0.65 0.390878 0.342895 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt index 42d0070c39d..73afad51c48 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 1.98 vpr 69.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70736 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.45 5081 14916 3009 10977 930 69.1 MiB 0.27 0.01 4.4281 -198.501 -4.4281 nan 0.00 0.00300537 0.00251178 0.118094 0.103153 -1 -1 -1 -1 6741 14.8154 1803 3.96264 3315 13570 497205 81432 9.20055e+06 4.79657e+06 787177. 4016.21 19 17112 118924 -1 4.40099 nan -202.066 -4.40099 0 0 0.13 -1 -1 69.1 MiB 0.34 0.282273 0.252167 69.1 MiB -1 0.26 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 2.02 vpr 69.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70816 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.53 5081 14916 3009 10977 930 69.2 MiB 0.26 0.01 4.4281 -198.501 -4.4281 nan 0.00 0.00303209 0.00274882 0.116032 0.102412 -1 -1 -1 -1 6767 14.8725 1813 3.98462 3295 13377 489418 80231 9.20055e+06 4.79657e+06 787177. 4016.21 18 17112 118924 -1 4.40099 nan -201.997 -4.40099 0 0 0.13 -1 -1 69.2 MiB 0.33 0.270765 0.24325 69.2 MiB -1 0.28 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 2.09 vpr 71.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73036 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.54 5066 14916 2828 10927 1161 71.3 MiB 0.32 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00299665 0.00251735 0.139481 0.119628 -1 -1 -1 -1 6988 15.3582 1874 4.11868 3892 16491 596262 97679 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.23403 nan -187.789 -4.23403 0 0 0.17 -1 -1 71.3 MiB 0.42 0.337391 0.298836 71.3 MiB -1 0.06 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 2.37 vpr 71.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73112 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.54 5066 14916 2828 10927 1161 71.4 MiB 0.36 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00287338 0.00244407 0.145055 0.130505 -1 -1 -1 -1 6949 15.2725 1858 4.08352 3794 15906 573229 94207 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.30087 nan -188.544 -4.30087 0 0 0.23 -1 -1 71.4 MiB 0.57 0.403361 0.368877 71.4 MiB -1 0.07 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt index 8e0c47bf03f..d51a6534507 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - slicem.xml carry_chain.blif common 0.90 vpr 57.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58700 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 18.2 MiB 0.24 70 15 2 12 1 57.3 MiB 0.00 0.00 0.645672 -5.8162 -0.645672 0.645672 0.00 0.000120184 0.000109173 0.000865636 0.00080802 -1 -1 -1 -1 25 294 14 133321 74067 -1 -1 0.23 0.0266638 0.0220764 1252 5405 -1 287 14 116 116 21465 12891 1.98076 1.98076 -20.8107 -1.98076 0 0 -1 -1 0.01 0.02 0.00 -1 -1 0.01 0.0055322 0.00492928 + slicem.xml carry_chain.blif common 1.14 vpr 59.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61108 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 20.9 MiB 0.25 70 15 4 10 1 59.7 MiB 0.00 0.00 0.532448 -5.19346 -0.532448 0.532448 0.00 0.000126011 0.000111009 0.000872338 0.000798258 -1 -1 -1 -1 25 262 18 133321 74067 -1 -1 0.48 0.0703731 0.0607281 1252 5405 -1 274 13 122 122 23159 13821 1.78919 1.78919 -18.223 -1.78919 0 0 -1 -1 0.00 0.02 0.01 -1 -1 0.00 0.00593831 0.00529293 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt index d6a3abf2024..2974b610be2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml ndff.blif common 0.46 vpr 56.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57772 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 17.6 MiB 0.01 31 35 6 27 2 56.4 MiB 0.01 0.00 0.212927 -2.22016 -0.212927 0.212927 0.00 5.0007e-05 3.8931e-05 0.000238974 0.000194906 -1 -1 -1 -1 4 28 4 59253.6 44440.2 -1 -1 0.06 0.0047932 0.00391937 184 632 -1 29 2 13 18 795 367 0.309802 0.309802 -2.85512 -0.309802 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00161011 0.00154347 + arch.xml ndff.blif common 0.30 vpr 59.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60508 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 20.6 MiB 0.00 31 59 13 43 3 59.1 MiB 0.00 0.00 0.247067 -2.25231 -0.247067 0.247067 0.00 3.5462e-05 2.8363e-05 0.000299521 0.0002448 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00397217 0.00338578 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00197845 0.00188555 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt index 282c80c20d3..936401071c3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.68 vpr 67.04 MiB 0.07 10084 -1 -1 5 0.18 -1 -1 33256 -1 -1 14 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68648 11 30 313 321 2 114 55 7 7 49 clb auto 27.3 MiB 0.34 439 1511 357 1028 126 67.0 MiB 0.04 0.00 4.62621 0 0 4.30823 0.00 0.000680839 0.000625665 0.0199326 0.0187542 -1 -1 -1 -1 639 5.91667 232 2.14815 338 674 15463 4560 1.07788e+06 754516 219490. 4479.39 10 5100 32136 -1 4.76665 4.41703 0 0 -164.948 -1.707 0.04 -1 -1 67.0 MiB 0.05 0.0545015 0.0506933 67.0 MiB -1 0.04 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.54 vpr 68.95 MiB 0.06 10496 -1 -1 5 0.18 -1 -1 36448 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70604 11 30 313 321 2 114 55 7 7 49 clb auto 29.5 MiB 0.39 459 2031 574 1374 83 68.9 MiB 0.04 0.00 4.6413 0 0 4.31525 0.00 0.000717512 0.000626394 0.019463 0.0174272 -1 -1 -1 -1 569 5.26852 227 2.10185 207 393 9602 2945 1.07788e+06 754516 219490. 4479.39 7 5100 32136 -1 4.62935 4.30491 0 0 -165.142 -1.707 0.05 -1 -1 68.9 MiB 0.06 0.0634405 0.0562085 68.9 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/config.txt index 2f93f53041c..440149973b7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/config.txt @@ -24,7 +24,7 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt # Script parameters -script_params_common = -starting_stage vpr +script_params_common = -starting_stage vpr --seed 6 script_params_list_add = -sdc_file sdc/samples/A.sdc script_params_list_add = -sdc_file sdc/samples/B.sdc script_params_list_add = -sdc_file sdc/samples/C.sdc diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt index 93ad79df1cb..f1ae2610488 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.46 vpr 63.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64540 5 3 11 14 2 9 10 4 4 16 clb auto 24.3 MiB 0.01 22 30 9 14 7 63.0 MiB 0.00 0.00 0.814339 -2.77068 -0.814339 0.571 0.01 4.6237e-05 3.9054e-05 0.0002174 0.000180615 -1 -1 -1 -1 8 18 2 107788 107788 4794.78 299.674 0.02 0.00197825 0.00183539 564 862 -1 18 4 10 10 199 87 0.757297 0.571 -2.63894 -0.757297 0 0 5401.54 337.596 0.00 0.01 0.00 -1 -1 0.00 0.00215654 0.00203426 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.51 vpr 62.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64424 5 3 11 14 2 9 10 4 4 16 clb auto 24.2 MiB 0.01 23 30 6 15 9 62.9 MiB 0.01 0.00 0.571 0 0 0.571 0.02 3.7988e-05 2.9784e-05 0.000252809 0.000212792 -1 -1 -1 -1 8 26 3 107788 107788 4794.78 299.674 0.03 0.00214308 0.00198029 564 862 -1 25 5 13 13 435 272 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.01 0.00 -1 -1 0.00 0.00179325 0.00170005 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.53 vpr 63.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64568 5 3 11 14 2 9 10 4 4 16 clb auto 24.3 MiB 0.01 20 30 10 18 2 63.1 MiB 0.00 0.00 0.645658 -2.18842 -0.645658 0.571 0.01 4.2928e-05 3.0736e-05 0.000257589 0.000202685 -1 -1 -1 -1 8 17 3 107788 107788 4794.78 299.674 0.01 0.00208504 0.00188215 564 862 -1 14 5 15 15 285 110 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00184632 0.00172634 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.57 vpr 62.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64396 5 3 11 14 2 9 10 4 4 16 clb auto 24.2 MiB 0.01 20 30 12 17 1 62.9 MiB 0.01 0.00 1.64534 -5.31677 -1.64534 0.571 0.01 5.3727e-05 3.88e-05 0.000288614 0.00022112 -1 -1 -1 -1 8 19 8 107788 107788 4794.78 299.674 0.05 0.00254374 0.00221143 564 862 -1 15 2 8 8 156 74 1.57153 0.571 -4.92067 -1.57153 0 0 5401.54 337.596 0.00 0.01 0.00 -1 -1 0.00 0.00180866 0.00171184 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.51 vpr 62.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64496 5 3 11 14 2 9 10 4 4 16 clb auto 24.2 MiB 0.01 20 30 8 18 4 63.0 MiB 0.00 0.00 1.44871 -2.90839 -1.44871 0.571 0.01 3.8739e-05 2.8831e-05 0.000233335 0.000188434 -1 -1 -1 -1 8 33 10 107788 107788 4794.78 299.674 0.02 0.0025966 0.00229332 564 862 -1 19 2 11 11 275 141 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00164291 0.00155522 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.51 vpr 62.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64328 5 3 11 14 2 9 10 4 4 16 clb auto 24.0 MiB 0.01 20 110 34 46 30 62.8 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 3.5398e-05 2.9142e-05 0.000512135 0.000417096 -1 -1 -1 -1 8 25 4 107788 107788 4794.78 299.674 0.02 0.00232795 0.00209925 564 862 -1 36 5 15 15 690 511 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00186912 0.00175661 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.44 vpr 65.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66884 5 3 11 14 2 9 10 4 4 16 clb auto 27.1 MiB 0.01 21 30 5 21 4 65.3 MiB 0.00 0.00 0.814658 -2.77132 -0.814658 0.571 0.01 3.9163e-05 3.0734e-05 0.00023521 0.000191167 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00213897 0.00197887 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00188153 0.00176769 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.42 vpr 65.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66820 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 22 30 6 14 10 65.3 MiB 0.00 0.00 0.571 0 0 0.571 0.01 6.1332e-05 3.1443e-05 0.00028123 0.000216755 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.00219985 0.00199813 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0028018 0.00269609 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.40 vpr 65.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66764 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.01 21 30 5 22 3 65.2 MiB 0.00 0.00 0.646297 -2.19033 -0.646297 0.571 0.01 3.8778e-05 3.099e-05 0.000214053 0.000176854 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00219902 0.00204346 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00216696 0.00200612 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.40 vpr 65.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66872 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 21 30 7 16 7 65.3 MiB 0.00 0.00 1.6463 -5.31965 -1.6463 0.571 0.01 4.3301e-05 3.3225e-05 0.000258104 0.000204952 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00214578 0.0019473 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00224405 0.00207678 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.38 vpr 65.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66984 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 22 30 8 15 7 65.4 MiB 0.00 0.00 1.44967 -2.9103 -1.44967 0.571 0.01 5.0024e-05 3.2956e-05 0.000205951 0.000157313 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00254156 0.00219599 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0022282 0.00180897 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.40 vpr 65.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66984 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.00 21 30 5 23 2 65.4 MiB 0.00 0.00 0.146298 0 0 0.571 0.01 5.2455e-05 4.3444e-05 0.00030806 0.000256078 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.01 0.00225516 0.00206503 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00187829 0.00175106 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt index c791c5fd70f..5a4eb2784da 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.90 vpr 63.86 MiB 0.01 6660 -1 -1 1 0.03 -1 -1 30168 -1 -1 3 9 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65396 9 8 75 70 1 36 20 5 5 25 clb auto 24.5 MiB 0.67 99 236 93 142 1 63.9 MiB 0.01 0.00 2.64007 -27.5545 -2.64007 2.64007 0.03 0.000150101 0.000136839 0.0027255 0.00257173 -1 -1 -1 -1 44 132 11 151211 75605.7 54748.7 2189.95 0.29 0.0536282 0.0447591 2196 9177 -1 123 7 84 95 3114 1581 2.22275 2.22275 -27.95 -2.22275 0 0 71025.7 2841.03 0.01 0.01 0.01 -1 -1 0.01 0.00628819 0.00587337 13 18 19 7 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.06 vpr 64.08 MiB 0.01 6644 -1 -1 1 0.03 -1 -1 30172 -1 -1 2 11 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65620 11 10 108 97 1 47 23 4 4 16 clb auto 24.7 MiB 2.90 130 119 34 71 14 64.1 MiB 0.02 0.00 3.45122 -42.2328 -3.45122 3.45122 0.02 0.00022162 0.000202735 0.00277225 0.00266397 -1 -1 -1 -1 32 246 49 50403.8 50403.8 20844.1 1302.76 0.19 0.0635376 0.0536173 1004 2840 -1 156 14 159 209 5514 3395 3.66504 3.66504 -47.9227 -3.66504 0 0 24991.0 1561.94 0.00 0.02 0.00 -1 -1 0.00 0.0101538 0.0089849 15 27 29 8 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 6.21 vpr 64.25 MiB 0.02 6556 -1 -1 1 0.03 -1 -1 30528 -1 -1 7 13 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65792 13 12 149 129 1 69 32 6 6 36 clb auto 24.8 MiB 4.92 213 1182 380 774 28 64.2 MiB 0.02 0.00 3.51316 -53.0648 -3.51316 3.51316 0.05 0.000206158 0.000187115 0.00735065 0.00685129 -1 -1 -1 -1 50 378 21 403230 176413 107229. 2978.57 0.23 0.0627034 0.0537731 3946 19047 -1 356 16 276 387 14108 5999 3.51316 3.51316 -57.4904 -3.51316 0 0 134937. 3748.26 0.02 0.02 0.02 -1 -1 0.02 0.014322 0.0130425 25 38 42 9 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 4.02 vpr 64.81 MiB 0.01 6608 -1 -1 1 0.05 -1 -1 30256 -1 -1 6 15 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66368 15 14 196 165 1 93 35 5 5 25 clb auto 25.0 MiB 2.37 300 1346 309 1009 28 64.8 MiB 0.03 0.00 3.75042 -65.1319 -3.75042 3.75042 0.03 0.000351053 0.000323744 0.0137524 0.0128999 -1 -1 -1 -1 52 464 29 151211 151211 63348.9 2533.96 0.55 0.128869 0.11071 2316 10503 -1 401 15 409 589 20950 9847 4.67732 4.67732 -77.987 -4.67732 0 0 82390.3 3295.61 0.02 0.05 0.01 -1 -1 0.02 0.0215504 0.0198136 36 51 57 11 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.23 vpr 64.92 MiB 0.01 6684 -1 -1 1 0.04 -1 -1 30264 -1 -1 5 17 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66480 17 16 251 206 1 119 38 5 5 25 clb auto 25.3 MiB 6.53 402 1424 302 1116 6 64.9 MiB 0.06 0.00 4.01364 -77.5944 -4.01364 4.01364 0.04 0.000638029 0.00057449 0.0201591 0.0188678 -1 -1 -1 -1 52 572 17 151211 126010 63348.9 2533.96 0.57 0.18627 0.160969 2316 10503 -1 511 21 627 1044 32807 14764 4.80785 4.80785 -90.325 -4.80785 0 0 82390.3 3295.61 0.01 0.04 0.01 -1 -1 0.01 0.025349 0.0229586 44 66 75 13 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.93 vpr 65.04 MiB 0.01 6560 -1 -1 1 0.04 -1 -1 30652 -1 -1 8 19 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66600 19 18 308 249 1 137 45 6 6 36 clb auto 25.5 MiB 5.82 477 1245 268 971 6 65.0 MiB 0.03 0.00 4.8546 -99.0847 -4.8546 4.8546 0.05 0.000431245 0.000395584 0.0118328 0.0111482 -1 -1 -1 -1 62 774 36 403230 201615 131137. 3642.71 0.93 0.239205 0.206338 4226 23319 -1 685 20 672 1088 36828 14161 5.13584 5.13584 -108.067 -5.13584 0 0 160622. 4461.73 0.02 0.07 0.02 -1 -1 0.02 0.037832 0.0338494 55 83 93 14 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.55 vpr 66.09 MiB 0.01 7168 -1 -1 1 0.03 -1 -1 33640 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67672 9 8 75 70 1 36 20 5 5 25 clb auto 27.1 MiB 0.69 94 695 228 460 7 66.1 MiB 0.01 0.00 2.48207 -26.1618 -2.48207 2.48207 0.03 0.000181733 0.000161557 0.00585234 0.0052913 -1 -1 -1 -1 52 134 15 151211 75605.7 63348.9 2533.96 0.11 0.0432562 0.0374575 2316 10503 -1 114 8 106 124 3566 1793 2.40307 2.40307 -27.5996 -2.40307 0 0 82390.3 3295.61 0.00 0.01 0.02 -1 -1 0.00 0.0069119 0.0064541 13 18 19 7 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.05 vpr 66.50 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33588 -1 -1 2 11 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68092 11 10 108 97 1 47 23 4 4 16 clb auto 27.2 MiB 3.14 125 439 123 270 46 66.5 MiB 0.01 0.00 3.45122 -41.5692 -3.45122 3.45122 0.01 0.000220655 0.000197533 0.0046684 0.00428671 -1 -1 -1 -1 30 238 26 50403.8 50403.8 19887.8 1242.99 0.18 0.0734016 0.0633094 992 2748 -1 177 19 176 222 5882 3651 3.90204 3.90204 -49.9067 -3.90204 0 0 24232.7 1514.54 0.00 0.02 0.00 -1 -1 0.00 0.013296 0.0120352 15 27 29 8 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 5.44 vpr 66.68 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33700 -1 -1 7 13 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68284 13 12 149 129 1 69 32 6 6 36 clb auto 27.4 MiB 4.03 199 682 229 444 9 66.7 MiB 0.02 0.00 3.51316 -53.1567 -3.51316 3.51316 0.06 0.000399911 0.000364812 0.00775114 0.00715794 -1 -1 -1 -1 40 438 24 403230 176413 88484.8 2457.91 0.50 0.147128 0.127344 3734 16003 -1 329 29 379 534 18280 7787 3.72931 3.72931 -57.4119 -3.72931 0 0 110337. 3064.92 0.00 0.02 0.01 -1 -1 0.00 0.0175574 0.0158074 25 38 42 9 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 3.95 vpr 66.76 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33776 -1 -1 6 15 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68364 15 14 196 165 1 93 35 5 5 25 clb auto 27.2 MiB 2.85 306 947 216 708 23 66.8 MiB 0.02 0.00 3.70693 -62.6491 -3.70693 3.70693 0.02 0.000376121 0.000333163 0.00931262 0.00852228 -1 -1 -1 -1 44 480 22 151211 151211 54748.7 2189.95 0.20 0.0954411 0.083284 2196 9177 -1 392 18 349 466 14859 7098 4.20858 4.20858 -72.9456 -4.20858 0 0 71025.7 2841.03 0.00 0.03 0.01 -1 -1 0.00 0.0211201 0.0192846 36 51 57 11 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.23 vpr 67.12 MiB 0.01 7040 -1 -1 1 0.06 -1 -1 33688 -1 -1 5 17 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68736 17 16 251 206 1 119 38 5 5 25 clb auto 27.6 MiB 7.05 397 2054 481 1553 20 67.1 MiB 0.04 0.00 3.86806 -74.2346 -3.86806 3.86806 0.03 0.00048716 0.000431817 0.0193024 0.0173986 -1 -1 -1 -1 50 602 24 151211 126010 61632.8 2465.31 0.24 0.130358 0.114428 2268 9834 -1 534 19 619 1012 32161 14755 4.95834 4.95834 -93.7979 -4.95834 0 0 77226.2 3089.05 0.00 0.04 0.01 -1 -1 0.00 0.0271021 0.0248239 44 66 75 13 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.16 vpr 67.18 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33916 -1 -1 8 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68792 19 18 308 249 1 137 45 6 6 36 clb auto 27.7 MiB 5.92 455 2365 460 1885 20 67.2 MiB 0.03 0.00 4.8546 -99.6039 -4.8546 4.8546 0.03 0.000494067 0.000457319 0.0145592 0.0132203 -1 -1 -1 -1 62 737 27 403230 201615 131137. 3642.71 0.40 0.139917 0.121866 4226 23319 -1 634 19 613 910 31131 12187 5.08188 5.08188 -101.573 -5.08188 0 0 160622. 4461.73 0.00 0.04 0.02 -1 -1 0.00 0.0328006 0.0301511 55 83 93 14 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt index 6d0dc10b927..8a6305788b3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common 6.87 vpr 56.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58140 6 7 19 26 0 19 26 3 3 9 -1 auto 18.1 MiB 0.00 51 216 43 63 110 56.8 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 5.75 4.0855e-05 3.4458e-05 0.0004697 0.000404466 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.11 0.00249677 0.00223949 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.01 0.04 -1 -1 0.00 0.00171008 0.00161397 + sub_tiles.xml sub_tiles.blif common 17.34 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60480 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.93 4.894e-05 4.1022e-05 0.00272802 0.000370563 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.13 0.00475066 0.00224296 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00235645 0.00226006 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt index effb073b2f4..518626ca870 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - heterogeneous_tile.xml sub_tile_directs.blif common 0.44 vpr 56.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57836 2 2 4 5 0 4 5 3 3 9 -1 auto 17.7 MiB 0.04 8 12 0 0 12 56.5 MiB 0.00 0.00 1.899 -3.798 -1.899 nan 0.02 2.1799e-05 1.5659e-05 0.000138032 0.000105158 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.01 0.00174536 0.00159206 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00138279 0.00133491 + heterogeneous_tile.xml sub_tile_directs.blif common 0.35 vpr 58.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60280 2 2 4 5 0 4 5 3 3 9 -1 auto 20.6 MiB 0.00 8 12 0 0 12 58.9 MiB 0.00 0.00 1.899 -3.798 -1.899 nan 0.03 1.7797e-05 1.2853e-05 0.000104532 7.7041e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.01 0.00210372 0.00170648 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.0014857 0.00144705 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt index 423988067a7..2adfcb2953c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.62 vpr 64.77 MiB 0.12 9348 -1 -1 3 0.34 -1 -1 34748 -1 -1 19 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66324 99 74 307 381 1 199 193 8 8 64 io memory auto 25.0 MiB 0.09 843 15232 2608 11323 1301 64.8 MiB 0.09 0.00 2.09714 -214.522 -2.09714 2.09714 0.11 0.00118231 0.00110602 0.0292446 0.027405 -1 -1 -1 -1 32 1663 43 2.23746e+06 1.57199e+06 106908. 1670.44 0.66 0.202684 0.181951 4378 18911 -1 1205 26 736 1206 90558 33684 2.26594 2.26594 -220.489 -2.26594 0 0 130676. 2041.82 0.04 0.09 0.03 -1 -1 0.04 0.0490947 0.0443597 + k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.13 vpr 66.94 MiB 0.07 9984 -1 -1 3 0.37 -1 -1 39768 -1 -1 19 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68544 99 74 307 381 1 199 193 8 8 64 io memory auto 27.3 MiB 0.07 869 22473 4565 15889 2019 66.9 MiB 0.09 0.00 2.15432 -215.614 -2.15432 2.15432 0.09 0.000919068 0.000833008 0.0321902 0.029066 -1 -1 -1 -1 32 1554 36 2.23746e+06 1.57199e+06 106908. 1670.44 0.41 0.172041 0.155343 4378 18911 -1 1152 12 699 1089 60199 20903 2.21433 2.21433 -220.084 -2.21433 0 0 130676. 2041.82 0.01 0.06 0.03 -1 -1 0.01 0.0316397 0.0293511 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt index 88f38747492..b4f05d4d127 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml styr.blif common_--target_ext_pin_util_1 1.86 vpr 66.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67772 10 10 168 178 1 73 31 6 6 36 clb auto 26.5 MiB 0.22 396 511 91 400 20 66.2 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.05 0.000501126 0.000456082 0.0105682 0.00992181 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 0.69 0.187639 0.16041 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.07 0.01 -1 -1 0.01 0.0401307 0.0361321 - EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.85 vpr 66.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67848 10 10 168 178 1 73 31 6 6 36 clb auto 26.7 MiB 0.24 396 511 91 400 20 66.3 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.05 0.00050814 0.000464386 0.0102811 0.00966555 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 0.71 0.196479 0.168384 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.07 0.01 -1 -1 0.01 0.0330747 0.0297042 - EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 5.19 vpr 66.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68216 10 10 168 178 1 162 111 14 14 196 clb auto 26.9 MiB 0.89 1456 5963 865 4880 218 66.6 MiB 0.06 0.00 3.05524 -37.9348 -3.05524 3.05524 0.65 0.000523477 0.000473123 0.0172523 0.0158836 -1 -1 -1 -1 26 2865 15 9.20055e+06 4.90435e+06 387483. 1976.95 1.88 0.188569 0.163851 18784 74779 -1 2696 13 472 1947 107713 24081 3.50167 3.50167 -42.0838 -3.50167 0 0 467681. 2386.13 0.17 0.07 0.07 -1 -1 0.17 0.0274362 0.0252919 - EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 1.60 vpr 66.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67712 10 10 168 178 1 75 33 7 7 49 clb auto 26.6 MiB 0.24 404 813 125 661 27 66.1 MiB 0.04 0.00 2.45517 -27.3027 -2.45517 2.45517 0.08 0.00050798 0.000465116 0.0193336 0.0182759 -1 -1 -1 -1 26 1116 28 1.07788e+06 700622 75813.7 1547.22 0.35 0.112548 0.0995004 3816 13734 -1 925 18 487 1699 71725 25249 2.97305 2.97305 -35.2593 -2.97305 0 0 91376.6 1864.83 0.02 0.09 0.01 -1 -1 0.02 0.036074 0.0329384 - EArch.xml styr.blif common_--target_ext_pin_util_0.0 4.47 vpr 66.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68092 10 10 168 178 1 163 124 14 14 196 clb auto 26.8 MiB 1.03 1516 7540 1142 6103 295 66.5 MiB 0.06 0.00 3.06133 -37.7953 -3.06133 3.06133 0.57 0.000550538 0.000486087 0.0169228 0.0153939 -1 -1 -1 -1 20 2911 18 9.20055e+06 5.60498e+06 354876. 1810.58 1.28 0.0956201 0.0845563 18004 60473 -1 2874 12 603 2265 131794 29163 3.74152 3.74152 -44.1586 -3.74152 0 0 387483. 1976.95 0.13 0.05 0.05 -1 -1 0.13 0.0197556 0.0180756 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.87 vpr 66.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67724 10 10 168 178 1 73 31 6 6 36 clb auto 26.5 MiB 0.19 396 511 91 400 20 66.1 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.05 0.00050848 0.000463468 0.0108023 0.0101532 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 0.76 0.210723 0.180638 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.07 0.01 -1 -1 0.01 0.0400523 0.0363482 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.86 vpr 66.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67892 10 10 168 178 1 73 31 6 6 36 clb auto 26.6 MiB 0.24 396 511 91 400 20 66.3 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.04 0.000515808 0.000471915 0.0113979 0.0107292 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 0.69 0.195893 0.168677 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.07 0.01 -1 -1 0.01 0.0384733 0.0348156 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 5.12 vpr 66.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68400 10 10 168 178 1 162 111 14 14 196 clb auto 27.1 MiB 0.91 1456 5963 865 4880 218 66.8 MiB 0.06 0.00 3.05524 -37.9348 -3.05524 3.05524 0.57 0.000858666 0.000789693 0.0217968 0.0201256 -1 -1 -1 -1 26 2865 15 9.20055e+06 4.90435e+06 387483. 1976.95 1.84 0.178818 0.155234 18784 74779 -1 2696 13 472 1947 107713 24081 3.50167 3.50167 -42.0838 -3.50167 0 0 467681. 2386.13 0.17 0.06 0.08 -1 -1 0.17 0.0255381 0.023411 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.90 vpr 66.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67816 10 10 168 178 1 73 31 6 6 36 clb auto 26.6 MiB 0.23 396 511 91 400 20 66.2 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.05 0.000710376 0.000647785 0.0115236 0.0108448 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 0.72 0.206379 0.177028 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.11 0.01 -1 -1 0.01 0.0399536 0.0360531 - EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.21 vpr 27.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28648 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.4 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.21 vpr 27.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28656 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.6 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.19 vpr 28.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28716 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.6 MiB 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.19 vpr 28.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28828 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.6 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_1 1.31 vpr 68.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70324 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.20 399 703 140 536 27 68.7 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000310541 0.000262563 0.00936798 0.00854482 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.46 0.175458 0.152388 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.01 -1 -1 0.00 0.0280432 0.0256776 + EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.18 vpr 68.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70172 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.19 399 703 140 536 27 68.5 MiB 0.01 0.00 2.34639 -26.9899 -2.34639 2.34639 0.02 0.000328824 0.000280405 0.00830952 0.00754823 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.31 0.10752 0.0932813 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0371511 0.0342602 + EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 4.10 vpr 69.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70728 10 10 168 178 1 162 111 14 14 196 clb auto 29.4 MiB 0.90 1467 5165 686 4267 212 69.1 MiB 0.05 0.00 2.95542 -36.8348 -2.95542 2.95542 0.39 0.000594399 0.00050939 0.0158932 0.0140866 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.49 0.204118 0.178235 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.04 0.10 0.10 -1 -1 0.04 0.0402804 0.0376719 + EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 1.27 vpr 68.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70312 10 10 168 178 1 75 33 7 7 49 clb auto 29.2 MiB 0.22 414 605 98 486 21 68.7 MiB 0.02 0.00 2.40687 -27.3475 -2.40687 2.40687 0.06 0.000598343 0.000517434 0.011833 0.0108149 -1 -1 -1 -1 26 1062 27 1.07788e+06 700622 75813.7 1547.22 0.28 0.112886 0.100348 3816 13734 -1 940 18 540 1691 67850 23781 2.86939 2.86939 -35.5441 -2.86939 0 0 91376.6 1864.83 0.00 0.05 0.02 -1 -1 0.00 0.0342617 0.0315172 + EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.32 vpr 68.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70636 10 10 168 178 1 163 124 14 14 196 clb auto 29.3 MiB 0.71 1526 7540 1144 6026 370 69.0 MiB 0.04 0.00 3.12689 -38.2571 -3.12689 3.12689 0.24 0.000341831 0.000287957 0.0139093 0.0123738 -1 -1 -1 -1 20 3129 15 9.20055e+06 5.60498e+06 295730. 1508.82 0.36 0.0484505 0.0438885 18004 60473 -1 3052 13 680 3211 188673 40435 3.88935 3.88935 -46.4141 -3.88935 0 0 387483. 1976.95 0.03 0.08 0.07 -1 -1 0.03 0.0262959 0.0240352 + EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.51 vpr 68.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70184 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.5 MiB 0.03 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000592996 0.000513744 0.0148871 0.0136124 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.60 0.233947 0.201424 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0337396 0.0309919 + EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.26 vpr 68.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69936 10 10 168 178 1 73 31 6 6 36 clb auto 28.8 MiB 0.14 399 703 140 536 27 68.3 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000607215 0.000528624 0.0138198 0.0125584 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.45 0.178959 0.157093 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.01 -1 -1 0.00 0.0299846 0.0274172 + EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 4.05 vpr 68.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70468 10 10 168 178 1 162 111 14 14 196 clb auto 29.3 MiB 0.89 1467 5165 686 4267 212 68.8 MiB 0.05 0.00 2.95542 -36.8348 -2.95542 2.95542 0.31 0.000662054 0.000579378 0.0167691 0.0149922 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.58 0.235946 0.204687 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.03 0.07 0.12 -1 -1 0.03 0.0296338 0.0273566 + EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.49 vpr 68.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69976 10 10 168 178 1 73 31 6 6 36 clb auto 28.8 MiB 0.21 399 703 140 536 27 68.3 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000326035 0.000277526 0.0147842 0.0134826 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.61 0.214908 0.181228 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.02 -1 -1 0.00 0.0279877 0.0256826 + EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.10 vpr 29.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30628 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.7 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.11 vpr 30.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31144 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.11 vpr 30.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31020 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.11 vpr 30.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30716 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt index af6269be78f..95f2081009b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 8.71 vpr 73.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 74812 229 197 2152 2349 1 1013 576 16 16 256 io auto 33.5 MiB 3.13 8848 180201 52690 111830 15681 73.1 MiB 1.31 0.03 2.99388 -664.24 -2.99388 2.99388 0.00 0.00538594 0.00461218 0.480806 0.428342 -1 -1 -1 -1 -1 11423 9 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.23 0.688229 0.621836 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 9.08 vpr 75.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 77084 229 197 2152 2349 1 1013 576 16 16 256 io auto 35.8 MiB 4.29 8858 177806 51921 111135 14750 75.3 MiB 1.45 0.02 2.93018 -671.396 -2.93018 2.93018 0.00 0.00692729 0.00619106 0.572476 0.497763 -1 -1 -1 -1 -1 11350 10 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.34 0.862195 0.757255 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt index 956417a33e9..a285dc5eca4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 5.18 vpr 65.63 MiB 0.10 9360 -1 -1 3 0.29 -1 -1 34572 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67208 99 130 363 493 1 251 298 12 12 144 clb auto 26.3 MiB 0.15 830 72933 24114 36385 12434 65.6 MiB 0.26 0.00 2.31523 -217.996 -2.31523 2.31523 0.32 0.000917378 0.000858642 0.0838167 0.0788673 -1 -1 -1 -1 38 1583 13 5.66058e+06 4.21279e+06 319130. 2216.18 2.38 0.45942 0.419671 12522 62564 -1 1389 8 493 651 37667 12430 2.73633 2.73633 -236.043 -2.73633 0 0 406292. 2821.48 0.13 0.04 0.07 -1 -1 0.13 0.0261213 0.0244905 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.34 vpr 67.74 MiB 0.06 9856 -1 -1 3 0.39 -1 -1 39776 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69364 99 130 363 493 1 251 298 12 12 144 clb auto 28.5 MiB 0.15 804 66963 21682 33533 11748 67.7 MiB 0.29 0.00 2.23767 -220.613 -2.23767 2.23767 0.27 0.00107588 0.000959454 0.0879605 0.0803385 -1 -1 -1 -1 38 1665 16 5.66058e+06 4.21279e+06 319130. 2216.18 0.81 0.341856 0.310926 12522 62564 -1 1367 8 564 725 39208 13509 2.60043 2.60043 -237.701 -2.60043 0 0 406292. 2821.48 0.03 0.05 0.14 -1 -1 0.03 0.0261531 0.0245164 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt index 3fa9e969200..ddf76e6dee9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.11 vpr 65.57 MiB 0.10 9356 -1 -1 3 0.35 -1 -1 34624 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67140 99 130 363 493 1 251 298 12 12 144 clb auto 26.2 MiB 0.16 850 68953 24096 34301 10556 65.6 MiB 0.21 0.00 2.17528 -135.263 -2.17528 2.17528 0.36 0.000607948 0.000558569 0.0540788 0.0494279 -1 -1 -1 -1 36 1722 23 5.66058e+06 4.21279e+06 305235. 2119.69 0.88 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.16 vpr 67.80 MiB 0.06 9984 -1 -1 3 0.37 -1 -1 39748 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69432 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.14 877 59998 22493 27317 10188 67.8 MiB 0.17 0.00 2.17528 -133.517 -2.17528 2.17528 0.25 0.000598743 0.00053199 0.0416228 0.0366674 -1 -1 -1 -1 40 1685 15 5.66058e+06 4.21279e+06 333335. 2314.82 1.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt index 13ad07bee3b..4503f0925f9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 6.73 vpr 65.30 MiB 0.11 9496 -1 -1 3 0.35 -1 -1 34624 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66864 99 130 363 493 1 252 298 12 12 144 clb auto 26.0 MiB 0.14 765 78903 26762 38665 13476 65.3 MiB 0.25 0.00 2.31285 0 0 2.31285 0.36 0.000595835 0.000546064 0.0568252 0.0524192 -1 -1 -1 -1 38 1556 15 5.66058e+06 4.21279e+06 319130. 2216.18 3.88 0.700323 0.59673 12522 62564 -1 1352 7 424 536 26689 9017 2.96222 2.96222 0 0 0 0 406292. 2821.48 0.13 0.03 0.07 -1 -1 0.13 0.0171393 0.0157816 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 3.64 vpr 67.62 MiB 0.06 9856 -1 -1 3 0.30 -1 -1 39896 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69248 99 130 363 493 1 252 298 12 12 144 clb auto 28.5 MiB 0.14 956 73928 27133 34341 12454 67.6 MiB 0.26 0.00 2.30557 0 0 2.30557 0.25 0.000962793 0.000867177 0.0597068 0.0524058 -1 -1 -1 -1 38 1840 8 5.66058e+06 4.21279e+06 319130. 2216.18 1.37 0.282428 0.244945 12522 62564 -1 1734 8 415 510 29213 8865 2.61298 2.61298 0 0 0 0 406292. 2821.48 0.02 0.03 0.09 -1 -1 0.02 0.0187719 0.0170722 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt index 26ddabd3b5a..0a5e59f0296 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.68 vpr 65.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66556 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.02 20 30 10 17 3 65.0 MiB 0.01 0.00 0.619658 -3.41326 -0.619658 0.545 0.01 3.9442e-05 2.8479e-05 0.000264801 0.000213415 -1 -1 -1 -1 20 15 1 107788 107788 10441.3 652.579 0.05 0.00220927 0.00202353 750 1675 -1 15 1 7 7 94 62 0.562699 0.545 -3.33969 -0.562699 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00165203 0.0015765 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.64 vpr 64.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66324 5 3 11 14 2 9 10 4 4 16 clb auto 26.0 MiB 0.02 20 30 10 17 3 64.8 MiB 0.01 0.00 0.619658 -3.41326 -0.619658 0.545 0.01 4.7331e-05 3.4794e-05 0.000313679 0.000255977 -1 -1 -1 -1 20 15 1 107788 107788 10441.3 652.579 0.02 0.00210853 0.00193266 750 1675 -1 15 1 7 7 94 62 0.562699 0.545 -3.33969 -0.562699 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.0016735 0.00159778 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.70 vpr 64.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66360 5 3 11 14 2 9 10 4 4 16 clb auto 26.0 MiB 0.03 20 30 10 17 3 64.8 MiB 0.04 0.00 0.619658 -3.41326 -0.619658 0.545 0.01 5.5384e-05 4.0883e-05 0.000339161 0.000274106 -1 -1 -1 -1 20 15 1 107788 107788 10441.3 652.579 0.02 0.00305328 0.00284599 750 1675 -1 15 1 7 7 94 62 0.562699 0.545 -3.33969 -0.562699 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00161855 0.0015492 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.62 vpr 67.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68616 5 3 11 14 2 9 10 4 4 16 clb auto 28.6 MiB 0.01 21 30 9 19 2 67.0 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.8501e-05 3.4711e-05 0.00027851 0.000219913 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00215999 0.00198392 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.00181366 0.00173531 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.62 vpr 67.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68636 5 3 11 14 2 9 10 4 4 16 clb auto 28.5 MiB 0.01 21 30 9 19 2 67.0 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 5.1152e-05 3.666e-05 0.000287379 0.000227035 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.03 0.0023614 0.00216487 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.0022135 0.00167838 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.55 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68936 5 3 11 14 2 9 10 4 4 16 clb auto 28.9 MiB 0.01 21 30 9 19 2 67.3 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 5.7208e-05 4.2383e-05 0.000322556 0.000257546 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.02 0.00215648 0.00197387 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.00181267 0.00173458 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt index d75c4e0f2bb..9d457582f18 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.86 vpr 66.88 MiB 0.12 10144 -1 -1 5 0.18 -1 -1 33460 -1 -1 14 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68484 11 30 313 321 2 115 55 7 7 49 clb auto 27.2 MiB 0.36 466 2759 556 2108 95 66.9 MiB 0.06 0.00 2.67362 -172.647 -2.67362 2.30794 0.00 0.000854492 0.000777061 0.032919 0.0303032 -1 -1 -1 -1 -1 574 7 1.07788e+06 754516 219490. 4479.39 0.04 0.063998 0.0591785 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.68 vpr 69.25 MiB 0.08 10496 -1 -1 5 0.17 -1 -1 36364 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70908 11 30 313 321 2 115 55 7 7 49 clb auto 29.8 MiB 0.39 448 1927 352 1502 73 69.2 MiB 0.04 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.000798161 0.000674358 0.0213182 0.0191108 -1 -1 -1 -1 -1 595 8 1.07788e+06 754516 219490. 4479.39 0.04 0.060298 0.0550487 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt index 2c41099abe5..070113b9371 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.56 vpr 64.55 MiB 0.11 10036 -1 -1 4 0.23 -1 -1 33332 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66096 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 421 2049 269 1715 65 64.5 MiB 0.05 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 0.000901868 0.000816005 0.0182749 0.0165852 -1 -1 -1 -1 -1 424 16 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0493513 0.0440772 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.56 vpr 64.68 MiB 0.09 9896 -1 -1 4 0.22 -1 -1 33244 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66236 11 30 262 292 2 99 60 7 7 49 clb auto 24.9 MiB 0.09 421 2049 269 1715 65 64.7 MiB 0.03 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 0.000505662 0.000447982 0.0141131 0.0127631 -1 -1 -1 -1 -1 424 16 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0443633 0.0397038 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.55 vpr 64.02 MiB 0.12 10036 -1 -1 4 0.21 -1 -1 33388 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65552 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 421 2049 269 1715 65 64.0 MiB 0.03 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 8.432e-06 2.592e-06 0.00561579 0.00470719 -1 -1 -1 -1 -1 424 16 1.07788e+06 1.02399e+06 207176. 4228.08 0.05 0.0266554 0.0212939 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.55 vpr 63.92 MiB 0.12 9868 -1 -1 4 0.21 -1 -1 33312 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65456 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 421 2049 269 1715 65 63.9 MiB 0.03 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 0.000527965 0.000121671 0.00657296 0.00525257 -1 -1 -1 -1 -1 424 16 1.07788e+06 1.02399e+06 207176. 4228.08 0.05 0.0298469 0.0235615 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.31 vpr 66.76 MiB 0.06 10368 -1 -1 4 0.22 -1 -1 36924 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68364 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 425 2283 406 1804 73 66.8 MiB 0.04 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000550429 0.00044745 0.0205892 0.0175295 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0715823 0.0554655 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.35 vpr 67.11 MiB 0.08 10368 -1 -1 4 0.22 -1 -1 36664 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68720 11 30 262 292 2 99 60 7 7 49 clb auto 27.5 MiB 0.09 425 2283 406 1804 73 67.1 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000592669 0.000483133 0.0176652 0.0153201 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.08 0.0695138 0.0618702 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.40 vpr 66.21 MiB 0.07 10368 -1 -1 4 0.18 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67804 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.09 425 2283 406 1804 73 66.2 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000259913 0.000168736 0.00804711 0.00632437 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.05 0.0326926 0.0257255 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.40 vpr 66.24 MiB 0.07 10368 -1 -1 4 0.22 -1 -1 36412 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67828 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.09 425 2283 406 1804 73 66.2 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000820125 0.000270462 0.0105947 0.00836537 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0358221 0.028376 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt index 676a758e26d..ec4372e5ea5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 69.07 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1213468 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1063.1 MiB 14.23 70903 253216 51547 191577 10092 1176.3 MiB 10.33 0.14 4.99319 -5223.26 -3.99319 2.64446 0.01 0.0393935 0.0325965 2.91026 2.41968 83183 6.68835 19827 1.59419 25954 36248 10076288 1815088 0 0 2.05929e+07 18207.7 15 331560 3499109 -1 5.28806 2.7363 -5589.94 -4.28806 0 0 6.16 -1 -1 1176.3 MiB 4.02 4.55065 3.84457 1176.3 MiB -1 12.94 + stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 76.86 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1215732 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1063.5 MiB 14.49 75097 245792 47628 188491 9673 1158.4 MiB 19.32 0.31 4.99421 -5497.03 -3.99421 2.87584 0.01 0.0645942 0.0566793 4.57717 3.66743 87123 7.00515 21186 1.70347 25964 36365 9630576 1720385 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.30154 2.77187 -5700.98 -4.30154 0 0 8.99 -1 -1 1158.4 MiB 6.77 7.11559 5.86421 1158.4 MiB -1 3.90 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt index f9dc973d7ee..9097fbde85d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 16.79 vpr 67.83 MiB 0.08 9652 -1 -1 6 0.16 -1 -1 34060 -1 -1 15 66 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69456 66 96 1000 687 1 578 192 18 18 324 mult_27 auto 28.6 MiB 1.69 5343 48856 15321 28109 5426 67.8 MiB 0.58 0.01 16.5319 -985.557 -16.5319 16.5319 1.33 0.00284838 0.00269661 0.271323 0.256526 -1 -1 -1 -1 56 12644 31 6.4517e+06 1.13409e+06 1.55150e+06 4788.57 8.30 0.994052 0.922886 50684 323660 -1 11612 24 4774 11145 2601588 732828 16.8532 16.8532 -1120.15 -16.8532 0 0 1.95585e+06 6036.58 0.72 0.84 0.31 -1 -1 0.72 0.163283 0.153391 133 202 146 33 66 33 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 18.00 vpr 70.38 MiB 0.05 10112 -1 -1 6 0.25 -1 -1 38052 -1 -1 15 66 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72072 66 96 1000 687 1 578 192 18 18 324 mult_27 auto 31.1 MiB 2.15 5241 46091 14804 26339 4948 70.4 MiB 0.71 0.01 16.7702 -967.772 -16.7702 16.7702 0.75 0.00350611 0.00326694 0.374139 0.351063 -1 -1 -1 -1 54 12671 42 6.4517e+06 1.13409e+06 1.49609e+06 4617.55 10.37 1.47511 1.37701 50360 316156 -1 11227 19 3612 7762 1892477 579383 16.9221 16.9221 -1089.8 -16.9221 0 0 1.91711e+06 5917.01 0.13 0.79 0.45 -1 -1 0.13 0.185679 0.177041 133 202 146 33 66 33 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt index bb1d1e6ccea..9b26c986ccf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.67 vpr 62.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64420 6 8 39 47 1 20 17 5 5 25 clb auto 24.5 MiB 0.03 69 227 71 153 3 62.9 MiB 0.01 0.00 1.42251 -15.9524 -1.42251 1.42251 0.00 0.000117366 0.000105443 0.00207021 0.0019072 -1 -1 -1 -1 86 4.52632 45 2.36842 140 253 6063 2435 323364 161682 20103.2 804.128 19 1140 2762 -1 1.32969 1.32969 -16.56 -1.32969 0 0 0.00 -1 -1 62.9 MiB 0.02 0.00917762 0.00816725 62.9 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.65 vpr 62.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64384 6 8 39 47 1 20 17 5 5 25 clb auto 24.5 MiB 0.03 69 227 71 153 3 62.9 MiB 0.01 0.00 1.42251 -15.9524 -1.42251 1.42251 0.00 0.000188315 0.000170732 0.00297437 0.002743 -1 -1 -1 -1 86 4.52632 45 2.36842 140 253 6063 2435 323364 161682 20103.2 804.128 19 1140 2762 -1 1.32969 1.32969 -16.56 -1.32969 0 0 0.00 -1 -1 62.9 MiB 0.02 0.0122453 0.0107752 62.9 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.36 vpr 63.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64592 6 8 39 47 1 20 17 5 5 25 clb auto 24.7 MiB 0.03 69 227 71 153 3 63.1 MiB 0.01 0.00 1.42347 -15.9604 -1.42347 1.42347 0.00 0.000131128 0.000118797 0.00230482 0.00213538 -1 -1 -1 -1 -1 -1 -1 -1 723 1098 45498 29013 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 63.1 MiB 0.05 -1 -1 63.1 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.36 vpr 62.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64336 6 8 39 47 1 20 17 5 5 25 clb auto 24.4 MiB 0.05 69 227 71 153 3 62.8 MiB 0.01 0.00 1.42347 -15.9604 -1.42347 1.42347 0.00 0.000130321 0.00011848 0.00234416 0.00216136 -1 -1 -1 -1 142 7.47368 68 3.57895 723 1098 45498 29013 323364 161682 9037.03 361.481 -1 996 1634 -1 1.87665 1.87665 -21.7004 -1.87665 0 0 0.00 -1 -1 62.8 MiB 0.05 -1 -1 62.8 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.53 vpr 65.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66664 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.03 88 59 31 28 0 65.1 MiB 0.01 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.00022667 0.0001997 0.00145978 0.00134015 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.01 -1 -1 65.1 MiB 0.01 0.0151269 0.0141345 65.1 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.49 vpr 65.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66748 6 8 39 47 1 20 17 5 5 25 clb auto 26.8 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000166651 0.000146123 0.00118945 0.00110009 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.2 MiB 0.01 0.0110046 0.0100571 65.2 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.25 vpr 65.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66768 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000189994 0.000167385 0.00110293 0.00101544 -1 -1 -1 -1 -1 -1 -1 -1 654 1027 31303 15229 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 65.2 MiB 0.03 -1 -1 65.2 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.27 vpr 65.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66748 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000187343 0.000161123 0.00133988 0.00123837 -1 -1 -1 -1 142 7.47368 66 3.47368 654 1027 31303 15229 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9824 -1.84852 0 0 0.00 -1 -1 65.2 MiB 0.04 -1 -1 65.2 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt index 949cccb520a..a8c8aed1d54 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.82 vpr 58.30 MiB 0.12 9420 -1 -1 6 0.20 -1 -1 33332 -1 -1 69 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59700 11 30 336 366 2 175 110 11 11 121 clb auto 19.3 MiB 0.08 1069 7737 1075 6148 514 58.3 MiB 0.07 0.00 3.58466 -257.927 -3.58466 3.35525 0.00 0.000795143 0.000713058 0.0296855 0.0265178 -1 -1 -1 -1 1020 5.96491 1020 5.96491 830 2510 115386 26241 180575 153823 597941. 4941.66 12 20106 83797 -1 3.41136 3.2074 -256.892 -3.41136 -0.21991 -0.0734 0.14 -1 -1 58.3 MiB 0.12 0.0657665 0.0592709 58.3 MiB -1 0.11 - k6_frac_N10_40nm.xml stereovision3.v common 2.09 vpr 59.37 MiB 0.15 9312 -1 -1 4 0.21 -1 -1 33464 -1 -1 13 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60796 11 30 262 292 2 110 54 6 6 36 clb auto 20.2 MiB 0.14 411 1380 237 1087 56 59.4 MiB 0.03 0.00 2.57043 -171.117 -2.57043 2.32238 0.00 0.000673202 0.000603541 0.0138837 0.0127263 -1 -1 -1 -1 489 4.61321 218 2.05660 216 331 9092 3075 862304 700622 161034. 4473.17 7 3844 24048 -1 2.49787 2.27724 -178.279 -2.49787 0 0 0.03 -1 -1 59.4 MiB 0.04 0.0384913 0.0354677 59.4 MiB -1 0.02 + k4_N4_90nm.xml stereovision3.v common 2.42 vpr 61.41 MiB 0.07 9984 -1 -1 6 0.21 -1 -1 36540 -1 -1 69 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62880 11 30 336 366 2 175 110 11 11 121 clb auto 21.7 MiB 0.07 1099 5370 731 4291 348 61.4 MiB 0.07 0.00 3.52668 -265.051 -3.52668 3.51868 0.00 0.000895008 0.000764708 0.0287001 0.0253164 -1 -1 -1 -1 1048 6.12865 1048 6.12865 944 2940 139156 30294 180575 153823 597941. 4941.66 16 20106 83797 -1 3.39028 3.32725 -266.23 -3.39028 -0.21991 -0.0734 0.19 -1 -1 61.4 MiB 0.11 0.0797492 0.0714232 61.4 MiB -1 0.02 + k6_frac_N10_40nm.xml stereovision3.v common 1.89 vpr 62.21 MiB 0.06 9984 -1 -1 4 0.20 -1 -1 36668 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63704 11 30 262 292 2 110 54 6 6 36 clb auto 22.6 MiB 0.15 403 1584 300 1231 53 62.2 MiB 0.04 0.00 2.57043 -171.01 -2.57043 2.32238 0.00 0.000808513 0.00071129 0.0212101 0.0190689 -1 -1 -1 -1 496 4.67925 221 2.08491 205 325 10915 3976 862304 700622 161034. 4473.17 9 3844 24048 -1 2.61311 2.27483 -177.098 -2.61311 0 0 0.05 -1 -1 62.2 MiB 0.04 0.0510796 0.0464992 62.2 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt index 43fe9e64de6..c745d2940f2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.46 vpr 58.19 MiB 0.15 9392 -1 -1 6 0.20 -1 -1 33308 -1 -1 69 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59584 11 30 336 366 2 175 110 11 11 121 clb auto 19.2 MiB 0.06 1069 7737 1075 6148 514 58.2 MiB 0.11 0.00 3.58466 -257.927 -3.58466 3.35525 0.00 0.00113995 0.0010258 0.0368023 0.0330354 -1 -1 -1 -1 1020 5.96491 1020 5.96491 830 2510 115386 26241 180575 153823 597941. 4941.66 12 20106 83797 -1 3.41136 3.2074 -256.892 -3.41136 -0.21991 -0.0734 0.11 -1 -1 58.2 MiB 0.08 0.070273 0.063129 58.2 MiB -1 0.09 - k6_frac_N10_40nm.xml stereovision3.v common 2.05 vpr 59.43 MiB 0.14 9392 -1 -1 4 0.20 -1 -1 33336 -1 -1 13 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60860 11 30 262 292 2 110 54 6 6 36 clb auto 20.2 MiB 0.14 411 1380 237 1087 56 59.4 MiB 0.04 0.00 2.57043 -171.117 -2.57043 2.32238 0.00 0.000753376 0.000667515 0.0140933 0.0129404 -1 -1 -1 -1 489 4.61321 218 2.05660 216 331 9092 3075 862304 700622 161034. 4473.17 7 3844 24048 -1 2.49787 2.27724 -178.279 -2.49787 0 0 0.03 -1 -1 59.4 MiB 0.04 0.0397773 0.0366976 59.4 MiB -1 0.02 + k4_N4_90nm.xml stereovision3.v common 2.36 vpr 61.16 MiB 0.06 9984 -1 -1 6 0.24 -1 -1 36564 -1 -1 69 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62624 11 30 336 366 2 175 110 11 11 121 clb auto 21.6 MiB 0.08 1099 5370 731 4291 348 61.2 MiB 0.08 0.00 3.52668 -265.051 -3.52668 3.51868 0.00 0.00109238 0.000939106 0.0296397 0.0256861 -1 -1 -1 -1 1048 6.12865 1048 6.12865 944 2940 139156 30294 180575 153823 597941. 4941.66 16 20106 83797 -1 3.39028 3.32725 -266.23 -3.39028 -0.21991 -0.0734 0.18 -1 -1 61.2 MiB 0.09 0.0740596 0.0653877 61.2 MiB -1 0.03 + k6_frac_N10_40nm.xml stereovision3.v common 1.71 vpr 62.40 MiB 0.03 10112 -1 -1 4 0.22 -1 -1 36668 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63900 11 30 262 292 2 110 54 6 6 36 clb auto 22.9 MiB 0.13 403 1584 300 1231 53 62.4 MiB 0.04 0.00 2.57043 -171.01 -2.57043 2.32238 0.00 0.000733682 0.000641677 0.0178767 0.0155436 -1 -1 -1 -1 496 4.67925 221 2.08491 205 325 10915 3976 862304 700622 161034. 4473.17 9 3844 24048 -1 2.61311 2.27483 -177.098 -2.61311 0 0 0.04 -1 -1 62.4 MiB 0.04 0.0527381 0.04796 62.4 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt index 369954619cf..8249d51c4a6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml styr.blif common 33.96 vpr 976.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1000220 10 10 168 178 1 68 30 11 8 88 io auto 953.8 MiB 0.62 354 536 67 434 35 976.8 MiB 0.06 0.00 6.57169 -72.0462 -6.57169 6.57169 0.00 0.000450859 0.000408422 0.0103745 0.00973574 -1 -1 -1 -1 586 8.74627 178 2.65672 259 971 58705 26468 0 0 194014. 2204.70 13 11730 32605 -1 6.82307 6.82307 -73.1617 -6.82307 0 0 0.08 -1 -1 976.8 MiB 0.07 0.0397393 0.0369452 976.8 MiB -1 0.04 + stratixiv_arch.timing.xml styr.blif common 34.23 vpr 978.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001816 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.58 371 490 69 397 24 978.3 MiB 0.06 0.00 6.66046 -72.2933 -6.66046 6.66046 0.00 0.000593468 0.00051514 0.0111956 0.0102241 -1 -1 -1 -1 549 8.19403 169 2.52239 264 964 62268 28521 0 0 194014. 2204.70 13 11730 32605 -1 6.70864 6.70864 -73.3171 -6.70864 0 0 0.08 -1 -1 978.3 MiB 0.07 0.0418866 0.0386921 978.3 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt index f20ab703070..5005a12aaca 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt @@ -12,12 +12,14 @@ archs_dir=arch/timing # Add circuits to list to sweep -include_list_add=display_control.sv -include_list_add=timer.sv -include_list_add=debounce.sv +#include_list_add=display_control.sv +#include_list_add=timer.sv +#include_list_add=debounce.sv # Add circuits to list to sweep -circuit_list_add=button_controller.sv +#circuit_list_add=button_controller.sv + +circuit_list_add=flattened_button_controller.sv # Add architectures to list to sweep diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt index 6c7dd369b44..c59221ce1d4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt @@ -12,11 +12,12 @@ archs_dir=arch/timing # Add circuits to list to sweep -include_list_add=PWM.v +#include_list_add=PWM.v # Add circuits to list to sweep -circuit_list_add=pulse_led.v +#circuit_list_add=pulse_led.v +circuit_list_add=flattened_pulse_width_led.sv # Add architectures to list to sweep arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt index 6b753bb4aa6..c2c180dab1d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt @@ -12,13 +12,13 @@ archs_dir=arch/timing # Add circuits to list to sweep -include_list_add=timer.sv -include_list_add=display_control.sv -include_list_add=time_counter.sv -include_list_add=modify_count.sv +#include_list_add=timer.sv +#include_list_add=display_control.sv +#include_list_add=time_counter.sv +#include_list_add=modify_count.sv # Add circuits to list to sweep -circuit_list_add=clock.sv +circuit_list_add=flattened_timer.sv # Add architectures to list to sweep diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt index 27a696e2c05..509f77a6434 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt @@ -1,3 +1,3 @@ regression_tests/vtr_reg_system_verilog/f4pga_button_controller/ regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/ -regression_tests/vtr_reg_system_verilog/f4pga_timer/ \ No newline at end of file +regression_tests/vtr_reg_system_verilog/f4pga_timer/ diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small/config/golden_results.txt index dc27ff97318..cc1a9e173eb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 235.14 - - -1 -1 -1 -1 3 6.08 -1 -1 -1 -1 -1 68 99 1 0 success v8.0.0-6991-g9a34a83d8-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T19:57:36 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing -1 99 130 343 473 1 217 298 12 12 144 clb auto 327.6 MiB 19.26 527 387.6 MiB 18.62 0.28 1.48813 -109.046 -1.48813 1.48813 14.66 0.0431227 0.0369718 2.52447 2.22009 44 1192 28 5.66058e+06 4.21279e+06 360780. 2505.42 69.79 14.6655 13.3453 1046 10 388 639 24800 7975 1.92172 1.92172 -132.535 -1.92172 0 0 470760. 3269.17 4.55 2.00 0.855374 0.779811 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 171.10 - - -1 -1 -1 -1 4 7.64 -1 -1 -1 -1 -1 15 11 0 0 success v8.0.0-6991-g9a34a83d8-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T19:57:36 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing -1 11 2 303 283 2 80 28 7 7 49 clb auto 325.4 MiB 14.61 267 384.7 MiB 2.15 0.04 1.86151 -149.067 -1.86151 1.77041 3.18 0.026727 0.0244673 0.629531 0.531796 20 457 19 1.07788e+06 808410 52439.0 1070.18 11.18 3.19863 2.80245 388 18 286 492 8676 3081 2.28191 2.05156 -171.957 -2.28191 0 0 68696.0 1401.96 0.49 2.13 1.0398 0.920285 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 239.31 - - -1 -1 -1 -1 3 17.61 -1 -1 -1 -1 -1 68 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing -1 99 130 344 474 1 227 298 12 12 144 clb auto 322.7 MiB 20.06 749 71938 22933 33485 15520 381.0 MiB 16.97 0.33 1.86413 -118.59 -1.86413 1.86413 11.65 0.0732576 0.068454 5.52499 5.15173 -1 -1 -1 -1 42 1520 10 5.66058e+06 4.21279e+06 345696. 2400.67 36.36 14.4547 13.0534 13090 66981 -1 1349 11 399 648 28156 8528 2.01841 2.01841 -138.411 -2.01841 0 0 434636. 3018.30 1.10 3.62 6.08 -1 -1 1.10 2.02601 1.79237 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 253.64 - - -1 -1 -1 -1 4 20.25 -1 -1 -1 -1 -1 15 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing -1 11 2 303 283 2 78 28 7 7 49 clb auto 317.6 MiB 15.14 262 1078 238 765 75 376.4 MiB 3.35 0.07 2.0391 -163.079 -2.0391 1.90116 2.96 0.058501 0.053558 1.68082 1.53185 -1 -1 -1 -1 28 333 12 1.07788e+06 808410 72669.7 1483.05 25.62 14.1524 12.0861 3564 12808 -1 288 8 200 345 4799 1871 2.11979 1.94261 -165.174 -2.11979 0 0 87745.0 1790.71 0.23 2.68 1.60 -1 -1 0.23 1.45763 1.25544 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small_odin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small_odin/config/golden_results.txt index 2ad6115ccf5..f9583dc46a1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small_odin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small_odin/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 216.22 - - 5.36 -1 -1 -1 3 13.41 -1 -1 -1 -1 -1 65 99 1 0 success v8.0.0-6991-g9a34a83d8-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T19:57:36 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing -1 99 130 363 493 1 251 295 12 12 144 clb auto 318.1 MiB 14.93 645 379.8 MiB 18.45 0.40 2.20394 -203.734 -2.20394 2.20394 15.22 0.0227102 0.0199136 2.38954 2.11394 44 1525 10 5.66058e+06 4.05111e+06 360780. 2505.42 75.30 14.1754 12.8861 1443 8 574 715 52691 16759 2.7395 2.7395 -240.01 -2.7395 0 0 470760. 3269.17 4.60 2.25 0.801898 0.732428 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 142.75 - - 5.84 -1 -1 -1 5 8.14 -1 -1 -1 -1 -1 14 11 0 0 success v8.0.0-6991-g9a34a83d8-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T19:57:36 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing -1 11 30 313 321 2 118 55 7 7 49 clb auto 323.5 MiB 19.41 406 383.2 MiB 3.65 0.05 2.27568 -159.51 -2.27568 2.03262 3.30 0.018455 0.0155492 1.00517 0.862416 30 877 23 1.07788e+06 754516 77114.5 1573.76 27.47 8.76219 7.74656 676 13 411 718 20274 7142 2.45236 2.25315 -180.16 -2.45236 0 0 95414.1 1947.23 0.85 2.72 1.20489 1.04235 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 214.19 - - 6.74 -1 -1 -1 3 31.59 -1 -1 -1 -1 -1 68 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing -1 99 130 363 493 1 251 298 12 12 144 clb auto 315.5 MiB 16.63 825 66963 24629 31658 10676 375.0 MiB 16.45 0.29 2.18081 -216.806 -2.18081 2.18081 11.68 0.0738834 0.069041 5.19912 4.84873 -1 -1 -1 -1 42 1542 18 5.66058e+06 4.21279e+06 345696. 2400.67 39.10 15.39 13.8531 13090 66981 -1 1416 8 543 745 35361 11414 2.49575 2.49575 -234.092 -2.49575 0 0 434636. 3018.30 1.10 3.44 6.11 -1 -1 1.10 1.69917 1.5038 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 185.29 - - 7.24 -1 -1 -1 5 21.35 -1 -1 -1 -1 -1 14 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing -1 11 30 313 321 2 115 55 7 7 49 clb auto 318.7 MiB 19.99 456 2239 413 1740 86 377.4 MiB 3.57 0.10 2.65898 -171.948 -2.65898 2.30209 2.96 0.064002 0.0582579 1.57937 1.43364 -1 -1 -1 -1 30 934 29 1.07788e+06 754516 77114.5 1573.76 17.77 10.2264 8.76037 3660 13876 -1 783 19 469 889 29198 10184 2.65817 2.36697 -188.291 -2.65817 0 0 95414.1 1947.23 0.24 4.44 1.68 -1 -1 0.24 2.66573 2.27986 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_large/config/config.txt similarity index 92% rename from vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_large/config/config.txt index 95b8603ec5b..ba529fa1152 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_large/config/config.txt @@ -14,6 +14,7 @@ includes_dir=benchmarks/verilog/koios # Add circuits to list to sweep circuit_list_add=bwave_like.float.large.v +circuit_list_add=bwave_like.fixed.large.v # Add architectures to list to sweep arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml @@ -35,4 +36,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt #Script parameters -script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 --target_utilization 0.28 \ No newline at end of file +script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 400 --target_utilization 0.12 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_large/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_large/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/config.txt index e4261a2b31f..0f11b550df2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/config.txt @@ -21,7 +21,6 @@ circuit_list_add=lstm.v circuit_list_add=gemm_layer.v circuit_list_add=tpu_like.large.os.v circuit_list_add=tpu_like.large.ws.v -circuit_list_add=tdarknet_like.small.v circuit_list_add=tdarknet_like.large.v circuit_list_add=dla_like.medium.v